Evaluation Board For PulSAR 48 Lead ADCs
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB
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FEATURES
Converter and Evaluation Development (EVAL-CED1Z)
compatibility
Versatile analog signal conditioning circuitry
On-board reference, clock oscillator and buffers
Buffered 14, 16 (or 18) bit parallel outputs
Buffered serial port interface
Ideal for DSP and data acquisition card interfaces
Analog and digital prototyping area
PC software for control and data analysis
GENERAL DESCRIPTION
The EVAL-AD76XXEDZ is an evaluation board for the 48 lead
AD761X, AD762X, AD763X, AD764X, AD765X, AD766X,
AD767X and AD795X 14-bit, 16-bit and 18- bit PulSAR®
analog to digital converter (ADC) family. These low power,
successive approximation register (SAR) architecture ADCs (see
ordering guide for product list ) offer very high performance
with 100kSPS to 3MSPS throughput rate range with a flexible
parallel or serial interface. The evaluation board is designed to
demonstrate the ADC's performance and to provide an easy to
understand interface for a variety of system applications. A full
description of the ADCs for this board are available at
www.Analog.com/PulSAR and should be consulted when
utilizing this evaluation board.
The evaluation board is ideal for use with Analog Devices USB
based Converter and Evaluation Development EVAL-CED1Z,
(CED) or as a stand-alone system. These boards are also
compatible for use with the EVAL-CONTROL BRDxZ capture
board and software for using this board is available on the
website. Since many newer PC’s do not offer a parallel port
along with overcomplicated BIOS port settings, the CED board
is strongly recommended.
The design offers the flexibility of applying external control
signals and is capable of generating conversion results on
parallel 14-bit, 16-bit or 18-bit wide buffered outputs. On-board
components include a high precision band gap reference,
(AD780, ADR431, or ADR435), reference buffers, a signal
conditioning circuit with two op-amps and digital logic.
The EVAL-AD76XXEDZ interfaces to the CED capture board
with a 96-pin DIN connector. A 40-pin IDC connector is used
for parallel output, and test points are provided for the serial
port. SMB connectors are provided for the low noise analog
signal source, and for an externally generated CNVST (convert
start input.
Figure 1. Evaluation Board
Analog Inputs
Supplies
External CNVST
PulSAR ADC
Reference/Buffer 96-Pin CED/ECB
Interface
EVAL-AD76XXCB Preliminary Technical Data
Rev. PrB | Page 2 of 23
TABLE OF CONTENTS
FEATURES ........................................................................................ 1
GENERAL DESCRIPTION ............................................................ 1
Overview........................................................................................ 3
Conversion Control/Master Clock............................................. 3
Analog Inputs................................................................................ 3
Power Supplies and Grounding .................................................. 3
Using the Eval-AD762X/AD765X/AD766X/ AD767XCBZ as
Stand-Alone................................................................................... 3
Schematics/PCB Layout............................................................... 4
Supplying Power for Stand-Alone use ....................................... 4
Evaluation Board Setting for Bipolar ADC Input
Configurations...............................................................................4
Hardware Setup .............................................................................4
Software Installation .....................................................................5
Running the Evaluation Software ..............................................6
Setup Screen...................................................................................6
DC Testing - Histogram ...............................................................6
AC Testing......................................................................................6
Evaluation Board Schematics and Artwork............................ 16
Ordering Guide .......................................................................... 22
LIST OF FIGURES
Figure 1. Evaluation Board .............................................................. 1
Figure 2. Setup Screen .................................................................... 10
Figure 3. Context Help ................................................................... 11
Figure 4. Histogram Screen ........................................................... 12
Figure 5. Summary.......................................................................... 13
Figure 6. FFT Spectrum ................................................................. 14
Figure 7. Oscilloscope .................................................................... 15
Figure 8. Schematic, Analog .......................................................... 16
Figure 9. Schematic, Digital........................................................... 17
Figure 10. Schematic, Power.......................................................... 18
Figure 11. Top Side Silk-Screen .................................................... 19
Figure 12. Top Layer....................................................................... 19
Figure 13. Ground Layer................................................................ 20
Figure 14. Shield Layer................................................................... 20
Figure 15. Bottom Side Layer........................................................ 21
Figure 16. Bottom Side Silk-Screen.............................................. 21
LIST OF TABLES
Table 1. CNVST Generation, Analog Input Range....................... 7
Table 2. Jumper Description............................................................ 8
Table 3. S16 - Configuration Select Switch Description.............. 8
Table 4. S35 - Configuration Select Switch Description.............. 8
Table 5.Test Points .............................................................................9
Table 6. Bill of Materials for the Connectors .............................. 22
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 3 of 23
OVERVIEW
Figure 1 shows the EVAL-AD76XXEDZ evaluation board.
When used in stand-alone mode or in conjunction with the
EVAL-CED1Z, the gate array, U10, provides the necessary
control signals for conversion and buffers the ADC data. The
evaluation board is a flexible design that enables the user to
choose among many different board configurations, analog
signal conditioning, reference, and different modes of
conversion data.
CONVERSION CONTROL/MASTER CLOCK
Conversion start (CNVST) controls the sample rate of the ADC
and is the only input needed for conversion; all SAR timing is
generated internally. CNVST is generated either by the gate
array or externally via J3 (SMB) and setting JP22 in the external
(EXT) position. The evaluation board is factory configured for
the CNVST range shown in Table 1. Externally generated
CNVST should have very low jitter and sharp edges for the
maximum dynamic performance of the part. Since CNVST
jitter usually results in poor SNR performance, it is
recommended to use the on-board CNVST generation
whenever possible.
The master clock (MCLK) source for the gate array is generated
from the CED capture board or from U12, the 40MHz local
oscillator selectable when using the accompanying software.
The range for CNVST in
Table 1is a ratio generated from this master clock. In stand-
alone mode, other clock frequencies can be used to change the
gate array generated CNVST by this ratio. However, other
timings will be affected – namely the slave serial clock (SCLK)
interface. In serial slave mode, SCLK = MCLK.
While the ADC is converting, activity on the BUSY pin turns on
the LED, D2. Additionally, the BUSY signal can be monitored
test point TP1. Buffered conversion data (BD) is available at
U10 on the output bus BD[0:15] on the 40-pin IDC connector
P2, and on the 96-pin connector P3. When operating with the
CED, data is transferred using a 16 bit bus and corresponding
word and byte modes selectable with the software. For the 18 bit
converters two consecutive 16 bit words are read, however, the
ADC data is still read into the gate array as 18 bits. Additionally,
BD is updated on the falling edge of BBUSY on P3-C17, and on
the rising edge of DBUSY on P2-33. When either parallel or
serial reading mode of the ADC is used, data is available on this
parallel bus.
When using Serial Mode, serial data is available at T3, T4, T5,
and T6 (SDOUT, SCLK, SYNC and RDERROR) and buffered
serial data is output on TP17, TP18, and TP19 (SCLK, SYNC,
and SDOUT). When using Slave Serial Mode, the external serial
clock SCLK applied to the ADC is the MCLK, U12, frequency
(40MHz). Refer to the device specific datasheet for full details
of the interface modes.
ANALOG INPUTS
The analog inputs amplifier circuitry (U6, U7 and discretes)
allows configuration changes such as positive or negative gain,
input range scaling, filtering, addition of a DC component, use
of different op-amp and supplies depending on the ADC. The
analog input amplifiers are set as unity gain buffers at the
factory. The supplies are selectable with solder pads and are set
for the ±12V range.
Table 1 shows the analog input range for the available
evaluation boards.
The default configuration for the single ended (SE) unipolar
ADCs sets U6 at mid-scale from the voltage divider (VCM *
R6/(R6+R7)) and U7 at mid-scale from the voltage divider (VCM
* R29(R29+R60)) for the differential unipolar ADCs.
For the bipolar devices (AD7663, AD665, AD7671), the buffer
output is centered at 0V (mid-scale) as these boards are
configured for the +/-5V input range. Note the input impedance
is 1k ohm (R6, R29 =1k ohm to GND). To use another input
range, the solder pads S[7:1] need to be reconfigured.
These input configurations allows a transition noise test
(histogram) without any other equipment. In some applications,
it is desired to use a bipolar or wider analog input range, for
instance, ± 10V, ± 5V, ± 2.5V, or 0 to -5V. For ADCs which do
not use these input ranges directly, simple modifications of the
input driver circuitry can be made without any performance
degradation. Refer to the datasheet under the Application Hints
section for component values or to application note AN594 on
the product web page for other input ranges.
Note that the AD7663, AD7665, and AD7671 evaluation boards
are factory configured for the +/-5V range. For different ranges,
the board needs appropriate solder pad configurations.
For dynamic performance, an FFT test can be done by applying
a very low distortion AC source.
POWER SUPPLIES AND GROUNDING
The evaluation board ground plane is separated into two
sections: a plane for the digital interface circuitry and an analog
plane for the analog input and external reference circuitry. To
attain high resolution performance, the board was designed to
ensure that all digital ground return paths do not cross the
analog ground return paths by connecting the planes together
directly under the converter. Power is supplied to the board
through P3 when using with the EVAL-CED1Z
USING THE EVAL-AD762X/AD765X/AD766X/
AD767XEDZ AS STAND-ALONE
Using the evaluation board as stand-alone does not require the
CED nor does it require use of the accompanied software.
When the CONTROL input to the gate array is LOW, which is
pulled down by default, the gate array provides the necessary
signals for conversion and buffers the conversion data.
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 4 of 23
In stand-alone mode, the gate arrays flexible logic buffers the
ADC data according to the read data mode configuration (word
or byte). In parallel reading mode the board is configured for
continuous reading since CS and RD are always driven LOW by
the gate array. Thus, the digital bus is not tri-stated in this mode
of operation and BD[0:15] will continuously be updated after a
new conversion. BD[0:15] is available on P2 after BUSY goes
HIGH. Note that with the 18 bit devices the full 18 bits of data
BD[-2:15] are output directly on P2 since the evaluation board
is not limited to 16 bit wide transfers in stand-alone operation.
When either parallel or serial reading mode, the data is available
on this parallel bus. Refer to Figure 9 to obtain the data output
pins on P2.
Configuration Switches
The evaluation board is configurable for the different operating
modes with 16 positions on the configuration select switches,
S16 and S35. A description of each switch setting and jumper
position is listed in Figure 9 and the available test points are
listed in Table 5. Note that the switches in the ON position
define a logic HIGH level (pulled up with 10kΩ,) and that the
switches are active only in stand-alone mode.
For all interface modes, S16 and S35 allows the selection of:
Warp, Normal or Impulse mode conversions (where applicable)
Binary or 2s complement data output
Reading during or after conversion
Resetting the ADC
ADC power-down
Internal Reference and Buffer power-down (where applicable)
In parallel reading mode, s16 allows the selection of:
Byte swapping for 8 bit interfacing (LSByte with MSByte)
18-bit, 16-bit and 8-bit interfacing (for 18-bit converters)
In serial reading mode, the default settings are Master Read
during Conversion Mode using the internal ADC serial clock.
Serial data is available at T3, T4, T5 and T6 for SDOUT, SCLK,
SYNC and RDERROR respectively. Buffered serial data is
output on the three test points TP17, TP18 and TP19 for SCLK,
SYNC, and SDOUT respectively.
For serial reading mode, S16 allows the selection of:
Choice of inverting SCLK and SYNC
Choice of using internal or external (slave mode) SCLK
SCHEMATICS/PCB LAYOUT
The EVAL-AD76XXEDZ is a 4-layer board carefully laid out
and tested to demonstrate the specific high accuracy
performance of the PulSAR ADC. Figure 8 to Figure 10 show
the schematics of the evaluation board. The printed circuit
layouts of the board are given in Figure 11 - Figure 16. Note
these layouts are not to scale.
Top side silk-screen - Figure 11
Top side layer - Figure 12
Ground layer - Figure 13
Shield layer - Figure 14
Bottom side layer - Figure 15
Bottom side silk-screen - Figure 16
SUPPLYING POWER FOR STAND-ALONE USE
Power needs to be supplied through the two power supply
blocks SJ1 and SJ2. Linear supplies are recommended. SJ1 is the
analog supply for the ADC (AVDD), front end op amps and
reference circuitry. SJ2 is the digital supply for the ADC
(DVDD, OVDD) and gate array. The supplies to the device are
configurable through the power supply jumpers shown in . In
most applications four supplies are required; ±12V and +5V for
analog, and +5V for digital. On board regulators, where
applicable, are used to reduce the operating voltages to the
correct levels. The analog and digital supplies can be from the
same source however, R27 (typically 20Ω) is required from
AVDD to DVDD. In this configuration, JP9, DVDD selection,
should be left open. Furthermore, the OVDD (ADC digital
output supply) may need to be brought up after the analog +5V
supply. See datasheet for details.
EVALUATION BOARD SETTING FOR BIPOLAR ADC
INPUT CONFIGURATIONS
The AD7610, AD7612, AD7631, AD7634, AD7663, AD7665,
AD7671, AD7951 and AD7952 can use both unipolar and
bipolar ranges. The available options are +/-10V, +/-5V, +/-2.5V,
0 to 10V, 0 to 5V and 0 to 2.5V (depending on the ADC).
For the AD7663, AD7665 and AD7671 the evaluation board is
set for the ±5V bipolar input range since these ADCs input
ranges are hardware pin strapped. Simple modifications to these
evaluation boards can be made to accommodate the different
input ranges by changing the INA-IND inputs with the available
solder pads.
iCMOS ADCs
For the AD7610, AD7612, AD7631 AD7634 and AD7951, the
evaluation board can use all input ranges since the input range
is controlled by software (or S16 DIP switches in stand-alone
mode).
For operating in unipolar mode for any of the bipolar
evaluation boards it is recommended to use the voltage divider
consisting of (VCM * R6/(R6+R7)) and (VCM * R29/(R29+R60)).
This allows a transition noise test without any additional
equipment.
HARDWARE SETUP
Using EVAL-CED1Z Capture Board
• EVAL-AD76XXEDZ PulSAR ADC evaluation board
• EVAL-CED1Z
• Enclosed World compatible 7V DC supply
• Enclosed USB to mini USB cable
• DC source (low noise for checking different input ranges)
• AC source (low distortion)
• Band pass filter suitable for 16 or 18 bit testing (value based
on signal frequency)
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 5 of 23
• PC operating Windows XP.
Proceed to the Software Installation section to install the
software. Note: The EVAL-CED1Z board must not be
connected to the PC’s USB port until the Software is
installed. The 7V DC supply can be connected however to
check the board has power (green LED lit).
SOFTWARE INSTALLATION
It is recommended to close all Windows’ applications prior to
installing the software.
System Requirements
• PC operating Windows XP.
• USB 2.0 (for CED board)
• Administrator privileges
CD-ROM –Navigate to Software\CED Version x.x, double click
on setup.exe and follow the instructions on the screen. If
another version of Analog Devices PulSAR Evaluation Software
is present, it may be necessary to remove this. To remove, click
on the Windows “Start” button, select “Control Panel” and “Add
or Remove Programs”. When the list populates, navigate to
Analog Devices High Resolution sampling ADC’s Evaluation
Software or PulSAR Evaluation Software and select Remove.
Website Download
The software versions are also available from the Analog
Devices PulSAR Analog to Digital Converter Evaluation Kit
page. After downloading the software, it is recommended to use
the WinZip “Extract” function to extract all of the necessary
components as opposed to just clicking on setup.exe in the
zipped file. After extracting, click on seteup.exe in the folder
created during the extraction and follow the instructions on the
screen. If another version exists, it may be necessary to remove
as detailed in the above CD-ROM section.
USB Drivers
The software will also install the necessary USB drivers. After
installing the software, power up the CED board and connect to
the PC USB 2.0 port. The Windows “Found New Hardware”
Wizard will display. Click on Next to install the drivers
automatically.
When installed properly, Windows displays the following.
On some PCs, the Found New hardware Wizard may show up
again and if so follow the same procedure to install it properly.
The “Device Manager” can be used to verify that the driver was
installed successfully.
Troubleshooting the Install
If the driver was not installed successfully the device manager
will display a question mark for “Other devices” as Windows
does not recognize the CED1Z board.
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 6 of 23
The “USB Device” can be opened to view it’s uninstalled
properties.
This is usually the case if the software and drivers were installed
by a user without administrator privileges. If so, log on as an
administrator with full privileges and reinstall the software.
RUNNING THE EVALUATION SOFTWARE
The evaluation board includes software for analyzing the
AD7682, AD7689, AD7699 and AD7949. The EVAL-CED1Z is
required when using the software. The software is used to
perform the following tests:
• Histogram for determining code transition noise (DC)
• Fast Fourier transforms (FFT) for signal to noise ratio
(SNR), SNR and distortion (SINAD), total harmonic
distortion (THD) and spurious free dynamic range (SFDR)
The software is located at C:\Program Files\Analog Devices\
PulSAR ADC Evaluation Software\Eval PulSAR CED.exe.
A shortcut is also added to the Windows “Start” menu under
“Analog Devices PulSAR ADC Evaluation Software”, “Eval
PulSAR CED”. To run the software, select the program from
either location.
SETUP SCREEN
Figure 2 is the setup screen where ADC device selection, test
type, input voltage range, sample rate and number of samples
are selected.
DC TESTING - HISTOGRAM
Figure 4 shows a screen shot for the histogram screen. This tests
the ADC for the code distribution for DC input and computes
the mean and standard deviation, or transition noise of the
converter and displays the results. Raw data is captured and
passed to the PC for statistical computations. To perform a
histogram test, select “Histogram” from the test selection
window and click on the “Start” radio button. Note: a histogram
test can be performed without an external source since the
evaluation board has a buffered VREF/2 source at the ADC input
for unipolar parts and at 0V for bipolar devices. To test other
DC values, apply a source to the J1/J2 inputs. It is advised to
filter the signal to make the DC source noise compatible with
that of the ADC. C26/C41 provide this filtering.
AC TESTING
Figure 6 is a screen shot of the fast Fourier transform, FFT. This
tests the traditional AC characteristics of the converter and
displays an FFT of the result. As in the histogram test, raw data
is captured and passed to the PC where the FFT is performed
thus displaying SNR, SINAD, THD and SFDR. The data can also
be displayed in the time domain. To perform an AC test, apply a
sinusoidal signal to the evaluation board at the SMB inputs J1
for IN+ and J2 for IN-. Low distortion, better than 100dB, is
required to allow true evaluation of the part. One possibility is
to filter the input signal from the AC source. There is no
suggested bandpass filter but consideration should be taken in
the choice. Furthermore, if using a low frequency bandpass
filter when the full-scale input range is more than a few Vpp, it
is recommended to use the on board amplifiers to amplify the
signal, thus preventing the filter from distorting the input
signal.
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 7 of 23
Table 1. CNVST Generation, Analog Input Range
Part Resolution
(bits)
Sample Rate Analog Input Range Analog Input Type
AD7621 16 3 MSPS 0 to 2.5V Diff, Unipolar
AD7622 16 2 MSPS 0 to 2.5V Diff, Unipolar
AD7623 16 1.33 MSPS 0 to 2.5V Diff, Unipolar
AD7641 18 2 MSPS 0 to 2.5V Diff, Unipolar
AD7643 18 1.25 MSPS 0 to 2.5V Diff, Unipolar
AD7650 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7651 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7652 16 500 kSPS 0 to 2.5V Single Ended, Unipolar
AD7653 16 1 MSPS 0 to 2.5V Single Ended, Unipolar
AD7660 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7661 16 100 kSPS 0 to 2.5V Single Ended, Unipolar
AD7663 16 250 kSPS -5V to +5V1 Single Ended, Bipolar
AD7664 16 570 kSPS 0 to 2.5V Single Ended, Unipolar
AD7665 16 570 kSPS -5V to +5V Single Ended, Bipolar
AD7666 16 500 kSPS 0 to 2.5V Single Ended, Unipolar
AD7667 16 1 MSPS 0 to 2.5V Single Ended, Unipolar
AD7671 16 1 MSPS -5V to +5V Single Ended, Bipolar
AD7674 18 800KSPS 0 to 5V Diff, Unipolar
AD7675 16 100 kSpS 0 to 2.5V Single Ended, Unipolar
AD7676 16 500 kSPS 0 to 2.5V Single Ended, Unipolar
AD7677 16 1 MSPS 0 to 2.5V Single Ended, Unipolar
AD7678 18 100KSPS 0 to 5V Diff, Unipolar
AD7679 18 571KSPS 0 to 5V Diff, Unipolar
1 Available Input Ranges are 0 to 2.5V, 0 to 5V, 0 to 10V, +/- 2.5V, +/-5V, and +/- 10V. however the board is factory configured for the +/-5V input range. Modify S1 to S7
accordingly (see schematics and datasheets) for different input range configuration.
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 8 of 23
Table 2. Jumper Description
Jumper Name
Default
Position
Function
JP1, JP2 BUFF BUFF Buffer amplifier: BUFF = use op amps to buffer analog input. NO BUFF = direct input from J1,
J2 (SMB).
JP3 VDRV- -12V
Buffer amplifier negative supply: Selection of -12V, -5V or GND when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
JP4 REFS REF Reference selection: REF = use on board reference output for ADC reference. VDD = use
analog supply (AVDD) for ADC reference.
JP6 OVDD 3.3V
ADC digital output supply voltage: Selection of 2.5V, 3.3V and VDIG. VDIG = +5V when using
EVAL-CED1Z or voltage on SJ2 in stand-alone mode.
JP7 VREF+ +12V
Reference circuit positive supply: Selection of +12V, +5V or AVDD when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
JP8 VDRV+ +12V
Buffer amplifier positive supply: Selection of +12V, +5V or AVDD when using EVAL-CED1Z or
voltages on SJ1 in stand alone mode.
JP9 DVDD VDIG/2.51 ADC digital supply voltage: Selection of +2.5V or VDIG (+5V) when using EVAL-CED1Z or
voltage on SJ2 in stand-alone mode.
JP19 AVDD +5V/2.51 ADC analog supply voltage: Selection of +2.5V, +5V or EXT when using EVAL-CED1Z
JP20 REFB BUF
Reference buffer: BUFF = use U2 to buffer or amplify reference source. NO BUFF = use
reference directly into ADC.
JP21 VIO 3.3V
Gate array I/O voltage: Selection of 3.3V or OVDD. Note: gate array will be damaged if >3.3V
(ie. when using OVDD = VDIG).
JP22 CNVST INT CNVST source: INT = use gate array to generate CNVST. EXT = use external source into J3, SMB
for CNVST.
1 For AD7621/22/23//25/41/43 these are set to +2.5V. Note that setting these to +5V will permanently destruct the ADC.
Table 3. S16 - Configuration Select Switch Description
Note: (OFF = LOW, ON = HIGH)
Position Name Default
Position
Function
1 WARP LOW
Conversion mode selection: Used in conjunction with IMPULSE. When HIGH with IMPULSE=
LOW, the fastest (Warp) mode is used for maximum throughput. When LOW and IMPULSE =
LOW, Normal mode is used.
2 IMPULSE LOW
Conversion mode selection: Used in conjunction with WARP. When HIGH with WARP = LOW, a
reduced power mode is used in which the power consumption is proportional to the
throughput rate.
3 BIP LOW For future use.
4 TEN LOW For future use.
5 A0/M0 LOW A0, input Mux selection: Used for AD7654/AD7655 (refer to datasheet).
M0, data output interface selection: Used along with M1 for 18-bit ADCs.
6 BYTE/M1 LOW
BYTESWAP, used for 8-bit interface mode on 16-bit ADCs: MSByte is swapped with LSByte on 8
data lines.
M1, data output interface selection: Used along with M0 for 18-bit ADCs.
7 OB/2C HIGH Data output select: LOW = Use 2’s complement output. HIGH = Straight binary output.
8 SER/PAR LOW Data output interface select: LOW = Parallel interface. HIGH = Serial interface.
9 EXT/INT LOW Serial clock source select: LOW = Use ADC internal serial clock, SCLK is an output. HIGH= Use
external clock, which is MCLK (40 MHz) and SCLK is an input. Not used in parallel reading mode.
10 INVSYNC LOW Serial sync (SYNC) active state: LOW = SYNC is active HIGH. HIGH = SYNC is active LOW. Used
only for Master mode (internal SCLK). Not used in parallel reading mode.
11 INVSCLK LOW Serial clock (SCLK) active edge: LOW = Use SCLK falling edge. HIGH = Use SCLK rising edge.
Active in all serial modes. Not used in parallel reading mode.
12 RDC LOW Read during convert: LOW = Read data after conversion (BUSY = LOW). HIGH = Read data
during conversions (BUSY = HIGH). Used in both parallel and serial interface modes.
Table 4. S35 - Configuration Select Switch Description
Note: (OFF = LOW, ON = HIGH)
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 9 of 23
Position Name Default
Position
Function
1 RESET LOW Reset ADC: LOW = Enables the converter. HIGH = Abort conversion (if any).
2 PD LOW
Power down: LOW = Enables the converter . HIGH = Powers down the converter. Power
consumption is reduced to a minimum after the current conversion.
3 PDBUF LOW
Internal reference buffer power down: LOW = Enable on chip buffer. HIGH = Power down
internal buffer.
4 PDREF LOW
Internal reference power down: LOW = Enable on chip reference. HIGH = Power down internal
reference. Note that when using the on chip reference, the buffer also needs to be enabled
(PDREF = PDBUF = HIGH).
Table 5.Test Points
Tes t
Point
Available
Signal
Type Description
TP1 BUSY Output BUSY signal.
TP2 A0/M0 Input Same as S16, position 5
TP3 SIG+ Input Analog +input.
TP4 AGND GND Analog ground close to SIG+.
TP5 REF Input/Output Reference input. Output for devices with on-chip reference.
TP7 DGND GND Digital ground near SJ2.
TP8 CNVST Input CNVST signal.
TP9 AGND GND Analog ground close to REF.
TP10 CS Input CS, chip select signal.
TP11 RD Input RD, read signal.
TP12 OVDD Power Digital output supply.
TP13 DVDD Power Digital core supply.
TP14 AVDD Power Analog supply.
TP15 AGND GND Analog ground close to SIG-.
TP16 SIG- Input Analog –input for differential parts.
TP17 SCLK Input/Output Buffered serial clock.
TP18 SYNC Output Buffered serial sync.
TP19 SDOUT Output Buffered serial data.
TP20 TEMP Output TEMP, for ADC with internal reference. Outputs temperature dependant voltage (approx.
300mV with TA = 25°C).
TP22 REFIN Input/Output
For ADCs with internal reference, REFBUFIN can be used to connect external reference into
the reference buffer input when PDBUF = LOW and PDREF = HIGH. With the internal
reference (and buffer) enabled, this pin will produce the internal bandgap reference voltage.
TP23 BVDD Output Internal reference bandgap supply. Connected to AVDD via s19.
T3 SDOUT Output Direct ADC serial data.
T4 SCLK Input/Output Direct ADC serial clock.
T5 SYNC Output Direct ADC serial SYNC.
T6 RDERROR Output Direct ADC serial read error.
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 10 of 23
Figure 2. Setup Screen
1. The arrow is used to start the software. When running
is displayed.
2. The part to be evaluated is selected here.
3. The controls are used to set:
Sample Frequency – Enter in kHz Units can be used such as 3k
(case sensitive) for 3,000,000 Hz or 3MSPS.
Clock Source - Selections between control (capture) board or
evaluation board.
Mode – This selects the conversion mode of operation. Some
ADCs have different modes Warp, Normal, and Impulse.
Cnv Mode – Conversion mode; this selects between continuous
(Cont.) or Burst conversion modes. In continuous mode, the
ADC is continuously converting. In Burst mode, the ADC is not
converting (sample clock held in inactive state) and the
conversions begin once the “Single Capture” or “Continuous
Capture” buttons have been selected.
Interface mode – This selects the digital interface to the on-
board FPGA.
Byteswap – A subset of the digital interface mode, this is used
to demonstrate byte-wide transfers to the FPGA.
Coding – Another subset to the digital interface mode, this can
be used to select straight binary or 2’s complement output. Note
the time domain chart and data output (F5) plots and saves data
in straight binary.
Reset – Resets the ADC.
PD, PDREF, PDBUF – These can be used to power down the
ADC, internal reference and internal reference buffer.
4. These controls are used for saving, printing, help, etc. and are
also accessed in the File menu.
Save (F5): type – LabView config, allows the current
configuration to be saved to a filename.dat file. Useful when
changing many of the default controls. To load the saved
configuration, use the Load Previous Configuration.
Type – Html, saves the current screen shot to an Html file.
Type – Spreadsheet, saves the current data displayed in the chart
in a tab delimited spreadsheet. Raw ADC Data is time domain
in Codes, FFT or Decimated is in dB.
5. Stop (F10) is used to stops the software. The can also be
used to stop the software. RESET is used to reset the CED or
ECB capture boards.
1
3
4
5
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 11 of 23
Figure 3. Context Help
1. To use the on-screen help. Select Help, Show Context Help or
click the Help (F1). An example of the Context Help is shown
above for the Sample Frequency. Placing the curser on most
screen items displays useful help for the particular control or
displayed unit.
2. These controls are used for axes and zooming panning.
Locks the graph axis to automatically fit the data.
Uses last axis set by user. , rescale the axes to the
automatic values.
, are used to set axes properties such as format,
precision, color, etc. Right mouse click to change to
Hexadecimal, number of digits, etc.
Displays the cursor.
Is used For zooming in and out.
Is used for panning.
Is used to set various graph properties such as graph
type, colors, lines, etc.
1
2
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 12 of 23
Figure 4. Histogram Screen
1. These radio buttons are used to perform a Single Capture or
Continuous Capture of data set in the # of Samples field. The
results are displayed in the chart. Note that the results can be
displayed as:
A
Or an (time domain)
2., 3.These display the statistics for the X and Y-axes,
respectively.
1
3 2
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 13 of 23
Figure 5. Summary
The charts can be displayed together when the tab is selected.
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 14 of 23
Figure 6. FFT Spectrum
1. Displays the FFT when the Spectrum chart is selected
2., 3. Display the data for the X and Y-axes, respectively.
.
3 2
1
1
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 15 of 23
Figure 7. Oscilloscope
1. Time domain data can be viewed with the oscilloscope also.
1
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 16 of 23
EVALUATION BOARD SCHEMATICS AND ARTWORK
123456
A
B
C
D
6
54321
D
C
B
A
S1 S2 S4 S6
R48
15
R46
0.0
C40
C38
R45
0.0
S3 S5 S7
R47
15
C39
TP5
REF
C32B
47uF
C31B
1uF
TP9
AGND
GND
REF
S12
GND
CNVST
CS
RD
BUSY
RESET
PD
D0
BYTE/M1
D1
IMPULSE
D2
WARP
D3
OB/2C
D4
SER/PAR
D5
T1/EOC
D6
PDRT0
D7
D8
D9
D10
D11
D12
D13
D14
D15
PD
RESET
IMPULSE
SER/PAR
RD
CS
CNVST
D[0..15]
BUSY
VCM
A0
A0
D[0..15]
INGND
IN_A
IN_B
IN_C
IN_D
T0PDR
PDBT1
S10
S9
S15 S14
S13
S11
S20 S8
C31T
C13
GND
S30
S31
R59
R43
TP15
AGND R61
0.0
R29
590
R60
590 C42
.1uF
C35
10pF-NPO
C37
.1uF
C41
TP4
GND
GND
R44
R5
0.0 C34
10pF-NPO
R6
590
R42
49.9
C26
C36
C22
.1uF
TP3
SIG+
GND
GND
GND
GND
TP16
SIG-
C20
.1uF
C19
R2
R1
R3
0
2
3
4
5
6
7
U7A
AD8021
2
3
4
5
6
7
U6A
AD8021
GND
GND
GND
VDRV+
VDRV-
VDRV+
VDRV-
VCM
VCM
J1
AIN+
J2
AIN-
SIG+
SIG-
R7
590
6
57
U2B
AD8032AR
2
3
4
1
8
U2A
GND
C29
.1uF
C27
.1uF
C28
.1uF
C25
.1uF
VREF+
GND
GND
GND
GND
C9
1uF
IN
3
GND
2
OUT 1
U5B
AD158X
R9
R4
10K
C6
1uF
VREF+AVDD
JP4
JP20
C8
10uF
VCM
REF
VOUT 6
TRIM 5
GND
4
TEMP
3
+VIN 2
2.5/3v
8
U5A
ADR43X
NOTE:
EITHER U5A OR U5B
IS USED AT A TIME
C52
.1uF
C53
.1uF
R31
49.9
R34
49.9
NOTE:
ANY PASSIVE COMPONENTS WITHOUT VALUE
ARE NOT POPULATED
R35
R37
10K
R10
GND
A
A
C60
C64
GND
C59
S19
AVDD
S18
REFOUT
M.M
EVAL-AD76XXCB
ANALOG
8-F eb-2005 Rev. : J
GND
VDRV+
VDRV-
VREF+
VREF+
GND
JP2
JP1
REFOUT
TP20
TEMP
C5B
.1uF C5T
.1uF
C9T
.1uF
C9B
.1uF
C7B
.1uF C7T
.1uF
OVDD
AVDD
DVDD
GND
GND
GND
AVDD
OVDDDVDD
TP12
OVDD
TP14
AVDD
TP13
DVDD
AVDDDVDDOVDD
GND
REFS
REFB
REF
VDD
BUF
NOBUF
BUF
NOBUF
NOBUF
DVDD 19
OVDD 18
AVDD 2
REF
37
REFGND
38
DGND 17
DGND 20
AGND 1
D3/DIVSCLK(1) 12
D2/DIVSCLK(0) 11
D1 10
D0 9
D4/EXT/INT 13
D5/INVSYNC 14
D6/INVSCLK 15
D7/RDC/SDIN 16
RESET
33
IMPULSE
7
PD
34
BYTESWAP
4
A0 3
IN_A/INBN
40 IN_B/INB2
41 IN_C
42 IN_D/IN+
43
INGND/IN-/INB1
39
REFIN/INA1
46
PDREF/T0 47
INA2
44
INAN/TEMP
45 PDBUF/T1 48
D10/SYNC 23
D9/SCLK 22
D8/SDOUT 21
CS 32
CNVST 35
BUSY 29
D11/RDERROR 24
D12 25
D13 26
D14 27
D15 28
RD 31
T0/PDREF 36
T1/EOC 30
OB/2C A/B
5WARP
6
SER/PAR
8
U1
AD76XX
DAC+ DAC+
DAC- DAC-
C55 C56
GND
R90
0.0
R91
0.0
S21
S17
+VS-VS
+VA
+VA -VS
-VS
R96
0.0
R97
0.0
BUF
S32
S33
TP22
VBG
S34
AIN+
VCMT
AIN+
SIG+
SIG-
VCMT
AIN-
AIN-
GND
GND
TEMP
TEMP
TP23
BVDD
BUF
Figure 8. Schematic, Analog
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 17 of 23
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
P2
GND
R28
100 R30
100
JP22 R36
1 M
TP8
CNVST
CNVOUT
3.3V
J3
CNVSTIN
BD0
A
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
GND
VIO
R32
100
R55
10K
R68
49.9
TP1
BUSY
TP11TP10
PD
T0PDR
SER/PAR
OB/2C
WARP
IMPULSE
BYTE/M1
PD
RESET
BUSY
RD
CS
CNVST
BYTE/M1
RESET
OB/2C
SER/PAR
IMPULSE
D[0..15]
PDBT1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D[0..15]
A0
WARP
PDRT0
T1/EOC
D9
A0
S26
TP2
A0
S24
S25
S22
S23
S28
S29
S27
GND
T1
T2
T3
T4
T5
T6
R54
10K
GND
BWR R66 10K
3.3V
ADCOK
SDOUT
SCLK
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
BCS
BBUSY
BRD
BWR
CONTROL
R52 10K
R51 10K
R80
100
D2
TP7
GND
VDIG
1
VDIG 4
OUT
3
GND 2
U12 3.3V
C30
.1uF
3.3V
AD1
AD0
CS 4
OE 3
CASC 6
DATA
1
DCLK
2
3.3V
73.3V
8
GND 5
U11
EPC1441
R38
1K R39
1K R40
1K C16
.1uF
GND
GND
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
AD0
DSPCLK
AD1
GND
CONTROL
BRD
BBUSY
SCLK
TFS0
SDOUT
TFS0
SDIN
CONFIG
CONF_D
STATUS
DCLK
DATA
SDIN
C5
C7
C19
B18
A18
B17
B15
B14
B13
B11
B10
B7
B6
B5
B3
B2
A14
C15
B9
C18
A19
C10
C17
A9
C9
B1
A17
A5
A6
C6
C14
A27
C27
P3A
SYNC
SYNC
AD2
GND
AD2
RESETS
3.3V
R65
10K
R63
10K
R64
10K
GND
M0
M1
M2
DSPCLK
R58 10K
R57 10K
RESETD
RESETD
R56 10K
R62 10K
M3
GND
FSYNC
BIP
T1
BIP
+VA
-VA
+12V
VDIG
-12V
A4
A12
A16
A20
B4
B12
B16
C4
C12
C16
C20
B20
B26
B27
B28
B29
B30
C21
C22
C23
C24
C25
C26
C29
A21
A22
A32
B32
C32
A31
B31
C31
C30
A8
B8
C8
A30
P3B
A23
A24
A25
A26
A29
B21
B22
B23
B24
B25
P3C
+VA
+12V
GND
GND
-VA
-12V
VDIG
C23
.1uF C24
.1uF
C17
.1uF
C18
.1uF
C3
.1uF
C21
.1uF
GND
C5
.1uF
C7
.1uF
C4
.1uF
C10
.1uF
C11
.1uF
C12
.1uF
VIO
GND
3.3V
R53
10K
R41 1K
R67 10K
DBUSY
VIO
3.3V
JP14
R11
10K
R12
10K
R13
10K
R16
10K
R14
10K
R17
10K
OB/2C
WARP
IMPULSE
RESET
BYTE/M1
PD
D4
D5
D6
D7
R74
1K
R72
1K
R73
1K
R75
1K
R78
1K
R79
1K
VIO
R15
10K
R19
10K
R20
10K
R22
10K
R81
10K
R21
10K
R70
1K
R33
1K
R69
1K
R71
1K
R76
1K
R77
1K
VIO
SER/PAR
GND
TP6
SYNC-FFT
TP17
SCLK
TP18
SYNC
TP19
SDOUT
EVAL-AD76XXCB
DIGITAL
M.M
8- Feb-2005 Rev. : J
BD-1
BD-2
DBUSY BCS
BD-1
BD-2
BD-1
BD-2
SER/PAR
BIPOLAR
EXT/
INVSYNC
INVSCLK
RDC
INT
PD
BYTE/M1
RESET
IMPULSE
WARP
OB/ 2C
R82
10k
R83
R85
10K
3.3V
BCS
DAC+ DAC+
DAC- DAC-
R88
10K
R89
10K
PDREF
TEN
R92
1K
R93
1K
PDREF
TEN
3.3V
TP21
GND
JP11
C57
GND
GND
DCLK 128
CONF_D 105
CE 4
CONFIG 53
DATA 125
BCS 111
RESETD 86
MSEL 33
STATUS 56
BD3 120
ADCOK 49
BD4 117
D11
10
MCLK 69
AD0 93
AD1 96
AD2 95
DR0 122
TFS0 118
SCLK0 116
FSYNC 131
BBUSY 85
BD15 73
BD13 81
BD12 72
BD11 84
BD10 87
BWR 114
BD9 94
BD8 109
BD7 110
BD6 112
BD5 115
BD2 123
BD1 124
BD0 129
CONTROL 130
D12
144
D13
143
BRD 113
BD14 82
DT0 121
RFS0 119
MODE0 47
MODE1 46
MODE2 45
DSPCLK 71
MODE3 44
RESETS 43
D10
11 D9
12 D8
14
D14
142
D0
26
CNVST
137
D6
16
D7
15
D15
141
D1
25
D2
24
D3
23
D4
22
D5
21
BUSY
140
RD
139
CS
138
RESET
136
PD
135
CNVSTOUT
2
SER/PAR
35
IMPULSE
36
WARP
37
OB/2C
38
BYTE
39
A0
57
PDREF
58
TEST0
59
EOC
60
TEST1_OUT
61
PDBUF
62
SCLKIN
13
TEMP
41
DBUSY 40
BD-1 107
BD-2 108
CNVSTOUTB
134
U10A
EPF6010ATC144-3
VIO 55
VIO 78
VIO 91
VIO 104
3.3V 6
3.3V 31
3.3V 77
3.3V 103
VIO 32
VIO 19
VIO 7
VIO 127
GND
5
GND
18
GND
30
GND
54
GND
76
GND
90
GND
102
GND
126
U10B
EPF6010ATC144
GND
3.3VVIO
124
S16A
223
S16B
322
S16C
421
S16D
520
S16E
619
S16F
718 S16G
817 S16H
916 S16I
1015 S16J
1114 S16K
1213 S16L
R100
10K
R101
10K
PDBUF
A0/M0
R98
1K
R99
1K
GND
1 8
S35A
2 7
S35B
3 6
S35C
4 5
S35D
PDBUF
A0/M0
PDREFPDRT0
A0/M0
PDBUF
TEN
CNVST
CS RD
R49
0
TEMP TEMP
C47
GND
R86
49.9
CNVOUT
EXT
INT
CNV SEL
Figure 9. Schematic, Digital
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 18 of 23
1 2 3 4 56
A
B
C
D
6
54321
D
C
B
A
C32
1uF
C33
1uF
C46
1uF
SJ2
GND
VDIG
VDIG
GND
+VA
+12V
JP7
JP8
-VA
1
2 4
3
JP3 VDRV-
GND
3.3V
GND
VDRV+
VREF+
1
2 4
3JP19
3
1
2
5
4
6
SJ1
C54
10uF
C51
10uF
C2
10uF
C50
10uF
+5V
+12V
-5V
GND
AVDD
GND
+VA
-VA
+12V
GND
GND
+VA
C43
1uF
C44
1uF
C49
10uF
C48
10uF
OVDD
DVDD
1
2 4
3
JP6
3.3VVDIG
AVDD
1
23
JP9
VDIG R27
EXT
-12V
-12V
OVDD
VDIG
DVDD
VDRV+
C1
10uF
VDRV-
OVDD
DVDD
3.3V VREF+
VREF+
JP21
3.3V
D1
VIO
VIO
AVDD
AVDD
GND
VIO
VIO
GND
C45
1uF
OUT 1
OUT 2
FB 3
NC
4
GND
5
SD
6
IN
7
IN
8
U5
ADP3334ARM
R8
106.1k
R24
94.5k
GND
2.5V
GND
OUT 1
OUT 2
FB 3
NC
4
GND
5
SD
6
IN
7
IN
8
U4
ADP3334ARM
R23
140K
R26
78.7K
GND
3.3V
GND
VDIG
M.M
EVAL-AD76XXCB
POWER
8-Fe b-2005 Rev . : J
VDIG
VDIG
OUT 1
OUT 2
FB 3
NC
4
GND
5
SD
6
IN
7
IN
8
U8
ADP3334ARM
R18
106.1k
R25
94.5k
GND
GND
R84
0
GND
C14
10uF
GND
-12V
-VA
+VA
+12V
1
2 4
3JP5
1
23
JP10
-12V
-12V
-VA
EXT
EXT
+12V
GND
C15
10uF
-VS
GND
C31
10uF
+VS
GND
+VA
+VA -VS
-VS
Figure 10. Schematic, Power
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 19 of 23
Figure 11. Top Side Silk-Screen
Figure 12. Top Layer
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 20 of 23
Figure 13. Ground Layer
Figure 14. Shield Layer
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 21 of 23
Figure 15. Bottom Side Layer
a
Figure 16. Bottom Side Silk-Screen
EVAL-AD76XXEDZ Preliminary Technical Data
Rev. PrB | Page 22 of 23
Table 6. Bill of Materials for the Connectors
Ref Des Connector Type Manf. Part No.
J1 – J3 RT Angle SMB Male Pasternack PE4177
P2 0.100 X 0.100 straight IDC header 2X20 3M 2540-6002UB
P3 32X3 RT PC MOUNT CONNECTOR ERNI 533402
ORDERING GUIDE
These evaluation boards are compatible with both EVAL-CED1Z and EVAL-CONTROL BRDxZ. For simplicity, this document was made
especially for EVAL-CED1Z usage. Refer to Analog Devices PulSAR Evaluation Kit product page for the user’s guide specific to EVAL-
CONTROL BRDxZ usage.
Evaluation Board Model Product
EVAL-AD7621CBZ AD7621ASTZ/ACPZ
EVAL-AD7622CBZ AD7622BSTZ/BCPZ
EVAL-AD7623CBZ AD7623ASTZ/ACPZ
EVAL-AD7641CBZ AD7641BSTZ/BCPZ
EVAL-AD7643CBZ AD7643BSTZ/BCPZ
EVAL-AD7650CBZ AD7650ASTZ/ACPZ
EVAL-AD7651CBZ AD7651ASTZ/ACPZ
EVAL-AD7652CBZ AD7652ASTZ/ACPZ
EVAL-AD7653CBZ AD7653ASTZ/ACPZ
EVAL-AD7660CBZ AD7660ASTZ/ACPZ
EVAL-AD7661CBZ AD7661ASTZ/ACPZ
EVAL-AD7663CBZ AD7663ASTZ/ACPZ
EVAL-AD7664CBZ AD7664ASTZ/ACPZ
EVAL-AD7665CBZ AD7665ASTZ/ACPZ
EVAL-AD7666CBZ AD7666ASTZ/ACPZ
EVAL-AD7667CBZ AD7667ASTZ/ACPZ
EVAL-AD7671CBZ AD7671ASTZ/ACPZ
EVAL-AD7674CBZ AD7674ASTZ/ACPZ
EVAL-AD7675CBZ AD7675ASTZ/ACPZ
EVAL-AD7676CBZ AD7676ASTZ/ACPZ
EVAL-AD7677CBZ AD7677ASTZ/ACPZ
EVAL-AD7678CBZ AD7678ASTZ/ACPZ
EVAL-AD7679CBZ AD7679ASTZ/ACPZ
EVAL-CED1Z USB Capture Board
Preliminary Technical Data EVAL-AD76XXEDZ
Rev. PrB | Page 23 of 23
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07201-0-3/09(PrB)
