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DInjection Current Cross−Coupling
<1mV/mA (see Figure 1)
DLow Crosstalk Between Switches
DPin Compatible with SN74HC4052,
SN74LV4052A, and CD4052B
D2-V to 6-V VCC Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This dual 4-to-1 CMOS analog multiplexer/demultiplexer is pin compatible with the 4052 function and also
features injection-current effect control. This feature has excellent value in automotive applications where
voltages in excess of normal supply voltages are common.
The injection-current effect control allows signals at disabled analog input channels to exceed the supply
voltage without affecting the signal of the enabled analog channel. This eliminates the need for external
diode/resistor networks typically used to keep the analog channel signals within the supply voltage range.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube SN74HC4852N SN74HC4852N
SOIC − D
Tube SN74HC4852D
HC4852
−40°C to 125°C
SOIC − D Tape and reel SN74HC4852DR HC4852
−40
°
C to 125
°
C
TSSOP − PW
Tube SN74HC4852PW
HC4852
TSSOP − PW Tape and reel SN74HC4852PWR HC4852
TVSOP − DGV Tape and reel SN74HC4852DGVR HC4852
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
ON
INH B A
ON
CHANNEL
L L L 1Y0, 2Y0
LL H 1Y1, 2Y1
LH L 1Y2, 2Y2
LH H 1Y3, 2Y3
H X X None
Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y0
2Y2
2-COM
2Y3
2Y1
INH
NC
GND
VCC
1Y2
1Y1
1-COM
1Y0
1Y3
A
B
D, DGV, N, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
SCLS573 − MARCH 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
1-COM
INH
B
A
2-COM
10
9
6
13
12
14
15
11
1
5
2
4
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, VIO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O diode current, IIOK (VIO < 0 or VIO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch through current, IS (VIO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS573 − MARCH 2004
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recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage 2 6 V
VCC = 2 V 1.5
High-level input voltage,
VCC = 3 V 2.1
V
IH
High-level input voltage,
control inputs
VCC = 3.3 V 2.3 V
VIH
control inputs
VCC = 4.5 V 3.15
V
VCC = 6 V 4.2
VCC = 2 V 0.5
Low-level input voltage,
VCC = 3 V 0.9
V
IL
Low-level input voltage,
control inputs
VCC = 3.3 V 1V
VIL
control inputs
VCC = 4.5 V 1.35
V
VCC = 6 V 1.8
VIControl input voltage 0 VCC V
VIO Input/output voltage 0 VCC V
VCC = 2 V 1000
VCC = 3 V 800
∆t/∆vInput transition rise or fall rate VCC = 3.3 V 700 ns
∆t/∆v
Input transition rise or fall rate
VCC = 4.5 V 500
ns
VCC = 6 V 400
TAOperating free-air temperature −40 125 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SCLS573 − MARCH 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C−40 TO 85°C−40 TO 1255C
UNIT
PARAMETER
TEST CONDITIONS
VCC MIN TYP MAX MIN MAX MIN MAX
UNIT
2.V 500 650 670 700
On-state
IS ≤ 2 mA
V = V to GND,
3 V 215 280 320 360
r
on
On-state
switch resistance
IS 2 mA
VI = VCC to GND,
VINH = VIL
3.3 V 210 270 305 345 Ω
ron
switch resistance
VINH = VIL
(see Figure 5)
4.5 V 160 210 240 270
Ω
(see Figure 5)
6 V 150 195 220 250
2.V 4 18 22 24
Difference in
IS ≤ 2 mA
3 V 2 12 14 16
∆r
on
Difference in
on-state resistance
between switches
IS ≤ 2 mA
V
I
= V
CC
/2
V = V
3.3 V 2 12 14 16 Ω
∆ron
on-state resistance
between switches
VI = VCC/2
VINH = VIL 4.5 V 2 8 12 16
Ω
INH IL
6 V 3 9 13 18
IIControl input current VI = VCC or GND 6 V ±0.1 ±0.1 ±1µA
IS(off)
Off-state switch
leakage current
(any one channel)
VI = VCC or GND
VINH = VIH
(see Figure 6)
6 V
±0.1 ±0.5 ±1
A
IS(off) Off-state switch
leakage current
(common channel)
VI = VCC or GND
VINH = VIH
(see Figure 7)
6 V
±0.2 ±2±4
µA
IS(on) On-state switch
leakage current
VI = VCC or GND,
VINH = VIL
(see Figure 8) 6 V ±0.1 ±0.5 ±1µA
ICC Supply current VI = VCC or GND 6 V 2 5 10 µA
CIC Control input capacitance A, B, INH 3.5 10 10 10 pF
CIS Common
terminal capacitance Switch off 22 40 40 40 pF
COS Switch terminal capacitance Switch off 6.7 15 15 15 pF
injection-current coupling specifications, TA = −40°C to 125°C (see Figure 1)
PARAMETER VCC TEST CONDITIONS TYP†MAX UNIT
3.3 V
II‡ ≤ 1 mA,
0.05 1
5 V
I
I
‡
≤
1 mA,
RS ≤ 3.9 kΩ
0.1 1
3.3 V
II‡ ≤ 10 mA,
R
S
≤
3.9 k
Ω0.345 5
V∆out
Maximum shift of output voltage of enabled analog channel
5 V
I
I
‡
≤
10 mA,
0.067 5
mV
V
∆ou
t
Maximum shift of output voltage of enabled analog channel
3.3 V
II‡ ≤ 1 mA,
0.05 2
mV
5 V
I
I
‡
≤
1 mA,
RS ≤ 20 kΩ
0.11 2
3.3 V
II‡ ≤ 10 mA,
R
S
≤
20 k
Ω0.05 20
5 V
I
I
‡
≤
10 mA,
0.024 20
†Typical values are measured at TA = 25°C.
‡II = total current injected into all disabled channels.
SCLS573 − MARCH 2004
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switching characteristics over recommended operating free-air temperature range,
VCC = 2 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
TO
TA = 25°C−40 TO 85°C−40 TO 125°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
tPHL Propagation
delay time COM or Yn Yn or COM 14.5 19.5 33 12 34 11 35 ns
tPLH
tPHL Propagation
delay time Channel Select COM or Yn 19.6 24.5 38 15.4 40 13.8 42 ns
tPZH
tPZL Enable
delay time INH COM or Yn 19.4 23.6 47.5 15.8 52.5 14.5 57.5 ns
tPHZ
tPLZ Disable
delay time INH COM or Yn 39.5 48.4 100 39.3 105 39 115 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
TO
TA = 25°C−40 TO 85°C−40 TO 125°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
tPHL Propagation
delay time COM or Yn Yn or COM 8.6 12 16.5 6.5 18 5.8 19.5 ns
tPLH
tPHL Propagation
delay time Channel Select COM or Yn 12.4 14.6 20 9.3 21.5 8.2 23 ns
tPZH
tPZL Enable
delay time INH COM or Yn 12.1 13.8 45 9.2 50 8.5 55 ns
tPHZ
tPLZ Disable
delay time INH COM or Yn 35.2 44.5 90 35.5 100 35 110 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
TO
TA = 25°C−40 TO 85°C−40 TO 125°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
tPHL Propagation
delay time COM or Yn Yn or COM 7.9 11 15 5.8 16.5 5 18.5 ns
tPLH
tPHL Propagation
delay time Channel Select COM or Yn 11.4 13.5 17.5 8.5 19 7.5 22 ns
tPZH
tPZL Enable
delay time INH COM or Yn 11.2 12.7 42.5 8.4 47.5 7.4 52.5 ns
tPHZ
tPLZ Disable
delay time INH COM or Yn 34.6 43.9 85 34.6 95 34.5 105 ns
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 4.5 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
TO
TA = 25°C−40 TO 85°C−40 TO 125°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
tPHL Propagation
delay time COM or Yn Yn or COM 6.3 8.6 11.6 4.6 12.5 4.5 13.5 ns
tPLH
tPHL Propagation
delay time Channel Select COM or Yn 9.3 11 14 6.5 15 5.6 17 ns
tPZH
tPZL Enable
delay time INH COM or Yn 8 9.9 40 5.3 45 4.4 50 ns
tPHZ
tPLZ Disable
delay time INH COM or Yn 28.5 41.4 80 28.2 90 28 100 ns
switching characteristics over recommended operating free-air temperature range,
VCC = 6 V, CL = 50 pF (unless otherwise noted) (see Figures 9−14)
PARAMETER
FROM
TO
TA = 25°C−40 TO 85°C−40 TO 125°C
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
tPHL Propagation
delay time COM or Yn Yn or COM 5.5 8 10.2 4.1 11 3.6 12 ns
tPLH
tPHL Propagation
delay time Channel Select COM or Yn 7.4 9.5 12.6 4.7 14.5 3.8 16.5 ns
tPZH
tPZL Enable
delay time INH COM or Yn 6.8 8.4 39 4.8 40 3.8 40 ns
tPHZ
tPLZ Disable
delay time INH COM or Yn 14.4 38 78 13.5 80 13 80 ns
operating characteristics, TA = 25°C (see Figure 15)
PARAMETER VCC TEST CONDITIONS TYP UNIT
Cpd
Power dissipation capacitance
3.3 V
No load
48
pF
C
pd
Power dissipation capacitance
5 V
No load
60
pF
SCLS573 − MARCH 2004
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APPLICATION INFORMATION
VCC = 5 V
IIO
VIN2 < VSS or VCC < VIN2
Any Disabled Channel
VSS < VIN1 < VCC
Enabled Channel
RS
Vout = VI1 V ± V∆out
Figure 1. Injection-Current Coupling Specification
5 V
HC4052A VCC
Microcontroller
Channel 1Y0
Channel 1Y1
Channel 1Y2
Channel 1Y3
Channel 2Y0
Channel 2Y1
Channel 2Y2
Channel 2Y3
2-COM
5 V 5 V
A/D − Input 2
VCC
(8y Identical
Circuitry)
Sensor
1-COM A/D − Input 1
Figure 2. Actual Technology Requires 32 Passive Components and One Extra 6-V Regulator
to Suppress Injection Current Into a Standard HC4052 Multiplexer
SCLS573 − MARCH 2004
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
HC4052A VCC
Microcontroller
Channel 1Y0
Channel 1Y1
Channel 1Y2
Channel 1Y3
Channel 2Y0
Channel 2Y1
Channel 2Y2
Channel 2Y3
2-COM
5 V
A/D − Input 2
VCC
(8x Identical
Circuitry)
Sensor
1-COM A/D − Input 1
Figure 3. Solution by Applying the HC4852 Multiplexer
+
+
+
N − Substrate (on VCC potential)
Disabled Analog Mux Input
VIn > VCC + 0.7 V
Gate = VCC
(Disabled)
Common Analog Output
Vout > VCC
P+ P+
Figure 4. Diagram of Bipolar Coupling Mechanism
(Appears if VIn Exceeds VCC, Driving Injection Current Into the Substrate)
SCLS573 − MARCH 2004
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PARAMETER MEASUREMENT INFORMATION
VCC
VI = VCC to GND
VINH = VIL
IS
VO
ron +VI–V
O
IT W
VI − VO
VCC
GND
(ON)
V
Figure 5. On-State Resistance Test Circuit
COMMON O/I
6
8
OFF
OFF
VCC
VCC
VCC
GND
VINH = VIH
16
ANC
Figure 6. Maximum Off-Channel Leakage Current, Any One Channel, Test Setup
VCC
Figure 7. Maximum Off-Channel Leakage Current,
Common Channel, Test Setup
COMMON O/I
6
8
OFF
OFF
VCC
ANALOG I/O
VCC
GND
VINH = VIH
16
A
Figure 8. Maximum On-Channel Leakage Current,
Channel to Channel, Test Setup
COMMON O
/I
6
8
ON
OFF
VCC VCC
VCC
GND
VINH = VIL
16
A
ANALOG I/O
NC
SCLS573 − MARCH 2004
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 9. Propagation Delays, Channel Select to
Analog Out
50%
tPLH tPHL
VCC
GND
CHANNEL
SELECT
ANALOG
OUT 50%
COMMON O/I
6
8
ON/OFF
OFF/ON
VCC
VCC
16
ANALOG I/O TEST POINT
CHANNEL SELECT
CL†
†Includes all probe and jig capacitance
Figure 10. Propagation Delay, Channel Select to
Analog Out, Test Setup
Figure 11. Propagation Delays, Analog In
to Analog Out
50%
tPLH tPHL
VCC
GND
ANALOG
IN
ANALOG
OUT 50%
COMMON O/I
6
8
ON
V
CC
16
TEST POIN
T
CL†
†Includes all probe and jig capacitance
Figure 12. Propagation Delay, Analog In to Analog
Out, Test Setup
ANALOG
I/O
SCLS573 − MARCH 2004
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 13. Propagation Delays, Enable to Analog
Out
ENABLE
ANALOG
OUT
ANALOG
OUT
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
GND
10%
90%
VCC
HIGH
IMPEDANCE
50 %
50 %
tftf
90%
50%
10%
HIGH
IMPEDANCE
Figure 14. Propagation Delay, Enable to Analog
Out, Test Setup
6
8
ON/OFF
VCC
VCC 16
ENABLE
1
2
1
2CL
TEST POIN
T
10 kΩ
Position 1 when testing t
PHZ
and t
PZH
Position 2 when testing tPLZ and tPZL
ANALOG
I/O
Figure 15. Power-Dissipation Capacitance, Test
Setup
COMMON O/I
6
8
ON/OFF
OFF/ON
VCC
VCC
16
ANALOG I/O NC
CHANNEL SELECT
A
11
VCC
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74HC4852D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DE4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DRE4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852DRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HC4852NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HC4852PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HC4852PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74HC4852 :
•Automotive: SN74HC4852-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HC4852DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74HC4852DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74HC4852PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC4852DGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74HC4852DR SOIC D 16 2500 333.2 345.9 28.6
SN74HC4852PWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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