ACPL-5160, ACPL-5161 and 5962-12236* 2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback Data Sheet Description Features This family of Avago 2.5 Amp Gate Drive Optocouplers provides Integrated Desaturation (VCE) Detection and Fault Status Feedback for IGBT VCE fault protection in a rugged, hermetically-sealed package. The devices are capable of operation and storage over the full military temperature range and can be purchased as either commercial-grade products or in fully MIL-STD compliant versions. The military standard devices are manufactured and tested on a MIL-PRF-38534 certified line to Class H specifications; Standard Microcircuit Drawing (SMD) 5962-12236. They are included in the Defense Logistics Agency (DLA) Land and Maritime Qualified Manufacturers List, QML-38534 for Hybrid Microcircuits. * * * * * * * * * * * * 2.5 A maximum peak output current Drive IGBTs up to IC = 150 A, VCE = 1200 V Optically isolated, FAULT status feedback Hermetically sealed ceramic package CMOS/TTL compatible 500 ns max. switching speeds "Soft" IGBT turn-off Integrated fail-safe IGBT protection - Desat (VCE) detection - Under Voltage Lock-Out protection (UVLO) with hysteresis User configurable: inverting, noninverting, auto-reset, auto-shutdown Wide operating VCC range: 15 V to 30 V -55 C to +125 C operating temperature range 15 kV/s Typical Common Mode Rejection (CMR) at VCM = 1000 V Fault Protected IGBT Gate Drive +HV ISOLATION BOUNDARY ISOLATION BOUNDARY ISOLATION BOUNDARY ACPL - 516x ACPL - 516x ACPL - 516x 3-PHASE INPUT M ACPL - 516x ACPL - 516x ISOLATION BOUNDARY ISOLATION BOUNDARY ACPL - 516x ISOLATION BOUNDARY ACPL - 516x ISOLATION BOUNDARY -HV FAULT MICROCONTROLLER * SMD pending CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Typical Fault Protected IGBT Gate Drive Circuit The ACPL-516x is an easy-to-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-to-implement. Features such as user configurable inputs, integrated VCE detection, under volt- age lockout (UVLO), "soft" IGBT turn-off and isolated fault feedback provide maximum design flexibility and circuit protection. ACPL-516x + - C RF VE 16 VIN- VLED2+ 15 VCC1 DESAT 14 1 VIN+ 2 3 4 GND1 VCC2 13 5 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1- VEE 9 * CBLANK 100 DDESAT + + - * VF - + RG VCE - + * - + RPULL-DOWN VCE - * THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED. Figure 1. Typical desaturation protected gate drive circuit, noninverting Description of Operation during Fault Condition 1. DESAT terminal monitors the IGBT VCE voltage through DDESAT. 2. When the voltage on the DESAT terminal exceeds 7 V, the IGBT gate voltage (VOUT ) is slowly lowered. 3. FAULT output goes low, notifying the microcontroller of the fault condition. 4. Microcontroller takes appropriate action. UVLO VIN+ VIN(VCC2 - VE) X X Active X Low X High 2 X X High Low X X X Not Active Output Control The outputs (VOUT and FAULT) of the ACPL-516x are controlled by the combination of VIN, UVLO and a detected IGBT Desat condition. As indicated in the below table, the ACPL-516x can be configured as inverting or noninverting using the VIN+ or VIN- inputs respectively. When an inverting configuration is desired, VIN+ must be held high and VIN- toggled. When a noninverting configuration is desired, VIN- must be held low and VIN+ toggled. Once UVLO is not active (VCC2 VE > VUVLO), VOUT is allowed to go high, and the DESAT (pin 14) detection feature of the ACPL-516x will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the DESAT detection and UVLO features of the ACPL-516x work in conjunction to ensure constant IGBT protection. Desat Condition Detected on Pin 14 Pin 6 (FAULT) Output X Yes X X No X Low X X High VOUT Low Low Low Low High Product Overview Description The ACPL-516x is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit with fault protection and feedback into one rugged, hermetically sealed package. TTL input logic levels allow direct interface with a microcontroller, and an optically isolated power output stage drives IGBTs with power ratings of up to 150 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. An output IC provides local protection for the IGBT to prevent damage during overcurrents, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in "watchdog" circuit monitors the power stage supply voltage to prevent IGBT damage caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. Two light emitting diodes and two integrated circuits housed in the same 16-pin ceramic package provide the input control circuitry, the output power stage, and two optical channels. The input Buffer IC is designed on a bipolar process, while the output Detector IC is manufacVLED1+ During powerup, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the ACPL-516x's output low. Once the output is in the high state, the DESAT (VCE) detection feature of the ACPL-516x provides IGBT protection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection. 8 13 INPUT IC VCC1 Under normal operation, the input gate control signal directly controls the IGBT gate through the isolated output detector IC. LED2 remains off and a fault latch in the input buffer IC is disabled. When an IGBT fault is detected, the output detector IC immediately begins a "soft" shutdown sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive overvoltages. Simultaneously, this fault status is transmitted back to the input buffer IC via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. VLED1- 7 VIN+ VIN- tured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal. Both optical channels are completely controlled by the input and output ICs respectively, making the internal isolation boundary transparent to the microcontroller. 12 1 LED1 2 D R I V E R 3 UVLO 11 14 VOUT DESAT DESAT 9,10 SHIELD LED2 RESET FAULT VCC2 VC 16 5 FAULT 6 SHIELD 4 GND1 OUTPUT IC 15 VLED2+ 3 HCPL-316J functional diagram VEE VE Package Pin Out 1 VIN+ VE 16 2 VIN- VLED2+ 15 3 VCC1 DESAT 14 4 GND1 VCC2 13 5 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1- VEE 9 Pin Descriptions Symbol Description Symbol VIN+ Noninverting gate drive voltage output (VOUT ) VE control input. Description Common (IGBT emitter) output supply voltage. VIN- Inverting gate drive voltage output VLED2+ (VOUT ) control input. LED 2 anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only.) VCC1 Positive input supply voltage. (4.5 V to 5.5 V) DESAT HCPL-316J Pkg Pinout Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 7 V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 s. See Note 25. GND1 Input Ground. Positive output supply voltage. RESET FAULT reset input. A logic low input for at least VC 0.1 s, asynchronously resets FAULT output high and enables VIN. Synchronous control of RESET relative to VIN is required. RESET is not affected by UVLO. Asserting RESET while VOUT is high does not affect VOUT. Collector of output pull-up triple-darlington transistor. It is connected to VCC2 directly or through a resistor to limit output turn-on current. FAULT Fault output. FAULT changes from a high impedance state to a logic low output within 5 s of the voltage on the DESAT pin exceeding an internal reference voltage of 7 V. FAULT output remains low until RESET is brought low. FAULT output is an open collector which allows the FAULT outputs from all ACPL-516x in a circuit to be connected together in a "wired OR" forming a single fault bus for interfacing directly to the microcontroller. Gate drive voltage output. VLED1+ LED 1 anode. This pin must be left unconnected VEE Output supply voltage. for guaranteed data sheet performance. (For optical coupling testing only.) VLED1- LED 1 cathode. This pin must be connected to ground. 4 VCC2 VOUT Selection Guide: Lead Configuration Options Avago Technologies Part Number and Options Commercial Grade ACPL-5160 MIL-PRF-38534, Class H ACPL-5161 Standard Lead Finish Gold Plate Solder Dipped* Option -200 Gull Wing/Soldered* Option -300 SMD Part Number Gold Plate 5962-1223601HEC Solder Dipped* 5962-1223601HEA Gull Wing/Soldered* 5962-1223601HXA *Solder contains lead Outline Drawings 0.89 (0.035) 1.65 (0.065) 20.06 (0.790) 20.83 (0.820) 8.13 (0.320) MAX. 4.45 (0.175) MAX. 0.51 (0.020) MIN. 3.81 (0.150) MIN. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MAX. Note: Dimensions in millimeters (inches) Device Marking Avago LOGO Avago P/N DLA SMD [1] DLA SMD [1] PIN ONE/ ESD IDENT A QYYWWZ XXXXXXXXXX XXXXXXXXXX XXXXX XXX A 50434 Note 1. Qualified parts only 5 COMPLIANCE INDICATOR, [1] DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Avago CAGE CODE [1] 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) Hermetic Optocoupler Options Option Description 200 Lead finish is solder dipped rather than gold plated. This option is available on standard commercial. DLA Drawing part numbers contain provisions for lead finish. 300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on standard commercial. This option has solder dipped leads. 4.57 (0.180) MAX. 0.51 (0.020) MIN. 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) Note: Dimensions in millimeters (inches) 4.57 (0.180) MAX. 0.51 (0.020) MIN. 1.40 (0.055) 1.65 (0.065) 4.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 5 MAX. 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 1.07 (0.042) 1.32 (0.052) 9.65 (0.380) 9.91 (0.390) Solder contains lead. Absolute Maximum Ratings Parameter Symbol Min. Max. Units C Note Storage Temperature Ts -65 150 Operating Temperature TA -55 125 Output IC Junction Temperature TJ 1501 Peak Output Current |Io(peak)| 2.5 A Fault Output Current IFAULT8.0 mA Positive Input Supply Voltage VCC1 -0.5 5.5 Input Pin Voltages VIN+, VIN- and VRESET -0.5 VCC1 Total Output Supply Voltage (VCC2 - VEE) -0.5 35 Negative Output Supply Voltage (VE - VEE) -0.5 15 3 Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE) Gate Drive Output Voltage Vo(peak) -0.5 VCC2 Collector Voltage VC VEE + 5 V VCC2 DESAT Voltage VDESAT VE VE + 10 Output IC Power Dissipation PO Input IC Power Dissipation PI150 Recommended Operating Conditions Parameter Symbol Min. 600 Max. 2 V mW Units 1 Note Operating Temperature TA -55 +125 Input Supply Voltage VCC1 4.5 5.5 Total Output Supply Voltage (VCC2 - VEE) 15 30 Negative Output Supply Voltage (VE - VEE) 0 15 3 Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE) Collector Voltage VC VEE + 6 VCC2 6 C V 25 6 Electrical Specifications (DC) Unless otherwise noted, all typical values at TA = 25C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter SymbolMin.Typ.Max. Units Logic Low Input Voltages VIN+L, VIN-L,0.8 VRESETL V Logic High Input Voltages VIN+H, VIN-H, 2.0 VRESETH Logic Low Input Currents IIN+L, IIN-L, IRESETL -0.5 -0.36 FAULT Logic Low Output Current IFAULTL 5.0 12 VFAULT = 0.4 V FAULT Logic High Output Current IFAULTH -40A VFAULT = VCC1 31 High Level Output Current IOH -0.5 VOUT = VCC2 - 4 V 3, 8, 32 -1.5 mA A Test Conditions VIN = 0.4 V -2.0 VOUT = VCC2 - 15 V Low Level Output Current 0.5 IOL Fig.Note 2.0 VOUT = VEE + 2.5 V 30 4 2 2.0 VOUT = VEE + 15 V 4, 9, 33 Low Level Output Current During Fault Condition IOLF 90 150 230 mA VOUT - VEE = 14 V 5, 34 5 High Level Output Voltage VOH VC - 3.5 VC - 2.5 VC - 1.5 V IOUT = -100 mA 6, 7, 8 VC -2.9 VC - 2.0 VC - 1.2 6, 8, 35 Low Level Output Voltage VOL 0.12 0.5 IOUT = 100 mA 7, 9, 36 23 High Level Input Supply ICC1H 18 22 mA VIN+ = VCC1 = 5.5 V, Current VIN- = 0 V 10, 37 38 IOUT = -650 A 4 2 VCIOUT = 0 Low Level Input Supply ICCIL 6.5 11 VIN+ = VIN- = 0 V, Current VCC1 = 5.5 V Output Supply Current ICC2 2.8 5 VOUT open 11, 12, 8 39, 40 Low Level Collector Current ICL 0.3 1.0 IOUT = 0 15, 59 24 High Level Collector Current ICH 0.3 1.3 IOUT = 0 15, 58 24 1.2 3.0 IOUT = -650 A 15, 57 VE Low Level Supply Current IEL -0.7 -0.43 0 14, 61 VE High Level Supply Current IEH -0.5 -0.16 0 14, 40 22 Blanking Capacitor ICHG -0.13 -0.26 -0.33 VDESAT = 0 - 6 V Charging Current -0.18 -0.26 -0.33 VDESAT = 0 - 6 V, TA = 25C - 125 C 13, 41 8, 9 Blanking Capacitor IDSCHG 10 37VDESAT = 7 V Discharge Current 42 UVLO Threshold 43 12.4 13.5 VUVLO- 11.2 12.4 VOUT < 5 V 6, 8, 11 UVLO Hysteresis (VUVLO+ VUVLO-) 0.4 1.2 DESAT Threshold VDESAT 6.5 7.0 7.5 VCC2 - VE > VUVLO- 8 7 VUVLO+ 11.6 V VOUT > 5 V 16, 44 6, 8, 10 Switching Specifications (AC) Unless otherwise noted, all typical values at TA = 25 C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note 12 VIN to High Level Output tPLH 0.10 0.28 0.50 s 152Propagation Delay Time Rg = 10 Cg = 10 nF, 17,18,19, 20,21,22, VIN to Low Level Output tPHL 0.10 0.29 0.50 Propagation Delay Time f = 10 kHz, Duty Cycle = 50% 45,54,55 Pulse Width Distortion PWD -0.30 0.01 Propagation Delay Difference Between Any Two Parts (tPHL - tPLH) PDD -0.35 10% to 90% Rise Time tr 90% to 10% Fall Time tf0.1 0.30 13, 14 0.35 14, 15 0.1 45 Rg = 10 , Cg = 10 nF DESAT Sense to 90% VOUT Delay tDESAT(90%) 0.18 0.5 23,56 16 DESAT Sense to 10% VOUT Delay tDESAT(10%) 1.9 3.0 VCC2 - VEE = 30 V 24,28, 46,56 DESAT Sense to Low Level FAULT tDESAT(FAULT) 1.5 5 Signal Delay 25,47, 56 17 DESAT Sense to DESAT Low Propagation Delay 56 18 26,27, 56 19 49 10 tDESAT(LOW) 0.25 RESET to High Level FAULT Signal tRESET(FAULT) 3 6.5 20 Delay RESET Signal Pulse Width PWRESET 0.1 UVLO to VOUT High Delay tUVLO ON 4.0 VCC2 = 1.0 ms UVLO to VOUT Low Delay tUVLO OFF 6.0 ramp11 Output High Level Common Mode |CMH| 9 15 kV/s Transient Immunity TA = 25 C, VCM = 1000 V, VCC2 = 30 V Output Low Level Common Mode |CML| 9 15 Transient Immunity TA = 25 C, 21 VCM = 1000 V, VCC2 = 30 V 50,51, 52,53 20 Package Characteristics Over recommended operating conditions (TA = -55 to +125 C) unless otherwise specified. Parameter Symbol Test Conditions Input-Output Leakage Current II-O VI-O = 1500 Vdc, RH 65%, t = 5 sec., TA = 25 C Resistance (Input-Output) RI-O VI-O = 500 VDC Capacitance (Input-Output) CI-O f = 1 MHz Group A Subgroups Limits Min. Typ.* 1 Units Note Max. 1.0 A 26, 27 1012 27 2.8 pF 27 *All typicals at TA = 25 C. 8 Fig Notes: 1. To achieve the absolute maximum power dissipation specified, pins 4, 9 and 10 require ground plane connections and may require airflow. For details on how to estimate junction temperature and power dissipation, see the Thermal Model section in the application notes at the end of this data sheet . The actual power dissipation achievable will depend on the application environment (PCB layout, air flow, part placement, and so on). No power derating is required when operating below 125 C using a high conductivity board. If a low conductivity board is used, then output IC power dissipation is derated linearly at 20 mW/C above 120 C. Input IC power dissipation is derated linearly at 5 mW/C above 120C. 2. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. For additional details on IOH peak, see the Applications section . Derate linearly from 3.0 A at +25 C to 2.5 A at +125 C. This compensates for increased IOPEAK due to changes in VOL over temperature. 3. This supply is optional. Required only when negative gate drive is implemented. 4. Maximum pulse width = 50 s, maximum duty cycle = 0.5%. 5. For further details, see the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet. 6. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a DC load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero units. 7. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 8. Once VOUT of the ACPL-516x is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the ACPL-516x will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Therefore, the DESAT detection and UVLO features of the ACPL-516x work in conjunction to ensure constant IGBT protection. 9. For further details, see the Blanking Time Control section in the applications notes at the end of this data sheet. 10. This is the `increasing' (that is, turn-on or `positive going' direction) of VCC2 - VE. 11. This is the `decreasing' (that is, turn-off or `negative going' direction) of VCC2 - VE. 12. This load condition approximates the gate load of a 1200 V/75 A IGBT. 13. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit. 14. As measured from VIN+, VIN- to VOUT. 15. The difference between tPHL and tPLH between any two ACPL-516x parts under the same test conditions. 16. Supply Voltage Dependent. 17. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. 18. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. 19. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 s is the guaranteed minimum FAULT signal pulse width when the ACPL-516x is configured for Auto-Reset. For further details, see the Auto-Reset section in the applications notes at the end of this data sheet. 20. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3 k pull-up resistor is needed in fault detection mode. 21. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (that is, VO < 1.0 V or FAULT < 0.8 V). 22. Does not include LED2 current during fault or blanking capacitor discharge current. 23. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 A while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pulldown resistor is not used. 24. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE. 25. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down. 26. This is a momentary withstand test, not an operating condition. 27. Device considered a two-terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 9 Performance Plots 7 IOL - OUTPUT LOW CURRENT - A 1.8 1.6 1.4 1.2 1.0 - 55 - 25 5 35 65 TA - TEMPERATURE - o C 95 Figure 3. IOH vs. temperature IOLF- LOW LEVEL OUTPUT CURRENT DURING FAULT CONDITION - mA 175 150 125 100 -55 oC 25 oC 125 oC 75 50 25 0 5 V OUT 10 15 20 - OUTPUT VOLTAGE - V 25 30 VOUT = VEE +15 V VOUT = VEE + 2.5 V 3 2 1 - 25 5 35 65 TA - TEMPERATURE - o C 95 125 0 95 125 IOUT = -650 A IOUT = -100 mA -1 -2 -3 -4 -55 - 25 5 35 65 TA - TEMPERATURE - o C 29.2 IOUT = 100 mA VOH - OUTPUT HIGH VOLTAGE -V VOL- OUTPUT LOW VOLTAGE - V 0.25 0.20 0.15 0.10 0.05 - 55 - 25 5 35 65 TA - TEMPERATURE - o C Figure 7. VOL vs. temperature 10 4 Figure 6. VOH vs. temperature Figure 5. IOLF vs. temperature 0.00 5 Figure 4. IOL vs. temperature 200 0 6 0 - 55 125 (V OH - VCC ) - HIGH OUTPUT VOLTAGE DROP -V I OH - OUTPUT HIGH CURRENT - A 2.0 95 125 125 oC 25 oC -55 oC 28.8 28.4 28.0 27.6 27.2 26.8 26.4 0.0 0.2 Figure 8. VOH vs. IOH 0.4 0.6 0.8 IOH - OUTPUT HIGH CURRENT - A 1.0 20 125 oC 25 oC -55 oC 4 I CC1 - SUPPLY CURRENT - mA VOL - OUTPUT LOW VOLTAGE - V 5 3 2 1 0 0.0 0.5 1.0 1.5 IOL - OUTPUT LOW CURRENT - A 2.0 Figure 9: VOL vs. IOL 3.0 I CC2 - SUPPLY CURRENT - mA I CC2 - SUPPLY CURRENT - mA - 25 5 35 65 95 TA - TEMPERATURE - o C 125 ICC2H ICC2L 2.80 2.7 2.6 2.75 2.5 2.4 2.70 2.3 - 25 5 35 65 TA - TEMPERATURE - o C 95 2.65 15 125 Figure 11: ICC2 vs. t emperature 0.00 -0.05 I E- V E SUPPLY CURRENT - mA -0.20 -0.25 -0.30 -55 20 25 VCC2 - OUTPUT SUPPLY VOLTAGE - V -25 5 35 65 TA - TEMPERATURE Figure 13. ICHG vs. temperature 30 Figure 12. ICC2 vs. VCC2 -0.15 I CHG - BLANKING CAPACITOR CHARGING CURRENT -mA 5 2.85 2.8 2.2 - 55 11 10 Figure 10. ICC1 vs. temperature ICC2H ICC2L 2.9 15 0 - 55 2.5 ICC1H ICC1L oC 95 125 IeH IeL -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -0.45 -0.50 -55 -25 5 35 65 TA - TEMPERATURE - o C Figure 14. IE vs. temperature 95 125 4 VDESAT DESAT THRESHOLD - V 3 I C - mA 7.5 -55 oC 25 oC 125 oC 7.0 2 6.5 1 0 0.5 1.0 I OUT - mA 1.5 6.0 - 55 2.0 Figure 15. IC vs. IOUT PROPAGATION DELAY - s PROPAGATION DELAY - s 0.40 0.35 0.30 0.25 - 55 - 25 5 35 65 TA - TEMPERATURE - o C 95 0.30 0.25 15 20 25 VCC - SUPPLY VOLTAGE -V 30 Figure 18. Propagation delay vs. supply voltage 0.45 0.45 Vcc1 = 5.5 V Vcc1 = 5.0 V Vcc1 = 4.5 V 0.40 PROPAGATION DELAY - s PROPAGATION DELAY - s 125 Tphl Tplh 0.35 0.20 125 Figure 17. Propagation delay vs. temperature 0.35 0.30 0.25 - 55 - 25 5 35 65 TA - TEMPERATURE - o C 95 Figure 19. VIN to high propagation delay vs. temperature (TPLH) 12 95 0.40 Tphl Tplh 0.45 0.20 5 35 65 TA - TEMPERATURE - o C Figure 16. DESAT threshold vs. temperature 0.50 0.20 - 25 125 Vcc1 = 5.5 V Vcc1 = 5.0 V Vcc1 = 4.5 V 0.4 0.35 0.3 0.25 0.2 - 55 - 25 5 35 65 TA - TEMPERATURE - o C 95 Figure 20. VIN to low propagation delay vs. temperature (TPHL) 125 0.40 0.40 Tplh Tphl 0.35 DELAY - s DELAY - s 0.35 0.30 0.30 0.25 0.25 0.20 Tplh Tphl 0 20 40 60 LOAD CAPACITANCE - nF 80 0.20 100 Figure 21. Propagation delay vs. load capacitance 0 10 20 30 LOAD RESISTANCE - OHM 50 Figure 22. Propagation delay vs. load resistance 3.0 0.45 Vcc2=30 V Vcc2=15 V 0.4 2.5 DELAY - s 0.35 DELAY - s 40 0.3 0.25 0.2 2.0 1.5 0.15 0.1 - 55 - 25 5 35 65 TA - TEMPERATURE - o C 95 Figure 23. DESAT sense to 90% Vout delay vs. temperature 2.6 VEE= VEE= VEE= VEE= 2.4 - 25 5 35 65 TA - TEMPERATURE - o C 95 125 Figure 24. DESAT sense to 10% Vout delay vs. temperature 0.008 0V -5 V -10 V -15 V Vcc2=30 V Vcc2=15 V 0.006 DELAY - ms DELAY - s 2.2 1.0 - 55 125 2.0 1.8 1.6 0.004 0.002 1.4 1.2 - 55 - 25 5 35 65 TA - TEMPERATURE - o C 95 125 Figure 25. DESAT sense to low level fault signal delay vs. temperature 13 0 0 10 20 30 LOAD CAPACITANCE - nF 40 Figure 26. DESAT sense to 10% Vout delay vs. load capacitance 50 0.0030 12 Vcc2 = 30 V Vcc2 = 15 V 10 DELAY - s DELAY - s 0.0025 0.0020 0.0015 0.0010 8 6 10 20 30 LOAD RESISTANCE - OHM 40 Figure 27. DESAT sense to 10% Vout delay vs. load resistance 14 Vcc1 = 5.5 V Vcc1 = 5.0 V Vcc1 = 4.5 V 50 4 - 55 - 25 5 35 65 TA - TEMPERATURE - o C 95 Figure 28. RESET to high level fault signal delay vs. temperature 125 Test Circuit Diagrams IFAULT VIN- VLED2+ VCC1 GND1 VIN+ VE VIN- VLED2+ DESAT VCC1 DESAT VCC2 GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE 0.1 F 0.1 F 10 mA + - 5V 5V IFAULT Figure 30. IFAULTL test circuit. 0.1 F VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE 0.1 F 30 V 0.1 F 15 V PULSED + - IOUT + - 30 V 0.1 F Figure 32. IOH pulsed test circuit. VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE + - 15 VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE Figure 34. IOLF test circuit. VEE VLED1- VEE 0.1 F 30 V 0.1 F 0.1 F + - IOUT 15 V PULSED 30 V + - HCPL-316J fig 33 0.1 F + - 5V VIN+ VOUT VLED1+ Figure 33. IOL pulsed test circuit. HCPL-316J fig 32 0.1 F FAULT HCPL-316J fig 31 VIN+ + - + - VC Figure 31. IFAULTH test circuit. HCPL-316J fig 30 5V RESET 5V 30 V 0.1 F + - IOUT + - 14 V 0.1 F 30 V + - 0.1 F VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE Figure 35. VOH pulsed test circuit. 0.1 F + - - + VE + - 0.4 V + - VIN+ + - 4.5 V 0.1 F 30 V 0.1 F + - VOUT 2A PULSED 0.1 F 30 V VIN- 0.1 F VLED2+ VCC1 DESAT GND1 VCC2 FAULT VOUT VLED1+ VEE VLED1- VEE + - ICC1 0.1 F 100 mA VC RESET 5.5 V 30 V 0.1 F + - VOUT 30 V 0.1 F Figure 36. VOL test circuit. VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE 0.1 F ICC1 HCPL-316J fig 37 VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 0.1 F 5V + - VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC RESET VC FAULT VOUT FAULT VOUT VLED1+ VEE VLED1+ VEE VLED1- VEE VLED1- VEE Figure 38. ICC1L test circuit. VIN- VE VLED2+ VCC1 DESAT GND1 VCC2 RESET 0.1 F 0.1 F 5V 30 V ICC2 0.1 F VC + - + - VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT FAULT VOUT VLED1+ VEE VLED1+ VEE VLED1- VEE VLED1- VEE Figure 40. ICC2L test circuit. 30 V ICC2 0.1 F 0.1 F + - 30 V HCPL-316J fig 39 + - VIN+ 0.1 F Figure 39. ICC2H test circuit. HCPL-316J fig 38 16 VIN- 0.1 F 30 V Figure 41. ICHG pulsed test circuit. ICHG 0.1 F + - + - VE Figure 37. ICC1H test circuit. HCPL-316J fig 36 5.5 V VIN+ + - + - VE + - 5V VIN+ 0.1 F 30 V 0.1 F 0.1 F + - 30 V VE VLED2+ GND1 VCC2 IDSCHG + - 5V 30 V 0.1 F VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 + - FAULT VOUT VEE VLED1+ VEE VEE VLED1- VEE FAULT VOUT VLED1+ VLED1- 0.1 F 30 V Figure 42. IDSCHG test circuit. VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VLED1- VIN SWEEP 0.1 F 0.1 F 15 V + - VE + - VIN+ + - 0.1 F 0.1 F 5V VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 VC FAULT VOUT VEE VLED1+ VEE VEE VLED1- VEE + - 0.1 F 15 V 3k 3k 17 VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE Figure 46. tDESAT(10%) test circuit. 30 V 0.1 F 0.1 F VOUT 10 + - 30 V 10 nF HCPL-316J fig 45 VIN VOUT 10 10 nF 0.1 F + - 5V + - 0.1 F Figure 45. tPLH, tPHL, tr, tf test circuit. HCPL-316J fig 44 VIN+ 0.1 F HCPL-316J fig 43 VIN+ RESET Figure 44. DESAT threshold test circuit. 0.1 F VOUT Figure 43. UVLO threshold test circuit. HCPL-316J fig 42 10 mA SWEEP + - VC RESET VC RESET 0.1 F 0.1 F 30 V 5V 0.1 F + - + - 0.1 F 3k VFAULT 30 V VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE Figure 47. tDESAT(FAULT) test circuit. VIN 0.1 F 0.1 F 10 10 nF + - DESAT 0.1 F + - VCC1 + - VIN- 7V + - VIN+ 30 V 0.1 F + - 30 V + - 3k VIN HIGH TO LOW VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 FAULT VOUT VLED1+ VEE VLED1- VEE 30 V 0.1 F + - 5V 0.1 F VC RESET VFAULT 0.1 STROBE F 8V + - 5V 0.1 F 0.1 F + - 10 30 V 3k 10 nF Figure 48. tRESET(FAULT) test circuit. 1 5V 1 VIN+ VE 16 2 VIN- VLED2+ 15 3 VCC1 DESAT 14 4 GND1 VCC2 13 5 RESET VC 12 0.1 F 100 pF VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE 25 V 0.1 F SCOPE 100 pF 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1 VEE 9 10 5V 0.1 F HCPL-316J fig 49 16 VLED2+ 15 2 VIN- 3 VCC1 DESAT 14 4 GND1 VCC2 13 5 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1 VEE 9 25 V 0.1 F 10 10 nF 9V VCm Figure 51. CMR test circuit, LED2 on. HCPL-316J fig 50 VE 16 2 VIN- VLED2+ 15 3 VCC1 DESAT 14 GND1 VCC2 4 10 nF 750 10 nF Figure 50. CMR test circuit, LED2 off. VIN+ RAMP 10 VE VIN+ VCm 1 0.1 F VOUT 3 k 3 k SCOPE VLED2+ + - 0.1 F VE VIN- Figure 49. UVLO delay test circuit. HCPL-316J fig 48 5V VIN+ 1 5V 0.1 F 25 V 0.1 F 13 VIN+ VE 16 2 VIN- HCPL-316J fig 51 VLED2+ 15 3 VCC1 DESAT 14 4 GND1 VCC2 13 5 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1 VEE 9 3 k 3 k 5 RESET VC 12 6 FAULT VOUT 11 25 V 0.1 F SCOPE 100 pF 7 VLED1+ VEE 10 8 VLED1 VEE 9 10 10 nF 100 pF VCm VCm Figure 52. CMR test circuit, LED1 off. 18 Figure 53. CMR test circuit, LED1 on. SCOPE 10 10 nF VINVIN- 2.5 V 0V VIN+ VIN+ 2.5 V 2.5 V 5.0 V 2.5 V tr tf tr 90% 50% 50% 10% VOUT tPLH tf 90% 10% VOUT tPHL tPLH Figure 54. VOUT propagation delay waveforms, noninverting configuration. tPHL Figure 55. VOUT propagation delay waveforms, inverting configuration. tDESAT (FAULT) HCPL-316J fig 54 tDESAT (10%) HCPL-316J fig 55 tDESAT (LOW) 7V VDESAT 50% tDESAT (90%) VOUT 90% 10% FAULT 50% (2.5 V) tRESET (FAULT) RESET Figure 56. Desat, VOUT, fault, reset delay waveforms. 19 50% VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VLED1- 0.1 F 5V + - 0.1 F 30 V 0.1 F IC VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VEE VLED1+ VEE VEE VLED1- VEE + - 0.1 F 650 A 30 V Figure 57. ICH test circuit. VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 VC 0.1 F 5V + - 30 V 0.1 F IC + - VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VOUT VLED1+ VEE VLED1+ VEE VLED1- VEE VLED1- VEE 0.1 F 30 V Figure 59. ICL test circuit. Figure 60. IEH test circuit. HCPL-316J fig 60 HCPL-316J fig 59 VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE IE 0.1 F + - + - Figure 61. IEL test circuit. 20 0.1 F FAULT 5V 0.1 F IC + - 0.1 F 30 V HCPL-316J fig 58 + - VIN+ 0.1 F 30 V Figure 58. ICH test circuit. HCPL-316J fig 57 RESET 0.1 F 30 V 0.1 F 0.1 F + - 30 V IE 0.1 F + - 0.1 F + - + - + - 5V 30 V 0.1 F 0.1 F + - 30 V Typical Application/Operation Introduction to Fault Detection and Protection The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are potentially destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply short circuits due to user misconnect or bad wiring, control signal failures due to noise or computational errors, overload conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions, the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become damaged when the current load approaches the saturation current of the device, and the collector to emitter voltage rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turnoff the overcurrents during a fault condition. A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required components, board space consumed, cost, and complexity have until now limited its use to high performance drives. The features which this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. Applications Information The ACPL-516x satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and an optically isolated fault status feedback signal into a single 16pin DIP package. The fault detection method, which is adopted in the ACPL-516x, is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach 21 destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false `fault' signals. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-516x limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly conservative overcurrent threshold is not needed to protect the IGBT. Recommended Application Circuit The ACPL-516x has both inverting and noninverting gate control inputs, an active low reset input, and an open collector fault output suitable for wired `OR' applications. The recommended application circuit shown in Figure 62 illustrates a typical gate drive implementation using the ACPL-516x. The four supply bypass capacitors (0.1 F) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5 mA) power supply suffices. The desat diode and 100 pF capacitor are the necessary external components for the fault detection circuitry. The gate resistor (10 ) serves to limit gate charge current and indirectly control the IGBT collector voltage rise and fall times. The open collector fault output has a passive 3.3 k pullup resistor and a 330 pF filtering capacitor. A 47 k pulldown resistor on VOUT provides a more predictable high level output voltage (VOH). In this application, the IGBT gate driver will shut down when a fault is detected and will not resume switching until the microcontroller applies a reset signal. ACPL-516x C 5V + - 3.3 k 0.1 F 330 pF VE 16 VIN- VLED2+ 15 VCC1 DESAT 14 4 GND1 VCC2 13 5 RESET VC 12 VCC2 = 18 V + - 6 FAULT VOUT 11 Rg 7 VLED1+ VEE 10 8 VLED1- VEE 9 1 VIN+ 2 3 0.1 F 0.1 F 100 pF 100 DDESAT + 47 k 0.1 F + - VF - VEE = -5 V Q1 + VCE - Q2 3-PHASE OUTPUT + VCE - Figure 62. Recommended application circuit. Description of Operation/Timing Fault Condition Figure 63 illustrates input and output waveforms under the conditions of normal operation, a desat fault condition, and normal reset behavior. When the voltage on the DESAT pin exceeds 7 V while the IGBT is on, VOUT is slowly brought low in order to "softly" turn-off the IGBT and prevent large di/dt induced voltages. Also activated is an internal feedback channel which brings the FAULT output low for the purpose of notifying the micro-controller of the fault condition. See Figure 63. Normal Operation During normal operation, VOUT of the ACPL-516x is controlled by either VIN+ or VIN-, with the IGBT collector-toemitter voltage being monitored through DDESAT. The FAULT output is high and the RESET input should be held high. See Figure 63. NORMAL OPERATION VINNON-INVERTING CONFIGURED INPUTS INVERTING CONFIGURED INPUTS FAULT CONDITION 0V 5V VIN+ VIN- 5V VIN+ 5V VDESAT 7V VOUT FAULT RESET Figure 63. Timing diagram. HCPL-316J fig 63 22 Reset The FAULT output remains low until RESET is brought low. See Figure 63. While asserting the RESET pin (LOW), the input pins must be asserted for an output low state (VIN+ is LOW or VIN- is HIGH). This may be accomplished either by software control (i.e. of the microcontroller) or hardware control (see Figures 73 and 74). RESET Slow IGBT Gate Discharge During Fault Condition Under Voltage Lockout When a desaturation fault is detected, a weak pull-down device in the ACPL-516x output drive stage will turn on to `softly' turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below VEE + 2 V, at which time the large pull down device clamps the IGBT gate to VEE. The ACPL-516x Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the ACPL-516x output low during power-up. IGBTs typically require gate voltages of 15 V to achieve their rated VCE(ON) voltage. At gate voltages below 13 V typically, their on-voltage increases dramatically, especially at higher currents. At very low gate voltages (below 10 V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever insufficient operating supply (VCC2) is applied. Once VCC2 exceeds VUVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. As VCC2 is increased from 0 V (at some level below VUVLO+), first the DESAT protection circuitry becomes active. As VCC2 is further increased (above VUVLO+), the UVLO clamp is released. Before the time the UVLO clamp is released, the DESAT protection is already active. Therefore, the UVLO and DESAT FAULT DETECTION features work together to provide seamless protection regardless of supply voltage (VCC2). DESAT Fault Detection Blanking Time The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor. The nominal blanking time is calculated in terms of external capacitance (CBLANK), FAULT threshold voltage (VDESAT ), and DESAT charge current (ICHG) as tBLANK = CBLANK x VDESAT / ICHG. The nominal blanking time with the recommended 100 pF capacitor is 100 pF * 7 V / 250 A = 2.8 sec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time also represents the longest time it will take for the ACPL-516x to respond to a DESAT fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after approximately 3 sec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. The recommended 100 pF capacitor should provide adequate blanking as well as fault response times for most applications. 23 Behavioral Circuit Schematic Output IC The functional behavior of the ACPL-516x is represented by the logic diagram in Figure 64 which fully describes the interaction and sequence of internal and external signals in the ACPL-516x. Three internal signals control the state of the driver output: the state of the signal LED, as well as the UVLO and Fault signals. If no fault on the IGBT collector is detected, and the supply voltage is above the UVLO threshold, the LED signal will control the driver output state. The driver stage logic includes an interlock to ensure that the pull-up and pull-down devices in the output stage are never on at the same time. If an undervoltage condition is detected, the output will be actively pulled low by the 50x DMOS device, regardless of the LED state. If an IGBT desaturation fault is detected while the signal LED is on, the Fault signal will latch in the high state. The triple darlington AND the 50x DMOS device are disabled, and a smaller 1x DMOS pulldown device is activated to slowly discharge the IGBT gate. When the output drops below 2 V, the 50x DMOS device again turns on, clamping the IGBT gate firmly to Vee. The Fault signal remains latched in the high state until the signal LED turns off. Input IC In the normal switching mode, no output fault has been detected, and the low state of the fault latch allows the input signals to control the signal LED. The fault output is in the opencollector state, and the state of the Reset pin does not affect the control of the IGBT gate. When a fault is detected, the FAULT output and signal input are both latched. The fault output changes to an active low state, and the signal LED is forced off (output LOW). The latched condition will persist until the Reset pin is pulled low. 250 A DESAT (14) + VIN+ (1) VIN- (2) - LED VCC1 (3) GND (4) VE (16) UVLO DELAY VCC2 (13) - + 12 V VC (12) FAULT FAULT (6) 7V Q R VOUT (11) S RESET (5) 50 x FAULT VEE (9,10) 1x Figure 64. Behavioral circuit schematic. 24 ACPL-516x 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT 7 VLED1+ 8 VLED1- ACPL-516x ACPL-516x VE 16 VE 16 VLED2+ 15 VLED2+ 15 DESAT 14 DESAT 14 VCC2 13 VCC2 13 VC 12 VC 12 VOUT 11 VOUT 11 VEE 10 VEE 10 VEE 9 VEE 9 Rg RPULL-DOWN Figure 65. Output pull-down resistor. 100 pF C 100 Rg Figure 66. DESAT pin protection. DDESAT 3.3 k + - 330 pF Figure 67. FAULT pin CMR protection. Other Recommended Components Capacitor on FAULT Pin for High CMR The application circuit in Figure 62 includes an output pull-down resistor, a DESAT pin protection resistor, a FAULT pin capacitor (330 pF), and a FAULT pin pull-up resistor. Rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. A 330 pF capacitor (Fig. 66) should be connected between the fault pin and ground to achieve adequate CMOS noise margins at the specified CMR value of 15 kV/s. The added capacitance does not increase the fault output delay when a desaturation condition is detected. Output Pull-Down Resistor During the output high transition, the output voltage rapidly rises to within 3 diode drops of VCC2. If the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly VCC2-3(VBE) to VCC2 within a period of several microseconds. To limit the output voltage to VCC2-3(VBE), a pull-down resistor between the output and VEE is recommended to sink a static current of several 650 A while the output is high. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, Rpull-down = [VCC2-3 * (VBE)] / 650 A. DESAT Pin Protection The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substantial current out of the IC if protection is not used. To limit this current to levels that will not damage the IC, a 100 ohm resistor should be inserted in series with the DESAT diode. The added resistance will not alter the DESAT threshold or the DESAT blanking time. 25 Pull-up Resistor on FAULT Pin The FAULT pin is an open-collector output and therefore requires a pull-up resistor to provide a high-level signal. Driving with Standard CMOS/TTL for High CMR Capacitive coupling from the isolated high voltage circuitry to the input referred circuitry is the primary CMR limitation. This coupling must be accounted for to achieve high CMR performance. The input pins VIN+ and VIN- must have active drive signals to prevent unwanted switching of the output under extreme common mode transient conditions. Input drive circuits that use pull-up or pull-down resistors, such as open collector configurations, should be avoided. Standard CMOS or TTL drive circuits are recommended. User-Configuration of the ACPL-516x Input Side The VIN+, VIN-, FAULT and RESET input pins make a wide variety of gate control and fault configurations possible, depending on the motor drive requirements. The ACPL516x has both inverting and noninverting gate control inputs, an open collector fault output suitable for wired `OR' applications and an active low reset input. ACPL-516x 1 VIN+ 2 VIN- 3 VCC1 4 GND1 Driving Input pf ACPL-516x in NonInverting/Inverting Mode 5 RESET 6 FAULT The Gate Drive Voltage Output of the ACPL-516x can be configured as inverting or noninverting using the VIN- and VIN+ inputs. As shown in Figure 68, when a noninverting configuration is desired, VIN- is held low by connecting it to GND1 and VIN+ is toggled. As shown in Figure 69, when an inverting configuration is desired, VIN+ is held high by connecting it to VCC1 and VIN- is toggled. 7 VLED1+ 8 VLED1- + - C Figure 68. Typical input configuration, noninverting. HCPL-316J fig 68 Local Shutdown, Local Reset As shown in Figure 70, the fault output of each ACPL516x gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition. ACPL-516x + - C Global-Shutdown, Global Reset As shown in Figure 71, when configured for inverting operation, the ACPL-516x can be configured to shutdown automatically in the event of a fault condition by tying the FAULT output to VIN+. For high reliability drives, the open collector FAULT outputs of each ACPL-516x can be wire `OR'ed together on a common fault bus, forming a single fault bus for interfacing directly to the micro-controller. When any of the six gate drivers detects a fault, the fault output signal will disable all six ACPL-516x gate drivers simultaneously and thereby provide protection against further catastrophic failures. 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT 7 VLED1+ 8 VLED1- Figure 69. Typical Input Configuration, Inverting. HCPL-316J fig 69 ACPL-516x C + - 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT 7 VLED1+ 8 VLED1- Figure 70. Local shutdown, local reset configuration. 26 Auto-Reset Resetting Following a Fault Condition As shown in Figure 72, when the inverting VIN- input is connected to ground (noninverting configuration), the ACPL-516x can be configured to reset automatically by connecting RESET to VIN+. In this case, the gate control signal is applied to the noninverting input as well as the reset input to reset the fault latch every switching cycle. During normal operation of the IGBT, asserting the reset input low has no effect. Following a fault condition, the gate driver remains in the latched fault state until the gate control signal changes to the `gate low' state and resets the fault latch. If the gate control signal is a continuous PWM signal, the fault latch will always be reset by the next time the input signal goes high. This configuration protects the IGBT on a cyclebycycle basis and automatically resets before the next `on' cycle. The fault outputs can be wire `OR'ed together to alert the microcontroller, but this signal would not be used for control purposes in this (AutoReset) configuration. When the ACPL 516x is configured for AutoReset, the guaranteed minimum FAULT signal pulse width is 3 s. To resume normal switching operation following a fault condition (FAULT output low), the RESET pin must first be asserted low in order to release the internal fault latch and reset the FAULT output (high). Prior to asserting the RESET pin low, the input (VIN) switching signals must be configured for an output (VOL) low state. This can be handled directly by the microcontroller or by hardwiring to synchronize the RESET signal with the appropriate input signal. Figure 73a shows how to connect the RESET to the VIN+ signal for safe automatic reset in the noninverting input configuration. Figure 73b shows how to configure the VIN+/RESET signals so that a RESET signal from the microcontroller causes the input to be in the "output-off" state. Similarly, Figures 73c and 73d show automatic RESET and microcontroller RESET safe configurations for the inverting input configuration. ACPL-516x ACPL-516x + - C CONNECT TO OTHER RESETS 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT 7 VLED1+ 8 VLED1- + - C CONNECT TO OTHER FAULTS 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT 7 VLED1+ 8 VLED1- Figure 72. Auto-reset configuration. Figure 71. Global-shutdown, global reset configuration. HCPL-316J fig 71 1 VIN+ 2 VIN- VCC ACPL-516x 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT VCC 3 VCC1 C C VIN+/ RESET FAULT 4 GND1 5 RESET RESET 6 FAULT FAULT 7 VLED1+ 7 VLED1+ 8 VLED1- 8 VLED1- Figure 73a. Safe hardware reset for noninverting input configuration (automatically resets for every VIN+ input). 27 ACPL-516x VIN+ Figure 73b. Safe hardware reset for noninverting input configuration. User-Configuration of the ACPL-516x Output Side RG and Optional Resistor RC: The value of the gate resistor RG (along with VCC2 and VEE) determines the maximum amount of gate-charging/discharging current (ION,PEAK and IOFF,PEAK) and thus should be carefully chosen to match the size of the IGBT being driven. Often it is desirable to have the peak gate charge current be somewhat less than the peak discharge current (ION,PEAK < IOFF,PEAK). For this condition, an optional resistor (RC) can be used along with RG to independently determine ION,PEAK and IOFF,PEAK without using a steering diode. As an example, refer to Figure 74. Assuming that RG is already determined and that the design IOH,PEAK = 0.5 A, the value of RC can be estimated in the following way: RC + RG = [VCC2 - VOH - (VEE)] IOH,PEAK = [4 V - (-5 V)] 0.5 A = 18 RC = 8 See "Power and Layout Considerations" section for more information on calculating value of RG. ACPL-516x VCC 1 VIN+ VIN- VIN- VIN- 2 VCC 3 ACPL-516x VCC 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT VCC VCC1 C C GND1 4 RESET RESET FAULT 5 RESET 6 FAULT 7 VLED1+ 7 VLED1+ 8 VLED1- 8 VLED1- FAULT Figure 73c. Safe hardware reset for inverting input configuration. HCPL-316J fig 73c HCPL-316J fig 73d ACPL-516x VE 16 VLED2+ 15 DESAT 14 VCC2 13 VC 12 VOUT 11 VEE 10 VEE 9 100 pF RC 8 10 10 nF 15 V Figure 74. Use of RC to further limit ION,PEAK. 28 Figure 73d. Safe hardware reset for inverting input configuration (automatically resets for every VIN- input). -5 V Higher Output Current Using an External Current Buffer: DESAT Diode and DESAT Threshold To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 75) may be used. Inverting types are not compatible with the desatura-tion fault protection circuitry and should be avoided. To preserve the slow IGBT turnoff feature during a fault condition, a 10 nF capacitor should be connected from the buffer input to VEE and a 10 W resistor inserted between the output and the common npn/pnp base. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8A maximum. The D44VH10/ D45VH10 pair is appropriate for currents up to 15 A maximum. ACPL-516x VE 16 VLED2+ 15 DESAT 14 VCC2 13 VC 12 VOUT 11 VEE 10 VEE 9 100 pF MJD44H11 or D44VH10 4.5 10 2.5 10 nF MJD45H11 or D45VH10 15 V The DESAT diode's function is to conduct forward current, allowing sensing of the IGBT's saturated collectorto-emitter voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the short period of time when the IGBT is switching, there is commonly a very high dVCE/dt voltage ramp rate across the IGBT's collector-to-emitter. This results in ICHARGE (= CD-DESAT x dVCE/dt) charging current which will charge the blanking capacitor, CBLANK. In order to minimize this charging current and avoid false DESAT triggering, it is best to use fast response diodes. Listed in the below table are fast-recovery diodes that are suitable for use as a DESAT diode (DDESAT ). In the recommended application circuit shown in Figure 62, the voltage on pin 14 (DESAT) is VDESAT = VF + VCE, (where VF is the forward ON voltage of DDESAT and VCE is the IGBT collector-toemitter voltage). The value of VCE which triggers DESAT to signal a FAULT condition, is nominally 7V - VF. If desired, this DESAT threshold voltage can be decreased by using multiple DESAT diodes in series. If n is the number of DESAT diodes then the nominal threshold value becomes VCE,FAULT(TH) = 7 V - n x VF. In the case of using two diodes instead of one, diodes with half of the total required maximum reverse-voltage rating may be chosen. -5 V Figure 75. Current buffer for increased drive current. Part Number Manufacturer trr (ns) Max. Reverse Voltage Rating, VRRM (V)Package Type MUR1100E Motorola 75 1000 59-04 (axial leaded) MURS160T3 Motorola 75 600 Case 403A (surface mount) UF4007 General Semi. 75 1000 DO-204AL (axial leaded) BYM26E Philips 75 1000 SOD64 (axial leaded) BYV26E Philips 75 1000 SOD57 (axial leaded) BYV99 Philips 75 600 SOD87 (surface mount) Power/Layout Considerations Operating Within the Maximum Allowable Power Ratings (Adjusting Value of RG): When choosing the value of RG, it is important to confirm that the power dissipation of the ACPL-516x is within the maximum allowable power rating. The steps for doing this are: 1. Calculate the minimum desired RG; 29 2. Calculate total power dissipation in the part referring to Figure 77. (Average switching energy supplied to ACPL-516x per cycle vs. RG plot); 3. Compare the input and output power dissipation calculated in step #2 to the maximum recommended dissipation for the ACPL-516x. (If the maximum recommended level has been exceeded, it may be necessary to raise the value of RG to lower the switching power and repeat step #2.) As an example, the total input and output power dissipation can be calculated given the following conditions: * ION, MAX ~ 2.0 A * VCC2 = 18 V * VEE = -5 V * fCARRIER = 15 kHz Step 1: Calculate RG minimum from IOL peak specification: To find the peak charging lOL assume that the gate is initially charged the steadystate value of VEE. Therefore apply the following relationship: [VOH@650 A - (VOL+VEE)] RG = -------------------- IOL,PEAK [VCC2 - 1 - (VOL + VEE )] = ------------------ IOL,PEAK PO(BIAS) = steadystate power dissipation in the ACPL516x due to biasing the device. PO(SWITCH) = transient power dissipation in the ACPL516x due to charging and discharging power device gate. ESWITCH = Average Energy dissipated in ACPL-516x due to switching of the power device over one switching cycle (J/cycle). fSWITCH = average carrier signal frequency. For RG = 10.5, the value read from Figure 77 is ESWITCH = 6.05 J. Assume a worstcase average ICC1 = 16.5 mA (which is given by the average of ICC1H and ICC1L ). Similarly the average ICC2 = 5.5 mA. PI = 16.5 mA * 5.5 V = 90.8 mW PO = PO(BIAS) + PO,SWITCH = 5.5 mA * (18 V - (-5 V)) + 6.051 J * 15 kHz 18 V - 1 V - (1.5 V + (5 V)) = -------------------- 2.0 A = 126.5 mW + 90.8 mW = 217.3 mW = 10.25 W 10.5 W (for a 1% resistor) (Note from Figure 76 that the real value of IOL may vary from the value calculated from the simple model shown.) Step 2: Calculate total power dissipation in the ACPL-516x: The ACPL-516x total power dissipation (PT ) is equal to the sum of the inputside power (PI) and outputside power (PO): PT = PI + PO PI = ICC1 * VCC1 PO = PO(BIAS) + PO,SWTICH = ICC2 * (VCC2-VEE ) + ESWITCH * fSWITCH where, 4 Step 3: Compare the calculated power dissipation with the absolute maximum values for the ACPL-516x: For the example, PI = 90.8 mW < 150 mW (abs. max.) ) OK PO = 217.3 mW < 600 mW (abs. max.) ) OK Therefore, the power dissipation absolute maximum rating has not been exceeded for the example. For an explanation on how to calculate the maximum junction temperature of the ACPL-516x for a given PC board layout configuration, refer to the following Thermal Model section. MAX. ION, IOFF vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V SWITCHING ENERGY vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V 9 8 3 7 1 6 IOFF (MAX.) 0 -1 ION (MAX.) Ess (Qg = 650 nC) 4 3 1 0 20 40 60 80 100 120 140 160 180 200 Rg () Figure 76. Typical peak ION and IOFF currents vs. Rg (for ACPL-516x output driving an IGBT rated at 600 V/100 A. HCPL-316J fig 76 30 5 2 -2 -3 Ess (J) ION, IOFF (A) 2 0 0 50 100 150 200 Rg () Figure 77. Switching energy plot for calculating average Pswitch (for ACPL-516x output driving an IGBT rated at 600 V/100 A). HCPL-316J fig 77 Thermal Model R11, R12, R13, R14, R21, R22, R23, R24, R31, R32, R33, R34, R41, R42, R43, R44: Thermal Resistances in C/W R11: Thermal Resistance of LED1 due to heating of LED1. R12: Thermal Resistance of LED1 due to heating of INPUT IC. R13: Thermal Resistance of LED1 due to heating of LED2 R14: Thermal Resistance of LED1 due to heating of OUTPUT IC R21: Thermal Resistance of INPUT IC due to heating of LED1. R22: Thermal Resistance of INPUT IC due to heating of INPUT IC. R23: Thermal Resistance of INPUT IC due to heating of LED2 R24: Thermal Resistance of INPUT IC due to heating of OUTPUT IC R31: Thermal Resistance of LED2 due to heating of LED1 R32: Thermal Resistance of LED2 due to heating of INPUT IC R33: Thermal Resistance of LED2 due to heating of LED2 R34: Thermal Resistance of LED2 due to heating of OUTPUT IC R41: Thermal Resistance of OUTPUT IC due to heating of LED1 R42: Thermal Resistance of OUTPUT IC due to heating of INPUT IC R42: Thermal Resistance of OUTPUT IC due to heating of LED2 R42: Thermal Resistance of OUTPUT IC due to heating of OUTPUT IC Description This thermal model assumes that the ACPL-516x optocoupler is mounted onto a 76.2 mm x 76.2 mm low and high conductivity printed circuit board (PCB) per JEDEC standard. The PCB boards are made of FR-4 material and the thickness of the copper traces is per JEDEC standards for low/high conductivity board. The ACPL-516x is a hybrid device with four die: an input LED1, an input buffer IC, an output feedback LED2, and an output detector IC. The temperature at the LEDs and the ICs of the optocoupler can be calculated by using the following equations: T1A = R11P1 + R12P2+ R13P3+ R14P4 T2A = R21P1 + R22P2+ R23P3+ R24P4 T3A = R31P1 + R32P2+ R33P3+ R34P4 T4A = R41P1 + R42P2 + R43P3+ R44P4 where: T1A = Temperature difference between ambient and LED1 T2A = Temperature difference between ambient and INPUT IC T3A = Temperature difference between ambient and LED2 T4A = Temperature difference between ambient and OUTPUT IC P1 = Power dissipation from LED1 P2 = Power dissipation from INPUT IC P3 = Power dissipation from LED2 P4 = Power dissipation from OUTPUT IC 31 Thermal Coefficient Data (units in C/W) High Conductivity Board R11 R12 R13 R24 R21 R22 R23 R24 R31 R32 R33 R34 R41 R42 R43 R44 111 26 28 26 24 66 30 23 23 29 79 25 27 26 26 35 Low Conductivity Board R11 R12 R13 R24 R21 R22 R23 R24 R31 R32 R33 R34 R41 R42 R43 R44 125 37 41 32 41 70 47 30 36 38 93 28 41 35 40 38 Junction Temperature Calculation Assume maximum power dissipation, Pmax(buffer) = 0.15 W, Pmax(detector)= 0.6 W, P(LED) ~ 0.02 W. If the ambient temperature is 125 C, the calculated junction temperature for a high conductivity board is: T2 = (R21 x P1 + R22 x P2 + R23 x P3 + R24 x P4) + Ta = (24 x 0.02 + 66 x 0.15 + 30 x 0.02 + 23 x 0.6 ) + 125 ~ 150 C T4 = (R41 x P1 + R42 x P2 + R43 x P3 + R44 x P4 ) + Ta = (27 x 0.02 + 26 x 0.15 + 26 x 0.02 + 35 x 0.6) + 125 ~ 150 C The junction temperatures of the input and output IC is ~ 150 C when operating at 125 C. No power derating is required when operating below 125 C using a high conductivity board. If low conductivity board is used, the calculated junction temperature is: T2 = (R21 x P1 + R22 x P2 + R23 x P3 + R24 x P4 ) + Ta = (41 x 0.02 + 70 x 0.15 + 47 x 0.02 + 30 x 0.6 ) + 125 ~ 155 C T4 = (R41 x P1 + R42 x P2 + R43 x P3 + R44 x P4 ) + Ta = (41 x 0.02 + 35 x 0.15 + 40 x 0.02 + 38 x 0.6) + 125 ~ 155 C The junction temperatures of the input and output IC exceeded the abs. max. junction temperature of 150 C. Power derating is required so that the junction temperatures do not exceed 150 C. Output IC power dissipation is derated linearly at 20 mW/C above 120 C. Input IC power dissipation is derated linearly at 5 mW/C above 120 C. 32 System Considerations Propagation Delay Difference (PDD) The ACPL-516x includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 62) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails, a potentially catastrophic condition that must be prevented. Delaying the ACPL-516x turn-on signals by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 79. The maximum dead time for the ACPL-516x is 800 ns (= 400 ns - (-400 ns)) over an operating temperature range of -55 C to 125 C. To minimize dead time in a given design, the turn-on of the ACPL-516x driving Q2 should be delayed (relative to the turn-off of the ACPL-516x driving Q1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 78. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 400 ns over the operating temperature range of 55 C to 125 C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. VIN+1 VOUT1 Q1 ON Q1 OFF Q2 ON VOUT2 Q2 OFF VIN+1 VIN+2 VOUT1 tPHLMIN tPHLMAX Q1 ON Q1 OFF tPLHMIN tPLHMAX Q2 ON VOUT2 VIN+2 Q2 OFF (tPHL-tPLH)MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHLMAX - tPHLMIN) + (tPLHMAX - tPLHMIN) = (tPHLMAX - tPLHMIN) - (tPHLMIN - tPLHMAX) = PDD*MAX - PDD*MIN tPHLMAX tPLHMIN PDD* MAX = (tPHL - tPLH)MAX = tPHLMAX - tPLHMIN *PDD = PROPAGATION DELAY NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 78. Minimum LED Skew for Zero Dead Time. For product information and a complete list of distributors, please go to our website: = PDD*MAX *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 79. Waveforms for Dead Time Calculation. www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright (c) 2005-2013 Avago Technologies. All rights reserved. AV02-3964EN - May 1, 2013 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Avago Technologies: ACPL-5160-200 ACPL-5160 ACPL-5161-200 5962-1223601HEA 5962-1223601HEC 5962-1223601HXA ACPL5161-300 ACPL-5161 ACPL-5160-300