GP4020/IG/GQ1N - Zarlink Semiconductor, Inc.

Ordering Information

GP4020/IG/GQ1N (trays)

GP4020/IG/GQ1Q (tape and reel, 1000 units per reel)

The GP4020 is available in a 100 pin PQFP package in

Industrial (-40°C to +85°C) grade. The ordering code is

standard for screened devices

Description

The GP4020 is a complete digital baseband processor

for a Global Positioning System (GPS) receiver. It

combines the 12-channel correlator function of the

GP2021 with an advanced ARM7TDMI (Thumb)

microprocessor to achieve a higher level of integration,

reduced system cost, reduced power consumption and

added functionality. The GP4020 complements the

GP2015 and GP2010 C/A code RF downconverters

available from Zarlink Semiconductor.

The correlator section contains 12 identical tracking

module blocks, one for each channel. Each channel

contains all the components necessary for acquiring

and tracking the received signal, and also contains

other functional blocks, which are used to produce part

of the measurement data set. Individual channels may

be deactivated for systems not requiring full 12-channel

operation and thus allowing for reduced power

consumption and processor loading.

The microprocessor section contains the Firefly MF1

microcontroller core, which includes an ARM7TDMI

with a Thumb instruction de-compressor plus the Firefly

BµILD module. Also included are a second UART,

BµILD Serial I/O, General I/O and Watchdog functions.

GP4020

GPS Receiver Baseband Processor

DS5134 ISSUE 4.4 May 2002

Features

• Complete GPS correlator and Firefly MF1

microcontroller core

• ARM 7TDMITM (Thumb®) Microprocessor, with JTAG

ICEBreakerTM Debug Interface

• Fully Configurable External Data Bus

• 12 Fully Independent Correlation Channels

• Low Voltage Operation: 3·3V

• Low Current Power–Down Mode

• 1PPS UTC Aligned Timing Output

• Dual UART

• 3-wire BµILD Serial Input/Output (BSIO) Interface

• 8 General Purpose Input/Output (GPIO) Lines

• Boot ROM, allowing Software Upload via UART

• 8K Bytes Internal SRAM

• Compatible with GP2015 and GP2010 RF Front Ends

Applications

•GPS Navigation Systems

•GPS Geodetic Receivers

•Time Transfer Receivers

•Automatic Vehicle Location (AVL)

•E911 Emergency Positioning

GP2015

GP2010

DS4374

DS4056

GPS Receiver RF Front End

(TQFP 48 package)

GPS Receiver RF Front End

(PQFP 44 package)

Part Description Data sheet

Related Products

Absolute Maximum Ratings

-0·5V to +5·0V

+7·0V max.

GND-0·5V to VDD+0·5V

-55°C to + 150°C

2kV

Supply voltage (V DD) from ground (GND)

Bias for 5V inputs

Input voltage (any input pin)

Output voltage (any output pin)

Storage temperature

Static discharge (HBM)*

*Mil Std 883 Human Body Model = discharge from 100pF through

1500Ω between any 2 pins

Manufactured under licence from ARM Ltd

ARM and the ARM logo are trademarks of Advanced RISC Machines Ltd

GP4020

Figure 1 - Block diagram

PLLAT1

PR_XIN

PR_XOUT

CLK_I

CLK_T

SAMPCLK

MAG0

SIGN0

RF_PLL_LOCK

IEXTINT2

TIMEMARK/TIC

PERIPHERAL

CONTROL

LOGIC

GPIO

BSIO

GPIO[7:0]

POWER_GOOD

NRESET

GPIO[7:0]

DISCIO

MULTI_FNIO

BµILD_CLK

NRESET

REAL

TIME

CLOCK

PLL

SYSTEM

CLOCK

GENERATOR

RTC_CLK

UART_CLK

NPOR_RESET

NRESET

12-CHANNEL

GPS

CORRELATOR

M_CLK

RAW

TIMEMARK

M_CLK

TIC

WDOG

ARM7

TDMI

MICRO

UART2

UART_CLK

DMAC

U2RXD

U2TXD

UART1

TIC

INTC

PER_INT

MEAS_INT

ACCUM_INT

1PPS

TIMEMARK

GENERATOR

SSM

JTAG

INTERFACE

SSM BDIAG/XPIN IO

BµILD BUS

SDATA[15:0]

SADD[19:0]

FIREFLY

MF1 CORE

MPC

UIM

BOOT

ROM

512316

SRAM

2K332

(6ns)

UIM BUS

U1RXD

U1TXD

NICE

NTRST

TMS

TDO

TDI

TCK

SWAIT

NOSE

NSUB

NSWE[1:0]

NCSC[2:0]

SDATA[15:0]

SADD[19:0]

GP4020

RTC_XIN

RTC_XOUT

NPOR_

RESET

GP4020

Figure 2 - Pin connections (top view)

125

100

QPA100

Pin No. Signal Name Type Associated Description Notes

circuit block

1 SADD[0] I/O MPC System Address bit 0

2 SADD[1] I/O MPC System Address bit 1

3 SADD[2] I/O MPC System Address bit 2

4 SADD[3] I/O MPC System Address bit 3

5 SADD[4] I/O MPC System Address bit 4

6 SADD[5] I/O MPC System Address bit 5

7 GNDPWR

8 SADD[6] I/O MPC System Address bit 6

9 SADD[7] I/O MPC System Address bit 7

10 VDD PWR

11 NSCS[0] I/O MPC System Chip Select 0 - Active Low 1

12 NSCS[1] O MPC System Chip Select 1 - Active Low 1

13 NSCS[2A] O MPC System Chip Select 2A - Active Low 1

14 SADD[19] O MPC System Address bit 19

15 SDATA[0] I/O MPC System Data bit 01

16 SDATA[1] I/O MPC System Data bit 11

17 SDATA[2] I/O MPC System Data bit 21

18 SDATA[3] I/O MPC System Data bit 31

19 GNDPWR

20 SDATA[4] I/O MPC System Data bit 41

21 SDATA[5] I/O MPC System Data bit 51

22 VDD PWR

23 SDATA[6] I/O MPC System Data bit 61

Cont…

Table 1 - Pin descriptions

All VDD and GND pins must be connected to ensure reliable operation. Any unused input pins must be tied either

high or low; no inputs should be left unconnected.

GP4020

Pin No. Signal Name Type Associated Description Notes

circuit block

24 SDATA[7] I/O MPC System Data bit 7 1

25 NSOE I/O MPC System Output Enable, active low 1

26 NSWE[1] I/O MPC System Write Enable bit 1, active low 1

27 NSWE[0] I/O MPC System Write Enable bit 0, active low 1

28 SDATA[8] I/O MPC System Data bit 8 1

29 SDATA[9] I/O MPC System Data bit 9 1

30 VDD PWR

31 SDATA[10] I/O MPC System Data bit 10 1

32 SDATA[11] I/O MPC System Data bit 11 1

33 GND PWR

34 SDATA[12] I/O MPC System Data bit 12 1

35 SDATA[13] I/O MPC System Data bit 13 1

36 SDATA[14] I/O MPC System Data bit 14 1

37 SDATA[15] I/O MPC System Data bit 15 1

38 SADD[18] I/O MPC System Address bit 18

39 SADD[17] I/O MPC System Address bit 17

40 SADD[16] I/O MPC System Address bit 16

41 GND PWR

42 SADD[15] I/O MPC System Address bit 15

43 SADD[14] I/O MPC System Address bit 14

44 VDD PWR

45 SADD[13] I/O MPC System Address bit 13

46 SADD[12] I/O MPC System Address bit 12

47 SADD[11] I/O MPC System Address bit 11

48 SADD[10] I/O MPC System Address bit 10

49 SADD[9] I/O MPC System Address bit 9

50 SADD[8] I/O MPC System Address bit 8

51 SWAIT I MPC System Wait input - allows

wait-states to be inserted into the

current Firefly clock cycle.

52 NSUB O MPC System Upper Byte, active low. 1,2

53 IEXTINT2 I INTC Interrupt source 2 input

(for external interrupts).

54 MULTI_FNIO I/O PCL Multi-function Input / Output. Used to set

Boot Up ROM area, and source either

100kHz square wave or System Clock.

55 DISCIO I/O PCL Discrete Input / Output. 3

Used either as input or to source

RF_Power_Down control signal or TIC.

56 RF_PLL_LOCK I INTC /PCL PLL Lock Indicator input from RF section.

When high this signal indicates that the

PLL within the RF section is in lock and

the master-clock inputs have stabilised.

57 A1VDD PWR SCG VDD Supply for CLK_T & CLK_I input

block in the System Clock Generator. This

pin should be well decoupled to pin 60

(GND) to ensure optimum noise immunity

58 CLK_T I SCG Master Clock Input from RF front end 4

40MHz 100mV rms.

59 CLK_I I SCG Inverted Master Clock Input from RF 4

front end: 40MHz 100mV rms.

Cont…

Table 1 - Pin descriptions (continued)

GP4020

Sampled Sign (polarity) data from RF front end.

Sampled Mag (amplitude) data from RF front

end.

Sample Clock output to the RF front end. Provides

a 5·714MHz clock with a 4:3 mark to space ratio.

Power Monitor input, high for normal operation;

low forces the GP4020 into Power Down mode.

System Clock Oscillator - crystal output for 10 to

16MHz crystal.

System Clock Oscillator - crystal inputfor 10 to

16MHz crystal.

TEST select pin,used with TESTMODE (pin 74).

Used for test purposes only and should be

connected to GND in normal operation.

Timemark output. This pin can be used to produce

a UTC-aligned 1 PPS output, or TIC output.

TEST select pin,used with TESTMODE (pin 74).

Used for test purposes only and should be

connected to GND in normal operation.

Real-time Clock Oscillator input for 32kHz crystal.

Real-time Clock Oscillator output for 32kHz crystal.

TEST select pin,used with TEST (pin 67). Used

for test purposes only and should be connected

to GND in normal operation.

System Reset input.

UART 2 Transmit data output.

UART 2 Receive data input.

UART 1 Transmit data output.

UART 1 Receive data input.

GND connection for PLL Block.

VDD connection for PLL Block.

System Clock Generator PLL Analog Test I/O.

Reserved for TEST purposes only and should

NOT be connected in normal operation.

ARM7 operating mode and JTAG / SSM Signal

Multiplex (pins 86, 87, 88, 89).

JTAG Test Clock/SSM Diagnostic broadcast

debug output bdiag[0]/System test control input

XReq.

JTAG Test Data In/SSM Diagnostic broadcast

debug output bdiag[1]/System Test control input

X/Write.

JTAG Test Data Out/SSM Diagnostic broadcast

debug output bdiag[2]/System test control input

XBurst.

Pin No. Signal name Associated

circuit block DescriptionType Notes

GND

SIGN0

MAG0

SAMPCLK

POWER_GOOD

PR_XOUT

PR_XIN

TEST

VDD

TIMEMARK / TIC

IDDQTEST

GND

RTC_XIN

RTC_XOUT

TESTMODE

NSRESET

U2TXD

U2RXD

U1TXD

U1RXD

PLLGND

PLLVDD

GND

PLLAT1

NICE

VDD

TCK/bdiag[0]/XReq

TDI/bdiag[1]/XWrite

TDO/bdiag[2]/XBurst

Table 1 - Pin descriptions (continued) Cont…

PWR

I/O

CORR

PCL

SCG

1PPS

RTC

PCL

UART2

UART1

SCGPLL

JTAG/SSM

MUTIPLEX

JTAG/SSM

GP4020

Pin No. Signal name NotesType Associated

circuit block Description

JTAG Test Mode Select/SSM Diagnostic

broadcast debug output bdiag[3]/System test

control input XCon.

JTAG interface Reset or SSM debug interface

multiplex (pins 86, 87, 88 and 89).

General Purpose Input/Output 7. Can be

multiplexed to SCG PLL Digital Test Output

(PLLDT1).

General Purpose Input/Output 6.

General Purpose Input/Output 5. Can be

multiplexed to DISCOP discrete output from

correlator.

General Purpose Input/Output 4. Also directly

connects to DISCIP1 on the 12-channel correlator.

General Purpose Input/Output 3. Can be

multiplexed to BSIO Slave Select[1].

General Purpose Input/Output 2. Can be

multiplexed to BSIO Slave Select[0].

General Purpose Input/Output 1. Can be

multiplexed to BSIO Data Input/Output.

General Purpose Input/Output pin 0. Can be

multiplexed to BSIO_CLK output.

TMS/bdiag[3]/XCon

NTRST

GPI0[7]/PLLDT1

GPIO[6]

GPIO[5]/DISCOP

GND

GPIO[4]/DISCIP1

GPIO[3]/BSIO_SS[1]

GPIO[2]/BSIO_SS[0]

VDD

GPIO[1]/BSIO_DATA

GPIO[0]/BSIO_CLK

100

Table 1 - Pin descriptions (continued)

I/O

PWR

I/O

PWR

I/O

JTAG/SSM

GPIO/SCG PLL

GPIO

GPIO/CORR

GPIO/BSIO

NOTES

1. High impedance is achieved on pins 11 to 18, 20, 21, 23 to 29, 31, 32, 34 to 37 when either:

(a) Data is not being written from GP4020.

(b) POWER_GOOD (pin 64) is low.

(d) Bit 10 (RF_SLEEP) of POW_CNTL register is high.

2. NSUB (pin 52) is the Upper Byte select output from the Memory Peripheral Controller, when single chip 16-bit

memories with NUB and NLB inputs are used. NSUB maps to NUB and address line SADD[0] to NLB.

3. Input is tolerant to being driven with a +5V HIGH level, as well as +3·3V HIGH nominal level.

4. Both CLK_T (pin 58) and CLK_I (pin 59) should not have an external DC bias of GREATER than +1·7V . Direct

connection from a GP2010/GP2015 RF front end is NOT possible, without bias-shift circuit (Figure 3).

5. TEST (pin 67) and TESTMODE (pin 74) are used together to set up manufacturing test modes for the GP4020,

as shown in Table 2 (0 = GND, 1 = VDD).

Table 2 - Test mode truth table

Details of ALL test modes are covered in section 2.10 of the Zarlink Semiconductor Firefly MF1 Core Design

Manual.

TEST

(pin 67)

TESTMODE

(pin 74)

Test function

Normal operation

Firefly Macrocell test mode

Firefly System test mode

UIM logic test mode

GP4020

NOTES (continued):

6. NICE (pin 84) and NRST (pin 90) control a number of operation modes and a debug on signal multiplex on pins

86 to 90 as follows:

NICE = low ARM7TDMI in ICE mode.

ARM7TDMI will not access memory unless instructed by the JTAG interface. NTRST

(pin 90) set Low will reset the JTAG.

NICE = High ARM7TDMI in Normal mode.

ARM7TDMI does not effect the reset on the JTAG inteface. However, a reset of Firefly

will also reset the JTAG.

NTRST (pin 90) has a reset and signal-multiplex function, dependent on the state of NICE (pin 84):

(i) NICE = Low:

JTAG debug signals connected to pins 86, 87, 88, 89 & 90, as follows:

Pin 86 = TCK = JTAG clock in

Pin 87 = TDI = JTAG data in

Pin 88 = TDO = JTAG data out

Pin 89 = TMS = JTAG mode select in

Pin 90 = NTRST = Active low reset to JTAG interface

(JTAG interface also reset when Firefly MF1 is reset)

(ii) NICE = High and NTRST = High:

Normal mode of operation for GP4020. System Services Module Broadcast Diagnostic debug output

signals connected to pins 86, 87, 88, 89 as follows:

Pin 86 = bdiag[0]

Pin 87 = bdiag[1]

Pin 88 = bdiag[2]

Pin 89 = bdiag[3]

Diagnostic mode must have been set-up using the Diagnostic Configuration Registers within Firefly MF1.

Refer to Section 8 of Firefly MF1 Core Design Manual (DM5003), from Zarlink Semiconductor, for more

information.

(iii) NICE = High & NTRST = Low:

Firefly MF1 System Test Control input signals connected to pins 86, 87, 88, 89 as follows:

Pin 86 = Xreq

Pin 87 = XWrite

Pin 88 = Xburst

Pin 89 = XCon

System test inputs are used in Firefly MF1 macrocell test mode for manufacturing test. Refer to Section 2.10

of Firefly MF1 Core Design Manual (DM5003), from Zarlink Semiconductor, for more information.

Glossary:

1PPS 1 Pulse Per Second

ARM® Advanced RISC Machines

ARM7TDMI™ ARM7 microprocessor with Thumb,

Debug, fast Multiplier and ICE Breaker

Extensions

BµILD Bus for µController Integration in Low-

Power Designs

B_CLK BµILD bus system clock

BSIO BµILD Serial Input / Output

CORR 12-channel Correlator

DMAC Direct Memory Access Controller

Firefly MF1 Zarlink Semiconductor

microcontroller cell, based on

ARM7TDMI, DMAC, INTC, MPC,

SYSTIC and UART

GPIO General Purpose Input / Output

GPS Global Positioning System

ICE In Circuit Emulation

INTC Interrupt Controller

MPC Memory Peripheral Controller

PCL Peripheral Control Logic

PLL Phase Locked Loop

RAM Random Access Memory

ROM Read Only Memory

RTC Real Time Clock

SCG System Clock Generator

SSM System Services Module

SYSTIC System Timer / Counter module

TIC Timer / Counter

UART Universal Asynchronous Receiver/

Transmitter

UIM Up-Integration Module

WDOG Watchdog

GP4020

Figure 3 - Block diagram of a typical GP4020-based GPS receiver

STATIC

RAM

(16-BIT)

FLASH

EPROM

(16-BIT)

SERIAL COMMS PORT 1

SERIAL COMMS PORT 2

GPIO / BSIO

FIREFLY MF1

MICROCONTROLLER

SYSTEM

SERVICES

TIMER/

COUNTER (32)

DMA

CONTROLLER

INTERRUPT

CONTROLLER

MEMORY

PERIPHERAL

CONTROLLER

UART 1

ICE

NICE

JTAG INTERFACE

ARMTDMI

13·3V

22k

8473

10p

10M

32kHz

CRYSTAL

10p

REAL TIME CLOCK

RTC_

XIN RTC_

XOUT

SYSTEM CLOCK

GENERATOR

WITH PLL

CLK_T

CLK_I

NSRESET

RF_PLL_LOCK

POWER_GOOD

SIGN0

MAG0

RAW_TIMEMARK

RESET

LOGIC

12-CHANNEL

CORRELATOR

SAMPCLK

WATCHDOG UART 2

BSIO 3-WIRE

SERIAL

INTERFACE

GENERAL

PURPOSE I/O

(8 LINES)

1 PPS

GENERATOR

SRAM

(2K332)

BOOT ROM

BµILD_

CLK

M_CLK

1 PULSE PER SECOND

13·3V

22k

10n

470

OPCLK1

OPCLK2

PRESET

SIGN

MAG

CLK

GP2015

10MHz

TCXO

1575MHz

FILTER

TEST

IDDQTEST

13·3V

2·7k

3·3k

10n

1·5V

ANTENNA

175MHz

FILTER

PREF

35MHz

SAW

FILTER

GP4020

Typical GPS Receiver

Figure 3 shows a typical GPS receiver employing a

GP2015 RF front end and a GP4020 correlator.

The RF section, GP2015, performs down conversion of

the L1 (1575·42MHz) signal for digital baseband

processing. The resultant signal is then correlated in the

GPS correlator within the GP4020 with an internally

generated replica of the satellite PRN code to be received.

Individual codes for each channel may be selected

independently to enable acquisition and tracking of up

to 12 different satellites simultaneously.

The results of the correlations form the accumulated

data and are transferred to the microprocessor to give

the broadcast satellite data (the Navigation Message)

and to control the software signal tracking.

Device Description

The GP4020 is a complete baseband processor for

Navstar GPS C/A code signals. It incorporates a 12-

channel GPS correlator, a Zarlink Firefly MF1

microcontroller core (incorporating the ARM7TDMI

Thumb microprocessor), Real Time Clock, 8KBytes of

on-chip SRAM and a boot ROM. The GP4020 uses a

fully configurable memory interface, allowing the use of

16-bit external memory. A block diagram of the GP4020

is shown in Figure 1.

The GP4020 GPS Baseband processor features:

• Firefly MF1 Core including ARM7TDMI

Microprocessor

• 12-channel Navstar GPS C/A code correlator

• 1KByte Onboard Boot ROM

• 8KByte Onboard SRAM

• 8-bit General Purpose I/O

• Debugging Serial Access Ports - JTAG or SSM

• System Timer / Counters

• Real Time Clock

• BSIO: 3-wire serial interface

• Watchdog

• 1Pulse-Per-Second output, with 25ns resolution

• Flexible system Clock Generator - can use clock

source from a crystal or from RF front end TCXO

ARM Processor (ARM7TDMI)

The ARM7TDMI is a 32-bit RISC microprocessor core

series 7 microprocessor core, with the following functional

extensions:

• Thumb (16-bit) instruction set

• Debug interface using J-TAG

• Fast Multiplier

• Embedded In-Circuit Emulation capability

The ARM7TDMI is object code compatible with all

earlier ARM6 and ARM7 based products. The

ARM7TDMI is a fully static design and as such

consumes dynamic power only when clocked.

Boot ROM

The GP4020 BOOT ROM contains code which is executed

every time there is a complete system reset (i.e. when main

power has been removed from the GP4020).

The code installed on the BOOT ROM, allows the

GP4020 to undertake either of 2 functions after a

complete reset:

• Run External Flash EPROM from the EPROM base

address.

• Load into the internal SRAM a unique program via

the UART1 input. This could be used for test

purposes, although the target use of this facility is to

allow for field upgrades of GPS receiver firmware, in

conjunction with a Flash EPROM.

BµILD Bus

This is a modular bus architecture and specification, via

which all on-chip modules communicate with each

other. These modules can either be bus masters or

slaves. A bus master can initiate a bus access, generate

addresses and control read or write transfers. A bus

slave responds to a bus master request when selected

by the system address decoder, and may, if required,

assert a wait signal on the bus until the relevant data

transfer has been completed. All internal data transfers

on the module bus are single cycle. The Firefly MF1

micro-controller has three modules that are capable of

operating as Bus masters. These are the ARM7TDMI

Core, DMAC and SSM, described below.

BµILD Serial Input Output (BSIO)

This module produces a 2-channel 3-wire serial interface

for up to 2 external ‘Slave’ serial interface devices (e.g.

serial EEPROM). It provides both Micro-wire Interface

and Serial Peripheral Interface (SPI) compatibility.

12-Channel Correlator

This module contains 12 channels of PRN code

correlators for spread-spectrum correlation of 12

simultaneous signals. Each channel contains an

independent carrier DCO to allow independent mix

down of a satellite signal to baseband before code

correlation occurs. The correlator is designed to extract

data modulated at a nominal chipping rate of

1·023Mbps, and can be used on both Navstar C/A code

GPS signals and Inmarsat WAAS codes.

GP4020

DMA Controller (DMAC)

Two DMA engines are available on the microcontroller.

These are configured as a pair to provide a memory-to-

memory DMA capability between any 2 locations in the

ARM7TDMI memory space. They may be used

independently for high speed fly-by transfers between

UART1 (or UART2) and either on-chip or off-chip

locations.

Single or multiple byte transfers (Demand or Burst

Mode) are supported and may be word, half word or

byte wide.

Embedded Microcontroller Debug Options

The Firefly MF1 Core incorporates three sophisticated

methods of hardware and software debug. The options

are:

●Embedded ICE, accessed via the ARM7TDMI

JTAG interface (Multi ICE access also possible)

●Angel Debug Monitor

●Logic Analyser coupled with an Inverse Assembler,

accessed via the SSM debug interface

The GP4020 can use any of these options, but special

emphasis has been placed on the Embedded ICE and

Logic Analyser options. The JTAG and SSM debug

interfaces are multiplexed onto the same pins, and can

be selected by setting NICE (pin 84) high for SSM, or

low for JTAG.

Firefly MF1 Microcontroller core

The Firefly MF1 Microcontroller is an Embedded Micro-

controller core developed by Zarlink Semiconductor. It

combines the processing power of the ARM7TDMI

microprocessor with a number of peripheral

components:

• Direct Memory Access Controller (DMAC)

• Interrupt Controller (INTC)

• Memory Peripheral Controller (MPC), incorporating

Up-Integration Module (UIM)

• System Services Module (SSM)

• System Timer/Counter (SYSTIC)

• Universal Asynchronous Receiver / Transmitter

(UART)

Interrupt Controller (INTC)

The ARM7TDMI core accepts two types of interrupt:

Normal (IRQ) and Fast (FIQ). All Interrupts can be

switched between types, depending upon the relative

priorities required. The INTC is the central control logic

that decodes the priority level and handles interrupt

request signals from a total of 8 fixed pre-defined,

internal sources and a number of external sources.

General Purpose Input Output (GPIO)

This module provides 8 I/O pins, which may be bit or byte

addressed and configured in a latched or transparent mode.

External Interrupts can be set for edge or level

sensitivity with a polarity option. To minimise interrupt

latency, there is a hard-wired priority scheme for each

channel for both FIQ and IRQ; alternatively this can be

ignored and the priority assessment handled in

software.

Memory/Peripheral Controller (MPC)

The MPC ensures the correct multiplexing of data is

applied for bus transfers between 8, 16 or 32-bit on-chip

or off-chip peripherals. Four different contiguous memory

areas are available, each with an address range of

1 MByte, with individually programmable wait and stop

state generation. A SWAP function allows memory area

1, which is addressed at system reset, to be switched with

memory area 4. This allows, for example, booting from

ROM and then switching memory area 1 to address

SRAM so that time-critical software and interrupt routines

can operate from fast memory.

Peripheral Control Logic (PCL)

The GP4020 incorporates some specific control logic,

which is used to control a number of functions:

• System Reset Control

• System Power-down, Sleep and Wake-up Control

• System Status and Control Registers

• Signal input/output multiplex control

RAM

The GP4020 contains 8KBytes (configured as

2K332-bit) of high-speed (6ns) Static RAM. This can

be used for either:

• Non-volatile storage of GPS data (Almanac,

Ephemeris, Position and Receiver Clock Offset),

while the receiver power is disabled

• A High-speed Interrupt Service Routine, while the

GP4020 is powered up

The internal SRAM appears at GP4020 Base Address

0x60000000, served by the MPC Memory Area 4. An

MPC SWAP function can swap this memory space with

0x00000000 if required.

GP4020

Since the memory is high-speed, it can be accessed

with Zero wait-states through the Memory Peripheral

Controller. Refer to section on the Memory Peripheral

Controller for more information.

Real Time Clock (RTC)

The GP4020 Real Time Clock uses an external 32kHz

crystal to give an indication of time to the GP4020 chip,

when the device is in Reset / Power Down. If a backup

battery is included in a GPS receiver using the GP4020,

the RTC will continue to operate regardless of the reset

state of the rest of the device.

The RTC is incremental, which means that the number

of seconds from a reset point are accumulated, rather

than a record of Gregorian date.

System Clock Generator (SCG)

The GP4020 System Clock Generator is used to

provide 2 system clocks:

• The M_CLK for the 12-channel Correlator; this is

derived from the CLK_T and CLK_I inputs from the

RF front end device and MUST be 40MHz. This

clock is fundamental to the correlator function, and

must be phase-locked to the RF front end.

•The BµILD_CLK for ALL components on the BµILD

Bus; this can be derived from M_CLK (see above) in

conjunction with a PLL and a divider to generate a

wide range of clock frequencies. In this way, the

BµILD_CLK can be phase-locked to the RF front end.

The clock can also be derived from an independent

crystal source.

System Services Module (SSM)

The System Services Module (SSM) ensures correct

bus operation through a number of modes (reset,

initialisation, debug, etc). It provides diagnostic

broadcast of address and data for internal transfers

along with information about the current operating

mode.

Additionally the SSM System Configuration Register

controls the operating mode of the GP4020.

Specifically the System Services Module performs the

following functions:

• Control the BµILD bus operational mode

• Arbitrate amongst competing resources for BµILD

bus mastership

• Interface to external bus masters and

manufacturing testers

• Control the activities of all BµILD bus modules during

system debug activity.

• Broadcast information about BµILD bus activity for

external diagnostics

• Hold BµILD bus logic levels when no other bus-

master is driving

• Register System Configuration data

System Timer/Counters (SYSTIC)

Two dual independent 32-bit timer/counters, with an 8-

bit pre-scaler capability for each counter, are provided

(Timers 1A, 1B, 2A and 2B). These are synchronous to

the system clock and may be polled, or set-up to

generate interrupts on over-run, with auto-reload.

The TIC functions provided by this module are part of

the Firefly MF1 core. Timer 1 (TIC1) appears at GP4020

Base Address 0xE000 E000, and Timer 2 (TIC2)

appears at Address 0xE000 F000. TIC enable (TEN)

lines are not available externally on this version of the

GP4020, but are tied low on-chip. The TIC functions can

be made available by setting the External enable

polarity bit of the TIC Control/Status register to a logic

‘0’.

Whilst these timer/counters are NOT required by the

GPS function in a GP4020 based GPS receiver, full

programming details of the programming of the System

Timer/Counter can be found in Section 7 of the Firefly

MF1 Core Design Manual.

1PPS Timemark Generator

The GP4020 Timemark generator is used in conjunction

with software to produce a 1 Pulse Per Second (1PPS)

output pulse, which is aligned to Universal

Time Co-ordinated (UTC) to a resolution of 25ns. The

accuracy of time transmitted from the Navstar GPS

space segment is very high, and this can be used to

provide a mobile timing reference to a similar accuracy.

Up Integration Module (UIM)

The Up Integration Module provides a series of internal

connection ports, which mimic the MPC external

interface. This allows the Firefly MF1 to communicate

with the Application Specific Logic used in the GP4020,

as though it was external to the chip, hence it acts as a

transparent interface.

GP4020

Directly-triggered DMA transfers with each UART are

also possible without the need for CPU intervention.

Watchdog (WDOG)

The GP4020 Watchdog can be used to detect hardware

or software run-time errors, and reset the system. The

processor is required to reset the watchdog periodically;

failure to do so will result in a chip-wide reset.

Universal Asynchronous Receive/Transmit

(UART1 and UART2)

The full duplex asynchronous channels of UART1 and

UART2 provide RS232 type interfaces, which support

an XON/XOFF software protocol. The Receive and

Transmit channels are double buffered. The UARTs

may be polled, or may use an interrupt scheme for

module bus transfers. An internal Baud rate generator

in each UART can provide selectable data rates,

derived from on-chip sources for an Rx/Tx pair.

Electrical Characteristics

TAMB = -40°C to +85°C, VDD = +3·0V to +3·6V (+3·3V nominal). The input thresholds and output voltage limits for the

logic signal pins are tested and guaranteed by production test. All other parameters are guaranteed by characterisation

and design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise specified.

Use in conjunction with the GP4020 GPS Baseband Processor Design Manual (DM5280).

Characteristic

Operating voltage range

Battery backup voltage

Supply Current

Full chip

40MHz low level differential input

Processor clock oscillator

Phase locked loop

Real time clock

Firefly MF1 microcontroller

Operating frequency

Output capacitance

Symbol Value

Min. Typ. Max. Units Conditions

Simulated. Firefly BµlLD_CLK =

30MHz, outputs loaded with

50pF, 12 tracking correlator

channels

Enabled

Disabled

Enabled

Disabled

Enabled - FOUT = 30MHz,

Mult Factor = 3

Enabled - FOUT = 60MHz,

Mult Factor = 6

Enabled - FOUT = 1 20MHz,

Mult Factor = 12

Enabled - FOUT = 240MHz,

Mult Factor = 24

Bµild_CLK – external memory

at >1 wait state or internal

memory at 0 wait state.

Bµild_CLK – external memory

access at 0 wait state.

Total external load, all outputs

and I/Os

Cont…

VBATT

IDD

ILLDI

IPRX

IPLL

IRTC

IFMF1

FBµILD

3·0

2·7

<100

2·9

3·4

4·5

6·2

3·27

0·7

3·6

100

4·4

100

0·9

1·0

7·75

31·25

27.5

µA

mA/MHz

MHz

GP4020

Electrical Characteristics (continued)

Characteristic

40MHz Low Level Differential Input

Input voltage bias

Differential input voltage

Input differential hysteresis

Input clock frequency

Input capacitance

Power-on delay

Processor Clock Oscillator

Frequency

Start up time

Mark:space

Transconductance

Output impedance

Feedback resistance

Phase Locked Loop

Input frequency

Output frequency

Duty cycle

Phase alignment offset (falling edges

of CLKINB, CLKFBKB)

Phase Alignment Jitter

Phase Jitter

CLKINB to CLKOUTB delay

PLL Settling Time

Real Time Clock

Crystal frequency

Start up time

Transconductance

Output impedance

Feedback resistance

BµILD Serial Input / Output (BSIO)

3-wire Bus Interface

BSIO_CLK output frequency

Serial clock output low period

Serial clock output high period

Serial clock output rise time

Serial clock output fall time

Serial data output delay

Serial enable output delay

Serial chip select enable to first clock

edge delay

Serial last clock edge delay to chip

select disable

Symbol Value

Min. Typ. Max. Units Conditions

Min. VDD = 3·0V Note 1

40MHz from RF front end

Not including package

Correct external components

Across frequency range

Across all conditions

Can be divided down by 1,2,4 or

8 for optimal BµlLD_CLK freq.

Note 2

Cycle-cycle edge jitter Note 2

In clock bypass mode

In clock synchronisation mode

Correct external components

Across frequency range

External component

SEROUT ref SERCLK

SERSEL ref SERCLK

VDBIAS

VDIFIN

VDIFHYS

FDIFIN

CDIFIN

FPRXIN

TPRXSU

FPLLIN

FPLLOUT

TPLLSET

FRTC

TRTCSTART

GMRTC

ZORTC

RFRTC

FSEROF

TSERCL

TSERCH

TSERCR

TSERCF

TSERDOD

TSEREOD

TSERCDC

TSERCEC

100

1·0

-20

2·24

220

0·43

147

32·768

400

9·56

422

1·715

150

4·4

250

+-0·2

+-0·25

+-0·15

MHz

mA/V

kΩ

MHz

µs

kHz

µA/V

MΩ

MHz

NOTES

1. The input pair CLK_T, CLK_I may be driven by a low amplitude differential sinewave from an RF Front-end.

Direct DC connection to a GP2010 or GP2015 RF front end is NOT possible, as the maximum DC bias from these

devices is in excess of maximum input bias limit.

2. Jitter is dominated by supply-noise effects. Users must keep on-chip supply noise below 1Vp-p by the use of

low noise outputs and as many supply pins as possible.

Cont…

GP4020

Electrical Characteristics (continued)

Characteristic

General Purpose Input/Output (GPIO)

Output delay

Input set-up time

Input hold time

UARTs

Standard Baud rate

Reset logic

Input reset pulse width

Symbol Value

Min. Typ. Max. Units Conditions

GPIO[7:0]

U1/2TXD, U1/2RXD

NSRESET input to cause

reset of whole chip

TGPOD

TGPIS

TGPIH

BDPUS

1·2

100

115·2

kBaud

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application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may

result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under

patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified

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