Rev. 1.3
March 2003 1/102
ST7SCR
8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K
FLA SH, 768 RAM, SMARTCARD I/F, TIMER
■Memories
– Up to 16K of ROM or High Densi ty Flash (HD-
Flash) program memory with read/write pro-
tection, HDFlash In -Circuit and In-Application
Programming . 100 write/erase cycles guaran-
teed, data retention: 20 years at 55°C
– Up to 768 bytes of RAM including up to 128
bytes stack and 256 bytes USB buffer
■Cl ock, Reset and Su pp ly Manag em ent
– Low Voltage Reset
– 2 power saving modes: Halt and Wait modes
– PLL for generating 48 MHz USB c lock us ing a
4 MHz crystal
■Interrupt Management
– Nested Interrupt Controller
■USB (Univers al Serial Bus) Interface
– 256-byte buffer for full speed bulk, control and
interrupt transfer types compliant with USB
specification (version 2.0)
– On-Chip 3.3V USB voltage regulator and
transceivers with soft ware power-down
– 7 USB Endpo ints:
One 8- byte Bidi rectional Control Endpoint
One 64-byte In Endpoint,
One 64-by te Out Endpoint
Four 8-byte In Endpoi nts
■35 or 4 I/O ports:
– Up to 4 LED outputs with software program-
mable consta nt current (3 or 7 mA).
– 2 Gen eral purpose I/Os program mable as in-
terrupts
– Up to 8 line inputs programmable as interrupts
– Up to 20 Outputs
– 1 line ass igned b y defau lt as static input after
reset
■ISO7816-3 UART Interface:
– 4 Mhz Clock generat ion
– Synchronous/Asynchronous protocols (T=0,
T=1)
– Automatic retry on parity er ror
– Programmable Baud rate from 372 clock puls-
es up to 11.625 clock pulses (D=32/F= 372)
– Card Insertion/Removal Detection
■Smartcar d Power S up ply:
– Selectable card VCC 1.8V, 3V, and 5V
– Internal Step-up converter for 5V supplied
Smartcards (with a current of up to 55mA) us-
ing only two external components .
– Programmable Smartcard Internal Voltage
Regulator (1.8V to 3.0V) with current overload
protection and 4 KV ESD protection (Human
Body Model) for all Smartcard Interface I/Os
■One 8-bit Timer
– Time Base Unit (TB U) for generating periodic
interrupts.
■Development Tools
– Full hardware/software dev elopment package
Table 1. De vice Summary
TQFP64 14x14 SO24
Features ST7FSCR1R4 ST7SCR1R4 ST7FSCR1E4 ST7SCR1E4
Program memory 16K FLASH 16K ROM 16K FLASH 16K ROM
User RAM (stack) - bytes 768 (128)
Peripherals USB Full-Speed (7 Ep), TBU, Watchdog timer, ISO7816-3 Interface
Operating Supply 4.0 to 5.5V
Package TQFP64 SO24
CPU Frequency 4 or 8 Mhz
Operating temperature 0°C to +70°C
1
Table of Conten ts
102
2/102
ST7SCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 INTR ODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.3 STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4 ICP (IN-CIRCUIT PROGRAM MING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 IAP (IN-APPLICATION PROG RAMMING) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6 PROGRAM MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3 CPU REG ISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1 CLOC K SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.4 CONCURRENT & NE STED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.5 INTERRUPT REGISTER DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 PO WER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8
8.3 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9
9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2 FUNCTIONAL D ESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12 ON-CHIP PER IPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.2 TIME BASE UNIT (TBU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.3 USB INTERFACE (U SB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12.4 SMARTCARD INTERFACE (CRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1
Table of Conten ts
3/102
13 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.2 INSTRUCTION GRO UPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.1 ABSOLUTE MAXIMUM RATING S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.2 RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.3 SUPPLY AND RESET CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.4 CLOCK AND TIMING CHARAC TERIST ICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.5 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
14.6 S MARTCARD SUPPLY SUP ERVISOR EL ECTRICAL CHARACTERISTICS . . . . . . . . 82
14.7 EMC CHARACTERISTIC S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
14.8 COMMUNICATION INTERFAC E CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . 89
15 PACKAGE CHA RACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
15.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16 DEVICE CONF IG URATI ON AND ORDERING INF ORMATIO N . . . . . . . . . . . . . . . . . . . . . . . . 92
16.1 DE VICE O RDE RING INFORMATION AND TRANSFER OF CUSTOMER CO DE . . . . . 93
16.2 DEVELOPMENT TOOL S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16.3 ST7 APPLICATION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
17 SUM MARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
E RRATA SH EET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
18 SILICON IDEN TIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9
19 REFERENCE SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20 SILICON LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.1 UNEXPECTED RESET FETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.2 USB: TWO CONSECU TIVE SETUP TOKENS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
20.3 USB BUFFER SHARED MEMO RY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.4 WDG (WATCHDOG) LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.5 SUPPLY CURRENT IN HALT MODE (SUSPEND) LIMITATIO N S . . . . . . . . . . . . . . . . 100
20.6 START-UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
20.7 I/O PORT INPUT HIGH L EVEL (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
21 Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
22 ERRATA SHEET ReVISION History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1
To obtain the m ost recent version of this datasheet,
please check at w ww.st.com>products>technical li terature>datasheet
Please note that an errata sheet can be found at the end of this document on
page 99.
ST7SCR
4/102
1 INTRO DU CTION
The ST7SCR and ST7FSCR devices are mem-
bers of the ST7 microcontrol ler fami ly designed for
USB applications. All devices are based on a com-
mon ind ustry-standard 8-bi t core, f eaturing an en-
hanced instruction set.
The ST7SCR ROM devices are factory-pro-
grammed and are not reprogrammable.
The ST7FSCR versions feature dual-voltage
Flash memory with Flash Programming capability.
They operate at a 4MHz external oscillator fre-
quency.
Under software c ontrol, all devices c an be pla ce d
in WAIT or HALT mode, reducing power consump-
tion when the application is in idle or stand-by
state.
The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highl y
efficient and compact applicat i on code. In addition
to standard 8-bi t data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.
The devices include an ST7 Core, up t o 16 Kbytes
of program memory, up to 512 bytes of user RAM,
up to 35 I/O lines and the following on-chi p peri ph-
erals:
– USB full speed interface wit h 7 endpoin ts, pro-
grammable in/out configuration and embedded
3.3V vol tage regulat or and transceivers (no ex-
ternal component s are needed).
– ISO7816-3 UA RT interface with Programmable
Baud rat e from 372 clock pulses up to 11.625
clock pulse s
– Smartcard Supply Block abl e to provide pro-
grammable supply voltage and I/O voltage levels
to the smartcards
– Low voltage reset ensuring proper power-on or
power-off of the device (selectable by option)
– Watchdog Timer
– 8-bit Timer (TB U)
Figure 1 . ST7SCR Block Diagram
8-B IT CORE
ALU
ADDRESS AND DATA BUS
OSCIN
OSCOUT
PA6
4MHz
CONTROL
RAM
(512 Bytes)
PROGRAM
(16K Bytes )
MEMORY
8-BIT TIMER
LVD
VPP
USBDP
USBDM
USBVCC
POR T C PC[7:0]
PB[7:0]
PA[5:0]
SUPPLY
MANAGER
PLL
OSCILLATOR
USB
PORT B
PORT A
USB
DATA
BUFFER
(256 bytes)
DIVIDER 8 MHz
3V/1 .8 V Vreg
DC/DC
CRDDET
CRDIO
CRDC4
CRDC8
CRDRST
CRDCLK
PD[7:0]
ISO7816 UART
PORT D
CONVERTER CRDVCC
SELF
WATCHDOG
LED LED[3:0]
or 4 MHz
48 MHz
DIODE
1
ST7SCR
5/102
2 PI N DESCRIPTI ON
Figure 2. 64-Pin TQFP Packag e Pino ut
WAKUP2/PA2
WAKUP2/PA3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
OSCIN
OSCOUT
CRDDET
VDD
WAKUP2/ICCDATA/PA0
WAKUP2/ICCCLK/PA1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
C4
CRDIO
C8
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
NC
CRDCLK
NC PA6
VPP
PC7/WAKUP1
PC6/WAKUP1
PC5/WAKUP1
PC4/WAKUP1
PC3/WAKUP1
PC2/WAKUP1
PC1/WAKUP1
PC0/WAKUP1
GND
VDD
NC
DP
DM
LED0
SELF1
SELF2
PA5
PA4
NC
NC
LED3
LED2
LED1
VDD
VDDA
USBVcc
CRDVCC
GND
GNDA
DIODE
CRDRST
NC = Not Connected
1
ST7SCR
6/102
PIN DESCRIPTION (Cont’d)
Figure 3. 24-Pin SO Package Pinout
14
13
11
12
15
16
17
18 LED0
DM
DP
USBVcc
OSCIN
OSCOUT
VPP
1
2
3
4
5
6
7
8
9
10
DIODE
CRDCLK
CRDRST
CRDVCC
PA6
CRDIO
19
20
C8
CRDDET
ICCDATA/WAKUP2/PA0
VDDA
C4
GNDA
ICCCLK/WAKUP2/PA1 NC
GND 21
22
23
24 VDD
SELF
1
ST7SCR
7/102
PIN DESCRIPTION (Cont’d)
Legend / Abbreviations:
Type: I = input , O = output, S = supply
In/Output level: CT = CMOS 0.3VDD/0.7VDD with
input trigger
Output level: HS = 10mA high sink (on N-buffer
only)
Port and control configuration:
– Input:float = floating, wpu = weak pull-up, int = in-
terrupt, ana = analog
– Output: OD = open drain, PP = push-pull
Refer to “I/O PORTS” on pag e 30 for more details
on the software configuration of the I/O ports.
Table 1. Pin Description
Pin n°
Pin Name
Type
Level
V
CARD
supplied
Port / Control
Main
Function
(after reset) Alternate Function
TQFP64
SO24
Input
Output
Input Output
wpu
int
OD
PP
1 5 CRDRST O CTX X Smartcard Reset
2 NC Not Connected
3 6 CRDCLK O CTX X Smartcard Clock
4 NC Not Connected
57C4 O C
TX X Smartcard C4
6 8 CRDIO I/O CTX X X Smartcard I/O
79C8 O C
TX X Smartcard C8
8 3 GND S Ground
9 PB0 O CTX X Port B0 1)
10 PB1 O CTX X Port B1 1)
11 PB2 O CTX X Port B2 1)
12 PB3 O CTX X Port B3 1)
13 PB4 O CTX X Port B4 1)
14 PB5 O CTX X Port B5 1)
15 PB6 O CTX X Port B6 1)
16 PB7 O CTX X Port B7 1)
17 10 CRDDET I CTX Smartcard Detection
18 VDD S Power Supply voltage 4V-5.5V
19 11 PA0/WAKUP2/
ICCDATA I/O CTX X X X Port A0 Interrupt, In-Circuit Communication
Data Input
20 12 PA1/WAKUP2/
ICCCLK I/O CTX X X X Port A1 Interrupt, In-Circuit Communication
Clock Input
21 PA2/WAKUP2 I/O CTX X X X Port A2 1) Interrupt
22 PA3/WAKUP2 I/O CTX X X X Port A3 1) Interrupt
23 PD0 O CTX X Port D0 1)
24 PD1 O CTX X Port D1 1)
25 PD2 O CTX X Port D2 1)
1
ST7SCR
8/102
26 PD3 O CTX X Port D3 1)
27 PD4 O CTX X Port D4 1)
28 PD5 O CTX X Port D5 1)
29 PD6 O CTX X Port D6 1)
30 PD7 O CTX X Port D7 1)
31 14 OSCIN CTInput/Output Oscillator pins. These pins connect a
4MHz parallel-resonant crystal, or an external source
to the on-chip oscillator.
32 15 OSCOUT CT
33 VDD S Power Supply voltage 4V-5.5V
34 GND S Ground
35 PC0/WAKUP1 I CTX X PC0 1) External interrupt
36 PC1/WAKUP1 I CTX X PC1 1) External interrupt
37 PC2/WAKUP1 I CTX X PC2 1) External interrupt
38 PC3/WAKUP1 I CTX X PC3 1) External interrupt
39 PC4/WAKUP1 I CTX X PC4 1) External interrupt
40 PC5/WAKUP1 I CTX X PC5 1) External interrupt
41 PC6/WAKUP1 I CTX X PC6 1) External interrupt
42 PC7/WAKUP1 I CTX X PC7 1) External interrupt
43 16 VPP SFlash programming voltage. Must be held low in nor-
mal operating mode.
44 17 PA6 I CTPA6
45 18 LED0 O HS X Constant Current Output
46 19 DM I/O CTUSB Data Minus line
47 20 DP I/O CTUSB Data Plus line
48 NC Not Connected
49 21 USBVCC O CT3.3 V Output for USB
50 22 VDDA S power Supply voltage 4V-5.5V
51 23 VDD S power Supply voltage 4V-5.5V
52 LED1 O HS X Constant Current Output
53 LED2 O HS X Constant Current Output
54 LED3 O HS X Constant Current Output
55 NC Not Connected
56 NC Not Connected
57 PA4 I/O CTX X X X Port A4
Pin n°
Pin Name
Type
Level
V
CARD
supplied
Port / Control
Main
Function
(after reset) Alternate Function
TQFP64
SO24
Input
Output
Input Output
wpu
int
OD
PP
1
ST7SCR
9/102
Note 1 : Keyboard interface
58 PA5 I/O CTX X X X Port A5
59 24 SELF2 O CTAn External inductance must be connected to these
pins for the step up converter (refer to Figure 4 to
choose the right capacitance)
60 24 SELF1 O CT
61 1 DIODE S CT
An External diode must be connected to this pin for
the step up converter (refer to Figure 4 to choose the
right componen t)
62 2 GNDA S Ground
63 3 GND S
64 4 CDRVCC O CTX Smartcard Supply pin
Pin n°
Pin Name
Type
Level
V
CARD
supplied
Port / Control
Main
Function
(after reset) Alternate Function
TQFP64
SO24
Input
Output
Input Output
wpu
int
OD
PP
ST7SCR
10/102
PIN DESCRIPTION (Cont’d)
Figure 4. Smartcard Interface Reference Application
Note 1: Refer to Section 6 on page 20.
LED0
DM
DP
USBVcc
OSCIN
OSCOUT
VPP
DIODE
CRDCLK
CRDRST
CRDVCC
PA6
CRDIO
C8
CRDDET
PA0
VDDA
C4
GNDA
PA1 NC
GND VDD
SELF VDD
CL1
CL2
C7 C8
C9
VDD
L1
C5
D1
R
LED
C4
VBUS
D-
D+
GND
SHIELD
C2C1 C3
C6
VDD
VDD
D+
D-
Mandatory values for the external components :
C2 : 4.7 µF, E SR 0.5 Ohm
L1 : 10 µH, 2 Ohm
C7 : 4.7 µF,ESR 0.5 Ohm
C5 : 1 nF
Crystal 4. 0 M Hz, Impedance max100 Ohm
Cl1, C l2 1)
D1: BAT4 2 SHOTT KY
C6 : 100 nF
C8 : 470 pF
C9 :
100 pF
C1 : 100nF
C3 : 1 µF
C4 : 4.7 µF
R : 1.5kOhm
1
ST7SCR
11/102
3 REGISTER & MEMORY MAP
As s hown in Figure 5, the MCU is capable of ad-
dressing 64K bytes of memor ies and I/O registers.
The available memory locations consist of 40
bytes of r egister locations, up to 512 bytes of RAM
and up to 16K by tes of user program memor y. The
RAM space i nc ludes u p to 128 byt es fo r the stac k
from 0100h to 017Fh.
The highest address bytes contain the user reset
and interrupt vectors.
IMPORTANT: Memory locations noted “Re-
served” m ust never be acc essed. A ccessi ng a re-
served area can have unpredictable effect s on the
device.
Figu re 5. Memory M a p
0000h
Interrupt & Reset Vectors
HW Registers
0040h
003Fh (see Table 2)
FFDFh
FFE0h
FFFFh (see Table 7)
C000h
033Fh
Program Memory
RAM
USB RAM
(16K Bytes)
Short Addressing
Stack (128 Bytes )
0100h
0180h
023Fh
0040h
00FFh
017Fh
16-bit Addressing RAM
RAM (192 Bytes)
( 192 Bytes)
023Fh
0240h
256 Bytes
(512 Bytes)
Unused
1
ST7SCR
12/102
Table 2. Hard war e Regis ter Memo ry Map
Address Block Register
Label Register
name Reset Status Remarks
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
CRD
CRDCR
CRDSR
CRDCCR
CRDETU1
CRDETU0
CRDGT1
CRDGT0
CRDWT2
CRDWT1
CRDWT0
CRDIER
CRDIPR
CRDTXB
CRDRXB
Smartcard Interface Control Register
Smartcard Interface Status Register
Smartcard Contact Control Register
Smartcard Elementary Time Unit 1
Smartcard Elementary Time Unit 0
Smartcard Guard time 1
Smartcard Guard time 0
Smartcard Character Waiting Time 2
Smartcard Character Waiting Time 1
Smartcard Character Waiting Time 0
Smartcard Interrupt Enable Register
Smartcard Interrupt Pending Register
Smartcard Transmit Buffer Register
Smartcard Receive Buffer Register
00h
80h
xxh
01h
74h
00h
0Ch
00h
25h
80h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
000Eh Watchdog WDGCR Watchdog Control Register 00h R/W
0011h
0012h
0013h
0014h
Port A
PADR
PADDR
PAOR
PAPUCR
Port A Data Register
Port A Data Direction Registe r
Option Register
Pull up Control Register
00h
00h
00h
00h
R/W
R/W
R/W
R/W
0015h
0016h
0017h Port B PBDR
PBOR
PBPUCR
Port B Data Register
Option Register
Pull up Control Register
00h
00h
00h
R/W
R/W
R/W
0018h Port C PCDR Port C Data Register 00h R/W
0019h
001Ah
001Bh Port D PDDR
PDOR
PDPUCR
Port D Data Register
Option Register
Pull up Control Register
00h
00h
00h
R/W
R/W
R/W
001Ch
001Dh
001Eh
001Fh
MISC
MISCR1
MISCR2
MISCR3
MISCR4
Miscellaneous Register 1
Miscellaneous Register 2
Miscellaneous Register 3
Miscellaneous Register 4
00h
00h
00h
00h
R/W
R/W
R/W
R/W
1
ST7SCR
13/102
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
USB
USBISTR
USBIMR
USBCTLR
DADDR
USBSR
EPOR
CNT0RXR
CNT0TXR
EP1TXR
CNT1TXR
EP2RXR
CNT2RXR
EP2TXR
CNT2TXR
EP3TXR
CNT3TXR
EP4TXR
CNT4TXR
EP5TXR
CNT5TXR
ERRSR
USB Interrupt Status Register
USB Interrupt Mask Register
USB Control Register
Device Address Register
USB Status Register
Endpoint 0 Register
EP 0 ReceptionCounter Register
EP 0 Transmission Counter Register
EP 1 Transmission Register
EP 1 Transmission Counter Register
EP 2 Reception Register
EP 2 Reception Counter Register
EP 2 Transmission Register
EP 2 Transmission Counter Register
EP 3 Transmission Register
EP 3 Transmission Counter Register
EP 4 Transmission Register
EP 4 Transmission Counter Register
EP 5 Transmission Register
EP 5 Transmission Counter Register
Error Status Register
00h
00h
06h
00h
00h
0xh
00h
00h
00h
00h
00h
0xh
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0035h
0036h TBU TBUCV
TBUCSR Timer counter value
Timer control status 00h
00h R/W
R/W
0037h
0038h
0039h
003Ah
ITC
ITSPR0
ITSPR1
ITSPR2
ITSPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
003Bh Flash FCSR Flash Control Status Register 00h R/W
003Eh LED_CTRL LED Control Register 00h R/W
Address Block Register
Label Register
name Reset Status Remarks
1
ST7SCR
14/102
4 FLA SH PROGRAM MEMORY
4.1 In t roduction
The ST7 dual voltage High Density Flash (HD-
Flash) is a non-volatile memory that can be electri-
cally erased as a single block or by i ndividual sec-
tors and programmed on a Byte-by-Byte basis us-
ing an external VPP supply.
The HDFlash devices can be programmed and
erased o ff-board (plugge d in a programm ing tool)
or on-board using ICP (In-Circuit Programm ing) or
IAP (In-Application Programming).
The array matrix organisation allows each sector
to be erased a nd reprogrammed wi thout affecting
ot her sectors.
4.2 Main Features
■Three Fla sh programm ing modes :
– Insertion in a program m ing tool. In this m ode,
all sectors including option bytes can be pro-
gramme d or erased.
– ICP (In-Circuit Programming). In this mode, all
sectors including option bytes can be pro-
gramme d o r erased without removing the de-
vice from the application board.
– IAP (In-Application Programming) In this
mode, al l sectors except Sector 0, can be pro-
gramme d o r erased without removing the de-
vice from the appli ca tion bo ard and wh ile the
application is running.
■ICT (In-Circuit Testing) for downloading and
execut i ng user application test patterns in RAM
■Read-out protection against piracy
■Register Access Security System (RASS) to
preve nt accidental programm ing or erasing
4.3 S tructur e
The Flash memory is organised in sectors and can
be used for both code and data storage.
Depending on the overall FLASH memory size in
the microcontroller device, there are up to three
user sectors (see T able 3). E ach of these s ectors
can be erased independently to avoid unneces-
sary erasing of the whole Flash memory when only
a partial erasing is re quired.
The first tw o sec tors have a fixed size of 4 K bytes
(see Figure 6). They are mapped in the upper part
of the ST7 addressing space so the reset and in-
terrupt vectors are located in Sector 0 (F000h-
FFFFh).
Table 3. Sector s availab le in FLASH devices
Figure 6. Memo ry map and sector address
Flash Memory Size
(bytes) Available Sectors
4K Sector 0
8K Sectors 0,1
> 8K Sectors 0,1, 2
4 Kbytes
4 Kbytes
SECTOR 1
SECTOR 0
SECTOR 2
16K USER FLASH MEMORY SIZE
FFFFh
F000h
EFFFh
E000h
DFFFh
C000h
8Kbytes ex.: user program
ex.: user data
ex.: user sy stem library
+ IAP BootLoader
+ library
1
ST7SCR
15/102
FLASH PROGRAM MEMORY (Cont’d)
4.4 ICP (In-Circuit Programming)
To perform ICP the microcontroller must be
switched to ICC (In-Circuit Commu nication) mod e
by an external control l er or programming tool.
Depending on the ICP co de dow nloaded in RAM ,
Flash memory programming can be fully custom-
ized (number of bytes to program, program loca-
tions, or selection serial communication interface
for downloading).
When using an STMicroelectronics or third-party
programming tool that supports ICP and the spe-
cific microcont roller device, the user needs only to
implement the ICP hardware interface on the ap-
plication board (see Figure 7). For more details on
the pin locations, refer to the device pinout de-
scription.
ICP needs six signa ls to be connected to th e pro-
gramming tool. These signal s are:
–V
SS: device power supply ground
–V
DD: fo r r e set by L VD
– OSCIN: t o force the clock during power-up
– ICCCLK: ICC output serial clock pin
– ICCDATA: ICC input serial data pin
–V
PP: ICC mode selection and programming
voltage.
If ICCCLK or ICCDATA are used for other purpos-
es in the appli cat ion, a serial resistor has to be im-
plemented to avoid a conflict in case one of the
other devices forces the signal level.
Note: To develop a c usto m program mi ng tool, re-
fer to the ST7 F LASH P rogrammin g and ICC Ref-
erence Manual wh ich gives full details on the ICC
protocol hardware and software.
4.5 IAP (In-Application Programming)
This mode uses a Boot Loader program previously
stored in Sect or 0 by the user (in ICP mo de or by
plugging the devi ce in a programming tool).
This mode is fully controlled by user software. This
allows it t o be adapted to the user application, (us-
er-defined strategy for entering programming
mode, choice of com mun ications prot ocol us ed t o
fetch the data to be stored, etc.). F or example, it i s
possible to downl oad code from the USB interface
and program it in t he Flash. IAP mode can be used
to program any of the F lash sectors except Sec tor
0, which is write/erase protected to al low recovery
in case errors occur during the progr am ming oper-
ation.
Figure 7. Typical ICP Interface
ICP PROGRAMMING TOOL CONNECTOR
10kΩ
CL2 CL1
ICCDATA
ICCCLK
V
SS
V
PP
OSCIN
OSCOUT
ST7
HE10 CONNECTOR TYPE
TOT
HE APPLICATION
V
DD
4.7kΩ
APPLICAT ION BOARD
1
246810
975 3
PROGRAMMING TOOL
ICC CONNECTOR
IC C Cab le
1
ST7SCR
16/102
FLASH PROGRAM MEMORY (Cont’d)
Note: If the ICCCLK or ICCDATA pins are only
used as outputs in the application, no signal isola-
tion is necessary. As soon as the Programming
Tool is plugged to the board, even if an ICC ses-
sion is not i n progress, the ICCCLK and ICCDATA
pins are not available for the application. If they
are used as inputs by the application, isolation
such as a serial resistor has to implemented in
case another device forces the signal. Ref er to the
Programming Tool documentation for recom-
mended resistor values.
4.6 Program Memo ry Read -out P rotection
The read-out protect ion is ena bled through an op-
tion bit.
For Flash devices, when this option is selected,
the program and data stored in the F lash m em ory
are prote ct ed ag ainst rea d-out piracy (including a
re-write protection). When this protection is re-
moved by reprogramming t he Option Byte, the en-
tire Flash program memory is first automatically
erased.
Refer to the Op tion Byte description for more de-
tails.
4.6.1 Regi ster Descrip tion
FLASH CONTROL/STATUS REGISTER (F CSR)
Read/Write
Reset Value: 0000 0000 (00h)
This register is reserved for use by Programming
Tool software. It control s t he FLASH programming
and erasing operations. For details on customizing
FLASH programming methods and In-Circui t Test-
ing, refer to the ST7 FLASH Programming and
ICC Ref e rence Manual.
70
00000000
1
ST7SCR
17/102
5 CE NTRAL PROCE SSING UNI T
5.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.
5.2 MAIN FE ATURES
■Enable executing 63 basic i nstructions
■Fast 8-bit by 8-bit multiply
■17 main addressing modes (with indirect
addres sing mo de)
■Two 8-bit index registers
■16-bit stack pointer
■Low power HALT and WAIT modes
■Priority maskable hardware interrupts
■Non-ma skable software/hardware interrupts
5.3 CPU REGIST ERS
The 6 CPU registers shown in Figure 8 are not
present in the memory mappi ng and ar e accessed
by specifi c ins t ru c tio n s .
Accumulator (A)
The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.
Index Registers (X and Y)
These 8-bit registers are used to create effective
addresses o r as tempo rary storage areas f or data
manipulation. (The Cross-Assembler generates a
precede instruction (PRE) to indicate that the fol-
lowing instruction refers to t he Y register.)
The Y register is not aff ected by the interrupt auto-
matic procedu res.
Prog ram C ou nte r (P C )
The program counter is a 16-bit register containing
the address of the nex t inst ruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High whic h is the MSB).
Figure 8. CPU Registers
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
STACK POINTER
CONDITION CODE REGISTER
PROGRAM COUNTER
70
1C1I1HI0NZ
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
70
70
70
0
7
15 8
PCH PCL
15 870
RESET VALUE = STACK HIGHER ADDRESS
RESET VALUE = 1X11X1XX
RESET VALUE = XXh
RESET VALUE = XXh
RESET VALUE = XXh
X = Undefined Value
1
ST7SCR
18/102
CE NTRA L PRO C ESSING UN IT (Cont’d)
Conditio n Code Reg ister (CC)
Read/Write
Reset Value: 111x1xxx
The 8-bit Condi tio n Code register contains the i n-
terrupt masks and four flags representative of the
result of the i nstruct ion just executed. This register
can also be handled by the PUSH and POP in-
structions.
These bits can be individually tested and/or con-
trolled by specific instructi ons.
Arithmetic Management Bits
Bi t 4 = H
Half carry
.
This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instructions. It is reset by hardware during
th e same instru ctions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruc-
tion. The H bit is us eful in BCD arithmetic subrou-
tines.
Bi t 2 = N
Negative
.
This bit is set and cl eared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It’s a copy of the re-
sult 7th bit.
0: The result of the last operation is positive or null.
1: Th e result of the l ast operation is negative
(i.e. the m ost significant bit is a log ic 1).
Thi s bit i s accessed by the JRMI and JRPL ins truc-
tions.
Bit 1 = Z
Zero
.
This bit is set and cleared by hardware. This bit in-
dicates that the res ult of the last arithme tic, logical
or data manipulation is zero.
0: T he result of the last operation is dif ferent from
zero.
1: The result of the last operat ion is zero.
This bit is accessed by the JREQ and JRNE test
instructions.
Bit 0 = C
Carry/borrow.
This bit is set and cleared by hardware and soft-
ware. It indicates an overf low or an un derflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit i s driven by th e SCF and RCF i nstructions
and tested by the JRC and JRNC in struct i ons. It i s
also affected by t he “bit test and branch”, shift and
rotate instructions.
Inte rru pt Manag em e nt B i ts
Bit 5,3 = I1, I0
Interrupt
The combination of the I1 and I0 bits gives the cur-
rent interrupt s oftware priority.
These t wo bits are set /cleared by hardware when
entering in interrupt. The load ed value is given by
the corresponding bits in the int errupt softwar e pri-
ority registers (IxSPR). They can be also set/
cleared by software with the RIM, SIM, IRET,
HALT, WFI and PUSH/ POP instructions.
See the interrupt management chapter for more
details.
70
11I1HI0NZC
Interrupt Softw are Priorit y I1 I0
Level 0 (main) 1 0
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1
1
ST7SCR
19/102
CE NTRA L PRO C ESSING UN IT (Cont’d)
St a ck Pointer ( SP)
Read/Write
Reset Value: 017Fh
The Stack Pointer is a 16-bit register which is al-
ways point ing to the next free loc at ion in t he st ack.
It is then dec remented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 9).
Since the stack is 256 bytes deep, th e 8 most sig-
nificant bits are forced by hard ware. Following a n
MCU Reset, or after a Reset Stack Pointer instruc-
tion (RSP), t he Stack Pointer contains its reset val-
ue (the SP7 to SP0 bits are set) which i s the stack
higher address.
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.
Note: When the lower li mit is exceeded, the Stack
Pointer wraps around to t he stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flo w.
The stack is u sed to save th e retu rn address dur-
ing a subroutine call and the CPU context during
an interr upt. The user may also dir ectly manipulate
the stack by means of the PUSH and POP inst ruc-
tions. In the case of an interrupt, the PCL is stored
at the f irst locati on po inted t o by t he SP. Then t he
other registers are stored in the next locations as
shown in Figure 9
– When an interrupt is received, t he SP is decre-
ment ed and the context is pushed on the stack.
– On return from interrupt, the SP is in crement ed
and the context is popped from the stack.
A subrouti ne call occupies two loc ations and an in-
terr upt five loca tions in the stack area.
Figure 9. Stack Manipulation Example
15 8
00000001
70
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
PCH
PCL
SP
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
PCL
PCH
X
A
CC
PCH
PCL
SP
SP
Y
CALL
Subroutine Interrupt
Event PUSH Y POP Y IRET RET
or RSP
@ 017Fh
@ 0100h
Stack Higher Address = 017Fh
Stack Lower Address = 0100h
1
ST7SCR
20/102
6 SUPPLY , RESET AND CLOCK MANAGEMENT
6.1 CLOCK SYSTEM
6.1.1 General Descri ption
The MCU ac cepts either a 4MHz crystal or an ex-
ternal clock signal to drive the internal oscillator.
The internal clock (fCPU) is derived from t he inter-
nal os c illa t or freq uenc y (fOSC) , wh ic h is 4 Mhz .
After reset, the internal clock (fCPU) is provided by
the internal oscillator (4Mhz frequency).
To activate the 48-MHz clock for the USB inter-
face, the us er m ust t urn on t he PLL by se tting th e
PLL_ON bit in the MISCR4 register. When the PLL
is locked, t he LOCK bit is set by hardware.
The user can then select an internal frequency
(fCPU) of either 4 MHz or 8MHz by programming
the CLK_SEL bit in the MISCR4 registe r (refer to
MISCELLANEOUS R EGISTERS sec tion on page
37).
The P LL provides a s ignal with a dut y cycle of 50
%.
The internal clock signal (fCPU) is also routed to
the on-chip peripherals. The CPU clock signal
consists of a square wave with a duty cycle of
50%.
Figure 10. Clock, Reset and Supply Block Diagram
The interna l oscillator is designed to operate with
an AT-cut parallel resonant quartz in the frequen-
cy range specified for fosc. The circuit shown in
Figure 12 is recommended when using a crystal,
and Table 4 lists the recommended capacitance.
The cry stal and associated components should be
mounted as close as possible to the input pins i n
order to minimize output distortion and start-up
stabilisation time. The LOCK bit in the MISCR4
register can also be used to generat e the fCPU di-
rectly from fOSC if the PLL and the USB interface
are not act ive.
Table 4. Recommended Values for 4 MHz
Crysta l Resonato r
Note: RSMAX is the equivalent serial resistor of the
crystal (see crystal spe cification).
PLL_
MISCR4 ON
-
-----
LOCK
4 Mhz INTERNAL
8 Mhz CLOCK (fCPU)
4 MHz PLL
X 12 48 MHz
USB
48 MHz
DIV
(fOSC)
CLK_
SEL
RSMAX 20 Ω25 Ω70 Ω
COSCIN 56pF 47pF 22pF
COSCOUT 56pF 47pF 22pF
1
ST7SCR
21/102
CLOCK SYSTEM (Cont’d)
6.1.2 External Clock
An external clock may be applied to the OSCIN in-
put with the OSCOUT pin not connected, as
shown on Figure 11.
Figure 11. .External Clock Source Connections
Figure 12. Crystal Resona tor
OSCIN OSCOUT
EXTERNAL
CLOCK
NC
OSCIN OSCOUT
COSCIN COSCOUT
1
ST7SCR
22/102
6.2 RESET SEQUENCE MANAGER (RSM)
6.2 .1 Int roducti on
The reset sequence manager has two reset sourc-
es:
■Internal LVD reset (Low Voltage Detection)
which includes both a power-on and a voltage
drop res et
■Internal watchdog reset generated by an
internal watchdog counter underflow as shown
in F igure 14.
6.2.2 Functional Desc ription
The reset service routine vector is fixed at ad-
dresses FFFEh-FFFF h in the ST7 memory map.
The basi c reset sequenc e consists of 3 phas es as
shown in Figure 13:
■A first delay of 30µs + 127 tCPU cycles during
which the int ernal reset is maintained.
■A second delay of 512 tCPU cycles after the
internal reset is generated. It allows the
oscillat or to stabilize and ens ures that recover y
has taken place from the Reset state.
■Reset vecto r fe tch (d u ra ti on : 2 clock cycles)
Low Vol tage Detecto r
The low voltage detector generates a reset when
VDD<VIT+ (rising edge) or V DD<VIT- (falling edge),
as shown in Figure 13.
The LVD filters spikes on VDD larger t han tg(VDD) to
avoi d para siti c rese ts. Se e “ SUP PLY AND RESET
CHARACTERI STICS” on page 79.
Figure 13. LVD RESET Sequence
Fi gure 14. Watchdog R ESET Seque nce
DELAY 1 RUN
LVD
RESET
FETCH VECTOR (2 tCPU)
DELAY 2
LVD
RESET
INTERNAL
RESET
DE LAY 1 = 30 µs + 127 tCPU
DELAY 2 = 512 tCPU
VDD
VIT+ VIT-
WATCHDOG
WATCHDOG UNDERFLOW
RESET
FETCH VECT OR (2 tCPU)
DELAY 1
WATCHDOG
RESET
DEL AY 2
DELAY 1 = 30µs + 127 tCPU
DELAY 2 = 512 tCPU
RUN
1
ST7SCR
23/102
7 INTE RRUPT S
7.1 INTRODUCTION
The ST7 enhanced interrupt management pro-
vides the f ollowing features:
■Hardware interrupts
■Software interrupt (TRAP)
■Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 soft ware programmable nesting levels
– Up to 16 interrupt v ectors fixed by hardware
– 3 non maskable events: TLI, RESET, TRAP
This interrupt manageme nt is based on:
– Bit 5 and bit 3 of the CPU CC register (I1 :0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vecto r addresses locat ed at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
7.2 MASKIN G AND PROC ESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see Tab le 5). The process-
ing flow is shown in Fi gure 15.
When an interrupt request has to be serviced:
– Normal proces sing is suspended at the end of
the current instruction execution.
– The P C, X, A and CC regist ers are saved onto
the stack.
– I1 and I0 bits of CC regi ster are set according t o
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fe tched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET i ns truction which causes the contents of the
saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 5. Interrupt Soft ware Priority Levels
Figu re 15. I nterrupt Proc essing Fl owchar t
Interrupt softw are priority Le vel I1 I0
Level 0 (main) Low
High
10
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable) 1 1
“IRET”
RESTORE PC, X, A, CC STACK PC, X, A, CC
LOAD I1:0 FRO M IN TERRU PT SW RE G.
FET CH NE XT
RESET TLI
PENDING
INSTRUCTION
I1:0
FROM STACK
LOAD PC FROM INTERRUPT V ECTOR
Y
N
Y
N
Y
N
Interrupt has the same or a
lower software pr iority
THE INTERRUPT
STAYS PENDING
th an current one
Interrupt has a higher
software priority
than current one
EXECUTE
INSTRUCTION
INTERRUPT
1
ST7SCR
24/102
INTERRUPTS (Cont’d)
Serv i cin g Pe nding Inte rrupts
As seve ra l interrupts can b e pen ding at the same
time, the interrupt to be taken into ac count is deter-
mined by the following two-step process:
– the highest software priori ty interrupt is serviced,
– if several interrupts have the same s oft ware pri-
ority then the inter rupt with the highest hardware
priority is serviced first.
Figure 16 describes this decision process.
Figure 16. Priority Decision Process
When an interrupt request is not serviced immedi-
ately, it is latched and then processed when its
software priority combined with the hardware pri-
ority becomes the highest one.
Note 1: The hardware priority is exclusive while
the software one is not. This allows the previous
process to succeed with only one interrupt.
Note 2: RESET, TRAP and TLI are n on mask abl e
and they can be c onsidered as hav in g the highest
software priority in the decision process.
Different Interrupt Vector Sources
Two interrupt source types are managed by the
ST7 interrupt controller: the non-maskable type
(RESET, TLI, TRAP) and the maskable type (ex-
ternal or fro m internal peripherals).
Non-Mask able Sourc es
These sources are processed regardless of the
state of the I1 and I0 bits of the CC register (see
Figure 15). After stacking the PC, X, A and CC
registers (except for RESET), the corresponding
vector is loaded in the PC re gister and the I 1 and
I0 bits of the CC are set to disable interrupts (level
3). These sources allow the processor to exit
HALT mode.
■TLI (Top Level Hardware Interrupt)
This hardware interrupt occurs when a specific
edge is detected on the dedicated TLI pin.
Caution: A TRAP instruction must not be used in a
T LI se rv i ce r out in e.
■TRAP (Non Maskable Software Interrupt)
This software interrupt is serviced when the TRAP
instruction is executed. It will be serviced accord-
ing to t he flowchart in Figure 15 as a TLI .
Caution: TRAP can be interrupted by a TLI.
■RESET
The RESET source h as the highe st priority in the
ST7. This means that the first current routine has
the highest soft ware priority (level 3) and the hi gh-
est hardware priority.
See the RESET chapter for more details.
Maskab le Sou rces
Maskable interrup t vector sourc es can be servi ced
if the corresponding interrupt is enabled and if its
own interrupt software priority (in ISP Rx registe rs)
is higher tha n the one curren tly being serviced (I1
and I0 in CC register). If any of these two condi-
tions is false, the interrupt is latched and thus re-
mains pendi ng.
■External Interrupt s
External interrupts allow the processor to exit f rom
HALT low power mode.
External inter rupt sensitivit y is sof tware selectable
through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched
and the interrupt request automatically cleared
upon entering the interrupt service routine.
If several input pins of a group connected to the
same interrupt line are selected simultaneously,
the s e w ill be log i cally NAN D ed.
■Peripheral Interrupt s
Usually the peripheral int errupts cause the MCU to
exit from HALT mode except those mentioned in
the “Interrupt Mapping” tabl e.
A peripheral interrupt occurs when a specific flag
is set in the peripheral status registers and if the
corresponding enable bit is set in the peripheral
control register.
The general sequence for clearing an interrupt is
based on an access to the status register followed
by a read or writ e to an associated register.
Note: The clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear se-
quence is executed.
PENDING
SOFTWARE Different
INTERRUPTS
Same
HIGHEST HARDWARE
PR IORITY SERVICED
PRIORITY
HIG HEST SOFTW ARE
PRIORITY SERVICED
1
ST7SCR
25/102
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and oth er specified interrupt s allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the f irst one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected throu gh the same dec i sion proc-
ess shown in Figure 16.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is s erviced
after the first one serviced.
7.4 CONCURRENT & NESTED MANAGEMENT
The following Figure 17 and Figure 18 show two
different interrupt management modes. The fi rst is
called concurrent mode and do es not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 18. The inte rrupt hardware priority is given
in this order from the lowes t to the hi ghes t: MA IN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack ov erflow may occur wi tho ut no-
tifying the software of the failure.
Figu re 17 . Con c u rre n t Int errupt Ma na g e m ent
Figure 18. Nested Interrupt Management
MAIN
IT4
IT2
IT1
TLI
IT1
MAIN
IT0
I1
HARDWARE PRIORITY
SOFTWARE
3
3
3
3
3
3/0
3
11
11
11
11
11
11 / 10
11
RIM
IT2
IT1
IT4
TLI
IT3
IT0
IT3
I0
10
PRIORITY
LEVEL
USED STACK = 10 BYTES
MAIN
IT2
TLI
MAIN
IT0
IT2
IT1
IT4
TLI
IT3
IT0
HARDW ARE PRIORITY
3
2
1
3
3
3/0
3
11
00
01
11
11
11
RIM
IT1
IT4 IT4
IT1
IT2
IT3
I1 I0
11 / 10 10
SOFTWARE
PRIORITY
LEVEL
USED STACK = 20 BYTES
1
ST7SCR
26/102
INTERRUPTS (Cont’d)
7.5 INTERRUPT REGISTER DESCRIPTION
CPU CC REGISTER INT ERRUPT BITS
Read/Write
Reset Value: 111x 1010 (xAh)
Bit 5, 3 = I1 , I0
S o ft war e Inter r u p t Pri ori ty
These two bits indicate the current interrupt soft-
ware priority.
These two bits are set/cleared by hardware whe n
entering in interrupt. The loaded val ue is given by
the corresponding bi ts in t he i nterrupt sof tware pri -
ority registers (ISPRx).
They ca n be also set/cleared by s oft ware wi th the
RIM, SIM, HALT, WFI, IRET and PUSH/POP in-
structions (see “Interrupt Dedicated Instruction
Set” table).
*Note: TLI, TRAP and RESET events are non
maskable s ources and can interrupt a level 3 pro-
gram.
INTERRUPT SOFTWARE PRIORITY REGIS-
TERS (ISPRX)
Read/Write (bit 7:4 of ISPR3 are read only)
Reset Value: 1111 1111 (FFh)
These four registers contain the interrupt software
priority of each interrupt vec tor.
– Each interrupt vector (except RESET and TRAP)
has corresponding bits in thes e registers where
its own soft ware priority is stored. This corre-
sponda nce is shown in the following table.
– Each I1_x and I 0_x bit value in the ISPRx r egis-
ters has the same meaning as the I1 and I0 bit s
in the CC register.
– Level 0 ca n not be writt en (I1_x=1, I0_x=0). In
this case, the previously stored value is kept. (ex-
ample: prev ious=CF h, write=64 h, result=44h )
The RE SE T, TRAP a nd TLI vectors hav e no soft-
ware priorities. When one is serviced, the I1 and I0
bits of the CC register are both set.
*Note: Bits in the ISPRx registers which corre-
spond to the T LI can be read and written but they
are not significant in the interrupt process man-
agement.
Caution: If the I1_x and I0_x bits are modified
while the interrupt x is executed the followin g be-
haviour has to be considered: If the interrupt x is
still pending (new interrupt or flag not cleared) and
the new so ftware priority is highe r than the previ-
ous one, the interrupt x is re-entered. Otherwise,
the software priority stays unchanged up to the
next interrupt request (after the IRET of the in ter-
rupt x).
70
11I1 HI0 NZC
Interrupt Software Priority Level I1 I0
Level 0 (main) Low
High
10
Level 1 0 1
Level 2 0 0
Level 3 (= interrupt disable*) 1 1
70
ISPR0 I1_3 I0_3 I1_2 I0_2 I1_1 I0_1 I1_0 I0_0
ISPR1 I1_7 I0_7 I1_6 I0_6 I1_5 I0_5 I1_4 I0_4
ISPR2 I1_11 I0_11 I1_10 I0_10 I1_9 I0_9 I1_8 I0_8
ISPR3 1 1 1 1 I1_13 I0_13 I1_12 I0_12
Vector address ISPRx bits
FFFBh-FFFAh I1_0 and I0_0 bits*
FFF9h-FFF8h I1_1 and I0_1 bits
... ...
FFE1h-FFE0h I1_13 and I0_13 bits
1
ST7SCR
27/102
INTERRUPTS (Cont’d)
Table 6. De dicated Interru pt Instruc tion Set
Note: During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI instructions
change the current software priority up to the next IRET instruction or one of the previously mentioned
instructions.
In order not to lose the current software priority level, the RIM, SIM, HALT, WFI and POP CC instructions
should never be used in an interrupt routine.
Tab le 7. I nt errupt Mapping
Note 1: T his interrupt can be used to exit from USB suspend mode.
Instruction New Description Function/Example I1 H I0 N Z C
HALT Entering Halt mode 1 0
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
JRM Jump if I1:0=11 I1:0=11 ?
JRNM Jump if I1:0<>11 I1:0<>11 ?
POP CC Pop CC from the Stack Mem => CC I1 H I0 N Z C
RIM Enable interrupt (level 0 set) Load 10 in I1:0 of CC 1 0
SIM Disable interrupt (level 3 set) Load 11 in I1:0 of CC 1 1
TRAP Software trap Software NMI 1 1
WFI Wait for interrupt 1 0
N° Source
Block Description Register
Label Priority
Order
Exit
from
HALT
Address
Vector
RESET Reset N/A Highest
Priority
Lowest
Priority
yes FFFEh-FFFFh
TRAP Software Interr upt
no
FFFCh-FFFDh
0 ICP FLASH Start programming NMI interrupt FFFAh-FFFBh
1 UART ISO7816-3 UART Interrupt UIC FFF8h-FFF9h
2 USB USB Communication Interrupt USBISTR FFF6h-FFF7h
3 WAKUP1 External Interrupt Port C yes FFF4h-FFF5h
4 WAKUP2 External Interrupt Port A yes FFF2h-FFF3h
5 TIM TBU Timer Interrupt TBUSR no FFF0h-FFF1h
6 CARDDET 1) Smartcard Insertion/Removal Interrupt 1) USCUR yes FFEEh-FFEFh
7 ESUSP End suspend Interrupt USBISTR FFECh-FFEDh
8 Not used no FFEAh-FFEBh
1
ST7SCR
28/102
8 POW ER SAVING MODES
8.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving modes are implemented in the ST7.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscill ator frequency.
From Run mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depend s on the oscillator
status.
8.2 WAIT MODE
WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This powe r s a v ing mo de is s elected by ca lling th e
“WFI” ST7 software i nstruct ion.
All peripherals remain active. During WAIT m ode,
the I bit of the CC register i s forced to 0, to enable
all interrupts. All other registers and memory re-
main unchanged. The MCU remains in WAIT
mode until an i nterrupt or Reset occurs, where up-
on the Program Counter branches to the starting
address of the interrupt or Reset service routine.
The MCU will r e main in W AIT mo de unt il a Res et
or an Int errupt occurs, c ausing i t to wake up.
Refer to Figure 19.
Figure 19. WAIT Mode Flow Chart
WFI INSTRUCTION
RESET
INTERRUPT Y
N
N
Y
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
ON
CLEARED
OFF
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
ON
SET
ON
FETCH RESET VECTOR
OR SERVICE INTERRUPT
512 CPU CLOCK
CYCLES DELAY
IF RESET
Note: Before servicing an interrupt, the CC
register is pushed on the st ack. The I-Bit is set
during the interrupt routine and cleared when
the CC register is popped.
1
ST7SCR
29/102
POWER SAVING MODES (Cont’d)
8.3 HALT M ODE
The HALT mode is the MCU lowest power con-
sumption mode. T he HALT mode is entered by ex-
ecuting the HALT instruction. The internal oscilla-
tor is th en turned off, causing all internal process-
ing to be stopped, including the operation of the
on-chip peripherals.
Note: The PLL must be disabled before a HALT
instruction.
When entering HALT mode, the I bit in th e Condi-
tion Code Register is cleared. Thus, any of the ex-
ternal interrupts (ITi or USB end suspend mode),
are allowed and if an interrupt occurs, the CPU
clock becomes active.
The MC U c an e xit HAL T m ode on reception of e i-
ther an external interrupt on ITi, an end suspend
mode interrupt coming from USB peripheral, or a
reset. The oscillato r is then t ur ned on and a stabi-
lization time is provided bef ore rele asing CPU op-
eration. The stabilization time is 512 CPU clock cy-
cles.
After the start up delay, the CPU continues opera-
tion by servicing the interrupt which wakes it up or
by fetching the reset vec tor if a res et wakes it up.
Figu re 20 . HAL T Mode Flo w Cha r t
N
NEXTERNAL
INTERRUPT*
RESET
HALT INSTRUCTION
512 CPU CLOCK
FETCH RESE T VECTOR
OR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
ON
SET
ON
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
OFF
OFF
CLEARED
OFF
Y
Y
Note: Before servicing an interrupt, the CC
register is pushed on t he sta ck. The I-Bit is set
during the interrupt routine and cleared when
the CC register is p opped.
1
ST7SCR
30/102
9 I/O PORTS
9.1 In t roduction
The I/ O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– alternate signal input/ output for t he on-chip pe-
ripherals.
– external int errupt detection
An I/ O port i s com pos ed of up to 8 pins. Each pin
can be programmed independently as di gi tal input
(with or without interrupt generation) or digital out-
put.
9.2 Fu nctional description
Each port is associated to 4 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
– Option Register (OR)
– Pull Up Register (PU)
Each I/ O pin may be progr ammed using the corre-
sponding register bits in DDR register: bit X corre-
sponding to pin X of the port. The same corre-
spondence is used for the DR regis ter.
Tab le 8. I /O Pi n Functions
In p ut Mo des
The input c onfigurat ion is sele cted by clearing th e
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Note 1: All the inputs are triggered by a Schmitt
trigger.
Note 2: When switching from input mode to output
mode, the DR register should be written first to
output the correct value as soon as the port is con-
figured as an output.
Interrupt function
When an I/O is configured in Input with Interrupt,
an event on this I/O can generate an external In-
terrupt request to the CP U. The interrupt sensitivi-
ty is given independently according to the descrip-
tion mentioned in the ITRFRE interrupt register.
Each pin can inde pendently generate an I nterrupt
request.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see Interrupts sec-
tion). If more than one input pin is selected simul-
taneously as interrupt source, this is logically
ORed. Fo r this reason if one of the int errupt pi ns is
tied low, it ma sks the other ones.
Output Mode
The pin is conf igured in out put mode by setting the
corresponding DDR register bit (see Table 7).
In this mode, writing “0” or “1” to the DR register
applies this digital value t o the I/O pin through the
latch. Then reading the DR register returns the
previously store d value.
Note: In this mode, the interrupt function is disa-
bled.
Di gi ta l Alternate Function
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over
standard I/O programming. When the signal is
coming from an on-chip peripheral, the I/O pin is
automat ically configured in output mode (push-pull
or open drain according to the peripheral).
When t he s igna l is going t o an on-chip peripheral,
the I/O pin ha s to be configured in input m ode. In
this case, the pin’ s state is also digitally readable
by addressing the DR register.
Notes:
1. Input pull-u p configuration can cause an unex-
pected value at the input of the alt ernate peripher-
al input.
2. When the on-chi p peripheral uses a pin as input
and output , this pin must be configured as an i nput
(DDR = 0).
Warning
: The alternate functi on m ust not be acti-
vated as long as the pin i s configured as input wi th
interrupt, in order to avoid generating s purious in-
terrupts.
DDR MODE
0 Input
1 Output
1
ST7SCR
31/102
I/O PORTS (Cont’d)
9.3 I/O Port Implementation
The hardware implementation on each I/O port de-
pends on the settings in the DDR register and spe-
cific feature of the I/O port such as true open drain.
9.3.1 Port A
Table 9. Port A Description
Figure 21. PA0, PA1, PA2, PA3, PA4, PA5 Configuration
Figu re 22 . P A6 C onfi gurati on
PORT A I / O
Input Output
PA[5:0] without pull-up * push-pull or open drain with software selectable pull-up
PA6 without pull-up -
*Reset State
DR
DDR
LATCH
LATCH
DR SEL
DDR SEL
VDD
PAD
ALTERNATE ENABLE
ALTERNATE ENABLE
ALTERNATE ENABLE
ALTERNATE
ALTERNATE INPUT
PULL-UP 1)
OUTPUT
P-BUFFER
N-BUFFER
1
0
1
0CMOS SCHMITT TRIGGER
VSS
VDD
DIODES
DATA BUS
Note 1: selectable by PAPUCR register
DR SEL
PAD
VDD
DIODES
DATA BUS
CMOS SCHMITT TRIGGER
1
ST7SCR
32/102
I/O PORTS (Cont’d)
9.3.2 Ports B and D
Table 10. Port B and D Description
Figure 23. Po r t B and D Confi gur atio n
PORTS B AND D Output *
PB[7:0] push-pull or open drain with software selectable pull-up
PD[7:0]
*Reset State = open drain
DR
LATCH
DR SEL
VDD
PAD
ALTERNATE ENABLE
ALTERNATE ENABLE
ALTERNATE ENAB LE
ALTERNATE
PULL-UP 1)
OUTPUT
P-BUFFER
N-BUFFER
1
VSS
VDD
DIODES
DATA BUS
OM
LATCH
PULL_UP
LATCH
01
0
‘0’
Note 1: selectable by PAP UCR register
1
ST7SCR
33/102
I/O PORTS (Cont’d)
9.3.3 Port C
Table 11. Port C Description
Figu re 24. P ort C C onf i gu rat i on
PORT C Input
PC[7:0] with pull-up
DR SEL
PAD
ALTERNATE INPUT
VDD
DIODES
CMOS SCHMITT TRIGGER
DATA BUS
PULL-UP VDD
1
ST7SCR
34/102
I/O PORTS (Cont’d)
9.4 R egister Descri pti on
DATA REGISTERS (PxDR)
Port A Data R egister (PADR): 0011h
Port B Data R egister (PBDR): 0015h
Port C Data Register (PCDR): 0018h
Port D Data Register (PCDR): 0019h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Reset Value Port B: 0000 0000 (00h)
Reset Value Port C: 00 00 0000 (00h)
Reset Value Port D: 00 00 0000 (00h)
Bits 7:0 = D[7:0]
Data Regist er 8 bits.
The DR register has a specific beh aviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken in account
even if the pin is con figured as an input. Readin g
the DR regi st er returns either the DR register l atch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
DATA DIRECT ION REGISTER (PADDR)
Port A Data Directio n Registe r (PADDR): 0012h
Read/Write
Reset Value Port A: 0000 0000 (00h)
Bits 7:0 = DD7-DD0
Data Direction Regist er 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mod e
OPTION REGISTER (PxOR)
Port x Option Register
PxOR with x = A, B, o r D
Port A Option Register (PAO R): 0013h
Port B Option Register (PBOR): 0016h
Port D Opt ion Register (PDOR): 001Ah
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = OM[7:0]
Option register 8 bit s.
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
selected.
Each bit is set and cleared by software.
0: Out put open drain
1: Out put push-pull
PULL UP CONTROL REGISTER (PxP UCR)
Port x Pull Up Register
PxPUCR with x = A, B, or D
Port A Pull up Register (PAPUCR): 0014h
Port B Pull up Register (PBPUCR): 0017h
Port D Pull up Register (PDPUCR): 001Bh
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = PU[7:0]
Pull up register 8 bits.
The PU register is used to control the pull u p.
Each bit is set and cleared by software.
0: Pull up inact i ve
1: Pull up active
70
D7 D6 D5 D4 D3 D2 D1 D0
70
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
70
OM7 OM6 OM5 OM4 OM3 OM2 OM1 OM0
70
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
1
ST7SCR
35/102
I/O PORTS (Cont’d)
Table 12. I/ O Ports Register M ap
Address
(Hex.) Register
Label 76543210
11 PADR
Reset Value MSB
0000000
LSB
0
12 PADDR
Reset Value MSB
0000000
LSB
0
13 PAOR
Reset Value MSB
0000000
LSB
0
14 PAPUCR
Reset Value MSB
0000000
LSB
0
15 PBDR
Reset Value MSB
0000000
LSB
0
16 PBOR
Reset Value MSB
0000000
LSB
0
17 PBPUCR
Reset Value MSB
0000000
LSB
0
18 PCDR
Reset Value MSB
0000000
LSB
0
19 PDDR
Reset Value MSB
0000000
LSB
0
1A PDOR
Reset Value MSB
0000000
LSB
0
1B PDPUCR
Reset Value MSB
0000000
LSB
0
1
ST7SCR
36/102
10 MISC ELLANEOUS R EGISTERS
MISCELLANEOUS REGISTER 1 (MISCR1)
Reset Value : 0000 0000 (00h)
Read/Write
Writing the ITIFREC register enables or disables
external interrupt on Port C. Each bit can be
masked independantly. The ITMx bit masks the
external interrupt on PC.x.
Bi ts [7:0] = ITM [7:0]
Interrupt Mask
0: external interrupt disabled
1: external interrupt enabled
MISCELLANEOUS REGISTER 2 (MISCR2)
Reset Value : 0000 0000 (00h)
Read/Write
Writing the ITIFREA register enables or disables
external interrupt on port A .
Bit 7 = Reserved.
Bit 6 = CRDIRM
CRD Insertion /Removal Interrupt
Mask
0: CRDI R interrupt disabl ed
1: CRDI R interrupt enabled
Bits [5:0] = ITM [14:9]
Interr u p t Mask
Bit x of MISCR2 masks the external interrupt on
port A.x.
Bit x = IT M
n
Interrupt Mask n
0: external interrupt disabled on PA.x.
1: external interrupt enabled on PA.x.
70
ITM
7ITM
6ITM
5ITM
4ITM
3ITM
2ITM
1ITM
0
70
-
CRD
IRM ITM
14 ITM
13 ITM
12 ITM
11 ITM
10 ITM
9
1
ST7SCR
37/102
MISCELLANEOUS REGISTER 3 (MISCR3)
Reset Value: 0000 0000 (00h)
Read/Write
This register is used to configure the edge and the
level sensitivity of the Port A and Port C external
interrupt. This means that all bits of a port must
have t he same sensitivity.
If a write access modifies bits 7:4, it clears the
pending int errupts.
CTRL0_C, CTRL1_C : Sensitivity on port C
CTRL0_A, CTRL1_A : Sensitivity on port A
MISCELLANEOUS REGISTER 4 (MISCR4)
Reser Value : 0000 0000 (00h).
Read/Write
Bit 7 = Reserved.
Bit 6 = PLL_ON
PLL Activation
0: PLL disabled
1: PLL enabled
Note: The PLL must be disabled before a HALT
instruction.
Bit 5 = CLK_SEL
Clock Sele ction
This bit is s et and cleared by software.
0: CPU frequency = 4MHz
1: CPU frequency = 8MHz
Bits 4:1 = Reserved.
Bit 0 = LOCK
PLL sta tus bit
0: PLL not lock ed. fCPU = fOSC ex ternal clock fre-
quency.
1: PLL locked. fCPU = 4 or 8 MHz depending on
CLKSEL bit.
70
CTR
L1_A CTR
L0_A CTR
L1_C CTR
L0_C ----
CTR
L1_X CTR
L0_X External
Interrupt Sensitivity
0 0 Falling edge & low level
0 1 Rising edge only
1 0 Falling edge only
1 1 Rising and falling edge
70
-
PLL
_ON CLK_
SEL - - - - LOCK
1
ST7SCR
38/102
MISC EL LANEOUS REGISTERS (Con t’d)
Table 13. R egister Ma p and Reset Values
Address
(Hex.) Regist er
Label 76543210
001C MISCR1
Reset Value ITM7
0ITM6
0ITM5
0ITM4
0ITM3
0ITM2
0ITM1
0ITM0
0
001D MISCR2
Reset Value 00
ITM14
0ITM13
0ITM12
0ITM11
0ITM10
0ITM9
0
001E MISCR3
Reset Value CTRL1_A
0CTRL0_A
0CTRL1_C
0CTRL0_C
00000
001Fh MISCR4
Reset Value 0PLL_ON
0RST_IN
0CLK_SE
0L 000
LOCK
0
1
ST7SCR
39/102
11 LEDs
Each of the four available LEDs can be selected
using the LED_CT RL regist er. Two types of LE Ds
are supported: 3mA and 7mA .
LED_CTRL REGISTER
Reset Value: 0000 0000 (00h)
Read/Write
Bits 7:4 = LDx
LED Enable
0: LED disabled
1: LED enabled
Bits 3: 0 = L Dx_I
Curren t selection on LDx
0: 3mA current on LDx pad
1: 7mA current on LDx pad
70
LD3 LD2 LD1 LD0 LD3_I LD2_I LD1_I LD0_I
1
ST7SCR
40/102
12 ON- CHIP PERIP HERALS
12.1 WATCHDOG TIMER (WDG)
12.1.1 Introduc tion
The Watchdog timer is used to detect the occur-
rence of a software fault, usual ly generated by ex-
ternal interference o r by unfores een logi cal cond i-
tions, which causes the application program to
abandon it s normal seque nce. The W atchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed t ime peri od, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
12.1.2 Mai n Features
■Programmable timer (64 increments of 65536
CPU cycles)
■Program m able reset
■Reset (if watchdog activated) when the T6 bit
reaches zer o
■Hardware Watchdog s electable by option byte
■Watchdog Reset indicated by status flag
12.1.3 Functional Descri ption
The counter value stored in the CR register (bits
T[6:0]), is decremente d every 65,5 36 m achine cy-
cles, and the length of the timeout period can be
programme d by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40 h to 3Fh (T6 bec omes cleared ), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see T able 14):
– The WDGA bit is set (wat chdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increment s
which represents the t ime delay before the
watchdog produces a reset.
Table 14 .Watchdog Timin g (fCPU = 8 MH z)
Fi gure 25. Watchdog B lock Diag ram
CR Register
initial value WDG timeout period
(ms)
Max FFh 524.288
Min C0h 8.192
RESET
WDGA
7-BIT DOWNCOU NTER
fCPU
T6 T0
CLOCK DIVIDER
WATCHDOG CONTROL REGISTER (CR)
÷65536
T1
T2
T3
T4
T5
1
ST7SCR
41/102
WATCHDOG TI MER (Cont’d)
12.1.4 So ftware Watch dog Op tion
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a s of tw are re-
set (the WDGA bi t is set and the T6 bit is cl eared).
12.1.5 Hardware Watchdog Option
If Hardware W atchdog is selected by option b yte,
the watchdog is always active and the WDGA bit in
the CR is not used.
12.1.6 Low P owe r Mo des
WAIT Instruction
No effect on Watchdog.
HALT Instruction
Halt mode can be used when the w atchdo g is en-
abled. When the oscillator is stopped, the WDG
stops count i ng and is no l onger able to generate a
reset until t he microcontrol ler receives an external
interrupt or a reset.
If an external interrupt is received, the WDG re-
starts coun ting after 514 CPU clocks. In the case
of the Software Watchdog option, if a r eset is gen-
erated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event is available to
wake up the microcont roller from Halt mode.
– Before executing the HALT instruction, refres h
the WDG count er, to avoid an unexpected WDG
reset immediately after waking up the microc on-
troller.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as Input before executi ng the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HAL T instruction due to a
program counter failure, it i s advised to clear all
occurrences of the data value 0x 8E from memo-
ry. For example, avoid defining a constan t in
ROM with the value 0x8E.
– As the HALT instruction cl ears the I bi t in the CC
register to allo w inter rupts, the user may choose
to clear all pending i nterrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the ex ternal interrupt rout ine correspondi ng to
the wake-up event (reset or external interrupt).
12.1.7 In terrupts
None.
12.1.8 Register Descrip tion
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA
Activation bit
.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generat e a reset.
0: Wat chdog disabled
1: Wat chdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over fro m 40h to 3Fh (T6
becomes cleared).
70
WDGA T6 T5 T4 T3 T2 T1 T0
1
ST7SCR
42/102
12.2 TIME BASE UNIT (TBU)
12.2.1 Introduc tion
The Tim ebase unit (TBU) can be used to generate
periodic interrupts.
12.2.2 Mai n Features
■8-b it upcounter
■Program m able prescaler
■Period between interrupts: max. 8.1ms (at 8
MHz fCPU )
■Maskabl e interrupt
12.2.3 Functional Descri ption
The TBU operates as a free-running upcount er.
When the TCEN bit in the TBUCS R register is set
by software, counti ng starts at the current value of
the TBUCV register. The TBUCV register is incre-
mented at the clock rate output from the prescaler
selected by programming the PR[2:0] bits in the
TBUCSR register.
When the counte r rolls over from FFh to 00 h, the
OVF bit i s set and a n in terrupt request is gene rat-
ed if ITE is set.
The user can write a value at any time in the
TBUCV register.
12.2.4 Programming Ex ampl e
In this example, timer is required to generate an in-
terrupt after a delay of 1 ms.
Assumi ng that fCPU i s 8 MHz and a pres caler divi-
sion factor of 256 will be programmed using the
PR[2:0] bits in the TBUCSR register, 1 ms = 32
TBU ti mer ticks.
In this case, the initial value to be loaded in the
TBUCV must be (256-32) = 224 (E0h).
ld A, E0h
ld TBUCV, A ; Initialize counter value
ld A 1Fh ;
ld TBUCSR, A ; Prescaler factor = 256,
; interrupt enable,
; TBU enable
Figure 26. TBU Block Diagram
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
INTERRUPT REQUE ST
TBU PRESCALER
fCPU
TBUCSR REGISTER
PR1 PR0PR2TCENITEOVF
MSB LSB
0
0
1
TBU
0
1
ST7SCR
43/102
TIMEBASE UNIT (Cont’d)
12.2.5 Low P owe r Mo des
12.2.6 Interrupts
Note: T he OVF interrupt ev ent is co nnecte d to an
interrupt vector (see Int errupts chapter).
It ge nerate s an interrupt if the ITE bit is set in th e
TBUCSR register and the I-bit in the CC regist er is
reset (RIM instruction).
12.2.7 Register Description
TBU COUNTER VALUE REGI STER (TBUCV)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = CV[7:0]
Counte r Value
This register contains the 8-bit counter value
which can be read and written anytime by soft-
ware. It is cont inuously increment ed by hardwar e if
TCEN=1.
TBU CONT ROL/S TATUS REGISTER (TBUCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits [7:6] = Reserved. Forced by hardware to 0
.
Bit 5 = OVF
Overflow Flag
This bit is s et only by ha rd ware, when t he count er
value rolls over from FFh to 00h. It is cleared by
software re ading the TBUCSR register. Writing to
this bit does not change the bit value.
0: No overflow
1: Counter overflow
Bit 4 = ITE
Interrupt enabled.
This bit is s et and cleared by software.
0: Overf l ow interrupt disabled
1: Overflow interr upt enabled. An i nterrupt request
is generated when OVF=1.
Bit 3 = TCEN
TBU Enable.
This bit is s et and cleared by software.
0: TBU counter is frozen and the prescaler is reset .
1: TBU counter and prescaler running.
Bits 2:0 = PR[2:0]
Pres ca ler Selection
These bits are set and cleared by software to se-
lect the prescaling factor.
Mode Description
WAIT No effect on TBU
HALT TB U halted.
Interrupt
Event Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Counter Over-
flow Event OVF ITE Yes No
70
CV7 CV6 CV5 CV4 CV3 CV2 CV1 CV0
70
0 0 OVF ITE TCEN PR2 PR1 PR0
PR2 PR1 PR0 Prescaler Division Factor
000 2
001 4
010 8
011 16
100 32
101 64
110 128
111 256
1
ST7SCR
44/102
12.3 USB INTERFACE (USB)
12.3.1 Introduc ti on
The USB Interface implements a full-speed func-
tion interface between the USB and the ST7 mi-
crocontroller. It is a highly integrated circuit whi ch
includes the transceiver, 3.3 voltage regulat or, SIE
and USB Data Buffer interface. No external com-
ponents are needed apart from the external pull-
up on USBDP for full speed recognition by the
USB host.
12.3.2 Main Features
■USB Sp ecification Version 1.1 Compliant
■Supp orts Full-Speed USB Protocol
■Seven E ndpoi nts (including def ault endpoint)
■CRC generation/checking, NRZI encoding/
dec oding and bit-stuff ing
■USB Su spend/ Resume operations
■On-Chip 3.3V Regul ator
■On-Chip USB Transceiver
12.3.3 Functional Description
The block diagram in Figure 27, gives an over view
of the US B interface hardware.
For general information on the USB, refer to the
“Universal Serial Bus Specifications” document
available at http//:www. usb.org.
Serial Interface Eng ine
The SIE (Serial Interface Engine) interfaces with
the USB, via the transceiver.
The SIE processes tokens , handles data transmis-
sion/reception, and handshaking as required by
the USB sta ndard. It also performs frame format-
ting, including CRC generation and checking.
Endpoints
The Endpoi nt regist ers indicate if the microcontrol-
ler is ready to transmit/receive, and how many
bytes need to be transmitted.
Data Transfer to/from USB Data Buffer Memor y
When a token for a valid Endpoint is recognized by
the USB interface, the related data transfer takes
place to/from the USB data buffer. At the end of
the transaction, an i nterrupt is generated.
Interrupts
By reading the Interrupt Status register, applica-
tion software can know w hich USB e vent has oc-
curred.
Figure 27. USB Block Diagram
CPU
Transceiver
3.3V
Voltage
Regulator
SIE
ENDPOINT
BUFFER
USB
Address,
and interrupts
USBDM
USBDP
USBVCC
48 MHz
REGISTERS
REGISTERS
data busses
USBGND
BUFFER
USB
DATA
INTERFACE
1
ST7SCR
45/102
USB INTERFACE (Cont’d)
USB Endpoint RAM Buffers
There are seven End points including one bidirec-
tional control Endpoint (Endpoint 0), five IN End-
points (Endpoi nt 1, 2, 3, 4, 5) and one OU T e nd-
point (Endpoint 2).
Endpoi nt 0 is 2 x 8 byte s in si ze , End point 1, 3, 4,
and Endpoi nt 5 are 8 by tes in size and Endpoint 2
is 2 x 64 bytes in size .
Fi gure 28. Endpoi nt Bu ffer S i ze
Endpoin t 2 Buffe r OUT
Endpoin t 1 Buffe r IN
Endpoin t 0 Buffe r IN
Endpoin t 0 Buffe r OUT
Endpoin t 2 Buffe r IN
8 Bytes
8 Bytes
8 Bytes
64 Bytes
64 Bytes
Endpoint 3 Buffer IN 8 Bytes
Endpoint 5 Buff er IN
Endpoint 4 Buffer IN 8 Bytes
8 Bytes
1
ST7SCR
46/102
USB INTERFACE (Cont’d)
12.3.4 Register Description
INTERRUPT ST ATUS REGISTER (USBIST R)
Read/Write
Reset Value: 0000 0000 (00h)
These bits cannot be set by software. When an in-
terrupt occurs t hes e bits are set by hardwar e. Soft-
ware must read them to determine the interrupt
type and clear them after servicing.
Note: T he CT R bit (whi ch is an OR of a ll the e nd-
point CTR flags) cannot be cleared directly, only
by clearing the CTR flags in the Endpoint regis-
ters.
Bi t 7 = CTR
Correct Transf er
.
This bit is set by hardware when a correct t ransfer
operation is performed. This bit is an OR of all
CTR flags (CTR0 in the EP0R register and
CTR_RX and CTR_TX in the EPnRXR and EP-
nTXR registers). By looking in the USBSR regis-
ter, the type of transfer can be determined from the
PID[1:0] bits for Endpoint 0. For the other End-
points, the Endpoint number on which the transfer
was made is identified by the EP[1:0] bits and the
type of t ransfe r by the IN/OUT bit.
0: No Correct Transf er detected
1: Correct Transf er det ected
Note: A transfer where the device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overruns, bit
stuffing or framing errors.
Bit 6 = Reserved, forced by hardware t o 0.
Bi t 5 = SOVR Setup Overrun.
This bit is set by hardware when a correct Setup
transfer operation is performed whil e the s oftw are
is servicing an interrupt which occured on the
same Endpoint (CTR0 bit in the EP0R register is
still set when SET UP correct transfer occurs).
0: No SETUP overrun detected
1: SETUP overrun detected
When this event occ urs, the USBS R regi st er is not
updated because the only source of the SOVR
event is the SETUP token reception on the Control
Endpoi nt (EP0).
Bit 4 = ERR
Error
.
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
1: Timeout, CRC, bit st uffing, nonstandard
frami ng or buffer overrun error detected
Note: Refer to the ERR[2:0] bits in the USBSR
register to determine the error ty pe.
Bit 3 = SUSP
Suspend mo de request
.
This bit is set by hardware when a constant idle
state is present on the bus li ne f or more than 3 ms,
indicating a suspend mode request from the USB.
The suspend request check is active imm ediately
after each USB reset event and is disabled by
hardware when suspend mode is forced (FSUSP
bit in the USBCTLR register) until the end of
resume sequence.
Bit 2 = ESUSP
End Suspend mode
.
This bit is se t by hardware when, during suspend
mode, a ctivity is detected that wakes t he USB in-
terface up from suspend mo de.
This interrupt is serviced by a specific vector, in or-
der to wake up the S T7 from HALT mode.
0: No End Suspend detected
1: End Suspend detec ted
Bit 1 = RESET
USB rese t.
This bit is set by hardware when the USB reset se-
quence is detected on the bus.
0: No USB reset signal detected
1: USB reset signal detected
Note: The DADDR, EP0R, EP1RXR, EP1TXR,
EP2RXR and EP2TXR registers are reset by a
USB rese t.
Bit 0 = SOF
Start of frame.
This bit is set by hardware when a SOF t oken is re-
ceived on the USB.
0: No SOF received
1: SOF received
Note: To avoid spurious clearing of some bits, it is
recomme nded to clear th em u sing a load instruc-
tion where all bits which must not be altered are
set, and all bits to be cleared are reset. Avoid read-
modify-write instructions like AND, XOR...
70
CTR 0 SOVR ERROR SUSP ESUSP RESET SOF
1
ST7SCR
47/102
USB INTERFACE (Cont’d)
INTERRUPT MAS K REGISTER (USBIMR)
Read/Write
Reset Value: 0000 0000 (00h)
These bits are mask bits for all the interrupt condi-
tion bits included i n t he USBISTR regist er. When-
ever one of the USBIMR bits is set, if the corre-
sponding USBISTR bit is set, and the I- bi t in the
CC register is cleared, an interrupt request is gen-
erated. For an explanation of each bit , please refer
to the desc ri ption of t h e USBISTR register.
CONTROL REGISTER (U SBCTLR)
Read/Write
Reset value: 0000 0110 (06h)
Bi t 7 = RSM
Resume Detected
This bit shows when a resume sequence has start-
ed on the USB port, requesting the USB interface
to wake-up from suspend state. It can be used to
determine the cause of an ESUSP eve nt.
0: No resume sequence detected on USB
1: Resume sequence detec ted on USB
Bi t 6 = U SB_RST
USB
Reset detected
.
This bit shows that a reset sequence has started
on the USB. I t can be used to determine the cause
of an ESUSP event (Reset sequence).
0: No reset s equen ce detect ed on USB
1: Reset s equ enc e detected on USB
Bits [5:4] = Reserved, forc ed by hardware to 0.
Bit 3 = RESUME
Resume
.
This bit is set by software to wake-up the Host
when the ST7 is in suspend mode.
0: Res ume signal not forced
1: Resume signal forced on the USB bus.
Software should clear this bit after t he appropriate
delay.
Bit 2 = PDWN
Power down
.
This bit is set by software to turn off the 3.3V on-
chip voltage regulator that supplies the external
pull-up resistor and the transceiver.
0: Voltage regulator on
1: Voltage regulator off
Note: After turning on the voltage regulator, soft-
ware sh ould allow at le ast 3 µs f or stabilisation of
the power supply before using the USB interface.
Bit 1 = FSUSP
Force suspend mode
.
This bit is set by s oftware to enter Suspend mode.
The ST7 should also be put in Halt mode to reduce
power consum pt ion.
0: Suspend mode inactive
1: Suspend mode active
When t he ha rdware det ects USB activity, it resets
this bit (it can also be reset by sof tware).
Bit 0 = FRES
Force res e t.
This bit is set by software to force a reset of the
USB interface, just as i f a RESET sequence came
fro m th e USB.
0: Res et not forced
1: USB interface reset forced.
The USB is held in RESET state until software
clears this bit, at which point a “USB-RESET” in-
terrupt will be generated if enabled.
70
CTRM 0 SOVR
MERRM SUSP
MESUSP
MRESET
MSOFM
70
RSM USB_
RST 00
RESU
ME PDWN FSUSP FRES
1
ST7SCR
48/102
USB INTERFACE (Cont’d)
DEVICE ADDRESS REGI STER (DADDR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = Reserved, forced by hardware t o 0.
Bits 6:0 = ADD[6:0]
Device address, 7 bits.
Software must write into this register the address
sent by t he host during enum eration.
Note: This register is also reset when a USB reset
is received or f orced throug h bit FRES in the US -
BCTLR register.
USB STATUS REGIST ER (USBSR)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:6 = PID[1:0]
Token PID bits 1 & 0 for End-
point 0 Control
.
USB token PI Ds are encoded in four bits. PID[1:0]
correspond to the most significant bits of the PID
field of th e last token PID receiv ed by Endpoin t 0.
Note: The least significant PID bits have a fixed
value of 01.
When a CTR interrupt occurs on Endpoint 0 (see
register USBISTR) the software should read the
PID[1:0] bits to retrieve the PID name of the token
received.
The USB specification defines PID bits as:
Bi t 5 = IN/OUT
Last transact ion direction for E nd-
point 1, 2 , 3, 4 or 5.
This bit is set by hardware when a CTR interrupt
occurs on Endpoin t 1, 2, 3, 4 or 5.
0: OUT transaction
1: IN transaction
Bits 4:3 = Reserved, forced by hardware to 0.
Bits 2:0 = EP[2:0]
Endpoint number.
These bits identify the endpoint which required at-
tention.
000 = Endpoi nt 0
001 = Endpoi nt 1
010 = Endpoi nt 2
011 = Endpoi nt 3
100 = Endpoi nt 4
101 = Endpoi nt 5
ERROR STATUS REGISTER (ERRS R)
Read only
Reset Value: 0000 0000 (00h)
Bits 7:3 = Reserved, forced by hardware to 0.
Bits 2:0 = ERR[2:0]
Error type
.
These bits identify the type of error which oc-
curred.
Note: these bits are set by hardware when an er-
ror interrupt occurs and are reset automatically
when the error bit (USBISTR bit 4) is cleared by
software.
70
0 ADD6ADD5ADD4ADD3ADD2ADD1ADD0
70
PID1 PID0 IN/
OUT 0 0 EP2 EP1 EP0
PID1 PID0 PID Name
00 OUT
10 IN
1 1 SETUP
70
00000ERR2ERR1ERR0
ERR2 ERR1 ERR0 Meaning
0 0 0 No error
0 0 1 Bitstuffing error
0 1 0 CRC error
011
EOP error (unexpected end of
packet or SE0 not followed by
J-state)
100
PID error (PID encoding error,
unexpected or unknown PID)
101
Memory over / underrun (mem-
ory controller has not an-
swered in time to a memory
data request)
111
Other error (wrong packet,
timeout error)
1
ST7SCR
49/102
USB INTERFACE (Cont’d)
EN DP OI N T 0 REGIST ER ( EP0 R)
Read/Write
Reset value: 0000 0000(0 0h)
This r eg is t er is us ed fo r co nt r olling Endpoint 0.
Bits 6:4 and bits 2:0 are also reset by a USB reset,
either received from the USB or forced through t he
FRES bit in USBCTLR.
Bi t 7 = CTR0
Correct Transf er
.
This bit is set by hardware when a correct t ransfer
operation is performed on Endpoint 0. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR on Endpoint 0
1: Correct t ransfer on Endpoint 0
Bit 6 = DTOG_TX
Data Toggle, for transmission
transfers
.
It contains the required value of the toggle bit
(0=DATA0, 1=DATA1) for the next transmitted
data packet. This bit is set by hardware on recep-
tion of a SETUP PID. DTOG_TX toggles only
when the transmitter has received the ACK signal
from the USB host. DTOG_TX and also
DTOG_RX are normally updat ed b y hardware, on
receipt of a r elevant PID. They can be also writt en
by the user, both for testing purposes and to force
a specific (DATA0 or DATA1) token.
Bits 5:4 = STAT_TX [1:0]
Status bits, for transmis-
sion transfers
.
These bits contain the information about the end-
point status, which are listed below
Table 15. Transmission Status Encoding
These bits are written b y s oftware. Hardware s ets
the STAT_TX and STAT_RX bits to NAK when a
correct transfer has occurred (CTR=1 ) addressed
to this endpoint; this allows software to prepare the
next set of data to be trans m itted .
Bit 3 = Reserved, forced by hardware to 0.
Bit 2 = DTOG_RX
Data Toggle, for reception
transfers
.
It contains the expected value of the toggle bit
(0=DATA0, 1=DATA1) for the next data packet.
This bit is cleared by hardware in the first stage
(Setup Stage) of a c ontrol tran sfer (SETUP trans-
actions start al ways with DATA0 PI D). The receiv-
er toggles DTOG_RX only if it receives a correct
data packet and the packet’s data PID matches
the receiver sequence bit.
70
CTR0 DTOG
_TX STAT_
TX1 STAT_
TX0 0DTOG
_RX STAT_
RX1 STAT_
RX0
STAT_TX1 STAT_TX0 Meaning
00
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
01STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
10NAK: the endpoint is NAKed
and all transmission requests
result in a NAK handshake.
11
VALID: this endpoint is enabled
(if an address match occurs, the
USB interface handles the
transaction).
1
ST7SCR
50/102
USB INTERFACE (Cont’d)
Bits 1:0 = STAT_RX [1:0]
St atus b its , for rece ption
transfers
.
These bit s contain the inf ormation abo ut the e nd-
point status, which are lis ted below:
Table 16. R eception Status Encodin g
These bits are written by sof tware. Hardware set s
the STAT_RX a nd STAT_TX bits to NAK when a
correct transfer has occurred (CTR=1) ad dressed
to t his endpoint, so the software has the t ime to ex-
amine the received data before acknowledging a
new transaction.
Note 1:
If a SETUP transacti on is received whil e the status
is different from DISABLED, it is ack nowleded and
the two directional status bits are set to NAK by
hardware.
Note 2:
When a STALL is answered by the USB device,
the two directional st at us bits are set to S T ALL by
hardware.
ENDPOINT TRANSMISSION REGISTER
(EP1TXR, EP2TXR, EP3TXR, EP4TXR,
EP5TXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controlling Endpoint 1, 2,
3, 4 or 5 transmiss ion. B its 2 :0 are also reset by a
USB reset, either received from the USB or forced
through the FRES bit in t he US BCTLR register.
Bits [7:4] = Reserved, forc ed by hardware to 0.
Bit 3 = CTR_TX
Correct Transm ission Transfer
.
This bit is set by hardwar e when a correct transfer
operation is performed in transmission. This bit
must be cleared after the corresponding interrupt
has been serviced.
0: No CTR in transmission on Endpoint 1, 2, 3, 4 or
5
1: Correct transfer in transmission on Endpoint 1,
2, 3, 4 or 5
Bit 2 = DTOG_TX
Data Toggle, for transmission
transfers
.
This bit contains the required value of the toggle
bit (0=DATA0, 1=DATA1) for the next data packet.
DTOG_TX toggles only when the transmitter has
received the ACK signal from the USB host.
DTOG_TX and DTOG_RX are normally updated
by har dware, at t he recei pt of a relevant PID. They
can be also written by the user, both for testing
purposes and to force a specific (DATA0 or
DATA1) token.
Bits [1:0] = STAT_TX [1:0]
Status bits, for trans-
mission transfers
.
These bits contain the information about the end-
point status, which is listed below
Table 17. Transmission Status Encoding
These bits are written by software, but hardware
sets the STAT_TX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint. This allows software to prepare the next
set of data to be transmitted.
STAT_RX1 STAT_RX0 Meaning
00
DISABLED: no function can be
executed on this endpoint and
messages related to this end-
point are ignored.
01
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
10
NAK: the endpoint is NAKed
and all reception requests re-
sult in a NAK handshake.
11
VALID: this endpoint is ena-
bled (if an address match oc-
curs, the USB interface
handles the transaction).
70
0000
CTR_T
XDTOG
_TX STAT_
TX1 STAT_
TX0
STAT_TX1 STAT_TX0 Meaning
00
DISABLED: transmission
transfers cannot be executed.
01
STALL: the endpoint is stalled
and all transmission requests
result in a STALL handshake.
10
NAK: the endpoint is naked
and all transmission requests
result in a NAK handshake.
11
VALID: this endpoint is ena-
bled for transmission.
1
ST7SCR
51/102
USB INTERFACE (Cont’d)
ENDPOINT 2 RECEPTION REGISTER
(EP2RXR)
Read/Write
Reset value: 0000 0000 (00h)
This register is used for controll ing Endpoint 2 re-
ception. Bits 2:0 are also reset by a USB reset , ei-
the r rec eive d from the USB or f orce d throu gh th e
FRES bit in the USBCT LR register.
Bits [7:4] = Reserved, forced by hardware to 0.
Bi t 3 = C TR_RX
Reception Correct Transfer
.
This bit is set by hardware when a correct t ransfer
operation is performed in reception. Th is bit must
be cleared after that the corresponding interrupt
has been serviced.
Bit 2 = DTOG_RX
Data Toggle, for reception
transfers
.
It contains the expected value of the toggle bit
(0=DATA0, 1 =DATA1) for the next data packet.
The receiver toggles DTO G_RX only if it receives
acorrect data packet and the packet’s data PID
matches the receiv er sequence bit.
Bits [1:0] = STAT_RX [1:0]
Status bits, for recep-
tion transfers
.
These bits contain the information about the end-
point status, which is list ed below:
Table 18. Reception Status Encoding
These bits are written by software, but hardware
sets the STAT_RX bits to NAK when a correct
transfer has occurred (CTR=1) addressed to this
endpoint , so the software has the time to examine
the received data before acknowledging a new
transaction.
70
0000
CTR_R
XDTOG
_RX STAT_
RX1 STAT_
RX0
STAT_RX1 STAT_RX0 Meaning
00
DISABLED: reception trans-
fers cannot be executed.
01
STALL: the endpoint is stalled
and all reception requests re-
sult in a STALL handshake.
10
NAK: the endpoint is naked
and all reception requests re-
sult in a NAK handshake.
11
VALID: this endpoint is ena-
bled for reception.
1
ST7SCR
52/102
USB INTERFACE (Cont’d)
RECEPTION COUNTER REGISTER (CNT0RXR)
Read/Write
Reset Value: 0000 0000 (00h)
This registe r contains t he allocated buf fer size for
endpoint 0 reception, setting the maximum
number of bytes the re lated endpoint can receive
with the next OUT or SETUP transaction. At the
end of a re ception, the value of thi s register is th e
max size decrem ented by the number of bytes re-
ceived (to determine the number of bytes re-
ceived, the software must subtract the content of
this register from the alloc ated buffer si ze).
TRANSMISSIO N COUNTER REGISTER
(CNT0TXR, CNT1TXR, CNT3TXR, CNT4TXR,
CNT5TXR)
Read/Write
Reset Val ue 0000 0000 (00h)
This register contains the number of bytes to be
transmitted by Endpo int 0, 1, 3, 4 or 5 at th e next
IN token addressed to it.
RECEPTION COUNTER REGISTER (CNT2RXR)
Read/Write
Reset Value: 0000 0000 (00h)
This regist er contains the allocated b uff er size for
endpoint 2
reception, setting the maximum
number of bytes the related endpoint can receive
with the next OUT transaction. At t he end of a re-
ception, the value of this register is the max size
decrement ed by the number of by tes received (to
determ ine the num ber of bytes rec eived, the sof t-
ware must subtract the content of t his register f rom
the allocated buffer size).
TRANSMISSION COUNT ER REGISTER
(CNT2TXR)
Read/Write
Reset Value 0000 0000 (00h)
This register contains the number of bytes to be
transmi tted by En dpoint 2 at the next IN token ad-
dressed to it.
70
0 0 0 0 CNT3 CNT2 CNT1 CNT0
70
0 0 0 0 CNT3 CNT2 CNT1 CNT0
70
0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT CNT0
70
0 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
1
ST7SCR
53/102
USB INTERFACE (Cont’d)
Table 19. USB Register Ma p and Reset values
Address
(Hex.) Register
Name 76543210
20 USBISTR
Rese t Va l ue CTR
00
0SOVR
0ERR
0SUSP
0ESUSP
0RESET
0SOF
0
21 USBIMR
Rese t Va l ue CTRM
00
0SOVRM
0ERRM
0SUSPM
0ESUSPM
0RESETM
0SOFM
0
22 USBCTLR
Rese t Va l ue RSM
0USB_RST
000
RESUME
0PDWN
1FSUSP
1FRES
0
23 DADDR
Rese t Va l ue 0ADD6
0ADD5
0ADD4
0ADD3
0ADD2
0ADD1
0ADD0
0
24 USBSR
Rese t Va l ue PID1
0PID0
0IN /OUT
000
EP2
0EP1
0EP0
0
25 EP0R
Rese t Va l ue CTR0
0DTOG_TX
0STAT_TX1
0STAT_TX0
00
0DTOG_RX
0STAT_RX1
0STAT_RX0
0
26 CNT0RXR
Rese t Va l ue 00 0 0
CNT3
0CNT2
0CNT1
0CNT0
0
27 CNT0TXR
Rese t Va l ue 00 0 0
CNT3
0CNT2
0CNT1
0CNT0
0
28 EP1TXR
Rese t Va l ue 00 0 0
CTR_TX
0DTOG_TX
0STAT_TX1
0STAT_TX0
0
29 CNT1TXR
Rese t Va l ue 00 0 0
CNT3
0CNT2
0CNT1
0CNT0
0
2A EP2RXR
Rese t Va l ue 00 0 0
CTR_RX
0DTOG_RX
0STAT_RX1
0STAT_RX0
0
2B CNT2RXR
Rese t Va l ue 0CNT6
0CNT5
0CNT4
0CNT3
0CNT2
0CNT1
0CNT0
0
2C EP2TXR
Rese t Va l ue 00 0 0
CTR_TX
0DTOG_TX
0STAT_TX1
0STAT_TX0
0
2D CNT2TXR
Rese t Va l ue 0CNT6
0CNT5
0CNT4
0CNT3
0CNT2
0CNT1
0CNT0
0
2E EP3TXR
Rese t Va l ue 00 0 0
CTR_TX
0DTOG_TX
0STAT_TX1
0STAT_TX0
0
2F CNT3TXR
Rese t Va l ue 00 0 0
CNT3
0CNT2
0CNT1
0CNT0
0
30 EP4TXR
Rese t Va l ue 00 0 0
CTR_TX
0DTOG_TX
0STAT_TX1
0STAT_TX0
0
31 CNT4TXR
Rese t Va l ue 00 0 0
CNT3
0CNT2
0CNT1
0CNT0
0
32 EP5TXR
Rese t Va l ue 00 0 0
CTR_TX
0DTOG_TX
0STAT_TX1
0STAT_TX0
0
1
ST7SCR
54/102
33 CNT5TXR 0 0 0 0 CNT3
0CNT2
0CNT1
0CNT0
0
34 ERRSR 0 0 0 0 0 ERR2
0ERR1
0ERR0
0
Address
(Hex.) Register
Name 76543210
1
ST7SCR
55/102
12.4 SMARTCAR D INTERFACE (CRD)
12.4.1 Introduc ti on
The Smartcard Interface (CRD) provides all the re-
quired signals for acting as a smartcard interface
device.
The interface is electrically compatible with (and
certifiable to) t he ISO7816, EMV, GS M and WHQL
standards.
Both synchronous (e.g. mem ory cards) and asyn-
chronous smartcards (e.g. microprocessor cards)
are supported.
The CRD generates the required voltages to be
applied to the smart card lines.
The power -off sequence is managed by the CRD.
Card insertion or card removal is detected by the
CRD using a card presence switch connected to
the external CRDDET pin. If a card is removed, the
CRD automatically deactivates the smartcard us-
ing the ISO7816 deactivation sequence.
An maskable interrupt is generated when a card is
i nserted or removed.
Any malfunction is repo rted to th e microcontroller
via the Smartcard Interrupt Pending Register
(CRDIPR) and Smart card Status (CRDSR) Regis-
ters.
12.4.2 Main features
■Support for ISO 7816-3 standard
■Character mode
■1 transmit buffer and 1 receive buffer
■4-Mhz fixed card clock
■11-bit etu (elementary time unit) c oun ter
■9-bit guardtim e counter
■24-bit general purpose waiting time counter
■Parity generation and checking
■Automatic character repetition on parity error
detection in transmission mode
■Automatic retry on parity error detection in
reception mode
■Card power-off deactivation sequence
generation
■Manual mode for driving the card I/O directly for
synchronous protocols
12.4.3 Functional Description
Figure 29 gives an overview of t he smartcard inter-
face.
Figure 29. S m artcard Interface Block Diag ram
CLK
SEL CRD
CLK
CRDCCR
IO
CRD CRD CRD
RST VCC
C8
CRD
C4
CRD
CRDIO
CRDC4
CRDC8
CRDRST
CRDCLK
CRDDET
0
1
UART SHIF T REGISTE R
CRDRXB CRDTXB
UART RECEIVE BUFFER UART TRA NSMIT BUFFER CARD DE T ECT ION
CARD INSERTION/
CRDVCC
POWER-OFF LOGIC
CLOCK
CONTROL
UART BIT
11-BIT
4 MHz
ETU COUNTER
9-BIT GUARDTIME COUNTER
24-BIT WAITIN G TIME COUNTER
PARITY GENERATION/CHECKING
COMMUNICATIONS CONTROL
CRD INTERRUPT
LOGIC
REMOVAL INTERRUPT
1
ST7SCR
56/102
SMARTCARD INTERFACE (Cont’d)
12.4.3.1 Powe r Su pply Ma nag em ent
Smartcard Power Supply Selection
The Smartcard interface consists of a power sup-
ply output on the CRDVCC pin and a set of card in-
terface I/Os which are powered by the same rail.
The card voltage (CRDVCC) is user programma-
ble via the VCARD [1:0] bits in the CRDCR regis-
ter (refer to the Smartcard Interface section).
Four voltage values can be selected:
5V, 3 V, 1.8 V or 0V.
Current Overload Detection and Card Removal
For each voltage, when an overload current is de-
tected (refer to Section 12.4 on page 55), o r when
a card is removed, the CRDVCC power supply
output is directly connected to ground.
12.4.3.2 I/O Driving Mode s
Smartcard I/Os are driven in two pri ncipal modes:
– UART mode (i.e. when the UART bit of the
CRDCR registe r is set)
– Manua l mode , driven directly by soft ware using
the Smart card Contact register (i.e. when the
UART bit of the CRDCR register is reset).
Card power-on activation must driven by software.
Card deactivation is hand led automatically by the
Power-off functi onal state machine hardware.
12.4.3.3 UART M ode
Two registers are connected to the UART shift
registe r: CRDTXB for transmission a nd CRDRXB
for reception. They act as buffers to off-load the
CPU.
A parity checker and generator is coupled to the
shifter.
Character repetition and retry are su pporte d.
The UART is in reception mode by default and
switches automatically to transmission mode
when a byte is wri tten in the buffer.
Priority is given to transmission.
Elementary Time Unit Counter
This 11-bit counter controls the working frequency
of the UART. The operating frequency of t he clock
is the same as the card clock frequency (i.e. 4
MHz).
A compensation mode can be activated via the
COMP bit of the CRDETU1 registe r to allow a fre-
quency granul arity down to a half-etu.
Note: The decimal value is limited to a half clock
cycle. The bit duration is not fixed. It alternates be-
tween n clock cy cles and n-1 cl ock cycl es, where n
is the valu e to be written in the CRDET U registe r.
The character duration (10 bits) is also equal to
10*(n - ½) clock cycles This is precise enough to
obtain the character duration specified by the
ISO7816-3 s tandard.
For example, if F=372 and D=32 (F being the clock
rate conversion factor and D the baud rat e adj ust-
ment), then etu =11.625 clock cycles.
To achieve this clock rate, compensation mode
must be activated and the etu duration must be
programm ed to 12 clock cycles.
The result will be an average character duration of
11.5 clock cycles (for 10 bits).
See Figure 30.
Guard t ime counter
The guardtime counter is a 9-bit counter which
manages the char acter frame. It controls the dura-
tion between tw o co nsecutive charac ters in trans-
mission.
It is i nc remen ted at the etu rate.
No guardtime is inserted for the first character
transmitted.
The guardtime between the last byte received
from the card and the next byte transmitted by the
reader must be handled by software.
1
ST7SCR
57/102
Figure 30. Compensati on Mode
12cy11cy12cy11cy12cy11cy12cy11cy12cy11cy
Start bit Data bits Parity bit
UART
CRDIO
Working Clock
F=372
D= 32
1
ST7SCR
58/102
SMARTCARD INTERFACE (Cont’d)
Waiting Time Counter
The Waiting Time counter is a 24-bit counter used
to generate a timeout signal.
The elementary time unit counter acts as a pres-
caler to the Waiting Time counter which is incre-
mented at the etu rate.
The Waiting Time Counter can be used in both
UART mode and Manual mode and acts in differ-
ent ways depending on the selected mod e.
The CRDWT2, CRDWT1 and CRDWT0 are load
registers only, the counter itse lf is not directly ac-
cessible.
UART Mode
The load conditions are either:
– A Start bit is detected while UA RT bit =1 and the
WTEN bit =1.
or
– A write access to the CRDWT2 register is per-
formed while the UART bit = 1 and the WTEN bit
= 0. In this case, the Waiting Time counter can be
used as a general purpose timer.
In UART mode, if the WTEN bit of the CRDCR reg-
ister is set, the counter is loaded automa tic ally on
start bit detection. Software can change the time
out value on-the-fly by wri ting to the
CRDWT registers. For example, in T=1 mode,
software must load the Block Waiting Time (BWT)
time-out in the CRDWT registers before the start
bit of the l ast transmitted character.
Then, after tr ansm ission of t his last character, sig-
nalled by the TXC interrupt, software must write
the CWT value (Character Waiting Time) in the
CRDWT registers. See exam ple in Figure 31.
Ma nu a l mode
The load conditions are:
– A write access to the CRDWT2 register is per-
formed while the UA RT bit = 0 and the WTEN bit
= 0
In Manual mode, if the WTEN bit of the CRDCR
register is reset, the timer acts as a general pur-
pose timer. The timer is loaded when a write ac-
cess to the CRDWT2 register occurs. The timer
starts when the WTEN bit = 1.
12.4.3.4 Interrupt generato r
The Smartcard Interface has 2 interrupt vectors:
– Card Insertion/Removal Interrupt
– CRD Interrupt
The CRD interrupt is cleared when sof tware reads
the CRDIPR register. The Card Insertion/Removal
is an external interrupt and is cleared automatical-
ly by hardware at the end of the interrupt service
routine (IRET instructi on).
If an interrupt occurs wh ile th e CRDIPR registe r is
being read, the corresponding bit will be set by
hardware aft er the read access is done.
Figure 31. Waiting Time Counter Example
BWT
CWT
Reader
Smartcard
Firmware must program BWT Firmware must program CWT
TXC Interrupt
Sta rt bit Waiting Time Coun ter
loaded on start bit
CHAR0 CHAR1 CHARn
CHAR0 CHAR1
1
ST7SCR
59/102
SMARTCARD INTERFACE (Cont’d)
12.4.3.5 Card detection mechanism
The CRDDET bit in the CRDCR Register indicates
if the card presence detector (card switc h) is open
or closed when a card is inserted. When the
CRDIRF bit of the CRDSR is set, it indicates that a
card is present.
To be ab le to power-on t he smartca rd , card pres-
ence is mandatory. Removing the smartcard will
automatically start the ISO7816-3 card deactiva-
tion sequence (see Section 12.4 .3.6).
There is no hardware debouncing: The CRDIRF
bit changes whenever the level on the CRDDET
pin changes. The card sw itch can generate an in-
terrupt which can be used to wake up the device
from suspend mode and for software debouncing.
Three different cases can occur:
– The microcon troller is in run mod e, waiting for
card insertion:
Card insertion generates an interrupt and the
CRDIRF bit in the CRDSR re gister is set. De-
bouncing is managed by s of tware. After the time
required for debouncing, if the CRDIRF bit is set,
the CRDVCC bit in the CRDCR regi ster is set by
software to apply the selected voltage to the
CRDVCC pin
– The microcontroller is in suspend mode and a
car d is in se rte d:
The ST7 is woken up by the interrupt. The card
insertion is then handled in the sam e way as in
the pr evious case.
– The card is removed:
– The CRDIRF bit is reset wit hout hardware de-
bouncing
– A Card I nsertion/Removal i nterrupt is gener at-
ed, (if enabled by the CRDIRM bit in the
MISCR2 register)
– The CRDVCC bit is immediately reset by
hardware, starting the card deactivation se-
quence.
Fi gure 32. C ard de tec t i on bl oc k di ag ram
CRDDET
CRD
CRDSR
1
0
CARD INSERTION/REMOVAL
0
7
IRF
DET
CRDCR
0
7
CNF
CRD
MISCR2
0
7
IRM
Pull-up
EDGE DETECTOR
Interrupt Request
SMARTCARD INTERFACE (CRD)
1
ST7SCR
60/102
SMARTCARD INTERFACE (Cont’d)
12.4.3.6 Card Deactivation Sequen ce
This sequence can be activated in two different
ways:
– Autom atica lly as soon as the card presence de-
tector detects a card removal (via the CRDIRF bit
in the CRDSR register, refer t o Section 12.4.3. 5).
– By software, writing the CRDVCC bit in the CRD-
CR register, for examp le:
– If there is a smartcard current overflow (i.e.
when the IOV FF bit in the CRDSR reg ister is
set)
– If the voltage i s not wi thin t he spe cified range
(i.e. when the VCARDOK bit in the CRDSR
register is cleared), but software must clear
the CRDVCC bit in the CRDCCR register to
start the deactivation sequence.
When the CRDVCC bit is cleared, this starts the
deactivation sequence. CRDCLK, CRDIO,
CRDC4 and CRDC8 pins are then deactivated as
shown in Figure 33:
Figure 33. Card deactivation sequence
Figu re 34. C ard volta ge se l ect io n and power OFF block di a g ra m
CRDVCC pin
CRDRST pin
CRDCLK pin
CRDIO pin
CRDC4 pin
CRDC8 pin
8 CPU Clk cycles
CRDVCC
CRD
CRDCCR
BLOCK
0
7
VCC
CRDCR
07
IRF
CRDSR
0
7
CRD VCARD
1
POWER OFF
IOVF OK
CRDIER
0
7
CRDIPR
0
7
IOVP VCRD
SMARTCARD
POWER SUPPLY
BLOCK
5V
VCARDOK Interrupt Request
IOVF Interrupt Request
2
2
Card voltage selection
2
IOVM VCRD
P
M
VCARD
0
VCARD
1
ST7SCR
61/102
SMARTCARD INTERFACE (Cont’d)
Figure 35. Power Off Timing Diagram
Note: Refer to the Electrical Characteristics sec-
tion for t he values of tON and tOFF.
Figure 36. Card clock selection block diagram
1100 00
VCARD[1:0]
CRDVCC
VCARDOK
VCRDP Interr upt
VCARDOK
11
VCRDP Interrupt
Software Power-Off Voltage Error
Power-On
Power-On
tOFF
tONtON
tOFF
0.4V
CLK
4 MHz 1
0
SEL CRD
CLK
CRDCCR
POWER OFF
BLOCK
CRDCLK
ISOCLK
DIV
PLLPLL
OSC
4 MHz
1
ST7SCR
62/102
SMARTCARD INTERFACE (Cont’d)
12.4.4 Register Description
SMARTCARD INTERFACE CONTROL REGIS-
TER (CRDCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bi t 7 = C RDRST
Smartcard Interface Reset.
This bit is set by software to reset the UART of the
Smartcard int erface.
0: No Smartcard UART Reset
1: Smartcard UART Reset
Bi t 6 = CRDDET
Card P res ence Det ector.
This bit is set and cleared by software to configure
the card presence detector switch.
0: Switch open if no card is pres ent
1: Switch closed if no c ard is present
Bits [5:4] = VCARD[1:0]
Card voltage selection.
These bits select the card voltage.
Bi t 3 = UART
UART Mod e Selection.
This bit is set and cleared by software to select
UART or manual mode.
0: CRDIO pin is a copy of the CRDIO bit in the
CRDCCR register (Manual mode).
1: CRDIO pin is the output of the smart card UART
(UART mode).
Caution: Before switching from Manual mode to
UART mode, software must set the CRDIO bit in
the CRDCCR regis ter.
Bit 2 = WTEN
Waiting Time Counter enable.
0: Waiting Time count er stopped . While WTEN =
0, a write access to the CRDWT2 register l oads
the Waiting time counter with the load value held
in the CRDWT0, CRDWT1 and CRDWT2 regis-
ters.
1: Start counter. I n UART mode, the counter is au-
tomaticall y reloaded on start bit detecti on.
Bit 1 = CREP
Automatic character repetition in
case of parity error.
0: In reception m ode: no parit y error signal indica-
tion (no retry on parity error).
In transmission m ode: no error signal process-
ing. No retransmiss ion of a refused character on
parity error.
1: Automatic parity management:
In t ransmission mode: up to 4 character repeti-
tions on parity error.
In reception mod e: up to 4 retr ie s are made on
parity error.
The P ARF parity error flag is s et by hardwa re if a
parity error is dete cted.
If the transmitted character is refused, the PARF
bit is set (but the TXCF bit is reset) and an interrupt
is generated if the PARM bit is set.
Note: If CREP=1, the PARF flag is set at the 5th
error (after 4 character repet i tions or 4 retries).
If CREP=0, the PARF bit is set after the first parity
error.
Bit 0 = CONV
ISO convention select ion.
0: Direct convention, the B0 bit (LSB) is sent first, a
’1’ is a level 1 on the Card I/O pin, the parity bit is
added after the B7 bit.
1: Inverse convention, the B7 bit (MSB) is sent
first, a ’1’ is a level 0 on Card I/O pin, the parit y
bit is added after the B0 bit.
Note: To detect the conv ention used by any card,
apply the following rul e. If a c ard uses the conven-
tion selected by t he reader, an RXC eve nt occurs
at answer to reset. Otherwise a parity error also
occurs.
70
CRD
RST CRD
DET VCAR
D 1 VCAR
D 0 U
ART WT
EN C
REP CO
NV
Bit 1 Bit 0 Vcard
00 0V
0 1 1.8V
10 3V
11 5V
1
ST7SCR
63/102
SMARTCARD INTERFACE (Cont’d)
SMARTCARD INTERFACE STATUS REGISTER
(CRDSR)
Read only (Read/Write on some bits)
Reset Value: 1000 0000 (80h)
Bi t 7 =TxBEF
Transm it Buffer Empty Flag.
- Read only
0: Trans mit buffer is not empty
1: Trans mit buffer is empty
Bi t 6 = C RDIRF
Card Insert ion/ Removal Fl ag.
- Read only
0: No card i s present
1: A card is pres ent
Bi t 5 = IOVF
Card Ov erl oad Current Flag.
- Read only
0: No card overl oad curren t
1: Card overload current
Bi t 4 = V CARDOK
Card voltage status Flag.
- Read only
0: The card voltage is not in th e specified range
1: The card voltage is within the specified range
Bit 3 = WTF
Waiting Tim e Counter overflow Flag.
- Read only
0: The WT Counter has not reached it s maximum
value
1: The WT Counter has reac hed its m aximum val-
ue
Bit 2 = TXCF
Transmi tted character Flag.
- Read/Write
This bit is set by hardware and cleared by soft-
ware.
0: No character transmitted
1: A character has been transmitted
Bit 1 = RXCF
Received character Flag.
- Read only
This bit is set by hardware and cleared by hard-
ware when the CRDRXB buffer is re ad.
0: No character received
1: A character has been received
Bit 0 = PARF
Parity Error Fl ag.
- Read/Write
This bit is set by hardware and cleared by soft-
ware.
0: No parity error
1: Parity error
Note: When a c haracter is received, the RXCF bit
is always set.When a character is received with a
parity error, the P AR F bit is also set.
70
TXBE
FCRD
IRF IOVF VCARD
OK WTF TXC
FRXC
FPAR
F
ST7SCR
64/102
SMARTCARD INTERFACE (Cont’d)
SMARTCARD CONTACT CONTROL REGISTER
(CRDCCR)
Read/Write
Reset Value: 00xx xx00 (xxh)
Note: To modify the content of this register, the LD
instruction must be used (do not use the BSET
and BRES instructions).
Bi t 7 = C LKSEL
Card cloc k selecti o n .
This bit i s set and cleared by software.
0: The sig nal on the CRDCLK pin is a copy of the
CRDCLK bit.
1: The sig nal on the CRDCLK pin is a 4M Hz fre-
quency clock .
Note: To start the clock at a known level, the CRD-
CLK bit should be changed before the CLKSEL
bit.
Bit 6 = Reserved, must be kept cleared.
Bi t 5 = C RDC8
CRDC8 pin control.
Reading this bit returns the value present on the
CRDC8 pin. Wr iting this bit outputs the bit value on
the pin.
Bi t 4 = C RDC4
CRDC4 pin control
Reading this bit returns the value present on the
CRDC4 pin. Wr iting this bit outputs the bit value on
the pin.
Bit 3 = CRDIO
CRDIO pin cont rol
.
This bit is active only if t he UART bit in the CRDCR
Register is reset. Reading thi s bit returns the value
present on the CRDIO pin.
If the UART bit is re se t:
– Writing “0” forces a lo w level on the CRDIO pi n
– Writing “1” forces the CRDIO pin to open drain
Hi-Z.
Bit 2 = CRDCLK
CRDCLK pin control
This bit is active only if the CLKSEL bit of the CRD-
CCR register is reset. Reading this bit returns the
value pr esent in the register (not t he CRDCLK pin
value).
When the CLKSE L bit is reset:
0: Level 0 to be appl ie d on CRDCLK pin.
1: Level 1 to be appl ie d on CRDCLK pin.
Note: To ensure that the clock stops at a given
value, write the desired value in the CRDCLK bit
prior to c hang ing the CLKSEL bit from 1 to 0.
Bit 1 = CRDRST
CRDRST pin control.
Reading this bit returns the value present on the
CRDRST pin. Writing this bit outputs the bit va lue
on the pin.
Bit 0 = CRDVCC
CRDVCC Pin Control.
This bit is set and cleared by sof twa re and forced
to 0 by hardware when no card is present
(CRDIRF bit=0).
0: No voltage to be applied on the CRDVCC pin.
1: The selected voltage must be applied on the
CRDVCC pin.
Figure 37. Smartcard I/O Pin Structure
70
CLK
SEL - CRD
C8 CRD
C4 CRD
IO CRD
CLK CRD
RST CRD
VCC
I/O PIN DATA BUS
CRDCCR
REGISTER
ST7SCR
65/102
SMARTCARD INTERFACE (Cont’d)
SMARTCARD ELEMENTARY TIME UNIT REG-
ISTER (CRDETUx)
CRDETU1
Read/Write
Reset Value: 0000 0001 (01h)
Bit 7 = COMP
Elementary Time Unit Compensa-
tion.
0: Compensation m ode disabl ed.
1: Compensation m ode enabl ed. To allow non in-
teger value, one cl ock cycle is subtracted from
the ETU value on odd bi t s. See Fi gure 30.
Bit [6:3] = Reser ved
Bi ts 2 :0 = ETU [10:8]
ETU value in card clock cy-
cles.
Writing CRDETU1 register reloads the ETU coun-
ter.
CRDETU0
Read/Write
Reset Value: 0111 0100 (74h)
Bits 7:0 = ETU [7:0]
ETU value in card clock cy-
cles.
Note: The value of ETU [10:0] must in the range
12 to 2047. To write 20 48, clear all the bits.
GUARDTIME REGIST ER (CRDGTx)
CRDGT1
Read/Write
Reset Value: 0000 0000 (00h)
CRDGT0
Read/Write
Reset Value: 0000 1100 (0Ch)
Software write s the Guardtim e value in th is regis-
ter. The value is loaded at the end of the current
Guard period.
GT: Guard Time: Mini mum time between two con-
secutive start bits in transmission mode. Val ue ex-
pressed in Elementary Time Units (from 11 to
511).
The Guardtime between the last byte received
from the card and the next byte transmitted by the
reader must be handled by software.
70
COMP0000ETU10ETU9ETU8
70
ETU7 ETU6 ETU5 ETU4 ETU3 ETU2 ETU1 ETU0
70
0000000GT8
70
GT7 GT6 GT5 GT4 GT3 GT2 GT1 GT0
ST7SCR
66/102
SMARTCARD INTERFACE (Cont’d)
CHARACTER WAITING TIME REGISTER (CRD-
WTx)
CRDWT2
Read/Write
Reset Value: 0000 0000 (00h) .
CRDWT1
Read/Write
Reset Value: 0010 0101 (25h)
CRDWT0
Read/Write
Reset Value: 1000 0000 (80h)
WT: Character waiting time value expressed in
ETU (0 / 16777215).
The CRDWT0, CRDWT1 and CRDWT2 registers
hold the load val ue of the Waiting Time count er.
Note: A read operation does not return the counter
value.
This counter can be used as a general purpose
timer.
If t he WTEN bit of the CRDCR regi ster is reset, the
counter is reloaded when a write access in the
CRDWT2 register occurs. It starts when the
WTEN bit is set.
If the WTEN bit in the CRDCR register is set and if
UART mode is activated, the counter acts as an
autoreload timer. The timer is reloaded when a
start bit is sent or detected. An interrupt is generat-
ed if the timer overflows between t wo cons ecut ive
start bits.
Note: When loaded with a 0 value, the Waiting
Time counter stays at 0 and the WTF bit = 1.
70
WT
23 WT
22 WT
21 WT
20 WT
19 WT
18 WT
17 WT
16
70
WT
15 WT
14 WT
13 WT
12 WT
11 WT
10 WT9 WT8
70
WT 7 WT6 WT 5 WT4 WT3 WT2 WT1 W T0
ST7SCR
67/102
SMARTCARD INTERFACE (Cont’d)
SMARTCARD INTERRUPT ENABLE REGISTER
(CRDIER)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = TXBEM
Transmit buffer empty interrupt
mask.
This bit is set and cleared by software to enable or
disable the TXBE interrupt.
0: TXBE i nterrupt disable d
1: TXBE interrupt enabled
Bit 6 = Reserved.
Bit 5 = IOVFM
Card Overload Current Interrupt
Mask.
This bit is set and cleared by software to enable or
disable the IOVF int errupt.
0: IOVF interrupt disabled
1: IOVF interrupt enabled
Bit 4 = VCRDM
Card Voltage Error Interrupt Mask.
This bit is set and cleared by software to enable or
disable the VCRD interrupt.
0: VCRD in terrupt disabled
1: VCRD in terrupt enabled
Bit 3 = WTM
Waiting Tim er Interru pt Mask.
This bit is set and cleared by software to enable or
disable the Waiting Timer overflow interrupt.
0: WT interrupt disabled
1: WT interrupt enabled
Bit 2 =TXCM
Transmitted Character Interrupt
Mask
This bit is set and cleared by software to enable or
disable the TXC interrupt.
0: TXC interrupt disabled
1: TXC interrupt enabled
Bit 1 =RXCM
Rece ived Character Interrupt Mask
This bit is set and cleared by software to enable or
disable t he RXC interrupt.
0: RXC interrupt disabled
1: RXC interrupt enabl ed
Bit 0 = PARM
Parity Error Interrupt. Mask
This bit is set and cleared by software to enable or
disable the parity error int errupt for parity error.
0: PAR interrupt disabled
1: PAR error interrupt enabled
70
TXBE
M-IOVF
MVCRDM WTM TXC
MRXC
MPAR
M
ST7SCR
68/102
SMARTCARD INTERFACE (Cont’d)
SMARTCARD INTERRUPT PENDING REGIS-
TER (CRDIP R)
Read Only
Reset Value: 0000 0000 (00h)
This register indicates the interrupt source. It is
cleared aft er a read operation.
Bit 7 = TXBEP
Transmit buffer empty interrupt
pending.
This bit is set by hardware when a TXBE e ven t oc-
curs and the TXBEM bit is set.
0: No TXBE interrupt pending
1: TXBE interrupt pending
Bit 6 = Reserved.
Bi t 5 = IOVF
Card Ov erl oad Current interrupt
pending.
This bit is set by hardware when a IOVF event oc-
curs and the IOVFM bit is set.
0: No IO V F interrupt pending
1: IOVF interrupt pending
Bi t 4 = VCRDP
C ard Voltage Error interrupt pend-
ing.
This bit is set by hardware when the VCARDOK bit
goes from 1 to 0 while the VCRDM bit is s et.
0: No VCRD i nterrupt pendi ng.
1: VCRD inte rrupt pending.
Bit 3 = WTP
Waiting Timer Overflow interrupt
pending.
This bit is set by hardware when a WT P event oc-
curs and the WTPM bit is set .
0: No WT interrupt pending
1: WT interrupt pendin g
Bit 2 = TXCP
Transmitted character interrupt
pending.
This bit is set by hardware when a character is
transmitted and the TXCM bit is set. It indicates
that the CRDTXB buffer can be loaded with the
next character to be transmitted.
0: No TXC interrupt pending
1: TXC interrupt pending
Bit 1 = RXCP
Received character interrupt pend-
ing.
This bit is set by hardware when a character is re-
ceived and the RXCM bit is set. It indicates that the
CRDRXB buf fer can be read.
0: No RXC interrupt pendi n g
1: RXC interrupt pendi ng
Bit 0 = PARP
Parity Error i nterrupt pending.
This bit is set b y hardware when a PAR ev ent oc-
curs and the PARM bit is set.
0: No PAR interrupt pending
1: PAR interrupt pending
SMARTCARD TRANSMIT BUFFER (CRDT XB)
Read/Write
Reset Value: 0000 0000 (00h)
This register is used to send a byte to th e smart-
card.
SMARTCARD RECEIVE BUFFER (CRDRXB)
Read
Reset Value: 0000 0000 (00h)
This register is used to receive a byte from the
smartcard.
70
TXBE
P-IOVF
PVCRD
PWTP TXCP RXC
PPAR
P
70
TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0
70
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
ST7SCR
69/102
SMARTCARD INTERFACE (Cont’d)
Table 20. R egister Ma p and Reset Values
Address
(Hex.) Regist er
Label 76543210
00 CRDCR
Reset Value CRDRST
0DETCNF
0VCARD1
0VCARD0
0UART
0WTEN
0CREP
0CONV
0
01 CRDSR
Reset Value TXBEF
1CRDIRF
0IOVF
0VCARDOK
0WTF
0TXCF
0RXCF
0PARF
0
02 CRDCCR
Reset Value CLKSEL
0-
0CRDC8
xCRDC4
xCRDIO
xCRDCLK
0CRDRST
xCRDVCC
0
03 CRDETU1
Reset Value COMP
0-
0-
0-
0-
0ETU10
1ETU9
0ETU8
0
04 CRDETU0
Reset Value ETU7
0ETU6
1ETU5
1ETU4
1ETU3
0ETU2
1ETU1
0ETU0
0
05 CRDGT1
Reset Value -
0-
0-
0-
0-
0-
0-
0GT8
0
06 CRDGT0
Reset Value GT7
0GT6
0GT5
0GT4
0GT3
1GT2
1GT1
0GT0
0
07 CRDWT2
Reset Value WT23
0WT22
0WT21
0WT20
0WT19
0WT18
0WT17
0WT16
0
08 CRDWT1
Reset Value WT15
0WT14
0WT13
1WT12
0WT11
0WT10
1WT9
0WT8
1
09 CRDWT0
Reset Value WT7
1WT6
0WT5
0WT4
0WT3
0WT2
0WT1
0WT0
0
0A CRDIER
Reset Value TXBEM
0-
0IOVM
0VCRDM
0WTM
0TXCM
0RXCM
0PARM
0
0B CRDIPR
Reset Value TXBEP
0-
0IOVP
0VCRDP WTP
0TXCP
0RXCP
0PARP
0
0C CRDTXB
Reset Value TB7
0TB6
0TB5
0TB4
0TB3
0TB2
0TB1
0TB0
0
0D CRDRXB
Reset Value RB7
0RB6
0RB5
0RB4
0RB3
0RB2
0RB1
0RB0
0
ST7SCR
70/102
13 INSTRUCTION SET
13.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:
The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do
so, most of the addressing modes may be subdi-
vided in two sub- modes called long and short:
– Long addressing mode is more powerful be-
cause it can use the full 64 Kbyte address s pace,
however it uses more bytes and more CPU cy-
cles.
– Short addressing mode is less powerful because
it can generally only access page zero (0000h -
00FFh range), but the instruction size i s more
compac t, and faster. All memory to m em ory in-
structions use shor t addressing modes only
(CLR , CPL , NEG, BS ET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, S RL, SRA, S WAP)
The ST7 Assemble r optimizes the use of long and
short addr essing modes.
Table 21. ST7 Addressing Mode Overview
Addressing Mode Example
Inherent nop
Immediate ld A,#$55
Direct ld A,$55
Indexed ld A,($55,X)
Indirect ld A,([$55],X)
Relative jrne loop
Bit operation bset byte,#5
Mode Syntax Destination Pointer
Address
(Hex.)
Pointer Size
(Hex.) Length
(Bytes)
Inherent nop + 0
Immediate ld A,#$55 + 1
Short Direct ld A,$10 00..FF + 1
Long Direct ld A,$1000 0000..FFFF + 2
No Offset Direct Indexed ld A,(X) 00..FF + 0
Short Direct Indexed ld A,($10,X) 00..1FE + 1
Long Direct Indexed ld A,($1000,X) 0000..FFFF + 2
Short Indirect ld A,[$10] 00..FF 00..FF byte + 2
Long Indirect ld A,[$10.w] 0000..FFFF 00..FF word + 2
Short Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte + 2
Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word + 2
Relative Direct jrne loop PC+/-127 + 1
Relative Indirect jrne [$10] PC+/-127 00..FF byte + 2
Bit Direct bset $10,#7 00..FF + 1
Bit Indirect bset [$10],#7 00..FF 00..FF byte + 2
Bit Direct Relative btjt $10,#7,skip 00..FF + 2
Bit Indirect Relative btjt [$10],#7,skip 00..FF 00..FF byte + 3
ST7SCR
71/102
INSTRUCTION S ET OVERVIEW (Cont’d)
13.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode full y speci fies all the required informa-
tion f or the CPU to process the operation.
13.1.2 Immediate
Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.
13.1.3 Direct
In Direct inst ructions, the operands ar e referenced
by t heir memory address.
The direct addressing mode consists of two sub-
modes:
Direct (short)
The addr ess is a byte, thus requires only one byte
after the opcode , but only allows 00 - FF add ress-
ing space.
Di rect (long)
The addr ess is a word, thus al lowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.
13.1.4 In dexed (No Offset, Sh ort , Lon g)
In this mode, the operand is referenced by its
memory address, which is defined by t he unsigned
addition of an index regist er (X or Y) with an offset.
The indirect addressing mode consists of three
sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.
Indexed (S hort)
The offset is a byt e, thus r equires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 byt es after the op-
code.
13.1.5 In direct (Short, Long)
The required data byt e to do the operation is found
by its memory address, located in memory (point-
er).
The po inter address follows the opcode. Th e i ndi-
rect addressing mode cons ists of two sub-mo des:
Indi rect (short )
The pointer address is a byte, t he pointer size is a
byte, thus allowing 00 - FF addr essing space, and
requires 1 byte after the opcode.
Indi rec t (long)
The pointer address is a byte, t he pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.
Inherent Instruction Function
NOP No opera tion
TRAP S/W Interrupt
WFI Wait For Interrupt (Low Pow-
er Mode)
HALT Halt Oscillator (Lowest Power
Mode)
RET Sub-routine Return
IRET Interrupt Sub-routine Return
SIM Set Interrupt Mask (level 3)
RIM Reset Interrupt Mask (level 0)
SCF Set Carry Flag
RCF Reset Carry Flag
RSP Reset Stack Pointer
LD Load
CLR Clear
PUSH/POP Push/Pop to/from the stack
INC/DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
MUL Byte Multiplication
SLL, SRL, SRA, RLC,
RRC Shift and Rotate Operations
SWAP Swap Nibbles
Immediate Instruction Function
LD Load
CP Compare
BCP Bit Compare
AND, OR, XOR Logical Operations
ADC, ADD, SUB, SBC Arithmetic Operations
ST7SCR
72/102
INSTRUCTION S ET OVERVIEW (Cont’d)
13. 1.6 Indirect Inde xed ( S hort, Long)
This is a combination of indirect and short i ndexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index re gister value (X or Y)
with a pointer val ue located in memory. The point-
er address follows th e opco de.
The indirect indexed addressing mode consists of
two sub-modes:
Indirect Indexe d (Short)
The pointer address is a byte, th e pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte aft er the opcode.
Indi rec t In de xed (Lon g)
The pointer address is a byte, th e pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte aft er the opcode.
Table 22. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
13.1.7 Relative mode (Direct, Indirect)
This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.
The relative addressing m ode consists of two sub-
modes:
Relative (Direct)
The offs et is fol lowing the opcode.
Relative (Indirect)
The offset is defined in memory, which address
follows the opcode.
Long and Short
Instructions Function
LD Load
CP Compare
AND, OR, XOR Logical Oper ations
ADC, ADD, SUB, SBC Arithmetic Additions/Sub-
stractions operations
BCP Bit Compare
Short Instructions
Only Function
CLR Clear
INC, DEC Increment/Decrement
TNZ Test Negative or Zero
CPL, NEG 1 or 2 Complement
BSET, BRES Bit Operations
BTJT, BTJF Bit Test and Jump Opera-
tions
SLL, SRL, SRA, RLC,
RRC Shift and Rotate Opera-
tions
SWAP Swap Nibbles
CALL, JP Call or Jump subroutine
Available Relative
Direct/Indirect
Instructions Function
JRxx Conditional Jump
CALLR Call Relative
ST7SCR
73/102
INSTRUCTION S ET OVERVIEW (Cont’d)
13.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instruction s may be subdi vided into 13 main groups as illustrated in
the following table:
Usin g a pre -byte
The instructions are described with one to four op-
codes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyt e opcodes are defined . These prebytes
modify the meaning of the instruction they pre-
cede.
The whole instruction becom es:
PC-2 E nd of previous instruction
PC-1 Prebyte
PC opcode
PC+1 Additiona l word (0 to 2) acc ordin g
to the number of bytes required to compute the ef-
fective address
These prebytes enable i nstruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the ins truction in X or
the instruc ti on using direct addressing mode . The
prebytes are:
PDY 90 Replace an X based instruction
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
PIX 92 Replace an instruction using di-
rect, direct bit, or direct re lative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X i ndex ed ad-
dressing mode to an instruction using indirect X in-
dexed addre ssing mode.
PIY 91 Replace an inst ruction using X in-
direct indexed addressing mode by a Y one.
Load and Transfer LD C LR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF
ST7SCR
74/102
INSTRUCTION S ET OVERVIEW (Cont’d)
Mnemo Description Function/Example Dst Src I1 H I0 N Z C
ADC Add with Carry A = A + M + C A M H N Z C
ADD Addition A = A + M A M H N Z C
AND Logical And A = A . M A M N Z
BCP Bit compare A, Memory tst (A . M) A M N Z
BRES Bit Reset bres Byte, #3 M
BSET Bit Set bset Byte, #3 M
BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C
BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C
CALL Call subroutine
CALLR Call subroutine relative
CLR Clear reg, M 0 1
CP Arithmetic Compare tst(Reg - M) reg M N Z C
CPL One Complement A = FFH-A reg, M N Z 1
DEC Decrement dec Y reg, M N Z
HALT Halt 10
IRET Interrupt routine return Pop CC, A, X, PC I1 H I0 N Z C
INC Increment inc X reg, M N Z
JP Absolute Jump jp [TBL.w]
JRA Jump relative always
JRT Jump relative
JRF Never jump jrf *
JRIH Jump if Port B INT pin = 1 (no Port B Interrupts)
JRIL Jump if Port B INT pin = 0 (Port B interrupt)
JRH Jump if H = 1 H = 1 ?
JRNH Jump if H = 0 H = 0 ?
JRM Jump if I1:0 = 11 I1:0 = 11 ?
JRNM Jump if I1:0 <> 11 I1:0 <> 11 ?
JRMI Jump if N = 1 (minus) N = 1 ?
JRPL Jump if N = 0 (plus) N = 0 ?
JREQ Jump if Z = 1 (equal) Z = 1 ?
JRNE Jump if Z = 0 (not equal) Z = 0 ?
JRC Jump if C = 1 C = 1 ?
JRNC Jump if C = 0 C = 0 ?
JRULT Jump if C = 1 Unsigned <
JRUGE Jump if C = 0 Jmp if unsigned >=
JRUGT Jump if (C + Z = 0) Unsigned >
ST7SCR
75/102
INSTRUCTION S ET OVERVIEW (Cont’d)
Mnemo Description Function/Example Dst Src I1 H I0 N Z C
JRULE Jump if (C + Z = 1) Unsigned <=
LD Load dst <= src reg, M M, reg N Z
MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0
NEG Negate (2’s compl) neg $10 reg, M N Z C
NOP No Operation
OR OR operation A = A + M A M N Z
POP Pop from the Stack pop reg reg M
pop CC CC M I1 H I0 N Z C
PUSH Push onto the Stack push Y M reg, CC
RCF Reset carry flag C = 0 0
RET Subroutine Return
RIM Enable Interrupts I1:0 = 10 (level 0) 1 0
RLC Rotate left true C C <= A <= C reg, M N Z C
RRC Rotate right true C C => A => C reg, M N Z C
RSP Reset Stack Pointer S = Max allowed
SBC Substract with Carry A = A - M - C A M N Z C
SCF Set carry flag C = 1 1
SIM Disable Interrupts I1:0 = 11 (level 3) 1 1
SLA Shift left Arithmetic C <= A <= 0 reg, M N Z C
SLL Shift left Logic C <= A <= 0 reg, M N Z C
SRL Shift right Logic 0 => A => C reg, M 0 Z C
SRA Shift right Arithmetic A7 => A => C reg, M N Z C
SUB Substraction A = A - M A M N Z C
SWAP SWAP nibble s A 7-A4 <=> A3-A0 reg , M N Z
TNZ Test for Neg & Zero tnz lbl1 N Z
TRAP S/W trap S/W interrupt 1 1
WFI Wait for Interrupt 1 0
XOR Exclusive OR A = A XOR M A M N Z
ST7SCR
76/102
14 ELECTRIC AL CHARACTERISTI CS
14.1 ABSOLUTE MAXIMUM RATINGS
This product contai ns devices for protecting the in-
puts against damage due to high static voltages,
however it is advisable to take normal precautions
to avoid appy ing any voltage higher t han the spec-
ified maximum rated voltages.
For proper operation it is recommended that VI
and VO be higher than VSS and lower than VDD.
Reliability is enhanced if unused inputs are con-
nected to an appropriate logic voltage level (VDD
or VSS).
Power Considerations. The average chip-junc-
tion temperature, TJ, in Celsius can be obtained
from: TJ =TA + PD x RthJA
Where: TA = Am bient Temperat ure.
RthJA =P acka ge thermal resistance
(junction-to ambient).
PD = PINT + PPORT.
PINT =I
DD x VDD (chip internal power).
PPORT =Port power dissipation
determined by the user)
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the devic e at these condi tions is
not implied. Exposure to maximum rating for ex-
tended periods may affect device r eliability.
General Warning: Direct connection to VDD or VSS of the I/O pins could damage the device in case of program counter
corruption (due to unw anted cha nge of the I/O configu ration). To g uarantee safe condit ions, this co nnection h as to be
done through a typical 10KΩ pull-up or pull-down resistor.
Thermal Characteristics
Symbol Ratings Value Unit
VDD - VSS Supply voltage 6.0 V
VIN Input voltage VSS - 0.3 to VDD + 0.3 V
VOUT Output voltage VSS - 0.3 to VDD + 0.3 V
ESD ESD susceptibility 2000 V
ESDCard ESD susceptibility for card pads 4000 V
IVDD_i Total current into VDD_i (source) 250 mA
IVSS_i Total current out of VSS_i (sink) 250
Symbol Ratings Value Unit
RthJA Package thermal resistance TQFP64
SO24 60
80 °C/W
TJmax Max. junction temperature 150 °C
TSTG Storage temperature range -65 to +150 °C
PD Power dissipation (maximum value) 500 mW
ST7SCR
77/102
14.2 RECOMMENDED OPERATING CONDITIONS
(Operating condition s TA = 0 to +70°C unless othe rwise speci fied)
Note 1: P os it iv e injection
The IINJ+ i s done through protection diodes insulat ed from the substrate of the die.
Note 2: For SmartCard I/Os, VCARD has to be considered.
Note 3: Neg ativ e inj ect ion
– The IINJ- is d one through protection diod es NOT INSULAT ED from the substrate of the die. The draw-
back is a small leakage (few µA) induced inside the die when a negative injection is performed. This leak-
age is tolerat ed by the digital structure, but it acts on the analog line ac cording to the impedance versus
a leakage current of f ew µA (if t he M CU has an AD converter). The effect depends on the pin which is
submitted to the injection. Of cour se, external digital signals applied to the component must have a max-
imum impeda nce close to 50K Ω.
Location of the negative current injection:
– Pure digital pins can toler ate 1.6mA. I n addition, t he best choice is to inject the current as far as possible
from the analog input pins.
General N o te: When several inputs are subm itted t o a c urrent inj ec tion, th e m axim um I INJ is th e sum of
the positive (resp. negativ e) currrents (instantaneous values).
GENERAL
Symbol Parameter Conditions Min Typ Max Unit
VDD Supply voltage 4.0 5.5 V
fOSC External clock source 4 MHz
TAAmbient temperature range 0 70 °C
CURRENT INJECTION ON I/O PORT AND CONTROL PINS
Symbol Parameter Conditions Min Typ Max Unit
IINJ+ Total positive injected current (1)
VEXTERNAL > VDD
(Standard I/Os)
VEXTERNAL > VSC_PWR
(Smartcard I/Os)
20 mA
IINJ- Total negative injected current (2,3) VEXTERNAL < VSS
Digital pins
Analog pins 20 mA
ST7SCR
78/102
RECOMMENDED OPERATING CONDITION S (Cont’d)
(TA=0 to +70oC, VDD-VSS=5.5V unless otherwis e specified)
Notes:
1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS; clock input (OSC1)
driven by external square wave.
2. All I/O pins in input mode with a static value at VDD or VSS; clock input (OSC1) driven by external square wave.
T = 0... +70oC, voltages are referred to VSS unless otherwise specified:
Note 1 : Hysteresis voltage between Schmitt trigger switching levels. Based on characterisation results, not tested.
Note 2 : Guaran teed by Charact erizat ion
Symbol Parameter Conditions Min Typ. Max Unit
IDD
Supply current in RUN mode 1) fOSC = 4MHz 10 15 mA
Supply current in WAIT mode 2) 3mA
Supply current in suspend mode External ILOAD = 0mA
(USB transc eiver enabled) 500 µA
Supply current in HALT mode External ILOAD = 0mA
(USB transc eiver disabled) 50 100
I/O PORT PINS
Symbol Parameter Conditions Min Typ Max Unit
VIL Input low level voltage 0.3xVDD V
VIH Input high level voltage 0.7xVDD
VHYS Schmidt trigger voltage hysteresis 1) 400 mV
VOL Output low level voltage
for Standard I/O port pins I=-5mA 1.3 V I=-2mA 0.4
VOH Output high level voltage I=3mA VDD-0.8
ILInput leakage current VSS<VPIN<VDD 1µA
RPU Pull-up equivalent resistor 50 90 170 KΩ
tOHL Output high to low level fall time
for high sink I/O port pins (Port D) 2)
Cl=50pF
6813
ns
tOHL Output high to low level fall time
for standard I/O port pins (Port A, B or
C) 2) 18 23
tOLH Output L-H rise time (Port D) 2) 7914
t
OLH Output L-H rise time for standard I/O
port pins (Port A, B or C) 2) 19 28
tITEXT External interrupt pulse time 1 tCPU
LED PINS
Symbol Parameter Conditions Min Typ Max Unit
ILsink Low curre nt Vpad > VDD-2.4 2 4 mA
ILsink High current Vpad > VDD-2.4 5.6 8.4
ST7SCR
79/102
14.3 SUPPLY AND RESET CHARACTERISTICS
(T = 0 to +70oC, VDD - VSS = 5.5V unless otherwise spe cified.
14.4 CLOCK AND TIMING CHARACTERISTICS
14.4.1 General Timings
(Operating condition s TA = 0 t o +70°C unless othe rwise speci fied)
* ∆tINST is the number of tCPU to finish the current instruction execution.
14.4.2 External Clock Sou rce
LOW VOLTAGE DETECTOR AND SUPERVISOR (LVDS)
Symbol Parameter Conditions Min Typ Max Unit
VIT+ R eset relea se threshol d
(VDD rising) 3.7 3.9 V
VIT- R eset gene ration threshold
(VDD falling) 3.3 3.5 V
Vhys Hysteresis VIT+ - VIT- 200 mV
VtPOR VDD rise time rate 20 ms/V
Symbol Parameter Conditions Min Typ 1) Max Unit
tc(INST) Instruction cycle time 2 3 12 tCPU
fCPU=4MHz 500 750 3000 ns
tv(IT) Interrupt reaction time 2)
tv(IT) = ∆tc(INST) + 10 10 22 tCPU
fCPU=4MHz 2.5 5.5 µs
Symbol Parameter Conditions Min Typ Max Unit
VOSC1H OSC1 input pin high level voltage
see Figure 38
0.7xVDD VDD V
VOSC1L OSC1 input pin low level voltage VSS 0.3xVDD
tw(OSC1H)
tw(OSC1L) OSC1 high or low time 3) 15 ns
tr(OSC1)
tf(OSC1) OSC1 rise or fall time 3) 15
ILOSCx Input leakage current VSS≤VIN≤VDD ±1 µA
ST7SCR
80/102
CLOCK AND T IMI NG CHARACTERISTICS (Cont’d)
Figure 38. Typical Application with an External Clock Source
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.
OSC1
OSC2
fOSC
EXTERNAL
ST7XXX
CLOCK SOURCE
Not c onnect ed i nternally
VOSC1L
VOSC1H
tr(OSC1) tf(OSC1) tw(OSC1H) tw(OSC1L)
IL
90%
10%
ST7SCR
81/102
CLOCK AND T IMI NG CHARACTERISTICS (Cont’d)
14.4.3 Cryst al Reson ator Oscillators
The ST7 internal clock is supplied with one Crystal
resonator oscillator. All the information given in
this paragraph are based on characterization re-
sults with specified typical external componants. In
the application, the resonator and the load capaci-
tors have to be placed as clos e as possible t o t he
oscillator pins in order to minimize output distortion
and start-up stabiliza tion time. Refer to the cryst al
resonator m anufacturer for more details (frequen-
cy, package, accuracy...).
Figure 39. T ypical Appli cation with a Crystal Resonator
Notes:
1. Resonator characteristics given by the crystal resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal resonator manufacturer for more details.
Symbol Parameter Conditions Min Typ Max Unit
fOSC Oscillator Frequency 3) MP: Medium power oscillator 4 MHz
RFFeedback resistor 20 40 kΩ
CL1
CL2
Recommanded load capaci-
tances versus equivalent se-
rial resistance of the crystal
resonator (RS)
See Table 4 on page 20 (MP oscillator) 22 56 pF
i2OSC2 driving current VDD=5V
VIN=VSS (MP oscillator) 110 190 µA
Oscil. Typical Crystal Resonator CL1
[pF] CL2
[pF] tSU(osc)
[ms] 2)
Reference Freq. Characteristic 1)
Crystal
MP JAUCH SS3-400-30-30/30 4MHz ∆fOSC=[±30ppm25°C,±30ppm∆Ta], Typ. RS=60Ω33 34 7~10
OSC2
OSC1 fOSC
CL1
CL2
i2
RF
ST7XXX
RESONATOR
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
ST7SCR
82/102
14.5 MEMORY CHARACTERISTI CS
Subject to general operating conditions for VDD, fOSC, and T A unless o the rwise specified .
14.5.1 RAM and Hardware Reg isters
14.5.2 FLASH M emory
Operating Conditions: fCPU = 8 MHz.
Warning: Do not connect 12V to VPP before VDD is powered on, as this may damage the device.
14.6 SMARTCARD SUPPLY SUPERVISO R ELECTRICAL CHARACTERIS TI CS
(TA = 0... +7 0oC, 4.0 < VDD - VSS < 5.5V unless othe rwise specifie d)
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention mode 1) HALT mode (or RESET) 2 V
DUAL VOLTAGE FLASH MEMORY
Symbol Parameter Conditions Min Typ Max Unit
fCPU Operating Frequ ency Read mode 8 MHz
Write / Erase mode,
TA=25°C 8
VPP Programming Voltage 4.0V <= VDD <= 5.5V 11.4 12.6 V
IPP VPP Current Write / Erase 30 mA
tPROG Byte Programmin g Time TA=25°C 100 500 µs
tERASE Sector Erasing Time 2 10 sec
Device Erasing Time 5 10
tVPP Internal VPP Stabilization Time 10 µs
tRET Data Reten tion TA ≤ 55°C 20 years
NRW Write Erase Cycles TA=25°C 100 cycles
SMARTC ARD SUPP LY SUPER VISO R
Symbol Parameter Conditions Min Typ Max Unit
5V regulator output (for IEC7816-3 Class A Cards)
VCARD SmartCard Power Supply Voltage 4.6 5.00 5.4 V
ISC SmartCard Supp ly Current 55 mA
IOVDET Current Overload Detection 120 1) mA
tIDET Detection time on Current Overload 170 1) 1400 1) µs
tOFF VCARD Turn off Time (see Figure 35 on
page 61)CLO A Dmax ≤ 4.7uF 750 µs
tON VCARD Turn on Time (see Figure 35 on
page 61)CLO A Dmax ≤ 4.7uF 150 500 µs
IVDD VDD supply current See note 100 mA
3V regulator output (for IEC7816-3 Class B Cards)
VCARD SmartCard Power Supply Voltage 2.7 3.3 V
ISC SmartCard Supply Current 50 mA
IOVDET Current Overload Detection 100 1) mA
tIDET Detection time on Current Overload 170 1) 1400 1) us
tOFF VCARD Turn off Time (see Figure 35 on
page 61)CLOADmax≤4.7uF 750 us
ST7SCR
83/102
Note 1 : Guaranteed by design.
Note 2 : Data based on characterization results, not tested in production.
Notes: VDD = 4.75 V, Card consumption = 55mA, CRDCLK frequency = 4MHz, LED with a 3mA current, USB in recep-
tion mode and CPU in WFI mode.
tON VCARD Turn on Time (see Figure 35 on
page 61)CLO A Dmax ≤ 4.7uF 150 500 µs
1.8V regulator output (for IEC7816-3 Class C Cards)
VCARD SmartCard Power Supply Voltage 1.65 1.95 V
ISC SmartCard Supply Current 20 mA
IOVDET Current Overload Detection 1001) mA
tIDET Detection time on Current Overload 170 1) 1400 1) us
tOFF VCARD Turn off Time (see Figure 35 on
page 61)CLO A Dmax ≤ 4.7uF 750 us
tON VCARD Turn on Time (see Figure 35 on
page 61)CLO A Dmax ≤ 4.7uF 150 500 µs
Smartcard CLKPin
VOL Output Low Level Voltage I=-50uA - - 0.4 2) V
VOH Output High Level Voltage I=50uA VCARD-0.5 2) -- V
T
OHL Output H-L Fall Time Cl=30pF - 20 ns
TOLH Output L-H Rise Time Cl=30pF - 20 ns
FVAR Frequency variat ion - 1 %
FDUTY Duty cycle 45 55 %
ISGND Short-circuit to Ground 15 mA
Smartcard I/O Pin
VIL Input Low Level Voltage - - 0.5 2) V
VIH Input High Level Voltage 0.6VCARD 2) -- V
V
OL Output Low Level Voltage I=-0.5mA - - 0.4 2) V
VOH Output High Level Voltage I=20uA 0.8VCARD 2) -V
CARD 2) V
ILInput Leak age Curren t VSS<VIN<VSC_PWR -10 - 10 µA
IRPU Pull-up Equivalent Resistance VIN=VSS 24 30 KΩ
TOHL Output H-L Fall Time Cl=30pF - 0.8 us
TOLH Output L-H Rise Time Cl=30pF - 0.8 us
ISGND Short-circuit to Ground 15 mA
Smartcard RST C4 and C8 Pin
VOL Output Low Level Voltage I=-0.5mA - - 0.4 2) V
VOH Output High Level Voltage I=20uA VCARD-0.5 2) -VCARD 2) V
TOHL Output H-L Fall Time Cl=30pF - 0.8 us
TOLH Output L-H Rise Time Cl=30pF - 0.8 us
ISGND Short-circuit to Ground 15 mA
SMARTC ARD SUPP LY SUPER VISO R
Symbol Parameter Conditions Min Typ Max Unit
ST7SCR
84/102
14.7 EMC CHARACTERIS TI CS
Sus ceptibility tests are performed on a sample ba-
sis during product charact erization.
14.7.1 Fun ctional EMS
(Electro Magnetic Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnet ic events
until a f ailure occurs (indicated by the LEDs).
■ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■FTB: A Burst of Fast Transi ent voltage (posi tive
and negative) is applied to VDD and VSS through
a 100pF capacit or, until a functional disturbance
occurs. This test conform s with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
Notes:
1. Data based on characterization results, not tested in production.
Symbol Parameter Conditions Neg 1) Pos 1) Unit
VFESD Voltage limits to be applied on any I/O pin
to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-2 1 0.7
kV
VFFTB
Fast transient voltage burst limits to be ap-
plied through 100pF on VDD and VDD pins
to induce a functional disturbance
VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-4 22
ST7SCR
85/102
EMC CHARACTERISTICS (Cont’d)
14.7.2 Absolute Electrical Sensi tivity
Based on th ree different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine it s performance in
terms of electrical sensitivity. For more details, re-
fer to t he AN1 181 ST7 appli cation note.
14.7.2.1 Electro-Static Dischar ge (ESD)
Electro-Static Discharges (1 positive then 1 nega-
tive pulse separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). The Huma n Bo dy Mod el is simulated.
This test conforms to the JESD22-A114A stand-
ard. S ee Figure 40 and the following test sequenc-
es.
Human B ody Mode l Test S e quenc e
– CL is loaded through S1 by the HV p ulse gener-
ator.
– S1 switches position from generator to R.
– A discharge from CL through R (body resistance)
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of t he next pulse.
14.7.2.2 Designing ha rden ed softwar e to av oi d
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefo re it is recom mended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Softwar e recommendations:
The software flowcha rt must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (c ontrol registers...)
Prequalification trials :
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied direc tly on t he device,over the range of spec-
ification values.When unexpected behaviour i s de-
tected,the sofware can be hardened to prev ent un-
recoverable errors o ccurring (see appl ication not e
AN1015).
Absolute Maximum Ratings
Figure 40. Typical Equivalent ESD Circuits
Notes:
1. Data based on characterization results, not tested in production.
Symbol Ratings Conditions Maximum value 1) Unit
VESD(HBM) Electro-static discharge voltage
(Human Body Model) TA=+25°C 1500 V
ST7 S2
R=1500Ω
S1
HIGH VOLTAGE CL=100pF
PULSE
GENERATOR
HUMAN BODY MODEL
ST7SCR
86/102
EMC CHARACTERISTICS (Cont’d)
14.7.2.3 Static and Dynamic Latch-U p
■LU: 3 complementary static tests are required
on 10 parts t o asses s t he l atch-up performance.
A supply overvoltage (applied to each power
sup ply pin), a current inje ct ion (applied to e ach
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on eac h sample. This test confo rm s to the EIA/
JESD 78 I C latch-up standard. For more details,
refer t o the AN1181 ST7 application note.
■DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 41. For
more details, refer to the AN1181 ST7
application note.
Electrical Sensi tivities
Figu re 41. S imp li fie d Diag ram of the ESD Gen e rato r fo r DLU
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that m ean s whe n a devic e bel ongs to C lass A it e xceed s the JED EC s tanda rd. B Cla ss str ictly c overs all t he
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Symbol Parameter Conditions Class 1)
LU Static latch- up class T A=+25°C A
DLU Dynamic latch-up class VDD=5.5V, fOSC=4MHz, TA=+25°C A
RCH=50MΩRD=330Ω
CS=150pF
ESD
HV RELAY
DISCHARGE TIP
DISCHARGE
RETURN CONNECTION
GENERATOR 2)
ST7
VDD
VSS
ST7SCR
87/102
EMC CHARACTERISTICS (Cont’d)
14.7.3 ESD Pin Protecti on Strateg y
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradat ion or destruction of the circuit el-
ements. The stress g enerally affec ts the circuit el-
ements which are conn ected to the pads bu t ca n
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
te cte d must not recei ve e xcessive cu rren t, voltage
or heating with in their st ructure.
An ESD network c ombines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pi ns subjected
to ESD stress. Two critical ESD stress cases are
presented in F igure 42 and Figure 43 for standard
pins.
Standard Pin Protection
To protect the output structure the following ele-
ment s are added:
– A diode t o VDD (3a) and a diode from VSS (3b)
– A protection device between VDD and VSS (4)
To protect the input structure the following ele-
ment s are added:
– A resistor in series wi th the pad (1)
– A diode t o VDD (2a) and a diode from VSS (2b)
– A protection device between VDD and VSS (4)
Figure 42. Positive Stress on a Standard Pad vs. VSS
Figure 43. Negative Stress on a Standard Pad vs. VDD
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
Path to avoid
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
ST7SCR
88/102
EMC CHARACTERISTICS (Cont’d)
Multisupply Configuration
When several types of ground (VSS, VSSA, ...) a nd
power supply (VDD, VDDA, .. .) ar e available for any
reason (better noise immunity...), the structure
shown in F igure 4 4 is implemen ted to prote ct the
device agains t ESD.
Figure 44. Multisupply Configuration
VDDA
VSSA
VDDA
VDD
VSS
BACK TO BACK DIODE
BETWEEN GROUNDS
VSSA
ST7SCR
89/102
14.8 COMMUNICATION INTERFAC E CHARACTERISTICS
14.8.1 USB - Universal Bus I nterface
Note 1: RL is t he load connected on the USB drivers.
Note 2: All the v oltages are measured from the l ocal ground potential.
Figure 45. USB: Data Signal Rise and Fall Time
Note1: Measured from 10% to 90% of the data signal. For more detailed informations, please refer to
Chapter 7 (Electrical) of the USB specif i cation (version 1.1).
USB DC Electrical Characteristics
Parameter Symbol Conditions Min. Max. Unit
Input Levels:
Differential Input Sensitivity VDI I(D+, D-) 0.2 V
Differential Common Mode Range VCM Includes VDI range 0.8 2.5 V
Single Ended Receiver Threshold VSE 1.3 2.0 V
Output Levels
Static Output Low VOL RL of 1.5K ohms to 3.6v 0.3 V
Static Output High VOH RL of 15K ohm to VSS 2.8 3.6 V
USBVCC: voltage level USBV VDD=5v 3.00 3.60 V
USB: Full speed electrical characteristics
Parameter Symbol Conditions Min Max Unit
Driver characteristics:
Rise time tr Note 1,CL=50 pF 4 20 ns
Fall Time tf Note 1, CL=50 pF 4 20 ns
Rise/ Fall Time matching trfm tr/tf 90 110 %
Output signal Crossover
Voltage VCRS 1.3 2.0 V
Differential
Da t a Lines
VSS
tf tr
Crossover
points
VCRS
ST7SCR
90/102
15 PACKAGE CHARACTERISTICS
15.1 PACKAGE MECHANICAL DATA
Figure 46. 64-P in Thin Qu ad Flat Pa ckag e
Figure 47. 24-Pi n P lastic Small Outline Package, 300-mil Width
Dim. mm inches
Min Typ Max Min Typ Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b0.30 0.37 0.45 0.012 0.015 0.018
c0.09 0.20 0.004 0.008
D 16.00 0.630
D1 14.00 0.551
E 16.00 0.630
E1 14.00 0.551
e0.80 0.031
θ0° 3.5° 7° 0° 3.5° 7°
L0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
Number of Pins
N64
c
h
L
L1
e
b
A
A1
A2
E
E1
D
D1
Dim. mm inches
Min Typ Max Min Typ Max
A2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B0.33 0.51 0.013 0.020
C0.23 0.32 0.009 0.013
D15.20 15.60 0.599 0.614
E7.40 7.60 0.291 0.299
e1.27 0.050
H10.00 10.65 0.394 0.419
h0.25 0.75 0.010 0.030
α0° 8° 0° 8°
L0.40 1.27 0.016 0.050
Number of Pins
N24
Dim. mm inches
Min Typ Max Min Typ Max
C
h x 45 ×
L
a
A
A1
e
B
D
H
E
ST7SCR
91/102
Figure 48. PACKAGE MECHANICAL DATA (Cont’d)
Figure 49. Reco mmend ed Reflow Oven Profile (MID JEDEC)
250
200
150
100
50
0100 200 300 400 Time [sec ]
Te mp. [°C]
ramp up
2°C/sec for 50sec
90 sec at 125°C 150 sec above 183°C
ramp down nat ural
2°C/sec max
Tmax=220+/-5°C
for 25 sec
ST7SCR
92/102
16 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in ROM
versions and in user programmable versions (High
Density FLASH).
FLASH devices are shipped to customers with a
default content (FFh).
This implies that FL ASH devices have to be con-
figured by the customer using the Option Byte
while the ROM devices are f actory-configured.
16.0.1 Option Bytes
The 8 option bits from the flash are programmed
through the static option byte SOB1. The desc ri p-
tion of each of th es e 8 bits i s given below.
Static option Byte (SOB1)
OPT7:6 = Reserved
OPT5= WDGSW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always activated)
1: Software (watchdog to be activated by software)
OPT4 = NEST
Interrupt Controller
This bit enables the nested Interrupt Controller.
0: Nes ted interrupt controll er disabled
1: Nes ted interrupt controll er enabl ed
OPT3 = ISOCLK
Clock source se lection
0: Card clock is generated by the divider (48MHz/
12 = 4MHz).
1: Card clock is generated by t he oscillator.
OPT2 = RETRY
Number of Retries for UART ISO
0: In case of an erroneous transfer, character is
transm itted 4 times.
1: In case of an erroneous transfer, character is
transm itted 5 times.
OPT1 =
Reserved, must be kept at 1.
OPT0 = FMP_R
Flash memory read-out protec-
tion
This option indicates if the user flash memory is
protected against read-out pi racy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. E rasing the
option bytes when the FMP_R option is selected
induce the whole user memory erasing first.
0 : read-out protection enabled
1 : read-out protection disabled
OPT
7654321
OPT
0
-- -- WDG-
SW NEST ISOCLKRETRY - FMP_R
ST7SCR
93/102
16.1 DEVICE ORDERING I NFORMATION AND TRANSFER OF CUST OMER CODE
Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means , with the hexadecimal file in .S19
format ge nerate d b y the development tool . All un-
used bytes must be set to FFh.
The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended. See page 94 .
The STMicr oelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.
Figure 50. Sales Type Coding Rules
Table 23. Ordering Information
Note 1. /xxx stands for the ROM or FASTROM-
co de nam e assigned by STM icroele ctronics.
ST7 FSCR1 R4B1/xxx
Family
Version Code
Sub family
Number of pins
ROM Size Code
Package Ty pe
Tempe rature Code
ROM Code (three letters)
1 = Standard (0 to +70°C) T = TQFP 4 = 16K R = 64 pins No letter = ROM
M = Plastic SO x = 24pins F = Flash
P = FASTROM
Sales Type 1) Program
Memory (byte s) RAM
(bytes) Package
ST7SCR1R4T1/xxx 16K ROM
768
TQFP64ST7PSCR1R4T1/xxx 16K FASTROM
ST7FSCR1R4T1 16K Flash
ST7SCR1E4M1/xxx 16K ROM SO24ST7PSCR1E4M1/xxx 16K FASTROM
ST7FSCR1E4M1 16K Flash
ST7SCR
94/102
ST7SCR MICROCONTROLLER O PTION LIST
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addre ss: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conta ct: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone N o: . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R eference/ROM Code* : . . . . . . . . . . . . . . . . . .
*The ROM code nam e is assigne d by STMicroelect ronics .
ROM code m ust be sent in .S 19 format. .Hex extension cannot be processed.
D evice Type/Mem ory Size/Pack age (check only one option):
Conditioning (check onl y one opt i on):
Note: Die product only for ROM device
Spe cial Marking: [ ] No [ ] Yes "_ _ _ _ _ _ _ _ _ _ "
Authorized characters are letters, digits, ’.’, ’ -’, ’ /’ and spaces only .
Maxim um character count:
S02 4 (13 char. max) : _ _ _ _ _ _ _ _ TQF P 64 (10 c har. max) : _ _ _ _ _ _ _ _ _ _
Watchdog: WDGSW [ ] Software Activation
[ ] Hardware Activation
Nested Interrupts NEST [ ] Nested Interrupts
[ ] Non Nested Interrupts
IS O C loc k Sour c e ISOCLK [ ] Osc illator
[ ] Divider
No. of Retries RETRY [ ] 5
[ ] 4
Readout Protection: FMP_R [ ] Disabled
[ ] Enabled
Sign ature
Date
--------------------------
ROM Device:
--------------------------|
|------------------------------------
16K
------------------------------------|
|
SO 24: | [ ] ST 7S CR1E4M 1 |
TQFP64: | [ ] ST7SCR1R4T1 |
--------------------------
FASTROM Device:
--------------------------|
|------------------------------------
16K
------------------------------------|
|
SO24: | [ ] ST 7PSCR1E4M1 |
TQFP64: | [ ] ST 7P SCR1R4T 1 |
-----------------------------------------------------------------
Packaged Product:
-----------------------------------------------------------------|
|----------------------------------------------------
Die Product (dice tested at 25°C only)
----------------------------------------------------
[ ] Tape & Reel [ ] Tray (TQFP package only) | [ ] Tape & Reel
[ ] Tube (SO package only) | [ ] Inked wafer
| [ ] Sawn wafer o n sticky foil
ST7SCR
95/102
16. 2 DEVELOPMENT TOOLS
Table 24. D evelopme nt Tools
16.2.1 ADAPTOR/SOCKET PROPOSAL
TBD
Development Tool Sales Type Remarks
Emulator ST7MDTS1-EMU2B
Programming Board ST7MDTS1-EPB2
ST7SCR
96/102
16.3 ST7 APPLICATION NO TES
IDENTIFICATION DESCRIPTION
EXAMPLE DRIVERS
AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC
AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971 I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION
AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
AN1046 UART EMULATION SOFTWARE
AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
AN1048 ST7 SOFTWARE LCD DRIVER
AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
AN1105 ST7 PCAN PERIPHERAL DRIVER
AN1129 PERMANENT MAGNET DC MOTOR DRIVE.
AN1130 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE
AN1149 HANDLING SUSPEND MODE ON A USB MOUSE
AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION
AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD
AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
AN1150 BENCHMARK ST72 VS PC16
AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
ST7SCR
97/102
AN 982 USING ST7 WITH CERAMIC RESONATOR
AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY
AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY
AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
AN1530 ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
PROGRAMMING AND TOOLS
AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985 EXECUTING CODE IN ST7 RAM
AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7
AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING
AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN
AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
AN1039 ST7 MATH UTILITY ROUTINES
AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
AN1179 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR
AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
IDENTIFICATION DESCRIPTION
ST7SCR
98/102
17 SUMMARY OF CHANGES
Description of the changes betwee n the current release of the specification and the previous one.
Revision Main changes Date
1.2 Removed LVD option bit (LVD cannot be disabled)
Updated Figure 7 on page 15 Dec-01
1.3
Changed status of the document
Changed Table 1, “Device Summary,” on page 1
Changed Figure 4 on page 10
Changed Section 4.2 on page 14
Added note in Section 4.5 on page 15
Changed description of the following registers in Section 12.3.4 on page 46: EP0R, Endpoint
Transmission Register and Endpoint 2 Reception Register.
Moved “Power Supply Management” chapter to Section 12.4.3.1 on page 56
Updated Section 14 on page 76
Added Section 14.7 on page 84
Changed Figure 46 on page 90
Removed references to true open drain pins
Changed Section 16.1 on page 93
Added warning in Section 14.5.2 on page 82
Added Erratasheet on page 99
March-03
Rev. 1.2
March 2003 99/102
ERRATA SHEET
ST7SCR LIMITATIONS AND CORRECTIONS
18 SILICON IDENTIFICATION
This document refers only to ST7FSCR devices s hown in Table 25. They ar e identifiabl e both
by the last letter of the Trace code marked on the dev ice package and by the last 3 digits of
the Internal Sales Type printed on the box label ( see al so Figure 51)
Table 25. Device Identificat ion
19 REFERENCE SPECIFICATION
ST7SCR Datasheet 1.3 (M ar ch 2003).
20 SILICON LIMITATIONS
20.1 UNEXPECTED RESET FETCH
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt controller
does not recognise the source of the interrupt and, by default, pa sses the RESE T vector ad-
dress to the CPU.
To solve this issue, a "POP CC " instruction must alwa ys be preced ed by a "SIM " instruction.
20.2 USB: TWO CONSECUTIV E SETUP TOKE NS
Description
Whe n tw o cons ecu tive S ETUP t ok ens are rec eiv ed and the s oftw are do es n ot hav e ti me t o
write the value 8 in the Endpoint 0 Reception Counter R egister (CNT0RXR), the data associ-
ated with the second SETU P ar e not copied to the buffer .
Impact
The im pact depends on the host be havio ur. In th e USB Spec 2.0 it is state d (chapter 5.5. 5
p43 ) tha t: “A S etu p tra nsac tion s houl d not no rm ally b e sent b efor e th e co mp letion o f a pre-
vious control transfer. However, if a transfer is aborted, for example, due to errors on the bus,
the host can s end the next Setup transaction prematurely fr om the endpoint’ s perspective”. If
the new Setup token is s ent because an error occurs in the pr evious one, it should contain the
same data so no application ma lfunction will occur.
Trace Code marked on device Internal Sales Type on box label
Flash Devices: “xxxxxxxxxX” 7FSCRxxxx$M1
7FSCRxxxx$T1
ERRATA SHEET
100/102
This limitation will be corrected i n the nex t si licon revision. In the new r evision, when a SETUP
token is re ceived, the value loaded in the internal counter is fi xed to 8 by hardware independ-
ently of the value in the CNT0RXR r egister.
20.3 USB BUFFER SHARED MEMORY ACCES S
Description
When fCPU i s at 4 MHz, a value w ritten in the USB buffer may be corr upted w hen VDD is le ss
than 4.4V. This limitation will be corrected in the next silicon revision.
Impact
USB buffer access cannot be guar anteed over the full VDD range when fCPU is at 4 MHz.
20.4 WDG (WATCHDOG ) LIMITATIONS
In f lash devi ces , t he W DG pres caler val ue is not 6553 6 as de scrib ed in Section 12.1.3 on
page 40 (Figure 25), it is actually 16.
This will be corrected in the next revision of the silicon.
20.5 SUPPLY CURRENT IN HALT MODE (SUSPEND) LIMITATIONS
The current consumption (IDD) in some devices m ay e xceed the maximum specified in the
documentation (up to 1mA).
Workaround
Declare 200mA max . pow er value in the US B Configur ation Descriptor .
20.5.1 VPP Pin Limitation
In the i mpacted fl ash dev ices, c ontrary to the datasheet spec ification (which speci fies that it
must be tied to VSS), the VPP pin m ust be tied to V DD in operating mode. This will be fixed in
the next silicon revision .
20.6 START-UP
The ST7SCR relies on internal LVD and it may not start- up correctly if the p ow er supply is
slow.
Workaround
Put a 1M Ω resistor between VDD and VSS to el iminate the offset on VDD that m ay cau se this
power-on problem.
ERRATA SHEET
101/102
20.7 I/O PORT INPUT H IGH LEVEL (VIH)
The VIH min value is 0.8*VDD and not 0.7*VDD as spec ified for the final silicon.
21 DEVICE MARKING
Figure 51. Revision M a rking on Box Label and Device Marking
22 ERRATA SHEET REVISION HISTORY
Revision Main Changes Date
1.2 Updated Secti on 2 0.5 "SUPPLY CURRENT IN HALT MODE (SUSPEND) Limi-
tations" on page 100
Added Sec tion 20.6 "S tart-UP" on page 100 03/13/03
TYPE xxxx
Internalxxx$xx
Trace Code
LAST 2 DIGITS AFTER $
IN INTERNAL SALES TYPE
INDICATE SILIC ON REV.
LAST LETTER OF TRACE CODE
ON DEVICE INDICATES
SILICON REV.
ON BOX LABEL
ERRATA SHEET
102/102
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no r esponsibility for the consequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or oth erwise under any pat ent or paten t rights of STMi croelectronics. Specific ations m entioned in this publication are s ubj ect
to change without notice. This publication supersedes and replaces all information previous ly supplied. STMicroelectronics products are not
authorized f or use as c ri tical com ponents in lif e support devices or systems wi t hout the express written ap proval of S T M i croele ctronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Pur ch ase of I2C Components by STMicroelectronics conveys a license under t he Philips I2C Patent. R ights to us e these component s in an
I2C sys tem is gr ant ed pro vided that the sys te m conform s to t h e I2C Standard Specification as defined by Philips.
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