Tsi310A-133CE - Tundra Semiconductor

Tsi310™ Feature Sheet

Features

133 MHz PCI-X Bus Bridge

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The Tsi310 Advantage

The Tundra Semiconductor (Tundra) Tsi310 is a 64-bit PCI-X bus bridge

that operates at speeds up to 133 MHz, and supports transfer rates up to

1 GByte/s. The PCI-X protocol is backward compatible with the PCI 2.2

bus standard ensuring that legacy PCI-based systems are portable to the

faster PCI-X en vironment.

The Tsi310 connects two electrically separate PCI-X bus domain s,

allowing concurrent operations on both buses. This results in optimal use

of the buses in various system configurations and enables hierarchical

expan sion of I/O b us structures. The de vice also supports conf igurations of

PCI or PCI-X mode on either bus, and in any combination.

In addition, the Tsi310 provides exte nsive buffering and prefetching

mechanisms for efficient data transfer between two buses, facilitating

multi-threaded operation and high system throughput.

Figure 1: Block Diagram

PCI-X Interfaces

The Tsi310 has two identical PCI-X Interfaces that each handle PCI and

PCI-X transactions for its respective bus, and, depending on the type of

transaction, can act as either a bus master or a bus slave. These Interfaces

transfer data and control information flo wing to and from the blocks shown

in Figure 1.

Primary PCI/PCI-X Bus

Secondary PCI/PCI-X Bus

80B6000_BK001_02

JTAG Secondary

Bus Arbiter

Primary

Clock PLL Secondary

Clock PLL

PCI-X

Interface

Bus

Master

Bus

Slave

PCI-X

Interface

Configuration Registers

Clocking & Reset

Data/Control Unit

Queue

Compare

Logic

Read Queue

8 entries PW Queue

8 entries

Address

Decode

Control

Logic

Burst Read

Buffer

4 Kbytes

Posted Write

Buffer

1 Kbyte

Single Data

Phase Buffer

4 Bytes

Data/Control Unit

Queue

Compare

Logic

Read Queue

8 entries PW Queue

8 entries

Address

Decode

Control

Logic

Burst Read

Buffer

4 Kbytes

Posted Write

Buffer

1 Kbyte

Single Data

Phase Buffer

4 Bytes Bus

Slave

Bus

Master

• Industry-standard 64-bit, 133-MHz

PCI-X bridge chip

• Full PCI 2.2 backward compatibility

• Allows concurrent primary and

secondary bus operation

• Supports conf igurat ion of PCI or PC I-X

mode on either bus in any combination

• Extensive built-in buffering and

prefetching mechanisms to enable

ef ficient data transfer between buses

• 304-pin, 31-mm HPBGA package

•3.3V I/Os

Optional Features

• Support for secondary side PCI-X

device privatization

• Ability to d efine an opaq ue (undecoded)

memory address region to facilitate

applications with embe dd ed pro cesso rs

• Definable base address register for use

by embedded subsystems on the

secondary bus

• Access to configuration register space

from the secondary bus

Standards

The Tsi310 complies with the following

industry standards:

• PCI-X Addendum to PCI Local Bus

Specification (Revision 1.0a)

• PCI Local Bus Specification

(Revision 2.2)

• PCI-to-PCI Bridge Architecture

Specification (Revision 1.1)

• PCI Bus Power Manage ment Interface

Specification (Revision 1.1)

•PCI Hot Plug Specification

(Revision 1.0)

Tsi310: 133 MHz PCI-X Bus Bridge

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Contact Information

Tundra Semiconductor Corporation

603 March Road, Kan ata

Ontario, Canada, K2K 2M5

Phone: 613- 592- 0714 or 1-8 00-2 67 -7231

Fax: 613-592-1320

www.tundra.com

Benefits The Tsi310 uses the 3.3V signaling environment. It employs two

phase-locked loops (PLLs), one for the primary clock domain and one for

the secondary clock domain. The PLL for each domain is used when the

bus is operating in PCI-X mode. In PCI mode, the PLL is bypassed to

allo w full frequenc y range as required b y the b us architecture . The two b us

clocks may be run synchronously or asynchronously, and a

spread-spectrum clock input is supported for either or both Interfaces.

Memory Buffer Architecture

The Tsi310 memory buffer architecture has the following features (see

Data/Control unit in Figure 1 ):

• Two 4-Kbyte burst read buffers that supp ort up to eight concurrent,

upstream and downstream transactions

• Two 1-Kbyte posted write buffers that support up to eight concurrent,

upstream and downstream transactions

• Two 4-Byte single data ph ase buffers that support transaction

forwarding in either direction

Transaction Forwarding

The Tsi310 includes one data/control unit for downstream transactions and

one for upstream transactions. Each of these identical units contains

separate buffers for burst read, posted write, and single data phase

operations. Also included in these blocks are write queues, queue compare

logic, address decoding upstream for forwarding, control logic, and other

control functions. The clocking and reset control unit manages these

common device functions.

The Tsi310 has I/O and Memory Base Address registers and Prefetchable

Memory Base Address registers for downstream forwarding, as well as

inverse decoding for upstream forwarding, VGA-compatible addressing,

and palette snooping for upstream transactions. The device uses a flat

addressing model and supports 64-bit addressing and dual address cycles.

The Tsi310 responds as a med iu m-speed device on both PCI-X Int erfaces,

and supports fast, back-to-back transactions as a bus slave.

PCI Bus Arbitration

The Tsi310 uses an arbiter for the secondary bus, which can be disabled if

an external arbiter is employed. W hen enabled, bus arbitration is provided

for the Tsi310 and up to six external masters. Each bu s master can be

assigned high or low priority, or be masked off.

Opaque Addressing (Optional)

The Tsi310 has an optional feature that can define an opaque (undecoded)

memory address region to facilitate applications with embedded

processors.

• Eases the migration of system designs

from PCI to the faster, more robust,

PCI-X protocol

• Simplifies system design by offering a

multitude of highly configurable

features

• Increases system performance b y

supporting concurrent, upstream and

downstream transactions

The Tsi310 eases the transi tion from PCI

bus architecture to the faster, more robust

PCI-X-based system designs.

Typical Applications

• Server RAID controllers

• External RAID systems

• Host bus adapters (for example, Fibre

Channel) in servers

• Network interface cards (NIC) in

switches/routers

Part Number

Tsi310-133CE