PIC18(L)F27/47K40 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with XLP Technology Description PIC18(L)F27/47K40 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications. These 28/40/44-pin devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons. They also offer a set of Core Independent Peripherals such as Complementary Waveform Generator (CWG), Windowed Watchdog Timer (WWDT), Cyclic Redundancy Check (CRC)/Memory Scan, Zero-Cross Detect (ZCD) and Peripheral Pin Select (PPS), providing for increased design flexibility and lower system cost. Core Features Power-Saving Operation Modes * C Compiler Optimized RISC Architecture * Only 83 Instructions * Operating Speed: - DC - 64 MHz clock input - 62.5 ns minimum instruction cycle * Programmable 2-Level Interrupt Priority * 31-Level Deep Hardware Stack * Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT) * Four 16-Bit Timers (TMR0/1/3/5) * Low-Current Power-on Reset (POR) * Power-up Timer (PWRT) * Brown-out Reset (BOR) * Low-Power BOR (LPBOR) Option * Programmable Code Protection * Windowed Watchdog Timer (WWDT): - Timer monitoring of overflow and underflow events - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software * Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower) * Idle: CPU Halted While Peripherals Operate * Sleep: Lowest Power Consumption * Peripheral Module Disable (PMD): - Ability to selectively disable hardware module to minimize active power consumption of unused peripherals Memory * * * * 128K bytes Program Flash Memory 3728 Bytes Data SRAM Memory 1024 Bytes Data EEPROM Direct, Indirect and Relative Addressing modes Operating Characteristics * Operating Voltage Ranges: - 1.8V to 3.6V (PIC18LF2x/4xK40) - 2.3V to 5.5V (PIC18F2x/4xK40) * Temperature Range: - Industrial: -40C to 85C - Extended: -40C to 125C 2016 Microchip Technology Inc. eXtreme Low-Power (XLP) Features * Sleep mode: 50 nA @ 1.8V, typical * Windowed Watchdog Timer: 500 nA @ 1.8V, typical * Secondary Oscillator: 500 nA @ 32 kHz * Operating Current: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical Digital Peripherals * Complementary Waveform Generator (CWG): - Rising and falling edge dead-band control - Full-bridge, half-bridge, 1-channel drive - Multiple signal sources * Capture/Compare/PWM (CCP) modules: - Two CCPs - 16-bit resolution for Capture/Compare modes - 10-bit resolution for PWM mode * 10-Bit Pulse-Width Modulators (PWM): - Two 10-bit PWMs * Serial Communications: - Two Enhanced USART (EUSART) with AutoBaud Detect, Auto-wake-up on Start. RS-232, RS-485, LIN compatible - SPI - I2C, SMBus and PMBusTM compatible * Up to 35 I/O Pins and One Input Pin: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change on all pins - Input level selection control Preliminary DS40001844B-page 1 PIC18(L)F27/47K40 Digital Peripherals (Continued) Clocking Structure * Programmable CRC with Memory Scan: - Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B) - Calculate CRC over any portion of Flash or EEPROM - High-speed or background operation * Hardware Limit Timer (TMR2/4/6+HLT): - Hardware monitoring and Fault detection * Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O * Data Signal Modulator (DSM) * High-Precision Internal Oscillator Block (HFINTOSC): - Selectable frequency range up to 64 MHz - 1% at calibration * 32 kHz Low-Power Internal Oscillator (LFINTOSC) * External 32 kHz Crystal Oscillator (SOSC) * External Oscillator Block: - Three crystal/resonator modes - 4x PLL with external sources * Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops * Oscillator Start-up Timer (OST) Analog Peripherals * 10-Bit Analog-to-Digital Converter with Computation (ADC2): - 35 external channels - Conversion available during Sleep - Four internal analog channels - Internal and external trigger options - Automated math functions on input signals: - averaging, filter calculations, oversampling and threshold comparison * Hardware Capacitive Voltage Divider (CVD) Support: - 8-bit precharge timer - Adjustable sample and hold capacitor array - Guard ring digital output drive * Zero-Cross Detect (ZCD): - Detect when AC signal on pin crosses ground * 5-Bit Digital-to-Analog Converter (DAC): - Output available externally - Programmable 5-bit voltage (% of VDD) - Internal connections to comparators, Fixed Voltage Reference and ADC * Two Comparators (CMP): - Four external inputs - External output via PPS * Fixed Voltage Reference (FVR) module: - 1.024V, 2.048V and 4.096V output levels 2016 Microchip Technology Inc. Programming/Debug Features * In-Circuit Debug Integrated On-Chip * In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) with Three Breakpoints via Two Pins Preliminary DS40001844B-page 2 PIC18(L)F27/47K40 Device Data Sheet Index Program Memory Flash (bytes) Data SRAM (bytes) Data EEPROM (bytes) I/O Pins 16-bit Timers Comparators 10-bit ADC2 with Computation (ch) 5-bit DAC Zero-Cross Detect CCP/10-bit PWM CWG 8-bit TMR with HLT Windowed Watchdog Timer CRC with Memory Scan EUSART I2C/SPI PPS Peripheral Module Disable Temperature Indicator Debug(1) PIC18(L)F2x/4xK40 Family Types PIC18(L)F24K40 (1) 16k 1024 256 25 4 2 24 1 1 2/2 1 3 Y Y 1 1 Y Y Y I PIC18(L)F25K40 (1) 32k 2048 256 25 4 2 24 1 1 2/2 1 3 Y Y 1 1 Y Y Y I PIC18(L)F26K40 (2) 64k 3728 1024 25 4 2 24 1 1 2/2 1 3 Y Y 2 2 Y Y Y I PIC18(L)F27K40 (3) 128k 3728 1024 25 4 2 24 1 1 2/2 1 3 Y Y 2 2 Y Y Y I PIC18(L)F45K40 (2) 32k 2048 256 36 4 2 35 1 1 2/2 1 3 Y Y 2 2 Y Y Y I PIC18(L)F46K40 (2) 64k 3728 1024 36 4 2 35 1 1 2/2 1 3 Y Y 2 2 Y Y Y I PIC18(L)F47K40 (3) 128k 3728 1024 36 4 2 35 1 1 2/2 1 3 Y Y 2 2 Y Y Y I Note 1: Debugging Methods: (I) - Integrated on Chip. Data Sheet Index: (Unshaded devices are described in this document.) 1. DS40001843 PIC18(L)F24/25K40 Data Sheet, 28-Pin, 8-bit Flash Microcontrollers 2. DS40001816 PIC18(L)F26/45/46K40 Data Sheet, 28/40/44-Pin, 8-bit Flash Microcontrollers 3. DS40001844 PIC18(L)F27/47K40 Data Sheet, 28/40/44-Pin, 8-bit Flash Microcontrollers Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 3 PIC18(L)F27/47K40 Pin Diagrams 28-pin SPDIP, SOIC, SSOP Note: 1 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 26 RB5 RA2 4 25 RB4 RA3 5 RB3 RA4 6 24 23 RA5 VSS 7 22 RB1 RB0 RA7 9 8 PIC18(L)F2xK40 VPP/MCLR/RE3 21 RB2 20 VDD VSS RA6 10 19 RC0 11 18 RC7 RC1 12 17 RC6 RC2 13 16 RC5 RC3 14 15 RC4 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 See Table 1 for location of all peripheral functions. RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 RA1 RA0 28-pin QFN (6x6x0.9mm), UQFN (4x4x0.5mm) 28 27 26 25 24 23 22 RA2 RA3 RA4 RA5 VSS RA7 RA6 1 2 3 4 5 6 7 PIC18(L)F2xK40 RC0 RC1 RC2 RC3 RC4 RC5 RC6 8 9 10 11 12 13 14 Note 1: See Table 1 for location of all peripheral functions. 2: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 4 PIC18(L)F27/47K40 40-pin PDIP Note: 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 RE0 7 34 RB1 RB0 RE1 9 RE2 10 VDD 11 VSS 12 RA7 RA6 RC0 8 PIC18(L)F4xK40 VPP/MCLR/RE3 33 32 VDD 31 VSS 30 RD7 29 RD6 13 28 RD5 14 27 RD4 15 26 RC7 RC1 16 25 RC6 RC2 17 RC5 RC3 18 24 23 RD0 19 22 RC4 RD3 RD1 20 21 RD2 See Table 2 for location of all peripheral functions. RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 40-pin UQFN (5x5x0.5mm) RC7 1 RD4 2 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 40 39 38 37 36 35 34 33 32 31 30 3 29 4 28 27 5 6 PIC18(L)F4xK40 26 7 25 8 24 23 9 22 21 10 RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 RB3 RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 11 12 13 14 15 16 17 18 19 20 Note 1: See Table 2 for location of all peripheral functions. 2: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 5 PIC18(L)F27/47K40 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 PIC18(L)F4xK40 7 8 9 10 11 RA6 RA7 NC VSS NC VDD RE2 RE1 RE0 RA5 RA4 RB3 NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD NC RB0 RB1 RB2 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 RC0 44-pin QFN (8x8x0.9mm) Note 1: See Table 2 for location of all peripheral functions. 2: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the only VSS connection to the device. RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC 44-pin TQFP RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PIC18(L)F4xK40 28 27 26 25 24 23 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 Note: NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 AN0/RA0 AN1/RA1 RA2 RA3 NC 12 13 14 15 16 17 18 19 20 21 22 See Table 2 for location of all peripheral functions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 6 Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-up Basic RA0 2 27 ANA0 -- C1IN0C2IN0- -- -- -- -- IOCA0 -- -- -- Y -- RA1 3 28 ANA1 -- C1IN1C2IN1- -- -- -- -- IOCA1 -- -- -- Y -- RA2 4 1 ANA2 DAC1OUT1 VREF- (DAC) VREF- (ADC) C1IN0+ C2IN0+ -- -- -- -- IOCA2 -- -- -- Y -- RA3 5 2 ANA3 VREF+ (DAC) VREF+ (ADC) C1IN1+ -- -- -- -- IOCA3 -- MDCIN1(1) -- Y -- RA4 6 3 ANA4 -- -- T0CKI(1) -- -- -- IOCA4 -- MDCIN2(1) -- Y -- RA5 7 4 ANA5 -- -- -- -- -- -- IOCA5 -- MDMIN(1) SS1(1) Y -- RA6 10 7 ANA6 -- -- -- -- -- -- IOCA6 -- -- -- Y CLKOUT OSC2 RA7 9 6 ANA7 -- -- -- -- -- -- IOCA7 -- -- -- Y OSC1 CLKIN RB0 21 18 ANB0 -- C2IN1+ -- -- CWG1(1) ZCDIN IOCB0 INT0(1) -- -- SS2(1) Y -- RB1 22 19 ANB1 -- C1IN3C2IN3- -- -- -- -- IOCB1 INT1(1) -- -- SCK2(1) SCL2(3,4) Y -- RB2 23 20 ANB2 -- -- -- -- -- -- IOCB2 INT2(1) -- -- SDI2(1) SDA2(3,4) Y -- RB3 24 21 ANB3 -- C1IN2C2IN2- -- -- -- -- IOCB3 -- -- -- Y -- RB4 25 22 ANB4 -- -- T5G(1) -- -- -- IOCB4 -- -- -- Y -- (1) I/O(2) RB5 26 23 ANB5 -- -- T1G -- -- -- IOCB5 -- -- -- Y -- RB6 27 24 ANB6 -- -- -- -- -- -- IOCB6 CK2(1) -- -- Y ICSPCLK RB7 28 25 ANB7 DAC1OUT2 -- T6AIN(1) -- -- -- IOCB7 RX2/DT2(1) -- -- Y ICSPDAT Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1). All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F27/47K40 DS40001844B-page 7 Reference Preliminary A/D 28-PIN ALLOCATION TABLE (PIC18(L)F27K40) 28-Pin (U)QFN TABLE 1: 28-Pin SPDIP, SOIC, SSOP 2016 Microchip Technology Inc. Pin Allocation Tables Reference Comparator CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-up Basic RC0 11 8 ANC0 -- -- T1CKI(1) T3CKI(1) T3G(1) -- -- -- IOCC0 -- -- -- Y SOSCO RC1 12 9 ANC1 -- -- -- CCP2(1) -- -- IOCC1 -- -- -- Y SOSCIN SOSCI RC2 13 10 ANC2 -- -- T5CKI(1) CCP1(1) -- -- IOCC2 -- -- -- Y -- RC3 14 11 ANC3 -- -- T2AIN(1) -- -- -- IOCC3 -- -- SCK1(1) SCL1(3,4) Y -- RC4 15 12 ANC4 -- -- -- -- -- -- IOCC4 -- -- SDI1(1) SDA1(3,4) Y -- RC5 16 13 ANC5 -- -- T4AIN(1) -- -- -- IOCC5 -- -- -- Y -- -- -- Y -- I/O(2) Timers A/D Preliminary 28-Pin (U)QFN 28-PIN ALLOCATION TABLE (PIC18(L)F27K40) (CONTINUED) 28-Pin SPDIP, SOIC, SSOP 2016 Microchip Technology Inc. TABLE 1: 17 14 ANC6 -- -- -- -- -- -- IOCC6 RC7 18 15 ANC7 -- -- -- -- -- -- IOCC7 RX1/DT1(1) -- -- Y -- RE3 1 26 -- -- -- -- -- -- -- IOCE3 -- -- -- Y VPP/MCLR VSS 19 16 -- -- -- -- -- -- -- -- -- -- -- -- VSS VDD 20 17 -- -- -- -- -- -- -- -- -- -- -- -- VDD VSS 8 5 -- -- -- -- -- -- -- -- -- -- -- -- VSS OUT(2) -- -- ADGRDA ADGRDB -- C1OUT C2OUT TMR0 CCP1 CCP2 PWM3 PWM4 CWG1A CWG1B CWG1C CWG1D -- -- TX1/CK1(3) DT1(3) TX2/CK2(3) DT2(3) DSM SDO1 SCK1 SDO2 SCK2 -- -- Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1). All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. DS40001844B-page 8 PIC18(L)F27/47K40 RC6 CK1(1) 44-Pin TQFP A/D Reference Comparator Timers CCP CWG ZCD Interrupt EUSART DSM MSSP Pull-up Basic RA0 2 17 19 19 ANA0 -- C1INOC2IN0- -- -- -- -- IOCA0 -- -- -- Y -- RA1 3 18 20 20 ANA1 -- C1IN1C2IN1- -- -- -- -- IOCA1 -- -- -- Y -- RA2 4 19 21 21 ANA2 DAC1OUT1 VREF- (DAC5) VREF- (ADC) C1IN0+ C2IN0+ -- -- -- -- IOCA2 -- -- -- Y -- RA3 5 20 22 22 ANA3 VREF+ (DAC5) VREF+ (ADC) C1IN1+ -- -- -- -- IOCA3 -- MDCIN1(1) -- Y -- RA4 6 21 23 23 ANA4 -- -- T0CKI(1) -- -- -- IOCA4 -- MDCIN2(1) -- Y -- RA5 7 22 24 24 ANA5 -- -- -- -- -- -- IOCA5 -- MDMIN(1) SS1(1) Y -- RA6 14 29 33 31 ANA6 -- -- -- -- -- -- IOCA6 -- -- -- Y CLKOUT OSC2 RA7 13 28 32 30 ANA7 -- -- -- -- -- -- IOCA7 -- -- -- Y OSC1 CLKIN RB0 33 8 9 8 ANB0 -- C2IN1+ -- -- CWG1(1) ZCDIN IOCB0 INT0(1) -- -- SS2(1) Y -- RB1 34 9 10 9 ANB1 -- C1IN3C2IN3- -- -- -- -- IOCB1 INT1(1) -- -- SCK2(1) SCL2(3,4) Y -- RB2 35 10 11 10 ANB2 -- -- -- -- -- -- IOCB2 INT2(1) -- -- SDI2(1) SDA2(3,4) Y -- RB3 36 11 12 11 ANB3 -- C1IN2C2IN2- -- -- -- -- IOCB3 -- -- -- Y -- RB4 37 12 14 14 ANB4 -- -- T5G(1) -- -- -- IOCB4 -- -- -- Y -- RB5 38 13 15 15 ANB5 -- -- T1G(1) -- -- -- IOCB5 -- -- -- Y -- RB6 39 14 16 16 ANB6 -- -- -- -- -- -- IOCB6 CK2(1) -- -- Y ICSPCLK RB7 40 15 17 17 ANB7 DAC1OUT2 -- T6AIN(1) -- -- -- IOCB7 RX2/DT2(1) -- -- Y ICSPDAT T1CKI(1) T3CKI(1) (1) -- -- -- IOCC0 -- -- -- Y SOSCO -- CCP2(1) -- -- IOCC1 -- -- -- Y SOSCIN SOSCI I/O(2) RC0 15 30 34 32 ANC0 -- -- RC1 16 31 35 35 ANC1 -- -- T3G DS40001844B-page 9 Note 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1). All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F27/47K40 44-Pin QFN Preliminary 40-Pin UQFN 40/44-PIN ALLOCATION TABLE (PIC18(L)F47K40) 40-Pin PDIP 2016 Microchip Technology Inc. TABLE 2: CCP1(1) -- -- IOCC2 -- -- -- Y -- -- -- -- IOCC3 -- -- SCK1(1) SCL1(3,4) Y -- -- -- SDI1(1) SDA1(3,4) -- -- Preliminary 18 33 37 37 ANC3 -- -- RC4 23 38 42 42 ANC4 -- -- -- -- -- -- IOCC4 RC5 24 39 43 43 ANC5 -- -- T4AIN(1) -- -- -- IOCC5 -- -- -- Y -- RC6 25 40 44 44 ANC6 -- -- -- -- -- -- IOCC6 CK1(1) -- -- Y -- RC7 26 1 1 1 ANC7 -- -- -- -- -- -- IOCC7 RX1/DT1(1) -- -- Y -- RD0 19 34 38 38 AND0 -- -- -- -- -- -- IOCD0 -- -- -- Y -- RD1 20 35 39 39 AND1 -- -- -- -- -- -- IOCD1 -- -- -- Y -- RD2 21 36 40 40 AND2 -- -- -- -- -- -- IOCD2 -- -- -- Y -- RD3 22 37 41 41 AND3 -- -- -- -- -- -- IOCD3 -- -- -- Y -- RD4 27 2 2 2 AND4 -- -- -- -- -- -- IOCD4 -- -- -- Y -- RD5 28 3 3 3 AND5 -- -- -- -- -- -- IOCD5 -- -- -- Y -- RD6 29 4 4 4 AND6 -- -- -- -- -- -- IOCD6 -- -- -- Y -- RD7 30 5 5 5 AND7 -- -- -- -- -- -- IOCD7 -- -- -- Y -- RE0 8 23 25 25 ANE0 -- -- -- -- -- -- -- -- -- -- Y -- RE1 9 24 26 26 ANE1 -- -- -- -- -- -- -- -- -- -- Y -- RE2 10 25 27 27 ANE2 -- -- -- -- -- -- -- -- -- -- Y -- RE3 1 16 18 18 -- -- -- -- -- -- -- IOCE3 -- -- -- Y VPP/MCLR VSS 12 6 6 6 -- -- -- -- -- -- -- -- -- -- -- -- VSS VDD 11 7 7 7 -- -- -- -- -- -- -- -- -- -- -- -- VDD VDD 32 26 28 28 -- -- -- -- -- -- -- -- -- -- -- -- VDD VSS 31 27 30 29 -- -- -- -- -- -- -- -- -- -- -- -- VSS OUT(2) -- -- ADGRDA ADGRDB -- C1OUT C2OUT TMR0 CCP1 CCP2 PWM3 PWM4 CWG1A CWG1B CWG1C CWG1D -- -- TX1/ CK1(3) DT1(3) TX2/ CK2(3) DT2(3) DSM SDO1 SCK1 SDO2 SCK2 -- -- OUT(2) -- 1: 2: 3: 4: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1). All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds. PIC18(L)F27/47K40 DS40001844B-page 10 RC3 Note T2AIN (1) Basic T5CKI(1) Pull-up -- MSSP -- DSM Timers ANC2 EUSART Comparator 36 Interrupt Reference 36 ZCD A/D 32 CWG 44-Pin TQFP 17 CCP 44-Pin QFN RC2 40-Pin UQFN I/O(2) 40/44-PIN ALLOCATION TABLE (PIC18(L)F47K40) (CONTINUED) 40-Pin PDIP 2016 Microchip Technology Inc. TABLE 2: PIC18(L)F27/47K40 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with PIC18(L)F26/45/46K40 Microcontrollers ............................................................................ 18 3.0 Device Configuration .................................................................................................................................................................. 21 4.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 34 5.0 Reference Clock Output Module ................................................................................................................................................ 53 6.0 Power-Saving Operation Modes ................................................................................................................................................ 58 7.0 Peripheral Module Disable (PMD).............................................................................................................................................. 66 8.0 Resets ........................................................................................................................................................................................ 73 9.0 Windowed Watchdog Timer (WWDT) ........................................................................................................................................ 82 10.0 Memory Organization ................................................................................................................................................................. 91 11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 123 12.0 8x8 Hardware Multiplier............................................................................................................................................................ 147 13.0 Cyclic Redundancy Check (CRC) Module with Memory Scanner............................................................................................ 149 14.0 Interrupts .................................................................................................................................................................................. 166 15.0 I/O Ports ................................................................................................................................................................................... 196 16.0 Interrupt-on-Change ................................................................................................................................................................. 208 17.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 212 18.0 Timer0 Module ......................................................................................................................................................................... 220 19.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 226 20.0 Timer2/4/6 Module ................................................................................................................................................................... 242 21.0 Capture/Compare/PWM Module .............................................................................................................................................. 263 22.0 Pulse-Width Modulation (PWM ) .............................................................................................................................................. 277 23.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 285 24.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 291 25.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 318 26.0 Master Synchronous Serial Port Module ................................................................................................................................. 329 27.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 386 28.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 417 29.0 Temperature Indicator Module ................................................................................................................................................. 419 30.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 421 31.0 Analog-to-Digital Converter with Computation (ADC2) Module ............................................................................................... 425 32.0 Comparator Module.................................................................................................................................................................. 461 33.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 471 34.0 In-Circuit Serial ProgrammingTM (ICSPTM) ............................................................................................................................... 478 35.0 Instruction Set Summary .......................................................................................................................................................... 480 36.0 Development Support............................................................................................................................................................... 530 37.0 Electrical Specifications............................................................................................................................................................ 534 38.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 564 39.0 Packaging Information.............................................................................................................................................................. 565 Appendix A: Revision History............................................................................................................................................................. 589 Appendix B: Device Differences ........................................................................................................................................................ 590 The Microchip Website ...................................................................................................................................................................... 591 Customer Change Notification Service .............................................................................................................................................. 591 Customer Support .............................................................................................................................................................................. 591 Product Identification System ............................................................................................................................................................ 592 2016 Microchip Technology Inc. Preliminary DS40001844B-page 11 PIC18(L)F27/47K40 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Website; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 12 PIC18(L)F27/47K40 1.0 DEVICE OVERVIEW 1.1.2 This document contains device specific information for the following devices: * PIC18F27K40 * PIC18LF27K40 * PIC18F47K40 * PIC18LF47K40 This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of high-endurance, Program Flash Memory. In addition to these features, the PIC18(L)F2x/4xK40 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 1.1.1 New Core Features XLP TECHNOLOGY All of the devices in the PIC18(L)F2x/4xK40 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the secondary oscillator or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-fly Mode Switching: The powermanaged modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * Peripheral Module Disable: Modules that are not being used in the code can be selectively disabled using the PMD module. This further reduces the power consumption. 2016 Microchip Technology Inc. MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18(L)F2x/4xK40 family offer several different oscillator options. The PIC18(L)F2x/ 4xK40 family can be clocked from several different sources: * HFINTOSC - 1-16 MHz precision digitally controlled internal oscillator * LFINTOSC - 31 kHz internal oscillator * EXTOSC - External clock (EC) - Low-power oscillator (LP) - Medium power oscillator (XT) - High-power oscillator (HS) * SOSC - Secondary oscillator circuit operating at 31 kHz * A Phase Lock Loop (PLL) frequency multiplier (4x) is available to both the External and Internal Oscillator modes enabling clock speeds of up to 64 MHz Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available. Preliminary DS40001844B-page 13 PIC18(L)F27/47K40 1.2 Other Special Features 1.3 * Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. * Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a boot loader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Extended Instruction Set: The PIC18(L)F2x/ 4xK40 family introduces an optional extension to the PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. * Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. * Enhanced Addressable EUSART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN bus protocol. Other enhancements include automatic baud rate detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). * 10-bit A/D Converter with Computation: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. It has a new module called ADC2 with computation features, which provides a digital filter and threshold interrupt functions. * Windowed Watchdog Timer (WWDT): - Timer monitoring of overflow and underflow events - Variable prescaler selection - Variable window size selection - All sources configurable in hardware or software 2016 Microchip Technology Inc. Details on Individual Family Members Devices in the PIC18(L)F2x/4xK40 family are available in 28-pin and 40/44-pin packages. The block diagram for this device is shown in Figure 1-1. The devices have the following differences: 1. 2. 3. 4. 5. 6. 7. Program Flash Memory Data Memory SRAM Data Memory EEPROM A/D channels I/O ports Enhanced USART Input Voltage Range/Power Consumption All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in the pin summary tables (Table 1 and Table 2). Preliminary DS40001844B-page 14 PIC18(L)F27/47K40 TABLE 1-1: DEVICE FEATURES PIC18(L)F27K40 PIC18(L)F47K40 Program Memory (Bytes) Features 131072 131072 Program Memory (Instructions) 65536 65536 Data Memory (Bytes) 3720 3720 Data EEPROM Memory (Bytes) 1024 1024 (1) I/O Ports A,B,C,D,E(1) A,B,C,E Capture/Compare/PWM Modules (CCP) 2 10-Bit Pulse-Width Modulator (PWM) 10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator 2 2 2 4 internal 24 external 4 internal 35 external 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin UQFN Packages 40-pin PDIP 40-pin UQFN 44-pin QFN 44-pin TQFP Interrupt Sources 36 Timers (16-/8-bit) 4/3 2 MSSP, 2 EUSART Serial Communications Enhanced Complementary Waveform Generator (ECWG) 1 Zero-Cross Detect (ZCD) 1 Data Signal Modulator (DSM) 1 Peripheral Pin Select (PPS) Yes Peripheral Module Disable (PMD) Yes 16-bit CRC with NVMSCAN Yes Programmable High/Low-Voltage Detect (HLVD) Yes Programmable Brown-out Reset (BOR) Yes POR, BOR, RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT Resets (and Delays) 75 Instructions; 83 with Extended Instruction Set enabled Instruction Set Operating Frequency Note 1: DC - 64 MHz PORTE contains the single RE3 input-only pin. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 15 PIC18(L)F27/47K40 FIGURE 1-1: PIC18(L)F2X/4XK40 FAMILY BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic Data Memory PCLATU PCLATH 21 PORTA Address Latch 20 PCU PCH PCL Program Counter RA<7:0> 12 Data Address<12> 31-Level Stack 4 BSR Address Latch Program Memory (8/16/32/64 Kbytes) STKPTR 12 FSR0 FSR1 FSR2 Data Latch 8 PORTB 12 RB<7:0> inc/dec logic Table Latch Instruction Bus <16> 4 Access Bank Address Decode ROM Latch PORTC RC<7:0> IR 8 State machine control signals Instruction Decode and Control PRODH PRODL PORTD 8x8 Multiply 3 8 W BITOP 8 Internal Oscillator Block Power-up Timer SOSCI LFINTOSC Oscillator SOSCO 64 MHz Oscillator Oscillator Start-up Timer Power-on Reset OSC1(2) OSC2(2) Single-Supply Programming In-Circuit Debugger MCLR(1) BOR HLVD FVR DAC Note Comparators C1/C2 Brown-out Reset Fail-Safe Clock Monitor CCP1 CCP2 PWM3 PWM4 Timer1 Timer3 Timer5 Timer2 Timer4 Timer6 8 8 8 Watchdog Timer Data Timer0 EEPROM 8 PORTE ALU<8> RE<2:0> RE3(1) 8 Precision Band Gap Reference ZCD MSSP1 EUSART1 ECWG MSSP2 EUSART2 RD<7:0> FVR CRC-Scan DSM DAC PMD ADC 10-bit FVR 1: RE3 is only available when MCLR functionality is disabled. 2: OSC1/CLKIN and OSC2/CLKOUT are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 4.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for additional information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 16 PIC18(L)F27/47K40 1.4 1.4.1 Register and Bit naming conventions 1.4.2.3 REGISTER NAMES When there are multiple instances of the same peripheral in a device, the peripheral control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an `x' in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.4.2 BIT NAMES There are two variants for bit names: * Short name: Bit function abbreviation * Long name: Peripheral abbreviation + short name 1.4.2.1 Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the COG1CON0 register can be set in C programs with the instruction COG1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.4.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction. 2016 Microchip Technology Inc. Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1<<G1MD1) COG1CON0,F 1<<G1MD2 | 1<<G1MD0 COG1CON0,F Example 2: BSF BCF BSF COG1CON0,G1MD2 COG1CON0,G1MD1 COG1CON0,G1MD0 1.4.3 1.4.3.1 REGISTER AND BIT NAMING EXCEPTIONS Status, Interrupt, and Mirror Bits Status, interrupt enables, interrupt flags, and mirror bits are contained in registers that span more than one peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant. 1.4.3.2 Legacy Peripherals There are some peripherals that do not strictly adhere to these naming conventions. Peripherals that have existed for many years and are present in almost every device are the exceptions. These exceptions were necessary to limit the adverse impact of the new conventions on legacy code. Peripherals that do adhere to the new convention will include a table in the registers section indicating the long name prefix for each peripheral instance. Peripherals that fall into the exception category will not have this table. These peripherals include, but are not limited to, the following: * EUSART * MSSP Preliminary DS40001844B-page 17 PIC18(L)F27/47K40 2.0 2.1 GUIDELINES FOR GETTING STARTED WITH PIC18(L)F27/47K40 MICROCONTROLLERS 2.2 Basic Connection Requirements Consider the following criteria when using decoupling capacitors: 2.2.1 The following pins must always be connected: * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") These pins must also be connected if they are being used in the end application: * PGC/PGD pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.4 "ICSPTM Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.5 "External Oscillator Pins") Additionally, the following pins may be required: * VREF+/VREF- pins are used when external voltage reference for analog modules is implemented The minimum mandatory connections are shown in Figure 2-1. RECOMMENDED MINIMUM CONNECTIONS Rev. 10-000249A 9/1/2015 VDD VDD R1 R2 Vss C2 MCLR C1 PIC18(L)Fxxxxx Vss Key (all values are recommendations): C1 and C2 : 0.1 PF, 20V ceramic R1: 10 k R2: 100 to 470 2016 Microchip Technology Inc. DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required. Getting started with the PIC18(L)F27/47K40 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. FIGURE 2-1: Power Supply Pins * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. 2.2.2 TANK CAPACITORS On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. Preliminary DS40001844B-page 18 PIC18(L)F27/47K40 2.3 Master Clear (MCLR) Pin 2.4 The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: ICSPTM Pins The PGC and PGD pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGCx/PGDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 36.0 "Development Support". EXAMPLE OF MCLR PIN CONNECTIONS VDD R1 R2 JP MCLR PIC18(L)F2x/4xK40 C1 Note 1: R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. 2: R2 470 will limit any current flowing into MCLR from the external capacitor, C1, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 19 PIC18(L)F27/47K40 2.5 External Oscillator Pins 2.6 Unused I/Os Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 4.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for details). Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low. The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. FIGURE 2-3: Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-3. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. Primary Oscillator Crystal DEVICE PINS Primary Oscillator OSC1 C1 OSC2 GND C2 SOSCO SOSCI Secondary Oscillator (SOSC) Crystal SOSC: C1 In planning the application's routing and I/O assignments, ensure that adjacent port pins, and other signals in close proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate website (www.microchip.com): SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT SOSC: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work" OSCO C2 Oscillator Crystal GND C1 OSCI DEVICE PINS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 20 PIC18(L)F27/47K40 3.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection, Device ID and Rev ID. 3.1 Configuration Words There are six Configuration Word bits that allow the user to setup the device with several choices of oscillators, Resets and memory protection options. These are implemented as Configuration Word 1 through Configuration Word 6 at 300000h through 30000Bh. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a `1'. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 21 PIC18(L)F27/47K40 3.2 Register Definitions: Configuration Words REGISTER 3-1: U-1 Configuration Word 1L (30 0000h): Oscillators R/W-1 -- R/W-1 RSTOSC<2:0> R/W-1 U-1 R/W-1 -- R/W-1 R/W-1 FEXTOSC<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `1' bit 6-4 RSTOSC<2:0>: Power-up Default Value for COSC bits This value is the Reset default value for COSC and selects the oscillator first used by user software. Refer to COSC operation. 111 = EXTOSC operating per FEXTOSC bits (device manufacturing default) 110 = HFINTOSC with HFFRQ = 4 MHz (Register 4-5) and CDIV = 4:1 (Register 4-2) 101 = LFINTOSC 100 = SOSC 011 = Reserved 010 = EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits 001 = Reserved 000 = HFINTOSC with HFFRQ = 64 MHz (Register 4-5) and CDIV = 1:1 (Register 4-2). Resets COSC/NOSC to 3'b110. bit 3 Unimplemented: Read as `1' bit 2-0 FEXTOSC<2:0>: FEXTOSC External Oscillator Mode Selection bits 111 = EC (external clock) above 8 MHz; PFM set to high power (device manufacturing default) 110 = EC (external clock) for 500 kHz to 8 MHz; PFM set to medium power 101 = EC (external clock) below 500 kHz; PFM set to low power 100 = Oscillator not enabled 011 = Reserved (do not use) 010 = HS (crystal oscillator) above 8 MHz; PFM set to high power 001 = XT (crystal oscillator) above 500 kHz, below 8 MHz; PFM set to medium power 000 = LP (crystal oscillator) optimized for 32.768 kHz; PFM set to low power 2016 Microchip Technology Inc. Preliminary DS40001844B-page 22 PIC18(L)F27/47K40 REGISTER 3-2: Configuration Word 1H (30 0001h): Oscillators U-1 U-1 R/W-1 U-1 R/W-1 U-1 U-1 R/W-1 -- -- FCMEN -- CSWEN -- -- CLKOUTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `1' bit 5 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = FSCM timer enabled 0 = FSCM timer disabled bit 4 Unimplemented: Read as `1' bit 3 CSWEN: Clock Switch Enable bit 1 = Writing to NOSC and NDIV is allowed 0 = The NOSC and NDIV bits cannot be changed by user software bit 2-1 Unimplemented: Read as `1' bit 0 CLKOUTEN: Clock Out Enable bit If FEXTOSC = HS, XT, LP, then this bit is ignored Otherwise: 1 = CLKOUT function is disabled; I/O or oscillator function on OSC2 0 = CLKOUT function is enabled; FOSC/4 clock appears at OSC2 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 23 PIC18(L)F27/47K40 REGISTER 3-3: R/W-1 Configuration Word 2L (30 0002h): Supervisor R/W-1 BOREN<1:0> R/W-1 U-1 U-1 U-1 R/W-1 R/W-1 LPBOREN -- -- -- PWRTE MCLRE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 BOREN<1:0>: Brown-out Reset Enable bits When enabled, Brown-out Reset Voltage (VBOR) is set by BORV bit 11 = Brown-out Reset enabled, SBOREN bit is ignored 10 = Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored 01 = Brown-out Reset enabled according to SBOREN 00 = Brown-out Reset disabled bit 5 LPBOREN: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 4-2 Unimplemented: Read as `1' bit 1 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 0 MCLRE: Master Clear (MCLR) Enable bit If LVP = 1 RE3 pin function is MCLR If LVP = 0 1 = MCLR pin is MCLR 0 = MCLR pin function is port defined function 2016 Microchip Technology Inc. Preliminary DS40001844B-page 24 PIC18(L)F27/47K40 REGISTER 3-4: Configuration Word 2H (30 0003h): Supervisor R/W-1 U-1 R/W-1 R/W-1 R/W-1 R/W-1 XINST -- DEBUG STVREN PPS1WAY ZCD R/W-1 R/W-1 BORV<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 XINST: Extended Instruction Set Enable bit 1 = Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode) 0 = Extended Instruction Set and Indexed Addressing mode enabled bit 6 Unimplemented: Read as `1' bit 5 DEBUG: Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger enabled bit 4 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 3 PPS1WAY: PPSLOCKED bit One-Way Set Enable bit 1 = The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 = The PPSLOCKED bit can be set and cleared as needed (provided an unlocking sequence is executed) bit 2 ZCD: ZCD Disable bit 1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 = ZCD always enabled, ZCDMD bit is ignored bit 1-0 BORV<1:0>: Brown-out Reset Voltage Selection bit(1) PIC18F2x/4xK40 device: 11 = Brown-out Reset Voltage (VBOR) set to 2.45V 10 = Brown-out Reset Voltage (VBOR) set to 2.45V 01 = Brown-out Reset Voltage (VBOR) set to 2.7V 00 = Brown-out Reset Voltage (VBOR) set to 2.85V PIC18LF2x/4xK40 device: 11 = Brown-out Reset Voltage (VBOR) set to 1.90V 10 = Brown-out Reset Voltage (VBOR) set to 2.45V 01 = Brown-out Reset Voltage (VBOR) set to 2.7V 00 = Brown-out Reset Voltage (VBOR) set to 2.85V Note 1: The higher voltage setting is recommended for operation at or above 16 MHz. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 25 PIC18(L)F27/47K40 REGISTER 3-5: U-1 CONFIGURATION WORD 3L (30 0004h): WINDOWED WATCHDOG TIMER R/W-1 -- R/W-1 R/W-1 R/W-1 R/W-1 WDTE<1:0> R/W-1 R/W-1 WDTCPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `1' bit 6-5 WDTE<1:0>: WDT Operating Mode bits 11 = WDT enabled regardless of Sleep; SEN bit in WDTCON0 is ignored 10 = WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit in WDTCON0 is ignored 01 = WDT enabled/disabled by SEN bit in WDTCON0 00 = WDT disabled, SEN bit in WDTCON0 is ignored bit 4-0 WDTCPS<4:0>: WDT Period Select bits WDTPS at POR WDTCPS Typical Time Out (FIN = 31 kHz) Software Control of WDTPS? Value Divider Ratio 11111 01011 1:65536 216 2s Yes 10011 ... 11110 10011 ... 11110 1:32 25 1 ms No 10010 10010 1:8388608 223 256s 10001 10001 1:4194304 222 128s 21 64s 10000 10000 1:2097152 2 01111 01111 1:1048576 220 32s 16s 01110 01110 1:524299 219 01101 01101 1:262144 218 8s 4s 01100 01100 1:131072 217 01011 01011 1:65536 216 2s 15 1s 01010 01010 1:32768 2 01001 01001 1:16384 214 512 ms 256 ms 128 ms 01000 01000 1:8192 213 00111 00111 1:4096 212 11 64 ms 00110 00110 1:2048 2 00101 00101 1:1024 210 32 ms 9 00100 00100 1:512 2 16 ms 00011 00011 1:256 28 8 ms 4 ms 00010 00010 1:128 27 00001 00001 1:64 26 2 ms 1:32 5 1 ms 00000 2016 Microchip Technology Inc. 00000 Preliminary 2 No DS40001844B-page 26 PIC18(L)F27/47K40 REGISTER 3-6: CONFIGURATION WORD 3H (30 0005h): WINDOWED WATCHDOG TIMER U-1 U-1 -- -- R/W-1 R/W-1 R/W-1 R/W-1 WDTCCS<2:0> R/W-1 R/W-1 WDTCWS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `1' bit 5-3 WDTCCS<2:0>: WDT Input Clock Selector bits If WDTE<1:0> fuses = 2'b00 This bit is ignored. Otherwise: 111 = Software Control 110 = Reserved (Default to LFINTOSC) . . . 010 = Reserved (Default to LFINTOSC) 001 = WDT reference clock is the 31.25 kHz HFINTOSC (MFINTOSC) 000 = WDT reference clock is the 31.0 kHz LFINTOSC (default value) bit 2-0 WDTCWS<2:0>: WDT Window Select bits WINDOW at POR WDTCWS 111 Value Window delay Percent of time Window opening Percent of time Software control of WINDOW Keyed access required? 111 n/a 100 Yes No No Yes 110 111 n/a 100 101 101 25 75 100 100 37.5 62.5 011 011 50 50 010 010 62.5 37.5 001 001 75 25 000 000 87.5 12.5 2016 Microchip Technology Inc. Preliminary DS40001844B-page 27 PIC18(L)F27/47K40 Register 3-7: Configuration Word 4L (30 0006h): Memory Write Protection R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WRT7 WRT6 WRT5 WRT4 WRT3 WRT2 WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown WRT<7:0>: User NVM Self-Write Protection bits(1) 1 = Corresponding Memory Block NOT write-protected 0 = Corresponding Memory Block write-protected Note 1: Refer to Table 10-2 for details on implementation of the individual WRT bits. Register 3-8: Configuration Word 4H (30 0007h): Memory Write Protection U-1 U-1 R/W-1 R/W-1 U-1 R/W-1 R/W-1 R/W-1 -- -- LVP SCANE -- WRTD WRTB WRTC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as `1' bit 5 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored. The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating LVP mode from the Configuration state. 0 = HV on MCLR/VPP must be used for programming bit 4 SCANE: Scanner Enable bit 1 = Scanner module is available for use, SCANMD bit enables the module 0 = Scanner module is NOT available for use, SCANMD bit is ignored bit 3 Unimplemented: Read as `1' bit 2 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM NOT write-protected 0 = Data EEPROM write-protected bit 1 WRTB: Boot Block Write Protection bit 1 = Boot Block NOT write-protected 0 = Boot Block write-protected bit 0 WRTC: Configuration Register Write Protection bit 1 = Configuration Register NOT write-protected 0 = Configuration Register write-protected 2016 Microchip Technology Inc. Preliminary DS40001844B-page 28 PIC18(L)F27/47K40 REGISTER 3-9: Configuration Word 5L (30 0008h): Code Protection U-1 U-1 U-1 U-1 U-1 U-1 R/W-1 R/W-1 -- -- -- -- -- -- CPD CP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `1' bit 1 CPD: Data NVM Memory Code Protection bit 1 = Data NVM code protection disabled 0 = Data NVM code protection enabled bit 0 CP: User NVM Program Memory Code Protection bit 1 = User NVM code protection disabled 0 = User NVM code protection enabled REGISTER 3-10: x = Bit is unknown Configuration Word 6L (30 000Ah): Memory Read Protection R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 EBTR7 EBTR6 EBTR5 EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown EBTR<7:0>: Table Read Protection bits(1) 1 = Corresponding Memory Block NOT protected from table reads executed in other blocks 0 = Corresponding Memory Block protected from table reads executed in other blocks Note 1: Refer to Table 10-2 for details on implementation of the individual EBTR bits. REGISTER 3-11: Configuration Word 6H (30 000Bh): Memory Read Protection U-1 U-1 U-1 U-1 U-1 U-1 R/W-1 U-1 -- -- -- -- -- -- EBTRB -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `1' -n = Value for blank device `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as `1' bit 1 EBTRB: Table Read Protection bit 1 = Memory Boot Block NOT protected from table reads executed in other blocks 0 = Memory Boot Block protected from table reads executed in other blocks bit 0 Unimplemented: Read as `1' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 29 2016 Microchip Technology Inc. TABLE 3-1: Address SUMMARY OF CONFIGURATION WORDS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value -- RSTOSC2 RSTOSC1 RSTOSC0 -- FEXTOSC2 FEXTOSC1 FEXTOSC0 1111 1111 30 0000h CONFIG1L 30 0001h CONFIG1H -- -- FCMEN -- CSWEN -- -- CLKOUTEN 1111 1111 30 0002h CONFIG2L BOREN1 BOREN0 LPBOREN -- -- -- PWRTE MCLRE 1111 1111 -- DEBUG STVREN PPS1WAY ZCD BORV1 BORV0 1111 1111 30 0003h CONFIG2H XINST 30 0004h CONFIG3L -- 30 0005h CONFIG3H -- -- 30 0006h CONFIG4L WRT7 WRT6 WRT5 WRT4 WRT3 WRT2 WRT1 WRT0 1111 1111 30 0007h CONFIG4H -- -- LVP SCANE -- WRTD WRTB WRTC 1111 1111 30 0008h CONFIG5L WDTE<1:0> WDTCPS<4:0> WDTCCS<2:0> 1111 1111 WDTCWS<2:0> 1111 1111 Preliminary -- -- -- -- -- -- CPD CP 1111 1111 30 000Ah CONFIG6L EBTR7 EBTR6 EBTR5 EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 1111 1111 30 000Bh CONFIG6H -- -- -- -- -- -- EBTRB -- 1111 1111 PIC18(L)F27/47K40 DS40001844B-page 30 PIC18(L)F27/47K40 3.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection and data memory are controlled independently. Internal access to the program memory is unaffected by any code protection setting. 3.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all `0's. The CPU can continue to read program memory, regardless of the protection bit settings. Self-writing the program memory is dependent upon the write protection setting. See Section 3.4 "Write Protection" for more information. 3.3.2 DATA MEMORY PROTECTION The entire Data EEPROM Memory space is protected from external reads and writes by the CPD bit in the Configuration Words. When CPD = 0, external reads and writes of Data EEPROM Memory are inhibited and a read will return all `0's. The CPU can continue to read Data EEPROM Memory regardless of the protection bit settings. 3.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 3.5 User ID Eight words in the memory space (200000h-200000Fh) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 11.2 "User ID, Device ID and Configuration Word Access" for more information on accessing these memory locations. For more information on checksum calculation, see the "PIC18(L)F2X/4XK40 Memory Programming Specification" (DS40001772). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 31 PIC18(L)F27/47K40 3.6 Device ID and Revision ID The 16-bit device ID word is located at 3F FFFEh and the 16-bit revision ID is located at 3F FFFCh. These locations are read-only and cannot be erased or modified. Development tools, such as device programmers and debuggers, may be used to read the Device ID, Revision ID and Configuration Words. Refer to 11.0 "Nonvolatile Memory (NVM) Control" for more information on accessing these locations. 3.7 Register Definitions: Device and Revision REGISTER 3-12: DEVICE ID: DEVICE ID REGISTER R R R R R R R R DEV15 DEV14 DEV13 DEV12 DEV11 DEV10 DEV9 DEV8 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit bit 15-0 `1' = Bit is set 0' = Bit is cleared x = Bit is unknown DEV<15:0>: Device ID bits Device Device ID PIC18F27K40 6960h PIC18LF27K40 6A40 PIC18F47K40 6900h PIC18LF47K40 69E0h 2016 Microchip Technology Inc. Preliminary DS40001844B-page 32 PIC18(L)F27/47K40 REGISTER 3-13: REVISION ID: REVISION ID REGISTER R R R R 1 0 1 0 R R R R MJRREV<5:2> bit 15 bit 8 R R R R R MJRREV<1:0> R R R MNRREV<5:0> bit 7 bit 0 Legend: R = Readable bit `1' = Bit is set 0' = Bit is cleared x = Bit is unknown bit 15-12 Read as `1010' These bits are fixed with value `1010' for all devices in this family. bit 11-6 MJRREV<5:0>: Major Revision ID bits These bits are used to identify a major revision. A major revision is indicated by an all-layer revision (A0, B0, C0, etc.). Revision A = 6'b00_0000 bit 5-0 MNRREV<5:0>: Minor Revision ID bits These bits are used to identify a minor revision. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 33 PIC18(L)F27/47K40 4.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) The external oscillator module can be configured in one of the following clock modes, by setting the FEXTOSC<2:0> bits of Configuration Word 1: 4.1 Overview 1. The oscillator module has multiple clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic resonators. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: * Selectable system clock source between external or internal sources via software. * Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL) and switch automatically to the internal oscillator. * Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. 2. 3. 4. 5. 6. ECL - External Clock Low-Power mode (below 100 kHz) ECM - External Clock Medium Power mode (100 kHz to 8 MHz) ECH - External Clock High-Power mode (above 8 MHz) LP - 32 kHz Low-Power Crystal mode. XT - Medium Gain Crystal or Ceramic Resonator Oscillator mode (between 100 kHz and 8 MHz) HS - High Gain Crystal or Ceramic Resonator mode (above 4 MHz) The ECH, ECM, and ECL Clock modes rely on an external logic level signal as the device clock source. The LP, XT, and HS Clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The internal oscillator block produces low and high-frequency clock sources, designated LFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 4-1). Multiple device clock frequencies may be derived from these clock sources. The RSTOSC bits of Configuration Word 1 (Register 3-1) determine the type of oscillator that will be used when the device runs after Reset, including when it is first powered up. If an external clock source is selected, the FEXTOSC bits of Configuration Word 1 must be used in conjunction with the RSTOSC bits to select the External Clock mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 34 Rev. 10-000208D 5/10/2016 CLKIN/OSC1 External Oscillator (EXTOSC) CLKOUT/OSC2 CDIV<4:0> 4x PLL COSC<2:0> SOSCIN/SOSCI Secondary Oscillator (SOSC) SOSCO Preliminary LFINTOSC 1001 111 256 1000 010 128 0111 100 64 0110 32 0101 16 0100 8 0011 101 31 kHz Oscillator 110 Reserved 011 Reserved 001 0010 Sleep Reserved 000 2 0001 Idle 1 0000 MFINTOSC DS40001844B-page 35 31.25 kHz and 500 kHz Oscillator LFINTOSC is used to monitor system clock System Clock SYSCMD 4 FRQ<3:0> 1,2,4,8,12,16,32,48,64 MHz Oscillator Sleep FSCM To Peripherals To Peripherals To Peripherals To Peripherals Peripheral Clock PIC18(L)F27/47K40 HFINTOSC 512 Post Divider 2016 Microchip Technology Inc. SIMPLIFIED PIC(R) MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 4-1: PIC18(L)F27/47K40 4.2 Register Definitions: Oscillator Control REGISTER 4-1: U-0 OSCCON1: OSCILLATOR CONTROL REGISTER1 R/W-f/f R/W-f/f -- R/W-f/f R/W-q/q R/W-q/q NOSC<2:0> R/W-q/q R/W-q/q NDIV<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared f = determined by fuse setting q = Reset value is determined by hardware bit 7 Unimplemented: Read as `0' bit 6-4 NOSC<2:0>: New Oscillator Source Request bits(1,2,3) The setting requests a source oscillator and PLL combination per Table 4-2. POR value = RSTOSC (Register 3-1). bit 3-0 NDIV<3:0>: New Divider Selection Request bits(2,3) The setting determines the new postscaler division ratio per Table 4-2. Note 1: The default value (f/f) is determined by the RSTOSC Configuration bits. See Table 4-1below. 2: If NOSC is written with a reserved value (Table 4-2), the operation is ignored and neither NOSC nor NDIV is written. 3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value. TABLE 4-1: RSTOSC DEFAULT OSCILLATOR SETTINGS SFR Reset Values NOSC/COSC CDIV OSCFRQ Initial FOSC Frequency 111 111 1:1 EXTOSC per FEXTOSC 110 110 4:1 FOSC = 1 MHz (4 MHz/4) 101 101 1:1 100 100 1:1 010 1:1 011 010 000 LFINTOSC SOSC Reserved 001 Note 1: 4 MHz 4 MHz EXTOSC + 4xPLL (1) Reserved 110 1:1 64 MHz FOSC = 64 MHZ EXTOSC must meet the PLL specifications (Table 37-9). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 36 PIC18(L)F27/47K40 REGISTER 4-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 R-q/q -- R-q/q R-q/q R-q/q R-q/q COSC<2:0> R-q/q R-q/q CDIV<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Reset value is determined by hardware bit 7 Unimplemented: Read as `0' bit 6-4 COSC<2:0>: Current Oscillator Source Select bits (read-only)(1,2) Indicates the current source oscillator and PLL combination per Table 4-2. bit 3-0 CDIV<3:0>: Current Divider Select bits (read-only)(1,2) Indicates the current postscaler division ratio per Table 4-2. Note 1: The POR value is the value present when user code execution begins. 2: The Reset value (q/q) is the same as the NOSC/NDIV bits. TABLE 4-2: NOSC/COSC AND NDIV/CDIV BIT SETTINGS NOSC<2:0> COSC<2:0> Clock Source NDIV<3:0> CDIV<3:0> Clock Divider 111 EXTOSC(1) 1111-1010 Reserved 110 HFINTOSC(2) 1001 512 101 LFINTOSC 1000 256 100 SOSC 0111 128 011 Reserved 0110 64 0101 32 001 Reserved 0100 16 000 Reserved 0011 8 0010 4 0001 2 0000 1 010 Note 1: 2: 3: (3) EXTOSC + 4x PLL EXTOSC configured by the FEXTOSC bits of Configuration Word 1 (Register 3-1). HFINTOSC frequency is set with the HFFRQ bits of the OSCFRQ register (Register 4-5). EXTOSC must meet the PLL specifications (Table 37-9). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 37 PIC18(L)F27/47K40 REGISTER 4-3: OSCCON3: OSCILLATOR CONTROL REGISTER 3 R/W/HC-0/0 R/W-0/0 U-0 R-0/0 R-0/0 U-0 U-0 U-0 CSWHOLD SOSCPWR -- ORDY NOSCR -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 CSWHOLD: Clock Switch Hold bit 1 = Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready 0 = Clock switch may proceed when the oscillator selected by NOSC is ready; NOSCR becomes `1', the switch will occur bit 6 SOSCPWR: Secondary Oscillator Power Mode Select bit 1 = Secondary oscillator operating in High-Power mode 0 = Secondary oscillator operating in Low-Power mode bit 5 Unimplemented: Read as `0' bit 4 ORDY: Oscillator Ready bit (read-only) 1 = OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC 0 = A clock switch is in progress bit 3 NOSCR: New Oscillator is Ready bit (read-only)(1) 1 = A clock switch is in progress and the oscillator selected by NOSC indicates a "ready" condition 0 = A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready bit 2-0 Unimplemented: Read as `0' Note 1: If CSWHOLD = 0, the user may not see this bit set because, when the oscillator becomes ready there may be a delay of one instruction clock before this bit is set. The clock switch occurs in the next instruction cycle and this bit is cleared. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 38 PIC18(L)F27/47K40 REGISTER 4-4: OSCSTAT: OSCILLATOR STATUS REGISTER 1 R-q/q R-q/q R-q/q R-q/q R-q/q R-q/q U-0 R-q/q EXTOR HFOR MFOR LFOR SOR ADOR -- PLLR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Reset value is determined by hardware bit 7 EXTOR: EXTOSC (external) Oscillator Ready bit 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used bit 6 HFOR: HFINTOSC Oscillator Ready bit 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used bit 5 MFOR: MFINTOSC Oscillator Ready 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used bit 4 LFOR: LFINTOSC Oscillator Ready bit 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used bit 3 SOR: Secondary (Timer1) Oscillator Ready bit 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used bit 2 ADOR: ADC Oscillator Ready bit 1 = The oscillator is ready to be used 0 = The oscillator is not enabled, or is not yet ready to be used bit 1 Unimplemented: Read as `0' bit 0 PLLR: PLL is Ready bit 1 = The PLL is ready to be used 0 = The PLL is not enabled, the required input source is not ready, or the PLL is not locked. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 39 PIC18(L)F27/47K40 REGISTER 4-5: OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-q/q R/W-q/q R/W-q/q R/W-q/q HFFRQ<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Reset value is determined by hardware bit 7-4 Unimplemented: Read as `0' bit 3-0 HFFRQ<3:0>: HFINTOSC Frequency Selection bits HFFRQ<3:0> Nominal Freq (MHz) 1001 1010 1111 1110 Reserved 1101 1100 1011 1000(3) 64 0111 48 0110 32 0101(4) 16 0100 12 0011 8 (1,2) 0010 Note 1: 4 0001 2 0000 1 Refer to Table 4-1 for more information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 40 PIC18(L)F27/47K40 REGISTER 4-6: OSCTUNE: HFINTOSC TUNING REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 HFTUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 HFTUN<5:0>: HFINTOSC Frequency Tuning bits 01 1111 = Maximum frequency * * * 00 0000 = Center frequency. Oscillator module is running at the calibrated frequency (default value). * * * 10 0000 = Minimum frequency 2016 Microchip Technology Inc. Preliminary DS40001844B-page 41 PIC18(L)F27/47K40 REGISTER 4-7: OSCEN: OSCILLATOR MANUAL ENABLE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN -- -- Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EXTOEN: External Oscillator Manual Request Enable bit 1 = EXTOSC is explicitly enabled, operating as specified by FEXTOSC 0 = EXTOSC could be enabled by requesting peripheral bit 6 HFOEN: HFINTOSC Oscillator Manual Request Enable bit 1 = HFINTOSC is explicitly enabled, operating as specified by OSCFRQ (Register 4-5) 0 = HFINTOSC could be enabled by requesting peripheral bit 5 MFOEN: MFINTOSC (500 kHz/31.25 kHz) Oscillator Manual Request Enable bit (Derived from HFINTOSC) 1 = MFINTOSC is explicitly enabled 0 = MFINTOSC could be enabled by requesting peripheral bit 4 LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit 1 = LFINTOSC is explicitly enabled 0 = LFINTOSC could be enabled by requesting peripheral bit 3 SOSCEN: Secondary Oscillator Manual Request Enable bit 1 = Secondary Oscillator is explicitly enabled, operating as specified by SOSCPWR 0 = Secondary Oscillator could be enabled by requesting peripheral bit 2 ADOEN: ADC Oscillator Manual Request Enable bit 1 = ADC oscillator is explicitly enabled 0 = ADC oscillator could be enabled by requesting peripheral bit 1-0 Unimplemented: Read as `0' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 42 PIC18(L)F27/47K40 4.3 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes). Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate internal system clock sources. The High-Frequency Internal Oscillator (HFINTOSC) can produce 1, 2, 4, 8, 12, 16, 32, 48 and 64 MHz clock. The frequency can be controlled through the OSCFRQ register (Register 4-5). The Low-Frequency Internal Oscillator (LFINTOSC) generates a fixed 31 kHz frequency. A 4x PLL is provided that can be used in conjunction with the external clock. When used with the HFINTOSC the 4x PLL has input frequency limitations. See Section 4.3.1.4 "4x PLL" for more details. The system clock can be selected between external or internal clock sources via the NOSC bits in the OSCCON1 register. See Section 4.4 "Clock Switching" for additional information. The system clock can be made available on the OSC2/CLKOUT pin for any of the modes that do not use the OSC2 pin. The clock out functionality is governed by the CLKOUTEN bit in the CONFIG1H register (Register 3-2). If enabled, the clock out signal is always at a frequency of FOSC/4. 4.3.1 EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: * Program the RSTOSC<2:0> and FEXTOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. * Write the NOSC<2:0> and NDIV<3:0> bits in the OSCCON1 register to switch the system clock source. See Section information. 4.3.1.1 4.4 "Clock Switching" for more EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 4-2 shows the pin connections for EC mode. 2016 Microchip Technology Inc. EC mode has three power modes to select from through Configuration Words: * ECH - High power, above 8 MHz * ECM - Medium power, 100 kHz-8 MHz * ECL - Low power, below 100 MHz The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC(R) MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 4-2: OSC1/CLKIN Clock from Ext. System PIC(R) MCU FOSC/4 or I/O(1) Note 1: 4.3.1.2 EXTERNAL CLOCK (EC) MODE OPERATION OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Words (CONFIG1H). LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification (above 100 kHz - 8 MHz). HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting (above 8 MHz). Figure 4-3 and Figure 4-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Preliminary DS40001844B-page 43 PIC18(L)F27/47K40 FIGURE 4-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) To Internal Logic Sleep 4.3.1.4 OSC1/CLKIN Quartz Crystal RF(2) OSC2/CLKOUT RS(1) C2 Note 1: A series resistor (RS) may be required for quartz crystals with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. FIGURE 4-4: Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR), or a wake-up from Sleep. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. PIC(R) MCU C1 4.3.1.3 CERAMIC RESONATOR OPERATION (XT OR HS MODE) 4x PLL The oscillator module contains a 4x PLL that can be used with the external clock sources to provide a system clock source. The input frequency for the PLL must fall within specifications. See the PLL Clock Timing Specifications in Table 37-9. The PLL can be enabled for use by one of two methods: 1. 2. Program the RSTOSC bits in the Configuration Word 1 to 010 (enable EXTOSC with 4x PLL). Write the NOSC bits in the OSCCON1 register to 010 (enable EXTOSC with 4x PLL). PIC(R) MCU OSC1/CLKIN C1 To Internal Logic RP(3) C2 Ceramic RS(1) Resonator Note 1: RF(2) Sleep OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 44 PIC18(L)F27/47K40 4.3.1.5 4.3.2 Secondary Oscillator The secondary oscillator is a separate oscillator block that can be used as an alternate system clock source. The secondary oscillator is optimized for 32.768 kHz, and can be used with an external crystal oscillator connected to the SOSCI and SOSCO device pins, or an external clock source connected to the SOSCIN pin. The secondary oscillator can be selected during run-time using clock switching. Refer to Section 4.4 "Clock Switching" for more information. FIGURE 4-5: QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) * Program the RSTOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. * Write the NOSC<2:0> bits in the OSCCON1 register to switch the system clock source to the internal oscillator during run-time. See Section 4.4 "Clock Switching" for more information. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. The internal oscillator block has two independent oscillators that can produce two internal system clock sources. SOSCI To Internal Logic 1. 32.768 kHz Quartz Crystal C2 The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. PIC(R) MCU C1 INTERNAL CLOCK SOURCES SOSCO 2. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. The HFINTOSC (High-Frequency Internal Oscillator) is factory-calibrated and operates from 1 to 64 MHz. The frequency of HFINTOSC can be selected through the OSCFRQ Frequency Selection register, and fine-tuning can be done via the OSCTUNE register. The LFINTOSC (Low-Frequency Internal Oscillator) is factory-calibrated and operates at 31 kHz. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: * AN826, "Crystal Oscillator Basics and Crystal Selection for PIC(R) and PIC(R) Devices" (DS00826) * AN849, "Basic PIC(R) Oscillator Design" (DS00849) * AN943, "Practical PIC(R) Oscillator Analysis and Design" (DS00943) * AN949, "Making Your Oscillator Work" (DS00949) * TB097, "Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS" (DS91097) * AN1288, "Design Practices for Low-Power External Oscillators" (DS01288) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 45 PIC18(L)F27/47K40 4.3.2.1 HFINTOSC 4.3.2.3 The High-Frequency Internal Oscillator (HFINTOSC) is a precision digitally-controlled internal clock source that produces a stable clock up to 64 MHz. The HFINTOSC can be enabled through one of the following methods: * Programming the RSTOSC<2:0> bits in Configuration Word 1 to `110' (FOSC = 1 MHz) or `000' (FOSC = 64 MHz) to set the oscillator upon device Power-up or Reset. * Write to the NOSC<2:0> bits of the OSCCON1 register during run-time. See Section 4.4 "Clock Switching" for more information. The HFINTOSC frequency can be selected by setting the HFFRQ<3:0> bits of the OSCFRQ register. The NDIV<3:0> bits of the OSCCON1 register allow for division of the HFINTOSC output from a range between 1:1 and 1:512. 4.3.2.2 MFINTOSC The module provides two (500 kHz and 31.25 kHz) constant clock outputs. These clocks are digital divisors of the HFINTOSC clock. Dynamic divider logic is used to provide constant MFINTOSC clock rates for all settings of HFINTOSC. The MFINTOSC cannot be used to drive the system but it is used to clock certain modules such as the Timers and WWDT. Internal Oscillator Frequency Adjustment The internal oscillator is factory-calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 4-3). The default value of the OSCTUNE register is 00h. The value is a 6-bit two's complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), WWDT, Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 4.3.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is a factory-calibrated 31 kHz internal clock source. The LFINTOSC is the frequency for the Power-up Timer (PWRT), Windowed Watchdog Timer (WWDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled through one of the following methods: * Programming the RSTOSC<2:0> bits of Configuration Word 1 to enable LFINTOSC. * Write to the NOSC<2:0> bits of the OSCCON1 register during run-time. See Section 4.4, Clock Switching for more information. 4.3.2.5 ADCRC The ADCRC is an oscillator dedicated to the ADC2 module. The ADCRC oscillator can be manually enabled using the ADOEN bit of the OSCEN register. The ADCRC runs at a fixed frequency of 600 kHz. ADCRC is automatically enabled if it is selected as the clock source for the ADC2 module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 46 PIC18(L)F27/47K40 4.3.2.6 Oscillator Status and Manual Enable The Ready status of each oscillator (including the ADCRC oscillator) is displayed in OSCSTAT (Register 4-4). The oscillators (but not the PLL) may be explicitly enabled through OSCEN (Register 4-7). 4.3.2.7 HFOR and MFOR Bits The HFOR and MFOR bits indicate that the HFINTOSC and MFINTOSC is ready. These clocks are always valid for use at all times, but only accurate after they are ready. When a new value is loaded into the OSCFRQ register, the HFOR and MFOR bits will clear, and set again when the oscillator is ready. During pending OSCFRQ changes the MFINTOSC clock will stall at a high or a low state, until the HFINTOSC resumes operation. 4.4 Clock Switching The system clock source can be switched between external and internal clock sources via software using the New Oscillator Source (NOSC) bits of the OSCCON1 register. The following clock sources can be selected using the following: * External oscillator * Internal Oscillator Block (INTOSC) Note: 4.4.1 The Clock Switch Enable bit in Configuration Word 1 can be used to enable or disable the clock switching capability. When cleared, the NOSC and NDIV bits cannot be changed by user software. When set, writing to NOSC and NDIV is allowed and would switch the clock frequency. NEW OSCILLATOR SOURCE (NOSC) AND NEW DIVIDER SELECTION REQUEST (NDIV) BITS When the new oscillator is ready, the New Oscillator Ready (NOSCR) bit of OSCCON3 is set and also the Clock Switch Interrupt Flag (CSWIF) bit of PIR1 sets. If Clock Switch Interrupts are enabled (CSWIE = 1), an interrupt will be generated at that time. The Oscillator Ready (ORDY) bit of OSCCON3 can also be polled to determine when the oscillator is ready in lieu of an interrupt. Note: The CSWIF interrupt will not wake the system from Sleep. If the Clock Switch Hold (CSWHOLD) bit of OSCCON3 is clear, the oscillator switch will occur when the New Oscillator is Ready bit (NOSCR) is set, and the interrupt (if enabled) will be serviced at the new oscillator setting. If CSWHOLD is set, the oscillator switch is suspended, while execution continues using the current (old) clock source. When the NOSCR bit is set, software should: * Set CSWHOLD = 0 so the switch can complete, or * Copy COSC into NOSC to abandon the switch. If DOZE is in effect, the switch occurs on the next clock cycle, whether or not the CPU is operating during that cycle. Changing the clock post-divider without changing the clock source (i.e., changing FOSC from 1 MHz to 2 MHz) is handled in the same manner as a clock source change, as described previously. The clock source will already be active, so the switch is relatively quick. CSWHOLD must be clear (CSWHOLD = 0) for the switch to complete. The current COSC and CDIV are indicated in the OSCCON2 register up to the moment when the switch actually occurs, at which time OSCCON2 is updated and ORDY is set. NOSCR is cleared by hardware to indicate that the switch is complete. 4.4.2 PLL INPUT SWITCH The New Oscillator Source (NOSC) and New Divider Selection Request (NDIV) bits of the OSCCON1 register select the system clock source and frequency that are used for the CPU and peripherals. Switching between the PLL and any non-PLL source is managed as described above. The input to the PLL is established when NOSC selects the PLL, and maintained by the COSC setting. When new values of NOSC and NDIV are written to OSCCON1, the current oscillator selection will continue to operate while waiting for the new clock source to indicate that it is stable and ready. In some cases, the newly requested source may already be in use, and is ready immediately. In the case of a divider-only change, the new and old sources are the same, so the old source will be ready immediately. The device may enter Sleep while waiting for the switch as described in Section 4.4.3 "Clock Switch and Sleep". When NOSC and COSC select the PLL with different input sources, the system continues to run using the COSC setting, and the new source is enabled per NOSC. When the new oscillator is ready (and CSWHOLD = 0), system operation is suspended while the PLL input is switched and the PLL acquires lock. This provides a truly glitch-free clock switch operation. 2016 Microchip Technology Inc. Note: Preliminary If the PLL fails to lock, the FSCM will trigger. DS40001844B-page 47 PIC18(L)F27/47K40 4.4.3 CLOCK SWITCH AND SLEEP If OSCCON1 is written with a new value and the device is put to Sleep before the switch completes, the switch will not take place and the device will enter Sleep mode. When the device wakes from Sleep and the CSWHOLD bit is clear, the device will wake with the `new' clock active, and the clock switch interrupt flag bit (CSWIF) will be set. When the device wakes from Sleep and the CSWHOLD bit is set, the device will wake with the `old' clock active and the new clock will be requested again. FIGURE 4-6: CLOCK SWITCH (CSWHOLD = 0) OSCCON1 WRITTEN OSC #2 OSC #1 ORDY NOTE 2 NOSCR NOTE 1 CSWIF CSWHOLD USER CLEAR Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed. 2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch. FIGURE 4-7: CLOCK SWITCH (CSWHOLD = 1) OSCCON1 WRITTEN OSC #1 OSC #2 ORDY NOSCR CSWIF NOTE 1 USER CLEAR CSWHOLD Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 48 PIC18(L)F27/47K40 FIGURE 4-8: CLOCK SWITCH ABANDONED OSCCON1 WRITTEN OSCCON1 WRITTEN OSC #1 ORDY NOTE 2 NOSCR CSWIF NOTE 1 CSWHOLD Note 1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared. 2: ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 49 PIC18(L)F27/47K40 4.5 Fail-Safe Clock Monitor 4.5.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, ECL/M/H and Secondary Oscillator). FIGURE 4-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock LFINTOSC Oscillator / 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 4.5.1 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the NOSC and NDIV bits of the OSCCON1 register. When switching to the external oscillator or PLL, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON1. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSCFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSCFIF flag will again become set by hardware. Clock Failure Detected FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 4-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 4.5.2 FAIL-SAFE OPERATION When the external clock fails, the FSCM overwrites the COSC bits to select HFINTOSC (3'b110). The frequency of HFINTOSC would be determined by the previous state of the HFFRQ bits and the NDIV/CDIV bits. The bit flag OSCFIF of the PIR1 register is set. Setting this flag will generate an interrupt if the OSCFIE bit of the PIE1 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation, by writing to the NOSC and NDIV bits of the OSCCON1 register. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 50 PIC18(L)F27/47K40 4.5.4 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. FIGURE 4-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 51 PIC18(L)F27/47K40 TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 OSCCON1 -- NOSC<2:0> NDIV<3:0> 36 OSCCON2 -- COSC<2:0> CDIV<3:0> 37 OSCCON3 Bit 6 Bit 5 CSWHOLD SOSCPWR Bit 4 -- Bit 3 Bit 2 ORDY NOSCR -- LFOR SOR ADOR Bit 1 Bit 0 Register on Page Name -- -- -- PLLR 38 OSCSTAT EXTOR HFOR OSCTUNE -- -- OSCFRQ -- -- -- -- OSCEN EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN -- -- 42 PIE1 OSCFIE CSWIE -- -- -- -- ADTIE ADIE 179 PIR1 OSCFIF CSWIF -- -- -- -- ADTIF ADIF 171 IPR1 OSCFIP CSWIP -- -- -- -- ADTIP ADIP 187 MFOR HFTUN<5:0> 39 41 HFFRQ<3:0> 40 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. TABLE 4-4: Name CONFIG1 Legend: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 -- -- FCMEN -- CSWEN -- -- CLKOUTEN 7:0 -- RSTOSC<2:0> -- FEXTOSC<2:0> Register on Page 23 -- = unimplemented location, read as `0'. Shaded cells are not used by clock sources. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 52 PIC18(L)F27/47K40 5.0 REFERENCE CLOCK OUTPUT MODULE The reference clock output module provides the ability to send a clock signal to the clock reference output pin (CLKR). The reference clock output can also be used as a signal for other peripherals, such as the Data Signal Modulator (DSM), Memory Scanner and Timer module. The reference clock output module has the following features: * Selectable clock source using the CLKRCLK register * Programmable clock divider * Selectable duty cycle FIGURE 5-1: CLOCK REFERENCE BLOCK DIAGRAM Rev. 10-000261B 5/11/2016 Reference Clock Divider CLKREN CLKRDIV<2:0> Counter Reset See CLKRCLK Register CLKRCLK<3:0> 111 64 110 32 101 16 100 8 011 4 010 2 001 CLKRDC<1:0> CLKR Duty Cycle PPS To Peripherals 000 CLKREN 2016 Microchip Technology Inc. 128 Preliminary DS40001844B-page 53 PIC18(L)F27/47K40 FIGURE 5-2: CLOCK REFERENCE TIMING P1 Rev. 10-000264B 5/25/2016 P2 CLKRCLK CLKREN CLKR Output CLKRDIV<2:0> = 001 CLKRDC<1:0> = 10 CLKR Output CLKRDIV<2:0> = 001 CLKRDC<1:0> = 01 Duty Cycle (50%) CLKRCLK/2 Duty Cycle (25%) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 54 PIC18(L)F27/47K40 5.1 Clock Source 5.3 The input to the reference clock output can be selected using the CLKRCLK register. 5.1.1 CLOCK SYNCHRONIZATION Once the reference clock enable (EN) is set, the module is ensured to be glitch-free at start-up. When the reference clock output is disabled, the output signal will be disabled immediately. Clock dividers and clock duty cycles can be changed while the module is enabled, but glitches may occur on the output. To avoid possible glitches, clock dividers and clock duty cycles should be changed only when the CLKREN is clear. 5.2 The module takes the clock input and divides it based on the value of the DIV<2:0> bits of the CLKRCON register (Register 5-1). The following configurations can be made based on the DIV<2:0> bits: * * * * * * * * The DC<1:0> bits of the CLKRCON register can be used to modify the duty cycle of the output clock. A duty cycle of 25%, 50%, or 75% can be selected for all clock rates, with the exception of the undivided base FOSC value. The duty cycle can be changed while the module is enabled; however, in order to prevent glitches on the output, the DC<1:0> bits should only be changed when the module is disabled (EN = 0). Note: 5.4 Programmable Clock Divider Base FOSC value FOSC divided by 2 FOSC divided by 4 FOSC divided by 8 FOSC divided by 16 FOSC divided by 32 FOSC divided by 64 FOSC divided by 128 Selectable Duty Cycle The DC1 bit is reset to `1'. This makes the default duty cycle 50% and not 0%. Operation in Sleep Mode The reference clock output module clock is based on the system clock. When the device goes to Sleep, the module outputs will remain in their current state. This will have a direct effect on peripherals using the reference clock output as an input signal. No change should occur in the module from entering or exiting from Sleep. The clock divider values can be changed while the module is enabled; however, in order to prevent glitches on the output, the DIV<2:0> bits should only be changed when the module is disabled (EN = 0). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 55 PIC18(L)F27/47K40 5.5 Register Definitions: Reference Clock Long bit name prefixes for the Reference Clock peripherals are shown in Table 5-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 5-1: Peripheral Bit Name Prefix CLKR CLKR REGISTER 5-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER R/W-0/0 U-0 U-0 EN -- -- R/W-1/1 R/W-0/0 DC<1:0> R/W-0/0 R/W-0/0 R/W-0/0 DIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: Reference Clock Module Enable bit 1 = Reference clock module enabled 0 = Reference clock module is disabled bit 6-5 Unimplemented: Read as `0' bit 4-3 DC<1:0>: Reference Clock Duty Cycle bits(1) 11 = Clock outputs duty cycle of 75% 10 = Clock outputs duty cycle of 50% 01 = Clock outputs duty cycle of 25% 00 = Clock outputs duty cycle of 0% bit 2-0 DIV<2:0>: Reference Clock Divider bits 111 = Base clock value divided by 128 110 = Base clock value divided by 64 101 = Base clock value divided by 32 100 = Base clock value divided by 16 011 = Base clock value divided by 8 010 = Base clock value divided by 4 001 = Base clock value divided by 2 000 = Base clock value Note 1: Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 56 PIC18(L)F27/47K40 REGISTER 5-2: CLKRCLK: CLOCK REFERENCE CLOCK SELECTION MUX U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 CLK<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 CLK<2:0>: CLKR Clock Selection bits 111 = Unimplemented 110 = Unimplemented 101 = Unimplemented 100 = SOSC 011 = MFINTOSC (500 kHz) 010 = LFINTOSC (31 kHz) 001 = HFINTOSC 000 = FOSC TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT Name Bit 7 Bit 6 Bit 5 CLKRCON EN -- -- CLKRCLK PMD0 RxyPPS Legend: Bit 4 Bit 3 Bit 2 DC<1:0> Bit 1 Bit 0 56 DIV<2:0> -- -- -- -- -- SYSCMD FVRMD HLVDMD CRCMD SCANMD -- -- -- CLK<2:0> NVMMD CLKRMD RxyPPS<4:0> Register on Page 57 IOCMD 67 217 -- = unimplemented, read as `0'. Shaded cells are not used by the CLKR module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 57 PIC18(L)F27/47K40 6.0 POWER-SAVING OPERATION MODES When the Doze Enable (DOZEN) bit is set (DOZEN = 1), the CPU executes only one instruction cycle out of every N cycles as defined by the DOZE<2:0> bits of the CPUDOZE register. For example, if DOZE<2:0> = 001, the instruction cycle ratio is 1:4. The CPU and memory execute for one instruction cycle and then lay idle for three instruction cycles. During the unused cycles, the peripherals continue to operate at the system clock speed. The purpose of the Power-Down modes is to reduce power consumption. There are three Power-Down modes: * Doze mode * Sleep mode * Idle mode 6.1 6.1.1 Doze Mode The Doze operation is illustrated in Figure 6-1. For this example: Doze mode allows for power saving by reducing CPU operation and program memory (PFM) access, without affecting peripheral operation. Doze mode differs from Sleep mode because the bandgap and system oscillators continue to operate, while only the CPU and PFM are affected. The reduced execution saves power by eliminating unnecessary operations within the CPU and memory. FIGURE 6-1: DOZE OPERATION * Doze enable (DOZEN) bit set (DOZEN = 1) * DOZE<2:0> = 001 (1:4) ratio * Recover-on-Interrupt (ROI) bit set (ROI = 1) As with normal operation, the PFM fetches for the next instruction cycle. The Q-clocks to the peripherals continue throughout. DOZE MODE OPERATION EXAMPLE (DOZE<2:0> = 001, 1:4) System Clock 1 1 2 /Z WZ 1 2 3 1 2 3 4 2 3 4 1 2 3 4 1 2 3 4 1 1 2 3 4 2 3 4 1 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2 3 4 3 4 1 2 3 4 1 2 3 4 PFM Op's Fetch Fetch Push 0004h Fetch Fetch CPU Op's Exec Exec Exec(1,2) NOP Exec Exec 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 CPU Clock Exec Interrupt Here (ROI = 1) Note 1: 2: Multi-cycle instructions are executed to completion before fetching 0004h. If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 58 PIC18(L)F27/47K40 6.1.2 6.2 INTERRUPTS DURING DOZE If an interrupt occurs and the Recover-On-Interrupt bit is clear (ROI = 0) at the time of the interrupt, the Interrupt Service Routine (ISR) continues to execute at the rate selected by DOZE<2:0>. Interrupt latency is extended by the DOZE<2:0> ratio. If an interrupt occurs and the ROI bit is set (ROI = 1) at the time of the interrupt, the DOZEN bit is cleared and the CPU executes at full speed. The prefetched instruction is executed and then the interrupt vector sequence is executed. In Figure 6-1, the interrupt occurs during the 2nd instruction cycle of the Doze period, and immediately brings the CPU out of Doze. If the Doze-On-Exit (DOE) bit is set (DOE = 1) when the RETFIE operation is executed, DOZEN is set, and the CPU executes at the reduced rate based on the DOZE<2:0> ratio. EXAMPLE 6-1: DOZE SOFTWARE EXAMPLE //Mainline operation bool somethingToDo = FALSE: void main() { initializeSystem(); // DOZE = 64:1 (for example) // ROI = 1; GIE = 1; // enable interrupts while (1) { // If ADC completed, process data if (somethingToDo) { doSomething(); DOZEN = 1; // resume low-power } } } // Data interrupt handler void interrupt() { // DOZEN = 0 because ROI = 1 if (ADIF) { somethingToDo = TRUE; DOE = 0; // make main() go fast ADIF = 0; } // else check other interrupts... if (TMR0IF) { timerTick++; DOE = 1; // make main() go slow TMR0IF = 0; } } 2016 Microchip Technology Inc. Sleep Mode Sleep mode is entered by executing the SLEEP instruction, while the Idle Enable (IDLEN) bit of the CPUDOZE register is clear (IDLEN = 0). Upon entering Sleep mode, the following conditions exist: 1. WDT will be cleared but keeps running if enabled for operation during Sleep The PD bit of the STATUS register is cleared (Register 10-2) The TO bit of the STATUS register is set (Register 10-2) The CPU clock is disabled LFINTOSC, SOSC, HFINTOSC and ADCRC are unaffected and peripherals using them may continue operation in Sleep. I/O ports maintain the status they had before Sleep was executed (driving high, low, or high-impedance) Resets other than WDT are not affected by Sleep mode 2. 3. 4. 5. 6. 7. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: - I/O pins should not be floating - External circuitry sinking current from I/O pins - Internal circuitry sourcing current from I/O pins - Current draw from pins with internal weak pull-ups - Modules using any oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 30.0 "5-Bit Digital-to-Analog Converter (DAC) Module" and Section 28.0 "Fixed Voltage Reference (FVR)" for more information on these modules. Preliminary DS40001844B-page 59 PIC18(L)F27/47K40 6.2.1 WAKE-UP FROM SLEEP 6.2.2 The device can wake-up from Sleep through one of the following events: 1. 2. 3. 4. 5. 6. External Reset input on MCLR pin, if enabled BOR Reset, if enabled Low-Power Brown-Out Reset (LPBOR), if enabled POR Reset Windowed Watchdog Timer, if enabled All interrupt sources except clock switch interrupt can wake-up the part. The first five events will cause a device Reset. The last one event is considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 8.13 "Determining the Cause of a Reset". When the SLEEP instruction is being executed, the next instruction (PC + 2) is prefetched. For the device to wake-up through an interrupt event, the corresponding Interrupt Enable bit must be enabled, as well as the Peripheral Interrupt Enable bit (PEIE = 1), for every interrupt not in PIR0. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source, with the exception of the clock switch interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared * If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up. Upon a wake from a Sleep event, the core will wait for a combination of three conditions before beginning execution. The conditions are: * PFM Ready * COSC-Selected Oscillator Ready * BOR Ready (unless BOR is disabled) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 60 PIC18(L)F27/47K40 FIGURE 6-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt Latency (4) Interrupt flag GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 6.2.3 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. LOW-POWER SLEEP MODE 6.2.3.1 The PIC18F2x/4xK40 device family contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC18F2x/4xK40 devices allows the user to optimize the operating current in Sleep, depending on the application requirements. Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. 2016 Microchip Technology Inc. Sleep Current vs. Wake-up Time In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking-up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. Preliminary DS40001844B-page 61 PIC18(L)F27/47K40 6.2.3.2 Peripheral Usage in Sleep 6.2.4.1 Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The Low-Power Sleep mode is intended for use with these peripherals: * * * * Brown-out Reset (BOR) Windowed Watchdog Timer (WWDT) External interrupt pin/Interrupt-On-Change pins Peripherals that run off external secondary clock source Note: 6.2.4 IDLE mode ends when an interrupt occurs (even if GIE = 0), but IDLEN is not changed. The device can re-enter IDLE by executing the SLEEP instruction. If Recover-On-Interrupt is enabled (ROI = 1), the interrupt that brings the device out of Idle also restores full-speed CPU execution when doze is also enabled. 6.2.4.2 It is the responsibility of the end user to determine what is acceptable for their application when setting the VREGPM settings in order to ensure operation in Sleep. The PIC18LF2x/4xK40 devices do not have a configurable Low-Power Sleep mode. PIC18LF2x/4xK40 devices are unregulated and are always in the lowest power state when in Sleep, with no wake-up time penalty. These devices have a lower maximum VDD and I/O voltage than the PIC18F2x/4xK40. See Section 37.0 "Electrical Specifications" for more information. IDLE MODE Idle and Interrupts Idle and WWDT When in Idle, the WWDT Reset is blocked and will instead wake the device. The WWDT wake-up is not an interrupt, therefore ROI does not apply. Note: 6.3 The WDT can bring the device out of Idle, in the same way it brings the device out of Sleep. The DOZEN bit is not affected. Peripheral Operation in Power Saving Modes All selected clock sources and the peripherals running off them are active in both IDLE and DOZE mode. Only in Sleep mode, both the FOSC and FOSC/4 clocks are unavailable. All the other clock sources are active, if enabled manually or through peripheral clock selection before the part enters Sleep. When IDLEN is set (IDLEN = 1), the SLEEP instruction will put the device into Idle mode. In Idle mode, the CPU and memory operations are halted, but the peripheral clocks continue to run. This mode is similar to Doze mode, except that in IDLE both the CPU and PFM are shut off. Note: If CLKOUTEN is enabled (CLKOUTEN = 0, Configuration Word 1H), the output will continue operating while in Idle. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 62 PIC18(L)F27/47K40 6.4 Register Definitions: Voltage Regulator Control REGISTER 6-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 -- -- -- -- -- -- VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as `1'. Maintain this bit set. Note 1: 2: PIC18F2x/4xK40 only. See Section 37.0 "Electrical Specifications". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 63 PIC18(L)F27/47K40 REGISTER 6-2: CPUDOZE: DOZE AND IDLE REGISTER R/W-0/u R/W/HC/HS-0/0 R/W-0/0 R/W-0/0 U-0 IDLEN DOZEN ROI DOE -- R/W-0/0 R/W-0/0 R/W-0/0 DOZE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 IDLEN: Idle Enable bit 1 = A SLEEP instruction inhibits the CPU clock, but not the peripheral clock(s) 0 = A SLEEP instruction places the device into full Sleep mode bit 6 DOZEN: Doze Enable bit(1,2) 1 = The CPU executes instruction cycles according to DOZE setting 0 = The CPU executes all instruction cycles (fastest, highest power operation) bit 5 ROI: Recover-On-Interrupt bit 1 = Entering the Interrupt Service Routine (ISR) makes DOZEN = 0 bit, bringing the CPU to full-speed operation 0 = Interrupt entry does not change DOZEN bit 4 DOE: Doze-On-Exit bit 1 = Executing RETFIE makes DOZEN = 1, bringing the CPU to reduced speed operation 0 = RETFIE does not change DOZEN bit 3 Unimplemented: Read as `0' bit 2-0 DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles 111 =1:256 110 =1:128 101 =1:64 100 =1:32 011 =1:16 010 =1:8 001 =1:4 000 =1:2 Note 1: 2: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit. Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 64 PIC18(L)F27/47K40 TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE -- -- -- -- -- INTEDG 169 PIE0 -- -- TMR0IE IOCIE -- INT2IE INT1IE INT0IE 178 PIE1 OSCFIE CSWIE -- -- -- -- ADTIE ADIE 179 PIE2 HLVDIE ZCDIE -- -- -- -- C2IE C1IE 180 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIE4 -- -- TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE 182 PIE5 -- -- -- -- -- TMR5GIE TMR3GIE TMR1GIE 183 PIE6 -- -- -- -- -- -- CCP2IE CCP1IE 184 PIE7 SCANIE CRCIE NVMIE -- -- -- -- CWG1IE 185 PIR0 -- -- TMR0IF IOCIF -- INT2IF INT1IF INT0IF 170 PIR1 OSCFIF CSWIF -- -- -- -- ADTIF ADIF 171 PIR2 HLVDIF ZCDIF(1) -- -- -- -- C2IF C1IF 172 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 PIR4 -- -- TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 173 IOCAP -- -- IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 210 IOCAN -- -- IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 210 IOCAF -- -- IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 210 (1) IOCCP -- -- IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 210 IOCCN(1) -- -- IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 210 IOCCF(1) -- -- IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 210 STATUS -- -- -- TO PD Z DC C 117 -- VREGPM Reserved 63 SEN 84 VREGCON -- -- -- -- -- CPUDOZE IDLEN DOZEN ROI DOE -- WDTCON0 -- -- WDTCON1 Legend: Note 1: -- DOZE<2:0> WDTPS<4:0> WDTPS<2:0> -- WINDOW<2:0> 64 85 -- = unimplemented location, read as `0'. Shaded cells are not used in Power-Down mode. PIC18(L)F4xK40 only. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 65 PIC18(L)F27/47K40 7.0 PERIPHERAL MODULE DISABLE (PMD) 7.3 Sleep, Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume some amount of power. There may be cases where the application needs what these modes do not provide: the ability to allocate limited power resources to the CPU while eliminating power consumption from the peripherals. The PIC18(L)F2x/4xK40 family addresses this requirement by allowing peripheral modules to be selectively enabled or disabled, placing them into the lowest possible power mode. Effects of a Reset Following any Reset, each control bit is set to `0', enabling all modules. 7.4 System Clock Disable Setting SYSCMD (PMD0, Register 7-1) disables the system clock (FOSC) distribution network to the peripherals. Not all peripherals make use of SYSCLK, so not all peripherals are affected. Refer to the specific peripheral description to see if it will be affected by this bit. For legacy reasons, all modules are ON by default following any Reset. 7.1 Disabling a Module Disabling a module has the following effects: * All clock and control inputs to the module are suspended; there are no logic transitions, and the module will not function. * The module is held in Reset. * Any SFR becomes "unimplemented" - Writing is disabled - Reading returns 00h * I/O functionality is prioritized as per Section 15.1, I/O Priorities * All associated Input Selection registers are also disabled 7.2 Enabling a Module When the PMD register bit is cleared, the module is re-enabled and will be in its Reset state (Power-on Reset). SFR data will reflect the POR Reset values. Depending on the module, it may take up to one full instruction cycle for the module to become active. There should be no interaction with the module (e.g., writing to registers) for at least one instruction after it has been re-enabled. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 66 PIC18(L)F27/47K40 7.5 Register Definitions: Peripheral Module Disable REGISTER 7-1: PMD0: PMD CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD 7 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SYSCMD: Disable Peripheral System Clock Network bit(1) See description in Section 7.4 "System Clock Disable". 1 = System clock network disabled (FOSC) 0 = System clock network enabled bit 6 FVRMD: Disable Fixed Voltage Reference bit 1 = FVR module disabled 0 = FVR module enabled bit 5 HLVDMD: Disable Low-Voltage Detect bit 1 = HLVD module disabled 0 = HLVD module enabled bit 4 CRCMD: Disable CRC Engine bit 1 = CRC module disabled 0 = CRC module enabled bit 3 SCANMD: Disable NVM Memory Scanner bit(2) 1 = NVM Memory Scan module disabled 0 = NVM Memory Scan module enabled bit 2 NVMMD: NVM Module Disable bit(3) 1 = All Memory reading and writing is disabled; NVMCON registers cannot be written 0 = NVM module enabled bit 1 CLKRMD: Disable Clock Reference bit 1 = CLKR module disabled 0 = CLKR module enabled bit 0 IOCMD: Disable Interrupt-on-Change bit, All Ports 1 = IOC module(s) disabled 0 = IOC module(s) enabled Note 1: 2: 3: Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked by FOSC/4 are not affected. Subject to SCANE bit in CONFIG4H. When enabling NVM, a delay of up to 1 s may be required before accessing data. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 67 PIC18(L)F27/47K40 REGISTER 7-2: PMD1: PMD CONTROL REGISTER 1 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as `0' bit 6 TMR6MD: Disable Timer TMR6 bit 1 = TMR6 module disabled 0 = TMR6 module enabled bit 5 TMR5MD: Disable Timer TMR5 bit 1 = TMR5 module disabled 0 = TMR5 module enabled bit 4 TMR4MD: Disable Timer TMR4 bit 1 = TMR4 module disabled 0 = TMR4 module enabled bit 3 TMR3MD: Disable Timer TMR3 bit 1 = TMR3 module disabled 0 = TMR3 module enabled bit 2 TMR2MD: Disable Timer TMR2 bit 1 = TMR2 module disabled 0 = TMR2 module enabled bit 1 TMR1MD: Disable Timer TMR1 bit 1 = TMR1 module disabled 0 = TMR1 module enabled bit 0 TMR0MD: Disable Timer TMR0 bit 1 = TMR0 module disabled 0 = TMR0 module enabled 2016 Microchip Technology Inc. Preliminary DS40001844B-page 68 PIC18(L)F27/47K40 REGISTER 7-3: PMD2: PMD CONTROL REGISTER 2 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- DACMD ADCMD -- -- CMP2MD CMP1MD ZCDMD(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as `0' bit 6 DACMD: Disable DAC bit 1 = DAC module disabled 0 = DAC module enabled bit 5 ADCMD: Disable ADC bit 1 = ADC module disabled 0 = ADC module enabled bit 4-3 Unimplemented: Read as `0' bit 2 CMP2MD: Disable Comparator CMP2 bit 1 = CMP2 module disabled 0 = CMP2 module enabled bit 1 CMP1MD: Disable Comparator CMP1 bit 1 = CMP1 module disabled 0 = CMP1 module enabled bit 0 ZCDMD: Disable Zero-Cross Detect module bit(1) 1 = ZCD module disabled 0 = ZCD module enabled Note 1: Subject to ZCD bit in CONFIG2H. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 69 PIC18(L)F27/47K40 REGISTER 7-4: PMD3: PMD CONTROL REGISTER 3 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- PWM4MD PWM3MD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as `0' bit 3 PWM4MD: Disable Pulse-Width Modulator PWM4 bit 1 = PWM4 module disabled 0 = PWM4 module enabled bit 2 PWM3MD: Disable Pulse-Width Modulator PWM3 bit 1 = PWM3 module disabled 0 = PWM3 module enabled bit 1 CCP2MD: Disable Pulse-Width Modulator CCP2 bit 1 = CCP2 module disabled 0 = CCP2 module enabled bit 0 CCP1MD: Disable Pulse-Width Modulator CCP1 bit 1 = CCP1 module disabled 0 = CCP1 module enabled 2016 Microchip Technology Inc. Preliminary DS40001844B-page 70 PIC18(L)F27/47K40 REGISTER 7-5: PMD4: PMD CONTROL REGISTER 4 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 UART2MD UART1MD MSSP2MD MSSP1MD -- -- -- CWG1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 UART2MD: Disable EUSART2 bit 1 = EUSART2 module disabled 0 = EUSART2 module enabled bit 6 UART1MD: Disable EUSART1 bit 1 = EUSART1 module disabled 0 = EUSART1 module enabled bit 5 MSSP2MD: Disable MSSP2 bit 1 = MSSP2 module disabled 0 = MSSP2 module enabled bit 4 MSSP1MD: Disable MSSP1 bit 1 = MSSP1 module disabled 0 = MSSP1 module enabled bit 3-1 Unimplemented: Read as `0' bit 0 CWG1MD: Disable CWG1 Module bit 1 = CWG1 module disabled 0 = CWG1 module enabled 2016 Microchip Technology Inc. Preliminary DS40001844B-page 71 PIC18(L)F27/47K40 REGISTER 7-6: PMD5: PMD CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- DSMMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as `0' bit 0 DSMMD: Disable Data Signal Modulator bit 1 = DSM module disabled 0 = DSM module enabled TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH PMD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PMD0 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD PMD1 -- TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD PMD2 -- DACMD ADCMD -- -- CMP2MD CMP1MD ZCDMD PMD3 -- -- -- -- PWM4MD PWM3MD CCP2MD CCP1MD PMD4 UART2MD UART1MD MSSP2MD MSSP1MD -- -- -- CWG1MD -- -- -- -- -- -- -- DSMMD PMD5 Legend: Register on page 67 68 69 70 71 72 -- = unimplemented, read as `0'. Shaded cells are not used by the PMD. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 72 PIC18(L)F27/47K40 8.0 RESETS There are multiple ways to reset this device: * * * * * * * * * Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 8-1. FIGURE 8-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000006E 5/11/2016 ICSPTM Programming Mode Exit RESET Instruction Stack Underflow Stack Overflow VPP/MCLR MCLRE WWDT Time-out/ Window voilation Device Reset Power-on Reset VDD Brown-out Reset(1) R LFINTOSC Power-up Timer PWRTE LPBOR Reset Note 1: See Table 8-1 for BOR active conditions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 73 PIC18(L)F27/47K40 FIGURE 8-2: LPBOR, BOR, POR RELATIONSHIP BOR BOR Event REARM POR Event To PCON indicator bit POR LPBOR POR Event LPBOR Event Reset logic 8.1 Register Definitions: BOR Control REGISTER 8-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u U-0 U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN -- -- -- -- -- -- BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN 01: SBOREN is read/write, but has no effect on the BOR. If BOREN = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as `0' bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset Circuit is active and armed 0 = The Brown-out Reset Circuit is disabled or is warming up 2016 Microchip Technology Inc. Preliminary DS40001844B-page 74 PIC18(L)F27/47K40 8.2 Register Definitions: Power Control REGISTER 8-2: PCON0: POWER CONTROL REGISTER 0 R/W/HS-0/q R/W/HS-0/q STKOVF STKUNF R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q WDTWV RWDT RMCLR R/W/HC-1/q R/W/HC-0/u R/W/HC-q/u RI POR BOR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred (more CALLs than fit on the stack) 0 = A Stack Overflow has not occurred or set to `0' by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred (more RETURNs than CALLs) 0 = A Stack Underflow has not occurred or set to `0' by firmware bit 5 WDTWV: Watchdog Window Violation bit 1 = A WDT window violation has not occurred or set to `1' by firmware 0 = A CLRWDT instruction was issued when the WDT Reset window was closed (set to `0' in hardware when a WDT window violation Reset occurs) bit 4 RWDT: WDT Reset Flag bit 1 = A WDT overflow/time-out Reset has not occurred or set to `1' by firmware 0 = A WDT overflow/time-out Reset has occurred (set to `0' in hardware when a WDT Reset occurs) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to `1' by firmware 0 = A MCLR Reset has occurred (set to `0' in hardware when a MCLR Reset occurs) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to `1' by firmware 0 = A RESET instruction has been executed (set to `0' in hardware upon executing a RESET instruction) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred or set to `1' by firmware 0 = A Power-on Reset occurred (set to `0' in hardware when a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred or set to `1' by firmware 0 = A Brown-out Reset occurred (set to `0' in hardware when a Brown-out Reset occurs) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 75 PIC18(L)F27/47K40 8.3 Power-on Reset (POR) 8.4.3 BOR CONTROLLED BY SOFTWARE The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. When the BOREN bits of Configuration Words are programmed to `01', the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. 8.4 BOR protection is unchanged by Sleep. Brown-out Reset (BOR) The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are: * * * * BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. 8.4.4 BOR AND BULK ERASE BOR is forced ON during PFM Bulk Erase operations to make sure that the system code protection cannot be compromised by reducing VDD. During Bulk Erase, the BOR is enabled at 2.45V for F and LF devices, even if it is configured to some other value. If VDD falls, the erase cycle will be aborted, but the device will not be reset. Refer to Table 8-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV<1:0> bits in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Table 37-11 for more information. 8.4.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to `11', the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 8.4.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to `10', the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 76 PIC18(L)F27/47K40 TABLE 8-1: BOR OPERATING MODES BOREN<1:0> SBOREN Device Mode BOR Mode 11 X X 10 Release of POR Wake-up from Sleep Active Wait for release of BOR (BORRDY = 1) Begins immediately Awake Active Wait for release of BOR (BORRDY = 1) N/A Sleep Hibernate N/A Wait for release of BOR (BORRDY = 1) 1 X Active 0 X Hibernate Wait for release of BOR (BORRDY = 1) Begins immediately X X Disabled X 01 00 FIGURE 8-3: Instruction Execution upon: Begins immediately BROWN-OUT SITUATIONS VDD Internal Reset VBOR TPWRT(1) VDD Internal Reset VBOR < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to `0'. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 77 PIC18(L)F27/47K40 8.5 Low-Power Brown-out Reset (LPBOR) 8.7 The Low-Power Brown-out Reset (LPBOR) provides an additional BOR circuit for low power operation. Refer to Figure 8-2 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. 8.5.1 ENABLING LPBOR The LPBOR is controlled by the LPBOREN bit of Configuration Word 2L. When the device is erased, the LPBOR module defaults to disabled. 8.5.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR'd together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON0 register and to the power control block. 8.6 MCLR The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 8-2). The RMCLR bit in the PCON0 register will be set to `0' if a MCLR has occurred. TABLE 8-2: MCLR CONFIGURATION MCLRE LVP MCLR x 1 Enabled 1 0 Enabled 0 0 Disabled 8.6.1 8.8 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON0 register will be set to `0'. See Table 8-3 for default conditions after a RESET instruction has occurred. 8.9 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON0 register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 10.2.1 "Stack Overflow and Underflow Resets" for more information. 8.10 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. Power-up Timer (PWRT) The Power-up Timer provides a nominal 66 ms (2048 cycles of LFINTOSC) time out on POR or Brown-out Reset. MCLR ENABLED The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. 8.6.2 The Windowed Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period or window set. The TO and PD bits in the STATUS register and the RWDT bit in the PCON0 register are changed to indicate a WDT Reset. The WDTWV bit in the PCON0 register indicates if the WDT Reset has occurred due to a time out or a window violation. See Section 9.0 "Windowed Watchdog Timer (WWDT)" for more information. 8.11 When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. Note: Windowed Watchdog Timer (WWDT) Reset An internal Reset event (RESET, instr, BOR, WWDT, POR STK), does not drive the MCLR pin low. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00000607). MCLR DISABLED When MCLR is disabled, the MCLR becomes input-only and pin functions such as internal weak pull-ups are under software control. See Section 15.1 "I/O Priorities" for more information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 78 PIC18(L)F27/47K40 8.12 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for selected oscillator source). MCLR must be released (if enabled). FIGURE 8-4: The total time out will vary based on oscillator configuration and Power-up Timer configuration. See Section 4.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator Start-up Timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 8-4). This is useful for testing purposes or to synchronize more than one device operating in parallel. RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2016 Microchip Technology Inc. Preliminary DS40001844B-page 79 PIC18(L)F27/47K40 8.13 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset. Table 8-3 shows the Reset conditions of these registers. TABLE 8-3: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register(2,3) PCON0 Register Power-on Reset 0 -110 0000 0011 110x Brown-out Reset 0 -110 0000 0011 11u0 MCLR Reset during normal operation 0 -uuu uuuu uuuu 0uuu MCLR Reset during Sleep 0 -10u uuuu uuuu 0uuu WDT Time-out Reset 0 -0uu uuuu uuu0 uuuu PC + 2 -00u uuuu uuuu uuuu 0 -uuu uuuu uu0u uuuu -10u 0uuu uuuu uuuu Condition WDT Wake-up from Sleep WWDT Window Violation Reset Interrupt Wake-up from Sleep PC + 2 (1) RESET Instruction Executed 0 -uuu uuuu uuuu u0uu Stack Overflow Reset (STVREN = 1) 0 -uuu uuuu 1uuu uuuu Stack Underflow Reset (STVREN = 1) 0 -uuu uuuu u1uu uuuu Legend: u = unchanged, x = unknown, -- = unimplemented bit, reads as `0'. Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2. 2: If a Status bit is not implemented, that bit will be read as `0'. 3: Status bits Z, C, DC are reset by POR/BOR (Register 10-2). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 80 PIC18(L)F27/47K40 8.14 Power Control (PCON0) Register The Power Control (PCON0) register contains flag bits to differentiate between a: * * * * * * * * Brown-out Reset (BOR) Power-on Reset (POR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Watchdog Window Violation (WDTWV) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) The PCON0 register bits are shown in Register 8-2. Hardware will change the corresponding register bit during the Reset process; if the Reset was not caused by the condition, the bit remains unchanged (Table 8-3). Software should reset the bit to the inactive state after restart (hardware will not reset the bit). Software may also set any PCON0 bit to the active state, so that user code may be tested, but no Reset action will be generated. TABLE 8-4: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN -- -- -- -- -- -- BORRDY 74 PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 75 STATUS -- TO PD N OV Z DC C 117 WDTCON0 -- -- SEN 84 WDTCON1 -- Name WDTPS<4:0> WDTCS<2:0> -- WINDOW<2:0> 85 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by Resets. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 81 PIC18(L)F27/47K40 9.0 WINDOWED WATCHDOG TIMER (WWDT) The Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The Windowed Watchdog Timer (WWDT) differs in that CLRWDT instructions are only accepted when they are performed within a specific window during the time-out period. The WWDT has the following features: * Selectable clock source * Multiple operating modes - WWDT is always on - WWDT is off when in Sleep - WWDT is controlled by software - WWDT is always off * Configurable time-out period is from 1 ms to 256s (nominal) * Configurable window size from 12.5% to 100% of the time-out period * Multiple Reset conditions 2016 Microchip Technology Inc. Preliminary DS40001844B-page 82 PIC18(L)F27/47K40 FIGURE 9-1: WINDOWED WATCHDOG TIMER BLOCK DIAGRAM Rev. 10-000 162A 1/2/201 4 WWDT Armed WDT Window Violation Window Closed Window Sizes CLRWDT Comparator WINDOW RESET Reserved 111 Reserved 110 Reserved 101 Reserved 100 Reserved 011 626& 010 MFINTOSC/16 001 LFINTOSC 000 R 18-bit Prescale Counter E CS PS R 5-bit WDT Counter Overflow Latch WDT Time-out WDTE<1:0> = 01 SEN WDTE<1:0> = 11 WDTE<1:0> = 10 Sleep 2016 Microchip Technology Inc. Preliminary DS40001844B-page 83 PIC18(L)F27/47K40 9.1 Register Definitions: Windowed Watchdog Timer Control REGISTER 9-1: WDTCON0: WATCHDOG TIMER CONTROL REGISTER 0 U-0 U-0 R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W(3)-q/q(2) R/W-0/0 -- -- WDTPS<4:0> SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-1 WDTPS<4:0>: Watchdog Timer Prescale Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) * * * 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 1x: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Note 1: 2: 3: Times are approximate. WDT time is based on 31 kHz LFINTOSC. When WDTCPS <4:0> in CONFIG3L = 11111, the Reset value of WDTPS<4:0> is 01011. Otherwise, the Reset value of WDTPS<4:0> is equal to WDTCPS<4:0> in CONFIG3L. When WDTCPS <4:0> in CONFIG3L 11111, these bits are read-only. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 84 PIC18(L)F27/47K40 REGISTER 9-2: WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1 (3) U-0 R/W -q/q(1) R/W(3)-q/q(1) R/W(3)-q/q(1) U-0 -- WDTCS<2:0> -- R/W(4)-q/q(2) R/W(4)-q/q(2) R/W(4)-q/q(2) WINDOW<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as `0' bit 6-4 WDTCS<2:0>: Watchdog Timer Clock Select bits 111 = Reserved * * * 010 = Reserved 001 = MFINTOSC 31.25 kHz 000 = LFINTOSC 31 kHz bit 3 Unimplemented: Read as `0' bit 2-0 WINDOW<2:0>: Watchdog Timer Window Select bits WINDOW Note 1: 2: 3: 4: <2:0> Window delay Percent of time Window opening Percent of time 111 N/A 100 110 12.5 87.5 101 25 75 100 37.5 62.5 011 50 50 010 62.5 37.5 001 75 25 000 87.5 12.5 If WDTCCS <2:0> in CONFIG3H = 111, the Reset value of WDTCS<2:0> is 000. The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3H register. If WDTCCS<2:0> in CONFIG3H 111, these bits are read-only. If WDTCWS<2:0> in CONFIG3H 111, these bits are read-only. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 85 PIC18(L)F27/47K40 REGISTER 9-3: R-0/0 WDTPSL: WWDT PRESCALE SELECT LOW BYTE REGISTER (READ-ONLY) R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 PSCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared PSCNT<7:0>: Prescale Select Low Byte bits(1) bit 7-0 Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. REGISTER 9-4: R-0/0 WDTPSH: WWDT PRESCALE SELECT HIGH BYTE REGISTER (READ-ONLY) R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 PSCNT<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: PSCNT<15:8>: Prescale Select High Byte bits(1) The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 86 PIC18(L)F27/47K40 REGISTER 9-5: R-0/0 WDTTMR: WDT TIMER REGISTER (READ-ONLY) R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 WDTTMR<4:0> R-0/0 STATE bit 7 R-0/0 PSCNT<17:16> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 WDTTMR<4:0>: Watchdog Window Value bits WINDOW WDT Window State Closed Open 111 N/A 00000-11111 100 110 00000-00011 00100-11111 87.5 101 00000-00111 01000-11111 75 100 00000-01011 01100-11111 62.5 011 00000-01111 10000-11111 50 010 00000-10011 10100-11111 37.5 001 00000-10111 11000-11111 25 000 00000-11011 11100-11111 12.5 bit 2 STATE: WDT Armed Status bit 1 = WDT is armed 0 = WDT is not armed bit 1-0 PSCNT<17:16>: Prescale Select Upper Byte bits(1) Note 1: Open Percent The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 87 PIC18(L)F27/47K40 9.2 Independent Clock Source 9.4 The WWDT can derive its time base from either the 31 kHz LFINTOSC or 31.25 kHz MFINTOSC internal oscillators, depending on the value of WDTE<1:0> Configuration bits. If WDTE = 2'b1x, then the clock source will be enabled depending on the WDTCCS<2:0> Configuration bits. If WDTE = 2'b01, the SEN bit should be set by software to enable WWDT, and the clock source is enabled by the WDTCS bits in the WDTCON1 register. Time intervals in this chapter are based on a minimum nominal interval of 1 ms. See Section 37.0 "Electrical Specifications" for LFINTOSC and MFINTOSC tolerances. 9.3 WWDT Operating Modes The Windowed Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 9-1. 9.3.1 WWDT IS ALWAYS ON When the WDTE bits of Configuration Words are set to `11', the WWDT is always on. WWDT protection is active during Sleep. 9.3.2 WWDT IS OFF IN SLEEP Time-out Period If the WDTCPS<4:0> Configuration bits default to 5'b11111, then the WDTPS bits of the WDTCON0 register set the time-out period from 1 ms to 256 seconds (nominal). If any value other than the default value is assigned to WDTCPS<4:0> Configuration bits, then the timer period will be based on the WDTCPS<4:0> bits in the CONFIG3L register. After a Reset, the default time-out period is 2s. 9.5 Watchdog Window The Windowed Watchdog Timer has an optional Windowed mode that is controlled by the WDTCWS<2:0> Configuration bits and WINDOW<2:0> bits of the WDTCON1 register. In the Windowed mode, the CLRWDT instruction must occur within the allowed window of the WDT period. Any CLRWDT instruction that occurs outside of this window will trigger a window violation and will cause a WWDT Reset, similar to a WWDT time out. See Figure 9-2 for an example. The window size is controlled by the WINDOW<2:0> Configuration bits, or the WINDOW<2:0> bits of WDTCON1, if WDTCWS<2:0> = 111. The five Most Significant bits of the WDTTMR register are used to determine whether the window is open, as defined by the WINDOW<2:0> bits of the WDTCON1 register. WWDT protection is not active during Sleep. In the event of a window violation, a Reset will be generated and the WDTWV bit of the PCON0 register will be cleared. This bit is set by a POR or can be set in firmware. 9.3.3 9.6 When the WDTE bits of Configuration Words are set to `10', the WWDT is on, except in Sleep. WWDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to `01', the WWDT is controlled by the SEN bit of the WDTCON0 register. WWDT protection is unchanged by Sleep. See Table 9-1 for more details. TABLE 9-1: WWDT OPERATING MODES WDTE<1:0> SEN 11 X 10 01 00 X Device Mode WWDT Mode X Active Awake Active Sleep Disabled The WWDT is cleared when any of the following conditions occur: * * * * * * * Any Reset Valid CLRWDT instruction is executed Device enters Sleep Exit Sleep by Interrupt WWDT is disabled Oscillator Start-up Timer (OST) is running Any write to the WDTCON0 or WDTCON1 registers 9.6.1 1 X Active 0 X Disabled X X Disabled Clearing the WWDT CLRWDT CONSIDERATIONS (WINDOWED MODE) When in Windowed mode, the WWDT must be armed before a CLRWDT instruction will clear the timer. This is performed by reading the WDTCON0 register. Executing a CLRWDT instruction without performing such an arming action will trigger a window violation regardless of whether the window is open or not. See Table 9-2 for more information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 88 PIC18(L)F27/47K40 9.7 Operation During Sleep When the device enters Sleep, the WWDT is cleared. If the WWDT is enabled during Sleep, the WWDT resumes counting. When the device exits Sleep, the WWDT is cleared again. The WWDT remains clear until the Oscillator Start-up Timer (OST) completes, if enabled. See Section 4.3.1.3 "Oscillator Start-up Timer (OST)" for more information on the OST. When a WWDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. The RWDT bit in the PCON0 register can also be used. See Section 10.0 "Memory Organization" for more information. TABLE 9-2: WWDT CLEARING CONDITIONS Conditions WWDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SEN = 0 WDTE<1:0> = 10 and enter Sleep Cleared CLRWDT Command Oscillator Fail Detected Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST Change INTOSC divider (IRCF bits) FIGURE 9-2: Unaffected WINDOW PERIOD AND DELAY Rev. 10-000 163A 11/8/201 3 CLRWDT Instruction (or other WDT reset) Window Period Window Closed Window Open Window Delay (window violation can occur) 2016 Microchip Technology Inc. Time-out Event Preliminary DS40001844B-page 89 PIC18(L)F27/47K40 TABLE 9-3: Name PCON0 SUMMARY OF REGISTERS ASSOCIATED WITH WINDOWED WATCHDOG TIMER Bit 7 Bit 6 STKOVF STKUNF WDTWV STATUS -- -- WDTCON0 -- -- WDTCON1 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RWDT RMCLR RI POR BOR 75 TO PD Z DC C 117 SEN 84 Bit 5 -- WDTPS<4:0> WDTCS<2:0> -- WINDOW<2:0> 85 WDTPSL PSCNT<7:0> 86 WDTPSH PSCNT<15:8> 86 WDTTMR WDTTMR<4:0> STATE PSCNT<17:16> 87 Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Windowed Watchdog Timer. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 90 PIC18(L)F27/47K40 10.0 MEMORY ORGANIZATION 10.1 There are three types of memory in PIC18 enhanced microcontroller devices: * Program Memory * Data RAM * Data EEPROM As Harvard architecture devices, the data and program memories use separate buses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Program Flash Memory and Data EEPROM Memory is provided in Section 11.0 "Nonvolatile Memory (NVM) Control". 2016 Microchip Technology Inc. Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2 Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2 Mbyte address will return all `0's (a NOP instruction). These devices contains the following: * PIC18(L)F27K40, PIC18(L)F47K40: 128 Kbytes of Flash memory, up to 65,536 single-word instructions PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Note: Preliminary For memory information on this family of devices, see Table 10-1 and Table 10-2. DS40001844B-page 91 PIC18(L)F27/47K40 TABLE 10-1: Note 1 00 0000h *** 00 0008h *** 00 0018h 00 001Ah * 00 3FFFh PROGRAM AND DATA MEMORY MAP PIC18(L)F24K40 PIC18(L)F25K40 PIC18(L)F45K40 PIC18(L)F26K40 PIC18(L)F46K40 PIC18(L)F27K40 PIC18(L)F47K40 PC<21:0> PC<21:0> PC<21:0> PC<21:0> Stack (31 levels) Stack (31 levels) Stack (31 levels) Stack (31 levels) Reset Vector Reset Vector Reset Vector Reset Vector *** *** *** *** Interrupt Vector High Interrupt Vector High Interrupt Vector High Interrupt Vector High *** *** *** *** Interrupt Vector Low Interrupt Vector Low Interrupt Vector Low Interrupt Vector Low User Flash Memory (8KW) 00 4000h * 00 7FFFh 00 8000h * 00 FFFFh 01 0000h * 01 FFFFh User Flash Memory (16KW) Note 1 00 0000h *** 00 0008h *** 00 0018h 00 001Ah * 00 3FFFh User Flash Memory (32KW) PFM Flash Memory (64KW) Not present(1) 00 8000h * 00 FFFFh 01 0000h * 01 FFFFh Not present(1) Not present(1) 02 0000h * 1F FFFFh 00 4000h * 00 7FFFh Not present(1) 02 0000h * 1F FFFFh 20 0000h *** 20 000Fh User IDs (8 Words) 20 0000h *** 20 000Fh 20 0010h *** 2F FFFFh Reserved 20 0010h *** 2F FFFFh 30 0000h *** 30 000Bh Configuration Words (6 Words) 30 0000h *** 30 000Bh 30 000Ch *** 30 FFFFh Reserved 30 000Ch *** 30 FFFFh 31 0000h *** 31 00FFh DataEEByte0 *** DataEEByte255 *** 31 03FFh Unimplemented DataEEByte0 31 0000h *** *** DataEEByte1023 *** 31 03FFh 31 0400h *** 3F FFFBh Reserved 31 0400h *** 3F FFFBh 3F FFFCh *** 3F FFFDh Revision ID (1 Word)(2) 3F FFFCh *** 3F FFFDh 3F FFFEh *** 3F FFFFh Device ID (1 Word)(2) 3F FFFEh *** 3F FFFFh Note 1: 2: The addresses do not roll over. The region is read as `0'. Device/Revision IDs are hard-coded in silicon. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 92 PIC18(L)F27/47K40 TABLE 10-2: Reg. MEMORY MAP AND CODE PROTECTION CONTROL Address (from/to) 00 0000h 00 07FFh 00 0800h 00 1FFFh 00 2000h 00 3FFFh Device PIC18(L)F24K40 PIC18(L)F25K40 PIC18(L)F45K40 PIC18(L)F26K40 PIC18(L)F46K40 PIC18(L)F27K40 PIC18(L)F47K40 Boot Block 1 KW CP, WRTB, EBTRB Boot Block 1 KW CP, WRTB, EBTRB Boot Block 1 KW CP WRTB, EBTRB Boot Block 1 KW CP WRTB, EBTRB Block 0 3 KW CP, WRT0, EBTR0 Block 0 3 KW CP, WRT0, EBTR0 Block 1 4 KW CP, WRT1, EBTR1 Block 1 4 KW CP, WRT1, EBTR1 Block 0 7 KW CP, WRT0, EBTR0 Block 0 7 KW CP, WRT0, EBTR0 Block 1 8 KW CP, WRT1, EBTR1 Block 1 8 KW CP, WRT1, EBTR1 Block 2 8 KW CP, WRT2, EBTR2 Block 2 8 KW CP, WRT2, EBTR2 Block 3 8 KW CP, WRT3, EBTR3 Block 3 8 KW CP, WRT3, EBTR3 00 4000h Block 2 4 KW CP, WRT2, EBTR2 00 5FFFh 00 6000h Block 3 4 KW CP, WRT3, EBTR3 00 7FFFh 00 8000h PFM 00 BFFFh 00 C000h 00 FFFFh 01 0000h Not present Block 4 8 KW CP, WRT4, EBTR4 01 3FFFh Not present 01 4000h Block 5 8 KW CP, WRT5, EBTR5 01 7FFFh Not present 01 8000h Block 6 8 KW CP, WRT6, EBTR6 01 BFFFh 01 C000h Block 7 8 KW CP, WRT7, EBTR7 01 FFFFh 30 0000h 6 Words WRTC CONFIG 30 000Bh 31 0000h Data EEPROM 31 00FFh 31 0100h 31 03FFh 2016 Microchip Technology Inc. 256 Words CPD, WRTD Unimplemented Preliminary 1 KW CPD, WRTD DS40001844B-page 93 PIC18(L)F27/47K40 10.1.1 PROGRAM COUNTER 10.1.2 The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 10.2.3.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, or as a 35-word by 21-bit RAM with a 6-bit Stack Pointer in ICD mode. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack (TOS) Special File registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits in the PCON0 register indicate if the stack is full or has overflowed or has underflowed. 10.1.2.1 Top-of-Stack Access Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 10-1). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the Global Interrupt Enable (GIE) bits while accessing the stack to prevent inadvertent stack corruption. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 94 PIC18(L)F27/47K40 FIGURE 10-1: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack <20:0> 11111 11110 11101 Top-of-Stack Registers TOSU 00h TOSH 1Ah STKPTR<4:0> 00010 TOSL 34h Top-of-Stack 10.1.2.2 Stack Pointer Return Stack Pointer (STKPTR) The STKPTR register (Register 10-1) contains the Stack Pointer value. The STKOVF (Stack Overflow) Status bit and the STKUNF (Stack Underflow) Status bit can be accessed using the PCON0 register. The value of the Stack Pointer can be 0 through 31. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for stack maintenance. After the PC is pushed onto the stack 32 times (without popping any values off the stack), the STKOVF bit is set. The STKOVF bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 3.1 "Configuration Words" for a description of the device Configuration bits.) If STVREN is set (default), a Reset will be generated and a Stack Overflow will be indicated by the STKOVF bit when the 32nd push is initiated. This includes CALL and CALLW instructions, as well as stacking the return address during an interrupt response. The STKOVF bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKOVF bit will be set on the 32nd push and the Stack Pointer will remain at 31 but no Reset will occur. Any additional pushes will overwrite the 31st push but the STKPTR will remain at 31. Setting STKOVF = 1 in software will change the bit, but will not generate a Reset. 001A34h 000D58h 00011 00010 00001 00000 If STVREN is cleared, the STKUNF bit will be set, but no Reset will occur. When STVREN = 0, STKUNF will be set but no Reset will occur. Note: 10.1.2.3 Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. PUSH and POP Instructions Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. The STKUNF bit is set when a stack pop returns a value of zero. The STKUNF bit is cleared by software or by POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 3.1 "Configuration Words" for a description of the device Configuration bits.) If STVREN is set (default) and the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC, it will set the STKUNF bit and a Reset will be generated. This condition can be generated by the RETURN, RETLW and RETFIE instructions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 95 PIC18(L)F27/47K40 10.2 Register Definitions: Stack Pointer REGISTER 10-1: STKPTR: STACK POINTER REGISTER U-0 U-0 U-0 -- -- -- R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKPTR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as `0' bit 4-0 STKPTR<4:0>: Stack Pointer Location bits 10.2.1 STACK OVERFLOW AND UNDERFLOW RESETS Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a Full or Underflow condition will set the appropriate STKOVF or STKUNF bit and then cause a device Reset. When STVREN is cleared, a Full or Underflow condition will set the appropriate STKOVF or STKUNF bit but not cause a device Reset. The STKOVF or STKUNF bits are cleared by the user software or a Power-on Reset. 10.2.2 Example 10-1 shows a source code example that uses the fast register stack during a subroutine call and return. EXAMPLE 10-1: FAST REGISTER STACK CODE EXAMPLE CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK RETURN, FAST SUB1 FAST REGISTER STACK A fast register stack is provided for the Status, WREG and BSR registers, to provide a "fast return" option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. In these cases, users must save the key registers by software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 96 PIC18(L)F27/47K40 10.2.3 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads 10.2.3.1 Computed GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 10-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value `nn' to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of two (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 10-2: ORG TABLE 10.2.3.2 MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 11.1.1 "Table Reads and Table Writes". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 97 PIC18(L)F27/47K40 10.3 10.3.1 PIC18 Instruction Cycle 10.3.2 An "Instruction Cycle" consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 10-3). CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruction register during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 10-2. FIGURE 10-2: INSTRUCTION FLOW/PIPELINING A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC PC PC + 2 PC + 4 OSC2/CLKOUT (RC mode) Execute INST (PC - 2) Fetch INST (PC) EXAMPLE 10-3: TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 4. BSF Execute INST (PC + 2) Fetch INST (PC + 4) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h 3. BRA Execute INST (PC) Fetch INST (PC + 2) SUB_1 Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 PORTA, BIT3 (Forced NOP) Flush (NOP) Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 98 PIC18(L)F27/47K40 10.3.3 INSTRUCTIONS IN PROGRAM MEMORY 10.3.4 The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of two and the LSb will always read `0' (see Section 10.1.1 "Program Counter"). Figure 10-3 shows an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 10-3 shows how the instruction GOTO 0006h is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 35.0 "Instruction Set Summary" provides further details of the instruction set. FIGURE 10-3: TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LFSR. In all cases, the second word of the instruction always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence - immediately after the first word - the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 10-4 shows how this works. Note: See Section 10.8 "PIC18 Instruction Execution and the Extended Instruction Set" for information on two-word instructions in the extended instruction set. INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations Instruction 1: Instruction 2: MOVLW GOTO 055h 0006h Instruction 3: MOVFF 123h, 456h EXAMPLE 10-4: Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h TWO-WORD INSTRUCTIONS CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; No, skip this word ; Execute this word as a NOP ADDWF REG3 ; continue code 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; Yes, execute this word ; 2nd word of instruction ADDWF REG3 ; continue code CASE 2: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 2016 Microchip Technology Inc. Preliminary DS40001844B-page 99 PIC18(L)F27/47K40 10.4 Note: Data Memory Organization 10.4.1 The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 10.7 "Data Memory and the Extended Instruction Set" for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. Figure 10-4 shows the data memory organization for the PIC18(L)F2x/4xK40 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the Bank Select Register (BSR). Section 10.4.2 "Access Bank" provides a detailed description of the Access RAM. BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the four Most Significant bits of a location's address; the instruction itself includes the eight Least Significant bits. Only the four lower bits of the BSR are implemented (BSR<3:0>). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory; the eight bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 10-4. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h while the BSR is 0Fh will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory maps in Figure 10-4 indicate which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 100 2016 Microchip Technology Inc. FIGURE 10-4: DATA MEMORY MAP FOR PIC18(L)F2X/4XK40 DEVICES Bank BSR<3:0> addr<7:0> 00h Bank 0 0001 Bank 2 0010 Bank 3 0011 Preliminary Banks 4 to 7 Access RAM Access RAM GPR GPR GPR 0FFh 100h FFh 00h FFh GPR GPR GPR 00h 3FFh 00h 400h -- GPR GPR 0111 Unimplemented GPR 1101 00h FFh DFFh Unimplemented(1) Unimplemented(1) SFR(1) SFR(1) GPR(1) E00h SFR(1) EFFh 00h F00h DS40001844B-page 101 SFR 1111 * * * SFR SFR FFh Note 1: It depends on the number of SFRs. Refer to Table 10-3 and Table 10-4. F5Fh F60h FFFh Virtual Bank Access RAM 00h 5Fh SFR 60h FFh PIC18(L)F27/47K40 800h 1000 -- * * * 7FFh Unimplemented FFh Bank 15 * * * FFh 0100 1110 060h 00h 00h Bank 14 000h FFh FFh Banks 8 to 13 Access RAM Address addr<11:0> 05Fh 0000 Bank 1 PIC18(L)F26K40 PIC18(L)F25K40 PIC18(L)F27K40 PIC18(L)F24K40 PIC18(L)F45K40 PIC18(L)F46K40 PIC18(L)F47K40 PIC18(L)F27/47K40 FIGURE 10-5: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 0 000h Data Memory Bank 0 100h Bank 1 200h 300h Bank 2 00h 7 FFh 00h 1 From Opcode(2) 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 102 PIC18(L)F27/47K40 10.4.2 ACCESS BANK 10.4.3 While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. This upper half is also where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 10-4). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0', however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. 10.4.4 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top portion of Bank 15 (F38h to FFFh). A list of these registers is given in Table 10-3 and Table 10-4. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle, without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 10.7.3 "Mapping the Access Bank in Indexed Literal Offset Mode". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 103 PIC18(L)F27/47K40 TABLE 10-3: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F27/47K40 DEVICES Name Address Name Address Name Address Name FFFh TOSU FD7h PCON0 FAFh T6TMR F87h LATE(2) FFEh TOSH FD6h T0CON1 FAEh CCPTMRS F86h LATD(2) FFDh TOSL FD5h T0CON0 FADh CCP1CAP F85h LATC FFCh STKPTR FD4h TMR0H FACh CCP1CON F84h LATB FFBh PCLATU FD3h TMR0L FABh CCP1H F83h LATA FFAh PCLATH FD2h T1CLK FAAh CCP1L F82h NVMCON2 FF9h PCL FD1h T1GATE FA9h CCP2CAP F81h NVMCON1 FF8h TBLPTRU FD0h T1GCON FA8h CCP2CON F80h NVMDAT FF7h TBLPTRH FCFh T1CON FA7h CCP2H F7Fh NVMADRH FF6h TBLPTRL FCEh TMR1H FA6h CCP2L F7Eh NVMADRL FF5h TABLAT FCDh TMR1L FA5h PWM3CON F7Dh CRCCON1 FF4h PRODH FCCh T3CLK FA4h PWM3DCH F7Ch CRCCON0 FF3h PRODL FCBh T3GATE FA3h PWM3DCL F7Bh CRCXORH FF2h INTCON FCAh T3GCON FA2h PWM4CON F7Ah CRCXORL FF1h -- FC9h T3CON FA1h PWM4DCH F79h CRCSHIFTH FF0h -- FC8h TMR3H FA0h PWM4DCL F78h CRCSHIFTL (1) FC7h TMR3L F9Fh BAUD1CON F77h CRCACCH FEEh POSTINC0(1) FC6h T5CLK F9Eh TX1STA F76h CRCACCL FEDh POSTDEC0(1) FC5h T5GATE F9Dh RC1STA F75h CRCDATH FECh PREINC0(1) FC4h T5GCON F9Ch SP1BRGH F74h CRCDATL FEBh PLUSW0(1) FC3h T5CON F9Bh SP1BRGL F73h ADFLTRH FEAh FSR0H FC2h TMR5H F9Ah TX1REG F72h ADFLTRL FE9h FSR0L FC1h TMR5L F99h RC1REG F71h ADACCH FE8h WREG FC0h T2RST F98h SSP1CON3 F70h ADACCL ADERRH FEFh INDF0 (1) FBFh T2CLKCON F97h SSP1CON2 F6Fh FE6h POSTINC1(1) FBEh T2HLT F96h SSP1CON1 F6Eh ADERRL FE5h POSTDEC1(1) FBDh T2CON F95h SSP1STAT F6Dh ADUTHH FE4h PREINC1(1) FBCh T2PR F94h SSP1MSK F6Ch ADUTHL FE3h PLUSW1 (1) FBBh T2TMR F93h SSP1ADD F6Bh ADLTHH FE2h FSR1H FBAh T4RST F92h SSP1BUF F6Ah ADLTHL FE1h FSR1L FB9h T4CLKCON F91h PORTE F69h ADSTPTH FE0h BSR FB8h T4HLT F90h PORTD(2) F68h ADSTPTL FDFh INDF2(1) FB7h T4CON F8Fh PORTC F67h ADCNT FDEh POSTINC2(1) FB6h T4PR F8Eh PORTB F66h ADRPT FDDh POSTDEC2(1) FB5h T4TMR F8Dh PORTA F65h ADSTAT FDCh PREINC2 (1) FB4h T6RST F8Ch TRISE(2) F64h ADRESH FDBh PLUSW2 (1) FB3h T6CLKCON F8Bh (2) F63h ADRESL FDAh FSR2H FB2h T6HLT F8Ah TRISC F62h ADPREVH FD9h FSR2L FB1h T6CON F89h TRISB F61h ADPREVL FD8h STATUS FB0h T6PR F88h TRISA F60h ADCON0 FE7h INDF1 TRISD Note 1: This is not a physical register. 2: Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 104 PIC18(L)F27/47K40 TABLE 10-4: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F27/47K40 DEVICES Name Address Name Address Name Address (1) Name Address Name F5Fh ADPCH F31h FVRCON F03h RD4PPS ED5h WDTPSH EA7h F5Eh ADPRE F30h HLVDCON1 F02h RD3PPS(1) ED4h WDTPSL EA6h T3CKIPPS T1GPPS F5Dh ADCAP F2Fh HLVDCON0 F01h RD2PPS(1) ED3h WDTCON1 EA5h T1CKIPPS F5Ch ADACQ F2Eh ANSELE(2) F00h RD1PPS(2) ED2h WDTCON0 EA4h T0CKIPPS F5Bh ADCON3 F2Dh WPUE EFFh RD0PPS(2) ED1h PIR7 EA3h INT2PPS F5Ah ADCON2 F2Ch ODCONE(2) EFEh RC7PPS ED0h PIR6 EA2h INT1PPS F59h ADCON1 F2Bh SLRCONE(2) EFDh RC6PPS ECFh PIR5 EA1h INT0PPS F58h ADREF F2Ah INLVLE EFCh RC5PPS ECEh PIR4 EA0h PPSLOCK BAUD2CON F57h ADCLK F29h IOCEP EFBh RC4PPS ECDh PIR3 E9Fh F56h ADACT F28h IOCEN EFAh RC3PPS ECCh PIR2 E9Eh TX2STA F55h MDCARH F27h IOCEF EF9h RC2PPS ECBh PIR1 E9Dh RC2STA F54h MDCARL F26h ANSELD(2) EF8h RC1PPS ECAh PIR0 E9Ch SP2BRGH F53h MDSRC F25h WPUD(2) EF7h RC0PPS EC9h PIE7 E9Bh SP2BRGL F52h MDCON1 F24h ODCOND(2) EF6h RB7PPS EC8h PIE6 E9Ah TX2REG F51h MDCON0 F23h SLRCOND(2) EF5h RB6PPS EC7h PIE5 E99h RC2REG F50h SCANDTRIG F22h INLVLD(2) EF4h RB5PPS EC6h PIE4 E98h SSP2CON3 F4Fh SCANCON0 F21h ANSELC EF3h RB4PPS EC5h PIE3 E97h SSP2CON2 F4Eh SCANHADRU F20h WPUC EF2h RB3PPS EC4h PIE2 E96h SSP2CON1 F4Dh SCANHADRH F1Fh ODCONC EF1h RB2PPS EC3h PIE1 E95h SSP2STAT F4Ch SCANHADRL F1Eh SLRCONC EF0h RB1PPS EC2h PIE0 E94h SSP2MSK F4Bh SCANLADRU F1Dh INLVLC EEFh RB0PPS EC1h IPR7 E93h SSP2ADD F4Ah SCANLADRH F1Ch IOCCP EEEh RA7PPS EC0h IPR6 E92h SSP2BUF F49h SCANLADRL F1Bh IOCCN EEDh RA6PPS EBFh IPR5 E91h SSP2SSPPS F48h CWG1STR F1Ah IOCCF EECh RA5PPS EBEh IPR4 E90h SSP2DATPPS F47h CWG1AS1 F19h ANSELB EEBh RA4PPS EBDh IPR3 E8Fh SSP2CLKPPS F46h CWG1AS0 F18h WPUB EEAh RA3PPS EBCh IPR2 E8Eh TX2PPS F45h CWG1CON1 F17h ODCONB EE9h RA2PPS EBBh IPR1 E8Dh RX2PPS F44h CWG1CON0 F16h SLRCONB EE8h RA1PPS EBAh IPR0 F43h CWG1DBF F15h INLVLB EE7h RA0PPS EB9h SSP1SSPPS F42h CWG1DBR F14h IOCBP EE6h PMD5 EB8h SSP1DATPPS F41h CWG1ISM F13h IOCBN EE5h PMD4 EB7h SSP1CLKPPS F40h CWG1CLKCON F12h IOCBF EE4h PMD3 EB6h TX1PPS F3Fh CLKRCLK F11h ANSELA EE3h PMD2 EB5h RX1PPS F3Eh CLKRCON F10h WPUA EE2h PMD1 EB4h MDSRCPPS F3Dh CMOUT F0Fh ODCONA EE1h PMD0 EB3h MDCARHPPS F3Ch CM1PCH F0Eh SLRCONA EE0h BORCON EB2h MDCARLPPS F3Bh CM1NCH F0Dh INLVLA EDFh VREGCON(1) EB1h CWGINPPS F3Ah CM1CON1 F0Ch IOCAP EDEh OSCFRQ EB0h CCP2PPS F39h CM1CON0 F0Bh IOCAN EDDh OSCTUNE EAFh CCP1PPS F38h CM2PCH F0Ah IOCAF EDCh OSCEN EAEh ADACTPPS F37h CM2NCH F09h RE2PPS(2) EDBh OSCSTAT EADh T6INPPS F36h CM2CON1 F08h RE1PPS(2) EDAh OSCCON3 EACh T4INPPS F35h CM2CON0 F07h RE0PPS(2) ED9h OSCCON2 EABh T2INPPS F34h DAC1CON1 F06h RD7PPS(2) ED8h OSCCON1 EAAh T5GPPS F33h DAC1CON0 F05h RD6PPS(2) ED7h CPUDOZE EA9h T5CKIPPS F32h ZCDCON F04h RD5PPS(2) ED6h WDTTMR EA8h T3GPPS Note 1: 2: Not available on LF parts Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 105 PIC18(L)F27/47K40 TABLE 10-5: Address FFFh REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES Name TOSU Bit 7 Bit 6 Bit 5 -- -- -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top of Stack Upper byte (TOS<20:16>) Value on POR, BOR ---xxxxx FFEh TOSH Top of Stack High byte (TOS<15:8>) xxxxxxxx FFDh TOSL Top of Stack Low byte (TOS<7:0>) xxxxxxxx FFCh STKPTR -- -- -- FFBh PCLATU -- -- -- FFAh PCLATH FF9h PCL FF8h TBLPTRU FF7h TBLPTRH Program Memory Table Pointer (TBLPTR<15:8>) 00000000 FF6h TBLPTRL Program Memory Table Pointer (TBLPTR<7:0>) 00000000 FF5h TABLAT TABLAT 00000000 FF4h PRODH Product Register High byte xxxxxxxx FF3h PRODL FF2h INTCON FF1h -- FF0h -- FEFh INDF0 -- -- STKPTR<4:0> --000000 Holding Register for PC<20:16> ---00000 Holding Register for PC<15:8> 00000000 PC Low byte (PC<7:0>) 00000000 Program Memory Table Pointer (TBLPTR<21:16>) --000000 Product Register Low byte GIE/GIEH PEIE/GIEL IPEN -- -- xxxxxxxx INT2EDG INT1EDG INT0EDG 000--111 Unimplemented -- Unimplemented -- Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) -------- FEEh POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) -------- FEDh POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) -------- FECh PREINC0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) -------- FEBh PLUSW0 Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W -------- FEAh FSR0H FE9h FSR0L Indirect Data Memory Address Pointer 0 Low xxxxxxxx FE8h WREG Working Register xxxxxxxx Uses contents of FSR0 to address data memory - value of FSR1 not changed (not a physical register) -------- FE7h INDF1 FE6h POSTINC1 -- -- -- -- Indirect Data Memory Address Pointer 0 High ----xxxx Uses contents of FSR0 to address data memory - value of FSR1 post-incremented (not a physical register) -------- FE5h POSTDEC1 Uses contents of FSR0 to address data memory - value of FSR1 post-decremented (not a physical register) -------- FE4h PREINC1 Uses contents of FSR0 to address data memory - value of FSR1 pre-incremented (not a physical register) -------- FE3h PLUSW1 Uses contents of FSR0 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR0 offset by W -------- Legend: Note 1: 2: x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 106 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 -- -- -- -- Bit 3 Bit 2 Bit 1 Bit 0 Indirect Data Memory Address Pointer 1 High Value on POR, BOR FE2h FSR1H FE1h FSR1L FE0h BSR FDFh INDF2 Uses contents of FSR0 to address data memory - value of FSR2 not changed (not a physical register) -------- FDEh POSTINC2 Uses contents of FSR0 to address data memory - value of FSR2 post-incremented (not a physical register) -------- Indirect Data Memory Address Pointer 1 Low -- -- -- -- ----xxxx xxxxxxxx Bank Select Register ----0000 FDDh POSTDEC2 Uses contents of FSR0 to address data memory - value of FSR2 post-decremented (not a physical register) -------- FDCh PREINC2 Uses contents of FSR0 to address data memory - value of FSR2 pre-incremented (not a physical register) -------- FDBh PLUSW2 Uses contents of FSR0 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR0 offset by W -------- FDAh FSR2H FD9h FSR2L FD8h STATUS -- FD7h PCON0 STKOVF FD6h T0CON1 FD5h T0CON0 -- -- -- -- Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low TO PD STKUNF WDTWV T0CS<2:0> T0EN -- T0OUT ----xxxx xxxxxxxx N OV Z DC C -1100000 RWDT RMCLR RI POR BOR 0011110q T0ASYNC T0CKPS<3:0> 00000000 T016BIT T0OUTPS<3:0> 0-000000 FD4h TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 11111111 FD3h TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 00000000 FD2h T1CLK -- -- -- -- CS<3:0> ----0000 FD1h T1GATE -- -- -- -- GSS<3:0> ----0000 FD0h T1GCON GE GPOL GTM GSPM -- -- GO/DONE GVAL -- -- 00000x-- -- SYNC RD16 ON --00-000 FCFh T1CON FCEh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 00000000 FCDh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 00000000 FCCh T3CLK -- -- -- -- CS<3:0> ----0000 FCBh T3GATE -- -- -- -- GSS<3:0> ----0000 GTM CKPS<1:0> FCAh T3GCON GE GPOL FC9h T3CON -- -- FC8h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register FC7h TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register FC6h TMR5CLK -- -- -- -- CS<3:0> ----0000 FC5h T5GATE -- -- -- -- GSS<3:0> ----0000 GTM FC4h T5GCON GE GPOL FC3h T5CON -- -- FC2h TMR5H Legend: Note 1: 2: GSPM CKPS<1:0> GSPM CKPS<1:0> GO/DONE GVAL -- -- 00000x-- -- SYNC RD16 ON --00-000 00000000 00000000 GO/DONE GVAL -- -- 00000x-- -- SYNC RD16 ON --00-000 Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 00000000 x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 107 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Holding Register for the Least Significant Byte of the 16-bit TMR5 Register Value on POR, BOR FC1h TMR5L FC0h T2RST -- -- -- -- RSEL<3:0> ----0000 FBFh T2CLKCON -- -- -- -- CS<3:0> ----0000 FBEh T2HLT PSYNC CPOL FBDh T2CON ON FBCh T2PR TMR2 Period Register 11111111 FBBh T2TMR Holding Register for the 8-bit TMR2 Register 00000000 FBAh T4RST -- -- -- -- RSEL<3:0> ----0000 FB9h T4CLKCON -- -- -- -- CS<3:0> ----0000 FB8h T4HLT PSYNC CPOL CSYNC CSYNC 00000000 MODE<4:0> CKPS<2:0> ON 00000000 OUTPS<3:0> 00000000 MODE<4:0> CKPS<2:0> 00000000 FB7h T4CON FB6h T4PR TMR4 Period Register OUTPS<3:0> 11111111 FB5h T4TMR Holding Register for the 8-bit TMR4 Register 00000000 FB4h T6RST -- -- -- -- RSEL<3:0> ----0000 FB3h T6CLKCON -- -- -- -- CS<3:0> ----0000 FB2h T6HLT PSYNC CPOL FB1h T6CON ON FB0h T6PR TMR6 Period Register FAFh T6TMR Holding Register for the 8-bit TMR6 Register FAEh CCPTMRS FADh CCP1CAP CSYNC MODE<4:0> CKPS<2:0> P4TSEL<1:0> 00000000 00000000 OUTPS<3:0> 00000000 11111111 00000000 P3TSEL<1:0> -- -- -- -- EN -- OUT FMT C2TSEL<1:0> -- C1TSEL<1:0> 01010101 CTS<1:0> ------00 -- MODE<3:0> FACh CCP1CON FABh CCPR1H Capture/Compare/PWM Register 1 (MSB) FAAh CCPR1L Capture/Compare/PWM Register 1 (LSB) FA9h CCP2CAP -- -- -- -- FA8h CCP2CON EN -- OUT FMT FA7h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxxxxxx FA6h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxxxxxx FA5h PWM3CON FA4h PWM3DCH FA3h PWM3DCL FA2h PWM4CON FA1h PWM4DCH FA0h PWM4DCL -- EN 0-000000 xxxxxxxx xxxxxxxx OUT POL -- -- OUT POL -- -- CTS<1:0> ------00 MODE<3:0> 0-000000 -- -- -- -- -- -- -- -- xx------ -- -- -- -- 0-00---- DC<7:0> DC<9:8> -- EN xxxxxxxx DC7:0> -- DC<9:8> -- 0-00---- xxxxxxxx -- -- -- -- xx------ F9Fh BAUD1CON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 01-00-00 F9Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 00000010 F9Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 00000000 F9Ch SP1BRGH Legend: Note 1: 2: EUSART1 Baud Rate Generator, High Byte 00000000 x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 108 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F9Bh SP1BRGL EUSART1 Baud Rate Generator, Low Byte 00000000 F9Ah TX1REG EUSART1 Transmit Register 00000000 F99h RC1REG EUSART1 Receive Register F98h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 00000000 F97h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 00000000 F96h SSP1CON1 WCOL SSPOV SSPEN CKP F95h SSP1STAT SMP CKE D/A P S R/W BF 00000000 00000000 SSPM<3:0> 00000000 UA F94h SSP1MSK MSK<7:0> 11111111 F93h SSP1ADD ADD<7:0> 00000000 F92h SSP1BUF BUF<7:0> xxxxxxxx (2) RE2 (2) RE1 RE1 (2) F91h PORTE -- -- -- -- RE0 F90h PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxxxxxx F8Fh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxxxxxx F8Eh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxxxxxx F8Dh PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxxxxxx TRISE1(2) ----xxxx F8Ch TRISE -- -- -- -- -- TRISE2(2) TRISE0 -----111 F8Bh TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 11111111 F8Ah TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 11111111 F89h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 11111111 F88h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11111111 LATE0 -----xxx F87h LATE -- (2) -- -- -- -- (2) LATE2 LATE1 (2) F86h LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxxxxxx F85h LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxxxxxx F84h LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxxxxxx F83h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxxxxxx F82h NVMCON2 F81h NVMCON1 F80h NVMDAT F7Fh NVMADRH F7Eh NVMADRL F7Dh CRCCON1 NVMCON2<7:0> NVMREG<1:0> -- FREE WRERR 00000000 WREN WR RD NVMDAT<7:0> -- -- -- -- -- 00000000 -- NVMADR<9:8> NVMADR<7:0> GO PLEN<3:0> BUSY ACCM ------xx xxxxxxxx DLEN<3:0> EN 00-0x000 00000000 F7Ch CRCCON0 F7Bh CRCXORH F7Ah CRCXORL F79h CRCSHIFTH SHIFT<15:8> 00000000 F78h CRCSHIFTL SHIFT<7:0> 00000000 F77h CRCACCH ACC<15:8> 00000000 -- -- SHIFTM FULL X<15:8> X<7:1> 0000--00 xxxxxxxx -- xxxxxxx0 F76h CRCACCL ACC<7:0> 00000000 F75h CRCDATH DATA<15:8> xxxxxxxx Legend: Note 1: 2: x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 109 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F74h CRCDATL DATA<7:0> xxxxxxxx F73h ADFLTRH ADFLTRH<15:8> xxxxxxxx F72h ADFLTRL ADFLTRL<7:0> xxxxxxxx F71h ADACCH ADACCH<15:8> xxxxxxxx F70h ADACCL ADACCL<7:0> xxxxxxxx F6Fh ADERRH ADERRH<15:8> 00000000 F6Eh ADERRL ADERRL<7:0> 00000000 F6Dh ADUTHH ADUTHH<15:8> 00000000 F6Ch ADUTHL ADUTHL<7:0> 00000000 F6Bh ADLTHH ADLTHH<15:8> 00000000 F6Ah ADLTHL ADLTHL<7:0> 00000000 F69h ADSTPTH ADSTPTH<15:8> 00000000 F68h ADSTPTL ADSTPTL<7:0> 00000000 F67h ADCNT ADCNT<7:0> 00000000 F66h ADRPT ADRPT<7:0> 00000000 ADAOV ADUTHR ADLTHR ADMATH ADSTAT<2:0> F65h ADSTAT F64h ADRESH ADRESH<7:0> 00000000 F63h ADRESL ADRESL<7:0> 00000000 -- 0000-000 F62h ADPREVH ADPREVH<15:8> 00000000 F61h ADPREVL ADPREVL<7:0> 00000000 F60h ADCON0 F5Fh ADPCH F5Eh ADPRE ADON ADCONT -- -- -- ADSC ADFM -- ADGO -- ADPCH<5:0> --000000 ADPRE<7:0> 00000000 F5Dh ADCAP F5Ch ADACQ F5Bh ADCON3 F5Ah ADCON2 ADPSIS F59h ADCON1 ADPPOL ADIPEN ADGPOL -- -- -- F58h ADREF -- -- -- ADNREF -- -- F57h ADCLK -- -- F56h ADACT -- -- -- -- -- -- ADCAP<4:0> ---00000 ADACQ<7:0> -- ADCALC<2:0> 00000000 ADSOI ADCRS<2:0> 00-000-0 ADTMD<2:0> ADACLR -0000000 ADMD<2:0> -- 00000000 ADDSEN ADPREF<1:0> ADCS<5:0> 000----0 ---0--00 --000000 ADACT<4:0> ---00000 F55h MDCARH -- -- -- -- -- CHS<2:0> -----000 F54h MDCARL -- -- -- -- -- CLS<2:0> -----000 F53h MDSRC -- -- -- -- SRCS<3:0> ----0000 F52h MDCON1 -- -- CHPOL CHSYNC -- -- CLPOL CLSYNC --00--00 F51h MDCON0 EN -- OUT OPOL -- -- -- MDBIT 0-00---0 F50h SCANTRIG -- -- -- -- F4Fh SCANCON0 SCANEN SCANGO BUSY INVALID INTM -- F4Eh SCANHADRU -- -- Legend: Note 1: 2: TSEL<3:0> HADR<21:16> ----0000 MODE<1:0> 00000-00 --111111 x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 110 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Value on POR, BOR Bit 0 F4Dh SCANHADRH HADR<15:8> 11111111 F4Ch SCANHADRL HADR<7:0> 11111111 -- -- LADR<21:16> F4Bh SCANLADRU F4Ah SCANLADRH LADR<15:8> 00000000 F49h SCANLADRL LADR<7:0> 00000000 --000000 F48h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 00000000 F47h CWG1AS1 -- -- AS5E AS4E AS3E AS2E AS1E AS0E --000000 -- -- 000101-- POLB POLA --x-0000 F46h CWG1AS0 SHUTDOWN REN F45h CWG1CON1 -- -- IN LSBD<1:0> -- POLD LSAC<1:0> F44h CWG1CON0 EN LD -- -- -- F43h CWG1DBF -- -- DBF<5:0> --000000 F42h CWG1DBR -- -- DBR<5:0> --000000 F41h CWG1ISM -- -- -- -- -- F40h CWG1CLKCON -- -- -- -- -- F3Fh CLKRCLK -- -- -- -- -- F3Eh CLKRCON CLKREN -- -- F3Dh CMOUT -- -- -- -- -- F3Ch CM1PCH -- -- -- -- -- F3Bh CM1NCH -- -- -- -- -- F3Ah CM1CON1 -- -- -- -- -- -- INTP INTN -----100 F39h CM1CON0 EN OUT -- POL -- -- HYS SYNC 00-0--00 POLC MODE<2:0> 00---000 ISM<2:0> -- -- -----000 CS -------0 CLKRxCLK<2:0> CLKRDC<1:0> -----000 CLKRDIV<2:0> -- MC2OUT 0--10000 MC1OUT PCH<2:0> ------00 -----000 NCH<2:0> -----000 F38h CM2PCH -- -- -- -- -- C2PCH<2:0> -----000 F37h CM2NCH -- -- -- -- -- C2NCH<2:0> -----000 F36h CM2CON1 -- -- -- -- -- -- INTP INTN -----100 F35h CM2CON0 EN OUT -- POL -- -- HYS SYNC 00-0--00 F34h DAC1CON1 -- -- -- DAC1R<4:0> PSS<1:0> ---xxxxx F33h DAC1CON0 EN -- OE1 OE2 F32h ZCDCON SEN -- OUT POL F31h FVRCON FVREN FVRRDY TSEN TSRNG F30h HLVDCON1 -- -- -- -- F2Fh HLVDCON0 EN -- OUT RDY -- -- F2Eh ANSELE(2) -- -- -- -- -- ANSELE2 ANSELE1 ANSELE0 (2) (2) (2) -- -- NSS 0-0000-0 INTN 0-x0--00 CDAFVR<1:0> ADFVR<1:0> 0x000000 HLVDSEL<3:0> ----0000 INTH F2Dh WPUE -- -- -- -- WPUE3 F2Ch ODCONE(2) -- -- -- -- -- F2Bh SLRCONE(2) -- -- -- -- -- SLRE2 F2Ah INLVLE -- -- -- -- INLVLE3 INLVLE2(2) F29h IOCEP -- -- -- -- IOCEP3 -- F28h IOCEN -- -- -- -- IOCEN3 F27h IOCEF -- -- -- -- IOCEF3 Legend: Note 1: 2: -- INTP WPUE2 ODCE2 INTL WPUE1 ODCE1 WPUE0 0-xx--00 -----111 ----0000 ODCE0 -----000 SLRE1 SLRE0 -----111 INLVLE1(2) INLVLE0(2) ----1111 -- -- ----0--- -- -- -- ----0--- -- -- -- ----0--- x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 111 PIC18(L)F27/47K40 TABLE 10-5: Address F26h F25h REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name ANSELD(2) WPUD (2) (2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0 11111111 WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 00000000 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 00000000 SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 11111111 F24h ODCOND F23h SLRCOND(2) F22h INLVLD(2) INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 10000000 F21h ANSELC ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 11111111 F20h WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 00000000 F1Fh ODCONC ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 00000000 F1Eh SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 11111111 F1Dh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 11111111 F1Ch IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 00000000 F1Bh IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 00000000 F1Ah IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 00000000 F19h ANSELB ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 11111111 F18h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 00000000 F17h ODCONB ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 00000000 F16h SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 11111111 F15h INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 11111111 F14h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 00000000 F13h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 00000000 F12h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 00000000 F11h ANSELA ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0 11111111 F10h WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 00000000 F0Fh ODCONA ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 00000000 F0Eh SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 11111111 F0Dh INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 11111111 F0Ch IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 00000000 F0Bh IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 00000000 F0Ah IOCAF IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 00000000 IOCAF7 IOCAF6 IOCAF5 F09h RE2PPS (2) -- -- -- RE2PPS<4:0> ---00000 F08h RE1PPS(2) -- -- -- RE1PPS<4:0> ---00000 F07h RE0PPS (2) -- -- -- RE0PPS<4:0> ---00000 F06h RD7PPS(2) -- -- -- RD7PPS<4:0> ---00000 F05h RD6PPS (2) -- -- -- RD6PPS<4:0> ---00000 F04h RD5PPS (2) -- -- -- RD5PPS<4:0> ---00000 F03h RD4PPS(2) -- -- -- RD4PPS<4:0> ---00000 F02h RD3PPS(2) -- -- -- RD3PPS<4:0> ---00000 F01h RD2PPS (2) -- -- -- RD2PPS<4:0> ---00000 F00h RD1PPS(2) -- -- -- RD1PPS<4:0> ---00000 Legend: Note 1: 2: x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 112 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR EFFh RD0PPS(2) -- -- -- RD0PPS<4:0> ---00000 EFEh RC7PPS -- -- -- RC7PPS<4:0> ---00000 EFDh RC6PPS -- -- -- RC6PPS<4:0> ---00000 EFCh RC5PPS -- -- -- RC5PPS<4:0> ---00000 EFBh RC4PPS -- -- -- RC4PPS<4:0> ---00000 EFAh RC3PPS -- -- -- RC3PPS<4:0> ---00000 EF9h RC2PPS -- -- -- RC2PPS<4:0> ---00000 EF8h RC1PPS -- -- -- RC1PPS<4:0> ---00000 EF7h RC0PPS -- -- -- RC0PPS<4:0> ---00000 EF6h RB7PPS -- -- -- RB7PPS<4:0> ---00000 EF5h RB6PPS -- -- -- RB6PPS<4:0> ---00000 EF4h RB5PPS -- -- -- RB5PPS<4:0> ---00000 EF3h RB4PPS -- -- -- RB4PPS<4:0> ---00000 EF2h RB3PPS -- -- -- RB3PPS<4:0> ---00000 EF1h RB2PPS -- -- -- RB2PPS<4:0> ---00000 EF0h RB1PPS -- -- -- RB1PPS<4:0> ---00000 EEFh RB0PPS -- -- -- RB0PPS<4:0> ---00000 EEEh RA7PPS -- -- -- RA7PPS<4:0> ---00000 EEDh RA6PPS -- -- -- RA6PPS<4:0> ---00000 EECh RA5PPS -- -- -- RA5PPS<4:0> ---00000 EEBh RA4PPS -- -- -- RA4PPS<4:0> ---00000 EEAh RA3PPS -- -- -- RA3PPS<4:0> ---00000 EE9h RA2PPS -- -- -- RA2PPS<4:0> ---00000 EE8h RA1PPS -- -- -- RA1PPS<4:0> ---00000 EE7h RA0PPS -- -- -- RA0PPS<4:0> ---00000 EE6h PMD5 -- -- -- -- EE5h PMD4 UART2MD UART1MD MSSP2MD MSSP1MD -- EE4h PMD3 -- -- -- -- PWM4MD EE3h PMD2 -- DACMD ADCMD -- -- -- -- -- DSMMD -------0 -- -- CWG1MD 0000---0 PWM3MD CCP2MD CCP1MD ----0000 CMP2MD CMP1MD ZCDMD -00--000 EE2h PMD1 -- TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD -0000000 EE1h PMD0 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD 00x00000 EE0h BORCON SBOREN -- -- -- -- -- -- BORRDY 1------q EDFh VREGCON(1) -- -- -- -- -- -- VREGPM Reserved ------01 EDEh OSCFRQ -- -- -- -- EDDh OSCTUNE EDCh OSCEN EDBh HFFRQ<3:0> ----1111 -- -- EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN -- -- 000000-- OSCSTAT EXTOR HFOR MFOR LFOR SOR ADOR -- PLLR qqqqqq-q EDAh OSCCON3 CSWHOLD SOSCPWR -- ORDY NOSCR -- -- -- 00-00--- ED9h OSCCON2 -- Legend: Note 1: 2: HFTUN<5:0> COSC<2:0> --100000 CDIV<3:0> -qqqqqqq x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 113 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 NOSC<2:0> Bit 1 Bit 0 ED8h OSCCON1 -- ED7h CPUDOZE IDLEN ED6h WDTTMR ED5h WDTPSH PSCNT<7:0> 00000000 ED4h WDTPSL PSCNT<15:8> 00000000 ED3h WDTCON1 -- ED2h WDTCON0 -- -- ED1h PIR7 SCANIF CRCIF NVMIF -- -- -- ED0h PIR6 -- -- -- -- -- -- DOZEN ROI NDIV<3:0> Value on POR, BOR DOE -- DOZE<2:0> WDTTMR<4:0> STATE WDTCS<2:0> -qqqqqqq -- 0000-000 PSCNT<17:16> WINDOW<2:0> WDTPS<4:0> xxxxx000 -qqq-qqq SEN --qqqqq0 -- CWG1IF 000----0 CCP2IF CCP1IF ------00 ECFh PIR5 -- -- -- -- -- TMR5GIF TMR3GIF TMR1GIF -----000 ECEh PIR4 -- -- TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF --000000 ECDh PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 00000000 ECCh PIR2 HLVDIF ZCDIF -- -- -- -- C2IF C1IF 00----00 ECBh PIR1 OSCFIF CSWIF -- -- -- -- ADTIF ADIF 00----00 ECAh PIR0 -- -- TMR0IF IOCIF -- INT2IF INT1IF INT0IF --00-000 EC9h PIE7 SCANIE CRCIE NVMIE -- -- -- -- CWG1IE 000----0 EC8h PIE6 -- -- -- -- -- -- CCP2IE CCP1IE ------00 EC7h PIE5 -- -- -- -- -- TMR5GIE TMR3GIE TMR1GIE -----000 EC6h PIE4 -- -- TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE --000000 EC5h PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 00000000 EC4h PIE2 HLVDIE ZCDIE -- -- -- -- C2IE C1IE 00----00 EC3h PIE1 OSCFIE CSWIE -- -- -- -- ADTIE ADIE 00----00 EC2h PIE0 -- -- TMR0IE IOCIE -- INT2IE INT1IE INT0IE --00-000 EC1h IPR7 SCANIP CRCIP NVMIP -- -- -- -- CWG1IP 111----1 EC0h IPR6 -- -- -- -- -- -- CCP2IP CCP1IP ------11 EBFh IPR5 -- -- -- -- -- TMR5GIP TMR3GIP TMR1GIP -----111 EBEh IPR4 -- -- TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP --111111 EBDh IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 11111111 EBCh IPR2 HLVDIP ZCDIP -- -- -- -- C2IP C1IP 11----11 EBBh IPR1 OSCFIP CSWIP -- -- -- -- ADTIP ADIP 11----11 EBAh IPR0 -- -- TMR0IP IOCIP -- INT2IP INT1IP INT0IP --11-111 EB9h SSP1SSPPS -- -- -- SSPSSPPS<4:0> ---00101 EB8h SSP1DATPPS -- -- -- SSPDATPPS<4:0> ---10100 EB7h SSP1CLKPPS -- -- -- SSPCLKPPS<4:0> ---10011 EB6h TX1PPS -- -- -- TXPPS<4:0> ---10110 EB5h RX1PPS -- -- -- RXPPS<4:0> ---10111 EB4h MDSRCPPS -- -- -- MDSRCPPS<4:0> ---00101 EB3h MDCARHPPS -- -- -- MDCARHPPS<4:0> ---00100 EB2h MDCARLPPS -- -- -- MDCARLPPS<4:0> ---00011 Legend: Note 1: 2: x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 114 PIC18(L)F27/47K40 TABLE 10-5: Address REGISTER FILE SUMMARY FOR PIC18(L)F27/47K40 DEVICES (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR EB1h CWGINPPS -- -- -- CWGINPPS<4:0> ---01000 EB0h CCP2PPS -- -- -- CCP2PPS<4:0> ---10001 EAFh CCP1PPS -- -- -- CCP1PPS<4:0> ---10010 EAEh ADACTPPS -- -- -- ADACTPPS<4:0> ---01100 EADh T6INPPS -- -- -- T6INPPS<4:0> ---01111 EACh T4INPPS -- -- -- T4INPPS<4:0> ---10101 EABh T2INPPS -- -- -- T2INPPS<4:0> ---10011 EAAh T5GPPS -- -- -- T5GPPS<4:0> ---01100 EA9h T5CKIPPS -- -- -- T5CKIPPS<4:0> ---10010 EA8h T3GPPS -- -- -- T3GPPS<4:0> ---10000 EA7h T3CKIPPS -- -- -- T3CKIPPS<4:0> ---10000 EA6h T1GPPS -- -- -- T1GPPS<4:0> ---01101 EA5h T1CKIPPS -- -- -- T1CKIPPS<4:0> ---10000 EA4h T0CKIPPS -- -- -- T0CKIPPS<4:0> ---00100 EA3h INT2PPS -- -- -- INT2PPS<4:0> ---01010 EA2h INT1PPS -- -- -- INT1PPS<4:0> ---01001 EA1h INT0PPS -- -- -- INT0PPS<4:0> ---01000 EA0h PPSLOCK -- -- -- E9Fh BAUD2CON ABDOVF RCIDL -- SCKP BRG16 E9Eh TX2STA CSRC TX9 TXEN SYNC SENDB E9Dh RC2STA SPEN RX9 SREN CREN ADDEN FERR -- -- -- -- PPSLOCKED -------0 -- WUE ABDEN 01-00-00 BRGH TRMT TX9D 00000010 OERR RX9D 00000000 E9Ch SP2BRGH EUSART2 Baud Rate Generator, High Byte 00000000 E9Bh SP2BRGL EUSART2 Baud Rate Generator, Low Byte 00000000 E9Ah TX2REG EUSART2 Transmit Register 00000000 E99h RC2REG EUSART2 Receive Register 00000000 E98h SSP2CON3 E97h E96h E95h ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 00000000 SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 00000000 SSP2CON1 WCOL SSPOV SSPEN CKP SSP2STAT SMP CKE D/A P SSPM<3:0> S R/W UA 00000000 BF 00000000 E94h SSP2MSK MSK<7:0> 11111111 E93h SSP2ADD ADD<7:0> 00000000 E92h SSP2BUF E91h SSP2SSPPS -- -- -- SSPSSPPS<4:0> ---00101 E90h SSP2DATPPS -- -- -- SSPDATPPS<4:0> ---10100 E8Fh SSP2CLKPPS -- -- -- SSPCLKPPS<4:0> ---10011 E8Eh TX2PPS -- -- -- TXPPS<4:0> ---10110 E8Dh RX2PPS -- -- -- RXPPS<4:0> ---10111 E8Ch - E7Eh -- Legend: Note 1: 2: BUF<7:0> xxxxxxxx Unimplemented -- x = unknown, u = unchanged, -- = unimplemented, q = value depends on condition Not available on LF devices. Not available on PIC18(L)F27K40 (28-pin variants). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 115 PIC18(L)F27/47K40 10.4.5 STATUS REGISTER The STATUS register, shown in Register 10-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Section 35.0 "Instruction Set Summary" and Table 35-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 116 PIC18(L)F27/47K40 10.5 Register Definitions: Status REGISTER 10-2: STATUS: STATUS REGISTER U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u -- TO PD N OV Z DC C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as `0' bit 6 TO: Time-Out bit 1 = Set at power-up or by execution of CLRWDT or SLEEP instruction 0 = A WDT time-out occurred bit 5 PD: Power-Down bit 1 = Set at power-up or by execution of CLRWDT instruction 0 = Set by execution of the SLEEP instruction bit 4 N: Negative bit used for signed arithmetic (2's complement); indicates if the result is negative, (ALU MSb = 1). 1 = The result is negative 0 = The result is positive bit 3 OV: Overflow bit used for signed arithmetic (2's complement); indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for current signed arithmetic operation 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1,2) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. 2: For Rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the Source register. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 117 PIC18(L)F27/47K40 10.6 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 10.7 "Data Memory and the Extended Instruction Set" for more information. While the program memory can be addressed in only one way - through the program counter - information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. 10.6.3 An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 10.7.1 "Indexed Addressing with Literal Offset". 10.6.1 The Access RAM bit `a' determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 10.4.1 "Bank Select Register (BSR)") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. Indirect addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are to be read or written. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for indirect addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 10-5. EXAMPLE 10-5: DIRECT ADDRESSING Direct addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 100h ; POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H, 1 ; All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue NEXT 10.6.2 INDIRECT ADDRESSING LFSR CLRF In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of direct addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 10.4.3 "General Purpose Register File") or a location in the Access Bank (Section 10.4.2 "Access Bank") as the data source for the instruction. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 118 PIC18(L)F27/47K40 10.6.3.1 FSR Registers and the INDF Operand 10.6.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore, the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers which cannot be directly read or written. Accessing these registers actually accesses the location to which the associated FSR register pair points, and also performs a specific action on the FSR value. They are: * POSTDEC: accesses the location to which the FSR points, then automatically decrements the FSR by 1 afterwards * POSTINC: accesses the location to which the FSR points, then automatically increments the FSR by 1 afterwards * PREINC: automatically increments the FSR by one, then uses the location to which the FSR points in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the location to which the result points in the operation. Indirect addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as "virtual" registers; they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. Because indirect addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 10-6: FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In this context, accessing an INDF register uses the value in the associated FSR register without changing it. Similarly, accessing a PLUSW register gives the FSR value an offset by that in the W register; however, neither W nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR register. INDIRECT ADDRESSING 000h Using an instruction with one of the indirect addressing registers as the operand.... Bank 0 ADDWF, INDF1, 1 100h Bank 1 200h ...uses the 12-bit address stored in the FSR pair associated with that register.... 300h FSR1H:FSR1L 7 0 x x x x 1 1 1 0 7 0 Bank 2 Bank 3 through Bank 13 1 1 0 0 1 1 0 0 ...to determine the data memory location to be used in that operation. E00h In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. Bank 14 F00h FFFh Bank 15 Data Memory 2016 Microchip Technology Inc. Preliminary DS40001844B-page 119 PIC18(L)F27/47K40 Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of indexed addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 10.6.3.3 Operations by FSRs on FSRs Indirect addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to either the INDF2 or POSTDEC2 register will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. Similarly, operations by indirect addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 10.7 Data Memory and the Extended Instruction Set Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. 10.7.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of indirect addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of indexed addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0) and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in direct addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. 10.7.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use direct addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is `1'), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is shown in Figure 10-7. Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 35.2.1 "Extended Instruction Syntax". What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also remain unchanged. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 120 PIC18(L)F27/47K40 FIGURE 10-7: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When `a' = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode. 000h 060h Bank 0 100h 00h Bank 1 through Bank 14 60h Valid range for `f' Access RAM F00h FFh Bank 15 F60h SFRs FFFh When `a' = 0 and f5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'. When `a' = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. Data Memory 000h 060h Bank 0 100h 001001da ffffffff Bank 1 through Bank 14 FSR2H FSR2L F00h Bank 15 F60h SFRs FFFh Data Memory BSR 00000000 000h 060h Bank 0 100h Bank 1 through Bank 14 001001da ffffffff F00h Bank 15 F60h SFRs FFFh 2016 Microchip Technology Inc. Data Memory Preliminary DS40001844B-page 121 PIC18(L)F27/47K40 10.7.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 10.4.2 "Access Bank"). An example of Access Bank remapping in this addressing mode is shown in Figure 10-8. 10.8 PIC18 Instruction Execution and the Extended Instruction Set Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in Section 35.2 "Extended Instruction Set". Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is `1') will continue to use direct addressing as before. FIGURE 10-8: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING Example Situation: ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). 000h Bank 0 100h 120h 17Fh 200h Bank 1 Window 00h Bank 1 Bank 1 "Window" 5Fh 60h Special File Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 2 through Bank 14 Bank 0 addresses below 5Fh can still be addressed by using the BSR. SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory 2016 Microchip Technology Inc. Preliminary DS40001844B-page 122 PIC18(L)F27/47K40 11.0 NONVOLATILE MEMORY (NVM) CONTROL Nonvolatile Memory (NVM) is separated into two types: Program Flash Memory (PFM) and Data EEPROM Memory. PFM, Data EEPROM, User IDs and Configuration bits can all be accessed using the NVMREG<1:0> bits of the NVMCON1 register. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. TABLE 11-1: NVM can be protected in two ways, by either code protection or write protection. Code protection (CP and CPD bits in Configuration Word 5L) disables access, reading and writing to both PFM and Data EEPROM Memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all nonvolatile memory, Configuration bits and User IDs. Write protection prohibits self-write and erase to a portion or all of the PFM, as defined by the WRT bits of Configuration Word 4H. Write protection does not affect a device programmer's ability to read, write or erase the device. NVM ORGANIZATION AND ACCESS INFORMATION Memory PC<20:0> ICSPTM Addr<21:0> TBLPTR<21:0> NVMADDR<9:0> User Flash Memory (PFM) User IDs(2) Reserved Configuration Reserved Execution User Access CPU Execution NVMREG TABLAT NVMDAT 00 0000h *** 01 FFFFh Read 10 Read/ Write(1) --(3) 20 0000h *** 20 000Fh No Access x1 Read/ Write --(3) 20 0010h 2F FFFFh 30 0000h *** 30 000Bh 30 000Ch 30 FFFFh User Data Memory (Data EEPROM) 31 0000h *** 31 03FFh Reserved 32 0000h Revision ID/ Device ID 3F FFFCh *** 3F FFFFh 3F FFFBh --(3) No Access No Access x1 00 --(3) Read/ Write --(3) No Access No Access --(3) --(3) No Access No Access Read/ Write x1 Read --(3) Note 1: Subject to Memory Write Protection settings. 2: User IDs are eight words ONLY. There is no code protection, table read protection or write protection implemented for this region. 3: Reads as `0', writes clear the WR bit and WRERR bit is set. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 123 PIC18(L)F27/47K40 11.1 Program Flash Memory The Program Flash Memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed one byte at a time. A write to program memory or program memory erase is executed on blocks of n bytes at a time. Refer to Table 11-3 for write and erase block sizes. A Bulk Erase operation cannot be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. rows. A row is the minimum size that can be erased by user software. Refer to Table 11-3 for the row sizes for the these devices. After a row has been erased, all or a portion of this row can be programmed. Data to be written into the program memory row is written to 6-bit wide data write latches. These latches are not directly accessible, but may be loaded via sequential writes to the TABLAT register. Note: A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. It is important to understand the PFM memory structure for erase and programming operations. Program memory word size is 16 bits wide. PFM is arranged in TABLE 11-2: Device FLASH MEMORY ORGANIZATION BY DEVICE Row Erase Size (Words) Write Latches (Bytes) 32 64 PIC18(L)F45K40 PIC18(L)F26K40 PIC18(L)F46K40 PIC18(L)F27K40 PIC18(L)F47K40 To modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, the new data and retained data can be written into the write latches to reprogram the row of PFM. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations Program Flash Memory (Words) Data Memory (Bytes) 16384 256 32768 1024 64 2016 Microchip Technology Inc. 128 Preliminary 65536 DS40001844B-page 124 PIC18(L)F27/47K40 11.1.1 TABLE READS AND TABLE WRITES In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is eight bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). The table read operation retrieves one byte of data directly from program memory and places it into the TABLAT register. Figure 11-1 shows the operation of a table read. FIGURE 11-1: The table write operation stores one byte of data from the TABLAT register into a write block holding register. The procedure to write the contents of the holding registers into program memory is detailed in Section 11.1.6 "Writing to Program Flash Memory". Figure 11-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. Tables containing data, rather than program instructions, are not required to be word aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned. TABLE READ OPERATION Instruction: TBLRD* Program Memory Table Pointer(1) TBLPTRH TBLPTRU Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. FIGURE 11-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Holding Registers Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR<MSBs>) Note 1: During table writes the Table Pointer does not point directly to program memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written. The process for writing the holding registers to the program memory array is discussed in Section 11.1.6 "Writing to Program Flash Memory". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 125 PIC18(L)F27/47K40 11.1.2 CONTROL REGISTERS 11.1.2.3 Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the following registers: * * * * NVMCON1 register NVMCON2 register TABLAT register TBLPTR registers 11.1.2.1 NVMCON1 and NVMCON2 Registers The NVMCON1 register (Register 11-1) is the control register for memory accesses. The NVMCON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading NVMCON2 will read all `0's. The NVMREG<1:0> control bits determine if the access will be to Data EEPROM Memory locations. PFM locations or User IDs, Configuration bits, Rev ID and Device ID. When NVMREG<1:0> = 00, any subsequent operations will operate on the Data EEPROM Memory. When NVMREG<1:0> = 10, any subsequent operations will operate on the program memory. When NVMREG<1:0> = x1, any subsequent operations will operate on the Configuration bits, User IDs, Rev ID and Device ID. The FREE bit allows the program memory erase operation. When the FREE bit is set, an erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. This bit is applicable only to the PFM and not to data EEPROM. When set, the WREN bit will allow a program/erase operation. The WREN bit is cleared on power-up. The WRERR bit is set by hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is successfully complete. The WR control bit initiates erase/write cycle operation when the NVMREG<1:0> bits point to the Data EEPROM Memory location, and it initiates a write operation when the NVMREG<1:0> bits point to the PFM location. The WR bit cannot be cleared by firmware; it can only be set by firmware. Then the WR bit is cleared by hardware at the completion of the write operation. TBLPTR - Table Pointer Register The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The loworder 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the Device ID, the User ID and the Configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations on the TBLPTR affect only the low-order 21 bits. 11.1.2.4 Table Pointer Boundaries TBLPTR is used in reads, writes and erases of the Program Flash Memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register. When a TBLWT is executed the byte in the TABLAT register is written, not to Flash memory but, to a holding register in preparation for a program memory write. The holding registers constitute a write block which varies depending on the device (see Table 11-3).The 3, 4, or 5 LSbs of the TBLPTRL register determine which specific address within the holding register block is written to. The MSBs of the Table Pointer have no effect during TBLWT operations. When a program memory write is executed the entire holding register block is written to the Flash memory at the address determined by the MSbs of the TBLPTR. The 3, 4, or 5 LSBs are ignored during Flash memory writes. For more detail, see Section 11.1.6 "Writing to Program Flash Memory". Figure 11-3 describes the relevant boundaries of TBLPTR based on Program Flash Memory operations. The NVMIF Interrupt Flag bit of the PIR7 register is set when the write is complete. The NVMIF flag stays set until cleared by firmware. 11.1.2.2 TABLAT - Table Latch Register The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 126 PIC18(L)F27/47K40 TABLE 11-3: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 11-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 TABLE ERASE/WRITE TBLPTR<21:n+1>(1) 7 TBLPTRL 0 TABLE WRITE TBLPTR<n:0>(1) TABLE READ - TBLPTR<21:0> Note 1: Refer to Table 11-3 for the row size values. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 127 PIC18(L)F27/47K40 11.1.3 READING THE PROGRAM FLASH MEMORY The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 11-4: The CPU operation is suspended during the read, and it resumes immediately after. From the user point of view, TABLAT is valid in the next instruction cycle. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 11-4 shows the interface between the internal program memory and the TABLAT. READS FROM PROGRAM FLASH MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 Instruction Register (IR) EXAMPLE 11-1: FETCH TBLRD TBLPTR = xxxxx0 TABLAT Read Register READING A PROGRAM FLASH MEMORY WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVF MOVWF TBLRD*+ MOVFW MOVF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD 2016 Microchip Technology Inc. ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data Preliminary DS40001844B-page 128 PIC18(L)F27/47K40 FIGURE 11-5: PROGRAM FLASH MEMORY READ FLOWCHART Rev. 10-000046B 8/7/2015 Start Read Operation Select PFM (NVMREG<1:0> = 0x10) Select Word Address (TBLPTR registers) Initiate Read operation (TBLRD) Data read now in TABLAT End Read Operation 2016 Microchip Technology Inc. Preliminary DS40001844B-page 129 PIC18(L)F27/47K40 11.1.4 NVM UNLOCK SEQUENCE FIGURE 11-6: The unlock sequence is a mechanism that protects the NVM from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: * * * * * NVM UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence PFM Row Erase Write of PFM write latches to PFM memory Write of PFM write latches to User IDs Write to Data EEPROM Memory Write to Configuration Words Write 55h to NVMCON2 The unlock sequence consists of the following steps and must be completed in order: * Write 55h to NVMCON2 * Write AAh to NMVCON2 * Set the WR bit of NVMCON1 Write AAh to NVMCON2 Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume with the next instruction. Initiate Write or Erase Operation (WR = 1) Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. EXAMPLE 11-2: End Unlock Operation NVM UNLOCK SEQUENCE BCF INTCON,GIE BANKSEL NVMCON1 ; Recommended so sequence is not interrupted BSF NVMCON1,WREN ; Enable write/erase MOVLW 55h ; Load 55h MOVWF NVMCON2 ; Step 1: Load 55h into NVMCON2 MOVLW AAh ; Step 2: Load W with AAh MOVWF NVMCON2 ; Step 3: Load AAh into NVMCON2 BSF INTCON1,WR ; Step 4: Set WR bit to begin write/erase BSF INTCON,GIE ; Re-enable interrupts Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown. If the timing of the steps 1 to 4 is corrupted by an interrupt or a debugger Halt, the action will not take place. 2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 130 PIC18(L)F27/47K40 11.1.5 ERASING PROGRAM FLASH MEMORY 11.1.5.1 The minimum erase block is 32 or 64 words (refer to Table 11-3). Only through the use of an external programmer, or through ICSPTM control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. For example, when initiating an erase sequence from a microcontroller with erase row size of 32 words, a block of 32 words (64 bytes) of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored. The NVMCON1 register commands the erase operation. The NVMREG<1:0> bits must be set to point to the Program Flash Memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The NVM unlock sequence described in Section 11.1.4 "NVM Unlock Sequence" should be used to guard against accidental writes. This is sometimes referred to as a long write. A long write is necessary for erasing the internal Flash. Instruction execution is halted during the long write cycle. The long write is terminated by the internal programming timer. Program Flash Memory Erase Sequence The sequence of events for erasing a block of internal program memory is: 1. NVMREG bits of the NVMCON1 register point to PFM Set the FREE and WREN bits of the NVMCON1 register Perform the unlock sequence as described in Section 11.1.4 "NVM Unlock Sequence" 2. 3. If the PFM address is write-protected, the WR bit will be cleared and the erase operation will not take place, WRERR is signaled in this scenario. The operation erases the memory row indicated by masking the LSBs of the current TBLPTR. While erasing PFM, CPU operation is suspended and it resumes when the operation is complete. Upon completion the WR bit is cleared in hardware, the NVMIF is set and an interrupt will occur if the NVMIE bit is also set. Write latch data is not affected by erase operations and WREN will remain unchanged. Note 1: If a write or erase operation is terminated by an unexpected event, WRERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. 2: WRERR is set if WR is written to `1' while TBLPTR points to a write-protected address. 3: WRERR is set if WR is written to `1' while TBLPTR points to an invalid address location (Table 10-1 and Table 11-1). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 131 PIC18(L)F27/47K40 EXAMPLE 11-3: ERASING A PROGRAM FLASH MEMORY BLOCK ; This sample row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in variables TBLPTR register ; 2. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F) MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BCF BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF NVMCON1, NVMREG0 NVMCON1, NVMREG1 NVMCON1, WREN NVMCON1, FREE INTCON, GIE 55h NVMCON2 AAh NVMCON2 NVMCON1, WR INTCON, GIE ; ; ; ; ; ERASE_BLOCK Required Sequence 2016 Microchip Technology Inc. point to Program Flash Memory access Program Flash Memory enable write to memory enable block Erase operation disable interrupts ; write 55h ; write AAh ; start erase (CPU stalls) ; re-enable interrupts Preliminary DS40001844B-page 132 PIC18(L)F27/47K40 FIGURE 11-7: PFM ROW ERASE FLOWCHART Start Erase Operation Select Memory: PFM (NVMREGS<1:0> = 10) Load Table Pointer register with address of the block being erased Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Disable Interrupts (GIE = 0) Unlock Sequence (Figure 11-6) CPU stalls while Erase operation completes (2 ms typical) Enable Interrupts (GIE = 1) Disable Write/Erase Operation (WREN = 0) 11.1.6 The programming write block size is described in Table 11-3. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are only as many holding registers as there are bytes in a write block. Refer to Table 11-3 for write latch size. Since the table latch (TABLAT) is only a single byte, the TBLWT instruction needs to be executed multiple times for each programming operation. The write protection state is ignored for this operation. All of the table write operations will essentially be short writes because only the holding registers are written. NVMIF is not affected while writing to the holding registers. After all the holding registers have been written, the programming operation of that block of memory is started by configuring the NVMCON1 register for a program memory write and performing the long write sequence. If the PFM address in the TBLPTR is write-protected or if TBLPTR points to an invalid location, the WR bit is cleared without any effect and the WREER is signaled. The long write is necessary for programming the internal Flash. CPU operation is suspended during a long write cycle and resumes when the operation is complete. The long write operation completes in one instruction cycle. When complete, WR is cleared in hardware and NVMIF is set and an interrupt will occur if NVMIE is also set. The latched data is reset to all `1s'. WREN is not changed. The internal programming timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note: End Erase Operation 2016 Microchip Technology Inc. WRITING TO PROGRAM FLASH MEMORY Preliminary The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes, it is not necessary to load all holding registers before executing a long write operation. DS40001844B-page 133 PIC18(L)F27/47K40 FIGURE 11-8: TABLE WRITES TO PROGRAM FLASH MEMORY TABLAT Write Register 8 8 TBLPTR = xxxx00 8 TBLPTR = xxxx01 Holding Register TBLPTR = xxxx02 Holding Register Holding Register 8 TBLPTR = xxxxYY(1) Holding Register Program Memory Note 1: Refer to Table 11-3 for number of holding registers (e.g., YY = 3F for 64 holding registers). 11.1.6.1 Program Flash Memory Write Sequence The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Read appropriate number of bytes into RAM. Refer to Table 11-2 for Write latch size. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the block erase procedure. Load Table Pointer register with address of first byte being written. Write the n-byte block into the holding registers with auto-increment. Refer to Table 11-2 for Write latch size. Set NVMREG<1:0> bits to point to program memory. Clear FREE bit and set WREN bit in NVMCON1 register. Disable interrupts. Execute the unlock sequence (see Section 11.1.4 "NVM Unlock Sequence"). WR bit is set in NVMCON1 register. The CPU will stall for the duration of the write (about 2 ms using internal timer). Re-enable interrupts. Verify the memory (table read). This procedure will require about 6 ms to update each write block of memory. An example of the required code is given in Example 11-4. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the bytes in the holding registers. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 134 PIC18(L)F27/47K40 EXAMPLE 11-4: WRITING TO PROGRAM FLASH MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL NVMCON1, NVMREG0 NVMCON1, NVMREG1 NVMCON1, WREN NVMCON1, FREE INTCON, GIE 55h NVMCON2 AAh NVMCON2 NVMCON1, WR INTCON, GIE ; load TBLPTR with the base ; address of the memory block ; point to buffer ; Load TBLPTR with the base ; address of the memory block READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat MODIFY_WORD ; update buffer word ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF WRITE_BUFFER_BACK MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L BlockSize COUNTER D'64'/BlockSize COUNTER2 2016 Microchip Technology Inc. ; ; ; ; ; point to Program Flash Memory point to Program Flash Memory enable write to memory enable Erase operation disable interrupts ; write 55h ; ; ; ; ; write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer ; number of bytes in holding register ; number of write blocks in 64 bytes Preliminary DS40001844B-page 135 PIC18(L)F27/47K40 EXAMPLE 11-4: WRITING TO PROGRAM FLASH MEMORY (CONTINUED) WRITE_BYTE_TO_HREGS MOVF MOVWF TBLWT+* DECFSZ BRA PROGRAM_MEMORY BCF BSF BSF BCF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF DCFSZ BRA BSF BCF POSTINC0, W TABLAT COUNTER WRITE_WORD_TO_HREGS NVMCON1, NVMREG0 NVMCON1, NVMREG1 NVMCON1, WREN NVMCON1, FREE INTCON, GIE 55h NVMCON2 0AAh NVMCON2 NVMCON1, WR COUNTER2 WRITE_BYTE_TO_HREGS INTCON, GIE NVMCON1, WREN 2016 Microchip Technology Inc. ; ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until holding registers are full ; ; ; ; ; point to Program Flash Memory point to Program Flash Memory enable write to memory enable write to memory disable interrupts ; write 55h ; write 0AAh ; start program (CPU stall) ; repeat for remaining write blocks ; re-enable interrupts ; disable write to memory Preliminary DS40001844B-page 136 PIC18(L)F27/47K40 FIGURE 11-9: PROGRAM FLASH MEMORY (PFM) WRITE FLOWCHART Rev. 10-000049B 12/4/2015 Start Write Operation Determine number of words to be written into PFM. The number of words cannot exceed the number of words per row (word_cnt) Load the value to write TABLAT Update the word counter (word_cnt--) Select access to PFM locations using NVMREG<1:0> bits Last word to write ? Select Row Address TBLPTR Select Write Operation (FREE = 0) Yes No Write Latches to PFM Disable Interrupts (GIE = 0) Unlock Sequence(1) Disable Interrupts (GIE = 0) CPU stalls while Write operation completes (2 ms typical) Load Write Latches Only Enable Write/Erase Operation (WREN = 1) Unlock Sequence(1) No delay when writing to PFM Latches Re-enable Interrupts (GIE = 1) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Write Operation Increment Address TBLPTR++ 2016 Microchip Technology Inc. Preliminary DS40001844B-page 137 PIC18(L)F27/47K40 11.1.6.2 11.1.6.3 Write Verify Unexpected Termination of Write Operation Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. Since program memory is stored as a full page, the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set which the user can check to decide whether a rewrite of the location(s) is needed. FIGURE 11-10: 11.1.6.4 PROGRAM FLASH MEMORY VERIFY FLOWCHART Rev. 10-000051B 12/4/2015 A write sequence is valid only when both the following conditions are met, this prevents spurious writes which might lead to data corruption. 1. Start Verify Operation 2. This routine assumes that the last row of data written was from an image saved on RAM. This image will be used to verify the data currently stored in PFM Read Operation(1) NVMDAT = RAM image ? Yes The WR bit is gated through the WREN bit. It is suggested to have the WREN bit cleared at all times except during memory writes. This prevents memory writes if the WR bit gets set accidentally. The NVM unlock sequence must be performed each time before a write operation. 11.2 Fail Verify Operation Last word ? Yes End Verify Operation 2016 Microchip Technology Inc. Reading Access The user can read from these blocks by setting the NVMREG bits to 0x01 or 0x11. The user needs to load the address into the TBLPTR registers. Executing a TBLRD after that moves the byte pointed to the TABLAT register. The CPU operation is suspended during the read and resumes after. When read access is initiated on an address outside the parameters listed in Table 11-3, the TABLAT register is cleared, reading back `0's. 11.2.2 No User ID, Device ID and Configuration Word Access When NVMREG<1:0> = 0x01 or 0x11 in the NVMCON1 register, the User ID's, Device ID/ Revision ID and Configuration Words can be accessed. Different access may exist for reads and writes (see Table 11-3). 11.2.1 No Protection Against Spurious Writes Writing Access The WREN bit in NVMCON1 must be set to enable writes. This prevents accidental writes to the CONFIG words due to errant (unexpected) code execution. The WREN bit should be kept clear at all times, except when updating the CONFIG words. The WREN bit is not cleared by hardware. The WR bit will be inhibited from being set unless the WREN bit is set. Preliminary DS40001844B-page 138 PIC18(L)F27/47K40 The user needs to load the TBLPTR and TABLAT register with the address and data byte respectively before executing the write command. An unlock sequence needs to be followed for writing to the USER IDs/ DEVICE IDs/CONFIG words (Section 11.1.4, NVM Unlock Sequence). If WRTC = 0 or if TBLPTR points an invalid address location (see Table 11-3), WR bit is cleared without any effect and WRERR is set. A single CONFIG word byte is written at once and the operation includes an implicit erase cycle for that byte (it is not necessary to set FREE). CPU execution is stalled and at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag bit (NVMIF) is set. The new CONFIG value takes effect when the CPU resumes operation. TABLE 11-4: USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS (NVMREG<1:0> = X1) Address 20 0000h-20 000Fh Function Read Access Write Access User IDs Yes Yes 3F FFFCh-3F FFFFh Revision ID/Device ID Yes No 30 0000h-30 000Bh Configuration Words 1-6 Yes Yes 2016 Microchip Technology Inc. Preliminary DS40001844B-page 139 PIC18(L)F27/47K40 11.3 Data EEPROM Memory 11.3.2 The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, which is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range. Four SFRs are used to read and write to the data EEPROM as well as the program memory. They are: * * * * * NVMCON1 NVMCON2 NVMDAT NVMADRL NVMADRH The EEPROM data memory is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the new data (erase-before-write). The write time is controlled by an internal programming timer; it will vary with voltage and temperature as well as from chip-to-chip. Please refer to the Data EEPROM Memory parameters in Section 37.0 "Electrical Specifications" for limits. NVMADRL AND NVMADRH REGISTERS The NVMADRH:NVMADRL registers are used to address the data EEPROM for read and write operations. 2016 Microchip Technology Inc. Access to the data EEPROM is controlled by two registers: NVMCON1 and NVMCON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. The NVMCON1 register (Register 11-1) is the control register for data and program memory access. Control bits NVMREG<1:0> determine if the access will be to program, Data EEPROM Memory or the User IDs, Configuration bits, Revision ID and Device ID. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The data EEPROM allows byte read and write. When interfacing to the data memory block, NVMDAT holds the 8-bit data for read/write and the NVMADRH:NVMADRL register pair hold the address of the EEPROM location being accessed. 11.3.1 NVMCON1 AND NVMCON2 REGISTERS The WRERR bit is set by hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. The WR control bit initiates write operations. The bit can be set but not cleared by software. It is cleared only by hardware at the completion of the write operation. The NVMIF interrupt flag bit of the PIR7 register is set when the write is complete. It must be cleared by software. Control bits, RD and WR, start read and erase/write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (NVMREG<1:0> = 0x10). Program memory is read using table read instructions. See Section 11.1.1 "Table Reads and Table Writes" regarding table reads. Preliminary DS40001844B-page 140 PIC18(L)F27/47K40 11.3.3 11.3.4 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the NVMADRL and NVMADRH register pair, clear NVMREG<1:0> control bit in NVMCON1 register to access Data EEPROM locations and then set control bit, RD. The data is available on the very next instruction cycle; therefore, the NVMDAT register can be read by the next instruction. NVMDAT will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 11-5. FIGURE 11-11: PROGRAM FLASH MEMORY READ FLOWCHART Start Read Operation Select Memory: Program Flash Memory, EEPROM, Config. Words, User ID (NVMREG) Select Word Address (NVMADRH:NVMADRL) Initiate Read Operation (RD = 1) Data read now in NVMDAT WRITING TO THE DATA EEPROM MEMORY To write an EEPROM data location, the address must first be written to the NVMADRL and NVMADRH register pair and the data written to the NVMDAT register. The sequence in Example 11-6 must be followed to initiate the write cycle. The write will not begin if NVM Unlock sequence, described in Section 11.1.4 "NVM Unlock Sequence", is not exactly followed for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in NVMCON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. After a write sequence has been initiated, NVMCON1, NVMADRL, NVMADRH and NVMDAT cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. Both WR and WREN cannot be set with the same instruction. After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. A single Data EEPROM word is written and the operation includes an implicit erase cycle for that word (it is not necessary to set FREE). CPU execution continues in parallel and at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag bit (NVMIF) is set. The user can either enable this interrupt or poll this bit. NVMIF must be cleared by software. End Read Operation 2016 Microchip Technology Inc. Preliminary DS40001844B-page 141 PIC18(L)F27/47K40 11.3.5 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. EXAMPLE 11-5: DATA EEPROM READ ; Data Memory Address to read BCF NVMCON1, NVMREG0 BCF NVMCON1, NVMREG1 MOVF EE_ADDRL, W MOVWF NVMADRL MOVF EE_ADDRH, W MOVWF NVMADRH BSF NVMCON1, RD MOVF NVMDAT, W EXAMPLE 11-6: ; ; ; ; ; ; ; ; Setup Data EEPROM Access Setup Data EEPROM Access Setup Address low byte Setup Address high byte (if applicable) Issue EE Read W = EE_DATA DATA EEPROM WRITE ; Data Memory Address to write BCF NVMCON1, NVMREG0 BCF NVMCON1, NVMREG1 MOVF EE_ADDRL, W MOVWF NVMADRL MOVF EE_ADDRH, W MOVWF NVMADRH ; Data Memory Value to write MOVF EE_DATA, W MOVWF NVMDAT ; Enable writes BSF NVMCON1, WREN ; Disable interrupts BCF INTCON, GIE ; Required unlock sequence MOVLW 55h MOVWF NVMCON2 MOVLW AAh MOVWF NVMCON2 ; Set WR bit to begin write BSF NVMCON1, WR ; Wait for write to complete BTFSC NVMCON1, WR BRA $-2 ; Enable INT BSF INTCON, GIE ; Disable writes BCF NVMCON1, WREN 2016 Microchip Technology Inc. ; ; ; ; ; ; Setup Data EEPROM access Setup Data EEPROM access Setup Address low byte Setup Address high byte (if applicable) ; ; ; ; ; ; ; ; ; ; ; Preliminary DS40001844B-page 142 PIC18(L)F27/47K40 11.3.6 OPERATION DURING CODEPROTECT Data EEPROM Memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. If the Data EEPROM is write-protected or if NVMADR points an invalid address location, the WR bit is cleared without any effect. WRERR is signaled in this scenario. 11.3.7 PROTECTION AGAINST SPURIOUS WRITE There are conditions when the user may not want to write to the Data EEPROM Memory. To protect against spurious EEPROM writes, various mechanisms have been implemented. On power-up, the WREN bit is cleared. In addition, writes to the EEPROM are blocked during the Power-up Timer period (TPWRT). The unlock sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch or software malfunction. 11.3.8 ERASING THE DATA EEPROM MEMORY Data EEPROM Memory can be erased by writing 0xFF to all locations in the Data EEPROM Memory that needs to be erased. EXAMPLE 11-7: DATA EEPROM REFRESH ROUTINE CLRF CLRF BCF BCF SETF BCF BSF NVMADRL NVMADRH NVMCON1, NVMREG0 NVMCON1, NVMREG1 NVMDAT INTCON, GIE NVMCON1, WREN MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA 0x55 NVMCON2 0xAA NVMCON2 NVMCON1, WR NVMCON1, WR $-2 NVMADRL, F Loop Loop //The following INCF MOVLW CPFSGT BRA BCF BSF ; ; ; ; ; ; ; ; ; ; ; ; ; ; Clear address low byte register Clear address high byte register (if applicable) Set access for EEPROM Set access for EEPROM Load 0xFF to data register Disable interrupts Enable writes Loop to refresh array Initiate unlock sequence Set WR bit to begin write Wait for write to complete ; Increment address low byte ; Not zero, do it again 4 lines of code are not needed if the part doesn't have NVMADRH register NVMADRH, F ; Decrement address high byte 0x03 ; Move 0x03 to working register NVMADRH ; Compare address high byte with working register Loop ; Skip if greater than working register ; Else go back to erase loop NVMCON1, WREN INTCON, GIE 2016 Microchip Technology Inc. ; Disable writes ; Enable interrupts Preliminary DS40001844B-page 143 PIC18(L)F27/47K40 11.4 Register Definitions: Nonvolatile Memory REGISTER 11-1: R/W-0/0 NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER R/W-0/0 NVMREG<1:0> U-0 R/S/HC-0/0 R/W/HS-x/q R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 -- FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit HC = Bit is cleared by hardware x = Bit is unknown -n = Value at POR S = Bit can be set by software, but not cleared `0' = Bit is cleared `1' = Bit is set U = Unimplemented bit, read as `0' bit 7-6 NVMREG<1:0>: NVM Region Selection bit 10 =Access PFM Locations x1 = Access User IDs, Configuration Bits, Rev ID and Device ID 00 = Access Data EEPROM Memory Locations bit 5 Unimplemented: Read as `0' bit 4 FREE: Program Flash Memory Erase Enable bit(1) 1 = Performs an erase operation on the next WR command 0 = The next WR command performs a write operation bit 3 WRERR: Write-Reset Error Flag bit(2,3,4) 1 = A write operation was interrupted by a Reset (hardware set), or WR was written to 1'b1 when an invalid address is accessed (Table 10-1, Table 11-1) or WR was written to 1'b1 when NVMREG<1:0> and address do not point to the same region or WR was written to 1'b1 when a write-protected address is accessed (Table 10-2). 0 = All write operations have completed normally bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase and refresh cycles 0 = Inhibits programming/erasing and user refresh of NVM bit 1 WR: Write Control bit(5,6,7) When NVMREG points to a Data EEPROM Memory location: 1 = Initiates an erase/program cycle at the corresponding Data EEPROM Memory location When NVMREG points to a PFM location: 1 = Initiates the PFM write operation with data from the holding registers 0 = NVM program/erase operation is complete and inactive bit 0 RD: Read Control bit(8) 1 = Initiates a read at address pointed by NVMREG and NVMADR, and loads data into NVMDAT 0 = NVM read operation is complete and inactive Note 1: 2: 3: 4: 5: 6: 7: 8: This can only be used with PFM. This bit is set when WR = 1 and clears when the internal programming timer expires or the write is completed successfully. Bit must be cleared by the user; hardware will not clear this bit. Bit may be written to `1' by the user in order to implement test sequences. This bit can only be set by following the unlock sequence of Section 11.1.4 "NVM Unlock Sequence". Operations are self-timed and the WR bit is cleared by hardware when complete. Once a write operation is initiated, setting this bit to zero will have no effect. The bit can only be set in software. The bit is cleared by hardware when the operation is complete. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 144 PIC18(L)F27/47K40 REGISTER 11-2: R/W-0 NVMCON2: NONVOLATILE MEMORY CONTROL 2 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMCON2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' x = Bit is unknown `0' = Bit is cleared `1' = Bit is set -n = Value at POR bit 7-0 Note 1: NVMCON2<7:0>: Refer to Section 11.1.4 "NVM Unlock Sequence". This register always reads zeros, regardless of data written. Register 11-3: R/W-x/0 NVMADRL: Data EEPROM Memory Address Low R/W-x/0 R/W-x/0 R/W-x/0 R/W-x/0 R/W-x/0 R/W-x/0 R/W-x/0 NVMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' x = Bit is unknown `0' = Bit is cleared `1' = Bit is set -n = Value at POR bit 7-0 NVMADR<7:0>: EEPROM Read Address bits REGISTER 11-4: NVMADRH: DATA EEPROM MEMORY ADDRESS HIGH U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- R/W-x/u bit 7 R/W-x/u NVMADR<9:8> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' x = Bit is unknown `0' = Bit is cleared `1' = Bit is set -n = Value at POR bit 7-2 Unimplemented: Read as `0' bit 1-0 NVMADR<9:8>: EEPROM Read Address bits 2016 Microchip Technology Inc. Preliminary DS40001844B-page 145 PIC18(L)F27/47K40 REGISTER 11-5: R/W-0/0 NVMDAT: DATA EEPROM MEMORY DATA R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 NVMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' x = Bit is unknown `0' = Bit is cleared `1' = Bit is set -n = Value at POR bit 7-0 NVMDAT<7:0>: The value of the data memory word returned from NVMADR after a Read command, or the data written by a Write command. TABLE 11-5: Name NVMCON1 SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 NVMREG<1:0> Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page -- FREE WRERR WREN WR RD 144 NVMCON2 Unlock Pattern NVMADRL NVMADR<7:0> NVMADRH -- -- -- -- -- NVMDAT TBLPTRU -- -- 145 145 -- NVMADR<9:8> NVMDAT<7:0> 145 146 Program Memory Table Pointer (TBLPTR<21:16>) 126* TBLPTRH Program Memory Table Pointer (TBLPTR<15:8>) 126* TBLPTRL Program Memory Table Pointer (TBLPTR<7:0>) 126* TABLAT TABLAT 125* GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE7 SCANIE CRCIE NVMIE -- -- -- -- CWG1IE 185 PIR7 SCANIF CRCIF NVMIF -- -- -- -- CWG1IF 177 SCANIP CRCIP NVMIP -- -- -- -- CWG1IP 193 INTCON IPR7 Legend: -- = unimplemented, read as `0'. Shaded bits are not used during EEPROM access. *Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 146 PIC18(L)F27/47K40 12.0 8x8 HARDWARE MULTIPLIER 12.1 Introduction EXAMPLE 12-1: All PIC18 devices include an 8x8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 12-1. 12.2 MOVF MULWF 8x8 UNSIGNED MULTIPLY ROUTINE ARG1, W ; ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 12-2: 8x8 SIGNED MULTIPLY ROUTINE MOVF ARG1, W MULWF ARG2 BTFSC ARG2, SB SUBWF PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 Operation Example 12-1 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 12-2 shows the sequence to do an 8x8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 12-1: Routine 8x8 unsigned 8x8 signed 16x16 unsigned 16x16 signed PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Multiply Method Program Memory (Words) Time Cycles (Max) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz Without hardware multiply 13 69 4.3 s 6.9 s 27.6 s 69 s Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 s Without hardware multiply 33 91 5.7 s 9.1 s 36.4 s 91 s Hardware multiply 6 6 375 ns 600 ns 2.4 s 6 s Without hardware multiply 21 242 15.1 s 24.2 s 96.8 s 242 s Hardware multiply 28 28 1.8 s 2.8 s 11.2 s 28 s Without hardware multiply 52 254 15.9 s 25.4 s 102.6 s 254 s Hardware multiply 35 40 2.5 s 4.0 s 16.0 s 40 s 2016 Microchip Technology Inc. Preliminary DS40001844B-page 147 PIC18(L)F27/47K40 Example 12-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 12-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>). EQUATION 12-1: RES3:RES0 = = 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVF MULWF 16 x 16 SIGNED MULTIPLY ROUTINE ; ARG1H:ARG1L ARG2H:ARG2L (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) EXAMPLE 12-3: EXAMPLE 12-4: ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ; ; ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : ; ; ; ; ; ; ; ; ; ; ARG1H * ARG2L-> PRODH:PRODL Add cross products Example 12-4 shows the sequence to do a 16 x 16 signed multiply. Equation 12-2 shows the algorithm used. The 32-bit result is stored in four registers (RES<3:0>). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. EQUATION 12-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) + (-1 ARG2H<7> ARG1H:ARG1L 216) + (-1 ARG1H<7> ARG2H:ARG2L 216) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 148 PIC18(L)F27/47K40 13.0 CYCLIC REDUNDANCY CHECK (CRC) MODULE WITH MEMORY SCANNER The Cyclic Redundancy Check (CRC) module provides a software-configurable hardware-implemented CRC checksum generator. This module includes the following features: * * * * * Any standard CRC up to 16 bits can be used Configurable Polynomial Any seed value up to 16 bits can be used Standard and reversed bit order available Augmented zeros can be added automatically or by the user * Memory scanner for fast CRC calculations on program memory user data * Software loadable data registers for communication CRC's 13.1 CRC Module Overview The CRC module provides a means for calculating a check value of program memory. The CRC module is coupled with a memory scanner for faster CRC calculations. The memory scanner can automatically provide data to the CRC module. The CRC module can also be operated by directly writing data to SFRs, without using a scanner. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 149 PIC18(L)F27/47K40 13.2 Register Definitions: CRC and Scanner Control Long bit name prefixes for the CRC and Scanner peripherals are shown in Table 13-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 13-1: Peripheral Bit Name Prefix CRC CRC REGISTER 13-1: CRCCON0: CRC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 R-0 R/W-0/0 U-0 U-0 R/W-0/0 R-0 EN GO BUSY ACCM -- -- SHIFTM FULL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: CRC Enable bit 1 = CRC module is released from Reset 0 = CRC is disabled and consumes no operating current bit 6 GO: CRC Start bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 5 BUSY: CRC Busy bit 1 = Shifting in progress or pending 0 = All valid bits in shifter have been shifted into accumulator and EMPTY = 1 bit 4 ACCM: Accumulator Mode bit 1 = Data is augmented with zeros 0 = Data is not augmented with zeros bit 3-2 Unimplemented: Read as `0' bit 1 SHIFTM: Shift Mode bit 1 = Shift right (LSb) 0 = Shift left (MSb) bit 0 FULL: Data Path Full Indicator bit 1 = CRCDATH/L registers are full 0 = CRCDATH/L registers have shifted their data into the shifter REGISTER 13-2: R/W-0/0 CRCCON1: CRC CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DLEN<3:0> R/W-0/0 R/W-0/0 R/W-0/0 PLEN<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 DLEN<3:0>: Data Length bits Denotes the length of the data word -1 (See Example 13-1) bit 3-0 PLEN<3:0>: Polynomial Length bits Denotes the length of the polynomial -1 (See Example 13-1) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 150 PIC18(L)F27/47K40 REGISTER 13-3: R/W-xx CRCDATH: CRC DATA HIGH BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x DATA<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DATA<15:8>: CRC Input/Output Data bits REGISTER 13-4: R/W-xx CRCDATL: CRC DATA LOW BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x DATA<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DATA<7:0>: CRC Input/Output Data bits Writing to this register fills the shifter. REGISTER 13-5: R/W-0/0 CRCACCH: CRC ACCUMULATOR HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ACC<15:8>: CRC Accumulator Register bits Writing to this register writes to the CRC accumulator register. Reading from this register reads the CRC accumulator. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 151 PIC18(L)F27/47K40 REGISTER 13-6: R/W-0/0 CRCACCL: CRC ACCUMULATOR LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ACC<7:0>: CRC Accumulator Register bits Writing to this register writes to the CRC accumulator register through the CRC write bus. Reading from this register reads the CRC accumulator. REGISTER 13-7: R-0 CRCSHIFTH: CRC SHIFT HIGH BYTE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 SHIFT<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SHIFT<15:8>: CRC Shifter Register bits Reading from this register reads the CRC Shifter. REGISTER 13-8: R-0 CRCSHIFTL: CRC SHIFT LOW BYTE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 SHIFT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 SHIFT<7:0>: CRC Shifter Register bits Reading from this register reads the CRC Shifter. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 152 PIC18(L)F27/47K40 REGISTER 13-9: R/W-x/x CRCXORH: CRC XOR HIGH BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x X<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 X<15:8>: XOR of Polynomial Term XN Enable bits REGISTER 13-10: CRCXORL: CRC XOR LOW BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x U-1 -- X<7:1> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 X<7:1>: XOR of Polynomial Term XN Enable bits bit 0 Unimplemented: Read as `1' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 153 PIC18(L)F27/47K40 REGISTER 13-11: SCANCON0: SCANNER ACCESS CONTROL REGISTER 0 R/W-0/0 R/W/HC-0/0 R-0 R-1 R/W-0/0 U-0 SCANEN SCANGO BUSY INVALID INTM -- R/W-0/0 bit 7 R/W-0/0 MODE<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 SCANEN: Scanner Enable bit(1) 1 = Scanner is enabled 0 = Scanner is disabled, internal states are reset bit 6 SCANGO: Scanner GO bit(2, 3) 1 = When the CRC sends a ready signal, NVM will be accessed according to MDx and data passed to the client peripheral. 0 = Scanner operations will not occur bit 5 BUSY: Scanner Busy Indicator bit(4) 1 = Scanner cycle is in process 0 = Scanner cycle is complete (or never started) bit 4 INVALID: Scanner Abort Signal bit 1 = SCANLADRL/H/U has incremented to an invalid address(6) or the scanner was not setup correctly(7) 0 = SCANLADRL/H/U points to a valid address bit 3 INTM: NVM Scanner Interrupt Management Mode Select bit If MODE = 10: This bit is ignored If MODE = 01 (CPU is stalled until all data is transferred): 1 = SCANGO is overridden (to zero) during interrupt operation; scanner resumes after returning from interrupt 0 = SCANGO is not affected by interrupts, the interrupt response will be affected If MODE = 00 or 11: 1 = SCANGO is overridden (to zero) during interrupt operation; scan operations resume after returning from interrupt 0 = Interrupts do not prevent NVM access bit 2 Unimplemented: Read as `0' bit 1-0 MODE<1:0>: Memory Access Mode bits(5) 11 = Triggered mode 10 = Peek mode 01 = Burst mode 00 = Concurrent mode Note 1: 2: 3: 4: 5: 6: 7: Setting SCANEN = 0 (SCANCON0 register) does not affect any other register content. This bit is cleared when LADR > HADR (and a data cycle is not occurring). If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response. BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal. See Table 13-2 for more detailed information. An invalid address can occur when the entire range of PFM is scanned and the value of LADR rolls over. An invalid address can also occur if the value in the Scan Low address registers points to a location that is not mapped in the memory map of the device. CRCEN and CRCGO bits must be set before setting SCANGO bit. Refer to Section 13.9 "Program Memory Scan Configuration". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 154 PIC18(L)F27/47K40 REGISTER 13-12: SCANLADRU: SCAN LOW ADDRESS UPPER BYTE REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 (1,2) LADR<21:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 LADR<21:16>: Scan Start/Current Address bits(1,2) Upper bits of the current address to be fetched from, value increments on each fetch of memory. Note 1: 2: Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. REGISTER 13-13: SCANLADRH: SCAN LOW ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 LADR<15:8>(1, 2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared LADR<15:8>: Scan Start/Current Address bits(1, 2) Most Significant bits of the current address to be fetched from, value increments on each fetch of memory. bit 7-0 Note 1: 2: Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 155 PIC18(L)F27/47K40 REGISTER 13-14: SCANLADRL: SCAN LOW ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 LADR<7:0>(1, 2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared LADR<7:0>: Scan Start/Current Address bits(1, 2) Least Significant bits of the current address to be fetched from, value increments on each fetch of memory bit 7-0 Note 1: 2: Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. REGISTER 13-15: SCANHADRU: SCAN HIGH ADDRESS UPPER BYTE REGISTER U-0 U-0 -- -- R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 HADR<21:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 HADR<21:16>: Scan End Address bits(1, 2) Upper bits of the address at the end of the designated scan Note 1: 2: Registers SCANHADRU/H/L form a 22-bit value but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 156 PIC18(L)F27/47K40 REGISTER 13-16: SCANHADRH: SCAN HIGH ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 HADR<15:8>(1, 2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HADR<15:8>: Scan End Address bits(1, 2) Most Significant bits of the address at the end of the designated scan bit 7-0 Note 1: 2: Registers SCANHADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. REGISTER 13-17: SCANHADRL: SCAN HIGH ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 HADR<7:0>(1, 2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HADR<7:0>: Scan End Address bits(1, 2) Least Significant bits of the address at the end of the designated scan bit 7-0 Note 1: 2: Registers SCANHADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access; registers should only be read or written while SCANGO = 0 (SCANCON0 register). While SCANGO = 1 (SCANCON0 register), writing to this register is ignored. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 157 PIC18(L)F27/47K40 REGISTER 13-18: SCANTRIG: SCAN TRIGGER SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TSEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 TSEL<3:0>: Scanner Data Trigger Input Selection bits 1111-1001 = Reserved 1000 = TMR6_postscaled 0111 = TMR5_output 0110 = TMR4_postscaled 0101 = TMR3_output 0100 = TMR2_postscaled 0011 = TMR1_output 0010 = TMR0_output 0001 = CLKREF_output 0000 = LFINTOSC 2016 Microchip Technology Inc. Preliminary DS40001844B-page 158 PIC18(L)F27/47K40 13.3 CRC Functional Overview The CRC module can be used to detect bit errors in the Flash memory using the built-in memory scanner or through user input RAM memory. The CRC module can accept up to a 16-bit polynomial with up to a 16-bit seed value. A CRC calculated check value (or checksum) will then be generated into the CRCACC<15:0> registers for user storage. The CRC module uses an XOR shift register implementation to perform the polynomial division required for the CRC calculation. EXAMPLE 13-1: CRC EXAMPLE Rev. 10-000206A 1/8/2014 CRC-16-ANSI x16 + x15 + x2 + 1 (17 bits) Standard 16-bit representation = 0x8005 CRCXORH = 0b10000000 CRCXORL = 0b0000010- (1) Data Sequence: 0x55, 0x66, 0x77, 0x88 DLEN = 0b0111 PLEN = 0b1111 Data entered into the CRC: SHIFTM = 0: 01010101 01100110 01110111 10001000 SHIFTM = 1: 10101010 01100110 11101110 00010001 Check Value (ACCM = 1): SHIFTM = 0: 0x32D6 CRCACCH = 0b00110010 CRCACCL = 0b11010110 SHIFTM = 1: 0x6BA2 CRCACCH = 0b01101011 CRCACCL = 0b10100010 Note 1: Bit 0 is unimplemented. The LSb of any CRC polynomial is always `1' and will always be treated as a `1' by the CRC for calculating the CRC check value. This bit will be read in software as a `0'. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 159 PIC18(L)F27/47K40 13.4 CRC Polynomial Implementation corresponding CRCXOR<15:0> bits with the value of 0x8004. The actual value is 0x8005 because the hardware sets the LSb to 1. However, the LSb of the CRCXORL register is unimplemented and always reads as `0'. Refer to Example 13-1. Any polynomial can be used. The polynomial and accumulator sizes are determined by the PLEN<3:0> bits. For an n-bit accumulator, PLEN = n-1 and the corresponding polynomial is n+1 bits. Therefore, the accumulator can be any size up to 16 bits with a corresponding polynomial up to 17 bits. The MSb and LSb of the polynomial are always `1' which is forced by hardware. All polynomial bits between the MSb and LSb are specified by the CRCXOR registers. For example, when using CRC16-ANSI, the polynomial is defined as X16+X15+X2+1. The X16 and X0 = 1 terms are the MSb and LSb controlled by hardware. The X15 and X2 terms are specified by setting the EXAMPLE 13-2: CRC LFSR EXAMPLE Rev. 10-000207A 5/27/2014 Linear Feedback Shift Register for CRC-16-ANSI x16 + x15 + x2 + 1 Data in Augmentation Mode ON b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 Data in Augmentation Mode OFF b15 13.5 b14 b13 b12 b11 b10 b9 b8 CRC Data Sources b6 b5 b4 b3 b2 b1 b0 The CRC module can be seeded with an initial value by setting the CRCACC<15:0> registers to the appropriate value before beginning the CRC. Data can be input to the CRC module in two ways: - User data using the CRCDATA registers (CRCDATH and CRCDATL) - Flash using the Program Memory Scanner 13.5.1 To set the number of bits of data, up to 16 bits, the DLEN bits of CRCCON1 must be set accordingly. Only data bits in CRCDATA registers up to DLEN will be used, other data bits in CRCDATA registers will be ignored. Data is moved into the CRCSHIFT as an intermediate to calculate the check value located in the CRCACC registers. The SHIFTM bit is used to determine the bit order of the data being shifted into the accumulator. If SHIFTM is not set, the data will be shifted in MSb first (Big Endian). The value of DLEN will determine the MSb. If SHIFTM bit is set, the data will be shifted into the accumulator in reversed order, LSb first (Little Endian). 2016 Microchip Technology Inc. b7 b0 CRC FROM USER DATA To use the CRC module on data input from the user, the user must write the data to the CRCDAT registers. The data from the CRCDAT registers will be latched into the shift registers on any write to the CRCDATL register. 13.5.2 CRC FROM FLASH To use the CRC module on data located in Flash memory, the user can initialize the Program Memory Scanner as defined in Section 13.9, Program Memory Scan Configuration. Preliminary DS40001844B-page 160 PIC18(L)F27/47K40 13.6 CRC Check Value 13.8 The CRC check value will be located in the CRCACC registers after the CRC calculation has finished. The check value will depend on two mode settings of the CRCCON register: ACCM and SHIFTM. When the ACCM bit is set, the CRC module augments the data with a number of zeros equal to the length of the polynomial to align the final check value. When the ACCM bit is not set, the CRC will stop at the end of the data. A number of zeros equal to the length of the polynomial can then be entered into CRCDAT to find the same check value as augmented mode. Alternatively, the expected check value can be entered at this point to make the final result equal 0. When the CRC check value is computed with the SHIFTM bit set, selecting LSb first, and the ACCM bit is set then the final value in the CRCACC registers will be reversed such that the LSb will be in the MSb position and vice versa. This is the expected check value in bit reversed form. If you are creating a check value to be appended to a data stream then a bit reversal must be performed on the final value to achieve the correct checksum. You can use the CRC to do this reversal by the following method: * * * * Save CRCACC value in user RAM space Clear the CRCACC registers Clear the CRCXOR registers Write the saved CRCACC value to the CRCDAT input The properly oriented check value will be in the CRCACC registers as the result. 13.7 CRC Interrupt The CRC will generate an interrupt when the BUSY bit transitions from 1 to 0. The CRCIF Interrupt Flag bit of the PIR7 register is set every time the BUSY bit transitions, regardless of whether or not the CRC interrupt is enabled. The CRCIF bit can only be cleared in software. The CRC interrupt enable is the CRCIE bit of the PIE7 register. 2016 Microchip Technology Inc. Configuring the CRC The following steps illustrate how to properly configure the CRC. 1. Determine if the automatic program memory scan will be used with the scanner or manual calculation through the SFR interface and perform the actions specified in Section 13.5 "CRC Data Sources", depending on which decision was made. 2. If desired, seed a starting CRC value into the CRCACCH/L registers. 3. Program the CRCXORH/L registers with the desired generator polynomial. 4. Program the DLEN<3:0> bits of the CRCCON1 register with the length of the data word - 1 (refer to Example 13-1). This determines how many times the shifter will shift into the accumulator for each data word. 5. Program the PLEN<3:0> bits of the CRCCON1 register with the length of the polynomial -2 (refer to Example 13-1). 6. Determine whether shifting in trailing zeros is desired and set the ACCM bit of the CRCCON0 register appropriately. 7. Likewise, determine whether the MSb or LSb should be shifted first and write the SHIFTM bit of the CRCCON0 register appropriately. 8. Write the CRCGO bit of the CRCCON0 register to begin the shifting process. 9a. If manual SFR entry is used, monitor the FULL bit of the CRCCON0 register. When FULL = 0, another word of data can be written to the CRCDATH/L registers, keeping in mind that CRCDATH should be written first if the data has more than eight bits, as the shifter will begin upon the CRCDATL register being written. 9b. If the scanner is used, the scanner will automatically stuff words into the CRCDATH/L registers as needed, as long as the SCANGO bit is set. 10a.If using the Flash memory scanner, monitor the SCANIF (or the SCANGO bit) for the scanner to finish pushing information into the CRCDATA registers. After the scanner is completed, monitor the CRCIF (or the BUSY bit) to determine that the CRC has been completed and the check value can be read from the CRCACC registers. If both the interrupt flags are set (or both BUSY and SCANGO bits are cleared), the completed CRC calculation can be read from the CRCACCH/L registers. 10b.If manual entry is used, monitor the CRCIF (or BUSY bit) to determine when the CRCACC registers will hold the check value. Preliminary DS40001844B-page 161 PIC18(L)F27/47K40 13.9 Program Memory Scan Configuration 13.11 Scanning Modes If desired, the program memory scan module may be used in conjunction with the CRC module to perform a CRC calculation over a range of program memory addresses. In order to set up the scanner to work with the CRC you need to perform the following steps: 1. 2. 3. 4. 5. Set the Enable bit in both the CRCCON0 and SCANCON0 registers. If they get disabled, all internal states of the scanner and the CRC are reset (registers are unaffected). Choose which memory access mode is to be used (see Section 13.11 "Scanning Modes") and set the MODE bits of the SCANCON0 register appropriately. Based on the memory access mode, set the INTM bits of the SCANCON0 register to the appropriate interrupt mode (see Section 13.11.5 "Interrupt Interaction") Set the SCANLADRL/H/U and SCANHADRL/H/ U registers with the beginning and ending locations in memory that are to be scanned. The CRCGO bit must be set before setting the SCANGO bit. Setting the SCANGO bit starts the scan. Both CRCEN and CRCGO bits must be enabled to use the scanner. When either of these bits are disabled, the scan aborts and the INVALID bit SCANCON0 is set. The scanner will wait for the signal from the CRC that it is ready for the first Flash memory location, then begin loading data into the CRC. It will continue to do so until it either hits the configured end address or an address that is unimplemented on the device, at which point the SCANGO bit will clear, Scanner functions will cease, and the SCANIF interrupt will be triggered. Alternately, the SCANGO bit can be cleared in software if desired. 13.10 Scanner Interrupt The scanner will trigger an interrupt when the SCANGO bit transitions from `1' to `0'. The SCANIF interrupt flag of PIR7 is set when the last memory location is reached and the data is entered into the CRCDATA registers. The SCANIF bit can only be cleared in software. The SCAN interrupt enable is the SCANIE bit of the PIE7 register. 2016 Microchip Technology Inc. The memory scanner can scan in four modes: Burst, Peek, Concurrent, and Triggered. These modes are controlled by the MODE bits of the SCANCON0 register. The four modes are summarized in Table 13-2. 13.11.1 BURST MODE When MODE = 01, the scanner is in Burst mode. In Burst mode, CPU operation is stalled beginning with the operation after the one that sets the SCANGO bit, and the scan begins, using the instruction clock to execute. The CPU is held in its current state until the scan stops. Note that because the CPU is not executing instructions, the SCANGO bit cannot be cleared in software, so the CPU will remain stalled until one of the hardware endconditions occurs. Burst mode has the highest throughput for the scanner, but has the cost of stalling other execution while it occurs. 13.11.2 CONCURRENT MODE When MODE = 00, the scanner is in Concurrent mode. Concurrent mode, like Burst mode, stalls the CPU while performing accesses of memory. However, while Burst mode stalls until all accesses are complete, Concurrent mode allows the CPU to execute in between access cycles. 13.11.3 TRIGGERED MODE When MODE = 11, the scanner is in Triggered mode. Triggered mode behaves identically to Concurrent mode, except instead of beginning the scan immediately upon the SCANGO bit being set, it waits for a rising edge from a separate trigger clock, the source of which is determined by the SCANTRIG register. 13.11.4 PEEK MODE When MODE = 10, the scanner is in Peek mode. Peek mode waits for an instruction cycle in which the CPU does not need to access the NVM (such as a branch instruction) and uses that cycle to do its own NVM access. This results in the lowest throughput for the NVM access (and can take a much longer time to complete a scan than the other modes), but does so without any impact on execution times, unlike the other modes. Preliminary DS40001844B-page 162 PIC18(L)F27/47K40 TABLE 13-2: SUMMARY OF SCANNER MODES Description MODE<1:0> First Scan Access CPU Operation 11 Triggered As soon as possible following a trigger Stalled during NVM access CPU resumes execution following each access 10 Peek At the first dead cycle Timing is unaffected CPU continues execution following each access 01 Burst 00 Concurrent As soon as possible 13.11.5 Stalled during NVM access CPU suspended until scan completes CPU resumes execution following each access INTERRUPT INTERACTION The INTM bit of the SCANCON0 register controls the scanner's response to interrupts depending on which mode the NVM scanner is in, as described in Table 13-3. TABLE 13-3: SCAN INTERRUPT MODES MODE<1:0> INTM MODE == Burst MODE == CONCURENT or TRIGGERED 1 Interrupt overrides SCANGO (to zero) to pause the burst and the interrupt handler executes at full speed; Scanner Burst resumes when interrupt completes. 0 Interrupts do not override SCANGO, and the scan (burst) operation will continue; interrupt Scanner accesses NVM during response will be delayed until scan interrupt response. completes (latency will be increased). MODE ==PEEK Scanner suspended during interrupt response (SCANGO = 0); interrupt executes at full speed This bit is ignored and scan resumes when the interrupt is complete. This bit is ignored In general, if INTM = 0, the scanner will take precedence over the interrupt, resulting in decreased interrupt processing speed and/or increased interrupt response latency. If INTM = 1, the interrupt will take precedence and have a better speed, delaying the memory scan. 13.11.6 WWDT INTERACTION Operation of the WWDT is not affected by scanner activity. Hence, it is possible that long scans, particularly in Burst mode, may exceed the WWDT time-out period and result in an undesired device Reset. This should be considered when performing memory scans with an application that also utilizes WWDT. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 163 PIC18(L)F27/47K40 13.11.7 IN-CIRCUIT DEBUG (ICD) INTERACTION The scanner freezes when an ICD halt occurs, and remains frozen until user-mode operation resumes. The debugger may inspect the SCANCON0 and SCANLADR registers to determine the state of the scan. The ICD interaction with each operating mode is summarized in Table 13-4. TABLE 13-4: ICD AND SCANNER INTERACTIONS Scanner Operating Mode ICD Halt Concurrent Triggered Peek Burst If external halt is asserted during the BSF(SCANCON.GO), ICD If external halt is asserted during entry occurs, and the burst is a scan cycle, the instruction delayed until ICD exit. (delayed by scan) may or may not execute before ICD entry, Otherwise, the current NVMdepending on external halt access cycle will complete, and timing. then the scanner will be interrupted for ICD entry. External Halt If external halt is asserted during the cycle immediately prior to the If external halt is asserted during scan cycle, both scan and the burst, the burst is suspended instruction execution happen and will resume with ICD exit. after the ICD exits. If scanner would peek an instruction that is not executed (because of ICD entry), the peek will occur after ICD exit, when the instruction executes. PC Breakpoint Scan cycle occurs before ICD entry and instruction execution happens after the ICD exits. If PCPB (or single step) is on BSF(SCANCON.GO), the ICD is entered before execution; execution of the burst will occur at ICD exit, and the burst will run to completion. Data Breakpoint The instruction with the dataBP executes and ICD entry occurs immediately after. If scan is requested during that cycle, the scan cycle is postponed until the ICD exits. Single Step If a scan cycle is ready after the debug instruction is executed, the scan will read PFM and then the ICD is re-entered. SWBP and ICDINST If SWBP replaces BSF(SCANCON.GO), the ICD will If scan would stall a SWBP, the be entered; instruction execution scan cycle occurs and the ICD is will occur at ICD exit (from entered. ICDINSTR register), and the burst will run to completion. 13.11.8 Note that the burst can be interrupted by an external halt. PERIPHERAL MODULE DISABLE Both the CRC and scanner module can be disabled individually by setting the CRCMD and SCANMD bits of the PMD0 register (Register 7-1). The SCANMD can be used to enable or disable to the scanner module only if the SCANE bit of Configuration Word 4 is set. If the SCANE bit is cleared, then the scanner module is not available for use and the SCANMD bit is ignored. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 164 PIC18(L)F27/47K40 TABLE 13-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH CRC Bit 7 Bit 6 Bit 5 CRCACCH Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACC<15:8> CRCACCL 151 ACC<7:0> CRCCON0 EN GO CRCCON1 BUSY ACCM Register on Page 152 -- DLEN<3:0> -- SHIFTM FULL PLEN<3:0> 150 150 CRCDATH DATA<15:8> 151 CRCDATL DATA<7:0> 151 CRCSHIFTH SHIFT<15:8> 152 CRCSHIFTL SHIFT<7:0> 152 CRCXORH X<15:8> 153 CRCXORL X<7:1> PMD0 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD SCANCON0 SCANEN SCANGO BUSY INVALID INTM -- -- -- SCANHADRU CLKRMD -- 153 IOCMD 67 MODE<1:0> 154 156 HADR<21:16> SCANHADRH HADR<15:8> 157 SCANHADRL HADR<7:0> 157 SCANLADRU -- -- LADR<15:8> SCANLADRL SCANTRIG INTCON 155 LADR<21:16> SCANLADRH 155 LADR<7:0> -- -- -- 156 TSEL<3:0> 158 IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIR7 SCANIF CRCIF NVMIF -- -- -- -- CWG1IF 177 PIE7 SCANIE CRCIE NVMIE -- -- -- -- CWG1IE 185 SCANIP CRCIP NVMIP -- -- -- -- CWG1IP 193 IPR7 Legend: GIE/GIEH PEIE/GIEL -- -- = unimplemented location, read as `0'. Shaded cells are not used for the CRC module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 165 PIC18(L)F27/47K40 14.0 INTERRUPTS 14.2 The PIC18(L)F2x/4xK40 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high or low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. A high priority interrupt event will interrupt a low priority interrupt that may be in progress. The registers for controlling interrupt operation are: * * * * INTCON PIR1, PIR2, PIR3, PIR4, PIR5, PIR6, PIR7 PIE1, PIE2, PIE3, PIE4, PIE5, PIE6, PIE7 IPR1, IPR2, IPR3, IPR4, IPR5, IPR6, IPR7 The interrupt priority feature is enabled by setting the IPEN bit of the INTCON register. When interrupt priority is enabled the GIE/GIEH and PEIE/GIEL Global Interrupt Enable bits of Compatibility mode are replaced by the GIEH high priority, and GIEL low priority, global interrupt enables. When the IPEN bit is set, the GEIH bit of the INTCON register enables all interrupts which have their associated bit in the IPRx register set. When the GEIH bit is cleared, then all interrupt sources including those selected as low priority in the IPRx register are disabled. When both GIEH and GIEL bits are set, all interrupts selected as low priority sources are enabled. It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority 14.1 Mid-Range Compatibility When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) microcontroller mid-range devices. In Compatibility mode, the interrupt priority bits of the IPRx registers have no effect. The PEIE/GIEL bit of the INTCON register is the global interrupt enable for the peripherals. The PEIE/GIEL bit disables only the peripheral interrupt sources and enables the peripheral interrupt sources when the GIE/GIEH bit is also set. The GIE/GIEH bit of the INTCON register is the global interrupt enable which enables all non-peripheral interrupt sources and disables all interrupt sources, including the peripherals. All interrupts branch to address 0008h in Compatibility mode. A high priority interrupt will vector immediately to address 00 0008h and a low priority interrupt will vector to address 00 0018h. 14.3 Interrupt Response When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. The GIE/GIEH bit is the Global Interrupt Enable when the IPEN bit is cleared. When the IPEN bit is set, enabling interrupt priority levels, the GIEH bit is the high priority Global Interrupt Enable and the GIEL bit is the low priority Global Interrupt Enable. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits in the INTCONx and PIRx registers. The interrupt flag bits must be cleared by software before re-enabling interrupts to avoid repeating the same interrupt. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE/GIEH bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the Interrupt-on-change pins, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one-cycle or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit. Note: 2016 Microchip Technology Inc. Interrupt Priority Preliminary Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS40001844B-page 166 PIC18(L)F27/47K40 FIGURE 14-1: PIC18 INTERRUPT LOGIC Rev. 10-000010B 5/4/2016 Wake-up if in Idle or Sleep modes PIR0 PIE0 IPR0 PIR1 PIE1 IPR1 Interrupt to CPU Vector at Location 0008h PIR2 PIE2 IPR2 GIEH/GIE IPEN IPEN GIEL/PEIE IPEN PIRx PIEx IPRx High Priority Interrupt Generation Low Priority Interrupt Generation PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR0 PIE0 IPR0 PIRx PIEx IPRx 2016 Microchip Technology Inc. Interrupt to CPU Vector at Location 0018h GIEH/GIE GIEL/PEIE Preliminary DS40001844B-page 167 PIC18(L)F27/47K40 14.4 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable and priority bits. 14.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are eight Peripheral Interrupt Request Flag registers (PIR0, PIR1, PIR2, PIR3, PIR4, PIR5, PIR6 and PIR7). 14.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are eight Peripheral Interrupt Enable registers (PIE0, PIE1, PIE2, PIE3, PIE4, PIE5, PIE6 and PIE7). When IPEN = 0, the PEIE/GIEL bit must be set to enable any of these peripheral interrupts. 14.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are eight Peripheral Interrupt Priority registers (IPR0, IPR1, IPR2, IPR3, IPR4 and IPR5, IPR6 and IPR7). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 168 PIC18(L)F27/47K40 14.8 Register Definitions: Interrupt Control REGISTER 14-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GIE/GIEH: Global Interrupt Enable bit If IPEN = 1: 1 = Enables all unmasked interrupts and cleared by hardware for high-priority interrupts only 0 = Disables all interrupts If IPEN = 0: 1 = Enables all unmasked interrupts and cleared by hardware for all interrupts 0 = Disables all interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit If IPEN = 1: 1 = Enables all low-priority interrupts and cleared by hardware for low-priority interrupts only 0 = Disables all low-priority interrupts If IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts bit 4-3 Unimplemented: Read as `0' bit 2 INT2EDG: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge of INT2 pin 0 = Interrupt on falling edge of INT2 pin bit 1 INT1EDG: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge of INT1 pin 0 = Interrupt on falling edge of INT1 pin bit 0 INT0EDG: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge of INT0 pin 0 = Interrupt on falling edge of INT0 pin Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 169 PIC18(L)F27/47K40 REGISTER 14-2: PIR0: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 0 U-0 U-0 R/W-0/0 R-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- TMR0IF(1) IOCIF(1,2) -- INT2IF(1,3) INT1IF(1,3) INT0IF(1,3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 TMR0IF: Timer0 Interrupt Flag bit(1) 1 = TMR0 register has overflowed (must be cleared by software) 0 = TMR0 register has not overflowed bit 4 IOCIF: Interrupt-on-Change Flag bit(1,2) 1 = IOC event has occurred (must be cleared by software) 0 = IOC event has not occurred bit 3 Unimplemented: Read as `0' bit 2 INT2IF: External Interrupt 2 Flag bit(1,3) 1 = External Interrupt 2 has occurred 0 = External Interrupt 2 has not occurred bit 1 INT1IF: External Interrupt 1 Flag bit(1,3) 1 = External Interrupt 1 has occurred 0 = External Interrupt 1 has not occurred bit 0 INT0IF: External Interrupt 0 Flag bit(1,3) 1 = External Interrupt 0 has occurred 0 = External Interrupt 0 has not occurred x = Bit is unknown Note 1: Interrupts are not disabled by the PEIE bit in the INTCON register. 2: IOCIF is a read-only bit, to clear the interrupt condition, all bits in the IOCF register must be cleared. 3: The external interrupt GPIO pin is selected by the INTPPS register. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 170 PIC18(L)F27/47K40 REGISTER 14-3: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 OSCFIF CSWIF(1) -- -- -- -- ADTIF ADIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 = Device clock operating bit 6 CSWIF: Clock-Switch Interrupt Flag bit(1) 1 = New oscillator is ready for switch (must be cleared by software) (see Figure 4-6 and Figure 4-7) 0 = New oscillator is not ready for switch or has not been started bit 5-2 Unimplemented: Read as `0' bit 1 ADTIF: ADC Threshold Interrupt Flag bit 1 = ADC Threshold interrupt has occurred (must be cleared by software) 0 = ADC Threshold event is not complete or has not been started bit 0 ADIF: ADC Interrupt Flag bit 1 = An A/D conversion completed (must be cleared by software) 0 = The A/D conversion is not complete or has not been started Note 1: The CSWIF interrupt will not wake the system from Sleep. The system will sleep until another interrupt causes the wake-up. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 171 PIC18(L)F27/47K40 REGISTER 14-4: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 HLVDIF ZCDIF -- -- -- -- C2IF C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 HLVDIF: HLVD Interrupt Flag bit 1 = HLVD interrupt event has occurred 0 = HLVD interrupt event has not occurred or has not been set up bit 6 ZCDIF: Zero-Cross Detect Interrupt Flag bit 1 = ZCD Output has changed (must be cleared in software) 0 = ZCD Output has not changed bit 5-2 Unimplemented: Read as `0' bit 1 C2IF: Comparator 2 Interrupt Flag bit 1 = Comparator C2 output has changed (must be cleared by software) 0 = Comparator C2 output has not changed bit 0 C1IF: Comparator 1 Interrupt Flag bit 1 = Comparator C1 output has changed (must be cleared by software) 0 = Comparator C1 output has not changed 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 172 PIC18(L)F27/47K40 REGISTER 14-5: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R-0/0 R-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RC1REG, is full (cleared by reading RC2REG) 0 = The EUSART2 receive buffer is empty bit 6 TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TX2REG, is empty (cleared by writing TX2REG) 0 = The EUSART2 transmit buffer is full bit 5 RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RC1REG, is full (cleared by reading RC1REG) 0 = The EUSART1 receive buffer is empty bit 4 TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TX1REG, is empty (cleared by writing TX1REG) 0 = The EUSART1 transmit buffer is full bit 3 BCL2IF: MSSP2 Bus Collision Interrupt Flag bit 1 = A bus collision has occurred while the MSSP2 module configured in I2C master was transmitting (must be cleared in software) 0 = No bus collision occurred bit 2 SSP2IF: Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 1 BCL1IF: MSSP1 Bus Collision Interrupt Flag bit 1 = A bus collision has occurred while the MSSP1 module configured in I2C master was transmitting (must be cleared in software) 0 = No bus collision occurred bit 0 SSP1IF: Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive 2016 Microchip Technology Inc. Preliminary DS40001844B-page 173 PIC18(L)F27/47K40 REGISTER 14-6: PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred bit 4 TMR5IF: TMR5 Overflow Interrupt Flag bit 1 = TMR5 register overflowed (must be cleared in software) 0 = TMR5 register did not overflow bit 3 TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred bit 2 TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 174 PIC18(L)F27/47K40 REGISTER 14-7: PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- -- TMR5GIF TMR3GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2 TMR5GIF: TMR5 Gate Interrupt Flag bit 1 = TMR5 gate interrupt occurred (must be cleared in software) 0 = No TMR5 gate occurred bit 1 TMR3GIF: TMR3 Gate Interrupt Flag bit 1 = TMR3 gate interrupt occurred (must be cleared in software) 0 = No TMR3 gate occurred bit 0 TMR1GIF: TMR1 Gate Interrupt Flag bit 1 = TMR1 gate interrupt occurred (must be cleared in software) 0 = No TMR1 gate occurred 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 175 PIC18(L)F27/47K40 REGISTER 14-8: PIR6: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- -- -- -- -- CCP2IF CCP1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as `0' bit 1 CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode. bit 0 CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare mode: 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM mode: Unused in PWM mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 176 PIC18(L)F27/47K40 REGISTER 14-9: PIR7: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 7 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 SCANIF CRCIF NVMIF -- -- -- -- CWG1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 SCANIF: SCAN Interrupt Flag bit 1 = SCAN interrupt has occurred (must be cleared in software) 0 = SCAN interrupt has not occurred or has not been started bit 6 CRCIF: CRC Interrupt Flag bit 1 = CRC interrupt has occurred (must be cleared in software) 0 = CRC interrupt has not occurred or has not been started bit 5 NVMIF: NVM Interrupt Flag bit 1 = NVM interrupt has occurred (must be cleared in software) 0 = NVM interrupt has not occurred or has not been started bit 4-1 Unimplemented: Read as `0' bit 0 CWG1IF: CWG Interrupt Flag bit 1 = CWG interrupt has occurred (must be cleared in software) 0 = CWG interrupt has not occurred or has not been started 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 177 PIC18(L)F27/47K40 REGISTER 14-10: PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0 U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- TMR0IE(1) IOCIE(1) -- INT2IE(1) INT1IE(1) INT0IE(1) bit 7 bit 0 Legend: IE R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 TMR0IE: Timer0 Interrupt Enable bit(1) 1 = Enabled 0 = Disabled bit 4 IOCIE: Interrupt-on-Change Enable bit(1) 1 = Enabled 0 = Disabled bit 3 Unimplemented: Read as `0' bit 2 INT2IE: External Interrupt 2 Enable bit(1) 1 = Enabled 0 = Disabled bit 1 INT1IE: External Interrupt 1 Enable bit(1) 1 = Enabled 0 = Disabled bit 0 INT0IE: External Interrupt 0 Enable bit(1) 1 = Enabled 0 = Disabled x = Bit is unknown Note 1: PIR0 interrupts are not disabled by the PEIE bit in the INTCON register. are not disabled by the PEIE bit in the INTCON register. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 178 PIC18(L)F27/47K40 REGISTER 14-11: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 OSCFIE CSWIE -- -- -- -- ADTIE ADIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CSWIE: Clock-Switch Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-2 Unimplemented: Read as `0' bit 1 ADTIE: ADC Threshold Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 ADIE: ADC Interrupt Enable bit 1 = Enabled 0 = Disabled 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 179 PIC18(L)F27/47K40 REGISTER 14-12: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 HLVDIE ZCDIE -- -- -- -- C2IE C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 HLVDIE: HLVD Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 ZCDIE: Zero-Cross Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-2 Unimplemented: Read as `0' bit 1 C2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 C1IE: Comparator 1 Interrupt Enable bit 1 = Enabled 0 = Disabled 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 180 PIC18(L)F27/47K40 REGISTER 14-13: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 R-/W0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 BCL2IE: MSSP2 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 SSP2IE: Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 BCL1IE: MSSP1 Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 SSP1IE: Synchronous Serial Port 1 Interrupt Enable bit 1 = Enabled 0 = Disabled 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 181 PIC18(L)F27/47K40 REGISTER 14-14: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 TMR5IE: TMR5 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 182 PIC18(L)F27/47K40 REGISTER 14-15: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- -- -- -- TMR5GIE TMR3GIE TMR1GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2 TMR5GIE: TMR5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3GIE: TMR3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 183 PIC18(L)F27/47K40 REGISTER 14-16: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- -- -- -- -- CCP2IE CCP1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 184 PIC18(L)F27/47K40 REGISTER 14-17: PIE7: PERIPHERAL INTERRUPT ENABLE REGISTER 7 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 SCANIE CRCIE NVMIE -- -- -- -- CWG1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 SCANIE: SCAN Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CRCIE: CRC Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 NVMIE: NVM Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4-1 Unimplemented: Read as `0' bit 0 CWG1IE: CWG Interrupt Enable bit 1 = Enabled 0 = Disabled 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 185 PIC18(L)F27/47K40 REGISTER 14-18: IPR0: PERIPHERAL INTERRUPT PRIORITY REGISTER 0 U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 -- -- TMR0IP IOCIP -- INT2IP INT1IP INT0IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 TMR0IP: Timer0 Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 IOCIP: Interrupt-on-Change Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as `0' bit 2 INT2IP: External Interrupt 2 Priority bit 1 = High priority 0 = Low priority bit 1 INT1IP: External Interrupt 1 Priority bit 1 = High priority 0 = Low priority bit 0 INT0IP: External Interrupt 0 Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 186 PIC18(L)F27/47K40 REGISTER 14-19: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 OSCFIP CSWIP -- -- -- -- ADTIP ADIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CSWIP: Clock-Switch Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-2 Unimplemented: Read as `0' bit 1 ADTIP: ADC Threshold Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 ADIP: ADC Interrupt Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 187 PIC18(L)F27/47K40 REGISTER 14-20: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 HLVDIP ZCDIP -- -- -- -- C2IP C1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 HLVDIP: HLVD Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ZCDIP: Zero-Cross Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 5-2 Unimplemented: Read as `0' bit 1 C2IP: Comparator 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 C1IP: Comparator 1 Interrupt Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 188 PIC18(L)F27/47K40 REGISTER 14-21: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCL2IP: MSSP2 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 BCL1IP: MSSP1 Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 SSP1IP: Synchronous Serial Port 1 Interrupt Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 189 PIC18(L)F27/47K40 REGISTER 14-22: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 -- -- TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 TMR6IP: TMR6 to PR6 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TMR5IP: TMR5 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 TMR4IP: TMR4 to PR4 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 190 PIC18(L)F27/47K40 REGISTER 14-23: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 -- -- -- -- -- TMR5GIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2 TMR5GIP: TMR5 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3GIP: TMR3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 191 PIC18(L)F27/47K40 REGISTER 14-24: IPR6: PERIPHERAL INTERRUPT PRIORITY REGISTER 6 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1/1 R/W-1/1 -- -- -- -- -- -- CCP2IP CCP1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 192 PIC18(L)F27/47K40 REGISTER 14-25: IPR7: PERIPHERAL INTERRUPT PRIORITY REGISTER 7 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 R/W-1/1 SCANIP CRCIP NVMIP -- -- -- -- CWG1IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 SCANIP: SCAN Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CRCIP: CRC Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 NVMIP: NVM Interrupt Priority bit 1 = High priority 0 = Low priority bit 4-1 Unimplemented: Read as `0' bit 0 CWG1IP: CWG Interrupt Priority bit 1 = High priority 0 = Low priority 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 193 PIC18(L)F27/47K40 14.9 INTn Pin Interrupts 14.10 TMR0 Interrupt PIC18(L)F2x/4xK40 devices have three external interrupt sources which can be assigned to any pin on PORTA and PORTB using PPS. The external interrupt sources are edge-triggered. If the corresponding INTxEDG bit in the INTCON0 register is set (= 1), the interrupt is triggered by a rising edge. It the bit is clear, the trigger is on the falling edge. All external interrupts (INT0, INT1 and INT2) can wakeup the processor from Idle or Sleep modes if bit INTxE was set prior to going into those modes. If the Global Interrupt Enable bit, GIE/GIEH, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority is determined by the value contained in the interrupt priority bits, INT0IP, INT1IP and INT2IP of the IPR0 register. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE of the PIE0 register. Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP of the IPR0 register. See Section 18.0 "Timer0 Module" for further details on the Timer0 module. 14.11 Interrupt-on-Change An input change on any port pins that support IOC sets Flag bit, IOCIF of the PIR0 register. The interrupt can be enabled/disabled by setting/clearing the enable bit, IOCIE of the PIE0 register. Pins must also be individually enabled in the IOCxP and IOCxN register. IOCIF is a read-only bit and the flag can be cleared by clearing the corresponding IOCxF registers. For more information refer to Section 16.0 "Interrupt-onChange". 14.12 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 10.2.2 "Fast Register Stack"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 14-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 14-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS 2016 Microchip Technology Inc. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TEMP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary DS40001844B-page 194 PIC18(L)F27/47K40 TABLE 14-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE/GIEH PEIE/GIEL IPEN -- INT2EDG INT1EDG INT0EDG 169 PIE0 TMR0IE IOCIE INT2IE INT1IE INT0IE 178 PIE1 OSCFIE CSWIE ADTIE ADIE 179 PIE2 HLVDIE ZCDIE C2IE C1IE 180 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIE4 TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE 182 PIE5 TMR5GIE TMR3GIE TMR1GIE 183 184 INTCON PIE6 CCP2IE CCP1IE PIE7 SCANIE CRCIE NVMIE CWG1IE 185 PIR0 TMR0IF IOCIF INT2IF INT1IF INT0IF 170 PIR1 OSCFIF CSWIF ADTIF ADIF 171 PIR2 HLVDIF ZCDIF C2IF C1IF 172 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 PIR4 TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 174 PIR5 TMR5GIF TMR3GIF TMR1GIF 175 PIR6 CCP2IF CCP1IF 176 PIR7 SCANIF CRCIF NVMIF CWG1IF 177 IPR0 TMR0IP IOCIP INT2IP INT1IP INT0IP 186 IPR1 OSCFIP CSWIP ADTIP ADIP 187 IPR2 HLVDIP ZCDIP C2IP C1IP 188 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 189 IPR4 TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP 190 IPR5 TMR5GIP TMR3GIP TMR1GIP 191 IPR6 CCP2IP CCP1IP 192 IPR7 SCANIP CRCIP NVMIP CWG1IP 193 Legend: -- = unimplemented locations, read as `0'. Shaded bits are not used for Interrupts. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 195 PIC18(L)F27/47K40 I/O PORTS PORTC PIC18(L)F47K40 PORTE PORTB PIC18(L)F27K40 Device GENERIC I/O PORT OPERATION PORT AVAILABILITY PER DEVICE PORTA TABLE 15-1: FIGURE 15-1: PORTD 15.0 Read LATx D Write LATx Write PORTx Each port has eight registers to control the operation. These registers are: TRISx Q CK VDD Data Register Data Bus * PORTx registers (reads the levels on the pins of the device) * LATx registers (output latch) * TRISx registers (data direction) * ANSELx registers (analog select) * WPUx registers (weak pull-up) * INLVLx (input level control) * SLRCONx registers (slew rate control) * ODCONx registers (open-drain control) I/O pin Read PORTx To digital peripherals To analog peripherals ANSELx VSS Most port pins share functions with device peripherals, both analog and digital. In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output; however, the pin can still be read. The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSELx bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 15-1. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 196 PIC18(L)F27/47K40 15.1 I/O Priorities EXAMPLE 15-1: Each pin defaults to the PORT data latch after Reset. Other functions are selected with the peripheral pin select logic. See Section 17.0 "Peripheral Pin Select (PPS) Module" for more information. ; ; ; ; Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital output functions may continue to control the pin when it is in Analog mode. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF Analog outputs, when enabled, take priority over digital outputs and force the digital output driver into a high-impedance state. INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'11111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<7:3> as inputs ;and set RA<2:0> as ;outputs The pin function priorities are as follows: 1. 2. 3. 4. 15.2.2 Configuration bits Analog outputs (disable the input buffers) Analog inputs Port inputs and outputs from PPS 15.2 PORTx Registers In this section the generic names such as PORTx, LATx, TRISx, etc. can be associated with PORTA, PORTB, PORTC and PORTD. For availability of PORTD refer to Table 15-1. The functionality of PORTE is different compared to other ports and is explained in a separate section. 15.2.1 DATA REGISTER PORTx is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISx (Register 15-2). Setting a TRISx bit (`1') will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISx bit (`0') will make the corresponding PORTx pin an output (i.e., it enables output driver and puts the contents of the output latch on the selected pin). Example 15-1 shows how to initialize PORTx. Reading the PORTx register (Register 15-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATx). The PORT data latch LATx (Register 15-3) holds the output port data and contains the latest value of a LATx or PORTx write. 15.2.3 ANALOG CONTROL The ANSELx register (Register 15-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELx bit high will cause all digital reads on the pin to be read as `0' and allow analog functions on the pin to operate correctly. The state of the ANSELx bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 15.2.4 The ANSELx bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to `0' by user software. OPEN-DRAIN CONTROL The ODCONx register (Register 15-6) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONx bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONx bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. Note: 2016 Microchip Technology Inc. DIRECTION CONTROL The TRISx register (Register 15-2) controls the PORTx pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISx register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read `0'. Preliminary It is not necessary to set open-drain control when using the pin for I2C; the I2C module controls the pin and makes the pin open-drain. DS40001844B-page 197 PIC18(L)F27/47K40 15.2.5 SLEW RATE CONTROL The SLRCONx register (Register 15-7) controls the slew rate option for each port pin. Slew rate for each port pin can be controlled independently. When an SLRCONx bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONx bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 15.2.6 INPUT THRESHOLD CONTROL The INLVLx register (Register 15-8) controls the input voltage threshold for each of the available PORTx input pins. A selection between the Schmitt Trigger CMOS or the TTL compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTx register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 37-8 for more information on threshold levels. Note: 15.2.7 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). TRISE controls the direction of the REx pins, even when they are being used as analog pins. The user must make sure to keep the pins configured as inputs when using them as analog inputs. RE<2:0> bits have other registers associated with them (i.e., ANSELE, WPUE, INLVLE, SLRCONE and ODCONE). The functionality is similar to the other ports. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. Note: The fourth pin of PORTE (MCLR/VPP/RE3) is an inputonly pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input-only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device's Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. RE3 in PORTE register is a read-only bit and will read `1' when MCLRE = 1 (i.e., Master Clear enabled). Note: WEAK PULL-UP CONTROL The WPUx register (Register 15-5) controls the individual weak pull-ups for each port pin. 15.2.8 CLRF PORTE Registers CLRF CLRF MOVLW MOVWF Depending on the device selected, PORTE is implemented in two different ways. 15.3.1 15.3.2 PORTE ON 40/44-PIN DEVICES For PIC18(L)F4xK40 devices, PORTE is a 4-bit wide port. Three pins (RE0, RE1 and RE2) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as `0's. The corresponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., disable the output driver). 2016 Microchip Technology Inc. On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. EXAMPLE 15-2: EDGE SELECTABLE INTERRUPT-ON-CHANGE An interrupt can be generated by detecting a signal at the port pin that has either a rising edge or a falling edge. Any individual pin can be configured to generate an interrupt. The interrupt-on-change module is present on all the pins that are common between 28-pin and 40/44-pin devices. For further details about the IOC module refer to Section 16.0 "Interrupt-on-Change". 15.3 On a Power-on Reset, RE<2:0> are configured as analog inputs. PORTE ; ; ; LATE ; ; ; ANSELE ; ; 05h ; ; ; TRISE ; ; ; INITIALIZING PORTE Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure analog pins for digital only Value used to initialize data direction Set RE<0> as input RE<1> as output RE<2> as input PORTE ON 28-PIN DEVICES For PIC18(L)F2xK40 devices, PORTE is only available when Master Clear functionality is disabled (MCLRE = 0). In this case, PORTE is a single bit, inputonly port comprised of RE3 only. The pin operates as previously described. RE3 in PORTE register is a readonly bit and will read `1' when MCLRE = 1 (i.e., Master Clear enabled). Preliminary DS40001844B-page 198 PIC18(L)F27/47K40 15.3.3 RE3 WEAK PULL-UP The port RE3 pin has an individually controlled weak internal pull-up. When set, the WPUE3 bit enables the RE3 pin pull-up. When the RE3 port pin is configured as MCLR, (CONFIG2L, MCLRE = 1 and CONFIG4H, LVP = 0), or configured for Low-Voltage Programming, (MCLRE = x and LVP = 1), the pull-up is always enabled and the WPUE3 bit has no effect. 15.3.4 INTERRUPT-ON-CHANGE The interrupt-on-change feature is available only on the RE3 pin for all devices. For further details refer to Section 14.11 "Interrupt-on-Change". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 199 PIC18(L)F27/47K40 15.4 Register Definitions: Port Control PORTx: PORTx REGISTER(1) REGISTER 15-1: R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u Rx7 Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 Note 1: Rx<7:0>: Rx7:Rx0 Port I/O Value bits 1 = Port pin is VIH 0 = Port pin is VIL Writes to PORTx are actually written to the corresponding LATx register. Reads from PORTx register return actual I/O pin values. TABLE 15-2: PORT REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PORTA X X RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 PORTB X X RB7(1) RB6(1) RB5 RB4 RB3 RB2 RB1 RB0 PORTC X X RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 PORTD X -- -- -- -- -- -- -- -- RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 PORTE X -- -- -- -- RE3(2) -- -- -- -- -- -- -- RE3(2) RE2 RE1 RE0 X X Note 1: Bits RB6 and RB7 read `1' while in Debug mode. 2: Bit PORTE3 is read-only, and will read `1' when MCLRE = 1 (Master Clear enabled). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 200 PIC18(L)F27/47K40 REGISTER 15-2: TRISx: TRI-STATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISx7 TRISx6 TRISx5 TRISx4 TRISx3 TRISx2 TRISx1 TRISx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 TRISx<7:0>: TRISx Port I/O Tri-state Control bits 1 = Port output driver is disabled 0 = Port output driver is enabled TABLE 15-3: TRIS REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRISA X X TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 TRISB X X TRISB7(1) TRISB6(1) TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 TRISC X X TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 TRISD X -- -- -- -- -- -- -- -- X TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 -- -- -- -- -- -- -- -- -- -- -- -- --(2) TRISE2 TRISE1 TRISE0 TRISE X X Note 1: 2: Bits RB6 and RB7 read `1' while in Debug mode. TRISE3 bit is read-only, and will read `1' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 201 PIC18(L)F27/47K40 LATx: LATx REGISTER(1) REGISTER 15-3: R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 LATx<7:0>: Rx7:Rx0 Output Latch Value bits Note 1: Writes to LATx are equivalent with writes to the corresponding PORTx register. Reads from LATx register return register values, not I/O pin values. TABLE 15-4: LAT REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LATA X X LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 LATB X X LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 LATC X X LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 LATD X -- -- -- -- -- -- -- -- LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 -- -- -- -- -- -- -- -- -- -- -- -- -- LATE2 LATE1 LATE0 X LATE X X 2016 Microchip Technology Inc. Preliminary DS40001844B-page 202 PIC18(L)F27/47K40 REGISTER 15-4: ANSELx: ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSELx7 ANSELx6 ANSELx5 ANSELx4 ANSELx3 ANSELx2 ANSELx1 ANSELx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 ANSELx<7:0>: Analog Select on Pins Rx<7:0> 1 = Digital Input buffers are disabled. 0 = ST and TTL input devices are enabled TABLE 15-5: ANALOG SELECT PORT REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANSELA X X ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0 ANSELB X X ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 ANSELC X X ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 ANSELD X -- -- -- -- -- -- -- -- X ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0 -- -- -- -- -- -- -- -- -- -- -- -- -- ANSELE2 ANSELE1 ANSELE0 ANSELE X X 2016 Microchip Technology Inc. Preliminary DS40001844B-page 203 PIC18(L)F27/47K40 REGISTER 15-5: WPUx: WEAK PULL-UP REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 WPUx7 WPUx6 WPUx5 WPUx4 WPUx3 WPUx2 WPUx1 WPUx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 WPUx<7:0>: Weak Pull-up PORTx Control bits 1 = Weak Pull-up enabled 0 = Weak Pull-up disabled TABLE 15-6: WEAK PULL-UP PORT REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPUA X X WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 WPUB X X WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 WPUC X X WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 WPUD X -- -- -- -- -- -- -- -- WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 WPUE X -- -- -- -- WPUE3(1) -- -- -- -- -- -- -- WPUE3(1) WPUE2 WPUE1 WPUE0 X X Note 1: If MCLRE = 1, the weak pull-up in RE3 is always enabled; bit WPUE3 is not affected. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 204 PIC18(L)F27/47K40 REGISTER 15-6: ODCONx: OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODCx7 ODCx6 ODCx5 ODCx4 ODCx3 ODCx2 ODCx1 ODCx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 ODCx<7:0>: Open-Drain Configuration on Pins Rx<7:0> 1 = Output drives only low-going signals (sink current only) 0 = Output drives both high-going and low-going signals (source and sink current) TABLE 15-7: OPEN-DRAIN CONTROL REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ODCONA X X ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 ODCONB X X ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 ODCONC X X ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 ODCOND X -- -- -- -- -- -- -- -- X ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 -- -- -- -- -- -- -- -- -- -- -- -- -- ODCE2 ODCE1 ODCE0 ODCONE X X 2016 Microchip Technology Inc. Preliminary DS40001844B-page 205 PIC18(L)F27/47K40 REGISTER 15-7: SLRCONx: SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRx7 SLRx6 SLRx5 SLRx4 SLRx3 SLRx2 SLRx1 SLRx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 SLRx<7:0>: Slew Rate Control on Pins Rx<7:0>, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate TABLE 15-8: SLEW RATE CONTROL REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLRCONA X X SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 SLRCONB X X SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 SLRCONC X X SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 SLRCOND X -- -- -- -- -- -- -- -- SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 -- -- -- -- -- -- -- -- -- -- -- -- -- SLRE2 SLRE1 SLRE0 X SLRCONE X X 2016 Microchip Technology Inc. Preliminary DS40001844B-page 206 PIC18(L)F27/47K40 REGISTER 15-8: INLVLx: INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLx7 INLVLx6 INLVLx5 INLVLx4 INLVLx3 INLVLx2 INLVLx1 INLVLx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-0 INLVLx<7:0>: Input Level Select on Pins Rx<7:0>, respectively 1 = ST input used for port reads and interrupt-on-change 0 = TTL input used for port reads and interrupt-on-change TABLE 15-9: INPUT LEVEL PORT REGISTERS Device Name 28 Pins 40/44 Pins Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INLVLA2 INLVLA1 INLVLA X X INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLB X X INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLC X X INLVLC7 INLVLC6 INLVLC5 INLVLC4(1) INLVLC3(1) INLVLC2 INLVLC1 INLVLC0 INLVLD X -- -- -- -- -- -- -- -- X INLVLE X X INLVLB2(1) INLVLB1(1) INLVLD2 (1) INLVLD1 INLVLA0 INLVLB0 INLVLD0(1) INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 -- -- -- -- INLVLE3 -- -- -- -- -- -- -- INLVLE3 INLVLE2 INLVLE1 INLVLE0 Note 1: Pins read the I2C ST inputs when MSSP inputs select these pins, and I2C mode is enabled. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 207 PIC18(L)F27/47K40 16.0 INTERRUPT-ON-CHANGE 16.3 PORTA, PORTB, PORTC and pin RE3 of PORTE can be configured to operate as Interrupt-on-Change (IOC) pins on PIC18(L)F2x/4xK40 family devices. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual port pin, or combination of port pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: * * * * Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags 16.1 Enabling the Module To allow individual port pins to generate an interrupt, the IOCIE bit of the PIE0 register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 16.2 The IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits located in the IOCAF, IOCBF, IOCCF and IOCEF registers respectively, are status flags that correspond to the interrupt-on-change pins of the associated port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the PIR0 register reflects the status of all IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits. 16.4 Figure 16-1 is a block diagram of the IOC module. Individual Pin Configuration For each port pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. A pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers, respectively. Interrupt Flags Clearing Interrupt Flags The individual status flags, (IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. EXAMPLE 16-1: MOVLW XORWF ANDWF 16.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 208 PIC18(L)F27/47K40 FIGURE 16-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q D S to data bus IOCAFx Q write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q3 Q2 Q3 Q4 Q4Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 2016 Microchip Technology Inc. Q4 Q4Q1 Preliminary Q4Q1 DS40001844B-page 209 PIC18(L)F27/47K40 16.6 Register Definitions: Interrupt-on-Change Control REGISTER 16-1: IOCxP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER EXAMPLE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCxP7 IOCxP6 IOCxP5 IOCxP4 IOCxP3 IOCxP2 IOCxP1 IOCxP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCxP<7:0>: Interrupt-on-Change Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the IOCx pin for a positive-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 16-2: IOCxN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER EXAMPLE R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCxN7 IOCxN6 IOCxN5 IOCxN4 IOCxN3 IOCxN2 IOCxN1 IOCxN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 IOCxN<7:0>: Interrupt-on-Change Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the IOCx pin for a negative-going edge. Associated Status bit and interrupt flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin REGISTER 16-3: IOCxF: INTERRUPT-ON-CHANGE FLAG REGISTER EXAMPLE R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCxF7 IOCxF6 IOCxF5 IOCxF4 IOCxF3 IOCxF2 IOCxF1 IOCxF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS - Bit is set in hardware bit 7-0 U = Unimplemented bit, read as `0' IOCxF<7:0>: Interrupt-on-Change Flag bits 1 = A enabled change was detected on the associated pin. Set when IOCP[n] = 1 and a positive edge was detected on the IOCn pin, or when IOCN[n] = 1 and a negative edge was detected on the IOCn pin 0 = No change was detected, or the user cleared the detected change 2016 Microchip Technology Inc. Preliminary DS40001844B-page 210 PIC18(L)F27/47K40 TABLE 16-1: Name IOC REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 IOCEP -- -- -- -- IOCEP3 (1) -- -- -- IOCEN -- -- -- -- IOCEN3(1) -- -- -- IOCEF -- -- -- -- IOCEF3(1) -- -- -- Note 1: If MCLRE = 1 or LVP = 1, RE3 port functionality is disabled and IOC on RE3 is not available. TABLE 16-2: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE/GIEH PEIE/GIEL IPEN INT2EDG INT1EDG INT0EDG 169 IOCxF IOCxF7 IOCxF6 IOCxF5 IOCxF4 IOCxF3 IOCxF2 IOCxF1 IOCxF0 210 IOCxN IOCxN7 IOCxN6 IOCxN5 IOCxN4 IOCxN3 IOCxN2 IOCxN1 IOCxN0 210 IOCxP7 IOCxP6 IOCxP5 IOCxP4 IOCxP3 IOCxP2 IOCxP1 IOCxP0 210 IOCxP Legend: -- = unimplemented location, read as `0'. Shaded cells are not used by interrupt-on-change. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 211 PIC18(L)F27/47K40 17.0 PERIPHERAL PIN SELECT (PPS) MODULE The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as shown in the simplified block diagram Figure 17-1. The peripheral input is selected with the peripheral xxxPPS register (Register 17-1), and the peripheral output is selected with the PORT RxyPPS register (Register 17-2). For example, to select PORTC<7> as the EUSART RX input, set RXxPPS to 5'b1 0111, and to select PORTC<6> as the EUSART TX output set RC6PPS to 5'b0 1001. 17.1 PPS Inputs Each peripheral has a PPS register with which the inputs to the peripheral are selected. Inputs include the device pins. Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer. Although every peripheral has its own PPS input selection register, the selections are identical for every peripheral as shown in Register 17-1. Note: 17.2 The notation "xxx" in the register name is a place holder for the peripheral identifier. For example, INT0PPS. PPS Outputs Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include: * EUSART (synchronous operation) * MSSP (I2C) Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown in Register 17-2. Note: The notation "Rxy" is a place holder for the pin identifier. For example, RA0PPS. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 212 PIC18(L)F27/47K40 FIGURE 17-1: SIMPLIFIED PPS BLOCK DIAGRAM Rev. 10-000262A 12/8/2015 RA0PPS abcPPS RA0 RA0 Peripheral abc RxyPPS Rxy Peripheral xyz RD7(1) RE2PPS xyzPPS Note 1: RE2(1) PORTD<7:0> and PORTE<2:0> are only available on PIC18(L)F4xK40 devices. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 213 PIC18(L)F27/47K40 17.3 Bidirectional Pins EXAMPLE 17-2: PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. Peripherals that have bidirectional signals include: * EUSART (synchronous operation) * MSSP (I2C) * CCP module Note: 17.4 The I2C default input pins are I2C and SMBus compatible. RB1 and RB2 are additional pins. RC4 and RC3 are default MMP1 pins and are SMBus compatible. Clock and data signals can be routed to any pin, however pins without I2C compatibility will operate at standard TTL/ST logic levels as selected by the INVLV register. PPS Lock The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the PPSLOCKED bit are shown in Example 17-1. EXAMPLE 17-1: PPS LOCK SEQUENCE PPS UNLOCK SEQUENCE ; Disable interrupts: BCF INTCON,GIE ; Bank to PPSLOCK register BANKSEL PPSLOCK MOVLB PPSLOCK MOVLW 55h ; Required sequence, next 4 instructions MOVWF PPSLOCK MOVLW AAh MOVWF PPSLOCK ; Clear PPSLOCKED bit to enable writes ; Only a BCF instruction will work BCF PPSLOCK,0 ; Enable Interrupts BSF INTCON,GIE 17.5 PPS One-Way Lock Using the PPS1WAY Configuration bit, the PPS settings can be locked in. When this bit is set, the PPSLOCKED bit can only be cleared and set one time after a device Reset. This allows for clearing the PPSLOCKED bit so that the input and output selections can be made during initialization. When the PPSLOCKED bit is set after all selections have been made, it will remain set and cannot be cleared until after the next device Reset event. 17.6 Operation During Sleep ; Disable interrupts: BCF INTCON,GIE PPS input and output selections are unaffected by Sleep. ; Bank to PPSLOCK register BANKSEL PPSLOCK MOVLB PPSLOCK MOVLW 55h 17.7 ; Required sequence, next 4 instructions MOVWF PPSLOCK MOVLW AAh MOVWF PPSLOCK Effects of a Reset A device Power-on-Reset (POR) clears all PPS input and output selections to their default values. All other Resets leave the selections unchanged. Default input selections are shown in the Section "Pin Allocation Tables".The PPS one-way is also removed. ; Set PPSLOCKED bit to disable writes ; Only a BSF instruction will work BSF PPSLOCK,0 ; Enable Interrupts BSF INTCON,GIE 2016 Microchip Technology Inc. Preliminary DS40001844B-page 214 PIC18(L)F27/47K40 17.8 Register Definitions: PPS Input Selection REGISTER 17-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION U-0 U-0 U-0 -- -- -- R/W-m/u(1) R/W-m/u(1) R/W-m/u(1) R/W-m/u(1) R/W-m/u(1) xxxPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit -n/n = Value at POR and BOR/Value at all other Resets u = Bit is unchanged x = Bit is unknown q = value depends on peripheral `1' = Bit is set U = Unimplemented bit, read as `0' m = value depends on default location for that input `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-3 xxxPPS<4:3>: Peripheral xxx Input PORTx Pin Selection bits See Table 17-1 for the list of available ports and default pin locations. 11 = PORTD (PIC18(L)F4xK40 only) 10 = PORTC 01 = PORTB 00 = PORTA bit 2-0 xxxPPS<2:0>: Peripheral xxx Input PORTx Pin Selection bits 111 = Peripheral input is from PORTx Pin 7 (Rx7) 110 = Peripheral input is from PORTx Pin 6 (Rx6) 101 = Peripheral input is from PORTx Pin 5 (Rx5) 100 = Peripheral input is from PORTx Pin 4 (Rx4) 011 = Peripheral input is from PORTx Pin 3 (Rx3) 010 = Peripheral input is from PORTx Pin 2 (Rx2) 001 = Peripheral input is from PORTx Pin 1 (Rx1) 000 = Peripheral input is from PORTx Pin 0 (Rx0) Note 1: The Reset value `m' of this register is determined by device default locations for that input. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 215 PIC18(L)F27/47K40 TABLE 17-1: PPS INPUT REGISTER DETAILS Peripheral PPS Input Register Default Pin Selection at POR Register Reset Value at POR Input Available from Selected PORTx PIC18(L)F27K40 PIC18(L)F47K40 Interrupt 0 INT0PPS RB0 5'b0 1000 A B -- A B -- -- Interrupt 1 INT1PPS RB1 5'b0 1001 A B -- A B -- -- Interrupt 2 INT2PPS RB2 5'b0 1010 A B -- A B -- -- Timer0 Clock T0CKIPPS RA4 5'b0 0100 A B -- A B -- -- Timer1 Clock T1CKIPPS RC0 5'b1 0000 A -- C A -- C -- Timer1 Gate T1GPPS RB5 5'b0 1101 -- B C -- B C -- Timer3 Clock T3CKIPPS RC0 5'b1 0000 -- B C -- B C -- Timer3 Gate T3GPPS RC0 5'b1 0000 A -- C A -- C -- Timer5 Clock T5CKIPPS RC2 5'b1 0010 A -- C A -- C -- Timer5 Gate T5GPPS RB4 5'b0 1100 -- B C -- B -- D Timer2 Clock T2INPPS RC3 5'b1 0011 A -- C A -- C -- Timer4 Clock T4INPPS RC5 5'b1 0101 -- B C -- B C -- Timer6 Clock T6INPPS RB7 5'b0 1111 -- B C -- B -- D CCP1 CCP1PPS RC2 5'b1 0010 -- B C -- B C -- CCP2 CCP2PPS RC1 5'b1 0001 -- B C -- B C -- CWG CWG1PPS RB0 5'b0 1000 -- B C -- B -- D DSM Carrier Low MDCARLPPS RA3 5'b0 0011 A -- C A -- -- D DSM Carrier High MDCARHPPS RA4 5'b0 0100 A -- C A -- -- D DSM Source MDSRCPPS RA5 5'b0 0101 A -- C A -- -- D ADC Conversion Trigger ADACTPPS RB4 5'b0 1100 -- B C -- B -- D MSSP1 Clock SSP1CLKPPS RC3 5'b1 0011 -- B C -- B C -- MSSP1 Data SSP1DATPPS RC4 5'b1 0100 -- B C -- B C -- MSSP1 Slave Select SSP1SSPPS RA5 5'b0 0101 A -- C A -- -- D MSSP2 Clock SSP2CLKPPS RB1 5'b0 1001 -- B C -- B -- D MSSP2 Data SSP2DATPPS RB2 5'b0 1010 -- B C -- B -- D MSSP2 Slave Select SSP2SSPPS RB0 5'b0 1000 -- B C -- B -- D EUSART1 Receive RX1PPS RC7 5'b1 0111 -- B C -- B C -- EUSART1 Transmit TX1PPS RC6 5'b1 0110 -- B C -- B C -- EUSART2 Receive RX2PPS RB7 5'b0 1111 -- B C -- B -- D EUSART2 Transmit TX2PPS RB6 5'b0 1110 -- B C -- B -- D 2016 Microchip Technology Inc. Preliminary DS40001844B-page 216 PIC18(L)F27/47K40 REGISTER 17-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER U-0 U-0 U-0 -- -- -- R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u RxyPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits(1) RxyPPS<4:0> Note 1: Pin Rxy Output Source Device Configuration PIC18(L)F27K40 PIC18(L)F47K40 5'b1 0111 ADGRDB A -- C A -- C -- -- 5'b1 0110 ADGRDA A -- C A -- C -- -- 5'b1 0101 DSM A -- C A -- -- D -- 5'b1 0100 CLKR -- B C -- B C -- -- 5'b1 0011 TMR0 -- B C -- B C -- -- 5'b1 0010 MSSP2 (SDO/SDA) -- B C -- B -- D -- 5'b1 0001 MSSP2 (SCK/SCL) -- B C -- B -- D -- 5'b1 0000 MSSP1 (SDO/SDA) -- B C -- B C -- -- 5'b0 1111 MSSP1 (SCK/SCL) -- B C -- B C -- -- 5'b0 1110 CMP2 A -- C A -- -- -- E 5'b0 1101 CMP1 A -- C A -- -- D -- 5'b0 1100 EUSART2 (RX) -- B C -- B -- D -- 5'b0 1011 EUSART2 (TX) -- B C -- B -- D -- 5'b0 1010 EUSART1 (RX) -- B C -- B C -- -- 5'b0 1001 EUSART1 (TX) -- B C -- B C -- -- 5'b0 1000 PWM4 A -- C A -- C -- -- 5'b0 0111 PWM3 A -- C A -- -- D -- 5'b0 0110 CCP2 -- B C -- B C -- -- 5'b0 0101 CCP1 -- B C -- B C -- -- 5'b0 0100 CWG1D -- B C -- B -- D -- 5'b0 0011 CWG1C -- B C -- B -- D -- 5'b0 0010 CWG1B -- B C -- B -- D -- 5'b0 0001 CWG1A -- B C -- B C -- -- 5'b0 0000 LATxy A B C A B C D E PORTD is present only on the PIC18(L)F45/46K40 devices. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 217 PIC18(L)F27/47K40 REGISTER 17-3: PPSLOCK: PPS LOCK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- PPSLOCKED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 Unimplemented: Read as `0' bit 0 PPSLOCKED: PPS Locked bit 1 = PPS is locked. PPS selections can not be changed. 0 = PPS is not locked. PPS selections can be changed. TABLE 17-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 -- -- Bit 2 Bit 1 Bit 0 Register on page -- -- PPSLOCKED 218 PPSLOCK -- -- -- INT0PPS -- -- -- INT0PPS<4:0> 215 INT1PPS -- -- -- INT1PPS<4:0> 215 INT2PPS -- -- -- INT2PPS<4:0> 215 T0CKIPPS -- -- -- T0CKIPPS<4:0> 215 T1CKIPPS -- -- -- T1CKIPPS<4:0> 215 T1GPPS -- -- -- T1GPPS<4:0> 215 T3CKIPPS -- -- -- T3CKIPPS<4:0> 215 T3GPPS -- -- -- T3GPPS<4:0> 215 T5CKIPPS -- -- -- T5CKIPPS<4:0> 215 T5GPPS -- -- -- T5GPPS<4:0> 215 T2INPPS -- -- -- T2INPPS<4:0> 215 T4INPPS -- -- -- T4INPPS<4:0> 215 T6INPPS -- -- -- T6INPPS<4:0> 215 CCP1PPS -- -- -- CCP1PPS<4:0> 215 CCP2PPS -- -- -- CCP2PPS<4:0> 215 CWG1PPS -- -- -- CWG1PPS<4:0> 215 MDCARLPPS -- -- -- MDCARLPPS<4:0> 215 MDCARHPPS -- -- -- MDCARHPPS<4:0> 215 MDSRCPPS -- -- -- MDSRCPPS<4:0> 215 ADACTPPS -- -- -- ADACTPPS<4:0> 215 SSP1CLKPPS -- -- -- SSP1CLKPPS<4:0> 215 SSP1DATPPS -- -- -- SSP1DATPPS<4:0> 215 SSP1SSPPS -- -- -- SSP1SSPPS<4:0> 215 RX1PPS -- -- -- RX1PPS<4:0> 217 TX1PPS -- -- -- TX1PPS<4:0> 215 SSP2CLKPPS -- -- -- SSP2CLKPPS<4:0> 215 SSP2DATPPS -- -- -- SSP2DATPPS<4:0> 215 2016 Microchip Technology Inc. Preliminary DS40001844B-page 218 PIC18(L)F27/47K40 TABLE 17-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED) Bit 6 Bit 5 SSP2SSPPS -- -- -- SSP2SSPPS<4:0> 215 RX2PPS -- -- -- RX2PPS<4:0> 217 TX2PPS -- -- -- TX2PPS<4:0> 215 RxyPPS -- -- -- RxyPPS<4:0> 217 Legend: Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page Bit 7 -- = unimplemented, read as `0'. Shaded cells are unused by the PPS module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 219 PIC18(L)F27/47K40 18.0 TIMER0 MODULE Timer0 module is an 8/16-bit timer/counter with the following features: * * * * * * * * * 16-bit timer/counter 8-bit timer/counter with programmable period Synchronous or asynchronous operation Selectable clock sources Programmable prescaler Programmable postscaler Operation during Sleep mode Interrupt on match or overflow Output on I/O pin (via PPS) or to other peripherals FIGURE 18-1: BLOCK DIAGRAM OF TIMER0 Rev. 10-000017C 10/27/2015 Reserved 111 Reserved 110 SOSC 101 LFINTOSC 100 HFINTOSC 011 FOSC/4 010 PPS 001 T0_match T0CKPS<3:0> TMR0 body Peripherals T0OUTPS<3:0> T0IF 1 Prescaler SYNC 0 IN OUT Postscaler TMR0 FOSC/4 T016BIT T0ASYNC 000 T0_out Q D T0CKIPPS PPS RxyPPS CK Q 3 T0CS<2:0> 16-bit TMR0 Body Diagram (T016BIT = 1) 8-bit TMR0 Body Diagram (T016BIT = 0) IN TMR0L R Clear IN TMR0L TMR0 High Byte OUT 8 Read TMR0L COMPARATOR OUT Write TMR0L T0_match 8 8 TMR0H TMR0 High Byte Latch Enable 8 TMR0H 8 Internal Data Bus 2016 Microchip Technology Inc. Preliminary DS40001844B-page 220 PIC18(L)F27/47K40 18.1 Timer0 Operation Timer0 can operate as either an 8-bit timer/counter or a 16-bit timer/counter. The mode is selected with the T016BIT bit of the T0CON register. 18.1.1 16-BIT MODE The register pair TMR0H:TMR0L, increments on the rising edge of the clock source. A 15-bit prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS<3:0> in the T0CON1 register). 18.1.1.1 Timer0 Reads and Writes in 16-Bit Mode In 16-bit mode, to avoid rollover between reading high and low registers, the TMR0H register is a buffered copy of the actual high byte of Timer0, which is neither directly readable nor writable (see Figure 18-1). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte was valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. 18.1.2 8-BIT MODE In normal operation, TMR0 increments on the rising edge of the clock source. A 15-bit prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS<3:0> in the T0CON1 register). In 8-bit mode, the value of TMR0L is compared to that of the Period buffer, a copy of TMR0H, on each clock cycle. When the two values match, the following events happen: * TMR0_out goes high for one prescaled clock period * TMR0L is reset * The contents of TMR0H are copied to the period buffer Both the prescaler and postscaler counters are cleared on the following events: * A write to the TMR0L register * A write to either the T0CON0 or T0CON1 registers * Any device Reset - Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or * Brown-out Reset (BOR) 18.1.3 COUNTER MODE In Counter mode, the prescaler is normally disabled by setting the T0CKPS bits of the T0CON1 register to `0000'. Each rising edge of the clock input (or the output of the prescaler if the prescaler is used) increments the counter by `1'. 18.1.4 TIMER MODE In Timer mode, the Timer0 module will increment every instruction cycle as long as there is a valid clock signal and the T0CKPS bits of the T0CON1 register (Register 18-2) are set to `0000'. When a prescaler is added, the timer will increment at the rate based on the prescaler value. 18.1.5 ASYNCHRONOUS MODE When the T0ASYNC bit of the T0CON1 register is set (T0ASYNC = `1'), the counter increments with each rising edge of the input source (or output of the prescaler, if used). Asynchronous mode allows the counter to continue operation during Sleep mode provided that the clock also continues to operate during Sleep. 18.1.6 SYNCHRONOUS MODE When the T0ASYNC bit of the T0CON1 register is clear (T0ASYNC = 0), the counter clock is synchronized to the system clock (FOSC/4). When operating in Synchronous mode, the counter clock frequency cannot exceed FOSC/4. 18.2 Clock Source Selection The T0CS<2:0> bits of the T0CON1 register are used to select the clock source for Timer0. Register 18-2 displays the clock source selections. 18.2.1 In 8-bit mode, the TMR0L and TMR0H registers are both directly readable and writable. The TMR0L register is cleared on any device Reset, while the TMR0H register initializes at FFh. INTERNAL CLOCK SOURCE When the internal clock source is selected, Timer0 operates as a timer and will increment on multiples of the clock source, as determined by the Timer0 prescaler. 18.2.2 EXTERNAL CLOCK SOURCE When an external clock source is selected, Timer0 can operate as either a timer or a counter. Timer0 will increment on multiples of the rising edge of the external clock source, as determined by the Timer0 prescaler. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 221 PIC18(L)F27/47K40 18.3 Programmable Prescaler 18.7 A software programmable prescaler is available for exclusive use with Timer0. There are 16 prescaler options for Timer0 ranging in powers of two from 1:1 to 1:32768. The prescaler values are selected using the T0CKPS<3:0> bits of the T0CON1 register. The prescaler is not directly readable or writable. Clearing the prescaler register can be done by writing to the TMR0L register or the T0CON0, T0CON1 registers or by any Reset. 18.4 Programmable Postscaler A software programmable postscaler (output divider) is available for exclusive use with Timer0. There are 16 postscaler options for Timer0 ranging from 1:1 to 1:16. The postscaler values are selected using the T0OUTPS<3:0> bits of the T0CON0 register. Timer0 Output The Timer0 output can be routed to any I/O pin via the RxyPPS output selection register (see Section 17.0 "Peripheral Pin Select (PPS) Module" for additional information). The Timer0 output can also be used by other peripherals, such as the auto-conversion trigger of the Analog-to-Digital Converter. Finally, the Timer0 output can be monitored through software via the Timer0 output bit (T0OUT) of the T0CON0 register (Register 18-1). TMR0_out will be a pulse of one postscaled clock period when a match occurs between TMR0L and PR0 (Period register for TMR0) in 8-bit mode, or when TMR0 rolls over in 16-bit mode. The Timer0 output is a 50% duty cycle that toggles on each TMR0_out rising clock edge. The postscaler is not directly readable or writable. Clearing the postscaler register can be done by writing to the TMR0L register or the T0CON0, T0CON1 registers or by any Reset. 18.5 Operation During Sleep When operating synchronously, Timer0 will halt. When operating asynchronously, Timer0 will continue to increment and wake the device from Sleep (if Timer0 interrupts are enabled) provided that the input clock source is active. 18.6 Timer0 Interrupts The Timer0 interrupt flag bit (TMR0IF) is set when either of the following conditions occur: * 8-bit TMR0L matches the TMR0H value * 16-bit TMR0 rolls over from `FFFFh' When the postscaler bits (T0OUTPS<3:0>) are set to 1:1 operation (no division), the T0IF flag bit will be set with every TMR0 match or rollover. In general, the TMR0IF flag bit will be set every T0OUTPS +1 matches or rollovers. If Timer0 interrupts are enabled (TMR0IE bit of the PIE0 register = `1'), the CPU will be interrupted and the device may wake from Sleep (see Section 18.2 "Clock Source Selection" for more details). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 222 PIC18(L)F27/47K40 18.8 Register Definitions: Timer0 Control REGISTER 18-1: T0CON0: TIMER0 CONTROL REGISTER 0 R/W-0/0 U-0 R-0 R/W-0/0 T0EN -- T0OUT T016BIT R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 T0OUTPS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 T0EN:TMR0 Enable bit 1 = The module is enabled and operating 0 = The module is disabled and in the lowest power mode bit 6 Unimplemented: Read as `0' bit 5 T0OUT:TMR0 Output bit (read-only) TMR0 output bit bit 4 T016BIT: TMR0 Operating as 16-Bit Timer Select bit 1 = TMR0 is a 16-bit timer 0 = TMR0 is an 8-bit timer bit 3-0 T0OUTPS<3:0>: TMR0 Output Postscaler (Divider) Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler 2016 Microchip Technology Inc. Preliminary DS40001844B-page 223 PIC18(L)F27/47K40 REGISTER 18-2: R/W-0/0 T0CON1: TIMER0 CONTROL REGISTER 1 R/W-0/0 T0CS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 T0ASYNC R/W-0/0 R/W-0/0 R/W-0/0 T0CKPS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 T0CS<2:0>:Timer0 Clock Source Select bits 111 = Reserved 110 = Reserved 101 = SOSC 100 = LFINTOSC 011 = HFINTOSC 010 = FOSC/4 001 = Pin selected by T0CKIPPS (Inverted) 000 = Pin selected by T0CKIPPS (Non-inverted) bit 4 T0ASYNC: TMR0 Input Asynchronization Enable bit 1 = The input to the TMR0 counter is not synchronized to system clocks 0 = The input to the TMR0 counter is synchronized to FOSC/4 bit 3-0 T0CKPS<3:0>: Prescaler Rate Select bit 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 2016 Microchip Technology Inc. Preliminary DS40001844B-page 224 PIC18(L)F27/47K40 REGISTER 18-3: R/W-0/0 TMR0L: TIMER0 COUNT REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR0<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TMR0<7:0>:TMR0 Counter bits <7:0> REGISTER 18-4: R/W-1/1 TMR0H: TIMER0 PERIOD REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TMR0<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 When T016BIT = 0 PR0<7:0>:TMR0 Period Register Bits <7:0> When T016BIT = 1 TMR0<15:8>: TMR0 Counter bits <15:8> TABLE 18-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page TMR0L TMR0<7:0> 225 TMR0H TMR0<15:8> 225 T0CON0 T0EN T0CON1 T0OUT T0CS<2:0> T016BIT T0ASYNC T0OUTPS<3:0> 223 T0CKPS<3:0> 224 T0CKIPPS T0CKIPPS<4:0> 215 TMR0PPS TMR0PPS<4:0> 215 GIE/GIEH PEIE/GIEL IPEN INT2EDG INT1EDG INT0EDG 169 PIR0 TMR0IF IOCIF INT2IF INT1IF INT0IF 170 INTCON PIE0 TMR0IE IOCIE INT2IE INT1IE INT0IE 178 IPR0 TMR0IP IOCIP INT2IP INT1IP INT0IP 186 PMD1 -- TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD 68 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by the Timer0 module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 225 PIC18(L)F27/47K40 19.0 TIMER1/3/5 MODULE WITH GATE CONTROL Timer1/3/5 module is a 16-bit timer/counter with the following features: * * * * * * * * * * * * * * * * 16-bit timer/counter register pair (TMRxH:TMRxL) Programmable internal or external clock source 2-bit prescaler Dedicated Secondary 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1/3/5 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) 16-Bit Read/Write Operation Time base for the Capture/Compare function with the CCP modules Special Event Trigger (with CCP) Selectable Gate Source Polarity Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt Figure 19-1 is a block diagram of the Timer1/3/5 module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 226 PIC18(L)F27/47K40 FIGURE 19-1: TIMER1/3/5 BLOCK DIAGRAM TMRxGATE<3:0> Rev. 10-000018G 8/7/2015 4 TxGPPS TxGSPM 0000 PPS 1 0 NOTE (5) Single Pulse Acq. Control 1 1111 D D 0 Q TxGVAL Q1 Q TxGGO/DONE TxGPOL CK Q Interrupt TMRxON R set bit TMRxGIF det TxGTM TMRxGE set flag bit TMRxIF TMRxON EN TMRx Tx_overflow TMRxH To Comparators (6) (2) TMRxL Q Synchronized Clock Input 0 D 1 TxCLK TxSYNC TMRxCLK<3:0> 4 TxCKIPPS (1) 0000 PPS Note (4) Prescaler 1,2,4,8 1111 det 2 TxCKPS<1:0> Note 1: Synchronize(3) Fosc/2 Internal Clock Sleep Input ST Buffer is high speed type when using TxCKIPPS. 2: TMRx register increments on rising edge. 3: Synchronize does not operate while in Sleep. 4: See Register 19-3 for clock source selections. 5: See Register 19-4 for gate source selection. 6: Synchronized comparator output should not be used in conjunction with synchronized input clock. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 227 PIC18(L)F27/47K40 19.1 Register Definitions: Timer1/3/5 Long bit name prefixes for the Timer1/3/5 are shown in Table 20-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 19-1: Peripheral Bit Name Prefix Timer1 T1 Timer3 T3 Timer5 T5 REGISTER 19-1: TxCON: TIMERx CONTROL REGISTER U-0 U-0 -- -- R/W-0/u R/W-0/u CKPS<1:0> U-0 R/W-0/u R/W-0/0 R/W-0/u -- SYNC RD16 ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared u = unchanged bit 7-6 Unimplemented: Read as `0' bit 5-4 CKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 Unimplemented: Read as `0' bit 2 SYNC: Timerx External Clock Input Synchronization Control bit TMRxCLK = FOSC/4 or FOSC: This bit is ignored. Timer1 uses the incoming clock as is. Else: 1 = Do not synchronize external clock input 0 = Synchronize external clock input with system clock bit 1 RD16: 16-Bit Read/Write Mode Enable bit 1 = All 16 bits of Timer1 can be read simultaneously (TMR1H is buffered) 0 = 16-bit reads of Timer1 are disabled (TMR1H not buffered) bit 0 ON: Timerx On bit 1 = Enables Timerx 0 = Disables Timerx 2016 Microchip Technology Inc. Preliminary DS40001844B-page 228 PIC18(L)F27/47K40 REGISTER 19-2: TxGCON: TIMERx GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u R-x U-0 U-0 GE GPOL GTM GSPM GGO/DONE GVAL -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GE: Timerx Gate Enable bit If TMRxON = 1: 1 = Timerx counting is controlled by the Timerx gate function 0 = Timerx is always counting If TMRxON = 0: This bit is ignored bit 6 GPOL: Timerx Gate Polarity bit 1 = Timerx gate is active-high (Timerx counts when gate is high) 0 = Timerx gate is active-low (Timerx counts when gate is low) bit 5 GTM: Timerx Gate Toggle Mode bit 1 = Timerx Gate Toggle mode is enabled 0 = Timerx Gate Toggle mode is disabled and Toggle flip-flop is cleared Timerx Gate Flip Flop Toggles on every rising edge bit 4 GSPM: Timerx Gate Single Pulse Mode bit 1 = Timerx Gate Single Pulse mode is enabled and is controlling Timerx gate) 0 = Timerx Gate Single Pulse mode is disabled bit 3 GGO/DONE: Timerx Gate Single Pulse Acquisition Status bit 1 = Timerx Gate Single Pulse Acquisition is ready, waiting for an edge 0 = Timerx Gate Single Pulse Acquisition has completed or has not been started. This bit is automatically cleared when TxGSPM is cleared. bit 2 GVAL: Timerx Gate Current State bit Indicates the current state of the Timerx gate that could be provided to TMRxH:TMRxL Unaffected by Timerx Gate Enable (TMRxGE) bit 1-0 Unimplemented: Read as `0' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 229 PIC18(L)F27/47K40 REGISTER 19-3: TMRxCLK: TIMERx CLOCK REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/u R/W-0/u R/W-0/u R/W-0/u CS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 CS<3:0>: Timerx Clock Source Selection bits CS u = unchanged Timer1 Timer3 Timer5 Clock Source Clock Source Clock Source Reserved Reserved Reserved 1011 TMR5 overflow TMR5 overflow Reserved 1010 TMR3 overflow Reserved TMR3 overflow 1001 Reserved TMR1 overflow TMR1 overflow 1000 TMR0 overflow TMR0 overflow TMR0 overflow 0111 CLKREF CLKREF CLKREF 0110 SOSC SOSC SOSC 0101 MFINTOSC (500 kHz) MFINTOSC (500 kHz) MFINTOSC (500 kHz) 0100 LFINTOSC LFINTOSC LFINTOSC 0011 HFINTOSC HFINTOSC HFINTOSC 0010 Fosc Fosc Fosc 0001 Fosc/4 Fosc/4 Fosc/4 0000 T1CKIPPS T3CKIPPS T5CKIPPS 1111-1100 2016 Microchip Technology Inc. Preliminary DS40001844B-page 230 PIC18(L)F27/47K40 REGISTER 19-4: U-0 TMRxGATE: TIMERx GATE ISM REGISTER U-0 -- U-0 -- U-0 -- R/W-0/u R/W-0/u R/W-0/u R/W-0/u GSS<3:0> -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 GSS<3:0>: Timerx Gate Source Selection bits GSS 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 2016 Microchip Technology Inc. u = unchanged Timer1 Timer3 Timer5 Gate Source Gate Source Gate Source Reserved ZCDOUT CMP2OUT CMP1OUT PWM4OUT PWM3OUT CCP2OUT CCP1OUT TMR6OUT (post-scaled) TMR5 overflow TMR4OUT (post-scaled) TMR3 overflow TMR2OUT (post-scaled) Reserved TMR0 overflow Pin selected by T1GPPS Reserved ZCDOUT CMP2OUT CMP1OUT PWM4OUT PWM3OUT CCP2OUT CCP1OUT TMR6OUT (post-scaled) TMR5 overflow TMR4OUT (post-scaled) Reserved TMR2OUT (post-scaled) TMR1 overflow TMR0 overflow Pin selected by T3GPPS Preliminary Reserved ZCDOUT CMP2OUT CMP1OUT PWM4OUT PWM3OUT CCP2OUT CCP1OUT TMR6OUT (post-scaled) Reserved TMR4OUT (post-scaled) TMR3 overflow TMR2OUT (post-scaled) TMR1 overflow TMR0 overflow Pin selected by T5GPPS DS40001844B-page 231 PIC18(L)F27/47K40 REGISTER 19-5: R/W-x/x TMRxL: TIMERx LOW BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x TMRxL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TMRxL<7:0>:Timerx Low Byte bits REGISTER 19-6: R/W-x/x TMRxH: TIMERx HIGH BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x TMRxH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TMRxH<7:0>:Timerx High Byte bits 2016 Microchip Technology Inc. Preliminary DS40001844B-page 232 PIC18(L)F27/47K40 19.2 Timer1/3/5 Operation The Timer1/3/5 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1/3/5 is enabled by configuring the ON and GE bits in the TxCON and TxGCON registers, respectively. Table 19-2 displays the Timer1/3/5 enable selections. TABLE 19-2: 19.3 * Asynchronous event on the TxGPPS pin * TMR0OUT * TMR1/3/5OUT (excluding the TMR for which it is being used) * TMR 2/4/6OUT (post-scaled) * CCP1/2OUT * PWM3/4OUT * CMP1/2OUT * ZCDOUT Note: TIMER1/3/5 ENABLE SELECTIONS GE 1 1 Count Enabled 1 0 Always On 0 1 Off 0 0 Off 19.3.2 Clock Source Selection INTERNAL CLOCK SOURCE When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1/3/5 prescaler. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: * * * * Timer1/3/5 Operation ON The CS<3:0> bits of the TMRxCLK register (Register 19-3) are used to select the clock source for Timer1/3/5. The four TMRxCLK bits allow the selection of several possible synchronous and asynchronous clock sources. Register 19-3 displays the clock source selections. 19.3.1 The following asynchronous sources may be used at the Timer1/3/5 gate: Timer1/3/5 enabled after POR Write to TMRxH or TMRxL Timer1/3/5 is disabled Timer1/3/5 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3/5 is enabled (TMRxON = 1) when TxCKI is low. EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1/3/5 module may work as a timer or a counter. When enabled to count, Timer1/3/5 is incremented on the rising edge of the external clock input of the TxCKIPPS pin. This external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated secondary internal oscillator circuit. When the FOSC internal clock source is selected, the Timer1/3/5 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1/3/5 value. To utilize the full resolution of Timer1/3/5, an asynchronous input signal must be used to gate the Timer1/3/5 clock input. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 233 PIC18(L)F27/47K40 19.4 Timer1/3/5 Prescaler 19.6 Timer1/3/5 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 19.5 Secondary Oscillator A secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The secondary oscillator is not dedicated only to Timer1/3/5; it can also be used by other modules. The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register (Register 4-7). This can be used as the clock source to the Timer using the TMRxCLK bits.The oscillator will continue to run during Sleep. Note: The oscillator requires a start-up and stabilization time before use. Thus, the SOSCEN bit of the OSCEN register should be set and a suitable delay observed prior to enabling Timer1/3/5. A software check can be performed to confirm if the secondary oscillator is enabled and ready to use. This is done by polling the SOR bit of the OSCSTAT (Register 4-4). 2016 Microchip Technology Inc. Timer1/3/5 Operation in Asynchronous Counter Mode If control bit SYNC of the TxCON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 19.6.1 "Reading and Writing Timer1/3/5 in Asynchronous Counter Mode"). Note: 19.6.1 When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. READING AND WRITING TIMER1/3/5 IN ASYNCHRONOUS COUNTER MODE Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register pair. Preliminary DS40001844B-page 234 PIC18(L)F27/47K40 19.7 Timer1/3/5 16-Bit Read/Write Mode FIGURE 19-2: Timer1/3/5 can be configured to read and write all 16 bits of data, to and from, the 8-bit TMRxL and TMRxH registers, simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit of the TxCON register. TIMER1/3/5 16-BIT READ/WRITE MODE BLOCK DIAGRAM From Timer1 Circuitry TMR1 High Byte TMR1L To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-Bit mode, the TMRxH register is not directly readable or writable and all read and write operations take place through the use of this TMRxH buffer register. 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1/3/5 value from a single instance in time. Reference the block diagram in Figure 19-2 for more details. 19.8 In contrast, when not in 16-Bit mode, the user must read each register separately and determine if the values have become invalid due to a rollover that may have occurred between the read operations. Timer1/3/5 can be configured to count freely or the count can be enabled and disabled using Timer1/3/5 gate circuitry. This is also referred to as Timer1/3/5 gate enable. When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRxL:TMRxH register pair at the same time. Timer1/3/5 gate can also be driven by multiple selectable sources. Any requests to write to the TMRxH directly does not clear the Timer1/3/5 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register. TMR1H 8 8 Internal Data Bus Block Diagram of Timer1 Example of TIMER1/3/5 Timer1/3/5 Gate 19.8.1 TIMER1/3/5 GATE ENABLE The Timer1/3/5 Gate Enable mode is enabled by setting the TMRxGE bit of the TxGCON register. The polarity of the Timer1/3/5 Gate Enable mode is configured using the TxGPOL bit of the TxGCON register. When Timer1/3/5 Gate Enable mode is enabled, Timer1/3/5 will increment on the rising edge of the Timer1/3/5 clock source. When Timer1/3/5 Gate signal is inactive, the timer will not increment and hold the current count. Enable mode is disabled, no incrementing will occur and Timer1/3/5 will hold the current count. See Figure 19-4 for timing details. TABLE 19-3: 2016 Microchip Technology Inc. TIMER1/3/5 GATE ENABLE SELECTIONS Timer1/3/5 Operation TMRxCLK TxGPOL TxG 1 1 Counts 1 0 Holds Count 0 1 Holds Count 0 0 Counts Preliminary DS40001844B-page 235 PIC18(L)F27/47K40 19.8.2 TIMER1/3/5 GATE SOURCE SELECTION 19.8.4 The gate source for Timer1/3/5 can be selected using the GSS<3:0> bits of the TMRxGATE register (Register 19-4). The polarity selection for the gate source is controlled by the TxGPOL bit of the TxGCON register (Register 19-2). Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1/3/5 clock or left asynchronous. For more information see Section 32.5.1 "Comparator Output Synchronization". 19.8.3 TIMER1/3/5 GATE TOGGLE MODE When Timer1/3/5 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1/3/5 gate signal, as opposed to the duration of a single level pulse. The Timer1/3/5 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 19-5 for timing details. Timer1/3/5 Gate Toggle mode is enabled by setting the GTM bit of the TxGCON register. When the GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. TIMER1/3/5 GATE SINGLE-PULSE MODE When Timer1/3/5 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1/3/5 Gate Single-Pulse mode is first enabled by setting the GSPM bit in the TxGCON register. Next, the GGO/DONE bit in the TxGCON register must be set. The Timer1/3/5 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1/3/5 until the GGO/DONE bit is once again set in software. Clearing the TxGSPM bit of the TxGCON register will also clear the GGO/DONE bit. See Figure 19-6 for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1/3/5 gate source to be measured. See Figure 19-7 for timing details. 19.8.5 TIMER1/3/5 GATE VALUE STATUS When Timer1/3/5 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1/3/5 gate is not enabled (GE bit is cleared). 19.8.6 TIMER1/3/5 GATE EVENT INTERRUPT When Timer1/3/5 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in the PIR5 register will be set. If the TMRxGIE bit in the PIE5 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1/3/5 gate is not enabled (GE bit is cleared). For more information on selecting high or low priority status for the Timer1/3/5 Gate Event Interrupt see Section 14.0 "Interrupts". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 236 PIC18(L)F27/47K40 19.9 Timer1/3/5 Interrupt 19.11 CCP Capture/Compare Time Base The Timer1/3/5 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of the PIR4 register is set. To enable the interrupt-on-rollover, you must set these bits: * * * * TMRxON bit of the TxCON register TMRxIE bits of the PIE4 register PEIE/GIEL bit of the INTCON register GIE/GIEH bit of the INTCON register The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine. For more information on selecting high or low priority status for the Timer1/3/5 Overflow Interrupt, see Section 14.0 "Interrupts". Note: The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before enabling interrupts. 19.10 Timer1/3/5 Operation During Sleep Timer1/3/5 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: * * * * * TMRxON bit of the TxCON register must be set TMRxIE bit of the PIE4 register must be set PEIE/GIEL bit of the INTCON register must be set TxSYNC bit of the TxCON register must be set Configure the TMRxCLK register for using secondary oscillator as the clock source * Enable the SOSCEN bit of the OSCEN register (Register 4-7) The CCP modules use the TMRxH:TMRxL register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. In Compare mode, an event is triggered when the value in the CCPRxH:CCPRxL register pair matches the value in the TMRxH:TMRxL register pair. This event can be a Special Event Trigger. For more information, see 21.0 "Capture/Compare/PWM Module". Section 19.12 CCP Special Event Trigger When any of the CCP's are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair. This special event does not cause a Timer1/3/5 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1/3/5. Timer1/3/5 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of Timer1/3/5 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a Special Event Trigger from the CCP, the write will take precedence. The device will wake-up on an overflow and execute the next instruction. If the GIE/GIEH bit of the INTCON register is set, the device will call the Interrupt Service Routine. The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 237 PIC18(L)F27/47K40 FIGURE 19-3: TIMER1/3/5 INCREMENTING EDGE TxCKI = 1 when TMRx Enabled TxCKI = 0 when TMRx Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 19-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5 N 2016 Microchip Technology Inc. N+1 Preliminary N+2 N+3 N+4 DS40001844B-page 238 PIC18(L)F27/47K40 FIGURE 19-5: TIMER1/3/5 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL TIMER1/3/5 FIGURE 19-6: N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 TMRxGIF N N+1 Set by hardware on falling edge of TxGVAL Cleared by software 2016 Microchip Technology Inc. N+2 Preliminary Cleared by software DS40001844B-page 239 PIC18(L)F27/47K40 FIGURE 19-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 TMRxGIF N N+1 N+2 N+3 Set by hardware on falling edge of TxGVAL Cleared by software N+4 Cleared by software 19.13 Peripheral Module Disable When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module's clock source. The Module Disable bits for Timer1 (TMR1MD), Timer3 (TMR3MD) and Timer5 (TMR5MD) are in the PMD1 register. See Section 7.0 "Peripheral Module Disable (PMD)" for more information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 240 PIC18(L)F27/47K40 TABLE 19-4: Name INTCON PIE4 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1/3/5 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL IPEN -- -- TMR6IE Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page -- -- INT2EDG INT1EDG INT0EDG 169 TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE 182 TMR5GIE TMR3GIE TMR1GIE 183 Bit 4 PIE5 -- -- -- -- -- PIR4 -- -- TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 173 TMR5GIF TMR3GIF TMR1GIF 174 PIR5 -- -- -- -- -- IPR4 -- -- TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP 190 TMR3GIP TMR1GIP 191 68 IPR5 -- -- -- -- -- TMR5GIP PMD1 -- TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD T1CON -- -- T1GCON GE GPOL T3CON -- -- T3GCON GE GPOL T5CON -- -- T5GCON GE GPOL CKPS<1:0> GTM GSPM CKPS<1:0> GTM GSPM CKPS<1:0> GTM GSPM -- SYNC RD16 ON 228 GO/DONE GVAL -- -- 229 -- SYNC RD16 ON 228 GO/DONE GVAL -- -- 229 -- SYNC RD16 ON 228 GO/DONE GVAL -- -- 229 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 232 TMR1L Least Significant Byte of the 16-bit TMR1 Register 232 TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 232 TMR3L Least Significant Byte of the 16-bit TMR3 Register 232 TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 232 TMR5L Least Significant Byte of the 16-bit TMR5 Register 232 T1CKIPPS -- -- -- T1CKIPPS<4:0> 215 T1GPPS -- -- -- T1GPPS<4:0> 215 T3CKIPPS -- -- -- T3CKIPPS<4:0> 215 T3GPPS -- -- -- T3GPPS<4:0> 215 T5CKIPPS -- -- -- T5CKIPPS<4:0> 215 T5GPPS -- -- -- T5GPPS<4:0> 215 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used by TIMER1/3/5. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 241 PIC18(L)F27/47K40 20.0 TIMER2/4/6 MODULE The Timer2/4/6 modules are 8-bit incorporate the following features: timers that * 8-bit Timer and Period registers (TMR2 and PR2, respectively) * Readable and writable (both registers) * Software programmable prescaler (1:1 to 1:128) * Software programmable postscaler (1:1 to 1:16) * Interrupt on TMR2 match with PR2 * One-shot operation * Full asynchronous operation * Includes Hardware Limit Timer (HLT) * Alternate clock sources * External Timer Reset signal sources * Configurable Timer Reset operation See Figure 20-1 for Timer2 clock sources. See Figure 20-2 for a block diagram of Timer2 with HLT. Note: Three identical Timer2 modules are implemented on this device. The timers are named Timer2, Timer4 and Timer6. All references to Timer2 apply as well to Timer4 and Timer6. All references to PR2 apply as well to PR4 and PR6. FIGURE 20-1: TIMER2 CLOCK SOURCE BLOCK DIAGRAM Rev. 10-000169D 8/7/2015 TxCLK <3:0> TXINPPS TXIN PPS 0000 See TxCLKCON Register TMRx_clk 1111 2016 Microchip Technology Inc. Preliminary DS40001844B-page 242 PIC18(L)F27/47K40 FIGURE 20-2: TIMER2 WITH HARDWARE LIMIT TIMER (HLT) BLOCK DIAGRAM TxRSEL <3:0> TxINPPS TxIN PPS External Reset (2) Sources Rev. 10-000168C 9/10/2015 TxMODE<4:0> TMRx_ers Edge Detector Level Detector Mode Control (2 clock Sync) MODE<3> reset CCP_pset(1) MODE<4:3>=01 enable D MODE<4:1>=1011 Q Clear ON TxCPOL 0 Prescaler TMRx_clk TMRx 3 Sync 1 TxCKPS<2:0> Fosc/4 TxPSYNC R Comparator Set flag bit TMRxIF Postscaler TMRx_postscaled 4 TxON Sync (2 Clocks) 1 PRx TxOUTPS<3:0> 0 TxCSYNC Note 1: Signal to the CCP to trigger the PWM pulse. 2: See TxRST Register 20-6 for external Reset sources. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 243 PIC18(L)F27/47K40 20.1 Register Definitions: Timer2/4/6 Control Long bit name prefixes for the Timer2/4/6 peripherals are shown in Table 20-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 20-1: Peripheral Bit Name Prefix Timer2 T2 Timer4 T4 Timer6 T6 REGISTER 20-1: R/W-0/0 TMRx: TIMERx COUNTER REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TxTMR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TxTMR<7:0>: Timerx Counter bits REGISTER 20-2: R/W-1/1 TxPR: TIMERx PERIOD REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TxPR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 TxPR<7:0>: Timerx Period Register bits 2016 Microchip Technology Inc. Preliminary DS40001844B-page 244 PIC18(L)F27/47K40 REGISTER 20-3: R/W/HC-0/0 TxCON: TIMERx CONTROL REGISTER R/W-0/0 TxON R/W-0/0 R/W-0/0 R/W-0/0 CKPS<2:0> R/W-0/0 R/W-0/0 R/W-0/0 OUTPS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 ON: Timerx On bit(1) 1 = Timerx is on 0 = Timerx is off: all counters and state machines are reset bit 6-4 CKPS<2:0>: Timerx-type Clock Prescale Select bits 111 = 1:128 Prescaler 110 = 1:64 Prescaler 101 = 1:32 Prescaler 100 = 1:16 Prescaler 011 = 1:8 Prescaler 010 = 1:4 Prescaler 001 = 1:2 Prescaler 000 = 1:1 Prescaler bit 3-0 OUTPS<3:0>: Timerx Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler Note 1: In certain modes, the TxON bit will be auto-cleared by hardware. See Section 20.5.1 "One-Shot Mode". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 245 PIC18(L)F27/47K40 REGISTER 20-4: TxHLT: TIMERx HARDWARE LIMIT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 PSYNC CPOL CSYNC R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 PSYNC: Timerx Prescaler Synchronization Enable bit(1, 2) 1 = TMRx Prescaler Output is synchronized to Fosc/4 0 = TMRx Prescaler Output is not synchronized to Fosc/4 bit 6 CPOL: Timerx Clock Polarity Selection bit(3) 1 = Falling edge of input clock clocks timer/prescaler 0 = Rising edge of input clock clocks timer/prescaler bit 5 CSYNC: Timerx Clock Synchronization Enable bit(4, 5) 1 = ON register bit is synchronized to TMR2_clk input 0 = ON register bit is not synchronized to TMR2_clk input bit 4-0 MODE<4:0>: Timerx Control Mode Selection bits(6, 7) See Table 20-2 for all operating modes. Note 1: 2: 3: 4: Setting this bit ensures that reading TMRx will return a valid data value. When this bit is `1', Timer2 cannot operate in Sleep mode. CKPOL should not be changed while ON = 1. Setting this bit ensures glitch-free operation when the ON is enabled or disabled. 5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set. 6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TMRx). 7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 246 PIC18(L)F27/47K40 TxMODE CONFIGURATION OPTIONS(2,6) TABLE 20-2: MODE<4:0> <4:3> <2:0> <4:0> Output Operation 11 xxx 24-31 10 000 16 Reserved 001 17 010 18 Monostable edge-triggered start(3) 011 19 100 20 101 21 Reserved 110 22 111 23 One-shot level triggered start with HLT action 000 08 001 09 010 10 011 11 100 12 101 13 110 14 111 15 01 00 Operation Timer Control Start Reset(1) Stop Reserved Input rising edge start timer TMRx_ers RE and TxON = 1 -- Input falling edge start timer TMRx_ers FE and TxON = 1 -- Input either edge start timer TMRx_ers edge and TxON = 1 -- Input high start timer, Input active-low Reset timer TMRx_ers = 1 and TxON = 1 TMRx_ers = 0 Input low start timer, Input active-high Reset timer TMRx_ers = 0 and TxON = 1 TMRx_ers = 1 One-shot SW start SW start (no HW control) TxON = 1 -- One-shot edge-triggered start(3) Input rising edge start timer TMRx_ers RE and TxON = 1 -- Input falling edge start timer TMRx_ers FE and TxON = 1 -- Input either edge start timer TMRx_ers edge and TxON = 1 -- Input rising edge start timer; Input rising edge Reset timer TMRx_ers RE and TxON = 1 TMRx_ers RE Input falling edge start timer, TMRx_ers FE Input falling edge Reset timer and TxON = 1 TMRx_ers FE Input rising edge start timer, Input active-low Reset timer TMRx_ers RE and TxON = 1 TMRx_ers = 0 Input falling edge start timer, Input active-high Reset timer TMRx_ers FE and TxON = 1 TMRx_ers = 1 TxON = 0 or Next clock after TMRx = PR2(5) Reserved One-shot edge-triggered start with HLT action(3) TxON = 0 or Next clock after TMRx = PR2(4) 000 00 SW gate (no HW control) TxON = 1 -- TxON = 0 001 01 HW gate, active-high TMRx_ers = 1 and TxON = 1 -- TxON = 0 or TMRx_ers = 0 010 02 HW gate, active-low TMRx_ers = 0 and TxON = 1 -- TxON = 0 or TMRx_ers = 1 Input either edge Reset timer TxON = 1 011 03 100 04 101 110 111 Note 1: 2: 3: 4: 5: 6: Roll-over pulse TxON = 0 or held in Reset(4) Roll-over pulse with HLT action TMRx_ers edge TxON = 0 Input rising edge Reset timer TMRx_ers RE 05 Input falling edge Reset timer TMRx_ers FE 06 Input active-low Reset timer TMRx_ers = 0 07 Input active-high Reset timer TMRx_ers = 1 TxON = 0 or held in Reset When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode. In all operating modes, TxON = 0 stops the counter without affecting the value of TMRx In edge-triggered one-shot and monostable modes (not "SW Start" mode), the triggered-start mechanism is reset and rearmed (prepared for next start) if TxON becomes `0' (zero); the counter will not restart until an input edge occurs. When TMRx = PRx, the next clock clears TxON. When TMRx = PRx, TxON is not cleared. Both TxON and TMRx_ers are subject to clock sync delays. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 247 PIC18(L)F27/47K40 REGISTER 20-5: TxCLKCON: TIMERx CLOCK SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 CS<3:0>: Timerx Clock Selection bits CS<3:0> TMR2 TMR4 TMR6 Clock Source Clock Source Clock Source 1111-1001 Reserved Reserved Reserved 1000 ZCD_OUT ZCD_OUT ZCD_OUT 0111 CLKREF_OUT CLKREF_OUT CLKREF_OUT 0110 SOSC SOSC SOSC 0101 MFINTOSC (31 kHz) MFINTOSC (31 kHz) MFINTOSC (31 kHz) 0100 LFINTOSC LFINTOSC LFINTOSC 0011 HFINTOSC HFINTOSC HFINTOSC 0010 Fosc Fosc Fosc 0001 Fosc/4 Fosc/4 Fosc/4 0000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 248 PIC18(L)F27/47K40 REGISTER 20-6: TxRST: TIMER2 EXTERNAL RESET SIGNAL SELECTION REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 RSEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 RSEL<3:0>: Timer2 External Reset Signal Source Selection bits RSEL<3:0> TMR2 TMR4 TMR6 Reset Source Reset Source Reset Source 1011-1111 Reserved Reserved Reserved 1010 ZCD_OUT ZCD_OUT ZCD_OUT 1001 CMP2OUT CMP2OUT CMP2OUT 1000 CMP1OUT CMP1OUT CMP1OUT 0111 PWM4OUT PWM4OUT PWM4OUT 0110 PWM3OUT PWM3OUT PWM3OUT 0101 CCP2OUT CCP2OUT CCP2OUT 0100 CCP1OUT CCP1OUT CCP1OUT 0011 TMR6 post-scaled TMR6 post-scaled Reserved 0010 TMR4 post-scaled Reserved TMR4 post-scaled 0001 Reserved TMR2 post-scaled TMR2 post-scaled 0000 Pin selected by T2INPPS Pin selected by T4INPPS Pin selected by T6INPPS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 249 PIC18(L)F27/47K40 20.2 Timer2 Operation 20.3 The 3-bit prescaler on the clock input allows for several prescaler options, from direct input to divide-by-128. These options are selected by the prescaler control bits CKPS<2:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator resets the value of TMR2 to 00h on the next cycle and drives the 4-bit output counter/postscaler (see Section 20.3 "Timer2 Interrupt"). In addition, the Timer can be Reset through the use of an external Reset signal as outlined in Section 20.5 "External Reset Sources". Timer2 Interrupt Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches one of 16 postscale options (from 1:1 through 1:16), which is selected with the postscaler control bits, OUTPS<3:0> of the T2CON register. The interrupt is enabled by setting the TMR2 Interrupt Enable bit, TMR2IE, of the PIE4 register. The interrupt timing is illustrated in Figure 20-3. The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: * * * * * * * * * * a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Windowed Watchdog Timer (WWDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction External Reset Source events, which resets the timer. Note: TMR2 is not cleared when T2CON is written. FIGURE 20-3: TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM Rev. 10-000205A 4/7/2016 CKPS 0b010 PRx 1 OUTPS 0b0001 TMRx_clk TMRx 0 1 0 1 0 1 0 TMRx_postscaled TMRxIF (1) (2) (1) Note 1: Setting the interrupt flag is synchronized with the instruction clock. Synchronization may take as many as 2 instruction cycles 2: Cleared by software. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 250 PIC18(L)F27/47K40 20.4 Timer2 Output 20.6 The Timer2 module's primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each match of the postscaler counter and the OUTPS<3:0> bits of the T2CON register. The PR2 postscaler is incremented each time the TMR2 value matches the PR2 value. This signal can be selected as an input to several other input modules: * The CRC memory scanner, as a trigger for triggered mode * The ADC module, as an auto-conversion trigger * Gate source for Timer1/3/5 * CWG, as an auto-shutdown source * Alternate SPI clock * Reset signals for other instances of itself (Timer2/4/6) In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. Both the actual TMR2 value as well as other internal signals are sent to the CCP module to properly clock both the period and pulse width of the PWM signal. See Section 21.5 "PWM Overview" and Section 22.0 "Pulse-Width Modulation (PWM )" for more details on setting up Timer2 for use with the CCP and PWM. 20.5 Operation Examples Unless otherwise specified, the following notes apply to the following timing diagrams: - Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the TxCON register are cleared). - The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full cycles for both ON and Timer2_ers. When using FOSC/4, the clock-sync delay is at least one instruction period for Timer2_ers; ON applies in the next instruction period. - ON and Timer2_ers are somewhat generalized, and clock-sync delays may produce results that are slightly different than illustrated. - The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in Section 21.5 "PWM Overview" and Section 22.0 "Pulse-Width Modulation (PWM )". The signals are not a part of the Timer2 module. External Reset Sources In addition to the clock source, Timer2 also takes in an external Reset source. This external Reset source is selected for Timer2, Timer4 and Timer6 with the T2RST, T4RST and T6RST registers, respectively. This source can control the starting and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. The mode of the timer is controlled by the MODE<4:0> bits of the TxHLT register. 20.5.1 ONE-SHOT MODE The MODE<3> bit of the TxHLT register controls whether the timer is in either the One-Shot mode or the original Normal Period mode. When this bit is set, the timer acts in the One-Shot mode, meaning that upon the timer register matching the PRx period register, the timer will stop incrementing until the timer is manually started again. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 251 PIC18(L)F27/47K40 20.6.1 SOFTWARE GATE MODE The Software Gate mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 20-4. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock. FIGURE 20-4: SOFTWARE GATE MODE TIMING DIAGRAM Rev. 10-000195B 5/30/2014 0b00000 MODE TMRx_clk Instruction(1) BSF BCF BSF ON PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 252 PIC18(L)F27/47K40 20.6.2 HARDWARE GATE MODE The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can also gate the timer. When used with the CCP the gating extends the PWM period. If the timer is stopped when the PWM output is high then the duty cycle is also extended. When MODE<4:0> = 00001 then the timer is stopped when the external signal is high. When MODE<4:0> = 00010, the timer is stopped when the external signal is low. Figure 20-5 illustrates the Hardware Gating mode for MODE<4:0> = 00001 in which a high input level stops the counter. FIGURE 20-5: HARDWARE GATE MODE TIMING DIAGRAM Rev. 10-000 196B 5/30/201 4 0b00001 MODE TMRx_clk TMRx_ers PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output 2016 Microchip Technology Inc. Preliminary DS40001844B-page 253 PIC18(L)F27/47K40 20.6.3 EDGE-TRIGGERED HARDWARE LIMIT MODE In Edge-Triggered Hardware Limit mode the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: * Reset on rising or falling edge (MODE<4:0> = 00011) * Reset on rising edge (MODE<4:0> = 00100) * Reset on falling edge (MODE<4:0> = 00101) When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 20-6. FIGURE 20-6: EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM Rev. 10-000 197B 5/30/201 4 0b00100 MODE TMRx_clk PRx 5 Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 254 PIC18(L)F27/47K40 20.6.4 LEVEL-TRIGGERED HARDWARE LIMIT MODE In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 20-7. Selecting MODE<4:0> = 00110 will cause the timer to reset on a low level external signal. Selecting MODE<4:0> = 00111 will cause the timer to reset on a high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0 the external signal is ignored. When the CCP uses the timer as the PWM time base then an external signal Reset will set the PWM output high after a two clock synchronization delay or the timer matches the PRx period value. The PWM output will remain high until the external signal is released and the timer counts up to match the CCPRx pulse-width value. FIGURE 20-7: LEVEL-TRIGGERED HARDWARE LIMIT TIMING DIAGRAM Rev. 10-000198B 5/30/2014 0b00111 MODE TMRx_clk 5 PRx Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 255 PIC18(L)F27/47K40 20.6.5 ONE-SHOT MODE When One-Shot mode is used in conjunction with the CCP/PWM operation the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse-width value. The PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match. In One-Shot mode, the timer resets and the ON bit is cleared when the timer value matches the PRx period value. The ON bit must be set by software to start another timer cycle. Setting MODE<4:0> = 01000 selects One-Shot mode which is illustrated in Figure 20-8. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. FIGURE 20-8: ONE-SHOT MODE TIMING DIAGRAM Rev. 10-000199B 5/30/2014 0b01000 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 256 PIC18(L)F27/47K40 20.6.6 EDGE-TRIGGERED ONE-SHOT MODE The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer: * Rising edge (MODE<4:0> = 01001) * Falling edge (MODE<4:0>= 01010) * Rising or Falling edge (MODE<4:0> = 01011) FIGURE 20-9: If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 20-9 illustrates operation in the rising edge One-Shot mode. When this mode is used in conjunction with the CCP then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated when the timer halts at the PRx period count match. EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM Rev. 10-000200B 5/30/2014 0b01001 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF BCF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 TMRx_out TMRx_postscaled PWM Duty Cycle 3 PWM Output Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 257 PIC18(L)F27/47K40 20.6.7 EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: * Rising edge Start and Reset (MODE<4:0> = 01100) * Falling edge Start and Reset (MODE<4:0> = 01101) The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 20-10 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 258 2016 Microchip Technology Inc. FIGURE 20-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT TIMING DIAGRAM Rev. 10-000 201B 5/30/201 4 MODE 0b01100 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers 0 TMRx 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0 Preliminary TMRx_postscaled PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001844B-page 259 PIC18(L)F27/47K40 Note PIC18(L)F27/47K40 20.6.8 LEVEL TRIGGERED HARDWARE LIMIT ONE-SHOT MODES In Level Triggered One-Shot mode the timer count is reset on the external signal level and starts counting when the external signal level relinquishes the Reset. Reset levels are selected as follows: * High Reset level (MODE<4:0> = 01110) * Low Reset level (MODE<4:0> = 01111) When the timer count matches the PRx period count then the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control a new external signal edge is required after the ON bit is set to start the counter. When Level Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse-width count. The PWM drive does not go active when the timer count clears at the PRx period count match. 20.7 Timer2 Operation During Sleep When TxPSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while processor is in Sleep mode. When TxPSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. Selecting the LFINTOSC, MFINTOSC, or HFINTOSC oscillator as the timer clock source will keep the selected oscillator running during Sleep. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 260 2016 Microchip Technology Inc. FIGURE 20-11: LEVEL-TRIGGERED HARDWARE LIMIT ONE-SHOT MODE TIMING DIAGRAM Rev. 10-000 202A 12/20/201 3 MODE 0b1110 TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 Preliminary TMRx_postscaled PWM Duty Cycle 3 PWM Output 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. DS40001844B-page 261 PIC18(L)F27/47K40 Note PIC18(L)F27/47K40 TABLE 20-3: Name CCPTMRS INTCON SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 P4TSEL<1:0> Bit 5 Bit 4 P3TSEL<1:0> Bit 3 Bit 2 Bit 1 C2TSEL<1:0> Bit 0 C1TSEL<1:0> GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG Register on Page 266 169 PIE4 -- -- TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE 182 PIR4 -- -- TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 174 IPR4 -- -- TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP 190 PMD1 -- TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD 68 PR2 TMR2 Timer2 Module Period Register 250* Holding Register for the 8-bit TMR2 Register 250* T2CON ON T2CLKCON -- -- CKPS<2:0> -- -- T2RST -- -- -- -- T2HLT PSYNC CPOL CSYNC PR4 OUTPS<3:0> -- CS<2:0> RSEL<3:0> MODE<4:0> ON T4CLKCON -- CKPS<2:0> -- -- -- T4RST -- -- -- T4HLT PSYNC CPOL CSYNC PR6 250* OUTPS<3:0> -- -- CS<2:0> RSEL<3:0> MODE<4:0> 248 249 250* Holding Register for the 8-bit TMR6 Register 250* T6CON ON T6CLKCON -- -- -- -- T6RST -- -- -- -- T6HLT PSYNC CPOL CSYNC MODE<4:0> 246 T2INPPS -- -- -- T2INPPS<4:0> 215 T4INPPS -- -- -- T4INPPS<4:0> 215 T6INPPS -- -- -- T6INPPS<4:0> 215 Legend: * CKPS<2:0> 245 246 Timer6 Module Period Register TMR6 249 250* Holding Register for the 8-bit TMR4 Register T4CON 248 246 Timer4 Module Period Register TMR4 245 OUTPS<3:0> -- CS<2:0> RSEL<3:0> 245 248 249 -- = unimplemented location, read as `0'. Shaded cells are not used for Timer2 module. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 262 PIC18(L)F27/47K40 21.0 CAPTURE/COMPARE/PWM MODULE 21.1 The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/Compare/PWM modules (CCP1 and CCP2). Each individual CCP module can select the timer source that controls the module. Each module has an independent timer selection which can be accessed using the CxTSEL bits in the CCPTMRS register (Register 21-2). The default timer selection is TMR1 when using Capture/Compare mode and TMR2 when using PWM mode in the CCPx module. Please note that the Capture/Compare mode operation is described with respect to TMR1 and the PWM mode operation is described with respect to TMR2 in the following sections. The Capture and Compare functions are identical for all CCP modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator `x' to indicate the use of a numeral to distinguish a particular module, when required. 2016 Microchip Technology Inc. CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input selection register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). 21.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers 1 through 6 that vary with the selected mode. Various timers are available to the CCP modules in Capture, Compare or PWM modes, as shown in Table 21-1. TABLE 21-1: CCP Mode Capture Compare PWM CCP MODE - TIMER RESOURCE Timer Resource Timer1, Timer3 or Timer5 Timer2, Timer4 or Timer6 The assignment of a particular timer to a module is determined by the timer to CCP enable bits in the CCPTMRS register (see Register 21-2) All of the modules may be active at once and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. 21.1.2 OPEN-DRAIN OUTPUT OPTION When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. Preliminary DS40001844B-page 263 PIC18(L)F27/47K40 21.2 Register Definitions: CCP Control Long bit name prefixes for the CCP peripherals are shown in Table 21-2. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 21-2: Peripheral Bit Name Prefix CCP1 CCP1 CCP2 CCP2 REGISTER 21-1: CCPxCON: CCPx CONTROL REGISTER R/W-0/0 U-0 R-x R/W-0/0 EN -- OUT FMT R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 MODE<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7 EN: CCP Module Enable bit 1 = CCP is enabled 0 = CCP is disabled bit 6 Unimplemented: Read as `0' bit 5 OUT: CCPx Output Data bit (read-only) bit 4 FMT: CCPW (pulse-width) Alignment bit MODE = Capture mode: Unused MODE = Compare mode: Unused MODE = PWM mode: 1 = Left-aligned format 0 = Right-aligned format Note 1: 2: x = Bit is unknown The set and clear operations of the Compare mode are reset by setting MODE = 4'b0000 or EN = 0. When MODE = 0001 or 1011, then the timer associated with the CCP module is cleared. TMR1 is the default selection for the CCP module, so it is used for indication purpose only. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 264 PIC18(L)F27/47K40 REGISTER 21-1: bit 3-0 CCPxCON: CCPx CONTROL REGISTER (CONTINUED) MODE<3:0>: CCPx Mode Select bits MODE 11xx 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Note 1: 2: Operating Mode PWM Compare Capture Compare Operation PWM operation Pulse output; clear TMR1(2) Pulse output Clear output(1) Set output(1) Every 16th rising edge of CCPx input Every 4th rising edge of CCPx input Every rising edge of CCPx input Every falling edge of CCPx input Every edge of CCPx input Toggle output Toggle output; clear TMR1(2) Disabled Set CCPxIF Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes -- The set and clear operations of the Compare mode are reset by setting MODE = 4'b0000 or EN = 0. When MODE = 0001 or 1011, then the timer associated with the CCP module is cleared. TMR1 is the default selection for the CCP module, so it is used for indication purpose only. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 265 PIC18(L)F27/47K40 REGISTER 21-2: R/W-0/0 CCPTMRS: CCP TIMERS CONTROL REGISTER R/W-1/1 P4TSEL<1:0> R/W-0/0 R/W-1/1 P3TSEL<1:0> R/W-0/0 R/W-1/1 R/W-0/0 C2TSEL<1:0> R/W-1/1 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 P4TSEL<1:0>: PWM4 Timer Selection bits 11 = PWM4 based on TMR6 10 = PWM4 based on TMR4 01 = PWM4 based on TMR2 00 = Reserved bit 5-4 P3TSEL<1:0>: PWM3 Timer Selection bits 11 = PWM3 based on TMR6 10 = PWM3 based on TMR4 01 = PWM3 based on TMR2 00 = Reserved bit 3-2 C2TSEL<1:0>: CCP2 Timer Selection bits 11 = CCP2 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode 10 = CCP2 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode 01 = CCP2 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode 00 = Reserved bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection bits 11 = CCP1 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode 10 = CCP1 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode 01 = CCP1 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode 00 = Reserved 2016 Microchip Technology Inc. Preliminary DS40001844B-page 266 PIC18(L)F27/47K40 REGISTER 21-3: CCPxCAP: CAPTURE INPUT SELECTION MULTIPLEXER REGISTER U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- R/W-0/x R/W-0/x CTS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1-0 CTS<1:0>: Capture Trigger Input Selection bits Connection CTS<1:0> R/W-x/x CCP1 CCP2 11 IOC_Interrupt 10 CMP2_output 01 CMP1_output Pin selected by CCP1PPS 00 REGISTER 21-4: x = Bit is unknown Pin selected by CCP2PPS CCPRxL: CCPx REGISTER LOW BYTE R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x CCPRx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown MODE = Capture Mode: CCPRxL<7:0>: LSB of captured TMR1 value MODE = Compare Mode: CCPRxL<7:0>: LSB compared to TMR1 value MODE = PWM Mode && FMT = 0: CCPRxL<7:0>: CCPW<7:0> - Pulse-Width LS 8 bits MODE = PWM Mode && FMT = 1: CCPRxL<7:6>: CCPW<1:0> - Pulse-Width LS 2 bits CCPRxL<5:0>: Not used 2016 Microchip Technology Inc. Preliminary DS40001844B-page 267 PIC18(L)F27/47K40 REGISTER 21-5: R/W-x/x CCPRxH: CCPx REGISTER HIGH BYTE R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x CCPRx<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-0 x = Bit is unknown MODE = Capture Mode: CCPRxH<7:0>: MSB of captured TMR1 value MODE = Compare Mode: CCPRxH<7:0>: MSB compared to TMR1 value MODE = PWM Mode && FMT = 0: CCPRxH<7:2>: Not used CCPRxH<1:0>: CCPW<9:8> - Pulse-Width MS 2 bits MODE = PWM Mode && FMT = 1: CCPRxH<7:0>: CCPW<9:2> - Pulse-Width MS 8 bits 2016 Microchip Technology Inc. Preliminary DS40001844B-page 268 PIC18(L)F27/47K40 21.3 Capture Mode 21.3.1 Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the capture source, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMRxH:TMRxL register pair, respectively. An event is defined as one of the following and is configured by the MODE<3:0> bits of the CCPxCON register: * * * * * Every falling edge of CCPx input Every rising edge of CCPx input Every 4th rising edge of CCPx input Every 16th rising edge of CCPx input Every edge of CCPx input (rising or falling) Note: In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. The capture source is selected by configuring the CTS<1:0> bits of the CCPxCAP register. The following sources can be selected: * * * * When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIR6 register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH:CCPRxL register pair is read, the old captured value is overwritten by the new captured value. CAPTURE SOURCES Pin selected by CCPxPPS C1_output C2_output IOC_interrupt 21.3.2 TIMER1 MODE RESOURCE Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. * See Section 19.0 "Timer1/3/5 Module with Gate Control" for more information on configuring Timer1. If an event occurs during a 2-byte read, the high and low-byte data will be from different events. It is recommended while reading the CCPRxH:CCPRxL register pair to either disable the module or read the register pair twice for data integrity. Figure 21-1 shows a simplified diagram of the capture operation. FIGURE 21-1: CAPTURE MODE OPERATION BLOCK DIAGRAM RxyPPS CCPx PPS TRIS Control CCPxCTS<1:0> CCPRxH CCPRxL IOC_interrupt 11 C2OUT_sink 10 01 C1OUT_sink PPS Prescaler 1,4,16 and Edge Detect 16 set ccpxif 16 00 CCPxMODE<3:0> TMR1H TMR1L CCPxPPS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 269 PIC18(L)F27/47K40 21.3.3 21.4 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE Interrupt Priority bit of the PIE6 register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIR6 register following any change in Operating mode. Note: 21.3.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP PRESCALER There are four prescaler settings specified by the MODE<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 21-1 demonstrates the code to perform this function. EXAMPLE 21-1: Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMRxH:TMRxL register pair. When a match occurs, one of the following events can occur: * * * * * * Toggle the CCPx output, clear TMRx Toggle the CCPx output Set the CCPx output Clear the CCPx output Pulse output Pulse output, clear TMRx The action on the pin is based on the value of the MODE<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set, and an ADC conversion can be triggered, if selected. All Compare modes can generate an interrupt and trigger an ADC conversion. When MODE = 4'b0001 or 4'b1011, the CCP resets the TMR register pair. Figure 21-2 shows a simplified diagram of the compare operation. FIGURE 21-2: COMPARE MODE OPERATION BLOCK DIAGRAM CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW MOVWF 21.3.5 ;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value CCPxMODE<3:0> Mode Select BANKSEL CCPxCON Set CCPxIF Interrupt Flag (PIR6) 4 CCPRxH CCPRxL PPS Q S R RxyPPS Output Logic Match TMR1H TRIS Output Enable CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. Comparator TMR1L Auto-conversion Trigger When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 270 PIC18(L)F27/47K40 21.4.1 21.5 CCPx PIN CONFIGURATION The software must configure the CCPx pin as an output by clearing the associated TRIS bit and defining the appropriate output pin through the RxyPPS registers. See Section 17.0 "Peripheral Pin Select (PPS) Module" for more details. The CCP output can also be used as an input for other peripherals. Note: 21.4.2 Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. TIMER1 MODE RESOURCE In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 19.0 "Timer1/3/5 Module with Gate Control" for more information on configuring Timer1. Note: 21.4.3 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the ON state and the low portion of the signal is considered the OFF state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 21-3 shows a typical waveform of the PWM signal. 21.5.1 STANDARD PWM OPERATION The standard PWM function described in this section is available and identical for all CCP modules. AUTO-CONVERSION TRIGGER All CCPx modes set the CCP interrupt flag (CCPxIF). When this flag is set and a match occurs, an auto-conversion trigger can take place if the CCP module is selected as the conversion trigger source. The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: Refer to Section 31.2.6 "Auto-Conversion Trigger" for more information. * * * * Note: 21.4.4 Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring PR2 registers T2CON registers CCPRxL and CCPRxH registers CCPxCON registers It is required to have FOSC/4 as the clock input to TMR2/4/6 for correct PWM operation. Figure 21-4 shows a simplified block diagram of PWM operation. Note: COMPARE DURING SLEEP Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the timer is running. The device will wake on interrupt (if enabled). The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. FIGURE 21-3: CCP PWM OUTPUT SIGNAL Period Pulse Width TMR2 = PR2 TMR2 = CCPRxH:CCPRxL TMR2 = 0 2016 Microchip Technology Inc. Preliminary DS40001844B-page 271 PIC18(L)F27/47K40 FIGURE 21-4: SIMPLIFIED PWM BLOCK DIAGRAM Rev. 10-000 157C 9/5/201 4 Duty cycle registers CCPRxH CCPRxL CCPx_out 10-bit Latch(2) (Not accessible by user) Comparator R Q S TMR2 Module R TMR2 To Peripherals set CCPIF PPS RxyPPS CCPx TRIS Control (1) ERS logic Comparator CCPx_pset PR2 Notes: 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time-base. 2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 272 PIC18(L)F27/47K40 21.5.2 SETUP FOR PWM OPERATION 21.5.4 The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register, and the CCPRxH register with the PWM duty cycle value and configure the FMT bit of the CCPxCON register to set the proper register alignment. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR4 register. See Note below. * Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. * Configure the T2CKPS bits of the T2CON register with the Timer prescale value. * Enable the Timer by setting the ON bit of the T2CON register. Enable PWM output pin: * Wait until the Timer overflows and the TMR2IF bit of the PIR4 register is set. See Note below. * Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: 21.5.3 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 21-1. EQUATION 21-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note 1: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) * The PWM duty cycle is transferred from the CCPRxL/H register pair into a 10-bit buffer. Note: The Timer postscaler (see Section 20.3 "Timer2 Interrupt") is not used in the determination of the PWM frequency. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. TIMER2 TIMER RESOURCE The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 273 PIC18(L)F27/47K40 21.5.5 PWM DUTY CYCLE 21.5.6 PWM RESOLUTION The PWM duty cycle is specified by writing a 10-bit value to the CCPRxH:CCPRxL register pair. The alignment of the 10-bit value is determined by the FMT bit of the CCPxCON register (see Figure 21-5). The CCPRxH:CCPRxL register pair can be written to at any time; however the duty cycle value is not latched into the 10-bit buffer until after a match between PR2 and TMR2. The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. Equation 21-2 is used to calculate the PWM pulse width. EQUATION 21-4: The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 21-4. Equation 21-3 is used to calculate the PWM duty cycle ratio. FIGURE 21-5: log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 PWM 10-BIT ALIGNMENT Note: Rev. 10-000 160A 12/9/201 3 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 PWM RESOLUTION FMT = 0 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 If the pulse-width value is greater than the period the assigned PWM pin(s) will remain unchanged. 10-bit Duty Cycle 9 8 7 6 5 4 3 2 1 0 EQUATION 21-2: PULSE WIDTH Pulse Width = CCPRxH:CCPRxL register pair T OSC (TMR2 Prescale Value) EQUATION 21-3: DUTY CYCLE RATIO CCPRxH:CCPRxL register pair Duty Cycle Ratio = ---------------------------------------------------------------------------------4 PR2 + 1 CCPRxH:CCPRxL register pair are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH:CCPRxL register pair, then the CCPx pin is cleared (see Figure 21-4). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 274 PIC18(L)F27/47K40 TABLE 21-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Timer Prescale PR2 Value Maximum Resolution (bits) TABLE 21-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale PR2 Value Maximum Resolution (bits) 21.5.7 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 21.5.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 4.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for additional details. 21.5.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 275 PIC18(L)F27/47K40 TABLE 21-5: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH CCPx Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE6 -- -- -- -- -- -- CCP2IE CCP1IE 184 PIR6 -- -- -- -- -- -- CCP2IF CCP1IF 176 IPR6 -- -- -- -- -- -- CCP2IP CCP1IP 192 PMD3 -- -- -- -- PWM4MD PWM3MD CCP2MD CCP1MD CCPxCON EN -- OUT FMT CCPxCAP -- -- -- -- MODE<3:0> -- -- CCPRxL CCPRx<7:0> CCPRxH CCPRx<15:8> CCPTMRS P4TSEL<1:0> P3TSEL<1:0> 70 264 CTS<1:0> 267 267 268 C2TSEL<1:0> C1TSEL<1:0> 266 CCPxPPS -- -- -- CCPxPPS<4:0> RxyPPS -- -- -- RxyPPS<4:0> T1CON -- -- TMR1GE T1GPOL T1GTM T1GSPM T1CLK -- -- -- -- CS<3:0> T1GATE -- -- -- -- GSS<3:0> TMR1L TMR1L7 TMR1L6 TMR1L5 TMR1L4 TMR1L3 TMR1L2 TMR1L1 TMR1L0 232 TMR1H TMR1H7 TMR1H6 TMR1H5 TMR1H4 TMR1H3 TMR1H2 TMR1H1 TMR1H0 232 T1GCON T1CKPS<1:0> T1SYNC T1RD16 TMR1ON 228 T1GO/DONE T1GVAL -- -- 229 TMR2<7:0> T2PR PR2<7:0> ON T2HLT PSYNC CPOL CSYNC T2CLKCON -- -- -- -- T2RST -- -- -- -- Legend: 217 -- TMR2 T2CON 215 CKPS<2:0> 230 231 244 244 OUTPS<3:0> MODE<4:0> 245 246 CS<3:0> 248 RSEL<3:0> 249 -- = Unimplemented location, read as `0'. Shaded cells are not used by the CCP module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 276 PIC18(L)F27/47K40 22.0 PULSE-WIDTH MODULATION (PWM ) Each PWM module can select the timer source that controls the module. Each module has an independent timer selection which can be accessed using the CCPTMRS register (Register 21-2). Please note that the PWM mode operation is described with respect to TMR2 in the following sections. The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: * * * * * Figure 22-1 shows a simplified block diagram of PWM operation. PRx TxCON PWMxDCH PWMxDCL PWMxCON Note: Figure 22-2 shows a typical waveform of the PWM signal. The corresponding TRIS bit must be cleared to enable the PWM output on the PWMx pin. FIGURE 22-1: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle registers PWMxDCL<7:6> PWMxDCH Latched (Not visible to user) PWMxOUT to other peripherals R Comparator Q 0 PPS S Q 1 PWMx RxyPPS TMR2 Module TMR2 Output Polarity (PWMxPOL) (1) Comparator PR2 Note 1: FIGURE 22-2: Clear Timer, PWMx pin and latch Duty Cycle 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to create a 10-bit time base. PWM OUTPUT Period Pulse Width For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 22.1.9 "Setup for PWM Operation using PWMx Pins". TMR2 = PR2 TMR2 = PWMxDCH<7:0>:PWMxDCL<7:6> TMR2 = 0 2016 Microchip Technology Inc. Preliminary DS40001844B-page 277 PIC18(L)F27/47K40 22.1 PWMx Pin Configuration 22.1.3 All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. 22.1.1 FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. The PWM timer can be selected using the PxTSEL bits in the CCPTMRS register. The default selection for PWMx is TMR2. Please note that the PWM module operation in the following sections is described with respect to TMR2. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when TMR2 is cleared. Each PWMx is cleared when TMR2 is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to PR2, the PWM output is never cleared (100% duty cycle). Note: The PWMxDCH and PWMxDCL registers are double buffered. The buffers are updated when Timer2 matches PR2. Care should be taken to update both registers before the timer match occurs. 22.1.2 PWM OUTPUT POLARITY The output polarity is inverted by setting the PWMxPOL bit of the PWMxCON register. PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 22-1. It is required to have FOSC/4 as the clock input to TMR2/4/6 for correct PWM operation. EQUATION 22-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note: TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) * The PWMxDCH and PWMxDCL register values are latched into the buffers. Note: 22.1.4 The Timer2 postscaler has no effect on the PWM operation. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. Equation 22-2 is used to calculate the PWM pulse width. Equation 22-3 is used to calculate the PWM duty cycle ratio. EQUATION 22-2: PULSE WIDTH Pulse Width = PWMxDCH:PWMxDCL<7:6> T OS C (TMR2 Prescale Value) Note: TOSC = 1/FOSC EQUATION 22-3: DUTY CYCLE RATIO PWMxDCH:PWMxDCL<7:6> Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1 The 8-bit timer TMR2 register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 278 PIC18(L)F27/47K40 22.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 22-4. EQUATION 22-4: PWM RESOLUTION log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 Note: If the pulse-width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 22-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 0.31 kHz Timer Prescale PR2 Value 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 0.31 kHz Timer Prescale PR2 Value 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 22.1.6 19.53 kHz 0xFF Maximum Resolution (bits) TABLE 22-2: 4.88 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 22.1.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 4.0 "Oscillator Module (with Fail-Safe Clock Monitor)" for additional details. 22.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 279 PIC18(L)F27/47K40 22.1.9 SETUP FOR PWM OPERATION USING PWMx PINS 22.1.10 The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. 6. 7. 8. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR4 register. See Note 1 below. * Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. * Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. * Enable Timer2 by setting the T2ON bit of the T2CON register. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIR4 register is set. See note below. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired pin PPS control bits. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. SETUP FOR PWM OPERATION TO OTHER DEVICE PERIPHERALS The following steps should be taken when configuring the module for PWM operation to be used by other device peripherals: 1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). 2. Clear the PWMxCON register. 3. Load the PR2 register with the PWM period value. 4. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. 5. Configure and start Timer2: * Clear the TMR2IF interrupt flag bit of the PIR4 register. See Note 1 below. * Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. * Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. * Enable Timer2 by setting the T2ON bit of the T2CON register. 6. Enable PWM output pin: * Wait until Timer2 overflows, TMR2IF bit of the PIR4 register is set. See Note 1 below. 7. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. 2: For operation with other peripherals only, disable PWMx pin outputs. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 280 PIC18(L)F27/47K40 22.2 Register Definitions: PWM Control Long bit name prefixes for the PWM peripherals are shown in Table 22-3. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 22-3: Peripheral Bit Name Prefix PWM3 PWM3 PWM4 PWM4 REGISTER 22-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0 EN -- OUT POL -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 Unimplemented: Read as `0' bit 5 OUT: PWM Module Output Level When Bit is Read bit 4 POL: PWM Output Polarity Select bit 1 = PWM output is inverted 0 = PWM output is normal bit 3-0 Unimplemented: Read as `0' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 281 PIC18(L)F27/47K40 REGISTER 22-2: R/W-0/0 CCPTMRS: CCP TIMERS CONTROL REGISTER R/W-1/1 P4TSEL<1:0> R/W-0/0 R/W-1/1 P3TSEL<1:0> R/W-0/0 R/W-1/1 R/W-0/0 C2TSEL<1:0> R/W-1/1 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-6 P4TSEL<1:0>: PWM4 Timer Selection bits 11 = PWM4 based on TMR6 10 = PWM4 based on TMR4 01 = PWM4 based on TMR2 00 = Reserved bit 5-4 P3TSEL<1:0>: PWM3 Timer Selection bits 11 = PWM3 based on TMR6 10 = PWM3 based on TMR4 01 = PWM3 based on TMR2 00 = Reserved bit 3-2 C2TSEL<1:0>: CCP2 Timer Selection bits 11 = CCP2 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode 10 = CCP2 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode 01 = CCP2 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode 00 = Reserved bit 1-0 C1TSEL<1:0>: CCP1 Timer Selection bits 11 = CCP1 is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode 10 = CCP1 is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode 01 = CCP1 is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode 00 = Reserved 2016 Microchip Technology Inc. Preliminary DS40001844B-page 282 PIC18(L)F27/47K40 REGISTER 22-3: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 DCh<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register. REGISTER 22-4: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u DCL<7:6> U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 DC<8:9>: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register. bit 5-0 Unimplemented: Read as `0' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 283 PIC18(L)F27/47K40 TABLE 22-4: Name CCPTMRS PWM3CON SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 P4TSEL<1:0> EN -- Bit 5 OUT DC<9:8>> EN -- Register on Page C2TSEL<1:0> C1TSEL<1:0> 282 -- -- 281 -- -- 283 -- -- -- -- -- -- 283 POL -- -- -- -- 281 DC<9:8> -- -- -- -- -- -- 283 INT2EDG INT1EDG INT0EDG 169 283 GIE/GIEH PEIE/GIEL IPEN -- -- -- -- TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE 182 TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 174 TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP 190 PIR4 -- -- TMR6IF IPR4 -- -- TMR6IP -- -- -- TMR2 RxyPPS<4:0> 217 TMR2<7:0> PR2 244 PR2<7:0> T2CON T2ON T2HLT T2OUTPS<3:0> T2PSYNC T2CPOL T2CSYNC -- -- -- -- T2RST -- -- -- -- -- 244 T2CKPS<2:0> T2CLKCON PMD3 Bit 0 DC<7:0> PWM4DCL RxyPPS Bit 1 OUT PWM4DCH PIE4 POL Bit 2 DC<7:0> PWM3DCL INTCON Bit 3 P3TSEL<1:0> PWM3DCH PWM4CON Bit 4 -- -- 245 T2MODE<4:0> -- 246 248 T2CS<3:0> 249 T2RSEL<3:0> PWM4MD PWM3MD CCP2MD CCP1MD 70 Legend: - = Unimplemented locations, read as `0', u = unchanged, x = unknown. Shaded cells are not used by the PWM. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 284 PIC18(L)F27/47K40 23.0 ZERO-CROSS DETECTION (ZCD) MODULE 23.1 The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero crossing threshold is the zero crossing reference voltage, VCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current-limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD module is shown in the simplified block diagram Figure 23-2. The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: * * * * A/C period measurement Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching External Resistor Selection The ZCD module requires a current-limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 A. Refer to Equation 23-1 and Figure 23-1. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. EQUATION 23-1: EXTERNAL RESISTOR V PEAK R SERIES = ----------------4 3 10 FIGURE 23-1: VPEAK EXTERNAL VOLTAGE VMAXPEAK VMINPEAK VCPINV 2016 Microchip Technology Inc. Preliminary DS40001844B-page 285 PIC18(L)F27/47K40 FIGURE 23-2: SIMPLIFIED ZCD BLOCK DIAGRAM VPULLUP Rev. 10-000194B 5/14/2014 optional VDD RPULLUP - Zcpinv ZCDxIN RSERIES RPULLDOWN + External voltage source optional ZCDx_output D Q ZCDxPOL ZCDxOUT bit Q1 Interrupt det ZCDxINTP ZCDxINTN Set ZCDIF flag Interrupt det 2016 Microchip Technology Inc. Preliminary DS40001844B-page 286 PIC18(L)F27/47K40 23.2 ZCD Logic Output 23.5 The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The ZCDOUT bit of the ZCDCON register is set when the current sink is active, and cleared when the current source is active. The ZCDOUT bit is affected by the polarity bit. The ZCDOUT signal can also be used as input to other modules. This is controlled by the registers of the corresponding module. ZCDOUT can be used as follows: * Gate source for TMR1/3/5 * Clock source for TMR2/4/6 * Reset source for TMR2/4/6 23.3 Correcting for VCPINV offset The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown in Equation 23-2. EQUATION 23-2: ZCD Logic Polarity The ZCDPOL bit of the ZCDCON register inverts the ZCDOUT bit relative to the current source and sink output. When the ZCDPOL bit is set, a ZCDOUT high indicates that the current source is active, and a low output indicates that the current sink is active. ZCD EVENT OFFSET When External Voltage Source is relative to Vss: T OFFSET V CPINV asin ------------------- V PEAK = ----------------------------------2 Freq The ZCDPOL bit affects the ZCD interrupts. 23.4 When External Voltage Source is relative to VDD: ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIR2 register will be set when either edge detector is triggered and its associated enable bit is set. The ZCDINTP enables rising edge interrupts and the ZCDINTN bit enables falling edge interrupts. Both are located in the ZCDCON register. Priority of the interrupt can be changed if the IPEN bit of the INTCON register is set. The ZCD interrupt can be made high or low priority by setting or clearing the ZCDIP bit of the IPR2 register. To fully enable the interrupt, the following bits must be set: * ZCDIE bit of the PIE2 register * ZCDINTP bit of the ZCDCON register (for a rising edge detection) * ZCDINTN bit of the ZCDCON register (for a falling edge detection) * PEIE and GIE bits of the INTCON register T OFFSET This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the VCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown in Equation 23-3 or Equation 23-4. EQUATION 23-3: ZCD PULL-UP/DOWN When External Signal is relative to Vss: R SERIE S V PULLUP - V CPINV R PULLUP = -------------------------------------------------------------------------- Changing the ZCDPOL bit will cause an interrupt, regardless of the level of the ZCDSEN bit. V CPINV When External Signal is relative to VDD: The ZCDIF bit of the PIR2 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 2016 Microchip Technology Inc. V DD - V CPINV asin --------------------------------- V PEAK = ------------------------------------------------2 Freq Preliminary R SERIES V CPINV R PULLDOWN = -------------------------------------------- V DD - V CPINV DS40001844B-page 287 PIC18(L)F27/47K40 The pull-up and pull-down resistor values are significantly affected by small variations of VCPINV. Measuring VCPINV can be difficult, especially when the waveform is relative to VDD. However, by combining Equations 23-2 and 23-3, the resistor value can be determined from the time difference between the ZCD_output high and low periods. Note that the time difference, T, is 4*TOFFSET. The equation for determining the pull-up and pull-down resistor values from the high and low ZCD_output periods is shown in Equation 23-4. EQUATION 23-4: PULL-UP/DOWN RESISTOR VALUES 23.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 23.8 Effects of a Reset The ZCD circuit can be configured to default to the active or inactive state on Power-on-Reset (POR). When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the ZCDSEN bit of the ZCDCON register must be set to enable the ZCD module. 23.9 Disabling the ZCD Module The ZCD module can be disabled in two ways: V BI A S R = R SERIES ---------------------------------------------------------------- - 1 T V PE AK sin Freq ---------- 2 1. 2. R is pull-up or pull-down resistor. VBIAS is VPULLUP when R is pull-up or VDD when R is pull-down. Configuration Word 2H has the ZCD bit which disables the ZCD module when set, but it can be enabled using the ZCDSEN bit of the ZCDCON register (Register 23-1). If the ZCD bit is clear, the ZCD is always enabled. The ZCD can also be disabled using the ZCDMD bit of the PMD2 register (Register 7-3). This is subject to the status of the ZCD bit. T is the ZCDOUT high and low period difference. 23.6 Handling VPEAK Variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of 600 A and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed 600 A and the minimum is at least 100 A, compute the series resistance as shown in Equation 23-5. The compensating pull-up for this series resistance can be determined with Equation 23-3 because the pull-up value is independent from the peak voltage. EQUATION 23-5: SERIES R FOR V RANGE V MAXPEAK + V MINPEAK R SERIES = ---------------------------------------------------------4 7 10 2016 Microchip Technology Inc. Preliminary DS40001844B-page 288 PIC18(L)F27/47K40 23.10 Register Definitions: ZCD Control REGISTER 23-1: ZCDCON: ZERO-CROSS DETECT CONTROL REGISTER R/W-0/0 U-0 R-x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ZCDSEN -- ZCDOUT ZCDPOL -- -- ZCDINTP ZCDINTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 ZCDSEN: Zero-Cross Detect Software Enable bit This bit is ignored when ZCDSEN fuse is set. 1= Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0= Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. bit 6 Unimplemented: Read as `0' bit 5 ZCDOUT: Zero-Cross Detect Data Output bit ZCDPOL bit = 0: 1 = ZCD pin is sinking current 0 = ZCD pin is sourcing current ZCDPOL bit = 1: 1 = ZCD pin is sourcing current 0 = ZCD pin is sinking current bit 4 ZCDPOL: Zero-Cross Detect Polarity bit 1 = ZCD logic output is inverted 0 = ZCD logic output is not inverted bit 3-2 Unimplemented: Read as `0' bit 1 ZCDINTP: Zero-Cross Detect Positive-Going Edge Interrupt Enable bit 1 = ZCDIF bit is set on low-to-high ZCD_output transition 0 = ZCDIF bit is unaffected by low-to-high ZCD_output transition bit 0 ZCDINTN: Zero-Cross Detect Negative-Going Edge Interrupt Enable bit 1 = ZCDIF bit is set on high-to-low ZCD_output transition 0 = ZCDIF bit is unaffected by high-to-low ZCD_output transition 2016 Microchip Technology Inc. Preliminary DS40001844B-page 289 PIC18(L)F27/47K40 TABLE 23-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page 180 PIE2 HLVDIE ZCDIE -- -- -- -- C2IE C1IE PIR2 HLVDIF ZCDIF -- -- -- -- C2IF C1IF 172 IPR2 HLVDIP ZCDIP -- -- -- -- C2IP C1IP 188 ZCDCON ZCDSEN -- ZCDOUT ZCDPOL -- -- ZCDINTP ZCDINTN 289 -- DACMD ADCMD -- -- CMP2MD CMP1MD ZCDMD 69 PMD2 Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the ZCD module. TABLE 23-2: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE Name Bits Bit 15/7 Bit 14/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register on Page CONFIG2 15:8 XINST -- DEBUG STVREN PPS1WAY ZCD BORV1 BORV0 24 -- -- -- PWRTE MCLRE 7:0 Legend: BOREN1 BOREN0 LPBOREN -- = unimplemented location, read as `0'. Shaded cells are not used by the ZCD module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 290 PIC18(L)F27/47K40 24.0 COMPLEMENTARY WAVEFORM GENERATOR (CWG) MODULE 24.2 The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms. It is backwards compatible with previous CCP functions. The PIC18(L)F2x/4xK40 family has one instance of the CWG module. The CWG has the following features: * Six operating modes: - Synchronous Steering mode - Asynchronous Steering mode - Full-Bridge mode, Forward - Full-Bridge mode, Reverse - Half-Bridge mode - Push-Pull mode * Output polarity control * Output steering * Independent 6-bit rising and falling event deadband timers - Clocked dead band - Independent rising and falling dead-band enables * Auto-shutdown control with: - Selectable shutdown sources - Auto-restart option - Auto-shutdown pin override control 24.1 Operating Modes The CWG module can operate in six different modes, as specified by the MODE<2:0> bits of the CWG1CON0 register: * * * * * * Half-Bridge mode Push-Pull mode Asynchronous Steering mode Synchronous Steering mode Full-Bridge mode, Forward Full-Bridge mode, Reverse All modes accept a single pulse data input, and provide up to four outputs as described in the following sections. All modes include auto-shutdown control as described in Section 24.10 "Auto-Shutdown" Note: 24.2.1 Except as noted for Full-bridge mode (Section 24.2.3 "Full-Bridge Modes"), mode changes should only be performed while EN = 0 (Register 24-1). HALF-BRIDGE MODE In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 24-2. A non-overlap (dead-band) time is inserted between the two outputs to prevent shoot through current in various power supply applications. Dead-band control is described in Section 24.6 "Dead-Band Control". The output steering feature cannot be used in this mode. A basic block diagram of this mode is shown in Figure 24-1. Fundamental Operation The CWG generates two output waveforms from the selected input source. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in Section 24.6 "Dead-Band Control". The unused outputs CWG1C and CWG1D drive similar signals, with polarity independently controlled by the POLC and POLD bits of the CWG1CON1 register, respectively. It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in Section 24.10 "Auto-Shutdown". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 291 PIC18(L)F27/47K40 FIGURE 24-1: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE, MODE<2:0> = 100) LSAC<1:0> Rev. 10-000209C 8/7/2015 `1' 00 `0' 01 High-Z 10 11 Rising Dead-Band Block CWG Clock clock 1 CWG Data A data out CWG Data data in 0 POLA CWG1A LSBD<1:0> `1' 00 `0' 01 High-Z 10 Falling Dead-Band Block clock CWG Data B data out data in 11 1 CWG Data CWG Data Input 0 POLB D Q E LSAC<1:0> EN `1' 00 `0' 01 High-Z 10 SHUTDOWN = 1 AS0E PPS CWG1PPS AS1E TMR2_postscaled CWG1B 11 1 Autoshutdown source 0 CWG1C POLC AS2E TMR4_postscaled LSBD<1:0> AS3E TMR6_postscaled AS4E CMP1OUT AS5E CMP2OUT S 00 `0' 01 High-Z 10 11 Q 1 R 0 CWG1D POLD REN SHUTDOWN = 0 `1' SHUTDOWN FREEZE D Q CWG Data 2016 Microchip Technology Inc. Preliminary DS40001844B-page 292 PIC18(L)F27/47K40 FIGURE 24-2: CWG1 HALF-BRIDGE MODE OPERATION CWGx_clock CWGxA CWGxC Falling Event Dead Band Rising Event Dead Band Rising Event D Falling Event Dead Band CWGxB CWGxD CWGx_data Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out 24.2.2 PUSH-PULL MODE In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 24-4. This alternation creates the push-pull effect required for driving some transformer-based power supply designs. Steering modes are not used in Push-Pull mode. A basic block diagram for the Push-Pull mode is shown in Figure 24-3. The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWG1A. The unused outputs CWG1C and CWG1D drive copies of CWG1A and CWG1B, respectively, but with polarity controlled by the POLC and POLD bits of the CWG1CON1 register, respectively. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 293 PIC18(L)F27/47K40 FIGURE 24-3: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE, MODE<2:0> = 101) LSAC<1:0> Rev. 10-000210C 8/7/2015 `1' 00 `0' 01 High-Z 10 11 1 CWG Data A CWG Data 0 CWG1A POLA D LSBD<1:0> Q Q `1' 00 `0' 01 High-Z 10 11 CWG Data B 1 CWG Data Input CWG Data D 0 CWG1B POLB Q LSAC<1:0> E `1' 00 `0' 01 High-Z 10 EN 11 SHUTDOWN = 1 1 AS0E PPS CWG1PPS 0 CWG1C POLC Autoshutdown source AS1E TMR2_postscaled LSBD<1:0> AS2E TMR4_postscaled `1' 00 `0' 01 High-Z 10 AS3E TMR6_postscaled AS4E CMP1OUT S AS5E CMP2OUT 11 Q 1 R 0 CWG1D POLD REN SHUTDOWN = 0 SHUTDOWN FREEZE D Q CWG Data 2016 Microchip Technology Inc. Preliminary DS40001844B-page 294 PIC18(L)F27/47K40 FIGURE 24-4: CWG1 PUSH-PULL MODE OPERATION CWG1 clock Input source CWG1A CWG1B 24.2.3 FULL-BRIDGE MODES In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the input data signal. The mode selection may be toggled between forward and reverse by toggling the MODE<0> bit of the CWG1CON0 while keeping MODE<2:1> static, without disabling the CWG module. When connected as shown in Figure 24-5, the outputs are appropriate for a full-bridge motor driver. Each CWG output signal has independent polarity control, so the circuit can be adapted to high-active and low-active drivers. A simplified block diagram for the Full-Bridge modes is shown in Figure 24-6. FIGURE 24-5: EXAMPLE OF FULL-BRIDGE APPLICATION Rev. 10-000263A 12/8/2015 VDD FET Driver QA QC FET Driver CWG1A CWG1B CWG1C CWG1D 2016 Microchip Technology Inc. LOAD FET Driver FET Driver QB Preliminary QD DS40001844B-page 295 PIC18(L)F27/47K40 FIGURE 24-6: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE MODES) MODE<2:0> = 010: Forward Rev. 10-000212C 8/7/2015 LSAC<1:0> MODE<2:0> = 011: Reverse Rising Dead-Band Block CWG Clock clock signal out signal in D CWG Data 00 `0' 01 High-Z 10 11 CWG Data MODE<2:0> `1' 1 CWG Data A 0 CWG1A POLA Q Q LSBD<1:0> cwg data signal in signal out clock CWG Clock `1' 00 `0' 01 High-Z 10 11 Falling Dead-Band Block CWG Data Input CWG Data 1 CWG Data B 0 CWG1B POLB D Q LSAC<1:0> E EN `1' 00 `0' 01 High-Z 10 11 SHUTDOWN = 1 AS0E PPS CWG1PPS AS1E TMR2_postscaled 1 CWG Data C Autoshutdown source 0 CWG1C POLC LSBD<1:0> AS2E TMR4_postscaled AS3E TMR6_postscaled AS4E CMP1OUT AS5E CMP2OUT S SHUTDOWN = 0 `0' 01 High-Z 10 1 CWG Data D REN 00 11 Q R `1' 0 CWG1D POLD SHUTDOWN FREEZE D Q CWG Data 2016 Microchip Technology Inc. Preliminary DS40001844B-page 296 PIC18(L)F27/47K40 In Forward Full-Bridge mode (MODE<2:0> = 010), CWG1A is driven to its active state, CWG1B and CWG1C are driven to their inactive state, and CWG1D is modulated by the input signal, as shown in Figure 24-7. In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or viceversa. This dead-band control is described in Section 24.6 "Dead-Band Control", with additional details in Section 24.7 "Rising Edge and Reverse Dead Band" and Section 24.8 "Falling Edge and Forward Dead Band". Steering modes are not used with either of the Full-Bridge modes. The mode selection may be toggled between forward and reverse toggling the MODE<0> bit of the CWG1CON0 while keeping MODE<2:1> static, without disabling the CWG module. In Reverse Full-Bridge mode (MODE<2:0> = 011), CWG1C is driven to its active state, CWG1A and CWG1D are driven to their inactive states, and CWG1B is modulated by the input signal, as shown in Figure 24-7. FIGURE 24-7: EXAMPLE OF FULL-BRIDGE OUTPUT Forward Mode Period CWG1A(2) CWG1B(2) CWG1C(2) Pulse Width CWG1D(2) (1) Reverse Mode (1) Period CWG1A(2) Pulse Width CWG1B(2) CWG1C(2) CWG1D(2) (1) Note 1: 2: (1) A rising CWG data input creates a rising event on the modulated output. Output signals shown as active-high; all POLy bits are clear. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 297 PIC18(L)F27/47K40 24.2.3.1 Direction Change in Full-Bridge Mode In Full-Bridge mode, changing MODE<2:0> controls the forward/reverse direction. Changes to MODE<2:0> change to the new direction on the next rising edge of the modulated input. A direction change is initiated in software by changing the MODE<2:0> bits of the CWG1CON0 register. The sequence is illustrated in Figure 24-8. * The associated active output CWG1A and the inactive output CWG1C are switched to drive in the opposite direction. * The previously modulated output CWG1D is switched to the inactive state, and the previously inactive output CWG1B begins to modulate. * CWG modulation resumes after the directionswitch dead band has elapsed. 24.2.3.2 Dead-Band Delay in Full-Bridge Mode Dead-band delay is important when either of the following conditions is true: 1. 2. The dead-band delay is inserted only when changing directions, and only the modulated output is affected. The statically-configured outputs (CWG1A and CWG1C) are not afforded dead band, and switch essentially simultaneously. Figure 24-8 shows an example of the CWG outputs changing directions from forward to reverse, at near 100% duty cycle. In this example, at time t1, the output of CWG1A and CWG1D become inactive, while output CWG1C becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shootthrough current will flow through power devices QC and QD for the duration of `t'. The same phenomenon will occur to power devices QA and QB for the CWG direction change from reverse to forward. When changing the CWG direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. Reduce the CWG duty cycle for one period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. The direction of the CWG output changes when the duty cycle of the data input is at or near 100%, or The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. FIGURE 24-8: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period CWG1A CWG1B Pulse Width CWG1C CWG1D Pulse Width TON External Switch C TOFF External Switch D Potential ShootThrough Current 2016 Microchip Technology Inc. T = TOFF - TON Preliminary DS40001844B-page 298 PIC18(L)F27/47K40 24.2.4 STEERING MODES 24.2.4.1 In both Synchronous and Asynchronous Steering modes, the modulated input signal can be steered to any combination of four CWG outputs and a fixed-value will be presented on all the outputs not used for the PWM output. Each output has independent polarity, steering, and shutdown options. Dead-band control is not used in either steering mode. Synchronous Steering Mode In Synchronous Steering mode (MODE<2:0> bits = 001, Register 24-1), changes to steering selection registers take effect on the next rising edge of the modulated data input (Figure 24-9). In Synchronous Steering mode, the output will always produce a complete waveform. When STRx = 0 (Register 24-5), then the corresponding pin is held at the level defined by DATx (Register 24-5). When STRx = 1, then the pin is driven by the modulated input signal. The POLx bits (Register 24-2) control the signal polarity only when STRx = 1. The CWG auto-shutdown operation also applies to steering modes as described in Section 24.14 "Register Definitions: CWG Control". Note: Only the STRx bits are synchronized; the SDATx (data) bits are not synchronized. The CWG auto-shutdown operation also applies in Steering modes as described in Section 24.10 "AutoShutdown"". An auto-shutdown event will only affect pins that have STRx = 1. FIGURE 24-9: EXAMPLE OF SYNCHRONOUS STEERING (MODE<2:0> = 001) CWG1 clock Input source CWG1A CWG1B 2016 Microchip Technology Inc. Preliminary DS40001844B-page 299 PIC18(L)F27/47K40 24.2.4.2 Asynchronous Steering Mode In Asynchronous mode (MODE<2:0> bits = 000, Register 24-1), steering takes effect at the end of the instruction cycle that writes to STR. In Asynchronous Steering mode, the output signal may be an incomplete waveform (Figure 24-10). This operation may be useful when the user firmware needs to immediately remove a signal from the output pin. FIGURE 24-10: EXAMPLE OF ASYNCHRONOUS STEERING (MODE<2:0>= 000) CWG1 INPUT End of Instruction Cycle End of Instruction Cycle STRA CWG1A CWG1A Follows CWG1 data input 24.2.4.3 Start-up Considerations The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG output pins. This is required because all I/O pins are forced to high-impedance at Reset. The POLy bits (Register 24-2) allow the user to choose whether the output signals are active-high or activelow. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 300 PIC18(L)F27/47K40 FIGURE 24-11: SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES) Rev. 10-000211C 8/7/2015 MODE<2:0> = 000: Asynchronous LSAC<1:0> MODE<2:0> = 001: Synchronous `1' 00 `0' 01 High-Z 10 11 CWG Data A 1 1 POLA DATA 0 CWG1A 0 STRA CWG Data CWG Data Input LSBD<1:0> `1' 00 `0' 01 High-Z 10 11 D CWG Data B Q E 1 1 POLB DATB EN 0 CWG1B 0 STRB LSAC<1:0> `1' 00 `0' 01 High-Z 10 SHUTDOWN = 1 AS0E PPS CWG1PPS AS1E TMR2_postscaled 11 Autoshutdown source CWG Data C 1 1 POLC AS2E TMR4_postscaled DATC 0 CWG1C 0 STRC AS3E TMR6_postscaled LSBD<1:0> AS4E CMP1OUT `1' 00 `0' 01 AS5E CMP2OUT High-Z 10 S 11 Q CWG Data D R 1 POLD REN SHUTDOWN = 0 DATD 0 1 0 CWG1D SHUTDOWN STRD FREEZE D Q CWG Data 2016 Microchip Technology Inc. Preliminary DS40001844B-page 301 PIC18(L)F27/47K40 24.3 Clock Source 24.5 The clock source is used to drive the dead-band timing circuits. The CWG module allows the following clock sources to be selected: * FOSC (system clock) * HFINTOSC When the HFINTOSC is selected, the HFINTOSC will be kept running during Sleep. Therefore, CWG modes requiring dead band can operate in Sleep, provided that the CWG data input is also active during Sleep.The clock sources are selected using the CS bit of the CWG1CLKCON register (Register 24-3). The system clock FOSC, is disabled in Sleep and thus dead-band control cannot be used. 24.4 Selectable Input Sources The CWG generates the output waveforms from the input sources in Table 24-1. TABLE 24-1: Source Peripheral SELECTABLE INPUT SOURCES Signal Name ISM<2:0> 24.5.1 Output Control CWG OUTPUTS Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register (see Section 17.0 "Peripheral Pin Select (PPS) Module"). 24.5.2 POLARITY CONTROL The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the POLy bits of the CWG1CON1. Auto-shutdown and steering options are unaffected by polarity. 24.6 Dead-Band Control The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM switches. Dead-band operation is employed for HalfBridge and Full-Bridge modes. The CWG contains two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge mode or for reverse dead-band Full-Bridge mode. The other is used for the falling edge of the input source control in Half-Bridge mode or for forward dead band in FullBridge mode. CWG1PPS Pin selected by CWG1PPS 000 CCP1 CCP1 Output 001 CCP2 CCP2 Output 010 PWM3 PWM4 PWM3 Output 011 PWM4 Output 100 Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. See CWG1DBR and CWG1DBF registers, respectively. CMP1 Comparator 1 Output 101 24.6.1 CMP2 Comparator 2 Output 110 DSM Data signal modulator output 111 The input sources are selected using the ISM<2:0> bits in the CWG1ISM register (Register 24-4). DEAD-BAND FUNCTIONALITY IN HALF-BRIDGE MODE In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the rising edge of the inverted output. This can be seen in Figure 24-2. 24.6.2 DEAD-BAND FUNCTIONALITY IN FULL-BRIDGE MODE In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE<0> bit of the CWG1CON0 register can be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWG1A and CWG1C signals will change immediately upon the first rising input edge following a direction change, but the modulated signals (CWG1B or CWG1D, depending on the direction of the change) will experience a delay dictated by the dead-band counters. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 302 PIC18(L)F27/47K40 24.7 Rising Edge and Reverse Dead Band In Half-Bridge mode, the rising edge dead band delays the turn-on of the CWG1A output after the rising edge of the CWG data input. In Full-Bridge mode, the reverse dead-band delay is only inserted when changing directions from Forward mode to Reverse mode, and only the modulated output CWG1B is affected. The CWG1DBR register determines the duration of the dead-band interval on the rising edge of the input source signal. This duration is from 0 to 64 periods of the CWG clock. Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. The CWG1DBR register value is double-buffered. When EN = 0 (Register 24-1), the buffer is loaded when CWG1DBR is written. If EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input, after the LD bit (Register 24-1) is set. Refer to Figure 24-12 for an example. 24.8 Falling Edge and Forward Dead Band In Half-Bridge mode, the falling edge dead band delays the turn-on of the CWG1B output at the falling edge of the CWG data input. In Full-Bridge mode, the forward dead-band delay is only inserted when changing directions from Reverse mode to Forward mode, and only the modulated output CWG1D is affected. The CWG1DBF register determines the duration of the dead-band interval on the falling edge of the input source signal. This duration is from zero to 64 periods of CWG clock. Dead-band delay is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. The CWG1DBF register value is double-buffered. When EN = 0 (Register 24-1), the buffer is loaded when CWG1DBF is written. If EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input after the LD (Register 241) is set. Refer to Figure 24-13 for an example. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 303 2016 Microchip Technology Inc. FIGURE 24-12: DEAD-BAND OPERATION, CWG1DBR = 0x01, CWG1DBF = 0x02 cwg_clock Input Source CWGxA CWGxB Preliminary FIGURE 24-13: DEAD-BAND OPERATION, CWG1DBR = 0x03, CWG1DBF = 0x06, SOURCE SHORTER THAN DEAD BAND Input Source CWGxA DS40001844B-page 304 CWGxB source shorter than dead band PIC18(L)F27/47K40 cwg_clock PIC18(L)F27/47K40 24.9 Dead-Band Jitter When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates jitter in the dead-band time delay. The maximum jitter is equal to one CWG clock period. Refer to Equation 24-1 for more details. EQUATION 24-1: T T T T JITTER JITTER T 1 = ------------------------------------------ DBx 4: 0> F CWG CLOCK DEAD - BAND_MIN DEAD - BANDMAX = T DEAD-BAND DELAY TIME CALCULATION 1 = ------------------------------------------ DBx 4: 0>+1 F CWG CLOCK DEAD - BAND _ MAX - TDEAD - BAND _ MIN 1 = -------------------------------------------F CWG _ CLOCK DEAD - BAND _ MAX = T DEAD - BAND _ MIN +T JITTER EXAMPLE DBR<4:0> = 0x0A = 10 F T JITTER T T CWG_CLOCK = 8 MHz 1 = ---------------- = 125 ns 8MHz DEAD - BAND_MIN DEAD - BAND_MAX = 125 ns*10 = 125 s = 1.25 s + 0.125s = 1.37s 2016 Microchip Technology Inc. Preliminary DS40001844B-page 305 PIC18(L)F27/47K40 24.10 Auto-Shutdown 24.10.1.3 Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. The auto-shutdown circuit is illustrated in Figure 24-14. The levels driven to the CWG outputs during an autoshutdown event are controlled by the LSBD<1:0> and LSAC<1:0> bits of the CWG1AS0 register (Register 24-6). The LSBD<1:0> bits control CWG1B/ D output levels, while the LSAC<1:0> bits control the CWG1A/C output levels. 24.10.1 24.10.1.4 SHUTDOWN The shutdown state can be entered by either of the following two methods: * Software generated * External Input 24.10.1.1 Software Generated Shutdown When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set. When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. The SHUTDOWN bit indicates when a shutdown condition exists. The bit may be set or cleared in software or by hardware. External Input Source External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. The override levels are selected by the LSBD<1:0> and LSAC<1:0> bits of the CWG1AS0 register (Register 24-6). Several input sources can be selected to cause a shutdown condition. All input sources are active-low. The sources are: * * * * * * Pin selected by CWG1PPS Timer2 post-scaled output Timer4 post-scaled output Timer6 post-scaled output Comparator 1 output Comparator 2 output After an auto-shutdown event has occurred, there are two ways to resume operation: * Software controlled * Auto-restart In either case, the shut-down source must be cleared before the restart can take place. That is, either the shutdown condition must be removed, or the corresponding ASxE bit must be cleared. 24.11.1 SOFTWARE-CONTROLLED RESTART If the REN bit of the CWG1AS0 register is clear (REN = 0), the CWG module must be restarted after an auto-shutdown event through software. Once all auto-shutdown sources are removed, the software must clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Note: The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. AUTO-RESTART If the REN bit of the CWG1AS0 register is set (REN = 1), the CWG module will restart from the shutdown state automatically. Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling autoshutdown, as long as the shutdown input level persists. 2016 Microchip Technology Inc. When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWG1IF flag bit of the PIR7 register is set (Register 14-5). 24.11.2 Shutdown input sources are individually enabled by the ASxE bits of the CWG1AS1 register (Register 24-7). Note: Auto-Shutdown Interrupts 24.11 Auto-Shutdown Restart Setting the SHUTDOWN bit of the CWG1AS0 register will force the CWG into the shutdown state. 24.10.1.2 Pin Override Levels Once all auto-shutdown conditions are removed, the hardware will automatically clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Note: Preliminary The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. DS40001844B-page 306 PIC18(L)F27/47K40 24.12 Operation During Sleep 24.13 The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. 1. The HFINTOSC remains active during Sleep when all the following conditions are met: * CWG module is enabled * Input source is active * HFINTOSC is selected as the clock source, regardless of the system clock source selected. 2. 3. 4. In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, then the CPU will go idle during Sleep, but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current. 5. 6. 7. 8. 9. 10. 11. 12. 13. Configuring the CWG Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured as inputs, ensuring that the outputs are inactive during setup. External hardware should ensure that pin levels are held to safe levels. Clear the EN bit, if not already cleared. Configure the MODE<2:0> bits of the CWG1CON0 register to set the output operating mode. Configure the POLy bits of the CWG1CON1 register to set the output polarities. Configure the ISM<2:0> bits of the CWG1ISM register to select the data input source. If a steering mode is selected, configure the STRx bits to select the desired output on the CWG outputs. Configure the LSBD<1:0> and LSAC<1:0> bits of the CWG1ASD0 register to select the autoshutdown output override states (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). If auto-restart is desired, set the REN bit of CWG1AS0. If auto-shutdown is desired, configure the ASxE bits of the CWG1AS1 register to select the shutdown source. Set the desired rising and falling dead-band times with the CWG1DBR and CWG1DBF registers. Select the clock source in the CWG1CLKCON register. Set the EN bit to enable the module. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit in software to start the CWG. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 307 2016 Microchip Technology Inc. FIGURE 24-14: CWG SHUTDOWN BLOCK DIAGRAM Write `1' to SHUTDOWN bit Rev. 10-000172C 8/7/2015 PPS AS0E CWGxINPPS C1OUT_sync AS4E C2OUT_sync AS5E TMR2_postscaled AS1E S Q SHUTDOWN S D Q FREEZE REN TMR4_postscaled AS2E CWG_shutdown R Write `0' to SHUTDOWN bit CWG_data TMR6_postscaled AS3E CK FIGURE 24-15: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01) Preliminary Shutdown Event Ceases REN Cleared by Software CWG Input Source SHUTDOWN Tri-State (No Pulse) CWG1A CWG1C CWG1B CWG1D Tri-State (No Pulse) No Shutdown DS40001844B-page 308 Shutdown Output Resumes PIC18(L)F27/47K40 Shutdown Source 2016 Microchip Technology Inc. FIGURE 24-16: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01) Shutdown Event Ceases REN auto-cleared by hardware CWG Input Source Shutdown Source SHUTDOWN CWG1A CWG1C CWG1B CWG1D Tri-State (No Pulse) Tri-State (No Pulse) No Shutdown Shutdown Output Resumes Preliminary PIC18(L)F27/47K40 DS40001844B-page 309 PIC18(L)F27/47K40 24.14 Register Definitions: CWG Control Long bit name prefixes for the CWG peripheral is shown in Table 24-2. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 24-2: Peripheral Bit Name Prefix CWG CWG l REGISTER 24-1: CWG1CON0: CWG CONTROL REGISTER 0 R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 EN LD(1) -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 MODE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 EN: CWG1 Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 LD: CWG1 Load Buffers bit(1) 1 = Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set 0 = Buffers remain unchanged bit 5-3 Unimplemented: Read as `0' bit 2-0 MODE<2:0>: CWG1 Mode bits 111 = Reserved 110 = Reserved 101 = CWG outputs operate in Push-Pull mode 100 = CWG outputs operate in Half-Bridge mode 011 = CWG outputs operate in Reverse Full-Bridge mode 010 = CWG outputs operate in Forward Full-Bridge mode 001 = CWG outputs operate in Synchronous Steering mode 000 = CWG outputs operate in Asynchronous Steering mode Note 1: This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 310 PIC18(L)F27/47K40 REGISTER 24-2: U-0 -- CWG1CON1: CWG CONTROL REGISTER 1 U-0 R-x -- IN U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- POLD POLC POLB POLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5 IN: CWG Input Value bit (read-only) bit 4 Unimplemented: Read as `0' bit 3 POLD: CWG1D Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 2 POLC: CWG1C Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 1 POLB: CWG1B Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity bit 0 POLA: CWG1A Output Polarity bit 1 = Signal output is inverted polarity 0 = Signal output is normal polarity 2016 Microchip Technology Inc. Preliminary DS40001844B-page 311 PIC18(L)F27/47K40 REGISTER 24-3: CWG1CLKCON: CWG1 CLOCK INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 -- -- -- -- -- -- -- CS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-1 Unimplemented: Read as `0' bit 0 CS: CWG Clock Source Selection Select bits CS REGISTER 24-4: Clock Source 1 HFINTOSC (remains operating during Sleep) 0 FOSC CWG1ISM: CWGx INPUT SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 ISM<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-3 Unimplemented Read as `0' bit 2-0 ISM<2:0>: CWG Data Input Selection Multiplexer Select bits ISM<2:0> Input Source 111 DSM OUT 110 CMP2 OUT 101 CMP1 OUT 100 PWM4 OUT 011 PWM3 OUT 010 CCP2 OUT 001 CCP1 OUT 000 Pin selected by CWG1PPS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 312 PIC18(L)F27/47K40 CWG1STR(1): CWG STEERING CONTROL REGISTER REGISTER 24-5: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 OVRD OVRC OVRB OVRA STRD(2) STRC(2) STRB(2) STRA(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 OVRD: Steering Data D bit bit 6 OVRC: Steering Data C bit bit 5 OVRB: Steering Data B bit bit 4 OVRA: Steering Data A bit bit 3 STRD: Steering Enable bit D(2) 1 = CWG1D output has the CWG data input waveform with polarity control from POLD bit 0 = CWG1D output is assigned to value of OVRD bit bit 2 STRC: Steering Enable bit C(2) 1 = CWG1C output has the CWG data input waveform with polarity control from POLC bit 0 = CWG1C output is assigned to value of OVRC bit bit 1 STRB: Steering Enable bit B(2) 1 = CWG1B output has the CWG data input waveform with polarity control from POLB bit 0 = CWG1B output is assigned to value of OVRB bit bit 0 STRA: Steering Enable bit A(2) 1 = CWG1A output has the CWG data input waveform with polarity control from POLA bit 0 = CWG1A output is assigned to value of OVRA bit Note 1: 2: The bits in this register apply only when MODE<2:0> = 00x (Register 24-1, Steering modes). This bit is double-buffered when MODE<2:0> = 001. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 313 PIC18(L)F27/47K40 REGISTER 24-6: CWG1AS0: CWG AUTO-SHUTDOWN CONTROL REGISTER 0 R/W/HS/HC-0/0 R/W-0/0 SHUTDOWN REN R/W-0/0 R/W-1/1 R/W-0/0 LSBD<1:0> R/W-1/1 U-0 U-0 -- -- LSAC<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS/HC = Bit is set/cleared by hardware q = Value depends on condition bit 7 SHUTDOWN: Auto-Shutdown Event Status bit(1,2) 1 = An auto-shutdown state is in effect 0 = No auto-shutdown event has occurred bit 6 REN: Auto-Restart Enable bit 1 = Auto-restart is enabled 0 = Auto-restart is disabled bit 5-4 LSBD<1:0>: CWG1B and CWG1D Auto-Shutdown State Control bits 11 = A logic `1' is placed on CWG1B/D when an auto-shutdown event occurs. 10 = A logic `0' is placed on CWG1B/D when an auto-shutdown event occurs. 01 = Pin is tri-stated on CWG1B/D when an auto-shutdown event occurs. 00 = The inactive state of the pin, including polarity, is placed on CWG1B/D after the required dead-band interval when an auto-shutdown event occurs. bit 3-2 LSAC<1:0>: CWG1A and CWG1C Auto-Shutdown State Control bits 11 = A logic `1' is placed on CWG1A/C when an auto-shutdown event occurs. 10 = A logic `0' is placed on CWG1A/C when an auto-shutdown event occurs. 01 = Pin is tri-stated on CWG1A/C when an auto-shutdown event occurs. 00 = The inactive state of the pin, including polarity, is placed on CWG1A/C after the required dead-band interval when an auto-shutdown event occurs. bit 1-0 Unimplemented: Read as `0' Note 1: 2: This bit may be written while EN = 0 (Register 24-1), to place the outputs into the shutdown configuration. The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this bit is cleared. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 314 PIC18(L)F27/47K40 REGISTER 24-7: CWG1AS1: CWG AUTO-SHUTDOWN CONTROL REGISTER 1 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 -- -- AS5E AS4E AS3E AS2E AS1E AS0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented Read as `0' bit 5 AS5E: CWG Auto-shutdown Source 5 (CMP2 OUT) Enable bit 1 = Auto-shutdown for CMP2 OUT is enabled 0 = Auto-shutdown for CMP2 OUT is disabled bit 4 AS4E: CWG Auto-shutdown Source 4 (CMP1 OUT) Enable bit 1 = Auto-shutdown for CMP1 OUT is enabled 0 = Auto-shutdown for CMP1 OUT is disabled bit 3 AS3E: CWG Auto-shutdown Source 3 (TMR6_Postscaled) Enable bit 1 = Auto-shutdown for TMR6_Postscaled is enabled 0 = Auto-shutdown for TMR6_Postscaled is disabled bit 2 AS2E: CWG Auto-shutdown Source 2 (TMR4_Postscaled) Enable bit 1 = Auto-shutdown for TMR4_Postscaled is enabled 0 = Auto-shutdown for TMR4_Postscaled is disabled bit 1 AS1E: CWG Auto-shutdown Source 1 (TMR2_Postscaled) Enable bit 1 = Auto-shutdown for TMR2_Postscaled is enabled 0 = Auto-shutdown for TMR2_Postscaled is disabled bit 0 AS0E: CWG Auto-shutdown Source 0 (Pin selected by CWG1PPS) Enable bit 1 = Auto-shutdown for CWG1PPS Pin is enabled 0 = Auto-shutdown for CWG1PPS Pin is disabled 2016 Microchip Technology Inc. Preliminary DS40001844B-page 315 PIC18(L)F27/47K40 REGISTER 24-8: CWG1DBR: CWG RISING DEAD-BAND COUNT REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 DBR<5:0>: CWG Rising Edge Triggered Dead-Band Count bits 11 1111 = 63-64 CWG clock periods 11 1110 = 62-63 CWG clock periods . . . 00 0010 = 2-3 CWG clock periods 00 0001 = 1-2 CWG clock periods 00 0000 = 0 CWG clock periods. Dead-band generation is bypassed REGISTER 24-9: CWG1DBF: CWG FALLING DEAD-BAND COUNT REGISTER U-0 U-0 -- -- R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u DBF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as `0' bit 5-0 DBF<5:0>: CWG Falling Edge Triggered Dead-Band Count bits 11 1111 = 63-64 CWG clock periods 11 1110 = 62-63 CWG clock periods . . . 00 0010 = 2-3 CWG clock periods 00 0001 = 1-2 CWG clock periods 00 0000 = 0 CWG clock periods. Dead-band generation is bypassed. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 316 PIC18(L)F27/47K40 TABLE 24-3: Name CWG1CON0 SUMMARY OF REGISTERS ASSOCIATED WITH CWG Bit 3 Bit 2 Bit 6 Bit 5 Bit 4 EN LD -- -- -- -- POLD POLC POLB POLA 311 -- -- CS 312 -- -- IN CWG1CLKCON -- -- -- -- -- CWG1ISM -- -- -- -- -- CWG1STR OVRD OVRC OVRB OVRA STRD CWG1AS0 SHUTDOWN REN CWG1AS1 -- -- CWG1DBR -- -- DBR<5:0> CWG1DBF -- -- DBF<5:0> SCANIE CRCIE PIE7 AS5E AS4E 310 312 ISM<2:0> STRC LSAC<1:0> AS3E Bit 0 MODE<2:0> CWG1CON1 LSBD<1:0> Bit 1 Register on Page Bit 7 AS2E STRB STRA 313 -- -- 314 AS1E AS0E 315 316 316 NVMIE -- -- -- -- CWG1IE 185 PIR7 SCANIF CRCIF NVMIF -- -- -- -- CWG1IF 177 IPR7 SCANIP CRCIP NVMIP -- -- -- -- CWG1IP 193 PMD4 UART2MD -- -- -- CWG1MD 71 Legend: UART1MD MSSP2MD MSSP1MD - = unimplemented locations read as `0'. Shaded cells are not used by CWG. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 317 PIC18(L)F27/47K40 25.0 DATA SIGNAL MODULATOR (DSM) MODULE The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical "AND" operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Using this method, the DSM can generate the following types of Key Modulation schemes: * Frequency-Shift Keying (FSK) * Phase-Shift Keying (PSK) * On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: * * * * * Carrier Synchronization Carrier Source Polarity Select Programmable Modulator Data Modulated Output Polarity Select Peripheral Module Disable, which provides the ability to place the DSM module in the lowest power consumption mode Figure 25-1 shows a Simplified Block Diagram of the Data Signal Modulator peripheral. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 318 PIC18(L)F27/47K40 FIGURE 25-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR MDCHS<2:0> Rev. 10-000248E 8/7/2015 Data Signal Modulator 000 See MDCARH Register CARH MDCHPOL D 111 SYNC Q 1 MDSRCS<3:0> 0 0000 MDCHSYNC RxyPPS See MDSRC Register MOD PPS MDOPOL 1111 MDCLS<2:0> D SYNC 000 Q 1 0 See MDCARL Register CARL MDCLSYNC MDCLPOL 111 2016 Microchip Technology Inc. Preliminary DS40001844B-page 319 PIC18(L)F27/47K40 25.1 Register Definitions: Modulation Control Long bit name prefixes for the Modulation peripheral is shown in Table 25-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 25-1: Peripheral Bit Name Prefix MD MD REGISTER 25-1: MDCON0: MODULATION CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 EN -- OUT OPOL -- -- -- BIT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: Modulator Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 6 Unimplemented: Read as `0' bit 5 OUT: Modulator Output bit Displays the current output value of the Modulator module.(1) bit 4 OPOL: Modulator Output Polarity Select bit 1 = Modulator output signal is inverted; idle high output 0 = Modulator output signal is not inverted; idle low output bit 3-1 Unimplemented: Read as `0' bit 0 BIT: Allows software to manually set modulation source input to module(2) Note 1: 2: The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. MDBIT must be selected as the modulation source in the MDSRC register for this operation. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 320 PIC18(L)F27/47K40 REGISTER 25-2: MDCON1: MODULATION CONTROL REGISTER 1 U-0 U-0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- CHPOL CHSYNC -- -- CLPOL CLSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5 CHPOL: Modulator High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 4 CHSYNC: Modulator High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = Modulator output is not synchronized to the high time carrier signal(1) bit 3-2 Unimplemented: Read as `0' bit 1 CLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted bit 0 CLSYNC: Modulator Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = Modulator output is not synchronized to the low time carrier signal(1) Note 1:Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 321 PIC18(L)F27/47K40 REGISTER 25-3: U-0 MDCARH: MODULATION HIGH CARRIER CONTROL REGISTER U-0 -- U-0 -- -- U-0 U-0 -- R/W-0/0 R/W-0/0 R/W-0/0 (1) -- CHS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 CHS<2:0>: Modulator Carrier High Selection bits(1) See Table 25-2 for signal list Note 1:Unused selections provide an input value. REGISTER 25-4: MDCARL: MODULATION LOW CARRIER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 CLS<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 CLS<2:0>: Modulator Carrier Low Input Selection bits(1) See Table 25-2 for signal list Note 1:Unused selections provide a zero as the input value. TABLE 25-2: MDCARH/MDCARL SELECTION MUX CONNECTIONS MDCARH CHS<2:0> Connection MDCARL CLS<2:0> Connection 111 7 PWM4 OUT 111 7 PWM4 OUT 110 6 PWM3 OUT 110 6 PWM3 OUT 101 5 CCP2 OUT 101 5 CCP2 OUT 100 4 CCP1 OUT 100 4 CCP1 OUT 011 3 CLKREF output 011 3 CLKREF output 010 2 HFINTOSC 010 2 HFINTOSC 001 1 FOSC (system clock) 001 1 FOSC (system clock) 000 0 Pin selected by MDCARHPPS 000 0 Pin selected by MDCARLPPS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 322 PIC18(L)F27/47K40 REGISTER 25-5: MDSRC: MODULATION SOURCE CONTROL REGISTER U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SRCS<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 SRCS<3:0>: Modulator Source Selection bits(1) See Table 25-3 for signal list Note 1:Unused selections provide a zero as the input value. TABLE 25-3: MDSRC SELECTION MUX CONNECTIONS MDSRCS<3:0> 1111-1110 Connection Reserved 1101 13 MSSP2 - SDO 1100 12 MSSP1 - SDO 1011 11 EUSART2 TX (TX/CK output) 1010 10 EUSART2 RX (DT output) 1001 9 EUSART1 TX (TX/CK output) 1000 8 EUSART1 RX (DT output) 0111 7 CMP2 OUT 0110 6 CMP1 OUT 0101 5 PWM4 OUT 0100 4 PWM3 OUT 0011 3 CCP2 OUT 0010 2 CCP1 OUT 0001 1 MDBIT 0000 0 Pin selected by MDSRCPPS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 323 PIC18(L)F27/47K40 TABLE 25-4: SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page MDCON0 EN -- OUT OPOL -- -- -- BIT 320 -- CLPOL CLSYNC 321 Name MDCON1 -- -- CHPOL CHSYNC -- MDCARH -- -- -- -- -- MDCARL -- -- -- -- -- MDSRC -- -- -- -- MDCARLPPS -- -- -- CARLPPS<4:0> 215 MDCARHPPS -- -- -- CARHPPS<4:0> 215 MDSRCPPS -- -- -- SRCPPS<4:0> 215 RxyPPS -- -- -- RxyPPS<4:0> 217 -- -- -- PMD5 Legend: -- CHS<2:0> 322 CLS<2:0> 322 SRCS<3:0> -- -- 323 -- DSMMD 72 -- = unimplemented, read as `0'. Shaded cells are not used in the Data Signal Modulator mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 324 PIC18(L)F27/47K40 25.2 DSM Operation 25.4 The DSM module can be enabled by setting the MDEN bit in the MDCON0 register. Clearing the MDEN bit in the MDCON0 register, disables the DSM module output and switches the carrier high and carrier low signals to the default option of MDCARHPPS and MDCARLPPS, respectively. The modulator signal source is also switched to the MDBIT in the MDCON0 register. This not only assures that the DSM module is inactive, but that it is also consuming the least amount of current. The values used to select the carrier high, carrier low, and modulator sources held by the Modulation Source, Modulation High Carrier, and Modulation Low Carrier control registers are not affected when the MDEN bit is cleared and the DSM module is disabled. The values inside these registers remain unchanged while the DSM is inactive. The sources for the carrier high, carrier low and modulator signals will once again be selected when the MDEN bit is set and the DSM module is again enabled and active. The modulated output signal can be disabled without shutting down the DSM module. The DSM module will remain active and continue to mix signals, but the output value will not be sent to the DSM pin. During the time that the output is disabled, the DSM pin will remain low. The modulated output can be disabled by clearing the MDEN bit in the MDCON register. 25.3 Modulator Signal Sources The modulator signal can be supplied from the following sources: * * * * * * * * External signal on pin selected by MDSRCPPS MDBIT bit in the MDCON0 register CCP1/2 Output PWM3/4 Output Comparator C1/C2 Output EUSART RX Signal EUSART TX Signal MSSP SDO Signal (SPI Mode Only) Carrier Signal Sources The carrier high signal and carrier low signal can be supplied from the following sources: * External signal on pin selected by MDCARHPPS/ MDCARLPPS * FOSC (system clock) * HFINTOSC * Reference Clock Module Signal * CCP1/2 Output Signal * PWM3/4 Output The carrier high signal is selected by configuring the MDCHS<2:0> bits in the MDCARH register. The carrier low signal is selected by configuring the MDCLS<2:0> bits in the MDCARL register. 25.5 Carrier Synchronization During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal is enabled by setting the MDCHSYNC bit in the MDCON1 register. Synchronization for the carrier low signal is enabled by setting the MDCLSYNC bit in the MDCON1 register. Figure 25-2 through Figure 25-6 show timing diagrams of using various synchronization methods. The modulator signal is selected by configuring the MDSRCS<3:0> bits in the MDSRC register. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 325 PIC18(L)F27/47K40 FIGURE 25-2: On Off Keying (OOK) Synchronization Carrier Low (CARL) Carrier High (CARH) Modulator (MOD) MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 FIGURE 25-3: No Synchronization (MDSHSYNC = 0, MDCLSYNC = 0) carrier_high carrier_low modulator MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State FIGURE 25-4: carrier_high carrier_low carrier_high carrier_low Carrier High Synchronization (MDSHSYNC = 1, MDCLSYNC = 0) carrier_high carrier_low modulator MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier State carrier_high 2016 Microchip Technology Inc. both carrier_low Preliminary carrier_high both carrier_low DS40001844B-page 326 PIC18(L)F27/47K40 FIGURE 25-5: Carrier Low Synchronization (MDSHSYNC = 0, MDCLSYNC = 1) carrier_high carrier_low modulator MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State FIGURE 25-6: carrier_high carrier_low carrier_high carrier_low Full Synchronization (MDSHSYNC = 1, MDCLSYNC = 1) carrier_high carrier_low modulator Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State carrier_high 2016 Microchip Technology Inc. carrier_low Preliminary carrier_high CL DS40001844B-page 327 PIC18(L)F27/47K40 25.6 Carrier Source Polarity Select 25.9 Operation in Sleep Mode The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high source is enabled by setting the MDCHPOL bit of the MDCON1 register. Inverting the signal for the carrier low source is enabled by setting the MDCLPOL bit of the MDCON1 register. The DSM module is not affected by Sleep mode. The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep. Refer to Section 6.0 "Power-Saving Operation Modes" for more details. 25.7 Upon any device Reset, the DSM module is disabled. The user's firmware is responsible for initializing the module before enabling the output. The registers are reset to their default values. Programmable Modulator Data The MDBIT of the MDCON0 register can be selected as the source for the modulator signal. This gives the user the ability to program the value used for modulation. 25.8 Modulated Output Polarity The modulated output signal provided on the DSM pin can also be inverted. Inverting the modulated output signal is enabled by setting the MDOPOL bit of the MDCON0 register. 2016 Microchip Technology Inc. 25.10 Effects of a Reset 25.11 Peripheral Module Disable The DSM module can be completely disabled using the PMD module to achieve maximum power saving. The DSMMD bit of PMD5 (Register 7-6) when set disables the DSM module completely. When enabled again all the registers of the DSM module default to POR status. Preliminary DS40001844B-page 328 PIC18(L)F27/47K40 26.0 Note: 26.1 MASTER SYNCHRONOUS SERIAL PORT MODULE 26.2 The PIC18(L)F27/47K40 devices have two MSSP. Therefore, all information in this section refers to both MSSP1 and MSSP2. MSSP Module Overview SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The PIC18(L)F27/47K40 devices have two MSSP modules that can operate in one of two modes: * * * * Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) Figure 26-1 shows the block diagram of the MSSP module when operating in SPI mode. * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: * * * * * Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices The I2C interface supports the following modes and features: * * * * * * * * * * * * * Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times 2016 Microchip Technology Inc. Preliminary DS40001844B-page 329 PIC18(L)F27/47K40 FIGURE 26-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SSPxDATPPS SDI PPS SSPSR Reg Shift Clock bit 0 SDO PPS RxyPPS SS SS Control Enable PPS SSPxSSPPS Edge Select SSPxCLKPPS(2) SCK SSPM<3:0> 4 PPS PPS TRIS bit 2 (CKP, CKE) Clock Select Edge Select RxyPPS(1) ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) Note 1: Output selection for master mode 2: Input selection for slave mode The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 26-2 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 330 PIC18(L)F27/47K40 FIGURE 26-2: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 26.3 SPI Mode Registers The MSSP module has five registers for SPI mode operation. These are: * * * * * * MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control STATUS registers in SPI mode operation. SSPxCON1 register is readable and writable. lower six bits of the SSPxSTAT are read-only. upper two bits of the SSPxSTAT are read/write. and The The The In one SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 26.11 "Baud Rate Generator". SSPSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 331 PIC18(L)F27/47K40 26.4 Register Definitions: MSSP Control REGISTER 26-1: R/W-0 SMP SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 (1) D/A P S R/W UA BF CKE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: Sample bit SPI Master mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. bit 6 CKE: SPI Clock Select bit(1) 1 = Transmit occurs on the transition from active to Idle clock state 0 = Transmit occurs on the transition from Idle to active clock state bit 5 D/A: Data/Address bit Used in I2C mode only. bit 4 P: Stop bit Used in I2C mode only. This bit is cleared when the MSSPx module is disabled; SSPEN is cleared. bit 3 S: Start bit Used in I2C mode only. bit 2 R/W: Read/Write Information bit Used in I2C mode only. bit 1 UA: Update Address bit Used in I2C mode only. bit 0 BF: Buffer Full Status bit (Receive mode only) 1 = Receive is complete, SSPxBUF is full 0 = Receive is not complete, SSPxBUF is empty Note 1: Polarity of clock state is set by the CKP bit (SSPxCON1<4>). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 332 PIC18(L)F27/47K40 REGISTER 26-2: R/W-0 WCOL SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) R/W-0 R/W-0 (1) (2) SSPOV SSPEN R/W-0 CKP R/W-0 SSPM3 (4) R/W-0 SSPM2 (4) R/W-0 SSPM1 (4) R/W-0 SSPM0(4) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit 1 = Idle state for the clock is a high level 0 = Idle state for the clock is a low level bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(4) 1010 = SPI Master mode: Clock = FOSC/(4 * (SSPxADD + 1))(3) 0101 = SPI Slave mode: Clock = SCKx pin; SSx pin control is disabled; SSx can be used as I/O pin 0100 = SPI Slave mode: Clock = SCKx pin; SSx pin control is enabled 0011 = SPI Master mode: Clock = TMR2 output/2 0010 = SPI Master mode: Clock = FOSC/64 0001 = SPI Master mode: Clock = FOSC/16 0000 = SPI Master mode: Clock = FOSC/4 Note 1: 2: 3: 4: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as inputs or outputs. SSPxADD = 0 is not supported. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 333 PIC18(L)F27/47K40 REGISTER 26-3: SSPxCON3: MSSPx CONTROL REGISTER 3 (SPI MODE) R/HS/HC-0 R/W-0 ACKTIM PCIE(1) R/W-0 SCIE (1) R/W-0 (2) BOEN R/W-0 R/W-0 R/W-0 R/W-0 SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set HS/HC = Bit is set/cleared by hardware x = Bit is unknown `0' = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit Unused in SPI. bit 6 PCIE: Stop Condition Interrupt Enable bit(1) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled bit 5 SCIE: Start Condition Interrupt Enable bit(1) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled bit 4 BOEN: Buffer Overwrite Enable bit(2) 1 = SSPxBUF updates every time a new data byte is shifted in, ignoring the BF bit 0 = If a new byte is received with BF bit already set, SSPOV is set, and the buffer is not updated bit 3 SDAHT: SDA Hold Time Selection bit Unused in SPI. bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit Unused in SPI. bit 1 AHEN: Address Hold Enable bit Unused in SPI. bit 0 DHEN: Data Hold Enable bit Unused in SPI. Note 1: 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 334 PIC18(L)F27/47K40 REGISTER 26-4: R/W-x SSPxBUF: MSSP DATA BUFFER REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BUF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 BUF<7:0>: MSSP Buffer bits REGISTER 26-5: R/W-0 SSPxADD: MSSP ADDRESS REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared Master mode: SPI mode bit 7-0 Baud Rate Clock Divider bits SCK/SCL pin clock period = ((SSPxADD<7:0> + 1) *4)/FOSC 2016 Microchip Technology Inc. Preliminary DS40001844B-page 335 PIC18(L)F27/47K40 26.5 SPI Mode Operation Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. Figure 26-3 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave's SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master's SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: * Master sends useful data and slave sends dummy data. * Master sends useful data and slave sends useful data. * Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) * Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: * SDI must have corresponding TRIS bit set * SDO must have corresponding TRIS bit cleared * SCK (Master mode) must have corresponding TRIS bit cleared * SCK (Slave mode) must have corresponding TRIS bit set * SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit, WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 336 PIC18(L)F27/47K40 When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. FIGURE 26-3: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (BUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPxBUF) LSb SCK General I/O Processor 1 2016 Microchip Technology Inc. SDO Serial Clock Slave Select (optional) Preliminary Shift Register (SSPSR) MSb LSb SCK SS Processor 2 DS40001844B-page 337 PIC18(L)F27/47K40 26.5.1 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 26-3) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 26-4, Figure 26-6, Figure 26-7 and Figure 26-8, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 26-4 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. Note: 2016 Microchip Technology Inc. Preliminary In Master mode the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPxCLKPPS register. DS40001844B-page 338 PIC18(L)F27/47K40 FIGURE 26-4: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPSR to SSPxBUF 26.5.2 SPI SLAVE MODE 26.5.3 In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 2016 Microchip Technology Inc. DAISY-CHAIN CONFIGURATION The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 26-5 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. Preliminary DS40001844B-page 339 PIC18(L)F27/47K40 26.5.4 SLAVE SELECT SYNCHRONIZATION When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100). FIGURE 26-5: When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to `0'. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI General I/O SDO SPI Slave #1 SS SCK SDI SDO SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 340 PIC18(L)F27/47K40 FIGURE 26-6: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPSR and bit count are reset SSPxBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF 2016 Microchip Technology Inc. Preliminary DS40001844B-page 341 PIC18(L)F27/47K40 FIGURE 26-7: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active FIGURE 26-8: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active 2016 Microchip Technology Inc. Preliminary DS40001844B-page 342 PIC18(L)F27/47K40 26.5.5 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 189 -- -- -- -- -- -- SSPxCON1 WCOL SSPOV SSPEN CKP SSPxCON3 ACKTIM PCIE SCIE BOEN SSPxDATPPS -- -- -- SSPDATPPS<4:0> 215 SSPxSSPPS -- -- -- SSPSSPPS<4:0> 215 SMP CKE D/A Name INTCON RxyPPS RxyPPS<4:0> SSPxBUF BUF<7:0> SSPxCLKPPS SSPxSTAT Legend: * 217 331* SSPxCLKPPS<4:0> P 215 SSPM<3:0> SDAHT S SBCDE R/W 333 AHEN DHEN UA BF 334 348 -- = Unimplemented location, read as `0'. Shaded cells are not used by the MSSP in SPI mode. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 343 PIC18(L)F27/47K40 26.6 I2C Mode Overview The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is FIGURE 26-9: controlled through addressing. Figure 26-9 is a block diagram of the I2C interface module in Master mode. Figure 26-10 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal data bus SSPxDATPPS(1) Read [SSPM<3:0>] Write SDA SDA in SSPxBUF Baud Rate Generator (SSPxADD) Shift Clock RxyPPS(1) SCL PPS Receive Enable (RCEN) SSPxCLKPPS(2) MSb LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Clock Cntl SSPSR PPS Clock arbitrate/BCOL detect (Hold off clock source) PPS PPS RxyPPS(2) SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSP1IF, BCL1IF Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output 2016 Microchip Technology Inc. Preliminary DS40001844B-page 344 PIC18(L)F27/47K40 FIGURE 26-10: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPxCLKPPS(2) SCL PPS Shift Clock Clock Stretching PPS SSPxBUF Reg SSPSR Reg LSb MSb RxyPPS(2) SSPxMSK Reg (1) SSPxDATPPS SDA Match Detect Addr Match PPS SSPxADD Reg PPS Start and Stop bit Detect RxyPPS(1) Set, Reset S, P bits (SSPxSTAT Reg) Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output The I2C bus specifies two signal connections: * Serial Clock (SCL) * Serial Data (SDA) Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 26-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. FIGURE 26-11: * Master Transmit mode (master is transmitting data to a slave) * Master Receive mode (master is receiving data from a slave) * Slave Transmit mode (slave is transmitting data to a master) * Slave Receive mode (slave is receiving data from the master) VDD SCL SCL VDD Master To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. 2016 Microchip Technology Inc. I2C MASTER/ SLAVE CONNECTION Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. Preliminary DS40001844B-page 345 PIC18(L)F27/47K40 The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 26.6.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. The I2C bus specifies three message protocols; * Single message where a master writes data to a slave. * Single message where a master reads data from a slave. * Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 346 PIC18(L)F27/47K40 26.6.2 26.7 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 2016 Microchip Technology Inc. Register Definitions: I2C Mode The MSSPx module has seven registers for I2C operation. These are: * MSSP Status Register (SSPxSTAT) * MSSP Control Register 1 (SSPxCON1) * MSSP Control Register 2 (SSPxCON2) * MSSP Control Register 3 (SSPxCON3) * Serial Receive/Transmit Buffer Register (SSPxBUF) * MSSP Address Register (SSPxADD) * I2C Slave Address Mask Register (SSPxMSK) * MSSP Shift Register (SSPSR) - not directly accessible SSPxCON1, SSPxCON2, SSPxCON3 and SSPxSTAT are the Control and Status registers in I2C mode operation. The SSPxCON1, SSPxCON2, and SSPxCON3 registers are readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPSR is the Shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. SSPxADD contains the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value. SSPxMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible when the SSPM<3:0> bits are specifically set to permit access. In receive operations, SSPSR and SSPxBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. Preliminary DS40001844B-page 347 PIC18(L)F27/47K40 REGISTER 26-6: SSPxSTAT: MSSPx STATUS REGISTER (I2C MASTER MODE) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P(1) S(1) R/W(2,3) UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enables SMBus-specific inputs 0 = Disables SMBus-specific inputs bit 5 D/A: Data/Address bit In Master mode: Reserved. In Slave mode: 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit(1) 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last bit 3 S: Start bit(1) 1 = Indicates that a Start bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit(2,3) In Slave mode: 1 = Read 0 = Write In Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress bit 1 UA: Update Address bit (10-Bit Slave mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit In Transmit mode: 1 = SSPxBUF is full 0 = SSPxBUF is empty In Receive mode: 1 = SSPxBUF is full (does not include the ACK and Stop bits) 0 = SSPxBUF is empty (does not include the ACK and Stop bits) Note 1: 2: 3: This bit is cleared on Reset and when SSPEN is cleared. This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSPx is in Active mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 348 PIC18(L)F27/47K40 REGISTER 26-7: SSPxCON1: MSSPx CONTROL REGISTER 1 (I2C MASTER MODE) R/W-0 R/W/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN(1) CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit HC = Bit is cleared by hardware -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared in software) 0 = No collision In Slave Transmit mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision In Receive mode (Master or Slave modes): This is a "don't care" bit. bit 6 SSPOV: Receive Overflow Indicator bit In Receive mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) 0 = No overflow In Transmit mode: This is a "don't care" bit in Transmit mode. bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1) 1 = Enables the serial port and configures the SDAx and SCLx pins as the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: SCKx Release Control bit In Slave mode: 1 = Releases clock 0 = Holds clock low (clock stretch), used to ensure data setup time In Master mode: Unused in this mode. bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(2) 1111 = I2C Slave mode: 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode: 7-bit address with Start and Stop bit interrupts enabled 1011 = I2C Firmware Controlled Master mode (slave Idle) 1001 = Load SSPxMSK register at SSPxADD SFR address(3,4) 1000 = I2C Master mode: Clock = FOSC/(4 * (SSPxADD + 1)) 0111 = I2C Slave mode: 10-bit address(3,4) 0110 = I2C Slave mode: 7-bit address Note 1: 2: 3: 4: When enabled, the SDAx and SCLx pins must be configured as inputs. Bit combinations not specifically listed here are either reserved or implemented in SPI mode only. When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the SSPxMSK register. This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit is `1'). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 349 PIC18(L)F27/47K40 REGISTER 26-8: SSPxCON2: MSSPx CONTROL REGISTER 2 (I2C MASTER MODE) R/W-0 R/W/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit HC = Bit is cleared by hardware -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit Unused in Master mode. bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1) 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit(2) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; automatically cleared by hardware 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2) 1 = Enables Receive mode for I2C 0 = Receive is Idle bit 2 PEN: Stop Condition Enable bit(2) 1 = Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Stop condition is Idle bit 1 RSEN: Repeated Start Condition Enable bit(2) 1 = Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Repeated Start condition is Idle bit 0 SEN: Start Condition Enable bit(2) 1 = Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware 0 = Start condition is Idle Note 1: 2: The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 350 PIC18(L)F27/47K40 SSPxCON3: MSSPx CONTROL REGISTER 3 (I2C MASTER MODE) REGISTER 26-9: R/HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set HS/HC = Bit is set/cleared by hardware x = Bit is unknown `0' = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit Unused in Master mode. bit 6 PCIE: Stop Condition Interrupt Enable bit(1) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled bit 5 SCIE: Start Condition Interrupt Enable bit(1) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled bit 4 BOEN: Buffer Overwrite Enable bit 1 = SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV effect on updating the buffer 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit 1 = Minimum of 300ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit Unused in Master mode. bit 1 AHEN: Address Hold Enable bit Unused in Master mode. bit 0 DHEN: Data Hold Enable bit Unused in Master mode. Note 1: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. REGISTER 26-10: SSPxBUF: MSSP DATA BUFFER REGISTER (I2C MASTER MODE) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BUF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 BUF<7:0>: MSSP Buffer bits 2016 Microchip Technology Inc. Preliminary DS40001844B-page 351 PIC18(L)F27/47K40 REGISTER 26-11: SSPxADD: MSSP ADDRESS REGISTER (I2C MASTER MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared Master mode: I2 C mode Baud Rate Clock Divider bits(1) SCK/SCL pin clock period = ((SSPxADD<7:0> + 1) *4)/FOSC bit 7-0 10-Bit Slave mode - Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a don't care. Bit pattern sent by master is fixed by I2C specification and must be equal to '11110'. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<9:8>: Two Most Significant bits of 10-bit Address bit 0 Not used: Unused in this mode. Bit state is a don't care. 10-Bit Slave mode - Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit Address 7-Bit Slave mode: bit 7-1 7-bit Slave Address bit 0 Not used: Unused in this mode. Bit state is a don't care. Note 1: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. REGISTER 26-12: SSPxMSK: MSSPx ADDRESS MASK REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK<7:1> R/W-1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADDn to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK0: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD0 to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 352 PIC18(L)F27/47K40 26.8 I2C Mode Operation TABLE 26-2: All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC(R) microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 26.8.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 26.8.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 26.8.3 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note 1: Data is tied to output zero when an I2C mode is enabled. 2: Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPxDATPPS registers. The SCL input is selected with the SSPxCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user's responsibility to make the selections so that both the input and the output for each function is on the same pin. 26.8.4 TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 353 PIC18(L)F27/47K40 26.8.5 START CONDITION 26.8.7 I2C The specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 26-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 26-13 shows the wave form for a Restart condition. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 26.8.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear, or high address match fails. 26.8.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 26-12: I2C START AND STOP CONDITIONS SDA SCL S Start Condition FIGURE 26-13: P Change of Change of Data Allowed Data Allowed Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed 2016 Microchip Technology Inc. Restart Condition Preliminary Data Allowed DS40001844B-page 354 PIC18(L)F27/47K40 26.8.9 ACKNOWLEDGE SEQUENCE 26.9.1.1 I2C Slave 7-bit Addressing Mode The ninth SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. The result of an ACK is placed in the ACKSTAT bit of the SSPxCON2 register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPxCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. 26.9 Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. SLAVE MODE ADDRESSES The SSPxADD register (Register 26-5) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of `1 1 1 1 0 A9 A8 0'. A9 and A8 are the two MSb's of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. 26.9.2 I2C Slave Mode Operation The MSSP Slave mode operates in one of four modes selected by the SSPM bits of the SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. 26.9.1 26.9.1.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 26-3. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit of the SSPxCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 26.9.6.2 "10-bit Addressing Mode" for more detail. The SSP Mask register affects the address matching process. See Section 26.9.9 "SSP Mask Register" for more information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 355 PIC18(L)F27/47K40 26.9.2.1 7-bit Addressing Reception 26.9.2.2 This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 26-14 and Figure 26-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBusTM that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 26-16 displays a module using both address and data holding. Figure 26-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge of SCL. 3. Slave clears the SSPxIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPxIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Note: SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set 11. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 356 2016 Microchip Technology Inc. FIGURE 26-14: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) Bus Master sends Stop condition From Slave to Master Receiving Address SDA SCL S Receiving Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 ACK 8 9 Receiving Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 ACK = 1 D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software Cleared by software SSPxIF set on 9th falling edge of SCL Preliminary BF SSPxBUF is read First byte of data is available in SSPxBUF SSPOV DS40001844B-page 357 PIC18(L)F27/47K40 SSPOV set because SSPxBUF is still full. ACK is not sent. 2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 26-15: Bus Master sends Stop condition Receive Address SDA SCL S Receive Data A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 R/W=0 ACK 8 9 SEN Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 SEN ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Clock is held low until CKP is set to `1' SSPxIF Cleared by software Preliminary BF SSPxBUF is read Cleared by software SSPxIF set on 9th falling edge of SCL First byte of data is available in SSPxBUF SSPOV CKP CKP is written to `1' in software, releasing SCL CKP is written to `1' in software, releasing SCL SCL is not held low because ACK= 1 DS40001844B-page 358 PIC18(L)F27/47K40 SSPOV set because SSPxBUF is still full. ACK is not sent. 2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 26-16: Master sends Stop condition Master Releases SDA to slave for ACK sequence Receiving Address SDA Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 Received Data ACK ACK=1 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPxIF If AHEN = 1: SSPxIF is set BF Preliminary ACKDT SSPxIF is set on 9th falling edge of SCL, after ACK Address is read from SSBUF Data is read from SSPxBUF Slave software clears ACKDT to CKP Slave software sets ACKDT to not ACK ACK the received byte When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL CKP set by software, SCL is released ACKTIM ACKTIM set by hardware on 8th falling edge of SCL S DS40001844B-page 359 P ACKTIM cleared by hardware in 9th rising edge of SCL ACKTIM set by hardware on 8th falling edge of SCL PIC18(L)F27/47K40 When AHEN=1: CKP is cleared by hardware and SCL is stretched No interrupt after not ACK from Slave Cleared by software 2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 26-17: R/W = 0 Receiving Address SDA ACK A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 3 4 5 6 7 Master sends Stop condition Master releases SDA to slave for ACK sequence 8 9 Receive Data 1 2 3 4 5 6 7 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 8 ACK 9 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P SSPxIF No interrupt after if not ACK from Slave Cleared by software BF Preliminary Received address is loaded into SSPxBUF Received data is available on SSPxBUF ACKDT Slave software clears ACKDT to ACK the received byte SSPxBUF can be read any time before next byte is loaded Slave sends not ACK CKP When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL S DS40001844B-page 360 P ACKTIM is cleared by hardware on 9th rising edge of SCL Set by software, release SCL CKP is not cleared if not ACK PIC18(L)F27/47K40 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared PIC18(L)F27/47K40 26.9.3 SLAVE TRANSMISSION 26.9.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 26-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 26.9.6 "Clock Stretching" for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPxCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 26.9.3.1 Master sends a Start condition on SDA and SCL. 2. S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPxIF bit. 4. Slave hardware generates an ACK and sets SSPxIF. 5. SSPxIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPxIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLxIF bit of the PIR register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision. 2016 Microchip Technology Inc. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. Preliminary DS40001844B-page 361 2016 Microchip Technology Inc. FIGURE 26-18: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) Master sends Stop condition Receiving Address SDA SCL S R/W = 1 Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 8 1 1 2 3 4 5 6 7 9 Transmitting Data 2 3 4 5 6 Automatic ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data 2 3 4 5 6 7 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL CKP Preliminary When R/W is set SCL is always held low after 9th SCL falling edge Set by software CKP is not held for not ACK ACKSTAT R/W R/W is copied from the matching address byte D/A Indicates an address has been received S DS40001844B-page 362 P PIC18(L)F27/47K40 Masters not ACK is copied to ACKSTAT PIC18(L)F27/47K40 26.9.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 26-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads the ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPxCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPxCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 363 2016 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) FIGURE 26-19: Master sends Stop condition Master releases SDA to slave for ACK sequence Receiving Address SDA SCL S 1 2 3 4 5 6 Automatic R/W = 1 ACK A7 A6 A5 A4 A3 A2 A1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 1 2 3 4 5 6 7 8 9 Transmitting Data 2 3 4 5 6 7 ACK 8 9 P SSPxIF Cleared by software BF Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF BF is automatically cleared after 8th falling edge of SCL ACKDT Preliminary Slave clears ACKDT to ACK address ACKSTAT Master's ACK response is copied to SSPxSTAT When AHEN = 1; CKP is cleared by hardware after receiving matching address. ACKTIM R/W DS40001844B-page 364 D/A ACKTIM is set on 8th falling edge of SCL CKP not cleared When R/W = 1; CKP is always cleared after ACK Set by software, releases SCL ACKTIM is cleared on 9th rising edge of SCL after not ACK PIC18(L)F27/47K40 CKP PIC18(L)F27/47K40 26.9.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 26.9.5 This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 26-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 26-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 26-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Note: If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPxIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPxIF is set. 14. If SEN bit of SSPxCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPxIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 365 2016 Microchip Technology Inc. I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 26-20: Master sends Stop condition Receive Second Address Byte Receive First Address Byte SDA SCL S 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 Receive Data Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 2 3 4 5 6 7 8 9 P SCL is held low while CKP = 0 SSPxIF Set by hardware on 9th falling edge Cleared by software Preliminary BF Receive address is read from SSPxBUF If address matches SSPxADD it is loaded into SSPxBUF Data is read from SSPxBUF When UA = 1; SCL is held low Software updates SSPxADD and releases SCL CKP Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte DS40001844B-page 366 PIC18(L)F27/47K40 UA 2016 Microchip Technology Inc. I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 26-21: Receive First Address Byte SDA SCL S Receive Second Address Byte R/W = 0 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 ACK 8 9 UA Receive Data A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 2 3 4 5 6 7 8 9 UA Receive Data D7 D6 D5 D4 D3 D2 D1 1 2 3 4 5 6 7 D0 ACK D7 8 9 1 D6 D5 2 SSPxIF Set by hardware on 9th falling edge Cleared by software Cleared by software BF Preliminary SSPxBUF can be read anytime before the next received byte Received data is read from SSPxBUF ACKDT UA Update to SSPxADD is not allowed until 9th falling edge of SCL CKP DS40001844B-page 367 If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL Update of SSPxADD, clears UA and releases SCL Set CKP with software releases SCL PIC18(L)F27/47K40 Slave software clears ACKDT to ACK the received byte 2016 Microchip Technology Inc. FIGURE 26-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) Master sends Restart event Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK SDA SCL S 1 2 3 4 5 6 7 8 9 Master sends not ACK Receiving Second Address Byte Receive First Address Byte A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 8 1 9 2 3 4 5 6 7 8 Transmitting Data Byte ACK 9 Master sends Stop condition ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 P Sr SSPxIF Set by hardware Cleared by software Set by hardware BF Preliminary SSPxBUF loaded with received address Received address is read from SSPxBUF Data to transmit is loaded into SSPxBUF UA UA indicates SSPxADD must be updated CKP After SSPxADD is updated, UA is cleared and SCL is released High address is loaded back into SSPxADD Set by software releases SCL Masters not ACK is copied R/W R/W is copied from the matching address byte D/A Indicates an address has been received DS40001844B-page 368 PIC18(L)F27/47K40 When R/W = 1; CKP is cleared on 9th falling edge of SCL ACKSTAT PIC18(L)F27/47K40 26.9.6 CLOCK STRETCHING 26.9.6.2 Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 26.9.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPxCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the ninth falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the ninth falling edge of SCL. It is now always cleared for read requests. FIGURE 26-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 26.9.6.3 Byte NACKing When the AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When the DHEN bit of SSPxCON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 26.9.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 26-23). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX - 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPxCON1 2016 Microchip Technology Inc. Preliminary DS40001844B-page 369 PIC18(L)F27/47K40 26.9.8 GENERAL CALL ADDRESS SUPPORT If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. 26.9.9 An SSP Mask (SSPxMSK) register (Register 26-12) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (`0') bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a "don't care". The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPxCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 26-24 shows a general call reception sequence. This register is reset to all `1's upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: * 7-bit Address mode: address compare of A<7:1>. In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. FIGURE 26-24: SSP MASK REGISTER 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT<0>) Cleared by software SSPxBUF is read GCEN (SSPxCON2<7>) '1' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 370 PIC18(L)F27/47K40 26.10 I2C Master Mode 26.10.1 Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic `0'. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled): * * * * Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received * Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. 2016 Microchip Technology Inc. I2C MASTER MODE OPERATION In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic `1'. Thus, the first byte transmitted is a 7-bit slave address followed by a `1' to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 26.11 "Baud Rate Generator" for more detail. 26.10.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 26-25). Preliminary DS40001844B-page 371 PIC18(L)F27/47K40 FIGURE 26-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX - 1 DX SCL allowed to transition high SCL deasserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 26.10.3 WCOL STATUS FLAG the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPxCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Note: 26.10.4 Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete. Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. I2C MASTER MODE START CONDITION TIMING To initiate a Start condition (Figure 26-26), the user sets the Start Enable bit, SEN bit of the SSPxCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is FIGURE 26-26: 2: The Philips I2C specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Set S bit (SSPxSTAT<3>) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit and sets SSPxIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 1st bit 2nd bit TBRG SCL S 2016 Microchip Technology Inc. Preliminary TBRG DS40001844B-page 372 PIC18(L)F27/47K40 26.10.5 I2C MASTER MODE REPEATED START CONDITION TIMING 26.10.6 A Repeated Start condition (Figure 26-27) occurs when the RSEN bit of the SSPxCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 26-28). Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: * SDA is sampled low when SCL goes from low-to-high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data `1'. FIGURE 26-27: REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPxCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears the RSEN bit and sets SSPxIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start 2016 Microchip Technology Inc. Preliminary DS40001844B-page 373 PIC18(L)F27/47K40 After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 26.10.6.1 9. 10. 11. 12. 13. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPxCON2 register. Interrupt is generated once the Stop/Restart condition is complete. BF Status Flag In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 26.10.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). The WCOL bit must be cleared by software before the next transmission. 26.10.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPxCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 26.10.6.4 1. 2. 3. 4. 5. 6. 7. 8. Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 374 2016 Microchip Technology Inc. FIGURE 26-28: I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Write SSPxCON2<0> SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSPxCON2<6> SEN = 0 A7 A6 A5 A4 A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 Transmit Address to Slave SDA ACKSTAT in SSPxCON2 = 1 A1 ACK = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCL held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 SSPxBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 9 P SSPxIF Cleared by software Cleared by software service routine from SSP interrupt Cleared by software Preliminary BF (SSPxSTAT<0>) SSPxBUF written SSPxBUF is written by software SEN PEN R/W DS40001844B-page 375 PIC18(L)F27/47K40 After Start condition, SEN cleared by hardware PIC18(L)F27/47K40 26.10.7 I2C Master Mode Reception Master mode reception (Figure 26-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPxIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPxCON2 register. 26.10.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is cleared when the SSPxBUF register is read. 26.10.7.2 SSPOV Status Flag 26.10.7.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 13. 14. 26.10.7.3 15. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 2016 Microchip Technology Inc. Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPxCON2 register. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPxCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit of the SSPxCON2 register and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPUF, clears BF. Master sets the ACK value sent to slave in the ACKDT bit of the SSPxCON2 register and initiates the ACK by setting the ACKEN bit. Master's ACK is clocked out to the slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. Preliminary DS40001844B-page 376 2016 Microchip Technology Inc. I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) FIGURE 26-29: Write to SSPxCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPxCON2<5>) = 0 Write to SSPxCON2<0>(SEN = 1), begin Start condition Transmit Address to Slave A7 SDA A6 A5 A4 A3 A2 RCEN = 1, start next receive ACK PEN bit = 1 written here RCEN cleared automatically Receiving Data from Slave Receiving Data from Slave A1 R/W Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 ACK from Master SDA = ACKDT = 0 Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, RCEN cleared ACK from Slave automatically start XMIT D7 D6 D5 D4 D3 D2 D1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK Bus master terminates transfer ACK is not sent SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 Data shifted in on falling edge of CLK Set SSPxIF interrupt at end of receive Preliminary Cleared by software Cleared by software Cleared by software BF (SSPxSTAT<0>) P Set SSPxIF at end of receive Set SSPxIF interrupt at end of Acknowledge sequence SSPxIF SDA = 0, SCL = 1 while CPU responds to SSPxIF 9 8 Cleared by software Cleared in software Set SSPxIF interrupt at end of Acknowledge sequence Set P bit (SSPxSTAT<4>) and SSPxIF Last bit is shifted into SSPSR and contents are unloaded into SSPxBUF SSPOV is set because SSPxBUF is still full ACKEN DS40001844B-page 377 RCEN Master configured as a receiver by programming SSPxCON2<3> (RCEN = 1) RCEN cleared automatically ACK from Master SDA = ACKDT = 0 RCEN cleared automatically PIC18(L)F27/47K40 SSPOV PIC18(L)F27/47K40 26.10.8 ACKNOWLEDGE SEQUENCE TIMING 26.10.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPxCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to `0'. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPxIF bit is set (Figure 26-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPxCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 26-30). 26.10.8.1 26.10.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 26-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software SSPxIF set at the end of Acknowledge sequence Cleared in software Note: TBRG = one Baud Rate Generator period. FIGURE 26-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 378 PIC18(L)F27/47K40 26.10.10 SLEEP OPERATION the I2C slave While in Sleep mode, module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 26.10.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 26.10.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: * * * * * Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition 26.10.13 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a `1' on SDA, by letting SDA float high and another master asserts a `0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a `1' and the data sampled on the SDA pin is `0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 26-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 26-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLxIF) BCLxIF 2016 Microchip Technology Inc. Preliminary DS40001844B-page 379 PIC18(L)F27/47K40 26.10.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 26-33). SCL is sampled low before SDA is asserted low (Figure 26-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 26-35). If, however, a `1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as `0' during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: * the Start condition is aborted, * the BCLxIF flag is set and * the MSSP module is reset to its Idle state (Figure 26-33). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data `1' during the Start condition. FIGURE 26-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSPx module reset into Idle state. SEN BCLxIF SDA sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDA = 0, SCL = 1. SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software 2016 Microchip Technology Inc. Preliminary DS40001844B-page 380 PIC18(L)F27/47K40 FIGURE 26-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLxIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software '0' '0' SSPxIF '0' '0' S FIGURE 26-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPxIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time out SEN BCLxIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 '0' S SSPxIF SDA = 0, SCL = 1, set SSPxIF 2016 Microchip Technology Inc. Preliminary Interrupts cleared by software DS40001844B-page 381 PIC18(L)F27/47K40 26.10.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data `0', Figure 26-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data `1' (Case 2). If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data `1' during the Repeated Start condition, see Figure 26-37. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 26-36: If, at the end of the BRG time out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLxIF and release SDA and SCL. RSEN BCLxIF Cleared by software S '0' SSPxIF '0' FIGURE 26-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLxIF SCL goes low before SDA, set BCLxIF. Release SDA and SCL. Interrupt cleared by software RSEN '0' S SSPxIF 2016 Microchip Technology Inc. Preliminary DS40001844B-page 382 PIC18(L)F27/47K40 26.10.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data `0' (Figure 26-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data `0' (Figure 26-39). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 26-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCLxIF SDA asserted low SCL PEN BCLxIF P '0' SSPxIF '0' FIGURE 26-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA SCL goes low before SDA goes high, set BCLxIF Assert SDA SCL PEN BCLxIF P '0' SSPxIF '0' 2016 Microchip Technology Inc. Preliminary DS40001844B-page 383 PIC18(L)F27/47K40 26.11 Baud Rate Generator EQUATION 26-1: The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 26-5). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. FOSC FCLOCK = --------------------------------------------- SSPADD + 1 4 Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal "Reload" in Figure 26-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 26-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. FIGURE 26-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> Reload SCL Control SSPCLK SSPxADD<7:0> Reload BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 26-3: Note: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical specifications in Table 37-8: Internal Oscillator Parameters, to ensure the system is designed to support IOL requirements. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 384 PIC18(L)F27/47K40 TABLE 26-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Reset Values on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 189 -- -- -- INTCON RxyPPS RxyPPS<4:0> SSPxADD SSPxBUF 335 BUF<7:0> SSPxCLKPPS -- -- -- 331* SSPCLKPPS<4:0> SSPxCON1 WCOL SSPOV SSPEN CKP SSPxCON2 GCEN ACKSTAT ACKDT ACKEN RCEN SSPxCON3 ACKTIM PCIE SCIE BOEN SDAHT -- -- -- SMP CKE D/A SSPxDATPPS Legend: * 215 SSPM<3:0> 333 PEN RSEN SEN 350 SBCDE AHEN DHEN 334 SSPDATPPS<4:0> SSPxMSK SSPxSTAT 217 ADD<7:0> 215 MSK<7:0> P 352 S R/W UA BF 332 -- = unimplemented location, read as `0'. Shaded cells are not used by the MSSP module in I2C mode. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 385 PIC18(L)F27/47K40 27.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) Note: These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The EUSART module includes the following capabilities: * * * * * * * * * * Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes * Sleep operation The PIC18(L)F27/47K40 devices have two EUSARTs. Therefore, all information in this section refers to both EUSART 1 and EUSART 2. The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. FIGURE 27-1: The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: * Automatic detection and calibration of the baud rate * Wake-up on Break reception * 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 27-1 and Figure 27-2. EUSART TRANSMIT BLOCK DIAGRAM Data Bus SYNC CSRC 8 TXEN MSb 1 0 TRMT FOSC PPS Multiplier TX_out /n TX9 n SPxBRGH SPxBRGL Pin Buffer and Control SYNC BRG16 Note 1: * * * Transmit Shift Register (TSR) CKPPS +1 RxyPPS(1) RXx/DTx pin LSb (8) 0 Baud Rate Generator Interrupt TXxIF TXxREG Register CKx pin PPS TXxIE x4 x16 x64 TX9D SYNC 1 X 0 0 0 0 BRGH X 1 1 0 0 1 BRG16 X 1 0 1 0 PPS RxyPPS In Synchronous mode, the DT output and RX input PPS selections should enable the same pin. 2016 Microchip Technology Inc. TXx/CKx pin Preliminary SYNC CSRC DS40001844B-page 386 PIC18(L)F27/47K40 FIGURE 27-2: EUSART RECEIVE BLOCK DIAGRAM SPEN RXx/DTx pin CREN OERR RCIDL RXxPPS(1) RSR Register MSb Pin Buffer and Control PPS Baud Rate Generator Data Recovery FOSC SPxBRGH SPxBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) *** 7 1 0 Start RX9 /n BRG16 +1 Stop LSb n FERR RX9D RCxREG Register 8 Note 1: In Synchronous mode, the DT output and RX input PPS selections should enable the same pin. FIFO Data Bus RCxIF RCxIE Interrupt The operation of the EUSART module is controlled through three registers: * Transmit Status and Control (TXxSTA) * Receive Status and Control (RCxSTA) * Baud Rate Control (BAUDxCON) These registers are detailed in Register 27-1, Register 27-2 and Register 27-3, respectively. The RXx/DTx and TXx/CKx input pins are selected with the RXxPPS and TXxPPS registers, respectively. TXx, CKx, and DTx output pins are selected with each pin's RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user's responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 387 PIC18(L)F27/47K40 27.1 Register Definitions: EUSART Control REGISTER 27-1: R/W-/0 TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 CSRC TX9 R/W-0/0 TXEN (1) R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission disabled or completed Synchronous mode: Don't care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed, if BRG16 = 1, baud rate is baudclk/4; else baudclk/16 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN bits of RCxSTA (Register 27-2) override TXEN in Sync mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 388 PIC18(L)F27/47K40 REGISTER 27-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R/HC-0/0 R/HC-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit HC = Bit is cleared by hardware u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Don't care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don't care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCxREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 389 PIC18(L)F27/47K40 REGISTER 27-3: BAUDxCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don't care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don't care bit 5 Unimplemented: Read as `0' bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is a low level (transmit data inverted) 0 = Idle state for transmit (TX) is a high level (transmit data is non-inverted) Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as `0' bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCxIF will be set. WUE will automatically clear after RCxIF is set. 0 = Receiver is operating normally Synchronous mode: Don't care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don't care 2016 Microchip Technology Inc. Preliminary DS40001844B-page 390 PIC18(L)F27/47K40 27.2 EUSART Asynchronous Mode 27.2.1.2 The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a `1' data bit, and a VOL Space state which represents a `0' data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 27-5 for examples of baud rate configurations. Transmitting Data A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 27.2.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is `0' which selects high true transmit idle and data bits. Setting the SCKP bit to `1' will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 27.5.1.2 "Clock Polarity". 27.2.1 27.2.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 27-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. 27.2.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: * TXEN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXxSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART and automatically configures the TXx/CKx I/O pin as an output. If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXxIF interrupt flag bit of the PIR3 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution. Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software. The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIE3 register. However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit. To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. The TXxIF Transmitter Interrupt flag is set when the TXEN enable bit is set. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 391 PIC18(L)F27/47K40 27.2.1.5 TSR Status 27.2.1.7 The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 27.2.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 27.2.2.7 "Address Detection" for more information on the Address mode. FIGURE 27-3: Write to TXxREG BRG Output (Shift Clock) 6. 7. 8. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 27.4 "EUSART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set. If interrupts are desired, set the TXxIE interrupt enable bit of the PIE3 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXxREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 TXx/CKx pin Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 TXxIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) 4. 5. Asynchronous Transmission Setup: 1 TCY Word 1 Transmit Shift Reg. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 392 PIC18(L)F27/47K40 FIGURE 27-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXxREG Word 2 Word 1 BRG Output (Shift Clock) TXx/CKx pin Start bit TXxIF bit (Transmit Buffer Reg. Empty Flag) bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Note: bit 0 1 TCY Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. TABLE 27-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDxCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 390 INTCON GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 173 Name PIE3 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 189 CREN ADDEN FERR OERR RX9D 389 RCxSTA SPEN RX9 SREN RxyPPS -- -- -- RxyPPS<4:0> TXxPPS -- -- -- TXPPS<4:0> 217 215 SPxBRGH EUSARTx Baud Rate Generator, High Byte SPxBRGL EUSARTx Baud Rate Generator, Low Byte 399* EUSARTx Transmit Register 391* TXxREG TXxSTA Legend: * CSRC TX9 TXEN SYNC SENDB BRGH 399* TRMT TX9D 388 -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous transmission. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 393 PIC18(L)F27/47K40 27.2.2 EUSART ASYNCHRONOUS RECEIVER 27.2.2.2 The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 27-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 27.2.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: * CREN = 1 * SYNC = 0 * SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCxSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXxSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCxSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RXx/DTx I/O pin as an input. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting `0' or `1' is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a `1'. If the data recovery circuit samples a `0' in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 27.2.2.4 "Receive Framing Error" for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCxIF interrupt flag bit of the PIR3 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Note: 27.2.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 27.2.2.5 "Receive Overrun Error" for more information on overrun errors. Receive Interrupts The RCxIF interrupt flag bit of the PIR3 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCxIF interrupts are enabled by setting all of the following bits: * RCxIE, Interrupt Enable bit of the PIE3 register * PEIE, Peripheral Interrupt Enable bit of the INTCON register * GIE, Global Interrupt Enable bit of the INTCON register The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 394 PIC18(L)F27/47K40 27.2.2.4 Receive Framing Error 27.2.2.7 Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 27.2.2.5 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register. 27.2.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 395 PIC18(L)F27/47K40 27.2.2.8 Asynchronous Reception Setup: 27.2.2.9 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 27.4 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RXx pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. 8. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 27-5: RXx/DTx pin 9-Bit Address Detection Mode Setup This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 27.4 "EUSART Baud Rate Generator (BRG)"). 2. Clear the ANSEL bit for the RXx pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device's address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 Rcv Shift Reg Rcv Buffer Reg. RCIDL bit 1 bit 7/8 Stop bit Start bit bit 0 Word 1 RCxREG bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCxREG Read Rcv Buffer Reg. RCxREG RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx input. The RCxREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 396 PIC18(L)F27/47K40 TABLE 27-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDxCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 390 INTCON GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP RCxREG EUSARTx Receive Register RCxSTA SPEN RX9 SREN RxyPPS -- -- -- RxyPPS<4:0> RXxPPS -- -- -- RXPPS<4:0> SPxBRGH Legend: * ADDEN FERR OERR RX9D 215 399* EUSARTx Baud Rate Generator, Low Byte CSRC TX9 TXEN SYNC SENDB BRGH 389 217 EUSARTx Baud Rate Generator, High Byte SPxBRGL TXxSTA CREN 189 394* 399* TRMT TX9D 388 -- = unimplemented location, read as `0'. Shaded cells are not used for asynchronous reception. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 397 PIC18(L)F27/47K40 27.3 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 4.3.2.3 "Internal Oscillator Frequency Adjustment" for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 27.4.1 "Auto-Baud Detect"). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 398 PIC18(L)F27/47K40 27.4 EUSART Baud Rate Generator (BRG) EXAMPLE 27-1: The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = ----------------------------------------------------------------------------64 [SPxBRGH:SPxBRGL] + 1 Solving for SPxBRGH:SPxBRGL: F OS C --------------------------------------------Desired Baud Rate 64 The SPxBRGH, SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Table 27-3 contains the formulas for determining the baud rate. Example 27-1 provides a sample calculation for determining the baud rate and baud rate error. CALCULATING BAUD RATE ERROR SPBRGH:SPBRGL = --------------------------------------------- - 1 16000000 -----------------------9600 = ------------------------ - 1 64 = 25.042 = 25 16000000 Calculated Baud Rate = --------------------------64 25 + 1 Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 27-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. = 9615 Calc. Baud Rate - Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate 9615 - 9600 = ---------------------------------- = 0.16% 9600 Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 399 PIC18(L)F27/47K40 TABLE 27-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 8-bit/Asynchronous FOSC/[64 (n+1)] SYNC BRG16 BRGH 0 0 0 0 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous FOSC/[16 (n+1)] FOSC/[4 (n+1)] Legend: x = Don't care, n = value of SPxBRGH:SPxBRGL register pair. TABLE 27-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDxCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 390 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 389 RCxSTA SPxBRGH EUSARTx Baud Rate Generator, High Byte 399* SPxBRGL EUSARTx Baud Rate Generator, Low Byte 399* TXxSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 388 Legend: -- = unimplemented location, read as `0'. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 400 PIC18(L)F27/47K40 TABLE 27-5: SAMPLE BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 -- -- -- -- -- -- -- 1221 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -- -3.55 -- 3 -- -- -- -- -- -- -- 57.60k -- 0.00 7 -- 57.60k -- 0.00 2 -- -- 115.2k Actual Rate % Error SPBRG value (decimal) Actual Rate -- 1.73 -- 255 % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) -- 1200 -- 0.00 -- 239 -- 1200 -- 0.00 -- 143 -- SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 -- 1202 -- 0.16 -- 103 300 1202 0.16 0.16 207 51 300 1200 0.00 191 47 300 1202 0.16 0.16 51 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 -- -- -- 0.00 9600 9615 0.16 12 -- -- -- 9600 0.00 5 -- -- -- 10417 10417 0.00 11 10417 0.00 5 -- -- -- -- -- -- 19.2k -- -- -- -- -- -- 19.20k 0.00 2 -- -- -- 57.6k -- -- -- -- -- -- 0 -- -- -- 115.2k -- -- -- -- -- -- 57.60k -- 0.00 -- -- -- -- -- SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE 300 1200 FOSC = 32.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 20.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 18.432 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 11.0592 MHz SPBRG Actual % value Rate Error (decimal) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9600 -- 0.00 -- 71 2400 -- -- -- -- -- -- -- -- -- 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 2016 Microchip Technology Inc. Preliminary DS40001844B-page 401 PIC18(L)F27/47K40 TABLE 27-5: SAMPLE BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 -- -- -- -- -- -- -- 1202 -- 0.16 -- 207 -- 1200 -- 0.00 -- 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 -- 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 32.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 20.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 18.432 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 11.0592 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 300.0 1200 0.00 -0.02 6666 3332 300.0 1200 -0.01 -0.03 4166 1041 300.0 1200 0.00 0.00 3839 959 300.0 1200 0.00 0.00 2303 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 BAUD RATE 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 299.9 1199 -0.02 -0.08 1666 416 300.1 1202 0.04 0.16 832 207 300.0 1200 0.00 0.00 767 191 300.5 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 -- -- -- 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 -- -- -- 57.6k 55556 -3.55 8 -- -- -- 57.60k 0.00 3 -- -- -- 115.2k -- -- -- -- -- -- 115.2k 0.00 1 -- -- -- BAUD RATE 2016 Microchip Technology Inc. Preliminary DS40001844B-page 402 PIC18(L)F27/47K40 TABLE 27-5: SAMPLE BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 32.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 20.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 18.432 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 11.0592 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 BAUD RATE 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 FOSC = 8.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 4.000 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 3.6864 MHz SPBRG Actual % value Rate Error (decimal) FOSC = 1.000 MHz SPBRG Actual % value Rate Error (decimal) 300 1200 300.0 1200 0.00 -0.02 6666 1666 300.0 1200 0.01 0.04 3332 832 300.0 1200 0.00 0.00 3071 767 300.1 1202 0.04 0.16 832 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 BAUD RATE 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 -- -- -- 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 -- -- -- 2016 Microchip Technology Inc. Preliminary DS40001844B-page 403 PIC18(L)F27/47K40 27.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII "U") which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 27-6. The fifth rising edge will occur on the RXx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH, SPxBRGL register pair, the ABDEN bit is automatically cleared and the RCxIF interrupt flag is set. The value in the RCxREG needs to be read to clear the RCxIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 27-6. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPx- FIGURE 27-6: Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 27.4.3 "Auto-Wake-up on Break"). 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. TABLE 27-6: BRG COUNTER CLOCK RATES BRG16 BRGH BRG Base Clock BRG ABD Clock 1 1 FOSC/4 FOSC/32 1 0 FOSC/16 FOSC/128 0 1 FOSC/16 FOSC/128 0 0 FOSC/64 FOSC/512 Note: During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter, independent of the BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value BRGH and SPxBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. RXx pin 0000h 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCxIF bit (Interrupt) Read RCxREG SPxBRGL XXh 1Ch SPxBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 404 PIC18(L)F27/47K40 27.4.2 AUTO-BAUD OVERFLOW 27.4.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RXx pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx pin. Upon detecting the fifth RX edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDxCON register. The RCxIF flag can be subsequently cleared by reading the RCxREG register. The ABDOVF flag of the BAUDxCON register can be cleared by software directly. To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDxCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 27.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 27-7), and asynchronously if the device is in Sleep mode (Figure 27-8). The interrupt condition is cleared by reading the RCxREG register. Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all `0's. This must be ten or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 405 PIC18(L)F27/47K40 FIGURE 27-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RXx/DTx Line RCxIF Note 1: Cleared due to User Read of RCxREG The EUSART remains in Idle while the WUE bit is set. FIGURE 27-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RXx/DTx Line RCxIF Note 1 Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCxREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 406 PIC18(L)F27/47K40 27.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 `0' bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 27-9 for the timing of the Break character sequence. 27.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 27.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; * RCxIF bit is set * FERR bit is set * RCxREG = 00h The second method uses the Auto-Wake-up feature described in Section 27.4.3 "Auto-Wake-up on Break". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCxIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG. FIGURE 27-9: Write to TXxREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TXx (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXxIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) 2016 Microchip Technology Inc. SENDB Sampled Here Preliminary Auto Cleared DS40001844B-page 407 PIC18(L)F27/47K40 27.5 EUSART Synchronous Mode 27.5.1.2 Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 27.5.1 SYNCHRONOUS MASTER MODE The following bits are used to configure the EUSART for synchronous master operation: * * * * * SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TXx/CKx pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. 2016 Microchip Technology Inc. A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 27.5.1.3 Synchronous Master Transmission Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXxSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 27.5.1.1 Clock Polarity Note: The TSR register is not mapped in data memory, so it is not available to the user. 27.5.1.4 Synchronous Master Transmission Setup: 1. 2. 3. 4. 5. 6. 7. 8. Preliminary Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 27.4 "EUSART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXxREG register. DS40001844B-page 408 PIC18(L)F27/47K40 FIGURE 27-10: SYNCHRONOUS TRANSMISSION RXx/DTx pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to TXxREG Reg Write Word 1 Write Word 2 TXxIF bit (Interrupt Flag) TRMT bit TXEN bit Note: `1' `1' Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words. FIGURE 27-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RXx/DTx pin bit 0 bit 1 bit 2 bit 6 bit 7 TXx/CKx pin Write to TXxREG reg TXxIF bit TRMT bit TXEN bit 2016 Microchip Technology Inc. Preliminary DS40001844B-page 409 PIC18(L)F27/47K40 TABLE 27-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDxCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 390 INTCON GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 189 RCxSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 389 RxyPPS -- -- -- RxyPPS<4:0> 217 TXxPPS -- -- -- TXPPS<4:0> 215 SPxBRGH EUSARTx Baud Rate Generator, High Byte 399* SPxBRGL EUSARTx Baud Rate Generator, Low Byte 399* EUSARTx Transmit Data Register TXxREG TXxSTA Legend: * CSRC TX9 TXEN SYNC SENDB BRGH 391* TRMT TX9D 388 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master transmission. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 410 PIC18(L)F27/47K40 27.5.1.5 Synchronous Master Reception 27.5.1.7 Data is received at the RXx/DTx pin. The RXx/DTx pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCxIF bit remains set as long as there are unread characters in the receive FIFO. Note: 27.5.1.6 If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TXx/CKx pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. 2016 Microchip Technology Inc. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 27.5.1.8 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 27.5.1.9 Synchronous Master Reception Setup: 1. Initialize the SPxBRGH:SPxBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RXx pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCxIE was set. 9. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. Preliminary DS40001844B-page 411 PIC18(L)F27/47K40 FIGURE 27-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit `0' `0' RCxIF bit (Interrupt) Read RCxREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. TABLE 27-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 203 ANSELC ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 203 BAUDxCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 390 INTCON GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP RCxREG EUSARTx Receive Data Register ADDEN FERR OERR RX9D 389 RCxSTA SPEN RX9 SREN RxyPPS -- -- -- RxyPPS<4:0> 217 RXxPPS -- -- -- RXPPS<4:0> 215 SPxBRGH EUSARTx Baud Rate Generator, High Byte SPxBRGL TXxSTA Legend: * CREN 189 394* 399* EUSARTx Baud Rate Generator, Low Byte CSRC TX9 TXEN SYNC SENDB BRGH 399* TRMT TX9D 388 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous master reception. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 412 PIC18(L)F27/47K40 27.5.2 SYNCHRONOUS SLAVE MODE 27.5.2.2 The following bits are used to configure the EUSART for synchronous slave operation: * * * * * SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 2. 3. 4. Setting the SYNC bit of the TXxSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXxSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCxSTA register enables the EUSART. 27.5.2.1 1. 5. 6. 7. 8. Synchronous Slave Transmission Setup Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CKx pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXxREG register. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see Section 27.5.1.3 "Synchronous Master Transmission"), except in the case of the Sleep mode. If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. 5. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXxREG register. The TXxIF bit will not be set. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXxIF bit will now be set. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 413 PIC18(L)F27/47K40 TABLE 27-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDxCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 390 INTCON GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 189 RCxSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 389 RxyPPS -- -- -- RxyPPS<4:0> 217 TXxPPS -- -- -- TXPPS<4:0> 215 CSRC TX9 TXEN TXxREG TXxSTA Legend: * EUSARTx Transmit Data Register SYNC SENDB 391* BRGH TRMT TX9D 388 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave transmission. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 414 PIC18(L)F27/47K40 27.5.2.3 EUSART Synchronous Slave Reception 27.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 27.5.1.5 "Synchronous Master Reception"), with the following exceptions: 1. Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CKx and DTx pins (if applicable). If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 2. * Sleep * CREN bit is always set, therefore the receiver is never idle * SREN bit, which is a "don't care" in Slave mode 3. 4. 5. 6. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. Synchronous Slave Reception Setup: 7. 8. 9. TABLE 27-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDxCON ABDOVF RCIDL -- SCKP BRG16 -- WUE ABDEN 390 INTCON GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 181 PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 173 IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP RCxREG EUSART Receive Data Register RCxSTA SPEN RX9 SREN RxyPPS -- -- -- RXxPPS -- -- -- TXxSTA CSRC TX9 TXEN Legend: * CREN ADDEN FERR OERR RX9D RxyPPS<4:0> SENDB BRGH 389 217 RXPPS<4:0> SYNC 189 394* 215 TRMT TX9D 388 -- = unimplemented location, read as `0'. Shaded cells are not used for synchronous slave reception. Page provides register information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 415 PIC18(L)F27/47K40 27.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 27.6.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: * RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see Section 27.5.2.4 "Synchronous Slave Reception Setup:"). * If interrupts are desired, set the RCxIE bit of the PIE3 register and the GIE and PEIE bits of the INTCON register. * The RCxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RXx/DTx and TXx/CKx pins, respectively. When the data word has been completely clocked in by the external device, the RCxIF interrupt flag bit of the PIR3 register will be set. Thereby, waking the processor from Sleep. 27.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: * The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see Section 27.5.2.2 "Synchronous Slave Transmission Setup"). * The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and transmit buffer. * If interrupts are desired, set the TXxIE bit of the PIE3 register and the PEIE bit of the INTCON register. * Interrupt enable bits TXxIE of the PIE3 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TXx/CKx pin and transmit data on the RXx/DTx pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another character for transmission, which will clear the TXxIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 416 PIC18(L)F27/47K40 28.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: * ADC input channel * ADC positive reference * Comparator input * Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the FVRCON register. Note: 28.1 Fixed Voltage Reference output cannot exceed VDD. The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 31.0 "Analog-to-Digital Converter with Computation (ADC2) Module" for additional information. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator module. Reference Section 30.0 "5-Bit Digital-to-Analog Converter (DAC) Module" and Section 32.0 "Comparator Module" for additional information. 28.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. Independent Gain Amplifiers The output of the FVR, which is connected to the ADC, Comparators, and DAC, is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. FIGURE 28-1: VOLTAGE REFERENCE BLOCK DIAGRAM Rev. 10-000 053C 12/9/201 3 ADFVR<1:0> CDAFVR<1:0> FVREN Note 1 2016 Microchip Technology Inc. 2 1x 2x 4x FVR_buffer1 (To ADC Module) 1x 2x 4x FVR_buffer2 (To Comparators and DAC) 2 + _ FVRRDY Preliminary DS40001844B-page 417 PIC18(L)F27/47K40 28.3 Register Definitions: FVR Control REGISTER 28-1: R/W-0/0 FVREN FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R-q/q R/W-0/0 (1) TSEN FVRRDY (3) R/W-0/0 TSRNG R/W-0/0 (3) R/W-0/0 R/W-0/0 CDAFVR<1:0> R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits 11 = Comparator FVR Buffer Gain is 4x, (4.096V)(2) 10 = Comparator FVR Buffer Gain is 2x, (2.048V)(2) 01 = Comparator FVR Buffer Gain is 1x, (1.024V) 00 = Comparator FVR Buffer is off bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit 11 = ADC FVR Buffer Gain is 4x, (4.096V)(2) 10 = ADC FVR Buffer Gain is 2x, (2.048V)(2) 01 = ADC FVR Buffer Gain is 1x, (1.024V) 00 = ADC FVR Buffer is off Note 1: 2: 3: FVRRDY is always `1'. Fixed Voltage Reference output cannot exceed VDD. See Section 29.0 "Temperature Indicator Module" for additional information. TABLE 28-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADCON0 ADON ADCONT -- ADCS -- CMxNCH -- -- -- -- -- CMxPCH -- -- -- -- -- DAC1CON1 -- -- -- Bit 2 Bit 1 Bit 0 ADFVR<1:0> ADFM -- ADGO Register on page 418 443 CxNCH<2:0> 464 CxPCH<2:0> 465 DAC1R<4:0> 424 Legend: -- = Unimplemented location, read as `0'. Shaded cells are not used with the Fixed Voltage Reference. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 418 PIC18(L)F27/47K40 29.0 TEMPERATURE INDICATOR MODULE FIGURE 29-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between -40C and +85C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. Rev. 10-000069A 7/31/2013 VDD TSEN The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, "Use and Calibration of the Internal Temperature Indicator" (DS00001333) for more details regarding the calibration process. 29.1 TEMPERATURE CIRCUIT DIAGRAM TSRNG VOUT Temp. Indicator To ADC Circuit Operation Figure 29-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 29-1 describes the output characteristics of the temperature indicator. EQUATION 29-1: VOUT RANGES 29.2 Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 29-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT Low Range: VOUT = VDD - 2VT TABLE 29-1: The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 28.0 "Fixed Voltage Reference (FVR)" for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 29.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 31.0 "Analog-to-Digital Converter with Computation (ADC2) Module" for detailed information. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 419 PIC18(L)F27/47K40 29.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between consecutive conversions of the temperature indicator output. TABLE 29-2: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 418 Legend: -- = Unimplemented location, read as `0'. Shaded cells are unused by the temperature indicator module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 420 PIC18(L)F27/47K40 30.0 5-BIT DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The positive input source (VSOURCE+) of the DAC can be connected to: * FVR Buffer * External VREF+ pin * VDD supply voltage The output of the DAC (DACx_output) can be selected as a reference voltage to the following: * * * * Comparator positive input ADC input channel DACxOUT1 pin DACxOUT2 pin The Digital-to-Analog Converter (DAC) can be enabled by setting the DACEN bit of the DAC1CON0 register. The negative input source (VSOURCE-) of the DAC can be connected to: * External VREF- pin * Vss FIGURE 30-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Rev. 10-000026F 8/7/2015 Reserved 11 FVR Buffer 10 VSOURCE+ 5 R 01 VREF+ AVDD DACR<4:0> 00 R DACPSS R 32-to-1 MUX R 32 Steps DACEN DACx_output To Peripherals R DACxOUT1(1) R DACOE1 R DACxOUT2(1) VREFAVSS 1 DACOE2 VSOURCE- 0 DACNSS Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 421 PIC18(L)F27/47K40 30.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DAC1R<4:0> bits of the DAC1CON1 register. The DAC output voltage can be determined by using Equation 30-1. 30.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Table 37-16. 30.3 DAC Voltage Reference Output The unbuffered DAC voltage can be output to the DACxOUTn pin(s) by setting the respective DACOEn bit(s) of the DACxCON0 register. Selecting the DAC reference voltage for output on either DACxOUTn pin automatically overrides the digital output buffer, the weak pull-up and digital input threshold detector functions of that pin. EQUATION 30-1: Reading the DACxOUTn pin when it has been configured for DAC reference voltage output will always return a `0'. Note: 30.4 The unbuffered DAC output (DACxOUTn) is not intended to drive an external load. Operation During Sleep When the device wakes up from Sleep through an interrupt or a Windowed Watchdog Timer Time-out, the contents of the DACxCON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 30.5 Effects of a Reset A device Reset affects the following: * DACx is disabled. * DACX output voltage is removed from the DACxOUTn pin(s). * The DAC1R<4:0> range select bits are cleared. DAC OUTPUT VOLTAGE IF DACEN = 1 DACR 4:0 DACx_output = VREF+ - VREF- ----------------------------5 + VREF2 Note: See the DAC1CON0 register for the available VSOURCE+ and VSOURCE- selections. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 422 PIC18(L)F27/47K40 30.6 Register Definitions: DAC Control Long bit name prefixes for the DAC peripheral is shown in Table 30-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 30-1: Peripheral Bit Name Prefix DAC DAC REGISTER 30-1: l DAC1CON0: DAC CONTROL REGISTER R/W-0/0 U-0 R/W-0/0 R/W-0/0 EN -- OE1 OE2 R/W-0/0 R/W-0/0 PSS<1:0> U-0 R/W-0/0 -- NSS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 EN: DAC Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as `0' bit 5 OE1: DAC Voltage Output Enable bit 1 = DAC voltage level is output on the DAC1OUT1 pin 0 = DAC voltage level is disconnected from the DAC1OUT1 pin bit 4 OE2: DAC Voltage Output Enable bit 1 = DAC voltage level is output on the DAC1OUT2 pin 0 = DAC voltage level is disconnected from the DAC1OUT2 pin bit 3-2 PSS<1:0>: DAC Positive Source Select bit 11 = Reserved 10 = FVR buffer 01 = VREF+ 00 = AVDD bit 1 Unimplemented: Read as `0' bit 0 NSS: DAC Negative Source Select bit 1 = VREF0 = AVSS 2016 Microchip Technology Inc. Preliminary DS40001844B-page 423 PIC18(L)F27/47K40 REGISTER 30-2: DAC1CON1: DAC DATA REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DAC1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 DAC1R<4:0>: Data Input Register for DAC bits TABLE 30-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 DAC1CON0 EN -- OE1 OE2 DAC1CON1 -- -- -- FVREN FVRRDY TSEN FVRCON Legend: Bit 3 Bit 2 PSS<1:0> Bit 1 Bit 0 -- NSS DAC1R<4:0> TSRNG CDAFVR<1:0> ADFVR<1:0> Register on page 423 424 418 -- = Unimplemented location, read as `0'. Shaded cells are not used with the DAC module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 424 PIC18(L)F27/47K40 31.0 ANALOG-TO-DIGITAL CONVERTER WITH COMPUTATION (ADC2) MODULE The Analog-to-Digital Converter with Computation (ADC2) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Additionally, the following features are provided within the ADC module: * 8-bit Acquisition Timer * Hardware Capacitive Voltage Divider (CVD) support: - 8-bit precharge timer - Adjustable sample and hold capacitor array - Guard ring digital output drive * Automatic repeat and sequencing: - Automated double sample conversion for CVD - Two sets of result registers (Result and Previous result) - Auto-conversion trigger - Internal retrigger * Computation features: - Averaging and low-pass filter functions - Reference comparison - 2-level threshold comparison - Selectable interrupts Figure 31-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion and upon threshold comparison. These interrupts can be used to wake-up the device from Sleep. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 425 PIC18(L)F27/47K40 ADC2 BLOCK DIAGRAM FIGURE 31-1: ADPREF<1:0> VREF+ pin 11 FVR_buffer1 Rev. 10-000034B 10/13/2015 Positive Reference Select 10 01 Reserved 00 ADNREF VDD VREF- pin 1 0 AN0 External Channel Inputs ANa Vref- . . . ANz Vref+ ADC_clk sampled input VSS Internal Channel Inputs ADCS<2:0> VSS ADC Clock Select FOSC/n Fosc Divider FRC FOSC FRC Temp Indicator DACx_output ADC CLOCK SOURCE FVR_buffer1 ADC Sample Circuit CHS<4:0> ADFM set bit ADIF Write to bit GO/DONE 10-bit Result GO/DONE Q1 Q4 16 start ADRESH Q2 TRIGSEL<3:0> 10 complete ADRESL Enable Trigger Select ADON . . . VSS Trigger Sources AUTO CONVERSION TRIGGER 2016 Microchip Technology Inc. Preliminary DS40001844B-page 426 PIC18(L)F27/47K40 31.1 ADC Configuration 31.1.3 When configuring and using the ADC the following functions must be considered: * * * * * * * * * * * * Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting Conversion Trigger Selection ADC Acquisition Time ADC Precharge Time Additional Sample and Hold Capacitor Single/Double Sample Conversion Guard Ring Outputs 31.1.1 31.1.2 The ADPREF<1:0> bits of the ADREF register provide control of the positive voltage reference. The positive voltage reference can be: * * * * * VREF+ pin VDD FVR 1.024V FVR 2.048V FVR 4.096V The ADNREF bit of the ADREF register provides control of the negative voltage reference. The negative voltage reference can be: * VREF- pin * VSS See Section 28.0 "Fixed Voltage Reference (FVR)" for more details on the Fixed Voltage Reference. PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 15.0 "I/O Ports" for more information. Note: Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION 31.1.4 * * * * * FOSC/2 FOSC/4 FOSC/6 FOSC/8 FOSC/10 . * * * * . * * * * Eight PORTA pins (RA<7:0>) Eight PORTB pins (RB<7:0>) Eight PORTC pins (RC<7:0>) Eight PORTD pins (RD<7:0>), PIC18(L)F45/46K40PIC18(L)F47K40 only) Three PORTE pins (RE<2:0>), PIC18(L)F47K40 only Temperature Indicator DAC output Fixed Voltage Reference (FVR) AVSS (ground) . * FOSC/128 * FRC (dedicated RC oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 31-2. For correct conversion, the appropriate TAD specification must be met. Refer to Table 37-14 for more information. Table 31-1 gives examples of appropriate ADC clock selections. The ADPCH register determines which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. 0 Note 1: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. Refer to Section 31.2 "ADC Operation" for more information. 2016 Microchip Technology Inc. CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCLK register and the ADCS bits of the ADCON0 register. There are 66 possible clock options: There are several channel selections available: * ADC VOLTAGE REFERENCE Preliminary 2: The internal control logic of the ADC runs off of the clock selected by the ADCS bit of ADCON0. What this can mean is when the ADCS bit of ADCON0 is set to `1' (ADC runs on FRC), there may be unexpected delays in operation when setting ADC control bits. DS40001844B-page 427 PIC18(L)F27/47K40 TABLE 31-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES(1,4) ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<5:0> 64 MHz 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000000 31.25 ns(2) 62.5 ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 000001 62.5 ns(2) 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s 125 ns(2) ns(2) ns(2) ns(2) FOSC/6 000010 FOSC/8 000011 ... FOSC/16 ... Legend: Note 1: 2: 3: 4: 187.5 250 ns(2) 300 400 ns(2) 375 750 500 ns(2) 1.0 s 1.5 s 6.0 s 2.0 s 8.0 s(3) ... ... ... ... ... ... ... ... 000100 250 ns(2) 500 ns(2) 800 ns(2) 1.0 s 2.0 s 4.0 s 16.0 s(3) ... ... ... ... ... ... ... ... 111111 2.0 s 4.0 s 6.4 s 8.0 s ADCS(ADCON0<4>) = 1 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s FOSC/128 FRC 187.5 ns(2) ns(2) 16.0 s(3) s(2) 128.0 s(2) 1.0-6.0 s 1.0-6.0 s 32.0 1.0-6.0 s Shaded cells are outside of recommended range. See TAD parameter for FRC source typical TAD value. These values violate the required TAD time. Outside the recommended TAD time. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 31-2: Precharge Time 1-127 TCY (TPRE) ANALOG-TO-DIGITAL CONVERSION TAD CYCLES Acquisition/ Sharing Time 1-127 TCY (TACQ) Rev. 10-000035B 7/15/2016 Conversion Time (Traditional Timing of ADC Conversion) TCY TCY-TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 b9 External and Internal External and Internal Channels are Channels share charged/discharged charge If ADPRE 0 If ADACQ 0 b8 b6 b5 b4 b3 b2 b1 2 TCY b0 Conversion starts Holding capacitor CHOLD is disconnected from analog input (typically 100ns) If ADPRE = 0 If ADACQ = 0 (Traditional Operation Start) Set GO bit 2016 Microchip Technology Inc. b7 Preliminary On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, DS40001844B-page 428 PIC18(L)F27/47K40 31.1.5 INTERRUPTS 31.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bits of the ADCON0 register controls the output format. Figure 31-3 shows the two output formats. Writes to the ADRES register pair are always right justified regardless of the selected format mode. Therefore, data read after writing to ADRES when ADFRM0 = 0 will be shifted left six places. For example, writing 0xFF to ADRESL will be read as 0xC0 in ADRESL and 0x3F logical OR'd with whatever was in the two MS bits in ADRESH. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the ADIE bit of the PIE1 register and the PEIE bit of the INTCON register must both be set and the GIE bit of the INTCON register must be cleared. If all three of these bits are set, the execution will switch to the Interrupt Service Routine. FIGURE 31-3: 10-BIT ADC CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 Unimplemented: Read as `0' 10-bit ADC Result (ADFM = 1) bit 0 MSB bit 7 LSB bit 0 Unimplemented: Read as `0' 2016 Microchip Technology Inc. bit 7 bit 0 10-bit ADC Result Preliminary DS40001844B-page 429 PIC18(L)F27/47K40 31.2 31.2.1 ADC Operation 31.2.4 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a `1'. A conversion may be started by any of the following: * Software setting the ADGO bit of ADCON0 to `1' * An external trigger (selected by Register 31-3) * A continuous-mode retrigger (see section Section 31.5.8 "Continuous Sampling mode") . Note: 31.2.2 The ADGO bit should not be set in the same instruction that turns on the ADC. Refer to Section 31.2.7 "ADC Conversion Procedure (Basic Mode)". COMPLETION OF A CONVERSION When any individual conversion is complete, the value already in ADRES is written into ADPREV (if ADPSIS = 1) and the new conversion results appear in ADRES. When the conversion completes, the ADC module will: ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. 31.2.5 EXTERNAL TRIGGER DURING SLEEP If the external trigger is received during sleep while ADC clock source is set to the FRC, ADC module will perform the conversion and set the ADIF bit upon completion. If an external trigger is received when the ADC clock source is something other than FRC, the trigger will be recorded, but the conversion will not begin until the device exits Sleep. * Clear the ADGO bit (unless the ADCONT bit of ADCON0 is set) * Set the ADIF Interrupt Flag bit * Set the ADMATH bit * Update ADACC When ADDSEN = 0 then after every conversion, or when ADDSEN = 1 then after every other conversion, the following events occur: * ADERR is calculated * ADTIF is set if ADERR calculation meets threshold comparison Importantly, filter and threshold computations occur after the conversion itself is complete. As such, interrupt handlers responding to ADIF should check ADTIF before reading filter and threshold results. 31.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the ADGO bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. In this case, filter and/or threshold occur. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 430 PIC18(L)F27/47K40 31.2.6 AUTO-CONVERSION TRIGGER The Auto-conversion Trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the ADGO bit is set by hardware. The Auto-conversion Trigger source is selected with the ADACT<4:0> bits of the ADACT register. Using the Auto-conversion Trigger does not assure proper ADC timing. It is the user's responsibility to ensure that the ADC timing requirements are met. See Table 31-2 for auto-conversion sources. TABLE 31-2: ADC AUTO-CONVERSION TABLE Source Peripheral Description ADCACTPPS Pin selected by ADCACTPPS TMR0 Timer0 overflow condition TMR1/3/5 Timer1/3/5 overflow condition TMR2/4/6 Match between Timer2/4/6 postscaled value and PR2/4/6 CCP1/2 CCP1/2 output PWM3/4 PWM3/4 output C1/2 Comparator C1/2 output IOC Interrupt-on-change interrupt trigger ADERR Read of ADERRH register ADRESH Read of ADRESH register ADPCH Write of ADPCH register 2016 Microchip Technology Inc. Preliminary DS40001844B-page 431 PIC18(L)F27/47K40 31.2.7 ADC CONVERSION PROCEDURE (BASIC MODE) This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: * Disable pin output driver (Refer to the TRISx register) * Configure pin as analog (Refer to the ANSELx register) Configure the ADC module: * Select ADC conversion clock * Configure voltage reference * Select ADC input channel (precharge+acquisition) * Turn on ADC module Configure ADC interrupt (optional): * Clear ADC interrupt flag * Enable ADC interrupt * Enable peripheral interrupt (PEIE bit) * Enable global interrupt (GIE bit)(1) If ADACQ = 0, software must wait the required acquisition time(2). Start conversion by setting the ADGO bit. Wait for ADC conversion to complete by one of the following: * Polling the ADGO bit * Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 31-1: ADC CONVERSION ;This code block configures the ADC ;for polling, VDD and VSS references, FRC ;oscillator and AN0 input. ; ;Conversion start & polling for completion ;are included. ; BANKSEL ADCON1 ; MOVLW B'11110000' ;Right justify, ;FRC oscillator MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B'00000001' ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 31.3 "ADC Acquisition Requirements". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 432 PIC18(L)F27/47K40 31.3 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 31-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 31-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 31-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be completed before the conversion can be started. To calculate the minimum acquisition time, Equation 31-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2s + T C + Temperature - 25C 0.05s/C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 - -------------------------n+1 2 -1 ;[1] VCHOLD charged to within 1/2 lsb -TC ---------- RC V AP P LI ED 1 - e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED - Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 - e = V A PP LIE D 1 - -------------------------n+1 2 -1 Note: Where n = number of bits of the ADC. Solving for TC: T C = - C HOLD R IC + R SS + R S ln(1/2047) = - 10pF 1k + 7k + 10k ln(0.0004885) = 1.37 s Therefore: T A CQ = 2s + 892ns + 50C- 25C 0.05 s/C = 4.62s Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 433 PIC18(L)F27/47K40 FIGURE 31-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.6V CHOLD = 10 pF Ref- Legend: CHOLD CPIN 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance RSS I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance = Resistance of Sampling Switch RSS SS = Sampling Switch VT Note 1: FIGURE 31-5: 5 6 7 8 9 10 11 Sampling Switch (k) = Threshold Voltage Refer to Table 37-4 (parameter D340 and D341). ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB REF- 2016 Microchip Technology Inc. 1.5 LSB Zero-Scale Transition Full-Scale Transition Preliminary REF+ DS40001844B-page 434 PIC18(L)F27/47K40 31.4 Capacitive Voltage Divider (CVD) Features The ADC module contains several features that allow the user to perform a relative capacitance measurement on any ADC channel using the internal ADC sample and hold capacitance as a reference. This relative capacitance measurement can be used to implement capacitive touch or proximity sensing applications. Figure 31-6 shows the basic block diagram of the CVD portion of the ADC module. FIGURE 31-6: HARDWARE CAPACITIVE VOLTAGE DIVIDER BLOCK DIAGRAM ADOUT Pad ADOUT ADOEN VDD ADIPPOL = 1 ADC Conversion Bus ANx ANx Pads ADIPPOL = 0 VGND ADDCAP<2:0> Additional Sample and Hold Cap VGND 2016 Microchip Technology Inc. VGND Preliminary VGND DS40001844B-page 435 PIC18(L)F27/47K40 31.4.1 CVD OPERATION A CVD operation begins with the ADC's internal sample and hold capacitor (CHOLD) being disconnected from the path which connects it to the external capacitive sensor node. While disconnected, CHOLD is precharged to VDD or VSS, while the path to the sensor node is also discharged to VDD or VSS. Typically, this node is discharged to the level opposite that of CHOLD. When the precharge phase is complete, the VDD/VSS bias paths for the two nodes are shut off and CHOLD and the path to the external sensor node are re-connected, at which time the acquisition phase of the CVD operation begins. During acquisition, a capacitive voltage divider is formed between the precharged CHOLD and sensor nodes, which results in a final voltage level setting on CHOLD, which is determined by the capacitances and precharge levels of the two nodes. After acquisition, the ADC converts the voltage level on CHOLD. This process is then repeated with the selected precharge levels for both the CHOLD and the inverted sensor nodes. Figure 31-7 shows the waveform for two inverted CVD measurements, which is known as differential CVD measurement. FIGURE 31-7: DIFFERENTIAL CVD MEASUREMENT WAVEFORM Precharge Acquisition Conversion Precharge Acquisition Conversion External Capacitive Sensor ADC Sample and Hold Capacitor Voltage VDD VSS First Sample Second Sample Time 2016 Microchip Technology Inc. Preliminary DS40001844B-page 436 PIC18(L)F27/47K40 31.4.2 PRECHARGE CONTROL 31.4.4 The Precharge stage is an optional period of time that brings the external channel and internal sample and hold capacitor to known voltage levels. Precharge is enabled by writing a non-zero value to the ADPRE register. This stage is initiated when an ADC conversion begins, either from setting the ADGO bit, a special event trigger, or a conversion restart from the computation functionality. If the ADPRE register is cleared when an ADC conversion begins, this stage is skipped. During the precharge time, CHOLD is disconnected from the outer portion of the sample path that leads to the external capacitive sensor and is connected to either VDD or VSS, depending on the value of the ADPPOL bit of ADCON1. At the same time, the port pin logic of the selected analog channel is overridden to drive a digital high or low out, in order to precharge the outer portion of the ADC's sample path, which includes the external sensor. The output polarity of this override is also determined by the ADPPOL bit of ADCON1. The amount of time that this charging needs is controlled by the ADPRE register. Note: 31.4.3 The external charging overrides the TRIS setting of the respective I/O pin. If there is a device attached to this pin, Precharge should not be used. ACQUISITION CONTROL The Acquisition stage is an optional time for the voltage on the internal sample and hold capacitor to charge or discharge from the selected analog channel.This acquisition time is controlled by the ADACQ register. If ADPRE = 0, acquisition starts at the beginning of conversion. When ADPRE = 1, the acquisition stage begins when precharge ends. Figure 31-8 shows a typical guard ring circuit. CGUARD represents the capacitance of the guard ring trace placed on the PCB board. The user selects values for RA and RB that will create a voltage profile on CGUARD, which will match the selected acquisition channel. The purpose of the guard ring is to generate a signal in phase with the CVD sensing signal to minimize the effects of the parasitic capacitance on sensing electrodes. It also can be used as a mutual drive for mutual capacitive sensing. For more information about active guard and mutual drive, see Application Note AN1478, "mTouchTM Sensing Solution Acquisition Methods Capacitive Voltage Divider" (DS01478). The ADC has two guard ring drive outputs, ADGRDA and ADGRDB. These outputs can be routed through PPS controls to I/O pins (see Section 17.0 "Peripheral Pin Select (PPS) Module" for details) and the polarity of these outputs are controlled by the ADGPOL and ADIPEN bits of ADCON1. At the start of the first precharge stage, both outputs are set to match the ADGPOL bit of ADCON1. Once the acquisition stage begins, ADGRDA changes polarity, while ADGRDB remains unchanged. When performing a double sample conversion, setting the ADIPEN bit of ADCON1 causes both guard ring outputs to transition to the opposite polarity of ADGPOL at the start of the second precharge stage, and ADGRDA toggles again for the second acquisition. For more information on the timing of the guard ring output, refer to Figure 31-8 and Figure 31-9. FIGURE 31-8: At the start of the acquisition stage, the port pin logic of the selected analog channel is overridden to turn off the digital high/low output drivers so they do not affect the final result of the charge averaging. Also, the selected ADC channel is connected to CHOLD. This allows charge averaging to proceed between the precharged channel and the CHOLD capacitor. Note: GUARD RING OUTPUTS GUARD RING CIRCUIT ADGRDA RA RB CGUARD ADGRDB When ADPRE! = 0, acquisition time cannot be `0'. In this case, setting ADACQ to `0' will set a maximum acquisition time (256 ADC clock cycles). When precharge is disabled, setting ADACQ to `0' will disable hardware acquisition time control. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 437 PIC18(L)F27/47K40 FIGURE 31-9: DIFFERENTIAL CVD WITH GUARD RING OUTPUT WAVEFORM Voltage Guard Ring Output External Capacitive Sensor VDD VSS First Sample Second Sample Time FIGURE 31-10: HARDWARE CVD SEQUENCE TIMING DIAGRAM Precharge Time Acquisition/ Sharing Time 1-255 TINST (TPRE) 1-255 TINST (TACQ) External and Internal External and Internal Channels share Channels are charged/discharged charge If ADPRE 0 If ADACQ 0 Conversion Time (Traditional Timing of ADC Conversion) TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b4 b1 b0 b6 b7 b2 b8 b3 b9 b5 Conversion starts Holding capacitor CHOLD is disconnected from analog input (typically 100 ns) If ADPRE = 0 If ADACQ = 0 (Traditional Operation Start) Set GO/DONE bit 31.4.5 On the following cycle: AADRES0H:AADRES0L is loaded, ADIF bit is set, GO/DONE bit is cleared ADDITIONAL SAMPLE AND HOLD CAPACITANCE Additional capacitance can be added in parallel with the internal sample and hold capacitor (CHOLD) by using the ADCAP register. This register selects a digitally programmable capacitance which is added to the ADC conversion bus, increasing the effective internal capacitance of the sample and hold capacitor in the ADC module. This is used to improve the match between internal and external capacitance for a better sensing performance. The additional capacitance does not affect analog performance of the ADC because it is not connected during conversion. See Figure 31-11. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 438 PIC18(L)F27/47K40 31.5 Computation Operation The ADC module hardware is equipped with post conversion computation features. These features provide data post-processing functions that can be operated on the ADC conversion result, including digital filtering/averaging and threshold comparison functions. FIGURE 31-11: COMPUTATIONAL FEATURES SIMPLIFIED BLOCK DIAGRAM Rev. 10-000260B 8/4/2015 ADCALC<2:0> ADMD<2:0> ADRES ADFILT Average/ Filter 1 0 Error Calculation ADERR Set Interrupt Flag Threshold Logic ADPREV ADSTPT ADPSIS ADUTHR ADLTHR The operation of the ADC computational features is controlled by ADMD <2:0> bits in the ADCON2 register. The module can be operated in one of five modes: * Basic: This is a legacy mode. In this mode, ADC conversion occurs on single (ADDSEN = 0) or double (ADDSEN = 1) samples. ADIF is set after all the conversion are complete. * Accumulate: With each trigger, the ADC conversion result is added to accumulator and ADCNT increments. ADIF is set after each conversion. ADTIF is set according to the calculation mode. * Average: With each trigger, the ADC conversion result is added to the accumulator. When the ADRPT number of samples have been accumulated, a threshold test is performed. Upon the next trigger, the accumulator is cleared. For the subsequent tests, additional ADRPT samples are required to be accumulated. * Burst Average: At the trigger, the accumulator is cleared. The ADC conversion results are then collected repetitively until ADRPT samples are accumulated and finally the threshold is tested. * Low-Pass Filter (LPF): With each trigger, the ADC conversion result is sent through a filter. When ADRPT samples have occurred, a threshold test is performed. Every trigger after that the ADC conversion result is sent through the filter and another threshold test is performed. The five modes are summarized in Table 31-3 below. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 439 2016 Microchip Technology Inc. TABLE 31-3: COMPUTATION MODES Bit Clear Conditions Value after Trigger completion Threshold Operations Value at ADTIF interrupt Preliminary Mode ADMD ADACC and ADCNT ADACC ADCNT Retrigger Threshold Test Interrupt ADAOV ADFLTR ADCNT Basic 0 ADACLR = 1 Unchanged Unchanged No Every Sample If threshold=true N/A N/A count Accumulate 1 ADACLR = 1 S + ADACC or (S2-S1) + ADACC If (ADCNT=FF): ADCNT, otherwise: ADCNT+1 No Every Sample If threshold=true ADACC Overflow ADACC/2ADCRS count Average 2 ADACLR = 1 or ADCNT>=ADRPT at ADGO or retrigger S + ADACC or (S2-S1) + ADACC If (ADCNT=FF): ADCNT, otherwise: ADCNT+1 No If ADCNT>= ADRPT If threshold=true ADACC Overflow ADACC/2ADCRS count Burst Average 3 ADACLR = 1 or ADGO set or retrigger Each repetition: same as Average End with sum of all samples Each repetition: same as Average End with ADCNT=ADRPT Repeat while ADCNT<ADRPT If ADCNT>= ADRPT If threshold=true ADACC Overflow ADACC/2ADCRS ADRPT Low-pass Filter 4 ADACLR = 1 S+ADACC-ADACC/ 2ADCRS or (S2-S1)+ADACC-ADACC/ ADCRS 2 If (ADCNT=FF): ADCNT, otherwise: ADCNT+1 No If ADCNT>= ADRPT If threshold=true ADACC Overflow Filtered Value count Note: S1 and S2 are abbreviations for Sample 1 and Sample 2, respectively. When ADDSEN = 0, S1 = ADRES; When ADDSEN = 1, S1 = ADPREV and S2 = ADRES. PIC18(L)F27/47K40 DS40001844B-page 440 PIC18(L)F27/47K40 31.5.1 DIGITAL FILTER/AVERAGE The digital filter/average module consists of an accumulator with data feedback options, and control logic to determine when threshold tests need to be applied. The accumulator is a 16-bit wide register which can be accessed through the ADACCH:ADACCL register pair. Upon each trigger event (the ADGO bit set or external event trigger), the ADC conversion result is added to the accumulator. If the accumulated value exceeds 2(accumulator_width)-1 = 216 = 65535, the overflow bit ADAOV in the ADSTAT register is set. The number of samples to be accumulated is determined by the ADRPT (A/D Repeat Setting) register. Each time a sample is added to the accumulator, the ADCNT register is incremented. Once ADRPT samples are accumulated (ADCNT = ADRPT), an accumulator clear command can be issued by the software by setting the ADACLR bit in the ADCON2 register. Setting the ADACLR bit will also clear the ADAOV (Accumulator overflow) bit in the ADSTAT TABLE 31-4: When ADC is operating from FRC, five FRC clock cycles are required to execute the ADACC clearing operation. The ADCRS <2:0> bits in the ADCON2 register control the data shift on the accumulator result, which effectively divides the value in accumulator (ADACCH:ADACCL) register pair. For the Accumulate mode of the digital filter, the shift provides a simple scaling operation. For the Average/Burst Average mode, the shift bits are used to determine number of samples for averaging. For the Low-pass Filter mode, the shift is an integral part of the filter, and determines the cut-off frequency of the filter. Table 31-4 shows the -3 dB cut-off frequency in T (radians) and the highest signal attenuation obtained by this filter at nyquist frequency (T = ). T (radians) @ -3 dB Frequency dB @ Fnyquist=1/(2T) 1 0.72 -9.5 2 0.284 -16.9 3 0.134 -23.5 4 0.065 -29.8 5 0.032 -36.0 6 0.016 -42.0 7 0.0078 -48.1 BASIC MODE 31.5.4 Basic mode (ADMD = 000) disables all additional computation features. In this mode, no accumulation occurs but threshold error comparison is performed. Double sampling, Continuous mode, and all CVD features are still available, but no features involving the digital filter/average features are used. 31.5.3 Note: LOW-PASS FILTER -3 dB CUT-OFF FREQUENCY ADCRS 31.5.2 register, as well as the ADCNT register. The ADACLR bit is cleared by the hardware when accumulator clearing action is complete. ACCUMULATE MODE In Accumulate mode (ADMD = 001), after every conversion, the ADC result is added to the ADACC register. The ADACC register is right-shifted by the value of the ADCRS bits in the ADCON2 register. This right-shifted value is copied in to the ADFLT register. The Formatting mode does not affect the right-justification of the ADACC value. Upon each sample, ADCNT is also incremented, incrementing the number of samples accumulated. After each sample and accumulation, the ADACC value has a threshold comparison performed on it (see Section 31.5.7 "Threshold Comparison") and the ADTIF interrupt may trigger. 2016 Microchip Technology Inc. AVERAGE MODE In Average Mode (ADMD = 010), the ADACC registers accumulate with each ADC sample, much as in Accumulate mode, and the ADCNT register increments with each sample. The ADFLT register is also updated with the right-shifted value of the ADACC register. The value of the ADCRS bits governs the number of right shifts. However, in Average mode, the threshold comparison is performed upon ADCNT being greater than or equal to a user-defined ADRPT value. In this mode when ADRPT = 2^ADCNT, then the final accumulated value will be divided by number of samples, allowing for a threshold comparison operation on the average of all gathered samples. Preliminary DS40001844B-page 441 PIC18(L)F27/47K40 31.5.5 BURST AVERAGE MODE 31.5.7 The Burst Average mode (ADMD = 011) acts the same as the Average mode in most respects. The one way it differs is that it continuously retriggers ADC sampling until the ADCNT value is greater than or equal to ADRPT, even if Continuous Sampling mode (see Section 31.5.8 "Continuous Sampling mode") is not enabled. This allows for a threshold comparison on the average of a short burst of ADC samples. 31.5.6 LOW-PASS FILTER MODE The Low-pass Filter mode (ADMD = 100) acts similarly to the Average mode in how it handles samples (accumulates samples until ADCNT value greater than or equal to ADRPT, then triggers threshold comparison), but instead of a simple average, it performs a low-pass filter operation on all of the samples, reducing the effect of high-frequency noise on the average, then performs a threshold comparison on the results. (see Table 31-3 for a more detailed description of the mathematical operation). In this mode, the ADCRS bits determine the cut-off frequency of the low-pass filter (as demonstrated by Table 31-4). THRESHOLD COMPARISON At the end of each computation: * The conversion results are latched and held stable at the end-of-conversion. * The error is calculated based on a difference calculation which is selected by the ADCALC<2:0> bits in the ADCON3 register. The value can be one of the following calculations (see Register 31-4 for more details): - The first derivative of single measurements - The CVD result in CVD mode - The current result vs. a setpoint - The current result vs. the filtered/average result - The first derivative of the filtered/average value - Filtered/average value vs. a setpoint * The result of the calculation (ADERR) is compared to the upper and lower thresholds, ADUTH<ADUTHH:ADUTHL> and ADLTH<ADLTHH:ADLTHL> registers, to set the ADUTHR and ADLTHR flag bits. The threshold logic is selected by ADTMD<2:0> bits in the ADCON3 register. The threshold trigger option can be one of the following: - Never interrupt - Error is less than lower threshold - Error is greater than or equal to lower threshold - Error is between thresholds (inclusive) - Error is outside of thresholds - Error is less than or equal to upper threshold - Error is greater than upper threshold - Always interrupt regardless of threshold test results - If the threshold condition is met, the threshold interrupt flag ADTIF is set. Note 1: The threshold operations. tests are signed 2: If ADAOV is set, a threshold interrupt is signaled. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 442 PIC18(L)F27/47K40 31.5.8 CONTINUOUS SAMPLING MODE 31.5.9 Setting the ADCONT bit in the ADCON0 register automatically retriggers a new conversion cycle after updating the ADACC register. That means the ADGO bit is set to generate automatic retriggering, until the device Reset occurs or the A/D Stop-on-interrupt bit (ADSOI in the ADCON3 register) is set (correct logic). 31.6 DOUBLE SAMPLE CONVERSION Double sampling is enabled by setting the ADDSEN bit of the ADCON1 register. When this bit is set, two conversions are required before the module will calculate threshold error (each conversion must still be triggered separately). The first conversion will set the ADMATH bit of the ADSTAT register and update ADACC, but will not calculate ADERR or trigger ADTIF. When the second conversion completes, the first value is transferred to ADPREV (depending on the setting of ADPSIS) and the value of the second conversion is placed into ADRES. Only upon the completion of the second conversion is ADERR calculated and ADTIF triggered (depending on the value of ADCALC). Register Definitions: ADC Control REGISTER 31-1: ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 U-0 R/W/HC-0 ADON ADCONT -- ADCS -- ADFM -- ADGO bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled bit 6 ADCONT: ADC Continuous Operation Enable bit 1 = ADGO is retriggered upon completion of each conversion trigger until ADTIF is set (if ADSOI is set) or until ADGO is cleared (regardless of the value of ADSOI) 0 = ADC is cleared upon completion of each conversion trigger bit 5 Unimplemented: Read as `0' bit 4 ADCS: ADC Clock Selection bit 1 = Clock supplied from FRC dedicated oscillator 0 = Clock supplied by FOSC, divided according to ADCLK register bit 3 Unimplemented: Read as `0' bit 2 ADFM: ADC results Format/alignment Selection 1 = ADRES and ADPREV data are right-justified 0 = ADRES and ADPREV data are left-justified, zero-filled bit 1 Unimplemented: Read as `0' bit 0 ADGO: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. The bit is cleared by hardware as determined by the ADCONT bit 0 = ADC conversion completed/not in progress 2016 Microchip Technology Inc. Preliminary DS40001844B-page 443 PIC18(L)F27/47K40 REGISTER 31-2: ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 ADPPOL ADIPEN ADGPOL -- -- -- -- ADDSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7 ADDPOL: Precharge Polarity bit If ADPRE>0x00: ADPPOL Action During 1st Precharge Stage External (selected analog I/O pin) Internal (AD sampling capacitor) 1 Shorted to AVDD CHOLD shorted to VSS 0 Shorted to VSS CHOLD shorted to AVDD Otherwise: The bit is ignored bit 6 ADIPEN: A/D Inverted Precharge Enable bit If ADDSEN = 1 1 = The precharge and guard signals in the second conversion cycle are the opposite polarity of the first cycle 0 = Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL Otherwise: The bit is ignored bit 5 ADGPOL: Guard Ring Polarity Selection bit 1 = ADC guard Ring outputs start as digital high during Precharge stage 0 = ADC guard Ring outputs start as digital low during Precharge stage bit 4-1 Unimplemented: Read as `0' bit 0 ADDSEN: Double-sample enable bit 1 = Two conversions are performed on each trigger. Data from the first conversion appears in ADPREV 0 = One conversion is performed for each trigger 2016 Microchip Technology Inc. Preliminary DS40001844B-page 444 PIC18(L)F27/47K40 REGISTER 31-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 ADPSIS R/W-0/0 R/W-0/0 ADCRS<2:0> R/W/HC-0 ADACLR R/W-0/0 R/W-0/0 R/W-0/0 ADMD<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 ADPSIS: ADC Previous Sample Input Select bits 1 = ADFLTR is transfered to ADPREV at start-of-conversion 0 = ADRES is transfered to ADPREV at start-of-conversion bit 6-4 ADCRS<2:0>: ADC Accumulated Calculation Right Shift Select bits If ADMD = 100: Low-pass filter time constant is 2ADCRS, filter gain is 1:1 If ADMD = 001, 010 or 011: The accumulated value is right-shifted by ADCRS (divided by 2ADCRS)(1,2) Otherwise: Bits are ignored bit 3 ADACLR: A/D Accumulator Clear Command bit(3) 0 = Clearing action is complete (or not started) 1 = ADACC, ADAOV and ADCNT registers are cleared bit 2-0 ADMD<2:0>: ADC Operating Mode Selection bits(4) 111-101 = Reserved 100 = Low-pass Filter mode 011 = Burst Average mode 010 = Average mode 001 = Accumulate mode 000 = Basic (Legacy) mode Note 1: 2: 3: 4: To correctly calculate an average, the number of samples (set in ADRPT) must be 2ADCRS. ADCRS = 3'b111 is a reserved option. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions. See Table 31-2 for Full mode descriptions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 445 PIC18(L)F27/47K40 REGISTER 31-4: U-0 ADCON3: ADC CONTROL REGISTER 3 R/W-0/0 R/W-0/0 R/W-0/0 ADCALC<2:0> -- R/W/HC-0 R/W-0/0 ADSOI R/W-0/0 R/W-0/0 ADTMD<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as `0' bit 6-4 ADCALC<2:0>: ADC Error Calculation Mode Select bits Action During 1st Precharge Stage ADCALC ADDSEN = 0 Single-Sample Mode ADDSEN = 1 CVD Double-Sample Mode(1) Application 111 Reserved Reserved Reserved Reserved 110 Reserved Reserved 101 ADLFTR-ADSTPT ADFLTR-ADSTPT Average/filtered value vs. setpoint 100 ADPREV-ADFLTR ADPREV-ADFLTR First derivative of filtered value(3) (negative) 011 Reserved 010 ADRES-ADFLTR (ADRES-ADPREV)-ADFLTR Actual result vs. averaged/filtered value Reserved 001 ADRES-ADSTPT (ADRES-ADPREV)-ADSTPT Actual result vs.setpoint 000 ADRES-ADPREV ADRES-ADPREV Reserved First derivative of single measurement(2) Actual CVD result in CVD mode(2) bit 3 ADSOI: ADC Stop-on-Interrupt bit If ADCONT = 1: 1 = ADGO is cleared when the threshold conditions are met, otherwise the conversion is retriggered 0 = ADGO is not cleared by hardware, must be cleared by software to stop retriggers bit 2-0 ADTMD<2:0>: Threshold Interrupt Mode Select bits 111 = Interrupt regardless of threshold test results 110 = Interrupt if ADERR>ADUTH 101 = Interrupt if ADERRADUTH 100 = Interrupt if ADERRADLTH or ADERR>ADUTH 011 = Interrupt if ADERR>ADLTH and ADERR<ADUTH 010 = Interrupt if ADERRADLTH 001 = Interrupt if ADERR<ADLTH 000 = Never interrupt Note 1: 2: 3: When ADPSIS = 0, the value of ADRES-ADPREV) is the value of (S2-S1) from Table 31-3. When ADPSIS = 0 When ADPSIS = 1. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 446 PIC18(L)F27/47K40 REGISTER 31-5: ADSTAT: ADC STATUS REGISTER R-0/0 R-0/0 R-0/0 R/HS/HC-0/0 U-0 ADAOV ADUTHR ADLTHR ADMATH -- R-0/0 R-0/0 R-0/0 ADSTAT<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared HS/HC = Bit is set/cleared by hardware bit 7 ADAOV: ADC Accumulator Overflow bit 1 = ADC accumulator or ADERR calculation have overflowed 0 = ADC accumulator and ADERR calculation have not overflowed bit 6 ADUTHR: ADC Module Greater-than Upper Threshold Flag bit 1 = ADERR >ADUTH 0 = ADERRADUTH bit 5 ADLTHR: ADC Module Less-than Lower Threshold Flag bit 1 = ADERR<ADLTH 0 = ADERRADLTH bit 4 ADMATH: ADC Module Computation Status bit 1 = Registers ADACC, ADFLTR, ADUTH, ADLTH and the ADAOV bit are updating or have already updated 0 = Associated registers/bits have not changed since this bit was last cleared bit 3 Unimplemented: Read as `0' bit 2-0 ADSTAT<2:0>: ADC Module Cycle Multistage Status bits(1) 111 = ADC module is in 2nd conversion stage 110 = ADC module is in 2nd acquisition stage 101 = ADC module is in 2nd precharge stage 100 = Not used 011 = ADC module is in 1st conversion stage 010 = ADC module is in 1st acquisition stage 001 = ADC module is in 1st precharge stage 000 = ADC module is not converting Note 1: If ADCS = 1, and FOSC<FRC, these bits may be invalid. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 447 PIC18(L)F27/47K40 REGISTER 31-6: ADCLK: ADC CLOCK SELECTION REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADCS<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 ADCS<5:0>: ADC Conversion Clock Select bits 111111 = FOSC/128 111110 = FOSC/126 111101 = FOSC/124 000000 = FOSC/2 REGISTER 31-7: ADREF: ADC REFERENCE SELECTION REGISTER U-0 U-0 U-0 R/W-0/0 U-0 U-0 -- -- -- ADNREF -- -- R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4 ADNREF: ADC Negative Voltage Reference Selection bit 1 = VREF- is connected to external VREF0 = VREF- is connected to AVSS bit 3-2 Unimplemented: Read as `0' bit 1-0 ADPREF: ADC Positive Voltage Reference Selection bits 11 = VREF+ is connected to internal Fixed Voltage Reference (FVR) module 10 = VREF+ is connected to external VREF+ 01 = Reserved 00 = VREF+ is connected to VDD 2016 Microchip Technology Inc. Preliminary DS40001844B-page 448 PIC18(L)F27/47K40 REGISTER 31-8: ADPCH: ADC POSITIVE CHANNEL SELECTION REGISTER U-0 U-0 -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADPCH<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 Unimplemented: Read as `0' bit 5-0 ADPCH<5:0>: ADC Positive Input Channel Selection bits 111111 = Fixed Voltage Reference (FVR)(2) 111110 = DAC1 output(1) 111101 = Temperature Indicator(3) 111100 = AVSS (Analog Ground) 111011 = Reserved. No channel connected. 100010 = ANE2(4) 100001 = ANE1(4) 100000 = ANE0(4) 011111 = AND7(4) 011110 = AND6(4) 011101 = AND5(4) 011100 = AND4(4) 011011 = AND3(4) 011010 = AND2(4) 011001 = AND1(4) 011000 = AND0(4) Note 1: 2: 3: 4: 010111 = ANC7 010110 = ANC6 010101 = ANC5 010100 = ANC4 010011 = ANC3 010010 = ANC2 010001 = ANC1 010000 = ANC0 001111 = ANB7 001110 = ANB6 001101 = ANB5 001100 = ANB4 001011 = ANB3 001010 = ANB2 001001 = ANB1 001000 = ANB0 000111 = ANA7 000110 = ANA6 000101 = ANA5 000100 = ANA4 000011 = ANA3 000010 = ANA2 000001 = ANA1 000000 = ANA0 See Section 30.0 "5-Bit Digital-to-Analog Converter (DAC) Module" for more information. See Section 28.0 "Fixed Voltage Reference (FVR)" for more information. See Section 29.0 "Temperature Indicator Module" for more information. PIC18F47K40 only. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 449 PIC18(L)F27/47K40 REGISTER 31-9: R/W-0/0 ADPRE: ADC PRECHARGE TIME CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADPRE<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADPRE<7:0>: Precharge Time Select bits 11111111 = Precharge time is 255 clocks of the selected ADC clock 11111110 = Precharge time is 254 clocks of the selected ADC clock 00000001 = Precharge time is 1 clock of the selected ADC clock 00000000 = Precharge time is not included in the data conversion cycle REGISTER 31-10: ADACQ: ADC ACQUISITION TIME CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADACQ<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note: ADACQ<7:0>: Acquisition (charge share time) Select bits 11111111 = Acquisition time is 255 clocks of the selected ADC clock 11111110 = Acquisition time is 254 clocks of the selected ADC clock 00000001 = Acquisition time is 1 clock of the selected ADC clock 00000000 = Acquisition time is not included in the data conversion cycle If ADPRE is not equal to `0', then ADACQ = b'00000000 means Acquisition time is 256 clocks of the selected ADC clock. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 450 PIC18(L)F27/47K40 REGISTER 31-11: ADCAP: ADC ADDITIONAL SAMPLE CAPACITOR SELECTION REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADCAP<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 ADCAP<4:0>: ADC Additional Sample Capacitor Selection bits 11111 = 31 pF 11110 = 30 pF 11101 = 29 pF 00011 = 3 pF 00010 = 2 pF 00001 = 1 pF 00000 = No additional capacitance REGISTER 31-12: ADRPT: ADC REPEAT SETTING REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADRPT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Unimplemented: Read as `0' bit 7-0 ADRPT<7:0>: ADC Repeat Threshold bits Counts the number of times that the ADC has been triggered and is used along with ADCNT to determine when the error threshold is checked when the computation is Low-pass Filter, Burst Average, or Average modes. See Table 31-3 for more details. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 451 PIC18(L)F27/47K40 REGISTER 31-13: ADCNT: ADC REPEAT COUNTER REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADCNT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADCNT<7:0>: ADC Repeat Count bits Determines the number of times that the ADC is triggered before the threshold is checked when the computation is Low-pass Filter, Burst Average, or Average modes. See Table 31-2 for more details. REGISTER 31-14: ADFLTRH: ADC FILTER HIGH BYTE REGISTER R-x R-x R-x R-x R-x R-x R-x R-x ADFLTR<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADFLTR<15:8>: ADC Filter Output Most Significant bits In Accumulate, Average, and Burst Average mode, this is equal to ADACC right shifted by the ADCRS bits of ADCON2. In LPF mode, this is the output of the Low-pass Filter. REGISTER 31-15: ADFLTRL: ADC FILTER LOW BYTE REGISTER R-x R-x R-x R-x R-x R-x R-x R-x ADFLTR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADFLTR<7:0>: ADC Filter Output Least Significant bits In Accumulate, Average, and Burst Average mode, this is equal to ADACC right shifted by the ADCRS bits of ADCON2. In LPF mode, this is the output of the Low-pass Filter. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 452 PIC18(L)F27/47K40 REGISTER 31-16: ADRESH: ADC RESULT REGISTER HIGH, ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result. REGISTER 31-17: ADRESL: ADC RESULT REGISTER LOW, ADFM = 0 R/W-x/u R/W-x/u ADRES<1:0> U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits. Lower two bits of 10-bit conversion result. bit 5-0 Reserved: Do not use. REGISTER 31-18: ADRESH: ADC RESULT REGISTER HIGH, ADFM = 1 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Sample Result bits. Upper two bits of 10-bit conversion result. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 453 PIC18(L)F27/47K40 REGISTER 31-19: ADRESL: ADC RESULT REGISTER LOW, ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits. Lower eight bits of 10-bit conversion result. REGISTER 31-20: ADPREVH: ADC PREVIOUS RESULT REGISTER R-x R-x R-x R-x R-x R-x R-x R-x ADPREV<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: ADPREV<15:8>: Previous ADC Results bits If ADPSIS = 1: Upper byte of ADFLTR at the start of current ADC conversion If ADPSIS = 0: Upper bits of ADRES at the start of current ADC conversion(1) If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the ADFM bit. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 454 PIC18(L)F27/47K40 REGISTER 31-21: ADPREVL: ADC PREVIOUS RESULT REGISTER R-x R-x R-x R-x R-x R-x R-x R-x ADPREV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 Note 1: ADPREV<7:0>: Previous ADC Results bits If ADPSIS = 1: Lower byte of ADFLTR at the start of current ADC conversion If ADPSIS = 0: Lower bits of ADRES at the start of current ADC conversion(1) If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the ADFM bit. REGISTER 31-22: ADACCH: ADC ACCUMULATOR REGISTER HIGH R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADACC<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADACC<15:8>: ADC Accumulator MSB. Upper eight bits of accumulator value. See Table 31-2 for more details. REGISTER 31-23: ADACCL: ADC ACCUMULATOR REGISTER LOW R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADACC<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADACC<7:0>: ADC Accumulator LSB. Lower eight bits of accumulator value. See Table 31-2 for more details. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 455 PIC18(L)F27/47K40 REGISTER 31-24: ADSTPTH: ADC THRESHOLD SETPOINT REGISTER HIGH R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADSTPT<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADSTPT<15:8>: ADC Threshold Setpoint MSB. Upper byte of ADC threshold setpoint, depending on ADCALC, may be used to determine ADERR, see Register 23-1 for more details. REGISTER 31-25: ADSTPTL: ADC THRESHOLD SETPOINT REGISTER LOW R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x ADSTPT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADSTPT<7:0>: ADC Threshold Setpoint LSB. Lower byte of ADC threshold setpoint, depending on ADCALC, may be used to determine ADERR, see Register 23-1 for more details. REGISTER 31-26: ADERRH: ADC SETPOINT ERROR REGISTER HIGH R-x R-x R-x R-x R-x R-x R-x R-x ADERR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADERR<7:0>: ADC Setpoint Error MSB. Upper byte of ADC Setpoint Error. Setpoint Error calculation is determined by ADCALC bits of ADCON3, see Register 23-1 for more details. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 456 PIC18(L)F27/47K40 REGISTER 31-27: ADERRL: ADC SETPOINT ERROR LOW BYTE REGISTER R-x R-x R-x R-x R-x R-x R-x R-x ADERR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADERR<7:0>: ADC Setpoint Error LSB. Lower byte of ADC Setpoint Error calculation is determined by ADCALC bits of ADCON3, see Register 23-1 for more details. REGISTER 31-28: ADLTHH: ADC LOWER THRESHOLD HIGH BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x ADLTH<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADLTH<15:8>: ADC Lower Threshold MSB. ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison. REGISTER 31-29: ADLTHL: ADC LOWER THRESHOLD LOW BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x ADLTH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADLTH<7:0>: ADC Lower Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 457 PIC18(L)F27/47K40 REGISTER 31-30: ADUTHH: ADC UPPER THRESHOLD HIGH BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x ADUTH<15:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADUTH<15:8>: ADC Upper Threshold MSB. ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison. REGISTER 31-31: ADUTHL: ADC UPPER THRESHOLD LOW BYTE REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x R/W-x/x ADUTH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-0 ADUTH<7:0>: ADC Upper Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be triggered by the results of this comparison. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 458 PIC18(L)F27/47K40 REGISTER 31-32: ADACT: ADC AUTO CONVERSION TRIGGER CONTROL REGISTER U-0 U-0 U-0 -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADACT<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets `1' = Bit is set `0' = Bit is cleared bit 7-5 Unimplemented: Read as `0' bit 4-0 ADACT<4:0>: Auto-Conversion Trigger Select Bits 11111 = Software write to ADPCH 11110 = Reserved, do not use 11101 = Software read of ADRESH 11100 = Software read of ADERRH 11011 = Reserved, do not use 10000 = Reserved, do not use 01111 = Interrupt-on-change Interrupt Flag 01110 = C2_out 01101 = C1_out 01100 = PWM4_out 01011 = PWM3_out 01010 = CCP2_trigger 01001 = CCP1_trigger 01000 = TMR6_postscaled 00111 = TMR5_overflow 00110 = TMR4_postscaled 00101 = TMR3_overflow 00100 = TMR2_postscaled 00011 = TMR1_overflow 00010 = TMR0_overflow 00001 = Pin selected by ADACTPPS 00000 = External Trigger Disabled 2016 Microchip Technology Inc. Preliminary DS40001844B-page 459 PIC18(L)F27/47K40 TABLE 31-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Register on Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIE1 OSCFIE CSWIE -- -- -- -- ADTIE ADIE 179 PIR1 OSCFIF CSWIF -- -- -- -- ADTIF ADIF 171 ADCON0 ADON ADCON -- ADCS -- ADFM -- ADGO 443 ADIPEN ADGPOL -- -- -- -- ADDSEN 444 INTCON ADCON1 ADPPOL ADCON2 ADPSIS ADCON3 -- ADACT -- ADCRS<2:0> ADACLR ADCALC<2:0> -- -- ADMD<2:0> ADSOI -- 445 ADTMD<2:0> 446 ADACT<4:0> 445 ADRESH ADRESH<7:0> 453, 453 ADRESL ADRESL<7:0> 453, 454 ADPREVH ADPREV<15:8> 454 ADPREVL ADPREV<7:0> 455 ADACCH ADACC<15:8> 455 ADACCL ADACC<7:0> 455 ADSTPTH ADSTPT<15:8> 456 ADSTPT ADSTPT<7:0> 456 ADERRL ADERR<7:0> 457 ADLTHH ADLTH<15:8> 457 ADLTHL ADLTH<7:0> 457 ADUTHH ADUTH<15:8> 458 ADUTHL ADUTH<7:0> ADSTAT ADAOV ADUTHR ADCLK -- -- ADREF -- -- ADPCH -- -- ADLTHR ADMATH -- ADNREF ADACQ ADACQ<7:0> -- -- 448 ADPREF<1:0> ADPCH<5:0> ADPRE<7:0> -- 447 ADCS<5:0> -- ADPRE ADCAP 458 ADSTAT<3:0> -- 448 449 450 450 ADCAP<4:0> 451 ADRPT ADRPT<7:0> 451 ADCNT ADCNT<7:0> 452 ADFLTR<15:8> 452 ADFLTRH ADFLTRL FVRCON DAC1CON1 OSCSTAT Legend: ADFLTR<7:0> FVREN FVRRDY TSEN -- -- -- EXTOR HFOR MFOR TSRNG 452 CDAFVR<1:0> ADFVR<1:0> DAC1R<4:0> LFOR SOR ADOR 418 424 -- PLLR 39 -- = unimplemented read as `0'. Shaded cells are not used for the ADC module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 460 PIC18(L)F27/47K40 32.0 Note: COMPARATOR MODULE 32.1 The PIC18(L)F27/47K40 devices have two comparators. Therefore, all information in this section refers to both C1 and C2. Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. A single comparator is shown in Figure 32-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. FIGURE 32-1: The analog comparator module includes the following features: * * * * * * * * * * * * Programmable input selection Programmable output polarity Rising/falling output edge interrupts Wake-up from Sleep CWG Auto-shutdown source Selectable voltage reference ADC Auto-trigger TMR1/3/5 Gate TMR2/4/6 Reset CCP Capture Mode Input DSM Modulator Source Input and Window signal to Signal Measurement Timer 2016 Microchip Technology Inc. Comparator Overview SINGLE COMPARATOR VIN+ + VIN- - Output VINVIN+ Output Note: Preliminary The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. DS40001844B-page 461 PIC18(L)F27/47K40 FIGURE 32-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxEN(1) 3 CxINTP Interrupt det CXIN0- 0 CXIN1- 1 CXIN2- 2 MUX CXIN3- 3 Set CxIF Reserved 4 Reserved 5 FVR Buffer 2 6 CxINTN Interrupt (2) det CXPOL CxNCH D Cx CxPCH to CMXCON0 (CXOUT) and CMOUT (MCXOUT) Q + EN Q1 7 CxHYS AGND CXSYNC TRIS bit 0 PPS D CXIN0+ 0 CXIN1+ 1 Reserved 2 Reserved 3 Reserved 4 DAC_Output 5 FVR Buffer 2 6 From Timer1 tmr1_clk MUX Q CXOUT RxyPPS 1 sync_CxOUT To Other Peripherals (2) 7 AGND CxEN CXPCH<2:0> 3 Note 1: 2: When CxEN = 0, the comparator will produce a `0' at the output. When CxEN = 0, all multiplexer inputs are disconnected. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 462 PIC18(L)F27/47K40 32.2 Register Definitions: Comparator Control Long bit name prefixes for the Comparators are shown in Table 32-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 32-1: Peripheral Bit Name Prefix C1 C1 C2 C2 REGISTER 32-1: R/W-0/0 EN CMxCON0: COMPARATOR x CONTROL REGISTER 0 R-0/0 U-0 R/W-0/0 U-0 U-1 R/W-0/0 R/W-0/0 OUT -- POL -- -- HYS SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 EN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 OUT: Comparator Output bit If POL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN If POL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN bit 5 Unimplemented: Read as `0' bit 4 POL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 Unimplemented: Read as `0' bit 2 Unimplemented: Read as `1' bit 1 HYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 SYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1/3/5 and I/O pin is synchronous to changes on Timer1 clock source. 0 = Comparator output to Timer1/3/5 and I/O pin is asynchronous Output updated on the falling edge of Timer1/3/5 clock source. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 463 PIC18(L)F27/47K40 REGISTER 32-2: CMxCON1: COMPARATOR x CONTROL REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 -- -- -- -- -- -- INTP INTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-2 Unimplemented: Read as `0' bit 1 INTP: Comparator Interrupt on Positive-Going Edge Enable bit 1 = The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive-going edge of the CxOUT bit bit 0 INTN: Comparator Interrupt on Negative-Going Edge Enable bit 1 = The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative-going edge of the CxOUT bit REGISTER 32-3: U-0 CMxNCH: COMPARATOR x INVERTING CHANNEL SELECT REGISTER U-0 -- -- U-0 -- U-0 -- U-0 R/W-0/0 -- R/W-0/0 R/W-0/0 NCH<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-3 Unimplemented: Read as `0' bit 2-0 NCH<2:0>: Comparator Inverting Input Channel Select bits 111 = AVSS 110 = FVR_Buffer2 101 = CxNCH not connected 100 = CxNCH not connected 011 = CxIN3010 = CxIN2001 = CxIN1000 = CxIN0- 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 464 PIC18(L)F27/47K40 REGISTER 32-4: CMxPCH: COMPARATOR x NON-INVERTING CHANNEL SELECT REGISTER U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- R/W-0/0 R/W-0/0 R/W-0/0 PCH<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as `0' bit 2-0 PCH<2:0>: Comparator Non-Inverting Input Channel Select bits 111 = AVSS 110 = FVR_Buffer2 101 = DAC_Output 100 = CxPCH not connected 011 = CxPCH not connected 010 = CxPCH not connected 001 = CxIN1+ 000 = CxIN0+ REGISTER 32-5: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 -- -- -- -- -- -- MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-2 Unimplemented: Read as `0' bit 1 MC2OUT: Mirror copy of C2OUT bit bit 0 MC1OUT: Mirror copy of C1OUT bit 2016 Microchip Technology Inc. Preliminary x = Bit is unknown DS40001844B-page 465 PIC18(L)F27/47K40 32.3 Comparator Control 32.3.3 Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 register (see Register 32-1) contains Control and Status bits for the following: * * * * * Enable Output Output polarity Hysteresis enable Timer1 output synchronization Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 32-2 shows the output state versus input conditions, including polarity control. TABLE 32-2: The CMxCON1 register (see Register 32-2) contains Control bits for the following: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 * Interrupt on positive/negative edge enables * Positive input channel selection * Negative input channel selection 32.3.1 COMPARATOR OUTPUT POLARITY COMPARATOR ENABLE Setting the EN bit of the CMxCON0 register enables the comparator for operation. Clearing the CxEN bit disables the comparator resulting in minimum current consumption. 32.3.2 COMPARATOR OUTPUT The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. The comparator output can also be routed to an external pin through the RxyPPS register (Register 17-2). The corresponding TRIS bit must be clear to enable the pin as an output. Note 1: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 466 PIC18(L)F27/47K40 32.4 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: See Comparator Specifications in Table 37-15 for more information. 32.5 Timer1/3/5 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1/3/5. See Section 19.8 "Timer1/3/5 Gate" for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 32.5.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from a comparator can be synchronized with Timer1 by setting the SYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 32-2) and the Timer1 Block Diagram (Figure 19-1) for more information. 32.6 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. 32.7 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxEN bit of the CMxCON0 register. Comparator Positive Input Selection Configuring the PCH<2:0> bits of the CMxPCH register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: * * * * CxIN0+, CxIN1+ analog pin DAC output FVR (Fixed Voltage Reference) AVSS (Ground) See Section 28.0 "Fixed Voltage Reference (FVR)" for more information on the Fixed Voltage Reference module. See Section 30.0 "5-Bit Digital-to-Analog Converter (DAC) Module" for more information on the DAC input signal. Any time the comparator is disabled (CxEN = 0), all comparator inputs are disabled. 32.8 Comparator Negative Input Selection The NCH<2:0> bits of the CMxNCH register direct an analog input pin and internal reference voltage or analog ground to the inverting input of the comparator: * CxIN0-, CxIN1-, CxIN2-, CxIN3- analog pin * FVR (Fixed Voltage Reference) * Analog Ground Note: To enable the interrupt, you must set the following bits: To use CxINy+ and CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. * EN and POL bits of the CMxCON0 register * CxIE bit of the PIE2 register * INTP bit of the CMxCON1 register (for a rising edge detection) * INTN bit of the CMxCON1 register (for a falling edge detection) * PEIE and GIE bits of the INTCON register 2016 Microchip Technology Inc. Preliminary DS40001844B-page 467 PIC18(L)F27/47K40 32.9 Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Table 37-15 and Table 3717 for more details. 32.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 32-3. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 32-3: ANALOG INPUT MODEL Rev. 10-000071A 8/2/2013 VDD RS < 10K Analog Input pin VT 0.6V RIC To Comparator ILEAKAGE(1) VA CPIN 5pF VT 0.6V VSS Legend: CPIN ILEAKAGE RIC RS VA VT = Input Capacitance = Leakage Current at the pin due to various junctions = Interconnect Resistance = Source Impedance = Analog Voltage = Threshold Voltage Note 1: See Section 37.0 "Electrical Specifications". 2016 Microchip Technology Inc. Preliminary DS40001844B-page 468 PIC18(L)F27/47K40 32.11 CWG1 Auto-Shutdown Source The output of the comparator module can be used as an auto-shutdown source for the CWG1 module. When the output of the comparator is active and the corresponding WGASxE is enabled, the CWG operation will be suspended immediately (see Section 24.10.1.2 "External Input Source"). 32.12 ADC Auto-Trigger Source The output of the comparator module can be used to trigger an ADC conversion. When the ADACT register is set to trigger on a comparator output, an ADC conversion will trigger when the Comparator output goes high. 32.13 TMR2/4/6 Reset The output of the comparator module can be used to reset Timer2. When the TxERS register is appropriately set, the timer will reset when the Comparator output goes high. 32.14 Operation in Sleep Mode The comparator module can operate during Sleep. The comparator clock source is based on the Timer1 clock source. If the Timer1 clock source is either the system clock (FOSC) or the instruction clock (FOSC/4), Timer1 will not operate during Sleep, and synchronized comparator outputs will not operate. A comparator interrupt will wake the device from Sleep. The CxIE bits of the PIE2 register must be set to enable comparator interrupts. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 469 PIC18(L)F27/47K40 TABLE 32-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page CMxCON0 EN OUT -- POL -- -- HYS SYNC 463 CMxCON1 -- -- -- -- -- -- CxINTP CxINTN 464 CMxNCH -- -- -- -- -- NCH<2:0> CMxPCH -- -- -- -- -- PCH<2:0> CMOUT -- -- -- -- -- -- MC2OUT 465 MC1OUT ADFVR<1:0> 465 FVRCON FVREN FVRRDY TSEN TSRNG INTCON GIE/GIEH PEIE/GIEL IPEN -- -- INT2EDG INT1EDG INT0EDG 169 PIR2 HLVDIF ZCDIF -- -- -- -- C2IF C1IF 172 PIE2 HLVDIE ZCDIE -- -- -- -- C2IE C1IE 180 IPR2 HLVDIP ZCDIP -- -- -- -- C2IP C1IP 188 PMD2 -- DACMD ADCMD -- -- CMP2MD CMP1MD ZCDMD 69 RxyPPS -- -- -- Legend: CDAFVR<1:0> 464 RxyPPS<4:0> 418 217 -- = unimplemented, read as `0'. Shaded cells are unused by the comparator module. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 470 PIC18(L)F27/47K40 33.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The HLVDINTH and HLVDINTL bits determine the overall operation of the module. When HLVDINTH is set, the module monitors for rises in VDD above the trip point set by the HLVDCON1 register. When HLVDINTL is set, the module monitors for drops in VDD below the trip point set by the HLVDCON1 register. When both the HLVDINTH and HLVDINTL bits are set, any changes above or below the trip point set by the HLVDCON1 register can be monitored. The PIC18(L)F2x/4xK40 of devices has a High/LowVoltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the direction of change from that point (positive going, negative going or both). If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt. The OUT bit can be read to determine if the voltage is greater than or less than the voltage level selected by the HLVDCON1 register. Complete control of the HLVD module is provided through the HLVDCON0 and HLVDCON1 register. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device. 33.1 When the HLVD module is enabled, a comparator uses an internally generated voltage reference as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage. The "trip point" voltage is the voltage level at which the device detects a high or low-voltage event, depending on the configuration of the module. The module's block diagram is shown in Figure 33-1. Since the HLVD can be software enabled through the HLVDEN bit, setting and clearing the enable bit does not produce a false HLVD event glitch. Each time the HLVD module is enabled, the circuitry requires some time to stabilize. The RDY bit (HLVDCON0<4>) is a read-only bit used to indicate when the band gap reference voltages are stable. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the HLVDIF bit. The module can only generate an interrupt after the module is turned ON and the band gap reference voltages are ready. FIGURE 33-1: Operation The trip point voltage is software programmable to any of 16 values. The trip point is selected by programming the HLVDSEL<3:0> bits (HLVDCON1<3:0>). HLVD MODULE BLOCK DIAGRAM VDD 16-to-1 MUX 4 HLVDSEL<3:0> HLVDEN HLVDOUT Trigger/ Interrupt Generation + HLVDRDY HLVDEN 2016 Microchip Technology Inc. HLVDIF HLVDINTH HLVDINTL Bandgap Reference Volatge Preliminary DS40001844B-page 471 PIC18(L)F27/47K40 33.2 HLVD Setup 33.3 To set up the HLVD module: 1. 2. 3. 4. 5. Select the desired HLVD trip point by writing the value to the HLVDSEL<3:0> bits of the HLVDCON1 register. Depending on the application to detect high-voltage peaks or low-voltage drops or both, set the HLVDINTH or HLVDINTL bit appropriately. Enable the HLVD module by setting the HLVDEN bit. Clear the HLVD interrupt flag (PIR2 register), which may have been set from a previous interrupt. If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE in the PIE2 register and GIE bits. An interrupt will not be generated until the HLVDRDY bit is set. Note: Before changing any module settings (HLVDINTH, HLVDINTL, HLVDSEL<3:0>), first disable the module (HLVDEN = 0), make the changes and re-enable the module. This prevents the generation of false HLVD events. 2016 Microchip Technology Inc. Current Consumption When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static current. The total current consumption, when enabled, is specified in electrical specification Parameter D206 (Table 37-3). Depending on the application, the HLVD module does not need to operate constantly. To reduce current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked. After such a check, the module could be disabled. 33.4 HLVD Start-up Time The internal reference voltage of the HLVD module, specified in electrical specification (Table 37-17), may be used by other internal circuitry, such as the programmable Brown-out Reset. If the HLVD or other circuits using the voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low or high-voltage condition can be reliably detected. This start-up time, TFVRST, is an interval that is independent of device clock speed. It is specified in electrical specification (Table 37-17). The HLVD interrupt flag is not enabled until TFVRST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (see Figure 33-2 or Figure 33-3). Preliminary DS40001844B-page 472 PIC18(L)F27/47K40 FIGURE 33-2: LOW-VOLTAGE DETECT OPERATION (HLVDINTL = 1) CASE 1: HLVDIF may not be Set VDD VHLVD HLVDIF Enable HLVD TFVRST HLVDRDY Band Gap Reference Voltage is Stable CASE 2: HLVDIF Cleared in Software VDD VHLVD HLVDIF Enable HLVD TFVRST HLVDRDY Band Gap Reference Voltage is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists 2016 Microchip Technology Inc. Preliminary DS40001844B-page 473 PIC18(L)F27/47K40 FIGURE 33-3: HIGH-VOLTAGE DETECT OPERATION (HLVDINTH = 1) CASE 1: HLVDIF may not be Set VHLVD VDD HLVDIF Enable HLVD TIRVST HLVDRDY HLVDIF Cleared in Software Band Gap Reference Voltage is Stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST HLVDRDY Band Gap Reference Voltage is Stable HLVDIF Cleared in Software HLVDIF Cleared in Software, HLVDIF Remains Set since HLVD Condition still Exists Applications FIGURE 33-4: In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For example, the HLVD module could be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a High-Voltage Detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature could save a design a few extra components and an attach signal (input pin). VA VB For general battery applications, Figure 33-4 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The interrupt could cause the execution of an Interrupt Service Routine (ISR), which would allow the application to perform "housekeeping tasks" and a controlled shutdown before the device voltage exits the valid operating range at TB. This would give the application a time window, represented by the difference between TA and TB, to safely exit. 2016 Microchip Technology Inc. TYPICAL LOW-VOLTAGE DETECT APPLICATION Voltage 33.5 Preliminary Time TA TB Legend: VA = HLVD trip point VB = Minimum valid device operating voltage DS40001844B-page 474 PIC18(L)F27/47K40 33.6 Operation During Sleep When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 33.7 Operation During Idle and Doze Modes In both Idle and Doze modes, the module is active and events are generated if peripheral is enabled. 33.8 Operation During Freeze When in Freeze mode, no new event or interrupt can be generated. The state of the LVDRDY bit is frozen. Register reads and writes through the CPU interface are allowed. 33.9 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 475 PIC18(L)F27/47K40 33.10 Register Definitions: HLVD Control Long bit name prefixes for the HLVD peripheral is shown in Table 33-1. Refer to Section 1.4.2.2 "Long Bit Names" for more information. TABLE 33-1: Peripheral Bit Name Prefix HLVD HLVD REGISTER 33-1: HLVDCON1: LOW-VOLTAGE DETECT CONTROL REGISTER 1 U-0 U-0 U-0 U-0 -- -- -- -- R/W-0/u R/W-0/u R/W-0/u R/W-0/u SEL<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 7-4 Unimplemented: Read as `0' bit 3-0 SEL<3:0>: High/Low Voltage Detection Limit Selection bits SEL<3:0> Typical Voltage 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Reserved 4.63V 4.32V 4.12V 3.91V 3.71V 3.60V 3.4V 3.09V 2.88V 2.78V 2.57V 2.47V 2.26V 2.06V 1.85V 2016 Microchip Technology Inc. Preliminary u = Bit is unchanged DS40001844B-page 476 PIC18(L)F27/47K40 REGISTER 33-2: HLVDCON0: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER 0 R/W-0/0 U-0 R-x R-x U-0 U-0 R/W-0/0 R/W-0/0 EN -- OUT RDY -- -- INTH INTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 7 EN: High/Low-voltage Detect Power Enable bit 1 = Enables HLVD, powers up HLVD circuit and supporting reference circuitry 0 = Disables HLVD, powers down HLVD and supporting circuitry bit 6 Unimplemented: Read as `0' bit 5 OUT: HLVD Comparator Output bit 1 = Voltage selected detection limit (HLVDL<3:0>) 0 = Voltage selected detection limit (HLVDL<3:0>) bit 4 RDY: Band Gap Reference Voltages Stable Status Flag bit 1 = Indicates HLVD Module is ready and output is stable 0 = Indicates HLVD Module is not ready bit 3-2 Unimplemented: Read as `0' bit 1 INTH: HLVD Positive going (High Voltage) Interrupt Enable 1 = HLVDIF will be set when voltage selected detection limit (HLVDSEL<3:0>) 0 = HLVDIF will not be set bit 0 INTL: HLVD Negative going (Low Voltage) Interrupt Enable 1 = HLVDIF will be set when voltage selected detection limit (HLVDSEL<3:0>) 0 = HLVDIF will not be set TABLE 33-2: REGISTERS ASSOCIATED WITH HIGH/LOW-VOLTAGE DETECT MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page HLVDCON0 EN -- OUT RDY -- -- INTH INTL 477 HLVDCON1 -- -- -- -- -- SEL<3:0> 476 IPEN -- INT2EDG INT1EDG INT0EDG 169 PIR2 HLVDIF ZCDIF -- -- -- -- C2IF C1IF 172 PIE2 HLVDIE ZCDIE -- -- -- -- C2IE C1IE 180 IPR2 HLVDIP ZCDIP -- -- -- -- C2IP C1IP 188 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD 67 INTCON PMD0 Legend: Note 1: GIE/GIEH PEIE/GIEL -- = unimplemented, read as `0'. Shaded cells are unused by the HLVD module. PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 477 PIC18(L)F27/47K40 34.0 IN-CIRCUIT SERIAL PROGRAMMINGTM (ICSPTM) 34.3 ICSPTM programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSPTM programming: * ICSPCLK * ICSPDAT * MCLR/VPP * VDD * VSS Connection to a target device is typically done through an ICSPTM header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 34-1. FIGURE 34-1: VDD In Program/Verify mode the program memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSPTM refer to the "PIC18(L)F2X/4XK40 Memory Programming Specification" (DS40001772). 34.1 The Low-Voltage Programming Entry mode allows the PIC(R) Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to `1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to `0'. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target High-Voltage Programming Entry Mode Low-Voltage Programming Entry Mode ICD RJ-11 STYLE CONNECTOR INTERFACE VPP/MCLR 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 34.2 Common Programming Interfaces 6 = No Connect Another connector often found in use with the PICkitTM programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 34-2. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 34-3 for more information. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 8.6 "MCLR" for more information. The LVP bit can only be reprogrammed to `0' by using the High-Voltage Programming mode. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 478 PIC18(L)F27/47K40 FIGURE 34-2: PICkitTM PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 34-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins. TYPICAL CONNECTION FOR ICSPTM PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 479 PIC18(L)F27/47K40 35.0 INSTRUCTION SET SUMMARY PIC18(L)F2x/4xK40 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of eight new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 35.1 Standard Instruction Set The standard PIC18 instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from these PIC(R) MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 35-2 lists byte-oriented, bit-oriented, literal and control operations. Table 35-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a') The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a') The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the four MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 35-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 35-2, lists the standard instructions recognized by the Microchip Assembler (MPASMTM). Section 35.1.1 "Standard Instruction Set" provides a description of each instruction. The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 480 PIC18(L)F27/47K40 TABLE 35-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. d Destination select bit d = 0: store result in WREG d = 1: store result in file register f dest Destination: either the WREG register or the specified register file location. f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). fs 12-bit Register file address (000h to FFFh). This is the source address. fd 12-bit Register file address (000h to FFFh). This is the destination address. GIE Global Interrupt Enable bit. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No change to register (such as TBLPTR with table reads and writes) *+ Post-Increment register (such as TBLPTR with table reads and writes) *- Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) +* n The relative address (2's complement number) for relative branch instructions or the direct address for CALL/BRANCH and RETURN instructions. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. PD Power-down bit. PRODH Product of Multiply High Byte. PRODL Product of Multiply Low Byte. s Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TO Time-out bit. TOS Top-of-Stack. u Unused or unchanged. WDT Watchdog Timer. WREG Working register (accumulator). x Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. zs 7-bit offset value for indirect addressing of register files (source). 7-bit offset value for indirect addressing of register files (destination). zd { } Optional argument. [text] Indicates an indexed address. (text) The contents of text. [expr]<n> Specifies bit n of the register indicated by the pointer expr. Assigned to. < > Register bit field. In the set of. italics User defined term (font is Courier). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 481 PIC18(L)F27/47K40 FIGURE 35-1: General Format for Instructions Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 OPCODE b (BIT #) a 0 f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 OPCODE 0 k (literal) MOVLW 7Fh k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 OPCODE 15 0 n<7:0> (literal) 12 11 GOTO Label 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 OPCODE 15 S 0 n<7:0> (literal) 12 11 CALL MYFUNC 0 n<19:8> (literal) 1111 S = Fast bit 15 OPCODE 15 OPCODE 2016 Microchip Technology Inc. 11 10 0 n<10:0> (literal) 8 7 BRA MYFUNC 0 n<7:0> (literal) Preliminary BC MYFUNC DS40001844B-page 482 PIC18(L)F27/47K40 TABLE 35-2: Mnemonic, Operands INSTRUCTION SET Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS Add WREG and f Add WREG and CARRY bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a SUBWF SUBWFB f, d, a f, d, a SWAPF TSTFSZ XORWF f, d, a f, a f, d, a Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 2: 3: 4: 2016 Microchip Technology Inc. 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 1 1 0101 0101 11da 10da ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N 1, 2 1 0011 1 (2 or 3) 0110 1 0001 10da 011a 10da ffff ffff ffff ffff ffff ffff None None Z, N 4 1, 2 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 Preliminary None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1, 2 DS40001844B-page 483 PIC18(L)F27/47K40 TABLE 35-2: INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 2 2 1 0000 0000 0000 1100 0000 0000 kkkk 0001 0000 kkkk 001s 0011 1, 2 1, 2 3, 4 3, 4 1, 2 CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n k, s CLRWDT DAW GOTO -- -- k NOP NOP POP PUSH RCALL RESET RETFIE -- -- -- -- n s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable RETLW RETURN SLEEP k s -- Return with literal in WREG Return from Subroutine Go into Standby mode Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 2: 3: 4: 2016 Microchip Technology Inc. 1 1 2 Preliminary TO, PD C None None None None None None All GIE/GIEH, PEIE/GIEL None None TO, PD 4 DS40001844B-page 484 PIC18(L)F27/47K40 TABLE 35-2: INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None None None None None C, DC, Z, OV, N Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: 2: 3: 4: Table Read Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 2 2 When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 485 PIC18(L)F27/47K40 35.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal `k' and the result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read literal `k' Process Data Write to W ADDLW Encoding: 0010 = 25h ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Before Instruction W 01da Description: 15h W = 10h After Instruction f {,d {,a}} Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register `f' Process Data Write to destination Example: ADDWF REG, 0, 0 Before Instruction W = REG = After Instruction W REG Note: = = 17h 0C2h 0D9h 0C2h All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 486 PIC18(L)F27/47K40 ADDWFC ADD W and CARRY bit to f ANDLW Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: Description: 0010 1 Cycles: 1 Q Cycle Activity: Q1 Example: Encoding: ffff ffff Add W, the CARRY flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: Decode 00da 0000 Q2 Q3 Q4 Process Data Write to destination ADDWFC k 1011 kkkk kkkk Description: The contents of W are AND'ed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: ANDLW 05Fh Before Instruction W = After Instruction W Read register `f' Before Instruction CARRY bit = REG = W = After Instruction CARRY bit = REG = W = AND literal with W = A3h 03h REG, 0, 1 1 02h 4Dh 0 02h 50h 2016 Microchip Technology Inc. Preliminary DS40001844B-page 487 PIC18(L)F27/47K40 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] Operands: -128 n 127 Operation: if CARRY bit is `1' (PC) + 2 + 2n PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are AND'ed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: ANDWF REG, 0, 0 Before Instruction W = REG = After Instruction W REG = = 1110 0010 nnnn nnnn Description: If the CARRY bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode Example: Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation HERE Before Instruction PC After Instruction If CARRY PC If CARRY PC 17h C2h 02h C2h 2016 Microchip Technology Inc. n Preliminary BC No operation 5 = address (HERE) = = = = 1; address (HERE + 12) 0; address (HERE + 2) DS40001844B-page 488 PIC18(L)F27/47K40 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] Operands: -128 n 127 Operation: if NEGATIVE bit is `1' (PC) + 2 + 2n PC Status Affected: None f, b {,a} Operation: 0 f<b> Status Affected: None Encoding: Description: Encoding: 1001 bbba ffff ffff Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Read register `f' BCF Before Instruction FLAG_REG = After Instruction FLAG_REG = Q3 Process Data FLAG_REG, Q4 Write register `f' 7, 0 n 1110 0110 nnnn nnnn Description: If the NEGATIVE bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation No operation C7h 47h 2016 Microchip Technology Inc. Example: HERE Before Instruction PC After Instruction If NEGATIVE PC If NEGATIVE PC Preliminary BN Jump = address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) DS40001844B-page 489 PIC18(L)F27/47K40 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if CARRY bit is `0' (PC) + 2 + 2n PC Operation: if NEGATIVE bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 0011 nnnn nnnn Encoding: n 1110 0111 nnnn nnnn Description: If the CARRY bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Description: If the NEGATIVE bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode Example: Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation HERE Before Instruction PC After Instruction If CARRY PC If CARRY PC BNC No operation Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) 2016 Microchip Technology Inc. Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode Example: Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation HERE Before Instruction PC After Instruction If NEGATIVE PC If NEGATIVE PC Preliminary BNN No operation Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) DS40001844B-page 490 PIC18(L)F27/47K40 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if OVERFLOW bit is `0' (PC) + 2 + 2n PC Operation: if ZERO bit is `0' (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 0101 nnnn nnnn Encoding: n 1110 0001 nnnn nnnn Description: If the OVERFLOW bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Description: If the ZERO bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode Example: Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation HERE Before Instruction PC = After Instruction If OVERFLOW = PC = If OVERFLOW = PC = No operation BNOV Jump Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode Example: Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation HERE Before Instruction PC After Instruction If ZERO PC If ZERO PC address (HERE) 0; address (Jump) 1; address (HERE + 2) 2016 Microchip Technology Inc. Q2 Read literal `n' No operation Preliminary BNZ No operation Jump = address (HERE) = = = = 0; address (Jump) 1; address (HERE + 2) DS40001844B-page 491 PIC18(L)F27/47K40 BRA Unconditional Branch BSF Bit Set f Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f<b> Status Affected: None Encoding: Description: n 1101 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a 2-cycle instruction. Words: 1 Cycles: 2 Encoding: No operation Example: Q2 Read literal `n' No operation Q3 Process Data No operation bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q4 Write to PC No operation 1000 Description: Q Cycle Activity: Q1 Decode f, b {,a} Q Cycle Activity: HERE Before Instruction PC After Instruction PC BRA Jump = address (HERE) = address (Jump) Q1 Decode Example: Q2 Read register `f' BSF Before Instruction FLAG_REG After Instruction FLAG_REG 2016 Microchip Technology Inc. Preliminary Q3 Process Data Q4 Write register `f' FLAG_REG, 7, 1 = 0Ah = 8Ah DS40001844B-page 492 PIC18(L)F27/47K40 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Description: If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: Q Cycle Activity: Q1 Decode Q Cycle Activity: Q3 Process Data Q4 No operation Q2 Read register `f' Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Q4 No operation If skip: Example: 3 cycles if skip and followed by a 2-word instruction. Q1 Decode Q2 Read register `f' Q3 Process Data Q4 No operation Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Q4 No operation If skip: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC BTFSC : : FLAG, 1, 0 = address (HERE) = = = = 0; address (TRUE) 1; address (FALSE) 2016 Microchip Technology Inc. Q4 No operation No operation Example: HERE FALSE TRUE Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC Preliminary BTFSS : : Q4 No operation No operation FLAG, 1, 0 = address (HERE) = = = = 0; address (FALSE) 1; address (TRUE) DS40001844B-page 493 PIC18(L)F27/47K40 BTG Bit Toggle f BOV Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if OVERFLOW bit is `1' (PC) + 2 + 2n PC Status Affected: None Operation: (f<b>) f<b> Status Affected: None Encoding: Description: 0111 Encoding: bbba ffff ffff Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Read register `f' BTG Branch if Overflow Q3 Process Data PORTC, 1110 0100 nnnn nnnn Description: If the OVERFLOW bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode 4, 0 Before Instruction: 0111 0101 [75h] PORTC = After Instruction: PORTC = 0110 0101 [65h] 2016 Microchip Technology Inc. Q4 Write register `f' n Example: Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation HERE Before Instruction PC = After Instruction If OVERFLOW = PC = If OVERFLOW = PC = Preliminary BOV No operation Jump address (HERE) 1; address (Jump) 0; address (HERE + 2) DS40001844B-page 494 PIC18(L)F27/47K40 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} Operands: -128 n 127 Operands: Operation: if ZERO bit is `1' (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS Status Affected: None Status Affected: None Encoding: Description: n 1110 1 Cycles: 1(2) No operation If No Jump: Q1 Decode Example: nnnn nnnn If the ZERO bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a 2-cycle instruction. Words: Q Cycle Activity: If Jump: Q1 Decode 0000 Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC Q2 Read literal `n' Q3 Process Data Q4 No operation HERE Before Instruction PC After Instruction If ZERO PC If ZERO PC BZ No operation 1110 1111 110s k19kkk k7kkk kkkk address (HERE) = = = = 1; address (Jump) 0; address (HERE + 2) kkkk0 kkkk8 Description: Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs (default). Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a 2-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Decode Q2 Q3 Read literal PUSH PC to `k'<7:0>, stack Jump = 2016 Microchip Technology Inc. Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) No operation Example: No operation HERE Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS = Preliminary No operation CALL Q4 Read literal `k'<19:8>, Write to PC No operation THERE, 1 address (HERE) address (THERE) address (HERE + 4) W BSR Status DS40001844B-page 495 PIC18(L)F27/47K40 CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: Description: f {,a} 0110 101a ffff ffff Clears the contents of the specified register. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 CLRWDT Clear Watchdog Timer Syntax: CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: Example: CLRF Before Instruction FLAG_REG After Instruction FLAG_REG Q3 Process Data 5Ah = 00h 2016 Microchip Technology Inc. 0100 Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q4 Write register `f' FLAG_REG, 1 = 0000 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set. Example: Q2 Read register `f' 0000 Description: Q Cycle Activity: Q1 Decode 0000 Preliminary Q2 No operation Q3 Process Data Q4 No operation CLRWDT Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD = ? = = = = 00h 0 1 1 DS40001844B-page 496 PIC18(L)F27/47K40 COMF Complement f CPFSEQ Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) - (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Operands: f {,d {,a}} 0 f 255 d [0,1] a [0,1] Operation: (f) dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Read register `f' COMF Before Instruction REG = After Instruction REG = W = Q3 Process Data REG, 0, 0 Q4 Write to destination Compare f with W, skip if f = W Encoding: 0110 f {,a} 001a ffff ffff Description: Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode 13h Q2 Read register `f' Q3 Process Data Q4 No operation If skip: 13h ECh Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: 2016 Microchip Technology Inc. Preliminary HERE NEQUAL EQUAL Q4 No operation Q4 No operation No operation CPFSEQ REG, 0 : : Before Instruction PC Address W REG After Instruction = = = HERE ? ? If REG PC If REG PC = = = W; Address (EQUAL) W; Address (NEQUAL) DS40001844B-page 497 PIC18(L)F27/47K40 CPFSGT Compare f with W, skip if f > W CPFSLT Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) -W), skip if (f) > (W) (unsigned comparison) Operation: (f) -W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: f {,a} 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 No operation Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Q4 No operation If skip: Example: HERE NGREATER GREATER Q4 No operation No operation = = Address (HERE) ? If REG PC If REG PC = = W; Address (GREATER) W; Address (NGREATER) 2016 Microchip Technology Inc. Encoding: f {,a} 0110 000a ffff ffff Description: Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q2 Read register `f' Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Q4 No operation If skip: Example: CPFSGT REG, 0 : : Before Instruction PC W After Instruction Compare f with W, skip if f < W Preliminary HERE NLESS LESS Q4 No operation No operation CPFSLT REG, 1 : : Before Instruction PC W After Instruction = = Address (HERE) ? If REG PC If REG PC < = = W; Address (LESS) W; Address (NLESS) DS40001844B-page 498 PIC18(L)F27/47K40 DAW Decimal Adjust W Register DECF Decrement f Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then Encoding: (W<7:4>) + 6 + DC W<7:4>; Description: Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 else (W<7:4>) + DC W<7:4> Status Affected: C Encoding: 0000 0000 0000 0111 Description: DAW adjusts the 8-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Read register W Example1: Q3 Process Data Q4 Write W Q1 Decode Before Instruction W = C = DC = Example 2: Before Instruction W = C = DC = After Instruction W C DC = = = A5h 0 0 01da ffff ffff Q Cycle Activity: DAW W = C = DC = After Instruction 0000 Example: Q2 Read register `f' DECF Before Instruction CNT = Z = After Instruction CNT = Z = 05h 1 0 Q3 Process Data CNT, Q4 Write to destination 1, 0 01h 0 00h 1 CEh 0 0 34h 1 0 2016 Microchip Technology Inc. Preliminary DS40001844B-page 499 PIC18(L)F27/47K40 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - 1 dest, skip if result = 0 Operation: (f) - 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Description: The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Encoding: 0100 Q2 Read register `f' Q3 Process Data Example: HERE DECFSZ GOTO 1 Cycles: 1(2) Note: Q Cycle Activity: Q4 No operation If skip: CNT, 1, 1 LOOP Q1 Decode Example: Q2 Read register `f' HERE ZERO NZERO Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) 2016 Microchip Technology Inc. 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = ffff Words: Q4 Write to destination Q4 No operation No operation ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation 11da Description: Q Cycle Activity: Q1 Decode f {,d {,a}} Preliminary DCFSNZ : : Q4 Write to destination Q4 No operation Q4 No operation No operation TEMP, 1, 0 = ? = = = = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) DS40001844B-page 500 PIC18(L)F27/47K40 GOTO Unconditional Branch INCF Increment f Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Encoding: 2 Cycles: 2 Q2 Read literal `k'<7:0>, Q3 No operation No operation No operation No operation Q4 Read literal `k'<19:8>, Write to PC No operation 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 0010 Description: anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a 2-cycle instruction. Words: f {,d {,a}} Q Cycle Activity: Example: Q1 Decode GOTO THERE After Instruction PC = Address (THERE) Example: Q2 Read register `f' INCF Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC = 2016 Microchip Technology Inc. Preliminary Q3 Process Data Q4 Write to destination CNT, 1, 0 FFh 0 ? ? 00h 1 1 1 DS40001844B-page 501 PIC18(L)F27/47K40 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 11da ffff ffff Encoding: 0100 The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: Q1 Decode ffff 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q2 Read register `f' Q3 Process Data Q4 Write to destination If skip: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write to destination If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Description: Q Cycle Activity: 10da Description: HERE NZERO ZERO Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = INCFSZ : : Q4 No operation Q4 No operation No operation CNT, 1, 0 Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: Before Instruction PC = After Instruction REG = If REG PC = If REG = PC = Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO) 2016 Microchip Technology Inc. HERE ZERO NZERO Preliminary INFSNZ Q4 No operation Q4 No operation No operation REG, 1, 0 Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) DS40001844B-page 502 PIC18(L)F27/47K40 IORLW Inclusive OR literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the 8bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: Q2 Read literal `k' Example: IORLW Q3 Process Data W = ffff ffff Words: 1 Cycles: 1 Q4 Write to W 35h 9Ah BFh 00da Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Before Instruction W = After Instruction 0001 f {,d {,a}} Description: Q Cycle Activity: Q1 Decode Inclusive OR W with f Q Cycle Activity: Q1 Decode Example: Q2 Read register `f' IORWF Before Instruction RESULT = W = After Instruction RESULT = W = 2016 Microchip Technology Inc. Preliminary Q3 Process Data Q4 Write to destination RESULT, 0, 1 13h 91h 13h 93h DS40001844B-page 503 PIC18(L)F27/47K40 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal `k' is loaded into the File Select Register pointed to by `f'. Words: 2 Cycles: 2 Move f Operation: f dest Status Affected: N, Z Encoding: Q2 Read literal `k' MSB Q3 Process Data Decode Read literal `k' LSB Process Data Example: After Instruction FSR2H FSR2L 03h ABh 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q4 Write literal `k' MSB to FSRfH Write literal `k' to FSRfL LFSR 2, 3ABh = = 0101 Description: Q Cycle Activity: Q1 Decode f {,d {,a}} Q Cycle Activity: Q1 Decode Example: Q2 Read register `f' MOVF Before Instruction REG W After Instruction REG W 2016 Microchip Technology Inc. Preliminary Q3 Process Data Q4 Write W REG, 0, 0 = = 22h FFh = = 22h 22h DS40001844B-page 504 PIC18(L)F27/47K40 MOVFF Move f to f MOVLB Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) Description: 1100 1111 ffff ffff ffff ffff ffffs ffffd The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Words: 2 Cycles: 2 (3) Move literal to low nibble in BSR 0000 0001 kkkk kkkk Description: The 8-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0', regardless of the value of k7:k4. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Read literal `k' Q3 Process Data MOVLB 5 Before Instruction BSR Register = After Instruction BSR Register = Q4 Write literal `k' to BSR 02h 05h Q Cycle Activity: Q1 Decode Decode Example: Q2 Read register `f' (src) No operation No dummy read MOVFF Before Instruction REG1 REG2 After Instruction REG1 REG2 Q3 Process Data Q4 No operation No operation Write register `f' (dest) REG1, REG2 = = 33h 11h = = 33h 33h 2016 Microchip Technology Inc. Preliminary DS40001844B-page 505 PIC18(L)F27/47K40 MOVLW Move literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The 8-bit literal `k' is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q2 Read literal `k' Example: MOVLW Q3 Process Data = ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q4 Write to W 5Ah After Instruction W 111a Description: Q Cycle Activity: Q1 Decode f {,a} 5Ah Q Cycle Activity: Q1 Decode Q2 Read register `f' Example: MOVWF Q3 Process Data Q4 Write register `f' REG, 0 Before Instruction W = REG = After Instruction W REG 2016 Microchip Technology Inc. Preliminary = = 4Fh FFh 4Fh 4Fh DS40001844B-page 506 PIC18(L)F27/47K40 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words: 1 Cycles: 1 Encoding: 0000 Q2 Read literal `k' Example: MULLW Q3 Process Data W PRODH PRODL After Instruction W PRODH PRODL = = = E2h ? ? = = = E2h ADh 08h ffff ffff An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q4 Write registers PRODH: PRODL 0C4h Before Instruction 001a Description: Q Cycle Activity: Q1 Decode f {,a} Q Cycle Activity: Q1 Decode Q2 Read register `f' Example: MULWF Q3 Process Data Q4 Write registers PRODH: PRODL REG, 1 Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL 2016 Microchip Technology Inc. Preliminary = = = = C4h B5h ? ? = = = = C4h B5h 8Ah 94h DS40001844B-page 507 PIC18(L)F27/47K40 NEGF Negate f NOP Syntax: NEGF Syntax: NOP Operands: 0 f 255 a [0,1] Operands: None Operation: No operation Operation: (f)+1f Status Affected: None Status Affected: N, OV, C, DC, Z Encoding: Description: f {,a} 0110 110a Encoding: ffff 1 Cycles: 1 0000 1111 ffff Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: No Operation 0000 xxxx Description: No operation. Words: 1 Cycles: 1 0000 xxxx 0000 xxxx Q Cycle Activity: Q1 Decode Q2 No operation Q3 No operation Q4 No operation Example: None. Q Cycle Activity: Q1 Decode Example: Q2 Read register `f' NEGF Before Instruction REG = After Instruction REG = Q3 Process Data Q4 Write register `f' REG, 1 0011 1010 [3Ah] 1100 0110 [C6h] 2016 Microchip Technology Inc. Preliminary DS40001844B-page 508 PIC18(L)F27/47K40 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Encoding: Example: 0000 0101 Words: 1 Cycles: 1 Q Cycle Activity: Q2 No operation Q3 POP TOS value POP GOTO NEW Q1 Decode Q4 No operation Example: Before Instruction TOS Stack (1 level down) = = 0031A2h 014332h After Instruction TOS PC = = 014332h NEW 2016 Microchip Technology Inc. 0000 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. Q Cycle Activity: Q1 Decode 0000 Description: Preliminary Q2 PUSH PC + 2 onto return stack Q3 No operation Q4 No operation PUSH Before Instruction TOS PC = = 345Ah 0124h After Instruction PC TOS Stack (1 level down) = = = 0126h 0126h 345Ah DS40001844B-page 509 PIC18(L)F27/47K40 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: n 1101 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a 2-cycle instruction. Words: 1 Cycles: 2 Encoding: No operation Example: HERE Q3 Process Data Q4 Write to PC No operation No operation 1111 1111 This instruction provides a way to execute a MCLR Reset by software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Read literal `n' PUSH PC to stack No operation 0000 Description: Q Cycle Activity: Q1 Decode 0000 After Instruction Registers = Flags* = Q2 Start Reset Q3 No operation Q4 No operation RESET Reset Value Reset Value RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 510 PIC18(L)F27/47K40 RETFIE Return from Interrupt RETLW Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged. Operation: k W, (TOS) PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: Encoding: 0000 0000 0001 1 Cycles: 2 Q Cycle Activity: 1100 kkkk kkkk W is loaded with the 8-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). Words: Q Cycle Activity: Q1 Decode Q2 Read literal `k' Q3 Process Data No operation No operation No operation Q4 POP PC from stack, Write to W No operation Example: Q1 Decode Q2 No operation Q3 No operation No operation No operation No operation Example: 0000 Description: GIE/GIEH, PEIE/GIEL. Encoding: Description: Return literal to W RETFIE Q4 POP PC from stack Set GIEH or GIEL No operation 1 After Interrupt PC W BSR Status GIE/GIEH, PEIE/GIEL 2016 Microchip Technology Inc. = = = = = TOS WS BSRS STATUSS 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W = Preliminary W contains table offset value W now has table value W = offset Begin table End of table 07h value of kn DS40001844B-page 511 PIC18(L)F27/47K40 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If `s' = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Description: Q Cycle Activity: Q1 Decode No operation Q2 No operation No operation Q3 Process Data No operation Q4 POP PC from stack No operation f {,d {,a}} 0011 01da ffff ffff The contents of register `f' are rotated one bit to the left through the CARRY flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f C Words: 1 Cycles: 1 Q Cycle Activity: Example: RETURN Q1 Decode After Instruction: PC = TOS Q2 Read register `f' Example: Before Instruction REG = C = After Instruction REG = = W C = 2016 Microchip Technology Inc. Preliminary RLCF Q3 Process Data Q4 Write to destination REG, 0, 0 1110 0110 0 1110 0110 1100 1100 1 DS40001844B-page 512 PIC18(L)F27/47K40 RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f<n>) dest<n + 1>, (f<7>) dest<0> Operation: Status Affected: N, Z (f<n>) dest<n - 1>, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: Description: f {,d {,a}} 0100 01da ffff ffff The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Encoding: Description: register f Words: 1 Cycles: 1 Q2 Read register `f' Example: Before Instruction REG = After Instruction REG = 0011 00da RLNCF Q3 Process Data Q4 Write to destination Words: 1 Cycles: 1 Q1 Decode Example: register f Q2 Read register `f' Q3 Process Data RRCF REG, 0, 0 Before Instruction REG = C = After Instruction REG = = W C = 0101 0111 2016 Microchip Technology Inc. ffff Q Cycle Activity: REG, 1, 0 1010 1011 ffff The contents of register `f' are rotated one bit to the right through the CARRY flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. C Q Cycle Activity: Q1 Decode f {,d {,a}} Preliminary Q4 Write to destination 1110 0110 0 1110 0110 0111 0011 0 DS40001844B-page 513 PIC18(L)F27/47K40 RRNCF Rotate Right f (No Carry) SETF Set f Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f<n>) dest<n - 1>, (f<0>) dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f' (default). If `a' is `0', the Access Bank will be selected (default), overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. 1 Cycles: 1 Example 1: RRNCF Before Instruction REG = After Instruction REG = Example 2: Q3 Process Data ffff ffff Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Read register `f' 100a The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Q Cycle Activity: Q1 Decode 0110 Description: register f Words: f {,a} Q4 Write to destination Q2 Read register `f' SETF Before Instruction REG After Instruction REG Q3 Process Data Q4 Write register `f' REG, 1 = 5Ah = FFh REG, 1, 0 1101 0111 1110 1011 RRNCF REG, 0, 0 Before Instruction W = REG = After Instruction ? 1101 0111 = = 1110 1011 1101 0111 W REG 2016 Microchip Technology Inc. Preliminary DS40001844B-page 514 PIC18(L)F27/47K40 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) - (f) - (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Example: Q2 No operation Q3 Process Data SLEEP Before Instruction ? TO = PD = ? After Instruction 1 TO = 0 PD = If WDT causes wake-up, this bit is cleared. 2016 Microchip Technology Inc. 0101 f {,d {,a}} 01da ffff ffff Description: Subtract register `f' and CARRY flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Subtract f from W with borrow Q4 Go to Sleep Q Cycle Activity: Q1 Decode Q2 Read register `f' Q3 Process Data Q4 Write to destination SUBFWB REG, 1, 0 Example 1: Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0 Preliminary DS40001844B-page 515 PIC18(L)F27/47K40 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k - (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Encoding: Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = SUBLW 02h 1 Cycles: 1 Q Cycle Activity: 02h ? 00h 1 ; result is zero 1 0 SUBLW ffff Words: 01h ? SUBLW ffff Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 02h 01h 1 ; result is positive 0 0 11da Description: Q Cycle Activity: Q1 0101 f {,d {,a}} 02h 03h ? FFh ; (2's complement) 0 ; result is negative 0 1 2016 Microchip Technology Inc. Q1 Decode Q2 Read register `f' SUBWF Example 1: Before Instruction REG = 3 W = 2 C = ? After Instruction REG = 1 W = 2 C = 1 Z = 0 N = 0 Example 2: SUBWF Before Instruction REG = 2 W = 2 C = ? After Instruction REG = 2 W = 0 C = 1 Z = 1 N = 0 Example 3: SUBWF Before Instruction REG = 1 W = 2 C = ? After Instruction REG = FFh W = 2 C = 0 Z = 0 N = 1 Preliminary Q3 Process Data Q4 Write to destination REG, 1, 0 ; result is positive REG, 0, 0 ; result is zero REG, 1, 0 ;(2's complement) ; result is negative DS40001844B-page 516 PIC18(L)F27/47K40 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) - (W) - (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: Description: 0101 10da ffff ffff Subtract W and the CARRY flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode f {,d {,a}} Q2 Read register `f' Q3 Process Data Q4 Write to destination SUBWFB REG, 1, 0 Example 1: Before Instruction (0001 1001) REG = 19h = 0Dh (0000 1101) W C = 1 After Instruction REG = 0Ch (0000 1100) = 0Dh (0000 1101) W C = 1 Z = 0 N = 0 ; result is positive SUBWFB REG, 0, 0 Example 2: Before Instruction REG = 1Bh (0001 1011) = 1Ah (0001 1010) W C = 0 After Instruction (0001 1011) REG = 1Bh W = 00h C = 1 Z = 1 ; result is zero N = 0 Example 3: SUBWFB REG, 1, 0 Before Instruction REG = 03h (0000 0011) W = 0Eh (0000 1110) C = 1 After Instruction REG = F5h (1111 0101) ; [2's comp] W = 0Eh (0000 1110) C = 0 Z = 0 N = 1 ; result is negative 2016 Microchip Technology Inc. Encoding: 0011 10da ffff ffff Description: The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: SWAPF Before Instruction REG = After Instruction REG = Preliminary REG, 1, 0 53h 35h DS40001844B-page 517 PIC18(L)F27/47K40 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; Example2: 0000 0000 0000 TBLRD = = = 55h 00A356h 34h = = 34h 00A357h +* ; Before Instruction TABLAT TBLPTR MEMORY (01A357h) MEMORY (01A358h) After Instruction TABLAT TBLPTR Status Affected: None Encoding: *+ ; Before Instruction TABLAT TBLPTR MEMORY (00A356h) After Instruction TABLAT TBLPTR = = = = AAh 01A357h 12h 34h = = 34h 01A358h 10nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode No operation Q2 No operation No operation (Read Program Memory) 2016 Microchip Technology Inc. Q3 Q4 No No operation operation No No operation operation (Write TABLAT) Preliminary DS40001844B-page 518 PIC18(L)F27/47K40 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) - 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register; Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2: None Encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* Description: This instruction uses the three LSBs of TBLPTR to determine which of the eight holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 11.1 "Program Flash Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: 1 Cycles: 2 TBLWT +*; Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No No No operation operation operation No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register ) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 519 PIC18(L)F27/47K40 TSTFSZ Test f, skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR literal with W 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a 2-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal `k' Process Data Write to W Example: XORLW 0AFh Before Instruction W = After Instruction W = B5h 1Ah Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data No operation Q1 Q2 Q3 Q4 If skip: No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation Example: No operation No operation HERE NZERO ZERO Before Instruction PC After Instruction If CNT PC If CNT PC No operation No operation TSTFSZ : : Q4 No operation No operation CNT, 1 = Address (HERE) = = = 00h, Address (ZERO) 00h, Address (NZERO) 2016 Microchip Technology Inc. No operation Preliminary DS40001844B-page 520 PIC18(L)F27/47K40 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f' (default). If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 35.2.3 "Byte-Oriented and BitOriented Instructions in Indexed Literal Offset Mode" for details. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register `f' Process Data Write to destination Example: XORWF Before Instruction REG = W = After Instruction REG = W = REG, 1, 0 AFh B5h 1Ah B5h 2016 Microchip Technology Inc. Preliminary DS40001844B-page 521 PIC18(L)F27/47K40 35.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 35-3. Detailed descriptions are provided in Section 35.2.2 "Extended Instruction Set". The opcode field descriptions in Table 35-1 apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18(L)F2x/4xK40 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. Note: The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. 35.2.1 EXTENDED INSTRUCTION SYNTAX Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 35.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". * dynamic allocation and deallocation of software stack space when entering and leaving subroutines * function pointer invocation * software Stack Pointer manipulation * manipulation of variables located in a software stack TABLE 35-3: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }"). EXTENSIONS TO THE PIC18 INSTRUCTION SET Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF f, k k MOVSS zs, zd PUSHL k SUBFSR SUBULNK f, k k zs, fd Description Cycles Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Move zs (source) to 1st word 2nd word fd (destination) Move zs (source) to 1st word zd (destination) 2nd word Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return 2016 Microchip Technology Inc. 1 2 2 2 16-Bit Instruction Word MSb LSb Status Affected 1000 1000 0000 1011 ffff 1011 xxxx 1010 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk None None None None 1 1110 1110 0000 1110 1111 1110 1111 1110 1 2 1110 1110 1001 1001 ffkk 11kk kkkk kkkk None None 2 Preliminary None None DS40001844B-page 522 PIC18(L)F27/47K40 35.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return Syntax: Operands: ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k FSR(f) None 1110 1000 ffkk Syntax: Operands: Operation: ADDULNK k 0 k 63 FSR2 + k FSR2, (TOS) PC None 1110 1000 11kk Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Example: kkkk The 6-bit literal `k' is added to the contents of the FSR specified by `f'. 1 1 Q2 Read literal `k' Q3 Process Data ADDFSR 2, 23h Before Instruction FSR2 = After Instruction FSR2 = Status Affected: Encoding: Description: Q4 Write to FSR Words: Cycles: 03FFh 0422h Q Cycle Activity: Q1 Decode No Operation Example: Q2 Read literal `k' No Operation Q3 Process Data No Operation Q4 Write to FSR No Operation ADDULNK 23h Before Instruction FSR2 = PC = After Instruction FSR2 = PC = Note: kkkk The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2 03FFh 0100h 0422h (TOS) All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s). 2016 Microchip Technology Inc. Preliminary DS40001844B-page 523 PIC18(L)F27/47K40 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, Status or BSR. Words: 1 Cycles: 2 Encoding: 1st word (source) 2nd word (destin.) No operation Example: Q2 Read WREG No operation HERE Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W = Q3 PUSH PC to stack No operation Q4 No operation No operation 0zzz ffff zzzzs ffffd Words: 2 Cycles: 2 Q Cycle Activity: Q1 Decode Decode address (HERE) 10h 00h 06h 2016 Microchip Technology Inc. 1011 ffff The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs' in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. CALLW 001006h address (HERE + 2) 10h 00h 06h 1110 1111 Description: Q Cycle Activity: Q1 Decode Move Indexed to f Example: Q2 Q3 Determine Determine source addr source addr No No operation operation No dummy read MOVSF Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2 Preliminary Q4 Read source reg Write register `f' (dest) [05h], REG2 = 80h = = 33h 11h = 80h = = 33h 33h DS40001844B-page 524 PIC18(L)F27/47K40 MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2 Syntax: MOVSS [zs], [zd] Syntax: PUSHL k Operands: 0 zs 127 0 zd 127 Operands: 0k 255 Operation: ((FSR2) + zs) ((FSR2) + zd) Operation: k (FSR2), FSR2 - 1 FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) Description 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. Words: 2 Cycles: 2 Encoding: Decode Example: Q2 Q3 Determine Determine source addr source addr Determine Determine dest addr dest addr 1010 kkkk kkkk Description: The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q Cycle Activity: Q1 Decode 1111 Q2 Read `k' Q3 Process data Q4 Write to destination PUSHL 08h Before Instruction FSR2H:FSR2L Memory (01ECh) = = 01ECh 00h After Instruction FSR2H:FSR2L Memory (01ECh) = = 01EBh 08h Q4 Read source reg Write to dest reg MOVSS [05h], [06h] Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h = 80h = 33h = 11h = 80h = 33h = 33h 2016 Microchip Technology Inc. Preliminary DS40001844B-page 525 PIC18(L)F27/47K40 SUBFSR Subtract Literal from FSR SUBULNK Syntax: Operands: SUBFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) - k FSRf None 1110 1001 ffkk Syntax: Operands: Operation: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode kkkk The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. 1 1 Q2 Read register `f' Q3 Process Data SUBFSR 2, 23h Example: Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh Q4 Write to destination Subtract Literal from FSR2 and Return SUBULNK k 0 k 63 FSR2 - k FSR2 (TOS) PC Status Affected: None 1110 1001 Encoding: 11kk kkkk Description: The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode No Operation Q2 Read register `f' No Operation Q3 Process Data No Operation Q4 Write to destination No Operation SUBULNK 23h Example: Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 526 PIC18(L)F27/47K40 35.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 10.7.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (`a' = 0), or in a GPR bank designated by the BSR (`a' = 1). When the extended instruction set is enabled and `a' = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byte-oriented and bitoriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 35.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types. 2016 Microchip Technology Inc. 35.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands When the extended instruction set is enabled, the file register argument, `f', in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled) when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM assembler. The destination argument, `d', functions as before. In the latest versions of the MPASMTM assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing. 35.2.4 CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18(L)F2x/ 4xK40, it is very important to consider the type of code. A large, re-entrant application that is written in `C' and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set. Preliminary DS40001844B-page 527 PIC18(L)F27/47K40 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k)<b> Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f' (default). Encoding: 1000 bbb0 kkkk kkkk Description: Bit `b' of the register indicated by FSR2, offset by the value `k', is set. Words: 1 Cycles: 1 Q Cycle Activity: Words: 1 Q1 Q2 Q3 Q4 Cycles: 1 Decode Read register `f' Process Data Write to destination Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read `k' Process Data Write to destination ADDWF Example: Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah [OFST] , 0 Before Instruction W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch = = = 17h 2Ch 0A00h = 20h = 37h = 20h BSF [FLAG_OFST], 7 = = 0Ah 0A00h = 55h = D5h Set Indexed (Indexed Literal Offset mode) SETF Syntax: SETF [k] Operands: 0 k 95 Operation: FFh ((FSR2) + k) Status Affected: None Encoding: 0110 1000 kkkk kkkk Description: The contents of the register indicated by FSR2, offset by `k', are set to FFh. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Read `k' SETF Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch 2016 Microchip Technology Inc. Preliminary Q3 Process Data Q4 Write register [OFST] = = 2Ch 0A00h = 00h = FFh DS40001844B-page 528 PIC18(L)F27/47K40 35.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS The latest versions of Microchip's software tools have been designed to fully support the extended instruction set of the PIC18(L)F2x/4xK40 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 529 PIC18(L)F27/47K40 36.0 DEVELOPMENT SUPPORT 36.1 The PIC(R) microcontrollers (MCU) and dsPIC(R) digital signal controllers (DSC) are supported with a full range of software and hardware development tools: * Integrated Development Environment - MPLAB(R) X IDE Software * Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families * Simulators - MPLAB X SIM Software Simulator * Emulators - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkitTM 3 * Device Programmers - MPLAB PM3 Device Programmer * Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits * Third-party development tools MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows(R), Linux and Mac OS(R) X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: * Color syntax highlighting * Smart code completion makes suggestions and provides hints as you type * Automatic code formatting based on user-defined rules * Live parsing User-Friendly, Customizable Interface: * Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. * Call graph window Project-Based Workspaces: * * * * Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: * Local file history feature * Built-in support for Bugzilla issue tracker 2016 Microchip Technology Inc. Preliminary DS40001844B-page 530 PIC18(L)F27/47K40 36.2 MPLAB XC Compilers 36.4 The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip's 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 36.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction 36.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility * Integration into MPLAB X IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multipurpose source files * Directives that allow complete control over the assembly process 2016 Microchip Technology Inc. Preliminary DS40001844B-page 531 PIC18(L)F27/47K40 36.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 36.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 2016 Microchip Technology Inc. 36.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 36.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer's PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial ProgrammingTM (ICSPTM). 36.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. Preliminary DS40001844B-page 532 PIC18(L)F27/47K40 36.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 36.12 Third-Party Development Tools A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. * Device Programmers and Gang Programmers from companies, such as SoftLog and CCS * Software Tools from companies, such as Gimpel and Trace Systems * Protocol Analyzers from companies, such as Saleae and Total Phase * Demonstration Boards from companies, such as MikroElektronika, Digilent(R) and Olimex * Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika(R) The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 533 PIC18(L)F27/47K40 37.0 ELECTRICAL SPECIFICATIONS 37.1 Absolute Maximum Ratings() Ambient temperature under bias...................................................................................................... -40C to +125C Storage temperature ........................................................................................................................ -65C to +150C Voltage on pins with respect to VSS on VDD pin PIC18F27/47K40 ...................................................................................................... -0.3V to +6.5V PIC18LF27/47K40 .................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40C TA +85C .............................................................................................................. 350 mA 85C TA +125C ............................................................................................................. 120 mA on VDD pin for 28-Pin devices(1) -40C TA +85C .............................................................................................................. 250 mA 85C TA +125C ............................................................................................................... 85 mA on VDD pin for 40-Pin devices(1) -40C TA +85C .............................................................................................................. 350 mA 85C TA +125C ............................................................................................................. 120 mA on any standard I/O pin ...................................................................................................................... 50 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Total power dissipation(2)................................................................................................................................ 800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 37-6 to calculate device specifications. Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 534 PIC18(L)F27/47K40 37.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD -- Operating Supply Voltage(1) PIC18LF27/47K40 VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V VDDMIN (Fosc 64 MHz) ......................................................................................................... +3.0V VDDMAX .................................................................................................................................... +3.6V PIC18F27/47K40 VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V VDDMIN (Fosc 32 MHz) ......................................................................................................... +2.5V VDDMIN (Fosc 64 MHz) ......................................................................................................... +3.0V VDDMAX .................................................................................................................................... +5.5V TA -- Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40C TA_MAX .................................................................................................................................... +85C Extended Temperature TA_MIN ...................................................................................................................................... -40C TA_MAX .................................................................................................................................. +125C Note 1: See Parameter Supply Voltage, DS Characteristics: Supply Voltage. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 535 PIC18(L)F27/47K40 VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC18F27/47K40 ONLY FIGURE 37-1: 5.5 VDD (V) 3.0 2.5 2.3 0 10 4 16 32 64 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 37-7 for each Oscillator mode's supported frequencies. VOLTAGE FREQUENCY GRAPH, -40C TA +125C, PIC18LF27/47K40 ONLY FIGURE 37-2: VDD (V) 3.6 3.0 2.5 1.8 0 4 10 16 32 64 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 37-7 for each Oscillator mode's supported frequencies. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 536 PIC18(L)F27/47K40 37.3 DC Characteristics TABLE 37-1: SUPPLY VOLTAGE PIC18LF27/47K40 Standard Operating Conditions (unless otherwise stated) PIC18F27/47K40 Param. No. Sym. Characteristic Min. Typ. Max. Units Conditions Supply Voltage D002 VDD 1.8 2.5 3.0 -- -- -- 3.6 3.6 3.6 V V V FOSC 16 MHz FOSC 16 MHz FOSC 32 MHz D002 VDD 2.3 2.5 3.0 -- -- -- 5.5 5.5 5.5 V V V FOSC 16 MHz FOSC 16 MHz FOSC 32 MHz RAM Data Retention(1) D003 VDR 1.5 -- -- V Device in Sleep mode D003 VDR 1.7 -- -- V Device in Sleep mode -- 1.6 -- V BOR or LPBOR disabled(3) -- 1.6 -- V BOR or LPBOR disabled(3) -- 0.8 -- V BOR or LPBOR disabled(3) -- 1.5 -- V BOR or LPBOR disabled(3) Power-on Reset Release VPOR D004 Voltage(2) VPOR D004 Power-on Reset Rearm VPORR D005 D005 Voltage(2) VPORR VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD 0.05 -- -- V/ms BOR or LPBOR disabled(3) D006 SVDD 0.05 -- -- V/ms BOR or LPBOR disabled(3) Data in "Typ." column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: See Figure 37-3, POR and POR REARM with Slow Rising VDD. 3: Please see Table 37-11 for BOR and LPBOR trip point information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 537 PIC18(L)F27/47K40 FIGURE 37-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) Note 1: 2: 3: TPOR(2) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 538 PIC18(L)F27/47K40 TABLE 37-2: SUPPLY CURRENT (IDD)(1,2,4) PIC18LF27/47K40 Standard Operating Conditions (unless otherwise stated) PIC18F27/47K40 Param. No. Symbol Device Characteristics Min. Typ. Max. Units D100 IDDXT4 XT = 4 MHz -- 450 650 D100 IDDXT4 XT = 4 MHz -- 550 750 D100A IDDXT4 XT = 4 MHz -- 310 -- D100A IDDXT4 XT = 4 MHz -- 410 -- A A A A Conditions VDD Note 3.0V 3.0V 3.0V PMD's all 1's 3.0V PMD's all 1's D101 IDDHFO16 HFINTOSC = 16 MHz -- 1.9 2.6 mA 3.0V D101 IDDHFO16 HFINTOSC = 16 MHz -- 2.0 2.7 mA 3.0V D101A IDDHFO16 HFINTOSC = 16 MHz -- 1.4 -- mA 3.0V PMD's all 1's D101A IDDHFO16 HFINTOSC = 16 MHz -- 1.5 -- mA 3.0V PMD's all 1's D102 IDDHFOPLL HFINTOSC = 64 MHz -- 7.4 9.4 mA 3.0V D102 IDDHFOPLL HFINTOSC = 64 MHz -- 7.5 9.5 mA 3.0V D102A IDDHFOPLL HFINTOSC = 64 MHz -- 5.2 -- mA 3.0V PMD's all 1's D102A IDDHFOPLL HFINTOSC = 64 MHz -- 5.3 -- mA 3.0V PMD's all 1's D103 IDDHSPLL32 HS+PLL = 64 MHz -- 6.9 8.9 mA 3.0V D103 IDDHSPLL32 HS+PLL = 64 MHz -- 7.0 9.0 mA 3.0V D103A IDDHSPLL32 HS+PLL = 64 MHz -- 4.9 -- mA 3.0V PMD's all 1's D103A IDDHSPLL32 HS+PLL = 64 MHz -- 5.0 -- mA 3.0V PMD's all 1's D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz -- 1.05 -- mA 3.0V D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz -- 1.15 -- mA 3.0V D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 -- 1.1 -- mA 3.0V D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 -- 1.2 -- mA 3.0V Data in "Typ." column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 6-2). 4: PMD bits are all in the default state, no modules are disabled. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 539 PIC18(L)F27/47K40 TABLE 37-3: POWER-DOWN CURRENT (IPD)(1,2) PIC18LF27/47K40 Standard Operating Conditions (unless otherwise stated) PIC18F27/47K40 Standard Operating Conditions (unless otherwise stated) VREGPM = 1 Param. No. Symbol Device Characteristics Conditions Min. Typ. Max. +85C Max. +125C Units 2 9 A 3.0V 3.0V VDD D200 IPD IPD Base -- 0.05 D200 D200A IPD IPD Base -- 0.4 4 12 -- 20 -- -- D201 IPD_WDT Low-Frequency Internal Oscillator/ WDT -- 0.4 3 10 A A A D201 IPD_WDT Low-Frequency Internal Oscillator/ WDT -- 0.6 5 13 A 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) -- 0.6 5 13 3.0V D202 IPD_SOSC Secondary Oscillator (SOSC) -- 0.8 8.5 15 D203 IPD_FVR FVR -- 31 -- -- D203 IPD_FVR FVR -- 32 -- -- D204 IPD_BOR Brown-out Reset (BOR) -- 9 14 18 D204 IPD_BOR Brown-out Reset (BOR) -- 14 19 21 D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) -- 0.5 -- -- D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) -- 0.7 -- -- D206 IPD_HLVD High/Low Voltage Detect (HLVD) -- 31 -- -- D206 IPD_HLVD High/Low Voltage Detect (HLVD) -- 32 -- -- D207 IPD_ADCA ADC - Active -- 250 -- -- D207 IPD_ADCA ADC - Active -- 280 -- -- D208 IPD_CMP Comparator -- 25 38 40 D208 IPD_CMP Comparator -- 28 50 60 A A A A A A A A A A A A A A Note 1: 2: 3: 4: 3.0V Note VREGPM = 0 3.0V 3.0V 3.0V FVRCON = 0X81 or 0x84 3.0V FVRCON = 0X81 or 0x84 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V ADC is converting (4) 3.0V ADC is converting (4) 3.0V 3.0V Data in "Typ." column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. ADC clock source is FRC. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 540 PIC18(L)F27/47K40 TABLE 37-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. VIL D300 D301 D302 D303 D304 D305 VIH D320 D321 D322 D323 D324 D325 IIL D340 Characteristic Input Low Voltage I/O PORT: with TTL buffer with Schmitt Trigger buffer with I2C levels with SMBus levels MCLR Input High Voltage I/O PORT: with TTL buffer with Schmitt Trigger buffer with I2C levels with SMBus levels MCLR Input Leakage Current(1) I/O Ports D341 MCLR(2) D342 IPUR D350 Min. Typ Max. Units Conditions -- -- -- -- -- -- -- -- -- -- -- -- 0.8 0.15 VDD 0.2 VDD 0.3 VDD 0.8 0.2 VDD V V V V V V 2.0 0.25 VDD + 0.8 0.8 VDD 0.7 VDD 2.1 0.7 VDD -- -- -- -- V V 4.5V VDD 5.5V 1.8V VDD 4.5V -- -- -- -- -- -- -- -- V V V V 2.0V VDD 5.5V -- 5 125 nA -- 5 1000 nA -- 50 200 nA 4.5V VDD 5.5V 1.8V VDD 4.5V 2.0V VDD 5.5V 2.7V VDD 5.5V 2.7V VDD 5.5V VSS VPIN VDD, Pin at high-impedance, 85C VSS VPIN VDD, Pin at high-impedance, 125C VSS VPIN VDD, Pin at high-impedance, 85C Weak Pull-up Current A VDD = 3.0V, VPIN = VSS 25 120 200 Output Low Voltage I/O ports -- -- 0.6 V IOL = 10.0mA, VDD = 3.0V Output High Voltage VOH -- -- V IOH = 6.0 mA, VDD = 3.0V I/O ports VDD - 0.7 All I/O pins -- 5 50 pF CIO Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. VOL D360 D370 D380 Note 2016 Microchip Technology Inc. Preliminary DS40001844B-page 541 PIC18(L)F27/47K40 TABLE 37-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units Conditions 100k -- -- E/W -40C TA +85C -- 40 -- Year Provided no other specifications are violated 1M 500k 10M -- -- -- E/W -40C TA +60C -40C TA +85C VDDMIN -- VDDMAX V -- 4.0 5.0 ms 10k -- -- E/W -40C TA +85C (Note 1) -- 40 -- Year Provided no other specifications are violated VDDMIN -- VDDMAX V VDDMIN -- VDDMAX V -- 2.0 2.5 ms Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance MEM21 TD_RET Characteristic Retention MEM22 ND_REF Total Erase/Write Cycles before Refresh MEM23 VD_RW VDD for Read or Erase/Write operation MEM24 TD_BEW Byte Erase and Write Cycle Time Program Flash Memory Specifications MEM30 EP Flash Memory Cell Endurance MEM32 TP_RET Characteristic Retention MEM33 VP_RD VDD for Read operation MEM34 VP_REW VDD for Row Erase or Write operation MEM35 TP_REW Self-Timed Row Erase or Self-Timed Write Note 1: Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 542 PIC18(L)F27/47K40 TABLE 37-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param No. TH01 TH02 TH03 TH04 TH05 TH06 TH07 Note 1: 2: 3: Sym. Characteristic JA Thermal Resistance Junction to Ambient JC Thermal Resistance Junction to Case Typ. Units 60 C/W 28-pin SPDIP package 80 C/W 28-pin SOIC package 90 C/W 28-pin SSOP package 27.5 C/W 28-pin UQFN 4x4 mm package 27.5 C/W 28-pin QFN 6x6mm package 47.2 C/W 40-pin PDIP package 46 C/W 44-pin TQFP package 24.4 C/W 44-pin QFN 8x8mm package 31.4 C/W 28-pin SPDIP package 24 C/W 28-pin SOIC package 24 C/W 28-pin SSOP package 24 C/W 28-pin UQFN 4x4mm package 24 C/W 28-pin QFN 6x6mm package 24.7 C/W 40-pin PDIP package 14.5 C/W 44-pin TQFP package C/W 20 Maximum Junction Temperature 150 C Power Dissipation -- W PINTERNAL Internal Power Dissipation -- W PI/O I/O Power Dissipation -- W Derated Power -- W PDER IDD is current to run the chip alone without driving any load on the output pins. TA = Ambient Temperature, TJ = Junction Temperature See absolute maximum ratings for total power dissipation. TJMAX PD 2016 Microchip Technology Inc. Conditions Preliminary 44-pin QFN 8x8mm package PD = PINTERNAL + PI/O(3) PINTERNAL = IDD x VDD(1) PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) PDER = PDMAX (TJ - TA)/JA(2) DS40001844B-page 543 PIC18(L)F27/47K40 37.4 AC Characteristics FIGURE 37-4: LOAD CONDITIONS Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins 2016 Microchip Technology Inc. Preliminary DS40001844B-page 544 PIC18(L)F27/47K40 FIGURE 37-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS2 OS1 OS2 OS20 CLKOUT (CLKOUT Mode) Note 1: See Table 37-7. TABLE 37-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency -- -- 500 kHz OS2 TECL_DC Clock Duty Cycle 40 -- 60 % ECM Oscillator OS3 FECM Clock Frequency -- -- 4 MHz OS4 TECM_DC Clock Duty Cycle 40 -- 60 % ECH Oscillator OS5 FECH Clock Frequency -- -- 32 MHz OS6 TECH_DC Clock Duty Cycle 40 -- 60 % Clock Frequency -- -- 100 kHz Note 4 Clock Frequency -- -- 4 MHz Note 4 Clock Frequency -- -- 20 MHz Note 4 Clock Frequency 32.4 32.768 33.1 kHz -- -- 64 MHz LP Oscillator OS7 FLP XT Oscillator OS8 FXT HS Oscillator OS9 FHS Secondary Oscillator OS10 FSEC System Oscillator OS20 FOSC * Note 1: 2: 3: 4: System Clock Frequency (Note 2, Note 3) These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. The system clock frequency (FOSC) is selected by the "main clock switch controls" as described in Section 6.0 "PowerSaving Operation Modes". The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 "Standard Operating Conditions". LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 545 PIC18(L)F27/47K40 TABLE 37-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic OS21 FCY Instruction Frequency OS22 TCY Instruction Period * Note 1: 2: 3: 4: Min. Typ Max. Units -- 62.5 FOSC/4 -- MHz 1/FCY -- ns Conditions These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. The system clock frequency (FOSC) is selected by the "main clock switch controls" as described in Section 6.0 "PowerSaving Operation Modes". The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 "Standard Operating Conditions". LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 546 PIC18(L)F27/47K40 INTERNAL OSCILLATOR PARAMETERS(1) TABLE 37-8: Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units Conditions OS50 FHFOSC Precision Calibrated HFINTOSC Frequency -- 4 8 12 16 32 64 -- MHz (Note 2) OS51 FHFOSCLP Low-Power Optimized HFINTOSC Frequency -- -- 1 2 -- -- MHz MHz OS52 FMFOSC Internal Calibrated MFINTOSC Frequency -- 500 -- kHz OS53* FLFOSC Internal LFINTOSC Frequency -- 31 -- kHz OS54* THFOSCST HFINTOSC Wake-up from Sleep Start-up Time -- -- 11 50 20 -- s s OS56 TLFOSCST -- 0.2 -- ms LFINTOSC Wake-up from Sleep Start-up Time VREGPM = 0 VREGPM = 1 * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature. FIGURE 37-6: PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 5% Temperature (C) 85 3% 60 2% 0 5% -40 1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 547 PIC18(L)F27/47K40 TABLE 37-9: PLL SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD 2.5V Param No. Sym. Characteristic PLL Input Frequency Range PLL01 FPLLIN PLL02 FPLLOUT PLL Output Frequency Range PLL03 TPLLST PLL Lock Time from Start-up PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) Min. Typ Max. Units Conditions 4 -- 16 MHz 16 -- 64 MHz Note 1 -- 200 -- s -0.25 -- 0.25 % * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 548 PIC18(L)F27/47K40 FIGURE 37-7: CLKOUT AND I/O TIMING Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 CLKOUT IO8 IO7 IO4 IO5 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO7, IO8 TABLE 37-10: I/O AND CLKOUT TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. IO1* TCLKOUTH CLKOUT rising edge delay (rising edge Fosc (Q1 cycle) to falling edge CLKOUT CLKOUT falling edge delay (rising edge Fosc (Q3 cycle) to rising edge CLKOUT Port output valid time (rising edge Fosc (Q1 cycle) to port valid) Port input setup time (Setup time before rising edge Fosc - Q2 cycle) Port input hold time (Hold time after rising edge Fosc - Q2 cycle) Port I/O rise time, slew rate enabled IO2* TCLKOUTL IO3* TIO_VALID IO4* TIO_SETUP IO5* TIO_HOLD IO6* TIOR_SLREN IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled IO8* TIOF_SLREN Port I/O fall time, slew rate enabled IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled IO10* TINT IO11* TIOC INT pin high or low time to trigger an interrupt Interrupt-on-Change minimum high or low time to trigger interrupt *These parameters are characterized but not tested. 2016 Microchip Technology Inc. Preliminary Typ Max. Units Conditions -- -- 70 ns -- -- 72 ns -- 50 70 ns 20 -- -- ns 50 -- -- ns -- 25 -- ns VDD = 3.0V -- 5 -- ns VDD = 3.0V -- 25 -- ns VDD = 3.0V VDD = 3.0V -- 5 -- ns 25 -- -- ns 25 -- -- ns DS40001844B-page 549 PIC18(L)F27/47K40 FIGURE 37-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST03 RST02 RST02 I/O pins Note 1: Asserted low. FIGURE 37-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) RST08 Reset RST04(1) (due to BOR) Note 1: Only if PWRTE bit in the Configuration Word register is programmed to `1'; 2 ms delay if PWRTE = 0. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 550 PIC18(L)F27/47K40 TABLE 37-11: RESET, WDT, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ Max. Units RST01* TMCLR MCLR Pulse Width Low to ensure Reset 2 -- -- s RST02* TIOZ I/O high-impedance from Reset detection -- -- 2 s RST03 Watchdog Timer Time-out Period -- 16 -- ms RST04* TPWRT Power-up Timer Period -- 65 -- ms RST05 TOST Oscillator Start-up Timer Period(1,2) RST06 VBOR Brown-out Reset Voltage(4) TWDT -- 1024 -- TOSC 2.7 2.55 2.3 2.3 1.8 2.85 2.7 2.45 2.45 1.9 3.0 2.85 2.6 2.6 2.05 V V V V V RST07 VBORHYS Brown-out Reset Hysteresis -- 40 -- mV RST08 TBORDC Brown-out Reset Response Time -- 3 -- s RST09 VLPBOR Low-Power Brown-out Reset Voltage 1.8 1.9 2.2 V Conditions 1:512 Prescaler BORV = 00 BORV = 01 BORV = 10 BORV = 11 (PIC18Fxxx) BORV = 11 (PIC18LFxxx) * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. TABLE 37-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. HLVD01 Symbol Characteristic Min. Typ Max. Units VDET Voltage Detection -- 1.90 -- V HLVDSEL<3:0>=0000 -- 2.10 -- V HLVDSEL<3:0>=0001 -- 2.25 -- V HLVDSEL<3:0>=0010 -- 2.50 -- V HLVDSEL<3:0>=0011 -- 2.60 -- V HLVDSEL<3:0>=0100 -- 2.75 -- V HLVDSEL<3:0>=0101 -- 2.90 -- V HLVDSEL<3:0>=0110 -- 3.15 -- V HLVDSEL<3:0>=0111 -- 3.35 -- V HLVDSEL<3:0>=1000 -- 3.60 -- V HLVDSEL<3:0>=1001 -- 3.75 -- V HLVDSEL<3:0>=1010 -- 4.00 -- V HLVDSEL<3:0>=1011 -- 4.20 -- V HLVDSEL<3:0>=1100 -- 4.35 -- V HLVDSEL<3:0>=1101 -- 4.65 -- V HLVDSEL<3:0>=1110 2016 Microchip Technology Inc. Preliminary Conditions DS40001844B-page 551 PIC18(L)F27/47K40 TABLE 37-13: ANALOG-TO-DIGITAL CONVERTER (ADC) ACCURACY SPECIFICATIONS(1,2): Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C, TAD = 1s Param No. Sym. Characteristic Min. Typ Max. Units Conditions AD01 NR Resolution -- -- 10 AD02 EIL Integral Error -- 0.1 1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V bit AD03 EDL Differential Error -- 0.1 1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V AD04 EOFF Offset Error -- 0.5 2.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V AD05 EGN Gain Error -- 0.2 1.0 LSb ADCREF+ = 3.0V, ADCREF-= 0V AD06 VADREF ADC Reference Voltage (ADREF+ - ADREF-) 1.8 -- VDD V AD07 VAIN Full-Scale Range ADREF- -- ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source -- 10 -- k AD09 RVREF ADC Voltage Reference Ladder Impedance -- 50 -- k Note 3 * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors. 2: The ADC conversion result never decreases with an increase in the input and has no missing codes. 3: This is the impedance seen by the VREF pads when the external reference pads are selected. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 552 PIC18(L)F27/47K40 TABLE 37-14: ANALOG-TO-DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param Sym. No. AD20 Characteristic ADC Clock Period TAD AD21 AD22 TCNV Conversion Time(1) Min. Typ Max. Units 1 -- 9 s Using FOSC as the ADC clock source ADOCS = 0 -- 2 -- s Using FRC as the ADC clock source ADOCS = 1 -- 11 + 3TCY -- TAD Set of GO/DONE bit to Clear of GO/ DONE bit AD23 TACQ Acquisition Time -- 2 -- s AD24 THCD Sample and Hold Capacitor Disconnect Time -- -- -- s Conditions FOSC-based clock source FRC-based clock source * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Does not apply for the ADCRC oscillator. FIGURE 37-10: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD132 2016 Microchip Technology Inc. Sampling Stopped Preliminary DS40001844B-page 553 PIC18(L)F27/47K40 FIGURE 37-11: ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 3 2 1 0 NEW_DATA ADIF 1 TCY GO DONE Sample AD132 Sampling Stopped Note 1: If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 554 PIC18(L)F27/47K40 TABLE 37-15: COMPARATOR SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param No. Sym. Characteristics CM01 VIOFF Input Offset Voltage CM02 VICM Input Common Mode Range CM03 CMRR CM04 VHYST CM05 TRESP(1) Note * 1: 2: Min. Typ. Max. Units -- -- 30 mV GND -- VDD V Common Mode Input Rejection Ratio -- 50 -- dB Comparator Hysteresis 15 25 35 mV Response Time, Rising Edge -- 300 600 ns Response Time, Falling Edge -- 220 500 ns Comments VICM = VDD/2 These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. A mode change includes changing any of the control register values, including module enable. TABLE 37-16: 5-BIT DAC SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param No. Sym. Characteristics Min. Typ. Max. Units DSB01 VLSB Step Size -- (VDACREF+ -VDACREF-) / 32 -- V DSB01 VACC Absolute Accuracy -- -- 0.5 LSb DSB03* RUNIT Unit Resistor Value -- 5000 -- DSB04* TST Settling Time(1) -- -- 10 s Note * 1: Comments These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Settling time measured while DACR<4:0> transitions from `00000' to `01111'. TABLE 37-17: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ. Max. Units Conditions FVR01 VFVR1 1x Gain (1.024V) -4 -- +4 % VDD 2.5V, -40C to 85C FVR02 VFVR2 2x Gain (2.048V) -4 -- +4 % VDD 2.5V, -40C to 85C FVR03 VFVR4 4x Gain (4.096V) -5 -- +5 % VDD 4.75V, -40C to 85C FVR04 TFVRST FVR Start-up Time -- 25 -- us TABLE 37-18: ZERO CROSS DETECT (ZCD) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25C Param. No. Sym. Characteristics Min Typ Max Units ZC01 VPINZC Voltage on Zero Cross Pin -- 0.75 -- V ZC02 IZCD_MAX Maximum source or sink current -- -- 600 A ZC03 TRESPH Response Time, Rising Edge -- 1 -- s TRESPL Response Time, Falling Edge -- 1 -- s Comments Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 555 PIC18(L)F27/47K40 FIGURE 37-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 37-19: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param No. Sym. Characteristic 40* TT0H T0CKI High Pulse Width 41* TT0L T0CKI Low Pulse Width 42* TT0P T0CKI Period 45* TT1H 46* TT1L 47* TT1P T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Low Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous T1CKI Input Synchronous Period 49* No Prescaler With Prescaler No Prescaler With Prescaler Min. Typ Max. Units Conditions 0.5 TCY + 20 10 0.5 TCY + 20 10 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 30 0.5 TCY + 20 15 30 Greater of: 30 or TCY + 40 N 60 2 TOSC -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns N = prescale value -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns N = prescale value Asynchronous -- -- ns -- 7 TOSC -- Timers in Sync TCKEZTMR1 Delay from External Clock Edge to Timer Increment mode * These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 556 PIC18(L)F27/47K40 FIGURE 37-13: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 37-4 for load conditions. TABLE 37-20: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +125C Param Sym. No. Characteristic CC01* TccL CCPx Input Low Time No Prescaler CC02* TccH CCPx Input High Time No Prescaler With Prescaler With Prescaler CC03* TccP * CCPx Input Period Min. Typ Max. Units 0.5TCY + 20 -- -- ns ns 20 -- -- 0.5TCY + 20 -- -- ns 20 -- -- ns 3TCY + 40 N -- -- ns Conditions N = prescale value These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 557 PIC18(L)F27/47K40 FIGURE 37-14: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 37-4 for load conditions. TABLE 37-21: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. US120 Symbol TCKH2DTV Characteristic Min. SYNC XMIT (Master and Slave) Clock high to data-out valid Max. Units Conditions -- 80 ns 3.0V VDD 5.5V -- 100 ns 1.8V VDD 5.5V US121 TCKRF Clock out rise time and fall time (Master mode) -- 45 ns 3.0V VDD 5.5V -- 50 ns 1.8V VDD 5.5V US122 TDTRF Data-out rise time and fall time -- 45 ns 3.0V VDD 5.5V -- 50 ns 1.8V VDD 5.5V FIGURE 37-15: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 37-4 for load conditions. TABLE 37-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. US125 US126 Symbol TDTV2CKL TCKL2DTL Characteristic Min. Max. Units SYNC RCV (Master and Slave) Data-setup before CK (DT hold time) 10 -- ns Data-hold after CK (DT hold time) 15 -- ns 2016 Microchip Technology Inc. Preliminary Conditions DS40001844B-page 558 PIC18(L)F27/47K40 FIGURE 37-16: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 37-4 for load conditions. FIGURE 37-17: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb SP78 bit 6 - - - - - -1 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 37-4 for load conditions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 559 PIC18(L)F27/47K40 FIGURE 37-18: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 37-4 for load conditions. FIGURE 37-19: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 37-4 for load conditions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 560 PIC18(L)F27/47K40 TABLE 37-23: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. SP70* Symbol Characteristic TSSL2SCH, TSSL2SCL SS to SCK or SCK input Min. Typ Max. Units 2.25*TCY -- -- ns Conditions SP71* TSCH SCK input high time (Slave mode) TCY + 20 -- -- ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 -- -- ns SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 -- -- ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 -- -- ns SP75* TDOR SDO data output rise time -- 10 25 ns 3.0V VDD 5.5V -- 25 50 ns 1.8V VDD 5.5V SDO data output fall time -- 10 25 ns SP76* TDOF SP77* TSSH2DOZ SS to SDO output high-impedance 10 -- 50 ns SP78* TSCR SCK output rise time (Master mode) -- 10 25 ns 3.0V VDD 5.5V -- 25 50 ns 1.8V VDD 5.5V -- 10 25 ns SP79* TSCF SCK output fall time (Master mode) SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge SP81* TDOV2SCH, TDOV2SCL SDO data output setup to SCK edge SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, TSCL2SSH SS after SCK edge * -- -- 50 ns 3.0V VDD 5.5V -- -- 145 ns 1.8V VDD 5.5V 1 Tcy -- -- ns -- -- 50 ns 1.5 TCY + 40 -- -- ns These parameters are characterized but not tested. Data in "Typ" column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 561 PIC18(L)F27/47K40 FIGURE 37-20: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 37-4 for load conditions. TABLE 37-24: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. SP90* Symbol TSU:STA SP91* THD:STA TSU:STO SP92* THD:STO SP93 * Characteristic Min. Typ Max. Units Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated Start condition 100 kHz mode 4700 -- -- Setup time 400 kHz mode 600 -- -- Start condition 100 kHz mode 4000 -- -- Hold time 400 kHz mode 600 -- -- Stop condition 100 kHz mode 4700 -- -- Setup time 400 kHz mode 600 -- -- Stop condition 100 kHz mode 4000 -- -- Hold time 400 kHz mode 600 -- -- ns ns These parameters are characterized but not tested. FIGURE 37-21: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 37-4 for load conditions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 562 PIC18(L)F27/47K40 TABLE 37-25: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. SP100* Symbol THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 -- s Device must operate at a minimum of 10 MHz 1.5TCY -- 100 kHz mode 4.7 -- s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 -- s Device must operate at a minimum of 10 MHz SSP module SP101* TLOW Clock low time 1.5TCY -- 100 kHz mode -- 1000 ns 400 kHz mode 20 + 0.1CB 300 ns -- 250 ns 20 + 0.1CB 250 ns SSP module SP102* SP103* TR TF SDA and SCL rise time SDA and SCL fall time 100 kHz mode 400 kHz mode SP106* SP107* SP109* SP110* THD:DAT TSU:DAT TAA TBUF Data input hold time Data input setup time Output valid from clock Bus free time Conditions 100 kHz mode 0 -- ns 400 kHz mode 0 0.9 s 100 kHz mode 250 -- ns 400 kHz mode 100 -- ns 100 kHz mode -- 3500 ns 400 kHz mode -- -- ns 100 kHz mode 4.7 -- s 400 kHz mode 1.3 -- s -- 400 pF CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start SP111 CB * Note 1: These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. 2: Bus capacitive loading 2016 Microchip Technology Inc. Preliminary DS40001844B-page 563 PIC18(L)F27/47K40 38.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 564 PIC18(L)F27/47K40 39.0 PACKAGING INFORMATION Package Marking Information 28-Lead SPDIP (.300") Example PIC18F27K40 /SP e3 1526017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX PIC18F27K40 /SO e3 1526017 YYWWNNN 28-Lead SSOP (5.30 mm) Example PIC18F27K40 /SS e3 1526017 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 565 PIC18(L)F27/47K40 Package Marking Information (Continued) 28-Lead QFN (6x6 mm) Example PIN 1 PIN 1 18F27K40 /ML e3 1526017 XXXXXXXX XXXXXXXX YYWWNNN 28-Lead UQFN (4x4x0.5 mm) Example PIN 1 PIN 1 PIC18 F27K40 /MV e 526017 3 40-Lead PDIP (600 mil) Example PIC18F45K40 /P e3 XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: 1526017 Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 566 PIC18(L)F27/47K40 Package Marking Information (Continued) 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 PIC18 F47K40 /MV e 1526017 3 44-Lead QFN (8x8x0.9 mm) Example PIN 1 PIN 1 18F47K40 /ML e3 1526017 XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example 44-Lead TQFP (10x10x1 mm) 18F47K40 /PT e3 XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: 1526017 Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 567 PIC18(L)F27/47K40 39.1 Package Details The following sections give the technical details of the packages. "# ! J * + #* $ * K% 6#/ ##* ** HLL666+ +L K ! K ' * *%* N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB V*# +# [+*# X$+5 '!# X !* X9Y? X ] ^ * *! X\ G9 _ _ %%! K K## ; G#* *! _ _ ? ; ;; $% * $% %* %%! K%* ? ^ \" [* ; ;j * *! [ ; ^ 5 5 ^ G _ _ [% K## V [%%* [ 6 [%%* \" 6 7 ; "# !"#$%&'*$ +" /5$*+$#*5 *%6* * * % 7' *9 * #* ; +# #%?% * $%+ %'# * $# # %'# * $# ## *& %@ #% +# %* ?B G9H G# +# * & *"$# 66* $** # 2016 Microchip Technology Inc. Preliminary 6 9G DS40001844B-page 568 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 569 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 570 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 571 PIC18(L)F27/47K40 $% "# & '* J * + #* $ * K% 6#/ ##* ** HLL666+ +L K &! ! K ' * *%* D N E E1 1 2 NOTE 1 b e c A2 A A1 L L1 V*# +# [+*# X$+5 '!# [[?? X X X\ ] ^ !* \" Y * _ _ %%! K K## j ^ *% '' _ _ \" %* ? ^ ^ %%! K%* ? ; j \" [* J *[* [ J * * [ [% K## J * [%%* jG9 ?J _ { { ^{ 5 _ ;^ "# !"#$%&'*$ +" /5$*+$#*5 *%6* * * % +# #%?% * $%+ %'# * $# # %'# * $# ## *& %++ #% ; +# %* ?B G9H G# +# * & *"$# 66* $** # ?JH ' +# /$#$6* $** /' ' +* $ ## 2016 Microchip Technology Inc. Preliminary 6 9;G DS40001844B-page 572 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 573 PIC18(L)F27/47K40 2016 Microchip Technology Inc. Preliminary DS40001844B-page 574 PIC18(L)F27/47K40 2016 Microchip Technology Inc. Preliminary DS40001844B-page 575 PIC18(L)F27/47K40 + ,4 " 5 7 9;9 +,"! < $ *'' = 5$ "# J * + #* $ * K% 6#/ ##* ** HLL666+ +L K 2016 Microchip Technology Inc. Preliminary ! K ' * *%* DS40001844B-page 576 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 577 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 578 PIC18(L)F27/47K40 > 9 ! "# J * + #* $ * K% 6#/ ##* ** HLL666+ +L K ! K ' * *%* N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB V*# +# [+*# X$+5 '!# X !* X9Y? X ] * *! X\ G9 _ _ %%! K K## _ G#* *! _ _ ? _ j $% * $% %* %%! K%* ? ^ _ ^ \" [* ^ _ * *! [ _ ^ _ 5 ; _ 5 _ ; G _ _ [% K## V [%%* [ 6 [%%* \" 6 7 "# !"#$%&'*$ +" /5$*+$#*5 *%6* * * % 7' *9 * #* ; +# #%?% * $%+ %'# * $# # %'# * $# ## *& %@ #% +# %* ?B G9H G# +# * & *"$# 66* $** # 2016 Microchip Technology Inc. Preliminary 6 9jG DS40001844B-page 579 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 580 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 581 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 582 PIC18(L)F27/47K40 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C 0.10 C C SEATING PLANE A1 A 44X A3 0.08 C SIDE VIEW L 0.10 C A B D2 0.10 C A B E2 K 2 1 NOTE 1 N 44X b 0.07 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-103D Sheet 1 of 2 2016 Microchip Technology Inc. Preliminary DS40001844B-page 583 PIC18(L)F27/47K40 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.80 0.00 6.25 6.25 0.20 0.30 0.20 MILLIMETERS NOM 44 0.65 BSC 0.90 0.02 0.20 REF 8.00 BSC 6.45 8.00 BSC 6.45 0.30 0.40 - MAX 1.00 0.05 6.60 6.60 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103D Sheet 2 of 2 2016 Microchip Technology Inc. Preliminary DS40001844B-page 584 PIC18(L)F27/47K40 44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV 44 G2 1 2 OV EV C2 Y2 G1 Y1 E SILK SCREEN X1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X44) X1 Contact Pad Length (X44) Y1 Contact Pad to Contact Pad (X40) G1 Contact Pad to Center Pad (X44) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.65 BSC MAX 6.60 6.60 8.00 8.00 0.35 0.85 0.30 0.28 0.33 1.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-2103C 2016 Microchip Technology Inc. Preliminary DS40001844B-page 585 PIC18(L)F27/47K40 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D1 NOTE 2 B (DATUM A) (DATUM B) E1 A NOTE 1 2X 0.20 H A B E A N 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A A2 C SEATING PLANE 0.10 C SIDE VIEW A1 1 2 3 N NOTE 1 44 X b 0.20 e C A B BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2 2016 Microchip Technology Inc. Preliminary DS40001844B-page 586 PIC18(L)F27/47K40 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c L (L1) SECTION A-A Notes: Units Dimension Limits Number of Leads N e Lead Pitch A Overall Height Standoff A1 A2 Molded Package Thickness Overall Width E Molded Package Width E1 D Overall Length D1 Molded Package Length b Lead Width c Lead Thickness Lead Length L Footprint L1 Foot Angle MIN 0.05 0.95 0.30 0.09 0.45 0 MILLIMETERS NOM 44 0.80 BSC 1.00 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC 0.37 0.60 1.00 REF 3.5 MAX 1.20 0.15 1.05 0.45 0.20 0.75 7 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2 2016 Microchip Technology Inc. Preliminary DS40001844B-page 587 PIC18(L)F27/47K40 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. Preliminary DS40001844B-page 588 PIC18(L)F27/47K40 APPENDIX A: REVISION HISTORY Revision A (5/2016) Initial release of this document. Revision B (9/2016) Updated Peripheral Module, Memory and Core features descriptions on cover page. Updated the PIC18(L)F2x/4xK40 Family Types Table. Updated Examples 11-1, 11-3, 11-5 and 11-6; Figures 14-1 and 32-2; Registers 4-2, 4-5, 13-18 and 32-6; Sections 1.2, 4.4.1, 4.5, 4.5.4, 17.3, 17.5, 17.7, 18.1, 18.1.1, 18.1.1.1, 18.1.2, 18.1.6, 18.3, 18.4, 18.7, 19.0, 19.8.1, 20.0, 21.3 and 26.3; Tables 4-2, 10-4, 37-2, 37-3, 37-5, 37-13 and 37-14. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 589 PIC18(L)F27/47K40 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Features(1) PIC18(L)F27K40 PIC18(L)F47K40 131072 131072 SRAM (Bytes) 3720 3720 EEPROM (Bytes) 1024 1024 Interrupt Sources 36 36 Ports A, B, C, (E) Ports A, B, C, D, E 2 2 4 internal 24 external 4 internal 35 external 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin UQFN 28-pin SPDIP 28-pin SOIC 28-pin SSOP 28-pin QFN 28-pin UQFN 40-pin PDIP 40-pin UQFN 44-pin TQFP 44-pin QFN Program Memory (Bytes) I/O Ports Capture/Compare/PWM Modules (CCP) 10-bit Analog-to-Digital Module Packages Note 1: PIC18F2xK40: operating voltage, 2.3V-5.5V. PIC18LF2xK40: operating voltage, 1.8V-3.6V. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 590 PIC18(L)F27/47K40 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under "Support", click on "Customer Change Notification" and follow the registration instructions. 2016 Microchip Technology Inc. Preliminary DS40001844B-page 591 PIC18(L)F27/47K40 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](2) - Tape and Reel Option X /XX XXX Temperature Range Package Pattern a) b) c) Device: PIC18F27K40, PIC18LF27K40, PIC18F47K40, PIC18LF47K40, Tape and Reel Option: Blank = standard packaging (tube or tray) T = Tape and Reel(1), (2) Temperature Range: E I = -40C to +125C = -40C to +85C Examples: PIC18F27K40-E/P 301 = Extended temp., PDIP package, QTP pattern #301. PIC18F47K40-E/SO = Extended temp., SOIC package. PIC18F47K40T-I/ML = Tape and reel, Industrial temp., QFN package. (Extended) (Industrial) Note 1: Package: Pattern: ML ML MV MV P PT SO SP SS = = = = = = = = = 28-lead QFN 6x6mm 44-lead QFN 8x8x0.9mm 28-lead UQFN 4x4x0.5mm 40-lead UQFN 5x5x0.5mm 40-lead PDIP 44-lead TQFP (Thin Quad Flatpack) 28-lead SOIC 28-lead Skinny Plastic DIP 28-lead SSOP 2: Tape and Reel option is available for ML, MV, PT, SO and SS packages with industrial Temperature Range only. Tape and Reel identifier only appears in catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. QTP, SQTP, Code or Special Requirements (blank otherwise) 2016 Microchip Technology Inc. Preliminary DS40001844B-page 592 PIC18(L)F27/47K40 Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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