MP1475
High-Efficiency, 3A, 16V, 500kHz
Synchronous, Step-Down Converter
MP1475 Rev. 1.01 www.MonolithicPower.com 1
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
The Future of Analog IC Technology
DESCRIPTION
The MP1475 is a high-frequency, synchronous,
rectified, step-down, switch-mode converter
with built-in power MOSFETs. It offers a very
compact solution to achieve a 3A continuous
output current with excellent load and line
regulation over a wide input supply range. The
MP1475 has synchronous mode operation for
higher efficiency over the output current load
range.
Current-mode operation provides fast transient
response and eases loop stabilization.
Full protection features include over-current
protection and thermal shut down.
The MP1475 requires a minimal number of
readily-available standard external components,
and is available in a space-saving 8-pin
TSOT23 package.
FEATURES
• Wide 4.5V-to-16V Operating Input Range
• 80m/30m Low RDS(ON) Internal Power
MOSFETs
• High-Efficiency Synchronous Mode
Operation
• Fixed 500kHz Switching Frequency
• Synchronizes from a 200kHz-to-2MHz
External Clock
• Power-Save Mode at light load
• Internal Soft-Start
• Power Good Indicator
• OCP Protection and Hiccup
• Thermal Shutdown
• Output Adjustable from 0.8V
• Available in an 8-pin TSOT-23 Package
APPLICATIONS
• Notebook Systems and I/O Power
• Digital Set-Top Boxes
• Flat-Panel Television and Monitors
• Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithi
c
Power Systems, Inc.
TYPICAL APPLICATION
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 2
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
ORDERING INFORMATION
Part Number* Package Top Marking
MP1475DJ TSOT-23-8 ADP
* For Tape & Reel, add suffix –Z (e.g. MP1475DJ–Z);
For RoHS Compliant Packaging, add suffix –LF (e.g. MP1475DJ–LF–Z)
PACKAGE REFERENCE
PG
IN
SW
GND
FB
VCC
EN/SYNC
BST
1
2
3
4
8
7
6
5
TOP VIEW
ABSOLUTE MAXIMUM RATINGS (1)
VIN ................................................ -0.3V to 17V
VSW ....................................................................
-0.3V (-5V for <10ns) to 17V (19V for <10ns)
VBST ...................................................... VSW+6V
All Other Pins................................-0.3V to 6V (2)
Continuous Power Dissipation (TA = +25°C) (3)
..........................................................1.25W
Junction Temperature.............................. 150°C
Lead Temperature ................................... 260°C
Storage Temperature................. -65°C to 150°C
Recommended Operating Conditions (4)
Supply Voltage VIN .......................... 4.5V to 16V
Output Voltage VOUT............... 0.8V to VIN x DMAX
Operating Junction Temp. (TJ). -40°C to +125°C
Thermal Resistance (5) θJA θJC
TSOT-23-8............................ 100 ..... 55... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) About the details of EN pin’s ABS MAX rating, please refer to
Page 9, Enable/SYNC control section.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance JA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/JA. Exceeding the maximum allowable powe
r
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanen
t
damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 3
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
ELECTRICAL CHARACTERISTICS (6)
VIN = 12V, TA = 25°C, unless otherwise noted.
Parameter Symbol Condition Min Typ Max Units
Supply Current (Shutdown) IIN V
EN = 0V 7 A
Supply Current (Quiescent) Iq V
EN = 2V, VFB = 1V 0.6 1 mA
HS Switch-On Resistance HSRDS-ON VBST-SW=5V 80 m
LS Switch-On Resistance LSRDS-ON VCC =5V 30 m
Switch Leakage SWLKG V
EN = 0V, VSW =12V 1 A
Current Limit (6) I
LIMIT Under 40% Duty Cycle 4.2 5 A
Oscillator Frequency fSW V
FB=0.75V 430 500 570 kHz
Fold-Back Frequency fFB V
FB<400mV 0.25 fSW
Maximum Duty Cycle DMAX V
FB=700mV 90 95 %
Minimum On Time(6) τON_MIN 40 ns
Sync Frequency Range fSYNC 0.2 2 MHz
TA =25°C 791 807 823
Feedback Voltage VFB -40°C<TA<85°C (7) 787 807 827
mV
Feedback Current IFB V
FB=820mV 10 50 nA
EN Rising Threshold VEN_RISING 1.2 1.4 1.6 V
EN Falling Threshold VEN_FALLING 1.1 1.25 1.4 V
VEN=2V 2 A
EN Input Current IEN
VEN=0 0 A
EN Turn-Off Delay ENtd-off 5 s
Power-Good Rising Threshold PGvth-Hi 0.9 VFB
Power-Good Falling Threshold PGvth-Lo 0.85 VFB
Power-Good Delay PGTd 0.4 ms
Power-Good Sink Current
Capabilily VPG Sink 4mA 0.4 V
Power-Good Leakage Current IPG-LEAK 1 A
VIN Under-Voltage Lockout
Threshold-Rising INUVVth 3.7 3.9 4.1 V
VIN Under-Voltage Lockout
Threshold-Hysteresis INUVHYS 650 mV
VCC Regulator VCC 5 V
VCC Load Regulation ICC=5mA 3 %
Soft-Start Period τSS 1.2 ms
Thermal Shutdown (6) 150 °C
Thermal Hysteresis (6) 20 °C
Notes:
6) Guaranteed by design.
7) Not tested in production and guaranteed by over-temperature correlation.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 4
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 5
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=4.7μH, TA = 25°C, unless otherwise noted.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 6
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 7
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
PIN FUNCTIONS
Package
Pin # Name Description
1 PG
Power Good Output. The output of this pin is an open drain that goes high if the output
voltage exceeds 90% of the normal voltage. There is a 0.4ms delay between when
FB90% to when the PG pin goes high.
2 IN
Supply Voltage. The IN pin supplies power for internal MOSFET and regulator. The
MP1475 operates from a +4.5V to +16V input rail. Requires a low-ESR, and low-
inductance capacitor (C1) to decouple the input rail. Place the input capacitor very close to
this pin and connect it with wide PCB traces and multiple vias to make the connection.
3 SW
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is driven
up to VIN by the high-side switch during the PWM duty cycle ON-time. The inductor current
drives the SW pin negative during the OFF-time. The ON-resistance of the low-side switch
and the internal body diode fixes the negative voltage. Connect using wide PCB traces
and multiple vias.
4 GND
System Ground. Reference ground of the regulated output voltage. PCB layout requires
extra care. For best results connect to GND with copper and vias.
5 BST
Bootstrap. Requires a capacitor connected between SW and BST pins is required to form
a floating supply across the high-side switch driver.
6 EN/SYNC
Enable. EN=high to enable the MP1475. Apply an external clock to change the switching
frequency. For automatic start-up, connect EN pin to VIN with an 100k resistor.
7 VCC
Internal 5V LDO output. Powers the driver and control circuits are powered from this
voltage. Decouple with a 0.1F-0.22F capacitor. Do not use a capacitor 0.22F.
8 FB
Feedback. Connect to the tap of an external resistor divider from the output to GND to set
the output voltage. The frequency fold-back comparator lowers the oscillator frequency
when the FB voltage is below 400mV to prevent current limit runaway during a short-circuit
fault condition. Place the resistor divider as close to the FB pin as possible.
A
void placing
vias on the FB traces.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 8
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
FUNCTIONAL BLOCK DIAGRAM
50pF
1MEG
6.5V
BST
RSEN
IN
Oscillator
VCC
Regulator
Bootstrap
Regulator
VCC
Currrent Sense
Amplifer
VCC
Current Limit
Comparator
Error Amplifier
Ref
Reference
EN/SYNC
FB
+
+
+
-
-
+
-
+
-
PG
SW
GND
LS
Driver
HS
Driver
Comparator
On Time Control
Logic Control
1pF
400k
Figure 1: Functional Block Diagram
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 9
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
OPERATION
The MP1475 is a high-frequency, synchronous,
rectified, step-down, switch-mode converter
with built-in power MOSFETs. It offers a very
compact solution that achieves a 3A continuous
output current with excellent load and line
regulation over a wide input supply range.
The MP1475 operates in a fixed-frequency,
peak-current–control mode to regulate the
output voltage. An internal clock initiates a
PWM cycle. The integrated high-side power
MOSFET turns on and remains on until the
current reaches the value set by the COMP
voltage. When the power switch is off, it
remains off until the next clock cycle starts. If,
within 95% of one PWM period, the current in
the power MOSFET does not reach the value
set by the COMP value, the power MOSFET is
forced to turn off.
Internal Regulator
A 5V internal regulator powers most of the
internal circuitries. This regulator takes the VIN
input and operates in the full VIN range. When
VIN exceeds 5.0V, the output of the regulator is
in full regulation. When VIN is less than 5.0V,
the output decreases, and the part requires a
0.1µF ceramic decoupling capacitor.
Error Amplifier
The error amplifier compares the FB pin voltage
to the internal 0.807V reference (VREF) and
outputs a current proportional to the difference
between the two. This output current then
charges or discharges the internal
compensation network to form the COMP
voltage, which controls the power MOSFET
current. The optimized internal compensation
network minimizes the external component
counts and simplifies the control loop design.
Enable/SYNC control
EN/SYNC is a digital control pin that turns the
regulator on and off. Drive EN high to turn on
the regulator; drive it low to turn it off. An
internal 1M resistor from EN/SYNC to GND
allows EN/SYNC to be floated to shut down the
chip.
The EN pin is clamped internally using a 6.5V
series-Zener-diode as shown in Figure 2.
Connecting the EN input pin through a pullup
resistor to the voltage on the IN pin limits the
EN input current to less than 100µA.
For example, with 12V connected to IN, RPULLUP
(12V – 6.5V) ÷ 100µA = 55k.
Connecting the EN pin is directly to a voltage
source without any pullup resistor requires
limiting the amplitude of the voltage source to
6V to prevent damage to the Zener diode.
Figure 2: 6.5V Zener Diode Connection
For external clock synchronization, connect a
clock with a frequency range between 200kHz
and 2MHz 2ms after the output voltage is set:
The internal clock rising edge will synchronize
with the external clock rising edge. Select an
external clock signal with a pulse width less
than 1.7s.
Under-Voltage Lockout (UVLO)
The MP1475 has under-voltage lock-out
protection (UVLO). When the VCC voltage
exceeds the UVLO rising threshold voltage, the
MP1475 will power up. It shuts off when the
VCC voltage drops below the UVLO falling
threshold voltage. This is non-latch protection.
The MP1475 is disabled when the input voltage
falls below 3.25V. If an application requires a
higher under-voltage lockout (UVLO) threshold,
use the EN pin as shown in Figure 3 to adjust
the input voltage UVLO by using two external
resistors. For best results, set the UVLO falling
threshold (VSTOP) above 4.5V using the
enable resistors. Set the rising threshold
(VSTART) to provide enough hysteresis to
allow for any input supply variations.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 10
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
Figure 3: Adjustable UVLO
Internal Soft-Start
The soft-start prevents the converter output
voltage from overshooting during startup. When
the chip starts, the internal circuitry generates a
soft-start voltage (VSS) that ramps up from 0V to
1.2V. When VSS is less than VREF, the error
amplifier uses VSS as the reference. When VSS
exceeds VREF, the error amplifier uses VREF as
the reference. The SS time is internally set to
1.2ms.
Power Good Indicator
MP1475 has an open drain pin as the power-
good indicator (PG). Pull this up to VCC or
another external source through a 100k
resistor. When VFB exceeds 90% of VREF, PG
switches goes high with 0.4ms delay time. If VFB
goes below 85% of VREF, an internal MOSFET
pulls the PG pin down to ground.
The internal circuit keeps the PG low once the
input supply exceeds 1.2V.
Over-Current-Protection and Hiccup
The MP1475 has a cycle-by-cycle over-current
limit when the inductor current peak value
exceeds the set current limit threshold.
Meanwhile, the output voltage drops until VFB is
below the under-voltage (UV) threshold—
typically 50% below the reference. Once UV is
triggered, the MP1475 enters hiccup mode to
periodically restart the part. This protection
mode is especially useful when the output is
dead-shorted to ground, and greatly reduces
the average short circuit current to alleviate
thermal issues and protect the regulator. The
MP1475 exits the hiccup mode once the over-
current condition is removed.
Thermal Shutdown
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the silicon die reaches temperatures that
exceed 150°C, it shuts down the whole chip.
When the temperature drops below its lower
threshold, typically 130°C, the chip is enabled
again.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. This
UVLO’s rising threshold is 2.2V with a
hysteresis of 150mV. The bootstrap capacitor
voltage is regulated internally by VIN through D1,
M1, R3, C4, L1 and C2 (Figure 4). If (VIN-VSW)
exceeds 5V, U1 will regulate M1 to maintain a
5V BST voltage across C4. A 20 resistor
placed between SW and BST cap. is strongly
recommended to reduce SW spike voltage.
V
IN
D1
5V
M1
U1
BST
C4
SW L1
V
OUT
C2
R3
Figure 4: Internal Bootstrap Charging Circuit
Startup and Shutdown
If both VIN and VEN exceed their respective
thresholds, the chip starts. The reference block
starts first, generating stable reference voltage
and currents, and then the internal regulator is
enabled. The regulator provides a stable supply
for the remaining circuitries.
Three events can shut down the chip: VEN low,
VIN low, and thermal shutdown. During the
shutdown procedure, the signaling path is first
blocked to avoid any fault triggering. The
COMP voltage and the internal supply rail are
then pulled down. The floating driver is not
subject to this shutdown command.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 11
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider sets the output
voltage (see Typical Application on page 1). The
feedback resistor R1 also sets the feedback loop
bandwidth with the internal compensation
capacitor (see Typical Application on page 1).
Choose R1 around 40k. R2 is then given by:
OUT
R1
R2 V1
0.807V
=
−
The T-type network—as shown in Figure 5—is
highly recommended when VOUT is low.
Rt
FB 8
R2
R1
Cf
VOUT
Figure 5: T-Type Network
Table 1 lists the recommended T-type resistors
value for common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
VOUT
(V) R1 (kΩ) R2 (kΩ) Rt (kΩ) Cf(pF) L(μH)
1.0 20.5 84.5 82 15 2.2
1.2 30.1 61.9 82 15 2.2
1.8 40.2 32.4 33 15 3.3
2.5 40.2 19.1 33 15 3.3
3.3 40.2 13 16 15 4.7
5 40.2 7.68 16 15 4.7
Selecting the Inductor
Use a1µH-to-10µH inductor with a DC current
rating of at least 25% percent higher than the
maximum load current for most applications. For
highest efficiency, use an inductor with a DC
resistance less than 15m. For most designs,
the inductance value can be derived from the
following equation.
OUT IN OUT
1
IN L OSC
V(VV)
LVIf
×−
=×Δ ×
Where IL is the inductor ripple current.
Choose the inductor ripple current to be
approximately 30% of the maximum load current.
The maximum inductor peak current is:
2
I
II L
LOAD)MAX(L
Δ
+=
Use a larger inductor for improved efficiency
under light-load conditions—below 100mA.
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, therefore requires a capacitor is to
supply the AC current to the step-down converter
while maintaining the DC input voltage. Use low
ESR capacitors for the best performance. Use
ceramic capacitors with X5R or X7R dielectrics
for best results because of their low ESR and
small temperature coefficients. For most
applications, use a 22µF capacitor.
Since C1 absorbs the input switching current, it
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated by:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×−×=
IN
OUT
IN
OUT
LOAD1C V
V
1
V
V
II
The worse case condition occurs at VIN = 2VOUT,
where:
2
I
ILOAD
1C =
For simplification, choose an input capacitor with
an RMS current rating greater than half of the
maximum load current.
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, add a small, high quality ceramic
capacitor (e.g. 0.1F) placed as close to the IC
as possible. When using ceramic capacitors,
make sure that they have enough capacitance to
provide sufficient charge to prevent excessive
voltage ripple at input. The input voltage ripple
caused by capacitance can be estimated as:
LOAD OUT OUT
IN IN
SIN
IV V
V1
fC1V V
⎛⎞
Δ= × ×−
⎜⎟
×⎝⎠
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 12
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
Selecting the Output Capacitor
The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low-
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output
voltage ripple low. The output voltage ripple can
be estimated as:
OUT OUT
OUT ESR
S1 IN S
VV 1
V1R
fL V 8fC2
⎛⎞⎛⎞
Δ= ×− × +
⎜⎟⎜⎟
×××
⎝⎠⎝ ⎠
Where L1 is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output voltage ripple. For
simplification, the output voltage ripple can be
estimated as:
OUT OUT
OUT 2
IN
S1
VV
V1
V
8f L C2
⎛⎞
=×−
⎜⎟
××× ⎝⎠
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated as:
OUT OUT
OUT ESR
IN
S1
VV
V1R
fL V
⎛⎞
=×−×
⎜⎟
×⎝⎠
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP1475 can be optimized for a wide range of
capacitance and ESR values.
External Bootstrap Diode
An external bootstrap diode can enhance the
efficiency of the regulator given the following
conditions:
z VOUT is 5V or 3.3V; and
z Duty cycle is high: D=
IN
OUT
V
V>65%
In these cases, add an external BST diode from
the VCC pin to BST pin, as shown in Figure 6.
SW
BST
MP1475 C
L
BST
C
OUT
External BST Diode
VCC
IN4148
Figure 6: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the BST capacitor value is 0.1µF
to 1F.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 13
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
PC Board Layout (8)
PCB layout is very important to achieve stable
operation especially for VCC capacitor and
input capacitor placement. For best results,
follow these guidelines:
1. Use large ground plane directly connect to
GND pin. Add vias near the GND pin if
bottom layer is ground plane.
2. Place the VCC capacitor to VCC pin and
GND pin as close as possible. Make the
trace length of VCC pin-VCC capacitor
anode-VCC capacitor cathode-chip GND
pin as short as possible.
3. Place the ceramic input capacitor close to
IN and GND pins. Keep the connection of
input capacitor and IN pin as short and
wide as possible.
4. Route SW, BST away from sensitive
analog areas such as FB. It’s not
recommended to route SW, BST trace
under chip’s bottom side.
5. Place the T-type feedback resistor R6 close
to chip to ensure the trace which connects
to FB pin as short as possible
Notes:
8) The recommended layout is based on the Figure 7 Typical
Application circuit on the next page.
8
7
6
5
L1
C2
C1
C1A
R4
R2
R3
C4
C5
1
2
3
4
Vin
GND
Vout
SW
GND
C3
R1
R6
R5
C2A
GND
SW
BST
GND
VOUT
EN/SYNC
VCC
Design Example
Below is a design example following the
application guidelines for the specifications:
Table 2: Design Example
VIN 12V
VOUT 3.3V
Io 3A
The detailed application schematic is shown in
Figure 8. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
Evaluation Board Datasheets.
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 14
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
TYPICAL APPLICATION CIRCUITS
Figure 7: 12VIN, 5V/3A Output
Figure 8: 12VIN, 3.3V/3A Output
Figure 9: 12VIN, 2.5V/3A Output
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER
MP1475 Rev. 1.01 www.MonolithicPower.com 15
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
Figure 10: 12VIN, 1.8V/3A Output
Figure 11: 12VIN, 1.2V/3A Output
Figure 12: 12VIN, 1V/3A Output
MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP1475 Rev. 1.01 www.MonolithicPower.com 16
4/3/2014 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
PACKAGE INFORMATION
TSOT23-8
FRONT VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER
FORMING) SHALL BE 0.10 MILLIMETERS MAX.
5) JEDEC REFERENCE IS MO-193, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
7) PIN 1 IS LOWER LEFT PIN WHEN READING TOP MARK
FROM LEFT TO RIGHT, (SEE EXAMPLE TOP MARK)
TO P VI EW RECOMMEND ED LAND PA TTERN
SEATING PLANE
SI DE VIEW
DETAIL ''A''
SEE DETAIL ''A''
IAAAA
PIN 1 ID
See note 7
EXA M PLE
TOP M ARK
