User's Manual 16 RL78/G13 User's Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.2.00 Feb 2012 Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the RL78/G13 and design and develop application systems and programs for these devices. The target products are as follows. * 20-pin: R5F1006x (x = A, C, D, E) * 44-pin: R5F101Fx (x = A, C, D, E, F, G, H, J, K, L) R5F1016x (x = A, C, D, E) * 24-pin: R5F1007x (x = A, C, D, E) * 48-pin: * 52-pin: * 64-pin: * 80-pin: * 100-pin: * 128-pin: R5F101Ex (x = A, C, D, E, F, G, H) Purpose R5F100Px (x = F, G, H, J, K, L) R5F101Px (x = F, G, H, J, K, L) R5F101Cx (x = A, C, D, E, F, G) * 40-pin: R5F100Ex (x = A, C, D, E, F, G, H) R5F100Mx (x = F, G, H, J, K, L) R5F101Mx (x = F, G, H, J, K, L) R5F101Bx (x = A, C, D, E, F, G) * 36-pin: R5F100Cx (x = A, C, D, E, F, G) R5F100Lx (x = C, D, E, F, G, H, J, K, L) R5F101Lx (x = C, D, E, F, G, H, J, K, L) R5F101Ax (x = A, C, D, E, F, G) * 32-pin: R5F100Bx (x = A, C, D, E, F, G) R5F100Jx (x = C, D, E, F, G, H, J, K, L) R5F101Jx (x = C, D, E, F, G, H, J, K, L) R5F1018x (x = A, C, D, E) * 30-pin: R5F100Ax (x = A, C, D, E, F, G) R5F100Gx (x = A, C, D, E, F, G, H, J, K, L) R5F101Gx (x = A, C, D, E, F, G, H, J, K, L) R5F1017x (x = A, C, D, E) * 25-pin: R5F1008x (x = A, C, D, E) R5F100Fx (x = A, C, D, E, F, G, H, J, K, L) R5F100Sx (x = H, J, K, L) R5F101Sx (x = H, J, K, L) This manual is intended to give users an understanding of the functions described in the Organization below. Organization The RL78/G13 manual is separated into two parts: this manual and the instructions edition (common to the RL78 Microcontroller). RL78/G13 RL78 Microcontroller User's Manual User's Manual (This Manual) Instructions * Pin functions * CPU functions * Internal block functions * Instruction set * Interrupts * Explanation of each instruction * Other on-chip peripheral functions * Electrical specifications How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark "<R>" shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. * How to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. * To know details of the RL78 Microcontroller instructions: Refer to the separate document RL78 Microcontroller Instructions User's Manual (R01US0015E). Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: xxx (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...xxxx or xxxxB Numerical representations: Binary ...xxxx Decimal Hexadecimal Related Documents ...xxxxH The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. RL78/G13 User's Manual Hardware This manual RL78 Microcontroller Instructions User's Manual R01US0015E Documents Related to Flash Memory Programming Document Name PG-FP5 Flash Memory Programmer User's Manual Document No. R20UT0008E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. Other Documents Document Name RENESAS MICROCOMPUTER GENERAL CATALOG Document No. R01CS0001E Semiconductor Package Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Package Mount Manual" website (http://www.renesas.com/products/package/manual/index.jsp). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 Features........................................................................................................................................... 1 1.2 Ordering Information...................................................................................................................... 3 1.3 Pin Configuration (Top View) ........................................................................................................ 8 1.3.1 20-pin products................................................................................................................................... 8 1.3.2 24-pin products................................................................................................................................... 9 1.3.3 25-pin products................................................................................................................................. 10 1.3.4 30-pin products................................................................................................................................. 11 1.3.5 32-pin products................................................................................................................................. 12 1.3.6 36-pin products................................................................................................................................. 13 1.3.7 40-pin products................................................................................................................................. 14 1.3.8 44-pin products................................................................................................................................. 15 1.3.9 48-pin products................................................................................................................................. 16 1.3.10 52-pin products............................................................................................................................... 18 1.3.11 64-pin products............................................................................................................................... 19 1.3.12 80-pin products............................................................................................................................... 21 1.3.13 100-pin products............................................................................................................................. 22 1.3.14 128-pin products............................................................................................................................. 24 1.4 Pin Identification........................................................................................................................... 25 1.5 Block Diagram .............................................................................................................................. 26 1.5.1 20-pin products................................................................................................................................. 26 1.5.2 24-pin products................................................................................................................................. 27 1.5.3 25-pin products................................................................................................................................. 28 1.5.4 30-pin products................................................................................................................................. 29 1.5.5 32-pin products................................................................................................................................. 30 1.5.6 36-pin products................................................................................................................................. 31 1.5.7 40-pin products................................................................................................................................. 32 1.5.8 44-pin products................................................................................................................................. 33 1.5.9 48-pin products................................................................................................................................. 34 1.5.10 52-pin products............................................................................................................................... 35 1.5.11 64-pin products............................................................................................................................... 36 1.5.12 80-pin products............................................................................................................................... 37 1.5.13 100-pin products............................................................................................................................. 38 1.5.14 128-pin products............................................................................................................................. 39 1.6 Outline of Functions..................................................................................................................... 40 Index-1 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 46 2.1 Port Function ................................................................................................................................ 46 2.1.1 20-pin products................................................................................................................................. 47 2.1.2 24-pin products................................................................................................................................. 48 2.1.3 25-pin products................................................................................................................................. 49 2.1.4 30-pin products................................................................................................................................. 50 2.1.5 32-pin products................................................................................................................................. 52 2.1.6 36-pin products................................................................................................................................. 54 2.1.7 40-pin products................................................................................................................................. 56 2.1.8 44-pin products................................................................................................................................. 58 2.1.9 48-pin products................................................................................................................................. 60 2.1.10 52-pin products............................................................................................................................... 62 2.1.11 64-pin products............................................................................................................................... 64 2.1.12 80-pin products............................................................................................................................... 66 2.1.13 100-pin products............................................................................................................................. 69 2.1.14 128-pin products............................................................................................................................. 72 2.2 Functions other than port pins ................................................................................................... 76 2.2.1 With functions for each product ........................................................................................................ 76 2.2.2 Pins for each product (pins other than port pins).............................................................................. 81 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 83 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 89 3.1 Memory Space .............................................................................................................................. 89 3.1.1 Internal program memory space..................................................................................................... 105 3.1.2 Mirror area...................................................................................................................................... 108 3.1.3 Internal data memory space ........................................................................................................... 110 3.1.4 Special function register (SFR) area .............................................................................................. 111 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ..................... 111 3.1.6 Data memory addressing ............................................................................................................... 112 3.2 Processor Registers................................................................................................................... 122 3.2.1 Control registers ............................................................................................................................. 122 3.2.2 General-purpose registers.............................................................................................................. 124 3.2.3 ES and CS registers....................................................................................................................... 126 3.2.4 Special function registers (SFRs) ................................................................................................... 127 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ......................... 133 3.3 Instruction Address Addressing............................................................................................... 142 3.3.1 Relative addressing........................................................................................................................ 142 3.3.2 Immediate addressing .................................................................................................................... 142 3.3.3 Table indirect addressing ............................................................................................................... 143 3.3.4 Register direct addressing.............................................................................................................. 144 Index-2 3.4 Addressing for Processing Data Addresses ........................................................................... 145 3.4.1 Implied addressing ......................................................................................................................... 145 3.4.2 Register addressing ....................................................................................................................... 145 3.4.3 Direct addressing ........................................................................................................................... 146 3.4.4 Short direct addressing .................................................................................................................. 147 3.4.5 SFR addressing.............................................................................................................................. 148 3.4.6 Register indirect addressing ........................................................................................................... 149 3.4.7 Based addressing........................................................................................................................... 150 3.4.8 Based indexed addressing ............................................................................................................. 153 3.4.9 Stack addressing............................................................................................................................ 154 CHAPTER 4 PORT FUNCTIONS ......................................................................................................... 155 4.1 Port Functions ............................................................................................................................ 155 4.2 Port Configuration...................................................................................................................... 156 4.2.1 Port 0.............................................................................................................................................. 158 4.2.2 Port 1.............................................................................................................................................. 166 4.2.3 Port 2.............................................................................................................................................. 174 4.2.4 Port 3.............................................................................................................................................. 176 4.2.5 Port 4.............................................................................................................................................. 181 4.2.6 Port 5.............................................................................................................................................. 190 4.2.7 Port 6.............................................................................................................................................. 198 4.2.8 Port 7.............................................................................................................................................. 201 4.2.9 Port 8.............................................................................................................................................. 208 4.2.10 Port 9............................................................................................................................................ 213 4.2.11 Port 10.......................................................................................................................................... 218 4.2.12 Port 11.......................................................................................................................................... 222 4.2.13 Port 12.......................................................................................................................................... 226 4.2.14 Port 13.......................................................................................................................................... 231 4.2.15 Port 14.......................................................................................................................................... 233 4.2.16 Port 15.......................................................................................................................................... 240 4.3 Registers Controlling Port Function ........................................................................................ 242 4.4 Port Function Operations .......................................................................................................... 261 4.4.1 Writing to I/O port ........................................................................................................................... 261 4.4.2 Reading from I/O port ..................................................................................................................... 261 4.4.3 Operations on I/O port .................................................................................................................... 261 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) ....................................... 262 4.5 Settings of Port Related Register When Using Alternate Function ...................................... 264 4.6 Cautions When Using Port Function........................................................................................ 270 4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) ............................................... 270 4.6.2 Notes on specifying the pin settings ............................................................................................... 271 Index-3 CHAPTER 5 CLOCK GENERATOR .................................................................................................... 272 5.1 Functions of Clock Generator................................................................................................... 272 5.2 Configuration of Clock Generator ............................................................................................ 274 5.3 Registers Controlling Clock Generator.................................................................................... 276 5.4 System Clock Oscillator ............................................................................................................ 291 5.4.1 X1 oscillator.................................................................................................................................... 291 5.4.2 XT1 oscillator.................................................................................................................................. 291 5.4.3 High-speed on-chip oscillator ......................................................................................................... 295 5.4.4 Low-speed on-chip oscillator .......................................................................................................... 295 5.5 Clock Generator Operation ....................................................................................................... 296 5.6 Controlling Clock........................................................................................................................ 298 5.6.1 Example of setting high-speed on-chip oscillator ........................................................................... 298 5.6.2 Example of setting X1 oscillation clock........................................................................................... 299 5.6.3 Example of setting XT1 oscillation clock ........................................................................................ 300 5.6.4 CPU clock status transition diagram............................................................................................... 301 5.6.5 Condition before changing CPU clock and processing after changing CPU clock ......................... 307 5.6.6 Time required for switchover of CPU clock and system clock ........................................................ 309 5.6.7 Conditions before clock oscillation is stopped ................................................................................ 310 5.7 Resonator and Oscillator Constants ........................................................................................ 311 CHAPTER 6 TIMER ARRAY UNIT...................................................................................................... 314 6.1 Functions of Timer Array Unit................................................................................................... 316 6.1.1 Independent channel operation function ........................................................................................ 316 6.1.2 Simultaneous channel operation function....................................................................................... 317 6.1.3 8-bit timer operation function (channels 1 and 3 only).................................................................... 318 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) ................................................................... 319 6.2 Configuration of Timer Array Unit ............................................................................................ 320 6.3 Registers Controlling Timer Array Unit.................................................................................... 328 6.4 Basic Rules of Timer Array Unit ............................................................................................... 353 6.4.1 Basic rules of simultaneous channel operation function................................................................. 353 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) ............................................. 355 6.5 Operation of Counter ................................................................................................................. 356 6.5.1 Count clock (fTCLK) .......................................................................................................................... 356 6.5.2 Start timing of counter .................................................................................................................... 358 6.5.3 Operation of counter....................................................................................................................... 359 6.6 Channel Output (TOmn pin) Control ........................................................................................ 364 6.6.1 TOmn pin output circuit configuration............................................................................................. 364 6.6.2 TOmn Pin Output Setting ............................................................................................................... 365 6.6.3 Cautions on Channel Output Operation ......................................................................................... 366 6.6.4 Collective manipulation of TOmn bit............................................................................................... 371 Index-4 6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start ............................................................... 372 6.7 Independent Channel Operation Function of Timer Array Unit............................................. 373 6.7.1 Operation as interval timer/square wave output ............................................................................. 373 6.7.2 Operation as external event counter .............................................................................................. 379 6.7.3 Operation as frequency divider (channel 0 of unit 0 only) .............................................................. 384 6.7.4 Operation as input pulse interval measurement ............................................................................. 388 6.7.5 Operation as input signal high-/low-level width measurement........................................................ 392 6.7.6 Operation as delay counter ............................................................................................................ 396 6.8 Simultaneous Channel Operation Function of Timer Array Unit .......................................... 401 6.8.1 Operation as one-shot pulse output function .................................................................................. 401 6.8.2 Operation as PWM function............................................................................................................ 408 6.8.3 Operation as multiple PWM output function ................................................................................... 415 6.9 Cautions When Using Timer Array Unit ................................................................................... 423 6.9.1 Cautions When Using Timer output................................................................................................ 423 CHAPTER 7 REAL-TIME CLOCK......................................................................................................... 424 7.1 Functions of Real-time Clock.................................................................................................... 424 7.2 Configuration of Real-time Clock ............................................................................................. 424 7.3 Registers Controlling Real-time Clock..................................................................................... 426 7.4 Real-time Clock Operation ........................................................................................................ 441 7.4.1 Starting operation of real-time clock ............................................................................................... 441 7.4.2 Shifting to HALT/STOP mode after starting operation.................................................................... 442 7.4.3 Reading/writing real-time clock....................................................................................................... 443 7.4.4 Setting alarm of real-time clock ...................................................................................................... 445 7.4.5 1 Hz output of real-time clock ......................................................................................................... 446 7.4.6 Example of watch error correction of real-time clock ...................................................................... 447 CHAPTER 8 12-BIT INTERVAL TIMER ................................................................................................ 450 8.1 Functions of 12-bit Interval Timer............................................................................................. 450 8.2 Configuration of 12-bit Interval Timer ...................................................................................... 450 8.3 Registers Controlling 12-bit Interval Timer.............................................................................. 451 8.4 12-bit Interval Timer Operation ................................................................................................. 454 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER................................................. 455 9.1 Functions of Clock Output/Buzzer Output Controller ............................................................ 455 9.2 Configuration of Clock Output/Buzzer Output Controller...................................................... 457 9.3 Registers Controlling Clock Output/Buzzer Output Controller ............................................. 457 9.4 Operations of Clock Output/Buzzer Output Controller .......................................................... 460 9.4.1 Operation as output pin .................................................................................................................. 460 9.5 Cautions of clock output/buzzer output controller................................................................. 460 Index-5 CHAPTER 10 WATCHDOG TIMER ..................................................................................................... 461 10.1 Functions of Watchdog Timer................................................................................................. 461 10.2 Configuration of Watchdog Timer .......................................................................................... 462 10.3 Register Controlling Watchdog Timer.................................................................................... 463 10.4 Operation of Watchdog Timer................................................................................................. 464 10.4.1 Controlling operation of watchdog timer ....................................................................................... 464 10.4.2 Setting overflow time of watchdog timer ....................................................................................... 465 10.4.3 Setting window open period of watchdog timer ............................................................................ 466 10.4.4 Setting watchdog timer interval interrupt ...................................................................................... 467 CHAPTER 11 A/D CONVERTER .......................................................................................................... 468 11.1 Function of A/D Converter....................................................................................................... 468 11.2 Configuration of A/D Converter .............................................................................................. 470 11.3 Registers Used in A/D Converter............................................................................................ 472 11.4 A/D Converter Conversion Operations .................................................................................. 494 11.5 Input Voltage and Conversion Results .................................................................................. 496 11.6 A/D Converter Operation Modes............................................................................................. 497 11.6.1 Software trigger mode (select mode, sequential conversion mode) ............................................. 497 11.6.2 Software trigger mode (select mode, one-shot conversion mode) ............................................... 498 11.6.3 Software trigger mode (scan mode, sequential conversion mode)............................................... 499 11.6.4 Software trigger mode (scan mode, one-shot conversion mode) ................................................. 500 11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) ............................... 501 11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode).................................. 502 11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ................................. 503 11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ................................... 504 11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) .................................... 505 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)..................................... 506 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) .................................... 507 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ...................................... 508 11.7 A/D Converter Setup Flowchart .............................................................................................. 509 11.7.1 Setting up software trigger mode.................................................................................................. 509 11.7.2 Setting up hardware trigger no-wait mode.................................................................................... 510 11.7.3 Setting up hardware trigger wait mode ......................................................................................... 511 11.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode) ........................................................................................................................ 512 11.7.5 Setting up test mode .................................................................................................................... 513 11.8 SNOOZE Mode Function.......................................................................................................... 514 11.9 How to Read A/D Converter Characteristics Table............................................................... 517 11.10 Cautions for A/D Converter ................................................................................................... 519 Index-6 CHAPTER 12 SERIAL ARRAY UNIT.................................................................................................. 523 12.1 Functions of Serial Array Unit................................................................................................. 525 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31)............................ 525 12.1.2 UART (UART0 to UART3)............................................................................................................ 526 12.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)........................................... 527 12.2 Configuration of Serial Array Unit .......................................................................................... 528 12.3 Registers Controlling Serial Array Unit.................................................................................. 534 12.4 Operation stop mode ............................................................................................................... 560 12.4.1 Stopping the operation by units .................................................................................................... 561 12.4.2 Stopping the operation by channels ............................................................................................. 562 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication ....................................................................................................................... 563 12.5.1 Master transmission ..................................................................................................................... 566 12.5.2 Master reception........................................................................................................................... 576 12.5.3 Master transmission/reception...................................................................................................... 585 12.5.4 Slave transmission ....................................................................................................................... 595 12.5.5 Slave reception............................................................................................................................. 605 12.5.6 Slave transmission/reception........................................................................................................ 612 12.5.7 SNOOZE mode function............................................................................................................... 622 12.5.8 Calculating transfer clock frequency............................................................................................. 626 12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication ................................................................. 628 12.6 Operation of UART (UART0 to UART3) Communication...................................................... 629 12.6.1 UART transmission ...................................................................................................................... 632 12.6.2 UART reception............................................................................................................................ 642 12.6.3 SNOOZE mode function............................................................................................................... 649 12.6.4 Calculating baud rate ................................................................................................................... 655 12.6.5 Procedure for processing errors that occurred during UART (UART0 to UART3) communication............................................................................................................................. 659 12.7 LIN Communication Operation ............................................................................................... 660 12.7.1 LIN transmission........................................................................................................................... 660 12.7.2 LIN reception ................................................................................................................................ 663 12.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication ....................................................................................................................... 669 12.8.1 Address field transmission............................................................................................................ 672 12.8.2 Data transmission......................................................................................................................... 678 12.8.3 Data reception .............................................................................................................................. 682 12.8.4 Stop condition generation............................................................................................................. 687 12.8.5 Calculating transfer rate ............................................................................................................... 688 12.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication .................................................................................. 690 Index-7 CHAPTER 13 SERIAL INTERFACE IICA ........................................................................................... 691 13.1 Functions of Serial Interface IICA........................................................................................... 691 13.2 Configuration of Serial Interface IICA .................................................................................... 694 13.3 Registers Controlling Serial Interface IICA............................................................................ 697 13.4 I2C Bus Mode Functions........................................................................................................... 711 13.4.1 Pin configuration........................................................................................................................... 711 13.4.2 Setting transfer clock by using IICWLn and IICWHn registers...................................................... 712 2 13.5 I C Bus Definitions and Control Methods .............................................................................. 714 13.5.1 Start conditions............................................................................................................................. 714 13.5.2 Addresses .................................................................................................................................... 715 13.5.3 Transfer direction specification..................................................................................................... 715 13.5.4 Acknowledge (ACK) ..................................................................................................................... 716 13.5.5 Stop condition............................................................................................................................... 717 13.5.6 Wait .............................................................................................................................................. 718 13.5.7 Canceling wait .............................................................................................................................. 720 13.5.8 Interrupt request (INTIICAn) generation timing and wait control................................................... 721 13.5.9 Address match detection method ................................................................................................. 722 13.5.10 Error detection............................................................................................................................ 722 13.5.11 Extension code........................................................................................................................... 722 13.5.12 Arbitration ................................................................................................................................... 723 13.5.13 Wakeup function......................................................................................................................... 725 13.5.14 Communication reservation........................................................................................................ 728 13.5.15 Cautions ..................................................................................................................................... 732 13.5.16 Communication operations......................................................................................................... 733 13.5.17 Timing of I2C interrupt request (INTIICAn) occurrence ............................................................... 740 13.6 Timing Charts ........................................................................................................................... 761 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR ......................................... 776 14.1 Functions of Multiplier and Divider/Multiply-Accumulator .................................................. 776 14.2 Configuration of Multiplier and Divider/Multiply-Accumulator............................................ 776 14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator ..................................... 782 14.4 Operations of Multiplier and Divider/Multiply-Accumulator ................................................ 784 14.4.1 Multiplication (unsigned) operation............................................................................................... 784 14.4.2 Multiplication (signed) operation................................................................................................... 785 14.4.3 Multiply-accumulation (unsigned) operation ................................................................................. 786 14.4.4 Multiply-accumulation (signed) operation ..................................................................................... 788 14.4.5 Division operation......................................................................................................................... 790 CHAPTER 15 DMA CONTROLLER ..................................................................................................... 792 15.1 Functions of DMA Controller .................................................................................................. 792 Index-8 15.2 Configuration of DMA Controller ............................................................................................ 793 15.3 Registers Controlling DMA Controller ................................................................................... 796 15.4 Operation of DMA Controller................................................................................................... 801 15.4.1 Operation procedure .................................................................................................................... 801 15.4.2 Transfer mode .............................................................................................................................. 802 15.4.3 Termination of DMA transfer ........................................................................................................ 802 15.5 Example of Setting of DMA Controller ................................................................................... 803 15.5.1 CSI consecutive transmission ...................................................................................................... 803 15.5.2 Consecutive capturing of A/D conversion results ......................................................................... 805 15.5.3 UART consecutive reception + ACK transmission........................................................................ 807 15.5.4 Holding DMA transfer pending by DWAITn bit ............................................................................. 809 15.5.5 Forced termination by software .................................................................................................... 810 15.6 Cautions on Using DMA Controller ........................................................................................ 812 CHAPTER 16 INTERRUPT FUNCTIONS............................................................................................. 814 16.1 Interrupt Function Types ......................................................................................................... 814 16.2 Interrupt Sources and Configuration ..................................................................................... 814 16.3 Registers Controlling Interrupt Functions............................................................................. 821 16.4 Interrupt Servicing Operations ............................................................................................... 834 16.4.1 Maskable interrupt request acknowledgmentv ............................................................................. 834 16.4.2 Software interrupt request acknowledgment ................................................................................ 837 16.4.3 Multiple interrupt servicing............................................................................................................ 837 16.4.4 Interrupt request hold ................................................................................................................... 841 CHAPTER 17 KEY INTERRUPT FUNCTION ..................................................................................... 842 17.1 Functions of Key Interrupt ...................................................................................................... 842 17.2 Configuration of Key Interrupt ................................................................................................ 842 17.3 Register Controlling Key Interrupt ......................................................................................... 844 CHAPTER 18 STANDBY FUNCTION .................................................................................................. 845 18.1 Standby Function and Configuration ..................................................................................... 845 18.1.1 Standby function........................................................................................................................... 845 18.1.2 Registers controlling standby function.......................................................................................... 846 18.2 Standby Function Operation ................................................................................................... 849 18.2.1 HALT mode .................................................................................................................................. 849 18.2.2 STOP mode.................................................................................................................................. 854 18.2.3 SNOOZE mode ............................................................................................................................ 859 CHAPTER 19 RESET FUNCTION........................................................................................................ 861 19.1 Register for Confirming Reset Source ................................................................................... 871 Index-9 CHAPTER 20 POWER-ON-RESET CIRCUIT ...................................................................................... 873 20.1 Functions of Power-on-reset Circuit ...................................................................................... 873 20.2 Configuration of Power-on-reset Circuit................................................................................ 874 20.3 Operation of Power-on-reset Circuit ...................................................................................... 874 20.4 Cautions for Power-on-reset Circuit....................................................................................... 877 CHAPTER 21 VOLTAGE DETECTOR .................................................................................................. 879 21.1 Functions of Voltage Detector ................................................................................................ 879 21.2 Configuration of Voltage Detector.......................................................................................... 880 21.3 Registers Controlling Voltage Detector ................................................................................. 880 21.4 Operation of Voltage Detector ................................................................................................ 885 21.4.1 When used as reset mode............................................................................................................ 885 21.4.2 When used as interrupt mode ...................................................................................................... 887 21.4.3 When used as interrupt and reset mode ...................................................................................... 889 21.5 Cautions for Voltage Detector................................................................................................. 895 CHAPTER 22 SAFETY FUNCTIONS ..................................................................................................... 897 22.1 Overview of Safety Functions ................................................................................................. 897 22.2 Registers Used by Safety Functions ...................................................................................... 898 22.3 Operation of Safety Functions ................................................................................................ 898 22.3.1 Flash memory CRC operation function (high-speed CRC)........................................................... 898 22.3.2 CRC operation function (general-purpose CRC) .......................................................................... 902 22.3.3 RAM parity error detection function .............................................................................................. 904 22.3.4 RAM guard function...................................................................................................................... 905 22.3.5 SFR guard function ...................................................................................................................... 906 22.3.6 Invalid memory access detection function .................................................................................... 907 22.3.7 Frequency detection function ....................................................................................................... 909 22.3.8 A/D test function ........................................................................................................................... 911 CHAPTER 23 REGULATOR ................................................................................................................. 915 23.1 Regulator Overview.................................................................................................................. 915 CHAPTER 24 OPTION BYTE............................................................................................................... 916 24.1 Functions of Option Bytes ...................................................................................................... 916 24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H)......................................................... 916 24.1.2 On-chip debug option byte (000C3H/ 010C3H)............................................................................ 917 24.2 Format of User Option Byte .................................................................................................... 918 24.3 Format of On-chip Debug Option Byte................................................................................... 922 24.4 Setting of Option Byte.............................................................................................................. 923 Index-10 CHAPTER 25 FLASH MEMORY .......................................................................................................... 924 25.1 Writing to Flash Memory by Using Flash Memory Programmer ......................................... 925 25.1.1 Programming Environment........................................................................................................... 927 25.1.2 Communication Mode .................................................................................................................. 927 25.2 Writing to Flash Memory by Using External Device (that Incorporates UART) ................. 928 25.2.1 Programming Environment........................................................................................................... 928 25.2.2 Communication Mode .................................................................................................................. 929 25.3 Connection of Pins on Board.................................................................................................. 930 25.3.1 P40/TOOL0 pin ............................................................................................................................ 930 25.3.2 RESET pin.................................................................................................................................... 930 25.3.3 Port pins ....................................................................................................................................... 931 25.3.4 REGC pin ..................................................................................................................................... 931 25.3.5 X1 and X2 pins ............................................................................................................................. 931 25.3.6 Power supply................................................................................................................................ 931 25.4 Data Flash ................................................................................................................................. 932 25.4.1 Data flash overview ...................................................................................................................... 932 25.4.2 Register controlling data flash memory ........................................................................................ 933 25.4.3 Procedure for accessing data flash memory ................................................................................ 934 25.5 Programming Method .............................................................................................................. 935 25.5.1 Controlling flash memory.............................................................................................................. 935 25.5.2 Flash memory programming mode............................................................................................... 936 25.5.3 Selecting communication mode.................................................................................................... 937 25.5.4 Communication commands .......................................................................................................... 938 25.5.5 Description of signature data........................................................................................................ 939 25.6 Security Settings ...................................................................................................................... 940 25.7 Flash Memory Programming by Self-Programming ............................................................. 942 25.7.1 Boot swap function ....................................................................................................................... 944 25.7.2 Flash shield window function........................................................................................................ 946 CHAPTER 26 ON-CHIP DEBUG FUNCTION ..................................................................................... 947 26.1 Connecting E1 On-chip Debugging Emulator to RL78/G13 ................................................. 947 26.2 On-Chip Debug Security ID ..................................................................................................... 948 26.3 Securing of User Resources ................................................................................................... 948 CHAPTER 27 BCD CORRECTION CIRCUIT ..................................................................................... 950 27.1 BCD Correction Circuit Function............................................................................................ 950 27.2 Registers Used by BCD Correction Circuit ........................................................................... 950 27.3 BCD Correction Circuit Operation .......................................................................................... 951 Index-11 CHAPTER 28 INSTRUCTION SET........................................................................................................ 953 28.1 Conventions Used in Operation List ...................................................................................... 954 28.1.1 Operand identifiers and specification methods............................................................................. 954 28.1.2 Description of operation column ................................................................................................... 955 28.1.3 Description of flag operation column ............................................................................................ 956 28.1.4 PREFIX instruction ....................................................................................................................... 956 28.2 Operation List ........................................................................................................................... 957 CHAPTER 29 ELECTRICAL SPECIFICATIONS ................................................................................. 974 29.1 Absolute Maximum Ratings .................................................................................................... 975 29.2 Oscillator Characteristics........................................................................................................ 977 29.2.1 X1, XT1 oscillator characteristics ................................................................................................. 977 29.2.2 On-chip oscillator characteristics.................................................................................................. 978 29.3 DC Characteristics ................................................................................................................... 979 29.3.1 Pin characteristics ........................................................................................................................ 979 29.3.2 Supply current characteristics ...................................................................................................... 984 29.4 AC Characteristics ................................................................................................................... 997 29.5 Peripheral Functions Characteristics................................................................................... 1000 29.5.1 Serial array unit .......................................................................................................................... 1000 29.5.2 Serial interface IICA ................................................................................................................... 1023 29.5.3 On-chip debug (UART)............................................................................................................... 1024 29.6 Analog Characteristics .......................................................................................................... 1024 29.6.1 A/D converter characteristics...................................................................................................... 1024 29.6.2 Temperature sensor characteristics ........................................................................................... 1028 29.6.3 POR circuit characteristics ......................................................................................................... 1028 29.6.4 LVD circuit characteristics .......................................................................................................... 1029 29.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics............. 1032 29.8 Flash Memory Programming Characteristics...................................................................... 1032 29.9 Timing Specs for Switching Flash Memory Programming Modes.................................... 1033 CHAPTER 30 PACKAGE DRAWINGS .............................................................................................. 1034 30.1 20-pin products....................................................................................................................... 1034 30.2 24-pin products....................................................................................................................... 1035 30.3 25-pin products....................................................................................................................... 1036 30.4 30-pin products....................................................................................................................... 1037 30.5 32-pin products....................................................................................................................... 1038 30.6 36-pin products....................................................................................................................... 1039 30.7 40-pin products....................................................................................................................... 1040 30.8 44-pin products....................................................................................................................... 1041 30.9 48-pin products....................................................................................................................... 1042 Index-12 30.10 52-pin products..................................................................................................................... 1044 30.11 64-pin products..................................................................................................................... 1045 30.12 80-pin products..................................................................................................................... 1048 30.13 100-pin products................................................................................................................... 1050 30.14 128-pin products................................................................................................................... 1052 APPENDIX A REVISION HISTORY ................................................................................................... 1053 A.1 Major Revisions in This Edition ............................................................................................. 1053 A.2 Revision History of Preceding Editions ................................................................................ 1062 Index-13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 RL78/G13 RENESAS MCU CHAPTER 1 OUTLINE 1.1 Features { Minimum instruction execution time can be changed from high speed (0.03125 s: @ 32 MHz operation with highspeed on-chip oscillator) to ultra low-speed (30.5 s: @ 32.768 kHz operation with subsystem clock) { General-purpose register: 8 bits x 32 registers (8 bits x 8 registers x 4 banks) { ROM: 16 to 512 KB, RAM: 2 to 32 KB, Data flash memory: -/4/8 KB { On-chip high-speed on-chip oscillator * Select from 32 MHz (TYP.), 24 MHz (TYP.), 16 MHz (TYP.), 12 MHz (TYP.), 8 MHz (TYP.), 4 MHz (TYP.), and 1 MHz (TYP.) { On-chip single-power-supply flash memory (with prohibition of block erase/writing function) { Self-programming (with boot swap function/flash shield window function) { On-chip debug function { On-chip power-on-reset (POR) circuit and voltage detector (LVD) { On-chip watchdog timer (operable with the dedicated low-speed on-chip oscillator) { On-chip multiplier and divider/multiply-accumulator * 16 bits x 16 bits = 32 bits (Unsigned or signed) * 32 bits / 32 bits = 32 bits (Unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) { On-chip key interrupt function { On-chip clock output/buzzer output controller { On-chip BCD adjustment { I/O ports: 16 to 120 (N-ch open drain: 0 to 4) { Timer * 16-bit timer: 8 to 16 channels * Watchdog timer: 1 channel * Real-time clock: 1 channel (Correction clock output) * 12-bit interval timer: 1 channel <R> { Serial interface * CSI: 2 to 4 channels * I C/Simplified I C communication: 2 to 8 channels 2 <R> 2 to 8 channels * UART/UART (LIN-bus supported): 2 { Different potential interface: Can connect to a 1.8/2.5/3 V device { 8/10-bit resolution A/D converter (VDD = EVDD =1.6 to 5.5 V): 6 to 26 channels { Standby function: HALT, STOP, SNOOZE mode { Power supply voltage: VDD = 1.6 to 5.5 V { Operating ambient temperature: TA = -40 to +85C Remarks 1. The functions mounted depend on the product. See 1.6 Outline of Functions. <R> 2. For details about extended-temperature products (operating ambient temperature: -40C to 105C), contact a Renesas Electronics Corporation or an authorized Renesas Electronics Corporation distributor. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1 RL78/G13 CHAPTER 1 OUTLINE { ROM, RAM capacities Flash Data ROM flash 128 8 KB KB RAM RL78/G13 20 pins 24 pins 25 pins 30 pins 32 pins 36 pins 12 - - - R5F100AG R5F100BG R5F100CG - KB - - - R5F101AG R5F101BG R5F101CG 96 8 KB 8 KB - - - R5F100AF R5F100BF R5F100CF KB - - - - R5F101AF R5F101BF R5F101CF 64 4 KB 4 KB R5F1006E R5F1007E R5F1008E R5F100AE R5F100BE R5F100CE KB - Note 1 R5F1016E R5F1017E R5F1018E R5F101AE R5F101BE R5F101CE 48 4 KB 3 KB R5F1006D R5F1007D R5F1008D R5F100AD R5F100BD R5F100CD KB - R5F1016D R5F1017D R5F1018D R5F101AD R5F101BD R5F101CD 32 4 KB R5F1006C R5F1007C R5F1008C R5F100AC R5F100BC R5F100CC KB - R5F1016C R5F1017C R5F1018C R5F101AC R5F101BC R5F101CC 16 4 KB R5F1006A R5F1007A R5F1008A R5F100AA R5F100BA R5F100CA KB - R5F1016A R5F1017A R5F1018A R5F101AA R5F101BA R5F101CA Flash Data ROM flash 512 8 KB KB 2 KB 2 KB RAM RL78/G13 40 pins 44 pins 48 pins 52 pins 64 pins 80 pins 100 pins 128 pins 32 KB - R5F100FL R5F100GL R5F100JL R5F100LL R5F100ML R5F100PL R5F100SL - Note 3 - R5F101FL R5F101GL R5F101JL R5F101LL R5F101ML R5F101PL R5F101SL 384 8 KB 24 KB - R5F100FK R5F100GK R5F100JK R5F100LK R5F100MK R5F100PK R5F100SK KB - - R5F101FK R5F101GK R5F101JK R5F101LK R5F101MK R5F101PK R5F101SK 256 8 KB 20 KB - R5F100FJ R5F100GJ R5F100JJ R5F100LJ R5F100MJ R5F100PJ R5F100SJ KB - Note 2 - R5F101FJ R5F101GJ R5F101JJ R5F101LJ R5F101MJ R5F101PJ R5F101SJ 192 8 KB 16 KB R5F100EH R5F100FH R5F100GH R5F100JH R5F100LH R5F100MH R5F100PH R5F100SH KB - R5F101EH R5F101FH R5F101GH R5F101JH R5F101LH R5F101MH R5F101PH R5F101SH 128 8 KB R5F100EG R5F100FG R5F100GG R5F100JG R5F100LG R5F100MG R5F100PG - KB - R5F101EG R5F101FG R5F101GG R5F101JG R5F101LG R5F101MG R5F101PG - 96 8 KB R5F100EF R5F100FF R5F100GF R5F100JF R5F100LF R5F100MF R5F100PF - KB - R5F101EF R5F101FF R5F101GF R5F101JF R5F101LF R5F101MF R5F101PF - 64 4 KB 4 KB R5F100EE R5F100FE R5F100GE R5F100JE R5F100LE - - - KB - Note 1 R5F101EE R5F101FE R5F101GE R5F101JE R5F101LE - - - 48 4 KB 3 KB R5F100ED R5F100FD R5F100GD R5F100JD R5F100LD - - - KB - R5F101ED R5F101FD R5F101GD R5F101JD R5F101LD - - - 32 4 KB R5F100EC R5F100FC R5F100GC R5F100JC R5F100LC - - - KB - R5F101EC R5F101FC R5F101GC R5F101JC R5F101LC - - - 16 4 KB R5F100EA R5F100FA R5F100GA - - - - - KB - R5F101EA R5F101FA R5F101GA - - - - - 12 KB 8 KB 2 KB 2 KB Notes 1. This is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) 2. This is about 19 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) 3. This is about 31 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 2 RL78/G13 CHAPTER 1 OUTLINE <R> 1.2 Ordering Information * Flash memory version (lead-free product) (1/4) Pin count 20 pins Package 20-pin plastic SSOP (7.62 mm Data flash Part Number Mounted R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP Not mounted R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP (300)) R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP 24 pins 24-pin plastic WQFN Mounted (fine pitch) (4 x 4) R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA Not mounted R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA 25 pins 25-pin plastic FLGA (3 x 3) Mounted R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA R5F1008ADLA, R5F1008CDLA, R5F1008DDLA, R5F1008EDLA Not mounted R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA R5F1018ADLA, R5F1018CDLA, R5F1018DDLA, R5F1018EDLA 30 pins 30-pin plastic SSOP Mounted R5F100AAASP, R5F100ACASP, R5F100ADASP, R5F100AEASP, R5F100AFASP, R5F100AGASP (7.62 mm (300)) R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP, R5F100AFDSP, R5F100AGDSP Not mounted R5F101AAASP, R5F101ACASP, R5F101ADASP, R5F101AEASP, R5F101AFASP, R5F101AGASP R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP, R5F101AFDSP, R5F101AGDSP 32 pins 32-pin plastic WQFN Mounted (fine pitch)(5 x 5) R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA, R5F100BFANA, R5F100BGANA R5F100BADNA, R5F100BCDNA, R5F100BDDNA, R5F100BEDNA, R5F100BFDNA, R5F100BGDNA Not mounted R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA, R5F101BFANA, R5F101BGANA R5F101BADNA, R5F101BCDNA, R5F101BDDNA, R5F101BEDNA, R5F101BFDNA, R5F101BGDNA 36 pins 36-pin plastic FLGA (4 x 4) Mounted R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA, R5F100CFALA, R5F100CGALA R5F100CADLA, R5F100CCDLA, R5F100CDDLA, R5F100CEDLA, R5F100CFDLA, R5F100CGDLA Not mounted R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA, R5F101CFALA, R5F101CGALA R5F101CADLA, R5F101CCDLA, R5F101CDDLA, R5F101CEDLA, R5F101CFDLA, R5F101CGDLA R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 3 RL78/G13 CHAPTER 1 OUTLINE (2/4) Pin count 40 pins Package 40-pin plastic WQFN Data flash Mounted (fine pitch)(6 x 6) Part Number R5F100EAANA, R5F100ECANA, R5F100EDANA, R5F100EEANA, R5F100EFANA, R5F100EGANA, R5F100EHANA R5F100EADNA, R5F100ECDNA, R5F100EDDNA, R5F100EEDNA, R5F100EFDNA, R5F100EGDNA, R5F100EHDNA Not mounted R5F101EAANA, R5F101ECANA, R5F101EDANA, R5F101EEANA, R5F101EFANA, R5F101EGANA, R5F101EHANA R5F101EADNA, R5F101ECDNA, R5F101EDDNA, R5F101EEDNA, R5F101EFDNA, R5F101EGDNA, R5F101EHDNA 44 pins 44-pin plastic LQFP (10 x 10) Mounted R5F100FAAFP, R5F100FCAFP, R5F100FDAFP, R5F100FEAFP, R5F100FFAFP, R5F100FGAFP, R5F100FHAFP, R5F100FJAFP, R5F100FKAFP, R5F100FLAFP R5F100FADFP, R5F100FCDFP, R5F100FDDFP, R5F100FEDFP, R5F100FFDFP, R5F100FGDFP, R5F100FHDFP, R5F100FJDFP, R5F100FKDFP, R5F100FLDFP Not mounted R5F101FAAFP, R5F101FCAFP, R5F101FDAFP, R5F101FEAFP, R5F101FFAFP, R5F101FGAFP, R5F101FHAFP, R5F101FJAFP, R5F101FKAFP, R5F101FLAFP R5F101FADFP, R5F101FCDFP, R5F101FDDFP, R5F101FEDFP, R5F101FFDFP, R5F101FGDFP, R5F101FHDFP, R5F101FJDFP, R5F101FKDFP, R5F101FLDFP 48 pins 48-pin plastic LQFP Mounted (fine pitch) (7 x 7) R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, R5F100GEAFB, R5F100GFAFB, R5F100GGAFB, R5F100GHAFB, R5F100GJAFB, R5F100GKAFB, R5F100GLAFB R5F100GADFB, R5F100GCDFB, R5F100GDDFB, R5F100GEDFB, R5F100GFDFB, R5F100GGDFB, R5F100GHDFB, R5F100GJDFB, R5F100GKDFB, R5F100GLDFB Not mounted R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB, R5F101GFAFB, R5F101GGAFB, R5F101GHAFB, R5F101GJAFB, R5F101GKAFB, R5F101GLAFB R5F101GADFB, R5F101GCDFB, R5F101GDDFB, R5F101GEDFB, R5F101GFDFB, R5F101GGDFB, R5F101GHDFB, R5F101GJDFB, R5F101GKDFB, R5F101GLDFB 48-pin plastic WQFN (7 x 7) Mounted R5F100GAANA, R5F100GCANA, R5F100GDANA, R5F100GEANA, R5F100GFANA, R5F100GGANA, R5F100GHANA, R5F100GJANA, R5F100GKANA, R5F100GLANA R5F100GADNA, R5F100GCDNA, R5F100GDDNA, R5F100GEDNA, R5F100GFDNA, R5F100GGDNA, R5F100GHDNA, R5F100GJDNA, R5F100GKDNA, R5F100GLDNA Not mounted R5F101GAANA, R5F101GCANA, R5F101GDANA, R5F101GEANA, R5F101GFANA, R5F101GGANA, R5F101GHANA, R5F101GJANA, R5F101GKANA, R5F101GLANA R5F101GADNA, R5F101GCDNA, R5F101GDDNA, R5F101GEDNA, R5F101GFDNA, R5F101GGDNA, R5F101GHDNA, R5F101GJDNA, R5F101GKDNA, R5F101GLDNA R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 4 RL78/G13 CHAPTER 1 OUTLINE (3/4) Pin count 52 pins Package 52-pin plastic LQFP (10 x 10) Data flash Mounted Part Number R5F100JCAFA, R5F100JDAFA, R5F100JEAFA, R5F100JFAFA, R5F100JGAFA, R5F100JHAFA, R5F100JJAFA, R5F100JKAFA, R5F100JLAFA R5F100JCDFA, R5F100JDDFA, R5F100JEDFA, R5F100JFDFA, R5F100JGDFA, R5F100JHDFA, R5F100JJDFA, R5F100JKDFA, R5F100JLDFA Not mounted R5F101JCAFA, R5F101JDAFA, R5F101JEAFA, R5F101JFAFA, R5F101JGAFA, R5F101JHAFA, R5F101JJAFA, R5F101JKAFA, R5F101JLAFA R5F101JCDFA, R5F101JDDFA, R5F101JEDFA, R5F101JFDFA, R5F101JGDFA, R5F101JHDFA, R5F101JJDFA, R5F101JKDFA, R5F101JLDFA 64 pins 64-pin plastic LQFP (12 x 12) Mounted R5F100LCAFA, R5F100LDAFA, R5F100LEAFA, R5F100LFAFA, R5F100LGAFA, R5F100LHAFA, R5F100LJAFA, R5F100LKAFA, R5F100LLAFA R5F100LCDFA, R5F100LDDFA, R5F100LEDFA, R5F100LFDFA, R5F100LGDFA, R5F100LHDFA, R5F100LJDFA, R5F100LKDFA, R5F100LLDFA Not mounted R5F101LCAFA, R5F101LDAFA, R5F101LEAFA, R5F101LFAFA, R5F101LGAFA, R5F101LHAFA, R5F101LJAFA, R5F101LKAFA, R5F101LLAFA R5F101LCDFA, R5F101LDDFA, R5F101LEDFA, R5F101LFDFA, R5F101LGDFA, R5F101LHDFA, R5F101LJDFA, R5F101LKDFA, R5F101LLDFA 64-pin plastic LQFP (fine pitch) Mounted (10 x 10) R5F100LCAFB, R5F100LDAFB, R5F100LEAFB, R5F100LFAFB, R5F100LGAFB, R5F100LHAFB, R5F100LJAFB, R5F100LKAFB, R5F100LLAFB R5F100LCDFB, R5F100LDDFB, R5F100LEDFB, R5F100LFDFB, R5F100LGDFB, R5F100LHDFB, R5F100LJDFB, R5F100LKDFB, R5F100LLDFB Not mounted R5F101LCAFB, R5F101LDAFB, R5F101LEAFB, R5F101LFAFB, R5F101LGAFB, R5F101LHAFB, R5F101LJAFB, R5F101LKAFB, R5F101LLAFB R5F101LCDFB, R5F101LDDFB, R5F101LEDFB, R5F101LFDFB, R5F101LGDFB, R5F101LHDFB, R5F101LJDFB, R5F101LKDFB, R5F101LLDFB 64-pin plastic FBGA (4 x 4) Mounted R5F100LCABG, R5F100LDABG, R5F100LEABG, R5F100LFABG, R5F100LGABG, R5F100LHABG, R5F100LJABG R5F100LCDBG, R5F100LDDBG, R5F100LEDBG, R5F100LFDBG, R5F100LGDBG, R5F100LHDBG, R5F100LJDBG Not mounted R5F101LCABG, R5F101LDABG, R5F101LEABG, R5F101LFABG, R5F101LGABG, R5F101LHABG, R5F101LJABG R5F101LCDBG, R5F101LDDBG, R5F101LEDBG, R5F101LFDBG, R5F101LGDBG, R5F101LHDBG, R5F101LJDBG R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 5 RL78/G13 CHAPTER 1 OUTLINE (4/4) Pin count 80 pins Package 80-pin plastic LQFP (14 x 14) Data flash Mounted Part Number R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA R5F100MFDFA, R5F100MGDFA, R5F100MHDFA, R5F100MJDFA, R5F100MKDFA, R5F100MLDFA Not mounted R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA R5F101MFDFA, R5F101MGDFA, R5F101MHDFA, R5F101MJDFA, R5F101MKDFA, R5F101MLDFA 80-pin plastic LQFP (fine pitch) Mounted (12 x 12) R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB, R5F100MKAFB, R5F100MLAFB R5F100MFDFB, R5F100MGDFB, R5F100MHDFB, R5F100MJDFB, R5F100MKDFB, R5F100MLDFB Not mounted R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB, R5F101MKAFB, R5F101MLAFB R5F101MFDFB, R5F101MGDFB, R5F101MHDFB, R5F101MJDFB, R5F101MKDFB, R5F101MLDFB 100 pins 100-pin plastic LQFP (fine pitch) Mounted (14 x 14) R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB, R5F100PKAFB, R5F100PLAFB R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB, R5F100PKDFB, R5F100PLDFB Not mounted R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB, R5F101PKAFB, R5F101PLAFB R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB, R5F101PKDFB, R5F101PLDFB 100-pin plastic LQFP (14 x 20) Mounted R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA, R5F100PKAFA, R5F100PLAFA R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA, R5F100PKDFA, R5F100PLDFA Not mounted R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA, R5F101PKAFA, R5F101PLAFA R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA, R5F101PKDFA, R5F101PLDFA 128 pins 128-pin plastic LQFP (fine pitch) Mounted R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB Not mounted R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB (14 x 20) R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 6 RL78/G13 <R> CHAPTER 1 OUTLINE Figure 1-1. Part Number, Memory Size, and Package of RL78/G13 Part No. R 5 F 1 0 0 L E A x x x F B Package type: SP : SSOP, 0.65 mm pitch FP : LQFP, 0.80 mm pitch FA : LQFP, 0.65 mm pitch FB : LQFP, 0.50 mm pitch NA : WQFN, 0.50 mm pitch LA : LGA, 0.50 mm pitch BG : FBGA, 0.40 mm pitch ROM number (Omitted with blank products) Classification: A : Consumer applications, operating ambient temperature : -40C to 85C D : Industrial applications, operating ambient temperature : -40C to 85C ROM capacity: A : 16 KB C : 32 KB D : 48 KB E : 64 KB F : 96 KB G : 128 KB H : 192 KB J : 256 KB K : 384 KB L : 512 KB Pin count: A : B : C : E : F : G: J : L : M: P : S : 20 to 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin 64-pin 80-pin 100-pin 128-pin RL78/G13 group 100 : Data flash is provided 101 : Data flash is not provided Memory type: F : Flash memory Renesas MCU Renesas semiconductor product Remark For details about extended-temperature products (operating ambient temperature: -40C to 105C), contact a Renesas Electronics Corporation or an authorized Renesas Electronics Corporation distributor. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 7 RL78/G13 CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 20-pin products * 20-pin plastic SSOP (7.62 mm (300)) P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P147/ANI18 P10/SCK00/SCL00 P11/SI00/RxD0/TOOLRxD/SDA00 P12/SO00/TxD0/TOOLTxD P16/TI01/TO01/INTP5/SO11 P17/TI02/TO02/SI11/SDA11 P30/INTP3/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remark For pin identification, see 1.4 Pin Identification. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 8 RL78/G13 CHAPTER 1 OUTLINE 1.3.2 24-pin products P22/ANI2 P147/ANI18 P10/SCK00/SCL00 P11/SI00/RxD0/TOOLRxD/SDA00 P12/SO00/TxD0/TOOLTxD P16/TI01/TO01/INTP5 * 24-pin plastic WQFN (fine pitch) (4 x 4) exposed die pad 18 17 16 15 14 13 19 12 20 11 21 10 22 9 23 8 24 7 1 2 3 4 5 6 P17/TI02/TO02/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 P31/TI03/TO03/INTP4/PCLBUZ0 P61/SDAA0 P60/SCLA0 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P40/TOOL0 RESET Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remark For pin identification, see 1.4 Pin Identification. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 9 RL78/G13 CHAPTER 1 OUTLINE 1.3.3 25-pin products * 25-pin plastic FLGA (3 x 3) Bottom View Top View 5 4 3 2 1 A B C D E E A B RESET 5 4 P122/X2/ EXCLK P137/INTP0 P121/X1 VDD 3 REGC VSS 2 P60/SCLA0 P61/SDAA0 1 A B C B A INDEX MARK INDEX MARK P40/TOOL0 D C D E P01/ANI16/ TO00/RxD1 P22/ANI2 P147/ANI18 P00/ANI17/ TI00/TxD1 P21/ANI1/ AVREFM P10/SCK00/ SCL00 P20/ANI0/ AVREFP P12/SO00/ TxD0/ TOOLTxD P11/SI00/ RxD0/ TOOLRxD/ SDA00 P30/INTP3/ SCK11/SCL11 P17/TI02/ TO02/SO11 P50/INTP1/ SI11/SDA11 P31/TI03/ TO03/INTP4/ PCLBUZ0 P16/TI01/ TO01/INTP5 P130 5 C D 4 3 2 1 E Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remark For pin identification, see 1.4 Pin Identification. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 10 RL78/G13 CHAPTER 1 OUTLINE 1.3.4 30-pin products * 30-pin plastic SSOP (7.62 mm (300)) P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P120/ANI19 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P147/ANI18 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 11 RL78/G13 CHAPTER 1 OUTLINE 1.3.5 32-pin products P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) * 32-pin plastic WQFN (5 x 5) exposed die pad 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 1 2 3 4 5 6 7 8 P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 P70 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P147/ANI18 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P120/ANI19 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 12 RL78/G13 CHAPTER 1 OUTLINE 1.3.6 36-pin products * 36-pin plastic FLGA (4 x 4) Top View Bottom View 6 5 4 3 2 1 A B C D E F F E D C B A INDEX MARK A P60/SCLA0 B VDD C P121/X1 D P122/X2/EXCLK E P137/INTP0 F P40/TOOL0 6 6 P62 P61/SDAA0 VSS REGC RESET P120/ANI19 5 5 P72/SO21 P71/SI21/ SDA21 P14/RxD2/SI20/ SDA20/(SCLA0) /(TI03)/(TO03) P31/TI03/TO03/ INTP4/ PCLBUZ0 P00/TI00/TxD1 P50/INTP1/ SI11/SDA11 P70/SCK21/ SCL21 P15/PCLBUZ1/ SCK20/SCL20/ (TI02)/(TO02) P22/ANI2 P20/ANI0/ AVREFP P21/ANI1/ AVREFM P30/INTP3/ SCK11/SCL11 P16/TI01/TO01/ INTP5/(RxD0) P12/SO00/ TxD0/TOOLTxD /(TI05)/(TO05) P11/SI00/RxD0/ TOOLRxD/ SDA00/(TI06)/ (TO06) P24/ANI4 P23/ANI3 P51/INTP2/ SO11 P17/TI02/TO02/ (TxD0) P13/TxD2/ SO20/(SDAA0)/ (TI04)/(TO04) P10/SCK00/ SCL00/(TI07)/ (TO07) P147/ANI18 B C 4 3 2 1 A D P01/TO00/RxD1 4 3 2 P25/ANI5 1 E F Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 13 RL78/G13 CHAPTER 1 OUTLINE 1.3.7 40-pin products P147/ANI18 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 * 40-pin plastic WQFN (6 x 6) 30 29 28 27 26 25 24 23 22 21 31 20 exposed die pad 32 19 33 18 34 17 35 16 36 15 37 14 38 13 39 12 40 11 1 2 3 4 5 6 7 8 9 10 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0 P62 P61/SDAA0 P60/SCLA0 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1 P00/TI00/TxD1 P120/ANI19 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 14 RL78/G13 CHAPTER 1 OUTLINE 1.3.8 44-pin products P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 * 44-pin plastic LQFP (10 x 10) 33 32 31 30 29 28 27 26 25 24 23 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 P50/INTP1/SI11/SDA11 P30/INTP3/RTC1HZ/SCK11/SCL11 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P31/TI03/TO03/INTP4/PCLBUZ0 P63 P62 P61/SDAA0 P60/SCLA0 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P01/TO00/RxD1 P00/TI00/TxD1 P120/ANI19 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 15 RL78/G13 CHAPTER 1 OUTLINE 1.3.9 48-pin products P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 * 48-pin plastic LQFP (fine pitch) (7 x 7) 36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 22 39 21 40 20 41 19 42 18 43 17 44 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK11/SCL11 P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 16 RL78/G13 CHAPTER 1 OUTLINE P140/PCLBUZ0/INTP6 P00/TI00/TxD1 P01/TO00/RxD1 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 * 48-pin plastic WQFN (7 x 7) 36 35 34 33 32 31 30 29 28 27 26 25 37 24 38 23 exposed die pad 39 22 40 21 41 20 42 19 43 18 44 17 45 16 46 15 47 14 48 13 1 2 3 4 5 6 7 8 9 10 11 12 P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(RXD0) P17/TI02/TO02/(TXD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P60/SCLA0 P61/SDAA0 P62 P63 P31/TI03/TO03/INTP4/(PCLBUZ0) P75/KR5/INTP9/SCK01/SCL01 P74/KR4/INTP8/SI01/SDA01 P73/KR3/SO01 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P30/INTP3/RTC1HZ/SCK11/SCL11 P120/ANI19 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 17 RL78/G13 CHAPTER 1 OUTLINE 1.3.10 52-pin products P30/INTP3/RTC1HZ/SCK11/SCL11 P50/INTP1/SI11/SDA11 P51/INTP2/SO11 P17/TI02/TO02/(TXD0) P16/TI01/TO01/INTP5/(RXD0) P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P10/SCK00/SCL00/(TI07)/(TO07) P146 P147/ANI18 * 52-pin plastic LQFP (10 x 10) 39 38 37 36 35 34 33 32 31 30 29 28 27 P71/KR1/SI21/SDA21 P25/ANI5 42 24 P72/KR2/SO21 P24/ANI4 43 23 P73/KR3/SO01 P23/ANI3 44 22 P74/KR4/INTP8/SI01/SDA01 P22/ANI2 45 21 P75/KR5/INTP9/SCK01/SCL01 P21/ANI1/AVREFM 46 20 P76/KR6/INTP10/(RXD2) P20/ANI0/AVREFP 47 19 P77/KR7/INTP11/(TXD2) P130 48 18 P31/TI03/TO03/INTP4/(PCLBUZ0) P03/ANI16/RxD1 49 17 P63 P02/ANI17/TxD1 50 16 P62 P01/TO00 51 15 P61/SDAA0 52 14 P60/SCLA0 VDD 8 9 10 11 12 13 VSS 6 7 REGC 5 P121/X1 3 4 P122/X2/EXCLK 2 P123/XT1 1 P40/TOOL0 P00/TI00 P137/INTP0 25 P124/XT2/EXCLKS 41 RESET P70/KR0/SCK21/SCL21 P26/ANI6 P41/TI07/TO07 26 P120/ANI19 40 P140/PCLBUZ0/INTP6 P27/ANI7 Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 18 RL78/G13 CHAPTER 1 OUTLINE 1.3.11 64-pin products * 64-pin plastic LQFP (12 x 12) P147/ANI18 P146 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00) P54 P53/(INTP11) P52/(INTP10) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 * 64-pin plastic LQFP (fine pitch) (10 x 10) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 P30/INTP3/RTC1HZ/SCK11/SCL11 P05/TI05/TO05 P06/TI06/TO06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3/SO01 P74/KR4/INTP8/SI01/SDA01 P75/KR5/INTP9/SCK01/SCL01 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P31/TI03/TO03/INTP4/(PCLBUZ0) P63 P62 P61/SDAA0 P60/SCLA0 6 7 8 9 10 11 12 13 14 15 16 P120/ANI19 P43 P42/TI04/TO04 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 <R> Cautions 1. Make EVSS0 pin the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 19 RL78/G13 CHAPTER 1 OUTLINE * 64-pin plastic FBGA (4 x 4) Top View Bottom View 8 7 6 5 4 3 2 1 A B C D E F G H H G F E D C B A Index mark Pin No. Name Pin No. Name Pin No. Name Pin No. Name A1 P05/TI05/TO05 C1 P51/INTP2/SO11 E1 P13/TxD2/SO20/ G1 (SDAA0)/(TI04)/(TO04) P146 A2 P30/INTP3/RTC1HZ /SCK11/SCL11 C2 P71/KR1/SI21/SDA21 E2 P14/RxD2/SI20/SDA20 G2 /(SCLA0)/(TI03)/(TO03) P25/ANI5 A3 P70/KR0/SCK21 /SCL21 C3 P74/KR4/INTP8/SI01 /SDA01 E3 P15/SCK20/SCL20/ (TI02)/(TO02) G3 P24/ANI4 A4 P75/KR5/INTP9 /SCK01/SCL01 C4 P52/(INTP10) E4 P16/TI01/TO01/INTP5 G4 /(SI00)/(RxD0) P22/ANI2 A5 P77/KR7/INTP11/ (TxD2) C5 P53/(INTP11) E5 P03/ANI16/SI10/RxD1 G5 /SDA10 P130 A6 P61/SDAA0 C6 P63 E6 P41/TI07/TO07 G6 P02/ANI17/SO10/TxD1 A7 P60/SCLA0 C7 VSS E7 RESET G7 P00/TI00 A8 EVDD0 C8 P121/X1 E8 P137/INTP0 G8 P124/XT2/EXCLKS B1 P50/INTP1/SI11 /SDA11 D1 P55/(PCLBUZ1)/ (SCK00) F1 P10/SCK00/SCL00/ (TI07)/(TO07) H1 P147/ANI18 B2 P72/KR2/SO21 D2 P06/TI06/TO06 F2 P11/SI00/RxD0 /TOOLRxD/SDA00/ (TI06)/(TO06) H2 P27/ANI7 B3 P73/KR3/SO01 D3 P17/TI02/TO02/ (SO00)/(TxD0) F3 P12/SO00/TxD0 /TOOLTxD/(INTP5)/ H3 P26/ANI6 (TI05)/(TO05) B4 P76/KR6/INTP10/ (RxD2) D4 P54 F4 P21/ANI1/AVREFM H4 P23/ANI3 B5 P31/TI03/TO03 /INTP4/(PCLBUZ0) D5 P42/TI04/TO04 F5 P04/SCK10/SCL10 H5 P20/ANI0/AVREFP B6 P62 D6 P40/TOOL0 F6 P43 H6 P141/PCLBUZ1/INTP7 B7 VDD D7 REGC F7 P01/TO00 H7 P140/PCLBUZ0/INTP6 B8 EVSS0 D8 P122/X2/EXCLK F8 P123/XT1 H8 P120/ANI19 Cautions 1. Make EVSS0 pin the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 20 RL78/G13 CHAPTER 1 OUTLINE 1.3.12 80-pin products * 80-pin plastic LQFP (14 x 14) P153/ANI11 P100/ANI20 P147/ANI18 P146 P111/(INTP11) P110/(INTP10) P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/INTP2/SO11 P50/INTP1/SI11/SDA11 * 80-pin plastic LQFP (fine pitch) (12 x 12) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 P142/SCK30/SCL30 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 P30/INTP3/RTC1HZ/SCK11/SCL11 P05/TI05/TO05 P06/TI06/TO06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P61/SDAA0 P60/SCLA0 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41/TI07/TO07 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Cautions 1. Make EVSS0 pin the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0 pin. 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 21 RL78/G13 CHAPTER 1 OUTLINE 1.3.13 100-pin products P100/ANI20 P147/ANI18 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO11 P50/SI11/SDA11 EVDD1 P30/INTP3/RTC1HZ/SCK11/SCL11 P87/(INTP9) * 100-pin plastic LQFP (fine pitch) (14 x 14) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 38 88 37 89 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 28 98 27 99 26 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TXD1) P81/(SI10)/(RXD1)/(SDA10) P80/(SCK10)/(SCL10) EVSS1 P05 P06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P102/TI06/TO06 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 22 RL78/G13 CHAPTER 1 OUTLINE P140/PCLBUZ0/INTP6 P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 P143/SI30/RxD3/SDA30 P144/SO30/TxD3 P145/TI07/TO07 P00/TI00 P01/TO00 P02/ANI17/SO10/TxD1 P03/ANI16/SI10/RxD1/SDA10 P04/SCK10/SCL10 P102/TI06/TO06 P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 P150/ANI8 P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 P100/ANI20 P147/ANI18 * 100-pin plastic LQFP (14 x 20) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51/SO11 P50/SI11/SDA11 P60/SCLA0 P61/SDAA0 P62/SCLA1 P63/SDAA1 P31/TI03/TO03/INTP4/(PCLBUZ0) P64/TI10/TO10 P65/TI11/TO11 P66/TI12/TO12 P67/TI13/TO13 P77/KR7/INTP11/(TXD2) P76/KR6/INTP10/(RXD2) P75/KR5/INTP9 P74/KR4/INTP8 P73/KR3 P72/KR2/SO21 P71/KR1/SI21/SDA21 P70/KR0/SCK21/SCL21 P06 P05 EVSS1 P80/(SCK10)/(SCL10) P81/(SI10)/(RXD1)/(SDA10) P82/(SO10)/(TXD1) P83 P84/(INTP6) P85/(INTP7) P86/(INTP8) P87/(INTP9) P30/INTP3/RTC1HZ/SCK11/SCL11 EVDD1 P120/ANI19 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 23 RL78/G13 CHAPTER 1 OUTLINE 1.3.14 128-pin products P100/ANI20 P147/ANI18 P146/(INTP4) P111/(INTP11) P110/(INTP10) P101 P117/ANI24 P116/ANI25 P115/ANI26 P114 P113 P112 P97/SO11 P96/SI11/SDA11 P95/SCK11/SCL11 P94 P93 P92 P91 P90 P10/SCK00/SCL00/(TI07)/(TO07) P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06) P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05) P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04) P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/(TO02) P16/TI01/TO01/INTP5/(SI00)/(RXD0) P17/TI02/TO02/(SO00)/(TXD0) P57/(INTP3) P56/(INTP1) P55/(PCLBUZ1)/(SCK00) P54/SCK31/SCL31 P53/SI31/SDA31 P52/SO31 P51 P50 P30/INTP3/RTC1HZ P87/(INTP9) * 128-pin plastic LQFP (fine pitch) (14 x 20) 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 64 104 63 105 62 106 61 107 60 108 59 109 58 110 57 111 56 112 55 113 54 114 53 115 52 51 116 50 117 49 118 48 119 47 120 46 121 45 122 44 123 43 124 42 125 41 126 40 127 39 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P86/(INTP8) P85/(INTP7) P84/(INTP6) P83 P82/(SO10)/(TXD1) P81/(SI10)/(RXD1)/(SDA10) P80/(SCK10)/(SCL10) EVDD1 EVSS1 P05 P06 P70/KR0/SCK21/SCL21 P71/KR1/SI21/SDA21 P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RXD2) P77/KR7/INTP11/(TXD2) P67/TI13/TO13 P66/TI12/TO12 P65/TI11/TO11 P64/TI10/TO10 P31/TI03/TO03/INTP4/(PCLBUZ0) P63/SDAA1 P62/SCLA1 P142/SCK30/SCL30 P141/PCLBUZ1/INTP7 P140/PCLBUZ0/INTP6 P120/ANI19 P37/ANI21 P36/ANI22 P35/ANI23 P34 P33 P32 P106/TI17/TO17 P105/TI16/TO16 P104/TI15/TO15 P103/TI14/TO14 P47/INTP2 P46/INTP1/TI05/TO05 P45/SO01 P44/SI01/SDA01 P43/SCK01/SCL01 P42/TI04/TO04 P41 P40/TOOL0 P127 P126 P125 RESET P124/XT2/EXCLKS P123/XT1 P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0 VDD EVDD0 P60/SCLA0 P61/SDAA0 P156/ANI14 P155/ANI13 P154/ANI12 P153/ANI11 P152/ANI10 P151/ANI9 P150/ANI8 P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P130 P102/TI06/TO06 P07 P04/SCK10/SCL10 P03/ANI16/SI10/RxD1/SDA10 P02/ANI17/SO10/TxD1 P01/TO00 P00/TI00 P145/TI07/TO07 P144/SO30/TxD3 P143/SI30/RxD3/SDA30 Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin. 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1). 3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.4 Pin Identification. 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines. 3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 24 RL78/G13 CHAPTER 1 OUTLINE 1.4 Pin Identification REGC: ANI0 to ANI14, Regulator capacitance ANI16 to ANI26: Analog input RESET: Reset AVREFM: A/D converter reference RTC1HZ: Real-time clock correction clock (1 Hz) output potential (- side) input AVREFP: A/D converter reference RxD0 to RxD3: potential (+ side) input SCK00, SCK01, SCK10, EVDD0, EVDD1: Power supply for port SCK11, SCK20, SCK21, EVSS0, EVSS1: Ground for port SCK30, SCK31: EXCLK: External clock input (Main SCLA0, SCLA1, SCL00, EXCLKS: system clock) SCL01, SCL10, SCL11, External clock input SCL20,SCL21, SCL30, Receive data Serial clock input/output (Subsystem clock) SCL31: INTP0 to INTP11: External interrupt input SDAA0, SDAA1, SDA00, KR0 to KR7: Key return SDA01,SDA10, SDA11, P00 to P07: Port 0 SDA20,SDA21, SDA30, P10 to P17: Port 1 SDA31: P20 to P27: Port 2 SI00, SI01, SI10, SI11, P30 to P37: Port 3 SI20, SI21, SI30, SI31: P40 to P47: Port 4 SO00, SO01, SO10, P50 to P57: Port 5 SO11, SO20, SO21, P60 to P67: Port 6 SO30, SO31: P70 to P77: Port 7 TI00 to TI07, P80 to P87: Port 8 TI10 to TI17: P90 to P97: Port 9 TO00 to TO07, P100 to P106: Port 10 TO10 to TO17: P110 to P117: Port 11 TOOL0: Data input/output for tool P120 to P127: Port 12 TOOLRxD, TOOLTxD: Data input/output for external device P130, P137: Port 13 TxD0 to TxD3: Transmit data P140 to P147: Port 14 VDD: Power supply P150 to P156: Port 15 VSS: Ground X1, X2: Crystal oscillator (main system clock) XT1, XT2: Crystal oscillator (subsystem clock) PCLBUZ0, PCLBUZ1: Programmable clock output/buzzer output R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Serial clock output Serial data input/output Serial data input Serial data output Timer input Timer output 25 RL78/G13 CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.1 20-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 5 P10 to P12, P16, P17 TI01/TO01/P16 ch1 PORT 2 3 P20 to P22 TI02/TO02/P17 ch2 PORT 3 P30 PORT 4 P40 ch3 ch4 PORT 12 ch5 <R> P121, P122 ch6 PORT 13 P137 ch7 PORT 14 P147 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR 2 RL78 CPU CORE CODE FLASH MEMORY DATA FLASH MEMORY A/D CONVERTER 3 ANI0/P20 to ANI2/P22 3 ANI16/P01, ANI17/P00, ANI18/P147 AVREFP/P20 AVREFM/P21 12-BIT INTERVAL TIMER POWER ON RESET/ VOLTAGE DETECTOR REAL-TIME CLOCK POR/LVD CONTROL RAM SERIAL ARRAY UNIT0 (4ch) RxD0/P11 TxD0/P12 UART0 RxD1/P01 TxD1/P00 UART1 RESET CONTROL ON-CHIP DEBUG VDD VSS TOOLRxD/P11, TOOLTxD/P12 SYSTEM CONTROL HIGH-SPEED ON-CHIP SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P17 SO11/P16 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P17 IIC11 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CRC OSCILLATOR VOLTAGE REGULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT TOOL0/P40 RESET X1/P121 X2/EXCLK/P122 REGC INTP0/P137 INTERRUPT CONTROL INTP3/P30 INTP5/P16 26 RL78/G13 CHAPTER 1 OUTLINE 1.5.2 24-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 5 P10 to P12, P16, P17 TI01/TO01/P16 ch1 PORT 2 3 P20 to P22 TI02/TO02/P17 ch2 PORT 3 2 P30, P31 TI03/TO03/P31 ch3 PORT 4 P40 PORT 5 P50 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER <R> LOW-SPEED ON-CHIP OSCILLATOR 12-BIT INTERVAL TIMER RL78 CPU CORE PORT 6 2 P60, P61 PORT 12 2 P121, P122 PORT 13 P137 PORT 14 P147 CODE FLASH MEMORY 3 ANI0/P20 to ANI2/P22 3 ANI16/P01, ANI17/P00, ANI18/P147 DATA FLASH MEMORY A/D CONVERTER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) RxD0/P11 TxD0/P12 UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P17 CSI11 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR RAM POR/LVD CONTROL RESET CONTROL VDD VSS TOOLRxD/P11, TOOLTxD/P12 TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL SERIAL INTERFACE IICA0 SDAA0/P61 SCLA0/P60 RESET X1/P121 HIGH-SPEED ON-CHIP X2/EXCLK/P122 OSCILLATOR SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 BUZZER OUTPUT PCLBUZ0/P31 CLOCK OUTPUT CONTROL DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR VOLTAGE REGULATOR REGC INTP0/P137 CRC INTP1/P50 INTERRUPT CONTROL 2 INTP3/P30, INTP4/P31 INTP5/P16 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 27 RL78/G13 CHAPTER 1 OUTLINE 1.5.3 25-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 5 P10 to P12, P16, P17 TI01/TO01/P16 ch1 PORT 2 3 P20 to P22 TI02/TO02/P17 ch2 PORT 3 2 P30, P31 TI03/TO03/P31 ch3 PORT 4 P40 PORT 5 P50 ch4 ch5 ch6 ch7 WINDOW WATCHDOG TIMER <R> LOW-SPEED ON-CHIP OSCILLATOR 12-BIT INTERVAL TIMER RL78 CPU CORE PORT 6 2 P60, P61 PORT 12 2 P121, P122 PORT 13 P130 P137 PORT 14 P147 CODE FLASH MEMORY 3 ANI0/P20 to ANI2/P22 3 ANI16/P01, ANI17/P00, ANI18/P147 DATA FLASH MEMORY A/D CONVERTER AVREFP/P20 AVREFM/P21 REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) RxD0/P11 TxD0/P12 UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P17 CSI11 POWER ON RESET/ VOLTAGE DETECTOR RAM POR/LVD CONTROL RESET CONTROL VDD VSS TOOLRxD/P11, TOOLTxD/P12 TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 SERIAL INTERFACE IICA0 SDAA0/P61 SCLA0/P60 RESET X1/P121 HIGH-SPEED ON-CHIP X2/EXCLK/P122 OSCILLATOR BUZZER OUTPUT PCLBUZ0/P31 CLOCK OUTPUT CONTROL DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR VOLTAGE REGULATOR REGC INTP0/P137 CRC INTP1/P50 INTERRUPT CONTROL 2 INTP3/P30, INTP4/P31 INTP5/P16 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 28 RL78/G13 CHAPTER 1 OUTLINE 1.5.4 30-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 TI01/TO01/P16 ch1 PORT 2 4 P20 to P23 TI02/TO02/P17 (TI02/TO02/P15) ch2 PORT 3 2 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) ch6 (TI07/TO07/P10) RxD2/P14 ch7 PORT 4 <R> LOW-SPEED ON-CHIP OSCILLATOR PORT 5 2 P50, P51 PORT 6 2 P60, P61 PORT 12 WINDOW WATCHDOG TIMER RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 P137 PORT 14 P147 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 CODE FLASH MEMORY RL78 CPU CORE A/D CONVERTER AVREFP/P20 AVREFM/P21 DATA FLASH MEMORY POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM RESET CONTROL VDD VSS TOOLRxD/P11, TOOLTxD/P12 SDAA0/P61(SDAA0/P13) SERIAL INTERFACE IICA0 SCLA0/P60(SCLA0/P14) IIC11 BUZZER OUTPUT 2 SERIAL ARRAY UNIT1 (2ch) UART2 LINSEL SCK20/P15 SI20/P14 SO20/P13 CSI20 SCL20/P15 SDA20/P14 IIC20 Remark P121, P122 12-BIT INTERVAL TIMER SERIAL ARRAY UNIT0 (4ch) RxD2/P14 TxD2/P13 P120 2 PORT 13 REAL-TIME CLOCK SCL11/P30 SDA11/P50 P40 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PCLBUZ0/P31, PCLBUZ1/P15 TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 HIGH-SPEED ON-CHIP OSCILLATOR X2/EXCLK/P122 VOLTAGE REGULATOR REGC CRC RxD2/P14 INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 29 RL78/G13 CHAPTER 1 OUTLINE 1.5.5 32-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 TI01/TO01/P16 ch1 PORT 2 4 P20 to P23 TI02/TO02/P17 (TI02/TO02/P15) ch2 PORT 3 2 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) (TI07/TO07/P10) RxD2/P14 PORT 4 PORT 5 2 P50, P51 ch6 PORT 6 3 P60 to P62 ch7 PORT 7 PORT 12 WINDOW WATCHDOG TIMER <R> LOW-SPEED ON-CHIP OSCILLATOR 12-BIT INTERVAL TIMER REAL-TIME CLOCK RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 PORT 14 P147 DATA FLASH MEMORY 4 ANI0/P20 to ANI3/P23 4 ANI16/P01, ANI17/P00, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 POWER ON RESET/ VOLTAGE DETECTOR RAM POR/LVD CONTROL VSS TOOLRxD/P11, TOOLTxD/P12 TOOL0/P40 ON-CHIP DEBUG SDAA0/P61(SDAA0/P13) SERIAL INTERFACE IICA0 SCLA0/P60(SCLA0/P14) BUZZER OUTPUT 2 CLOCK OUTPUT CONTROL SERIAL ARRAY UNIT1 (2ch) Remark P137 RESET CONTROL SCK11/P30 SI11/P50 SO11/P51 SCL20/P15 SDA20/P14 P120 P121, P122 2 PORT 13 A/D CONVERTER VDD SCK20/P15 SI20/P14 SO20/P13 P70 CODE FLASH MEMORY RL78 CPU CORE SERIAL ARRAY UNIT0 (4ch) RxD2/P14 TxD2/P13 P40 LINSEL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CSI20 DIRECT MEMORY ACCESS CONTROL IIC20 BCD ADJUSTMENT UART2 PCLBUZ0/P31, PCLBUZ1/P15 CRC SYSTEM CONTROL RESET X1/P121 HIGH-SPEED ON-CHIP OSCILLATOR X2/EXCLK/P122 VOLTAGE REGULATOR REGC RxD2/P14 INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 30 RL78/G13 CHAPTER 1 OUTLINE 1.5.6 36-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 TI01/TO01/P16 ch1 PORT 2 6 P20 to P25 TI02/TO02/P17 (TI02/TO02/P15) ch2 PORT 3 2 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) (TI07/TO07/P10) RxD2/P14 PORT 4 PORT 5 2 P50, P51 ch6 PORT 6 3 P60 to P62 ch7 PORT 7 3 P70 to P72 2 P121, P122 WINDOW WATCHDOG TIMER <R> LOW-SPEED ON-CHIP OSCILLATOR PORT 12 UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 P137 PORT 14 P147 DATA FLASH MEMORY A/D CONVERTER POWER ON RESET/ VOLTAGE DETECTOR RAM VSS CSI20 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR SCL21/P70 SDA21/P71 IIC21 TOOLRxD/P11, TOOLTxD/P12 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) 2 CLOCK OUTPUT CONTROL IIC20 ANI18/P147, ANI19/P120 POR/LVD CONTROL TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED ON-CHIP BUZZER OUTPUT LINSEL SCL20/P15 SDA20/P14 2 OSCILLATOR UART2 CSI21 ANI0/P20 to ANI5/P25 RESET CONTROL VDD SERIAL ARRAY UNIT1 (2ch) 6 AVREFP/P20 AVREFM/P21 SERIAL INTERFACE IICA0 Remark PORT 13 CODE FLASH MEMORY RL78 CPU CORE SERIAL ARRAY UNIT0 (4ch) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 P120 12-BIT INTERVAL TIMER REAL-TIME CLOCK RxD2/P14 TxD2/P13 P40 DIRECT MEMORY ACCESS CONTROL PCLBUZ0/P31, PCLBUZ1/P15 VOLTAGE REGULATOR REGC RxD2/P14 INTP0/P137 CRC INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 BCD ADJUSTMENT Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 31 RL78/G13 CHAPTER 1 OUTLINE 1.5.7 40-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 TI01/TO01/P16 ch1 PORT 2 7 P20 to P26 TI02/TO02/P17 (TI02/TO02/P15) ch2 PORT 3 2 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) (TI07/TO07/P10) RxD2/P14 PORT 4 PORT 5 2 P50, P51 ch6 PORT 6 3 P60 to P62 ch7 PORT 7 4 P70 to P73 4 P121 to P124 WINDOW WATCHDOG TIMER <R> LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 PORT 12 REAL-TIME CLOCK RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P01 TxD1/P00 UART1 SCK00/P10 SI00/P11 SO00/P12 CSI00 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 P137 PORT 14 P147 DATA FLASH MEMORY A/D CONVERTER POWER ON RESET/ VOLTAGE DETECTOR VSS TOOLRxD/P11, TOOLTxD/P12 SDAA0/P61(SDAA0/P13) CSI20 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR IIC21 KR0/P70 to KR3/P73 4 POR/LVD CONTROL RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SCLA0/P60(SCLA0/P14) 2 CLOCK OUTPUT CONTROL SCL21/P70 SDA21/P71 ANI18/P147, ANI19/P120 RESET X1/P121 X2/EXCLK/P122 BUZZER OUTPUT UART2 IIC20 2 SYSTEM CONTROL LINSEL SCL20/P15 SDA20/P14 ANI0/P20 to ANI6/P26 RAM VDD CSI21 7 AVREFP/P20 AVREFM/P21 KEY RETURN SERIAL ARRAY UNIT1 (2ch) Remark PORT 13 CODE FLASH MEMORY RL78 CPU CORE SERIAL INTERFACE IICA0 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 P120 12-BIT INTERVAL TIMER SERIAL ARRAY UNIT0 (4ch) RxD2/P14 TxD2/P13 P40 DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT PCLBUZ0/P31, PCLBUZ1/P15 CRC HIGH-SPEED XT1/P123 ON-CHIP OSCILLATOR XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD2/P14 INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 32 RL78/G13 CHAPTER 1 OUTLINE 1.5.8 44-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 TI01/TO01/P16 ch1 PORT 2 8 P20 to P27 TI02/TO02/P17 (TI02/TO02/P15) ch2 PORT 3 2 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) ch3 PORT 4 2 P40, P41 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 PORT 5 2 P50, P51 (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 ch6 PORT 6 4 P60 to P63 ch7 PORT 7 4 P70 to P73 4 P121 to P124 WINDOW WATCHDOG TIMER <R> LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 PORT 12 PORT 13 TxD0/P12(TxD0/P17) RxD1/P01 TxD1/P00 REAL-TIME CLOCK CODE FLASH MEMORY RL78 CPU CORE DATA FLASH MEMORY A/D CONVERTER P146, P147 8 ANI0/P20 to ANI7/P27 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL11/P30 SDA11/P50 IIC11 KR0/P70 to KR3/P73 4 RAM POWER ON RESET/ VOLTAGE DETECTOR VDD SERIAL ARRAY UNIT1 (2ch) POR/LVD CONTROL VSS TOOLRxD/P11, TOOLTxD/P12 RESET CONTROL SDAA0/P61(SDAA0/P13) SERIAL INTERFACE IICA0 UART2 SYSTEM CONTROL 2 CLOCK OUTPUT CONTROL CSI20 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR TOOL0/P40 ON-CHIP DEBUG SCLA0/P60(SCLA0/P14) BUZZER OUTPUT LINSEL PCLBUZ0/P31, PCLBUZ1/P15 RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP OSCILLATOR CRC XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD2/P14 INTP0/P137 CSI21 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 Remark 2 UART1 CSI00 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 PORT 14 UART0 SCK00/P10 SI00/P11 SO00/P12 RxD2/P14 TxD2/P13 P137 12-BIT INTERVAL TIMER SERIAL ARRAY UNIT0 (4ch) RxD0/P11(RxD0/P16) P120 DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 33 RL78/G13 CHAPTER 1 OUTLINE 1.5.9 48-pin products TIMER ARRAY UNIT (8ch) PORT 0 2 P00, P01 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 TI01/TO01/P16 ch1 PORT 2 8 P20 to P27 TI02/TO02/P17 (TI02/TO02/P15) ch2 PORT 3 2 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) ch3 PORT 4 2 P40, P41 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 PORT 5 2 P50, P51 (TI06/TO06/P11) ch6 PORT 6 4 P60 to P63 TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 ch7 PORT 7 6 P70 to P75 4 P121 to P124 PORT 12 WINDOW WATCHDOG TIMER <R> LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 PORT 14 REAL-TIME CLOCK RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P01 TxD1/P00 UART1 DATA FLASH MEMORY 8 ANI0/P20 to ANI7/P27 A/D CONVERTER 2 ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 RAM POWER ON RESET/ VOLTAGE DETECTOR CSI01 SCL00/P10 SDA00/P11 IIC00 SCL01/P75 SDA01/P74 IIC01 SCL11/P30 SDA11/P50 IIC11 VDD KR0/P70 to KR5/P75 6 VSS TOOLRxD/P11, TOOLTxD/P12 POR/LVD CONTROL RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL SERIAL ARRAY UNIT1 (2ch) HIGH-SPEED SCLA0/P60(SCLA0/P14) BUZZER OUTPUT CSI20 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CSI21 DIRECT MEMORY ACCESS CONTROL SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 RESET X1/P121 X2/EXCLK/P122 SDAA0/P61(SDAA0/P13) SERIAL INTERFACE IICA0 2 UART2 LINSEL Remark P140, P146, P147 CSI00 CSI11 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 3 CODE FLASH MEMORY RL78 CPU CORE KEY RETURN SCK11/P30 SI11/P50 SO11/P51 RxD2/P14 TxD2/P13 P130 P137 PORT 13 12-BIT INTERVAL TIMER SERIAL ARRAY UNIT0 (4ch) SCK00/P10 SI00/P11 SO00/P12 SCK01/P75 SI01/P74 SO01/P73 P120 PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P15 ON-CHIP XT1/P123 OSCILLATOR XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD2/P14 INTP0/P137 CRC INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 INTP6/P140 BCD ADJUSTMENT 2 INTP8/P74, INTP9/P75 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 34 RL78/G13 CHAPTER 1 OUTLINE 1.5.10 52-pin products TIMER ARRAY UNIT (8ch) PORT 0 4 P00 to P03 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 PORT 2 8 P20 to P27 PORT 3 2 P30, P31 PORT 4 2 P40, P41 PORT 5 2 P50, P51 TI01/TO01/P16 ch1 TI02/TO02/P17 (TI02/TO02/P15) ch2 TI03/TO03/P31 (TI03/TO03/P14) ch3 (TI04/TO04/P13) ch4 (TI05/TO05/P12) ch5 (TI06/TO06/P11) ch6 PORT 6 4 P60 to P63 TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) ch7 PORT 7 8 P70 to P77 PORT 12 WINDOW WATCHDOG TIMER P120 4 P121 to P124 P130 P137 PORT 13 <R> LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 12-BIT INTERVAL TIMER REAL-TIME CLOCK SERIAL ARRAY UNIT0 (4ch) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P03 TxD1/P02 UART1 SCK00/P10 SI00/P11 SO00/P12 SCK01/P75 SI01/P74 SO01/P73 PORT 14 IIC00 SCL01/P75 SDA01/P74 IIC01 SCL11/P30 SDA11/P50 IIC11 A/D CONVERTER 4 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 KEY RETURN POWER ON RESET/ VOLTAGE DETECTOR KR0/P70 to KR7/P77 8 POR/LVD CONTROL RESET CONTROL VDD VSS TOOLRxD/P11, TOOLTxD/P12 TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP SDAA0/P61(SDAA0/P13) SERIAL INTERFACE IICA0 SERIAL ARRAY UNIT1 (2ch) XT2/EXCLKS/P124 VOLTAGE REGULATOR UART2 2 CLOCK OUTPUT CONTROL CSI20 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CSI21 OSCILLATOR SCLA0/P60(SCLA0/P14) BUZZER OUTPUT LINSEL REGC PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P15 CRC RxD2/P14 (RxD2/P76) INTP0/P137 INTERRUPT CONTROL 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 INTP5/P16 INTP6/P140 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 Remark ANI0/P20 to ANI7/P27 DATA FLASH MEMORY CSI01 SCL00/P10 SDA00/P11 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 8 CODE FLASH MEMORY RL78 CPU CORE RAM CSI11 TxD2/P13(TxD2/P77) P140, P146, P147 CSI00 SCK11/P30 SI11/P50 SO11/P51 RxD2/P14(RxD2/P76) 3 DIRECT MEMORY ACCESS CONTROL 4 INTP8/P74 to INTP11/P77 BCD ADJUSTMENT Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 35 RL78/G13 CHAPTER 1 OUTLINE 1.5.11 64-pin products TIMER ARRAY UNIT (8ch) PORT 0 7 P00 to P06 TI00/P00 TO00/P01 ch0 PORT 1 8 P10 to P17 TI01/TO01/P16 ch1 PORT 2 8 P20 to P27 TI02/TO02/P17 (TI02/TO02/P15) ch2 PORT 3 2 P30, P31 TI03/TO03/P31 (TI03/TO03/P14) ch3 TI04/TO04/P42 (TI04/TO04/P13) PORT 4 4 P40 to P43 ch4 TI05/TO05/P05 (TI05/TO05/P12) ch5 PORT 5 6 P50 to P55 ch6 PORT 6 4 P60 to P63 ch7 PORT 7 8 P70 to P77 4 P121 to P124 TI06/TO06/P06 (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) PORT 12 WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR <R> RTC1HZ/P30 PORT 14 UART0 RxD1/P03 TxD1/P02 UART1 A/D CONVERTER SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL01/P75 SDA01/P74 IIC01 ANI0/P20 to ANI7/P27 4 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120 AVREFP/P20 AVREFM/P21 DATA FLASH MEMORY KEY RETURN KR0/P70 to KR7/P77 8 POWER ON RESET/ VOLTAGE DETECTOR POR/LVD CONTROL RAM RESET CONTROL TOOL0/P40 ON-CHIP DEBUG VDD, VSS, TOOLRxD/P11, EVDD0 EVSS0 TOOLTxD/P12 SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP SCL10/P04 SDA10/P03 IIC10 SCL11/P30 SDA11/P50 IIC11 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) BUZZER OUTPUT PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) UART2 LINSEL OSCILLATOR XT2/EXCLKS/P124 SCLA0/P60(SCLA0/P14) VOLTAGE REGULATOR 2 SERIAL ARRAY UNIT1 (2ch) Remark 8 CODE FLASH MEMORY RL78 CPU CORE CSI01 CSI10 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 P140, P141, P146, P147 CSI00 SCK10/P04 SI10/P03 SO10/P02 TxD2/P13(TxD2/P77) 4 REAL-TIME CLOCK RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) RxD2/P14(RxD2/P76) P130 P137 PORT 13 12-BIT INTERVAL TIMER SERIAL ARRAY UNIT0 (4ch) SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P75 SI01/P74 SO01/P73 P120 CLOCK OUTPUT CONTROL MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CSI20 DIRECT MEMORY ACCESS CONTROL REGC RxD2/P14 (RxD2/P76) INTP0/P137 CRC 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 2 INTP6/P140, INTP7/P141 2 INTP8/P74, INTP9/P75 2 INTP10/P76(INTP10/P52), INTP11/P77(INTP11/P53) INTERRUPT CONTROL INTP5/P16(INTP5/P12) CSI21 SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 BCD ADJUSTMENT Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 36 RL78/G13 CHAPTER 1 OUTLINE 1.5.12 80-pin products TIMER ARRAY UNIT0 (8ch) TIMER ARRAY UNIT1 (4ch) TI00/P00 TO00/P01 ch0 ch0 TI10/TO10/P64 PORT 0 7 P00 to P06 TI01/TO01/P16 ch1 ch1 TI11/TO11/P65 PORT 1 8 P10 to P17 TI02/TO02/P17 (TI02/TO02/P15) ch2 ch2 TI12/TO12/P66 PORT 2 8 P20 to P27 TI03/TO03/P31 (TI03/TO03/P14) ch3 ch3 TI13/TO13/P67 PORT 3 2 P30, P31 TI04/TO04/P42 (TI04/TO04/P13) ch4 PORT 4 6 P40 to P45 TI05/TO05/P05 (TI05/TO05/P12) ch5 PORT 5 6 P50 to P55 PORT 6 8 P60 to P67 PORT 7 8 P70 to P77 TI06/TO06/P06 (TI06/TO06/P11) TI07/TO07/P41 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) ch6 ch7 SERIAL ARRAY UNIT0 (4ch) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P03 TxD1/P02 UART1 SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P43 SI01/P44 SO01/P45 SCL00/P10 SDA00/P11 IIC00 SCL01/P43 SDA01/P44 IIC01 SCL10/P04 SDA10/P03 IIC10 SCL11/P30 SDA11/P50 IIC11 CODE FLASH MEMORY RL78 CPU CORE P110, P111 2 BUZZER OUTPUT CSI21 CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) 2 IIC20 SCL21/P70 SDA21/P71 IIC21 SCL30/P142 SDA30/P143 IIC30 SCL31/P54 SDA31/P53 IIC31 P140 to P144, P146, P147 PORT 15 4 P150 to P153 KEY RETURN 8 KR0/P70 to KR7/P77 POR/LVD CONTROL RESET CONTROL CSI20 SCL20/P15 SDA20/P14 7 SDAA0/P61(SDAA0/P13) SDAA1/P63 SCLA1/P62 CSI31 PORT 14 VDD, VSS, TOOLRxD/P11, EVDD0 EVSS0 TOOLTxD/P12 UART3 SCK31/P54 SI31/P53 SO31/P52 P130 P137 PORT 13 POWER ON RESET/ VOLTAGE DETECTOR SCLA0/P60(SCLA0/P14) CSI30 P121 to P124 RAM SERIAL INTERFACE IICA1 LINSEL P120 4 DATA FLASH MEMORY SERIAL INTERFACE IICA0 UART2 SCK30/P142 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR CRC TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP OSCILLATOR XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD2/P14 (RxD2/P76) INTP0/P137 DIRECT MEMORY ACCESS CONTROL BCD ADJUSTMENT WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR RTC1HZ/P30 Remark PORT 11 PORT 12 SERIAL ARRAY UNIT1 (4ch) <R> P100 PORT 10 CSI01 CSI11 SI30/P143 SO30/P144 A/D CONVERTER AVREFP/P20 AVREFM/P21 SCK11/P30 SI11/P50 SO11/P51 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 ANI8/P150 to ANI11/P153 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 CSI00 CSI10 RxD3/P143 TxD3/P144 ANI0/P20 to ANI7/P27 4 5 SCK10/P04 SI10/P03 SO10/P02 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) 8 12-BIT INTERVAL TIMER REAL-TIME CLOCK 2 INTP1/P50, INTP2/P51 2 INTP3/P30, INTP4/P31 2 INTP6/P140, INTP7/P141 2 INTP8/P74, INTP9/P75 2 INTP10/P76(INTP10/P110), INTP11/P77(INTP11/P111) INTP5/P16(INTP5/P12) INTERRUPT CONTROL Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 37 RL78/G13 CHAPTER 1 OUTLINE 1.5.13 100-pin products TIMER ARRAY UNIT0 (8ch) TIMER ARRAY UNIT1 (4ch) TI00/P00 TO00/P01 ch0 ch0 TI10/TO10/P64 PORT 0 7 P00 to P06 TI01/TO01/P16 ch1 ch1 TI11/TO11/P65 PORT 1 8 P10 to P17 TI02/TO02/P17 (TI02/TO02/P15) ch2 ch2 TI12/TO12/P66 PORT 2 8 P20 to P27 TI03/TO03/P31 (TI03/TO03/P14) ch3 ch3 TI13/TO13/P67 PORT 3 2 P30, P31 TI04/TO04/P42 (TI04/TO04/P13) ch4 PORT 4 8 TI05/TO05/P46 (TI05/TO05/P12) P40 to P47 ch5 PORT 5 8 P50 to P57 PORT 6 8 P60 to P67 PORT 7 8 P70 to P77 PORT 8 8 P80 to P87 PORT 10 3 P100 to P102 PORT 11 2 P110, P111 4 P121 to P124 TI06/TO06/P102 (TI06/TO06/P11) TI07/TO07/P145 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) ch6 ch7 SERIAL ARRAY UNIT0 (4ch) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P03(RxD1/P81) TxD1/P02(TxD1/P82) UART1 SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P43 SI01/P44 SO01/P45 A/D CONVERTER AVREFP/P20 AVREFM/P21 CSI01 PORT 12 CSI10 SCK11/P30 SI11/P50 SO11/P51 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL01/P43 SDA01/P44 IIC01 SCL10/P04(SCL10/P80) SDA10/P03(SDA10/P81) IIC10 SCL11/P30 SDA11/P50 IIC11 CODE FLASH MEMORY RL78 CPU CORE LINSEL RxD3/P143 TxD3/P144 UART3 CSI20 P120 P130 P137 PORT 13 DATA FLASH MEMORY PORT 14 8 P140 to P147 PORT 15 7 P150 to P156 KEY RETURN 8 KR0/P70 to KR7/P77 RAM POWER ON RESET/ VOLTAGE DETECTOR VDD, VSS, TOOLRxD/P11, EVDD0, EVSS0, TOOLTxD/P12 EVDD1 EVSS1 UART2 RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) SERIAL INTERFACE IICA1 SDAA1/P63 SCLA1/P62 BUZZER OUTPUT 2 CSI21 CLOCK OUTPUT CONTROL SCK30/P142 SI30/P143 SO30/P144 CSI30 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR SCK31/P54 SI31/P53 SO31/P52 CSI31 DIRECT MEMORY ACCESS CONTROL SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 SCL30/P142 SDA30/P143 IIC30 SCL31/P54 SDA31/P53 IIC31 PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) CRC WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR POR/LVD CONTROL RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP OSCILLATOR XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD2/P14 (RxD2/P76) INTP0/P137 BCD ADJUSTMENT RTC1HZ/P30 Remark ANI8/P150 to ANI14/P156 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100 CSI00 SERIAL ARRAY UNIT1 (4ch) <R> ANI0/P20 to ANI7/P27 7 5 SCK10/P04(SCK10/P80) SI10/P03(SI10/P81) SO10/P02(SO10/P82) SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 8 12-BIT INTERVAL TIMER 2 INTP1/P46(INTP1/P56), INTP2/P47 2 INTP3/P30(INTP3/P57), INTP4/P31(INTP4/P146) INTERRUPT CONTROL INTP5/P16(INTP5/P12) 2 INTP6/P140(INTP6/P84), INTP7/P141(INTP7/P85) 2 INTP8/P74(INTP8/P86), INTP9/P75(INTP9/P87) 2 INTP10/P76(INTP10/P110), INTP11/P77(INTP11/P111) REAL-TIME CLOCK Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 38 RL78/G13 CHAPTER 1 OUTLINE 1.5.14 128-pin products TIMER ARRAY UNIT0 (8ch) TIMER ARRAY UNIT1 (8ch) TI00/P00 TO00/P01 ch0 ch0 TI10/TO10/P64 PORT 0 8 P00 to P07 TI01/TO01/P16 ch1 ch1 TI11/TO11/P65 PORT 1 8 P10 to P17 TI02/TO02/P17 (TI02/TO02/P15) ch2 ch2 TI12/TO12/P66 PORT 2 8 P20 to P27 TI03/TO03/P31 (TI03/TO03/P14) ch3 ch3 TI13/TO13/P67 PORT 3 8 P30 to P37 TI04/TO04/P42 (TI04/TO04/P13) ch4 ch4 TI14/TO14/P103 PORT 4 8 TI05/TO05/P46 (TI05/TO05/P12) P40 to P47 ch5 ch5 TI15/TO15/P104 PORT 5 8 P50 to P57 ch6 ch6 TI16/TO16/P105 ch7 ch7 TI17/TO17/P106 PORT 6 8 P60 to P67 PORT 7 8 P70 to P77 PORT 8 8 P80 to P87 PORT 9 8 P90 to P97 PORT 10 7 P100 to P106 PORT 11 8 P110 to P117 TI06/TO06/P102 (TI06/TO06/P11) TI07/TO07/P145 (TI07/TO07/P10) RxD2/P14 (RxD2/P76) SERIAL ARRAY UNIT0 (4ch) RxD0/P11(RxD0/P16) TxD0/P12(TxD0/P17) UART0 RxD1/P03(RxD1/P81) TxD1/P02(TxD1/P82) UART1 SCK00/P10(SCK00/P55) SI00/P11(SI00/P16) SO00/P12(SO00/P17) SCK01/P43 SI01/P44 SO01/P45 CSI00 CSI10 SCK11/P95 SI11/P96 SO11/P97 CSI11 SCL00/P10 SDA00/P11 IIC00 SCL01/P43 SDA01/P44 IIC01 SCL10/P04(SCL10/P80) SDA10/P03(SDA10/P81) IIC10 SCL11/P95 SDA11/P96 IIC11 SCK20/P15 SI20/P14 SO20/P13 SCK21/P70 SI21/P71 SO21/P72 <R> ANI8/P150 to ANI14/P156 ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100, ANI21/37, ANI22/P36, ANI23/P35, ANI24/P117, ANI25/P116, ANI26/P115 A/D CONVERTER AVREFP/P20 AVREFM/P21 UART2 4 P120, P125 to P127 4 P121 to P124 CODE FLASH MEMORY P130 P137 PORT 13 DATA FLASH MEMORY PORT 14 8 P140 to P147 PORT 15 7 P150 to P156 KEY RETURN 8 POWER ON RESET/ VOLTAGE DETECTOR VDD, VSS, TOOLRxD/P11, EVDD0, EVSS0, TOOLTxD/P12 EVDD1 EVSS1 SERIAL INTERFACE IICA0 SDAA0/P61(SDAA0/P13) SCLA0/P60(SCLA0/P14) UART3 SERIAL INTERFACE IICA1 SDAA1/P63 SCLA1/P62 CSI20 BUZZER OUTPUT CSI21 CLOCK OUTPUT CONTROL PCLBUZ0/P140 (PCLBUZ0/P31), PCLBUZ1/P141 (PCLBUZ1/P55) LINSEL PORT 12 KR0/P70 to KR7/P77 RAM 2 SCK30/P142 SI30/P143 SO30/P144 CSI30 MULTIPLIER& DIVIDER, MULITIPLYACCUMULATOR SCK31/P54 SI31/P53 SO31/P52 CSI31 DIRECT MEMORY ACCESS CONTROL SCL20/P15 SDA20/P14 IIC20 SCL21/P70 SDA21/P71 IIC21 SCL30/P142 SDA30/P143 IIC30 SCL31/P54 SDA31/P53 IIC31 CRC WINDOW WATCHDOG TIMER LOW-SPEED ON-CHIP OSCILLATOR POR/LVD CONTROL RESET CONTROL TOOL0/P40 ON-CHIP DEBUG SYSTEM CONTROL RESET X1/P121 X2/EXCLK/P122 HIGH-SPEED XT1/P123 ON-CHIP OSCILLATOR XT2/EXCLKS/P124 VOLTAGE REGULATOR REGC RxD2/P14 (RxD2/P76) INTP0/P137 BCD ADJUSTMENT RTC1HZ/P30 Remark 7 11 RL78 CPU CORE SERIAL ARRAY UNIT1 (4ch) RxD3/P143 TxD3/P144 ANI0/P20 to ANI7/P27 CSI01 SCK10/P04(SCK10/P80) SI10/P03(SI10/P81) SO10/P02(SO10/P82) RxD2/P14(RxD2/P76) TxD2/P13(TxD2/P77) 8 12-BIT INTERVAL TIMER REAL-TIME CLOCK 2 INTP1/P46 (INTP1/P56), INTP2/P47 2 INTP3/P30 (INTP3/P57), INTP4/P31 (INTP4/P146) INTERRUPT CONTROL INTP5/P16 (INTP5/P12) 2 INTP6/P140 (INTP6/P84), INTP7/P141 (INTP7/P85) 2 INTP8/P74 (INTP8/P86), INTP9/P75 (INTP9/P87) 2 INTP10/P76 (INTP10/P110), INTP11/P77 (INTP11/P111) Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 39 RL78/G13 CHAPTER 1 OUTLINE 1.6 Outline of Functions <R> [20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H other than timer output. <R> (1/2) Item 20-pin Note1 16 to 128 - 4 to 8 2 to 12 R5F101Cx 2 to 12 R5F100Cx Note1 16 to 128 - 4 to 8 36-pin R5F101Bx 16 to 128 - 2 to 4 R5F100Bx 16 to 64 4 32-pin R5F101Ax 2 to 4 Note1 R5F100Ax Main system clock Note1 30-pin R5F1018x 2 to 4 - 4 R5F1008x RAM (KB) 16 to 64 - 4 25-pin R5F1017x 16 to 64 Data flash memory (KB) Memory space R5F1007x R5F1016x R5F1006x Code flash memory (KB) 24-pin - 4 to 8 Note1 2 to 12 Note1 1 MB High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip oscillator HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V), LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V), LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V) - Subsystem clock Low-speed on-chip oscillator 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) * * * * Instruction set I/O port Timer Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits x 8 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 16 20 21 26 28 32 CMOS I/O 13 15 15 21 22 26 CMOS input 3 3 3 3 3 3 CMOS output - - 1 - - - N-ch O.D I/O (6 V tolerance) - 2 2 2 3 3 16-bit timer 8 channels Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer (IT) 1 channel Timer output 3 channels (PWM Note 2 ) outputs: 2 4 channels Note 2 (PWM outputs: 3 ) RTC output Notes 1. 4 channels (PWM outputs: 3 8 channels Note 3 Note 2 ), (PWM outputs: 7 Note 2 ) - In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) <R> 2. <R> 3. The number of outputs varies, depending on the setting of channels in use and the number of the master (6.8.3 Operation as multiple PWM output function). When setting to PIOR = 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 40 RL78/G13 CHAPTER 1 OUTLINE <R> (2/2) Item 20-pin R5F101Cx 2 36-pin R5F100Cx R5F101Bx 1 32-pin R5F100Bx R5F101Ax R5F100Ax 1 30-pin R5F1018x R5F1008x - 25-pin R5F1017x R5F1007x R5F1016x R5F1006x Clock output/buzzer output 24-pin 2 2 * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter 6 channels 6 channels Serial interface [20-pin, 24-pin, 25-pin products] 6 channels 8 channels 8 channels 8 channels * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 [30-pin, 32-pin products] * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 1 channel 2 [36-pin products] * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 2 channel/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channel 2 2 I C bus - 1 channel 1 channel 1 channel Multiplier and divider/multiply- * 16 bits x 16 bits = 32 bits (Unsigned or signed) accumulator * 32 bits / 32 bits = 32 bits (Unsigned) 1 channel 1 channel * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored interrupt Internal 23 24 24 27 27 27 sources 3 5 5 6 6 6 External - Key interrupt * Reset by RESET pin Reset * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: 1.51 0.03 V * Power-down-reset: 1.50 0.03 V Voltage detector * Rising edge : 1.67 V to 4.06 V (14 stages) * Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = -40 to +85 C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 41 RL78/G13 CHAPTER 1 OUTLINE <R> [40-pin, 44-pin, 48-pin, 52-pin, 64-pin products] Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set <R> to 00H other than timer output. (1/2) Item 40-pin 2 to 32 32 to 512 - 4 to 8 Note1 2 to 32 Note1 R5F101Lx Main system clock - R5F100Lx Memory space 2 to 32 16 to 512 4 to 8 64-pin R5F101Jx 2 to 16 Note1 R5F100Jx RAM (KB) - 52-pin R5F101Gx Note1 16 to 512 4 to 8 R5F100Gx - 4 to 8 48-pin R5F101Fx 16 to 192 Data flash memory (KB) R5F100Fx R5F101Ex R5F100Ex Code flash memory (KB) 44-pin 32 to 512 - 4 to 8 2 to 32 Note1 1 MB High-speed system clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip oscillator HS (High-speed main) mode: HS (High-speed main) mode: LS (Low-speed main) mode: LV (Low-voltage main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V), 1 to 8 MHz (VDD = 1.8 to 5.5 V), 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V Low-speed on-chip oscillator 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) * * * * Instruction set I/O port Timer Notes 1. <R> <R> 2. 3. Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits x 8 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. Total 36 40 44 48 58 CMOS I/O 28 31 34 38 48 CMOS input 5 5 5 5 5 CMOS output - - 1 1 1 N-ch O.D I/O (6 V tolerance) 3 4 4 4 4 16-bit timer 8 channels Watchdog timer 1 channel Real-time clock (RTC) 1 channel 12-bit interval timer (IT) 1 channel Note 2 Timer output 4 channels (PWM 5 channels (PWM outputs: 4 ), Note 2 Note 3 Note 2 (PWM outputs: 7 ) outputs: 3 ), 8 channels Note 3 8 channels Note 2 (PWM outputs: 7 ) RTC output 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz or ) 8 channels (PWM Note 2 outputs: 7 ) In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) In the case of the 20 KB, this is about 19 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) In the case of the 32 KB, this is about 31 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) The number of outputs varies, depending on the setting of channels in use and the number of the master (6.8.3 Operation as multiple PWM output function). When setting to PIOR = 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 42 RL78/G13 CHAPTER 1 OUTLINE (2/2) <R> Item 40-pin 52-pin 64-pin R5F101Lx 2 R5F100Lx R5F101Jx 2 R5F100Jx R5F101Gx R5F100Gx 2 48-pin R5F101Fx R5F100Fx R5F101Ex R5F100Ex Clock output/buzzer output 44-pin 2 2 * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 9 channels 10 channels Serial interface [40-pin, 44-pin products] 10 channels 12 channels 12 channels * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels 2 [48-pin, 52-pin products] * CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels 2 * CSI: 1 channel/UART: 1 channel/simplified I C: 1 channel 2 * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels 2 [64-pin products] * CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels 2 * CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels 2 * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels 2 2 I C bus 1 channel 1 channel 1 channel Multiplier and divider/multiply- * 16 bits x 16 bits = 32 bits (Unsigned or signed) accumulator * 32 bits / 32 bits = 32 bits (Unsigned) 1 channel 1 channel * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 2 channels Vectored Internal 27 27 27 27 27 interrupt sources External 7 7 10 12 13 4 4 6 8 8 Key interrupt * Reset by RESET pin Reset * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: 1.51 0.03 V * Power-down-reset: 1.50 0.03 V Voltage detector * Rising edge : 1.67 V to 4.06 V (14 stages) * Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = -40 to +85 C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 43 RL78/G13 CHAPTER 1 OUTLINE [80-pin, 100-pin, 128-pin products] Caution <R> This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item 80-pin R5F100Mx Code flash memory (KB) 100-pin R5F101Mx R5F100Px 96 to 512 Data flash memory (KB) RAM (KB) 8 to 32 R5F101Px R5F100Sx 96 to 512 - 8 128-pin Note 1 192 to 512 - 8 8 to 32 R5F101Sx Note 1 - 8 16 to 32 Note 1 Memory space 1 MB Main system High-speed system clock clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V High-speed on-chip oscillator HS (High-speed main) mode: HS (High-speed main) mode: LS (Low-speed main) mode: LV (Low-voltage main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V), 1 to 8 MHz (VDD = 1.8 to 5.5 V), 1 to 4 MHz (VDD = 1.6 to 5.5 V) Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz (TYP.): VDD = 1.6 to 5.5 V Low-speed on-chip oscillator 15 kHz (TYP.): VDD = 1.6 to 5.5 V General-purpose register 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) 30.5 s (Subsystem clock: fSUB = 32.768 kHz operation) * * * * Instruction set I/O port Timer Total 74 92 120 CMOS I/O 64 82 110 CMOS input 5 5 5 CMOS output 1 1 1 N-ch O.D I/O (6 V tolerance) 4 4 4 16-bit timer 12 channels 12 channels 16 channels Watchdog timer 1 channel 1 channel 1 channel Real-time clock (RTC) 1 channel 1 channel 1 channel 12-bit interval timer (IT) Notes 1. Data transfer (8/16 bits) Adder and subtractor/logical operation (8/16 bits) Multiplication (8 bits x 8 bits) Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc. 1 channel 1 channel 12 channels Note 2 (PWM outputs: 10 ) Timer output 12 channels Note 2 ) (PWM outputs: 10 RTC output 1 * 1 Hz (subsystem clock: fSUB = 32.768 kHz or ) 1 channel 16 channels Note 2 (PWM outputs: 14 ) In the case of the 20 KB, this is about 19 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) In the case of the 32 KB, this is about 31 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) <R> 2. The number of outputs varies, depending on the setting of channels in use and the number of the master (refer to 6.8.3 Operation as multiple PWM output function). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 44 RL78/G13 CHAPTER 1 OUTLINE (2/2) <R> Item 80-pin R5F100Mx 100-pin R5F101Mx Clock output/buzzer output R5F100Px R5F101Px 2 128-pin R5F100Sx 2 R5F101Sx 2 * 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) * 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 17 channels 20 channels Serial interface [80-pin, 100-pin, 128-pin products] 26 channels * CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels 2 * CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels 2 * CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I C: 2 channels 2 * CSI: 2 channels/UART: 1 channel/simplified I C: 2 channels 2 2 I C bus 2 channel 2 channel 2 channel Multiplier and divider/multiply- * 16 bits x 16 bits = 32 bits (Unsigned or signed) accumulator * 32 bits / 32 bits = 32 bits (Unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 4 channels Vectored Internal 37 37 41 interrupt sources External 13 13 13 8 8 8 Key interrupt * Reset by RESET pin Reset * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit * Power-on-reset: 1.51 0.03 V * Power-down-reset: 1.50 0.03 V Voltage detector * Rising edge : 1.67 V to 4.06 V (14 stages) * Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature TA = -40 to +85 C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 45 RL78/G13 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Function Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies (1) 20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin, 40-pin, 44-pin, 48-pin, 52-pin products Power Supply VDD Corresponding Pins All pins (2) 64-pin products Power Supply Corresponding Pins EVDD0 Port pins other than P20 to P27, P121 to P124, and P137 VDD * P20 to P27, P121 to P124, and P137 * RESET, REGC (3) 80-pin products Power Supply Corresponding Pins EVDD0 Port pins other than P20 to P27, P121 to P124, P137, and P150 to P153 VDD * P20 to P27, P121 to P124, P137, and P150 to P153 * RESET, REGC (4) 100-pin products Power Supply Corresponding Pins EVDD0, EVDD1 Port pins other than P20 to P27, P121 to P124, P137, and P150 to P156 VDD * P20 to P27, P121 to P124, P137, and P150 to P156 * RESET, REGC (5) 128-pin products Power Supply Corresponding Pins EVDD0, EVDD1 Port pins other than P20 to P27, P121 to P124, P137, and P150 to P156 VDD * P20 to P27, P121 to P124, P137, and P150 to P156 * RESET, REGC R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 46 RL78/G13 <R> CHAPTER 2 PIN FUNCTIONS Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions. 2.1.1 20-pin products Function Name P00 I/O I/O P01 P10 I/O P11 P12 P16 Function After Reset Port 0. 2-bit I/O port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Note 1 . P00 and P01 can be set to analog input Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Analog input port ANI17/TI00/TxD1 Port 1. 5-bit I/O port. Input of P10, P11, P16, and P17 can be set to TTL input buffer. Output of P10 to P12, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port SCK00/SCL00 TOOLRxD/SDA00 SO00/TxD0/ TOOLTxD TI01/TO01/INTP5/ SO11 TI02/TO02/SI11/ SDA11 I/O P21 P22 P30 I/O Port 2. 3-bit I/O port. Note 2 . Can be set to analog input Input/output can be specified in 1-bit units. Analog input port Port 3. 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port ANI0/AVREFP ANI1/AVREFM ANI2 INTP3/ SCK11/SCL11 P40 I/O Port 4. 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port TOOL0 P121 Input Port 12. 2-bit input only port. Input port X1 P122 <R> ANI16/TO00/RxD1 SI00/RxD0/ P17 P20 Alternate Function X2/EXCLK P137 Input Port 13. 1-bit input only port. Input port INTP0 P147 I/O Port 14. 1-bit I/O port. Note 1 . P147 can be set to analog input Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Analog input port ANI18 Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 47 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.2 24-pin products Function Name P00 I/O I/O P01 P10 I/O P11 P12 P16 P17 P20 I/O P21 P22 P30 I/O P31 After Reset Alternate Function Port 0. 2-bit I/O port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Note 1 . P00 and P01 can be set to analog input Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Analog input port ANI17/TI00/TxD1 Port 1. 5-bit I/O port. Input of P10, P11, P16, and P17 can be set to TTL input buffer. Output of P10 to P12, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port SCK00/SCL00 Port 2. 3-bit I/O port. Note 2 . Can be set to analog input Input/output can be specified in 1-bit units. Analog input port Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port ANI16/TO00/RxD1 SI00/RxD0/ TOOLRxD/SDA00 SO00/TxD0/ TOOLTxD TI01/TO01/INTP5 TI02/TO02/SO11 ANI0/AVREFP ANI1/AVREFM ANI2 INTP3/ SCK11/SCL11 TI03/TO03/INTP4/ PCLBUZ0 P40 I/O Port 4. 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port TOOL0 P50 I/O Port 5. 1-bit I/O port. Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port INTP1/SI11/SDA11 P60 I/O Port 6. 2-bit I/O port. Output of P60 and P61 can be set to N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Input port SCLA0 Port 12. 2-bit input only port. Input port P61 P121 Input P122 <R> Function SDAA0 X1 X2/EXCLK P137 Input Port 13. 1-bit input only port. Input port INTP0 P147 I/O Port 14. 1-bit I/O port. Note 1 P147 can be set to analog input . Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Analog input port ANI18 Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 48 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.3 25-pin products Function Name P00 I/O I/O P01 P10 I/O P11 P12 P16 P17 P20 I/O P21 P22 P30 I/O P31 After Reset Alternate Function Port 0. 2-bit I/O port. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Note 1 . P00 and P01 can be set to analog input Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Analog input port ANI17/TI00/TxD1 Port 1. 5-bit I/O port. Input of P10, P11, P16, and P17 can be set to TTL input buffer. Output of P10 to P12, and P17 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port SCK00/SCL00 Port 2. 3-bit I/O port. Note 2 . Can be set to analog input Input/output can be specified in 1-bit units. Analog input port Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port ANI16/TO00/RxD1 SI00/RxD0/ TOOLRxD/SDA00 SO00/TxD0/ TOOLTxD TI01/TO01/INTP5 TI02/TO02/SO11 ANI0/AVREFP ANI1/AVREFM ANI2 INTP3/ SCK11/SCL11 TI03/TO03/INTP4/ PCLBUZ0 P40 I/O Port 4. 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port TOOL0 P50 I/O Port 5. 1-bit I/O port. Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port INTP1/SI11/SDA11 P60 I/O Port 6. 2-bit I/O port. Output of P60 and P61 can be set to N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. Input port SCLA0 Port 12. 2-bit input only port. Input port Port 13. 1-bit output port and 1-bit input only port. Output port Input port INTP0 Port 14. 1-bit I/O port. Note 1 P147 can be set to analog input . Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Analog input port ANI18 P61 P121 Input P122 <R> Function P130 Output P137 Input P147 I/O SDAA0 X1 X2/EXCLK - Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 49 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.4 30-pin products (1/2) Function Name I/O I/O P00 P01 Function After Reset Port 0. Analog input 2-bit I/O port. port Alternate Function ANI17/TI00/TxD1 ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Note 1 . P00 and P01 can be set to analog input Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. I/O P10 P11 Port 1. Input port (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/TOOLRxD/ buffer. SDA00/(TI06)/(TO06) Output of P10 to P15, and P17 can be set to N-ch open-drain P12 SO00/TxD0/TOOLTxD/ output (VDD tolerance). (TI05)/(TO05) Input/output can be specified in 1-bit units. P13 SCK00/SCL00/(TI07)/ 8-bit I/O port. Use of an on-chip pull-up resistor can be specified by a TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02)/(TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 TI02/TO02/(TxD0) P20 I/O P21 P22 Port 2. Analog input ANI0/AVREFP 4-bit I/O port. Note 2 Can be set to analog input . port ANI1/AVREFM ANI2 Input/output can be specified in 1-bit units. ANI3 P23 I/O P30 Port 3. Input port 2-bit I/O port. SCK11/SCL11 Input/output can be specified in 1-bit units. P31 TI03/TO03/INTP4/ Use of an on-chip pull-up resistor can be specified by a PCLBUZ0 software setting at input port. P40 I/O Port 4. INTP3/ Input port TOOL0 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 50 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O Function Port 5. After Reset Input port 2-bit I/O port. P51 Alternate Function INTP1/SI11/SDA11 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 I/O Port 6. Input port 2-bit I/O port. P61 SCLA0 SDAA0 Output of P60 and P61 can be set to N-ch open-drain output (6 V tolerance). Input/output can be specified in 1-bit units. P120 P121 I/O Input Port 12. Analog input 1-bit I/O port and 2-bit input only port. Note P120 can be set to analog input . port Input port For only P120, input/output can be specified in 1-bit units. P122 ANI19 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be specified by a software setting at input port. P137 Input Port 13. Input port INTP0 Port 14. Analog input ANI18 1-bit I/O port. Note P147 can be set to analog input . port 1-bit input only port. P147 I/O Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 51 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.5 32-pin products (1/2) Function Name I/O I/O P00 P01 Function After Reset Port 0. Analog input 2-bit I/O port. port Alternate Function ANI17/TI00/TxD1 ANI16/TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Note 1 . P00 and P01 can be set to analog input Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. I/O P10 P11 Port 1. Input port (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/TOOLRxD/ buffer. SDA00/(TI06)/(TO06) Output of P10 to P15, and P17 can be set to N-ch open-drain P12 SO00/TxD0/TOOLTxD/ output (VDD tolerance). (TI05)/(TO05) Input/output can be specified in 1-bit units. P13 SCK00/SCL00/(TI07)/ 8-bit I/O port. Use of an on-chip pull-up resistor can be specified by a TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02)/(TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 TI02/TO02/(TxD0) P20 I/O P21 P22 Port 2. Analog input ANI0/AVREFP 4-bit I/O port. Note 2 Can be set to analog input . port ANI1/AVREFM ANI2 Input/output can be specified in 1-bit units. ANI3 P23 I/O P30 Port 3. Input port 2-bit I/O port. SCK11/SCL11 Input/output can be specified in 1-bit units. P31 TI03/TO03/INTP4/ Use of an on-chip pull-up resistor can be specified by a PCLBUZ0 software setting at input port. P40 I/O Port 4. INTP3/ Input port TOOL0 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 52 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O Function Port 5. After Reset Input port 2-bit I/O port. P51 Alternate Function INTP1/SI11/SDA11 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 I/O Port 6. Input port 3-bit I/O port. P61 SCLA0 SDAA0 Output of P60 to P62 can be set to N-ch open-drain output P62 - (6 V tolerance). Input/output can be specified in 1-bit units. P70 I/O Port 7. - Input port 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P120 P121 I/O Input Port 12. Analog input 1-bit I/O port and 2-bit input only port. Note . P120 can be set to analog input port Input port For only P120, input/output can be specified in 1-bit units. P122 ANI19 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be specified by a software setting at input port. P137 Input Port 13. Input port INTP0 Port 14. Analog input ANI18 1-bit I/O port. Note P147 can be set to analog input . port 1-bit input only port. P147 I/O Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 53 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.6 36-pin products (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI00/TxD1 TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P10 I/O P11 Port 1. Input port (TI07)/(TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/TOOLRxD/ buffer. SDA00/(TI06)/(TO06) Output of P10 to P15, and P17 can be set to N-ch open-drain P12 SO00/TxD0/TOOLTxD output (VDD tolerance). /(TI05)/(TO05) Input/output can be specified in 1-bit units. P13 SCK00/SCL00 8-bit I/O port. Use of an on-chip pull-up resistor can be specified by a TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02)/(TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 P20 TI02/TO02/(TxD0) I/O P21 P22 Port 2. Analog input ANI0/AVREFP 6-bit I/O port. Note Can be set to analog input . port ANI1/AVREFM ANI2 Input/output can be specified in 1-bit units. P23 ANI3 P24 ANI4 P25 ANI5 P30 I/O P31 Port 3. Input port INTP3/SCK11/SCL11 2-bit I/O port. TI03/TO03/INTP4/PCL Input/output can be specified in 1-bit units. BUZ0 Use of an on-chip pull-up resistor can be specified by a software setting at input port. P40 I/O Port 4. Input port TOOL0 1-bit I/O port. Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 54 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O Function Port 5. After Reset Input port 2-bit I/O port. P51 Alternate Function INTP1/SI11/SDA11 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 I/O Port 6. Input port 3-bit I/O port. P61 SCLA0 SDAA0 Output of P60 to P62 can be set to N-ch open-drain output P62 - (6 V tolerance). Input/output can be specified in 1-bit units. P70 I/O Port 7. Input port 3-bit I/O port. P71 SI21/SDA21 Output of P71 can be set to N-ch open-drain output P72 SCK21/SCL21 SO21 (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P120 P121 I/O Input Port 12. Analog input 1-bit I/O port and 2-bit input port. Note . P120 can be set to analog input port Input port For only P120, input/output can be specified in 1-bit units. P122 ANI19 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be specified by a software setting at input port. P137 Input Port 13. Input port INTP0 Port 14. Analog input ANI18 1-bit I/O port. Note P147 can be set to analog input . port 1-bit input port. P147 I/O Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 55 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.7 40-pin products (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI00/TxD1 TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P10 I/O P11 Port 1. Input port (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/TOOLRxD/ buffer. SDA00/(TI06)/(TO06) Output of P10 to P15, and P17 can be set to N-ch open-drain P12 SO00/TxD0/TOOLTxD output (VDD tolerance). /(TI05)/(TO05) Input/output can be specified in 1-bit units. P13 SCK00/SCL00/(TI07)/ 8-bit I/O port. Use of an on-chip pull-up resistor can be specified by a TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02)/(TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 P20 TI02/TO02/(TxD0) I/O P21 P22 Port 2. Analog input ANI0/AVREFP 7-bit I/O port. Note Can be set to analog input . port ANI1/AVREFM ANI2 Input/output can be specified in 1-bit units. P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P30 I/O Port 3. Input port 2-bit I/O port. SCK11/SCL11 Input/output can be specified in 1-bit units. P31 TI03/TO03/INTP4/PCL Use of an on-chip pull-up resistor can be specified by a BUZ0 software setting at input port. P40 I/O Port 4. INTP3/RTC1HZ/ Input port TOOL0 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 56 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O Function Port 5. After Reset Input port 2-bit I/O port. P51 Alternate Function INTP1/SI11/SDA11 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 I/O Port 6. Input port 3-bit I/O port. P61 SCLA0 SDAA0 Output of P60 to P62 can be set to N-ch open-drain output P62 - (6 V tolerance). Input/output can be specified in 1-bit units at input port. P70 I/O Port 7. Input port 4-bit I/O port. P71 KR1/SI21/SDA21 Output of P71 can be set to N-ch open-drain output P72 KR2/SO21 (VDD tolerance). P73 KR0/SCK21/SCL21 KR3 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P120 P121 I/O Input Port 12. Analog input 1-bit I/O port and 4-bit input only port. Note . P120 can be set to analog input port For only P120, input/output can be specified in 1-bit units. Input port For only P120, use of an on-chip pull-up resistor can be P122 XT1 P124 P137 X1 X2/EXCLK specified by a software setting at input port. P123 ANI19 XT2/EXCLKS Input Port 13. Input port INTP0 Port 14. Analog input ANI18 1-bit I/O port. Note . P147 can be set to analog input port 1-bit input only port. P147 I/O Input/output can be specified. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 57 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.8 44-pin products (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI00/TxD1 TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P10 I/O P11 Port 1. Input port (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/TOOLRxD/ buffer. SDA00/(TI06)/(TO06) Output of P10 to P15, and P17 can be set to N-ch open-drain P12 SO00/TxD0/TOOLTxD output (VDD tolerance). /(TI05)/(TO05) Input/output can be specified in 1-bit units. P13 SCK00/SCL00/(TI07)/ 8-bit I/O port. Use of an on-chip pull-up resistor can be specified by a TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02)/(TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 P20 TI02/TO02/(TxD0) I/O P21 P22 Port 2. Analog input ANI0/AVREFP 8-bit I/O port. Note Can be set to analog input . port ANI1/AVREFM ANI2 Input/output can be specified in 1-bit units. P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 P30 I/O Port 3. Input port 2-bit I/O port. SCK11/SCL11 Input/output can be specified in 1-bit units. P31 TI03/TO03/INTP4/PCL Use of an on-chip pull-up resistor can be specified by a BUZ0 software setting at input port. P40 P41 I/O Port 4. 2-bit I/O port. INTP3/RTC1HZ/ Input port TOOL0 TI07/TO07 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 58 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O Function Port 5. After Reset Input port 2-bit I/O port. P51 Alternate Function INTP1/SI11/SDA11 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 I/O Input port 4-bit I/O port. P61 SCLA0 SDAA0 Output of P60 to P63 can be set to N-ch open-drain output P62 P63 P70 Port 6. I/O (6 V tolerance). - Input/output can be specified in 1-bit units. - Port 7. Input port 4-bit I/O port. P71 KR1/SI21/SDA21 Output of P71 can be set to N-ch open-drain output P72 KR2/SO21 (VDD tolerance). P73 KR0/SCK21/SCL21 KR3 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P120 P121 I/O Input Port 12. Analog input 1-bit I/O port and 4-bit input only port. Note . P120 can be set to analog input port Input port For only P120, input/output can be specified in 1-bit units. P122 XT1 specified by a software setting at input port. P124 P137 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be P123 ANI19 XT2/EXCLKS Input Port 13. Input port INTP0 1-bit input only port. P146 P147 I/O Port 14. Input port 2-bit I/O port. Note P147 can be set to analog input . Analog input - ANI18 port Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 59 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.9 48-pin products (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI00/TxD1 TO00/RxD1 Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P10 I/O P11 Port 1. Input port (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/TOOLRxD/ buffer. SDA00/(TI06)/(TO06) Output of P10 to P15, and P17 can be set to N-ch open-drain P12 SO00/TxD0/TOOLTxD output (VDD tolerance). /(TI05)/(TO05) Input/output can be specified in 1-bit units. P13 SCK00/SCL00/(TI07)/ 8-bit I/O port. Use of an on-chip pull-up resistor can be specified by a TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02)/(TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 P20 TI02/TO02/(TxD0) I/O P21 P22 Port 2. Analog input ANI0/AVREFP 8-bit I/O port. Note Can be set to analog input . port ANI1/AVREFM ANI2 Input/output can be specified in 1-bit units. P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 P30 I/O Port 3. Input port 2-bit I/O port. SCK11/SCL11 Input/output can be specified in 1-bit units. P31 TI03/TO03/INTP4/ Use of an on-chip pull-up resistor can be specified by a (PCLBUZ0) software setting at input port. P40 P41 I/O Port 4. 2-bit I/O port. INTP3/RTC1HZ/ Input port TOOL0 TI07/TO07 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 60 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name P50 I/O I/O Function Port 5. After Reset Input port 2-bit I/O port. P51 Alternate Function INTP1/SI11/SDA11 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 I/O Input port 4-bit I/O port. P61 SCLA0 SDAA0 Output of P60 to P63 can be set to N-ch open-drain output P62 P63 P70 Port 6. I/O (6 V tolerance). - Input/output can be specified in 1-bit units. - Port 7. Input port 6-bit I/O port. P71 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 KR0/SCK21/SCL21 KR2/SO21 (VDD tolerance). P73 Input/output can be specified in 1-bit units. KR3/SO01 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8/SI01/ software setting at input port. SDA01 P75 KR5/INTP9/SCK01/ SCL01 P120 P121 I/O Input Port 12. Analog input 1-bit I/O port and 4-bit input only port. Note P120 can be set to analog input . port Input port For only P120, input/output can be specified in 1-bit units. P122 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be P123 ANI19 XT1 specified by a software setting at input port. P124 XT2/EXCLKS - Output Port 13. Output port P137 Input 1-bit output port and 1-bit input port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 P130 P146 P147 3-bit I/O port. Note . P147 can be set to analog input Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a - Analog input ANI18 port software setting at input port. <R> Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 61 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.10 52-pin products (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 4-bit I/O port. P01 Alternate Function TI00 TO00 Input of P01 and P03 can be set to TTL input buffer. P02 Output of P00, P02 and P03 can be set to N-ch open-drain P03 output (VDD tolerance). Note 1 . P02 and P03 can be set to analog input Analog input ANI17/TxD1 port ANI16/RxD1 Input port SCK00/SCL00/(TI07)/ Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. I/O P10 P11 Port 1. 8-bit I/O port. (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/TOOLRxD/ buffer. SDA00/(TI06)/(TO06) Output of P10 to P15, and P17 can be set to N-ch open-drain P12 SO00/TxD0/TOOLTxD output (VDD tolerance). /(TI05)/(TO05) Input/output can be specified in 1-bit units. P13 Use of an on-chip pull-up resistor can be specified by a TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02)/(TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 TI02/TO02/(TxD0) I/O P20 P21 P22 Port 2. Analog input ANI0/AVREFP 8-bit I/O port. Note 2 Can be set to analog input . port ANI1/AVREFM ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 P30 I/O Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. P31 Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> ANI2 Input/output can be specified in 1-bit units. P23 Input port INTP3/RTC1HZ/ SCK11/SCL11 TI03/TO03/INTP4/ (PCLBUZ0) Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 62 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name I/O I/O P40 Function Port 4. After Reset Input port 2-bit I/O port. P41 Alternate Function TOOL0 TI07/TO07 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. I/O P50 Port 5. Input port 2-bit I/O port. P51 INTP1/SI11/SDA11 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P60 I/O Port 6. Input port 4-bit I/O port. P61 SCLA0 SDAA0 Output of P60 to P63 can be set to N-ch open-drain output P62 P63 P70 I/O (6 V tolerance). - Input/output can be specified in 1-bit units at input port. - Port 7. Input port 8-bit I/O port. P71 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 KR0/SCK21/SCL21 KR2/SO21 (VDD tolerance). P73 Input/output can be specified in 1-bit units. KR3/SO01 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8/SI01/ software setting at input port. SDA01 P75 KR5/INTP9/SCK01/ SCL01 P76 KR6/INTP10/(RxD2) P77 KR7/INTP11/(TxD2) P120 I/O P121 Input Port 12. Analog input 1-bit I/O port and 4-bit input only port. Note P120 can be set to analog input . port Input port For only P120, input/output can be specified in 1-bit units. P122 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be P123 ANI19 XT1 specified by a software setting at input port. P124 XT2/EXCLKS - Output Port 13. Output port P137 Input 1-bit output port and 1-bit input only port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 P130 3-bit I/O port. Note . P147 can be set to analog input P146 P147 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a - Analog input ANI18 port software setting at input port. <R> Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 63 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.11 64-pin products (1/2) Function Name I/O I/O P00 P01 P02 P03 P04 P05 Function After Reset Port 0. 7-bit I/O port. Input of P01, P03, and P04 can be set to TTL input buffer. Output of P00 and P02 to P04 can be set to N-ch open-drain output (EVDD tolerance). Note 1 . P02 and P03 can be set to analog input Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port Port 1. 8-bit I/O port. Input of P10, P11, and P13 to P17 can be set to TTL input buffer. Output of P10 to P15, and P17 can be set to N-ch open-drain output (EVDD tolerance). Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port TI00 TO00 Analog input port Input port ANI17/SO10/TxD1 ANI16/SI10/RxD1/ SDA10 SCK10/SCL10 TI05/TO05 P06 TI06/TO06 I/O P10 P11 P12 P13 SCK00/SCL00/(TI07)/ (TO07) SI00/RxD0/ TOOLRxD/SDA00/ (TI06)/(TO06) SO00/TxD0/TOOLTxD/ (INTP5)/(TI05)/(TO05) TxD2/SO20/(SDAA0)/ (TI04)/(TO04) P14 RxD2/SI20/SDA20/ (SCLA0)/(TI03)/ (TO03) P15 SCK20/SCL20/(TI02)/ (TO02) P16 TI01/TO01/INTP5/ (SI00)/(RxD0) P17 TI02/TO02/(SO00)/ (TxD0) P20 I/O P21 P22 Port 2. 8-bit I/O port. Note 2 . Can be set to analog input Input/output can be specified in 1-bit units. Analog input port ANI0/AVREFP ANI1/AVREFM ANI2 P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 I/O P30 P31 P40 I/O P41 P42 P43 <R> Alternate Function Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port Port 4. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port INTP3/RTC1HZ/ SCK11/SCL11 TI03/TO03/INTP4/ (PCLBUZ0) TOOL0 TI07/TO07 TI04/TO04 - Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 64 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name I/O I/O P50 Function Port 5. After Reset Input port 6-bit I/O port. P51 (INTP10) Output of P50 can be set to N-ch open-drain output (EVDD P53 tolerance). P54 Input/output can be specified in 1-bit units. (INTP11) - Use of an on-chip pull-up resistor can be specified by a P55 (PCLBUZ1)/(SCK00) software setting at input port. P60 I/O Port 6. Input port 4-bit I/O port. P61 INTP1/SI11/SDA11 INTP2/SO11 Input of P55 can be set to TTL input buffer. P52 Alternate Function SCLA0 SDAA0 Output of P60 to P63 can be set to N-ch open-drain output P62 P63 I/O P70 (6 V tolerance). - Input/output can be specified in 1-bit units. - Port 7. Input port 8-bit I/O port. P71 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 KR0/SCK21/SCL21 KR2/SO21 (EVDD tolerance). P73 Input/output can be specified in 1-bit units. KR3/SO01 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8/SI01/ software setting at input port. SDA01 P75 KR5/INTP9/SCK01/ SCL01 P76 KR6/INTP10/(RxD2) P77 KR7/INTP11/(TxD2) P120 I/O P121 Input Port 12. Analog input 1-bit I/O port and 4-bit input only port. Note P120 can be set to analog input . port For only P120, input/output can be specified in 1-bit units. Input port X1 P122 For only P120, use of an on-chip pull-up resistor can be X2/EXCLK P123 specified by a software setting at input port. XT1 P124 XT2/EXCLKS - Output Port 13. Output port P137 Input 1-bit output port and 1-bit input only port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 P130 4-bit I/O port. Note P147 can be set to analog input . P141 P146 PCLBUZ1/INTP7 - Input/output can be specified in 1-bit units. P147 <R> ANI19 Use of an on-chip pull-up resistor can be specified by a Analog input software setting at input port. port ANI18 Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 65 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.12 80-pin products (1/3) Function Name P00 I/O I/O Function Port 0. After Reset Input port 7-bit I/O port. P01 Alternate Function TI00 TO00 Input of P01, P03 and P04 can be set to TTL input buffer. P02 Output of P00, P02 to P04 can be set to N-ch open-drain Analog input ANI17/SO10/TxD1 ANI16/SI10/RxD1/ P03 output (EVDD tolerance). Note 1 . P02 and P03 can be set to analog input port P04 Input/output can be specified in 1-bit units. Input port SDA10 Use of an on-chip pull-up resistor can be specified by a P05 SCK10/SCL10 TI05/TO05 software setting at input port. TI06/TO06 P06 I/O P10 P11 Port 1. Input port (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/ buffer. TOOLRxD/SDA00/ Output of P10 to P15, and P17 can be set to N-ch open-drain (TI06)/(TO06) output (EVDD tolerance). P12 SO00/TxD0/TOOLTxD Input/output can be specified in 1-bit units. /(INTP5)/(TI05)/(TO05) Use of an on-chip pull-up resistor can be specified by a P13 SCK00/SCL00/(TI07)/ 8-bit I/O port. TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) SCK20/SCL20/(TI02)/ P15 (TO02) TI01/TO01/INTP5/ P16 (SI00)/(RxD0) TI02/TO02/(SO00)/ P17 (TxD0) I/O P20 P21 P22 Port 2. Analog input ANI0/AVREFP 8-bit I/O port. Note 2 . Can be set to analog input port ANI1/AVREFM ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 P30 I/O Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. P31 Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> ANI2 Input/output can be specified in 1-bit units. P23 Input port INTP3/RTC1HZ/ SCK11/SCL11 TI03/TO03/INTP4/ (PCLBUZ0) Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 66 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/3) Function Name P40 I/O I/O Function Port 4. After Reset Input port 6-bit I/O port. P41 TOOL0 TI07/TO07 Input of P43 and P44 can be set to TTL input buffer. P42 Alternate Function TI04/TO04 Output of P43 to P45 can be set to N-ch open-drain output P43 (EVDD tolerance). SCK01/SCL01 P44 Input/output can be specified in 1-bit units. SI01/SDA01 Use of an on-chip pull-up resistor can be specified by a P45 P50 SO01 software setting at input port. I/O Port 5. Input port 6-bit I/O port. P51 INTP1/SI11/SDA11 INTP2/SO11 Input of P53 to P55 can be set to TTL input buffer. P52 P53 Output of P50, P52 to P55 can be set to N-ch open-drain SO31 output (EVDD tolerance). SI31/SDA31 Input/output can be specified in 1-bit units. P54 SCK31/SCL31 Use of an on-chip pull-up resistor can be specified by a P55 P60 (PCLBUZ1)/(SCK00) software setting at input port. I/O Port 6. Input port 8-bit I/O port. P61 SDAA0 Output of P60 to P63 can be set to N-ch open-drain output P62 SCLA0 SCLA1 (6 V tolerance). P63 Input/output can be specified in 1-bit units. SDAA1 P64 For P64 to P67, use of an on-chip pull-up resistor can be TI10/TO10 P65 specified by a software setting at input port. TI11/TO11 P66 TI12/TO12 P67 TI13/TO13 P70 I/O Port 7. Input port 8-bit I/O port. P71 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 KR0/SCK21/SCL21 KR2/SO21 (EVDD tolerance). P73 Input/output can be specified in 1-bit units. KR3 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8 software setting at input port. P75 KR5/INTP9 P76 KR6/INTP10/(RxD2) P77 KR7/INTP11/(TxD2) P100 I/O Port 10. Analog input 1-bit I/O port. port P100 can be set to analog input ANI20 Note . Use of an on-chip pull-up resistor can be specified by a software setting at input port. P110 P111 I/O Port 11. 2-bit I/O port. Input port (INTP10) (INTP11) Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 67 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/3) Function Name P120 P121 I/O Function After Reset I/O Port 12. Analog input port Input 1-bit I/O port and 4-bit input only port. Note 1 . P120 can be set to analog input Input port For only P120, input/output can be specified in 1-bit units. P122 ANI19 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be P123 Alternate Function XT1 specified by a software setting at input port. P124 XT2/EXCLKS - Output Port 13. Output port P137 Input 1-bit output port and 1-bit input port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 P130 7-bit I/O port. P141 PCLBUZ1/INTP7 Input of P142 and P143 can be set to TTL input buffer. P142 SCK30/SCL30 Output of P142 to P144 can be set to N-ch open-drain output P143 SI30/RxD3/SDA30 (EVDD tolerance). Note 1 . P147 can be set to analog input P144 SO30/TxD3 Input/output can be specified in 1-bit units. P146 - Use of an on-chip pull-up resistor can be specified by a P147 software setting at input port. Analog input ANI18 port P150 P151 P152 I/O Port 15. Analog input ANI8 4-bit I/O port. Note 2 Can be set to analog input . port ANI9 Input/output can be specified in 1-bit units. ANI11 P153 <R> ANI10 Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 68 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.13 100-pin products (1/3) Function Name P00 I/O I/O Function Port 0. After Reset Input port 7-bit I/O port. P01 Alternate Function TI00 TO00 Input of P01, P03 and P04 can be set to TTL input buffer. P02 Output of P00, P02 to P04 can be set to N-ch open-drain P03 output (EVDD tolerance). Note 1 . P02 and P03 can be set to analog input Input/output can be specified in 1-bit units. P04 Use of an on-chip pull-up resistor can be specified by a P05 Analog input ANI17/SO10/TxD1 port ANI16/SI10/RxD1/ SDA10 Input port SCK10/SCL10 - software setting at input port. - P06 I/O P10 P11 Port 1. Input port (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/ buffer. TOOLRxD/SDA00/ Output of P10 to P15, and P17 can be set to N-ch open-drain (TI06)/(TO06) output (EVDD tolerance). P12 SO00/TxD0/TOOLTxD/ Input/output can be specified in 1-bit units. (INTP5)/(TI05)/(TO05) Use of an on-chip pull-up resistor can be specified by a P13 SCK00/SCL00/(TI07)/ 8-bit I/O port. TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) SCK20/SCL20/(TI02)/ P15 (TO02) TI01/TO01/INTP5/ P16 (SI00)/(RxD0) TI02/TO02/(SO00)/ P17 (TxD0) I/O P20 P21 P22 Port 2. Analog input ANI0/AVREFP 8-bit I/O port. Note 2 . Can be set to analog input port ANI1/AVREFM P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 P30 I/O Port 3. 2-bit I/O port. Input/output can be specified in 1-bit units. P31 Use of an on-chip pull-up resistor can be specified by a software setting at input port. <R> ANI2 Input/output can be specified in 1-bit units. Input port INTP3/RTC1HZ/ SCK11/SCL11 TI03/TO03/INTP4/ (PCLBUZ0) Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 69 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/3) Function Name P40 I/O I/O Function Port 4. After Reset Input port Alternate Function TOOL0 8-bit I/O port. P41 - Input of P43 and P44 can be set to TTL input buffer. P42 TI04/TO04 Output of P43 to P45 can be set to N-ch open-drain output P43 (EVDD tolerance). SCK01/SCL01 P44 Input/output can be specified in 1-bit units. SI01/SDA01 Use of an on-chip pull-up resistor can be specified by a P45 SO01 software setting at input port. P46 INTP1/TI05/TO05 P47 INTP2 P50 I/O Port 5. Input port 8-bit I/O port. P51 SI11/SDA11 SO11 Input of P53 to P55 can be set to TTL input buffer. P52 SO31 Output of P50, P52 to P55 can be set to N-ch open-drain P53 output (EVDD tolerance). SI31/SDA31 P54 Input/output can be specified in 1-bit units. SCK31/SCL31 Use of an on-chip pull-up resistor can be specified by a P55 (PCLBUZ1)/(SCK00) software setting at input port. P56 (INTP1) P57 (INTP3) P60 I/O Port 6. Input port 8-bit I/O port. P61 SDAA0 Output of P60 to P63 can be set to N-ch open-drain output P62 SCLA0 SCLA1 (6 V tolerance). P63 Input/output can be specified in 1-bit units. SDAA1 P64 For P64 to P67, use of an on-chip pull-up resistor can be TI10/TO10 specified by a software setting at input port. P65 TI11/TO11 P66 TI12/TO12 P67 TI13/TO13 P70 I/O Port 7. Input port 8-bit I/O port. P71 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 KR0/SCK21/SCL21 KR2/SO21 (EVDD tolerance). P73 Input/output can be specified in 1-bit units. KR3 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8 software setting at input port. P75 KR5/INTP9 P76 KR6/INTP10/(RxD2) P77 KR7/INTP11/(TxD2) P80 P81 P82 I/O Port 8. 8-bit I/O port. Input of P80 and P81 can be set to TTL input buffer. Output of P80 to P82 can be set to N-ch open-drain output P83 (EVDD tolerance). P84 Input/output can be specified in 1-bit units. P85 Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input port (SCK10)/(SCL10) (SI10)/(RxD1)/(SDA10) (SO10)/(TxD1) - (INTP6) (INTP7) P86 (INTP8) P87 (INTP9) Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 70 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/3) Function Name P100 I/O I/O P101 Function After Reset Port 10. Analog input 3-bit I/O port. Note 1 . P100 can be set to analog input port ANI20 - Input port Input/output can be specified in 1-bit units. P102 Alternate Function TI06/TO06 Use of an on-chip pull-up resistor can be specified by a software setting at input port. I/O P110 Port 11. Input port 2-bit I/O port. P111 (INTP10) (INTP11) Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P120 I/O P121 Input Port 12. Analog input 1-bit I/O port and 4-bit input only port. Note 1 P120 can be set to analog input . port Input port For only P120, input/output can be specified in 1-bit units. P122 X1 X2/EXCLK For only P120, use of an on-chip pull-up resistor can be P123 ANI19 XT1 specified by a software setting at input port. P124 XT2/EXCLKS - Output Port 13. Output port P137 Input 1-bit output port and 1-bit input port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 P130 8-bit I/O port. P141 PCLBUZ1/INTP7 Input of P142 and P143 can be set to TTL input buffer. P142 SCK30/SCL30 Output of P142 to P144 can be set to N-ch open-drain output P143 SI30/RxD3/SDA30 (EVDD tolerance). Note 1 . P147 can be set to analog input P144 SO30/TxD3 Input/output can be specified in 1-bit units. P145 TI07/TO07 Use of an on-chip pull-up resistor can be specified by a P146 (INTP4) software setting at input port. Analog input P147 ANI18 port P150 I/O P151 P152 <R> Port 15. Analog input ANI8 7-bit I/O port. Note 2 Can be set to analog input . port ANI9 Input/output can be specified in 1-bit units. ANI10 P153 ANI11 P154 ANI12 P155 ANI13 P156 ANI14 Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 71 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.1.14 128-pin products (1/4) Function Name P00 I/O I/O Function Port 0. After Reset Input port 8-bit I/O port. P01 Input of P01, P03 and P04 can be set to TTL input buffer. P02 Output of P00, P02 to P04 can be set to N-ch open-drain P03 output (EVDD tolerance). Note 1 . P02 and P03 can be set to analog input P04 Input/output can be specified in 1-bit units. Alternate Function TI00 TO00 Analog input ANI17/SO10/TxD1 port ANI16/SI10/RxD1/ SDA10 Input port SCK10/SCL10 Use of an on-chip pull-up resistor can be specified by a P05 - software setting at input port. - P06 - P07 I/O P10 P11 Port 1. Input port 8-bit I/O port. (TO07) Input of P10, P11, and P13 to P17 can be set to TTL input SI00/RxD0/ buffer. TOOLRxD/SDA00/ Output of P10 to P15, and P17 can be set to N-ch open-drain (TI06)/(TO06) output (EVDD tolerance). P12 SO00/TxD0/TOOLTxD/ Input/output can be specified in 1-bit units. (INTP5)/(TI05)/(TO05) Use of an on-chip pull-up resistor can be specified by a P13 SCK00/SCL00/(TI07)/ TxD2/SO20/(SDAA0)/ software setting at input port. (TI04)/(TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/(TI03)/ (TO03) SCK20/SCL20/(TI02)/ P15 (TO02) TI01/TO01/INTP5/ P16 (SI00)/(RxD0) TI02/TO02/(SO00)/ P17 (TxD0) I/O P20 P21 P22 <R> Port 2. Analog input ANI0/AVREFP 8-bit I/O port. Note 2 Can be set to analog input . port ANI1/AVREFM Input/output can be specified in 1-bit units. ANI2 P23 ANI3 P24 ANI4 P25 ANI5 P26 ANI6 P27 ANI7 Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 72 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/4) Function Name I/O I/O P30 Function Port 3. After Reset Input port 8-bit I/O port. Note P35 to P37 can be set to analog input . P31 Alternate Function INTP3/RTC1HZ TI03/TO03/INTP4/ (PCLBUZ0) Input/output can be specified in 1-bit units. P32 P33 Use of an on-chip pull-up resistor can be specified by a - software setting at input port. - - P34 P35 Analog input ANI23 P36 port ANI22 ANI21 P37 I/O P40 Input port TOOL0 8-bit I/O port. P41 - Input of P43 and P44 can be set to TTL input buffer. P42 TI04/TO04 Output of P43 to P45 can be set to N-ch open-drain output P43 (EVDD tolerance). SCK01/SCL01 P44 Input/output can be specified in 1-bit units. SI01/SDA01 Use of an on-chip pull-up resistor can be specified by a P45 SO01 software setting at input port. P46 INTP1/TI05/TO05 P47 INTP2 I/O P50 Port 5. - Input port 8-bit I/O port. P51 - Input of P53 to P55 can be set to TTL input buffer. P52 SO31 Output of P50, P52 to P55 can be set to N-ch open-drain P53 output (EVDD tolerance). SI31/SDA31 P54 Input/output can be specified in 1-bit units. SCK31/SCL31 Use of an on-chip pull-up resistor can be specified by a P55 (PCLBUZ1)/(SCK00) software setting at input port. P56 (INTP1) P57 (INTP3) I/O P60 Port 6. 8-bit I/O port. P61 Output of P60 to P63 can be set to N-ch open-drain output P62 (6 V tolerance). Input port SCLA0 SDAA0 SCLA1 P63 Input/output can be specified in 1-bit units. SDAA1 P64 For P64 to P67, use of an on-chip pull-up resistor can be TI10/TO10 specified by a software setting at input port. P65 <R> Port 4. TI11/TO11 P66 TI12/TO12 P67 TI13/TO13 Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 73 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/4) Function Name P70 I/O I/O Port 7. After Reset Input port 8-bit I/O port. P71 Alternate Function KR0/SCK21/SCL21 KR1/SI21/SDA21 Output of P71 and P74 can be set to N-ch open-drain output P72 KR2/SO21 (EVDD tolerance). P73 Input/output can be specified in 1-bit units. KR3 P74 Use of an on-chip pull-up resistor can be specified by a KR4/INTP8 software setting at input port. P75 KR5/INTP9 P76 KR6/INTP10/(RxD2) P77 KR7/INTP11/(TxD2) P80 I/O P81 Port 8. (SCK10)/(SCL10) 8-bit I/O port. (SI10)/(RxD1)/(SDA10) Input of P80 and P81 can be set to TTL input buffer. P82 (SO10)/(TxD1) Output of P80 to P82 can be set to N-ch open-drain output P83 (EVDD tolerance). P84 Input/output can be specified in 1-bit units. - (INTP6) Use of an on-chip pull-up resistor can be specified by a P85 (INTP7) software setting at input port. P86 (INTP8) P87 (INTP9) P90 I/O Port 9. - Input port 8-bit I/O port. P91 - Output of P96 can be set to N-ch open-drain output (EVDD tolerance). - P93 Input/output can be specified in 1-bit units. - P94 Use of an on-chip pull-up resistor can be specified by a - P92 software setting at input port. P95 SCK11/SCL11 P96 SI11/SDA11 P97 SO11 P100 P101 P102 P103 <R> Function I/O Port 10. Analog input 7-bit I/O port. Note . P100 can be set to analog input port Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. ANI20 - Input port TI06/TO06 TI14/TO14 P104 TI15/TO15 P105 TI16/TO16 P106 TI17/TO17 Note When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 74 RL78/G13 CHAPTER 2 PIN FUNCTIONS (4/4) Function Name I/O I/O P110 Function Port 11. After Reset Input port 8-bit I/O port. Note 1 P115 to P117 can be set to analog input . P111 P112 Alternate Function (INTP10) (INTP11) - Input/output can be specified in 1-bit units. P113 Use of an on-chip pull-up resistor can be specified by a - P114 software setting at input port. - P115 Analog input ANI26 P116 port ANI25 ANI24 P117 P120 I/O P121 Input Port 12. Analog input 4-bit I/O port and 4-bit input port. Note 1 P120 can be set to analog input . port Input port For only P120, P125 to P127, input/output can be specified in P122 ANI19 X1 X2/EXCLK 1-bit units. P123 For only P120, P125 to P127, use of an on-chip pull-up XT1 P124 resistor can be specified by a software setting. at input port XT2/EXCLKS P125 - I/O P126 - P127 - - Output Port 13. Output port P137 Input 1-bit output port and 1-bit input port. Input port INTP0 P140 I/O Port 14. Input port PCLBUZ0/INTP6 P130 8-bit I/O port. P141 PCLBUZ1/INTP7 Input of P142 and P143 can be set to TTL input buffer. P142 SCK30/SCL30 Output of P142 to P144 can be set to N-ch open-drain output P143 SI30/RxD3/SDA30 (EVDD tolerance). Note 1 . P147 can be set to analog input P144 SO30/TxD3 Input/output can be specified in 1-bit units. P145 TI07/TO07 Use of an on-chip pull-up resistor can be specified by a P146 (INTP4) software setting. at input port at input port Analog input P147 ANI18 port P150 I/O P151 P152 <R> Port 15. Analog input ANI8 7-bit I/O port. Note 2 Can be set to analog input . port ANI9 Input/output can be specified in 1-bit units. ANI10 P153 ANI11 P154 ANI12 P155 ANI13 P156 ANI14 Notes 1. When the each pin is used as input, specify them as either digital or analog in Port mode control register X (PMCX) (This register can be specified in 1-bit unit). <R> 2. Setting digital or analog to each pin can be done in A/D port configuration register (ADPC). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 75 RL78/G13 CHAPTER 2 PIN FUNCTIONS <R> 2.2 Functions other than port pins 2.2.1 With functions for each product (1/5) Function 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin 24-pin 20-pin Name ANI0 ANI1 ANI2 ANI3 - - - ANI4 - - - - - ANI5 - - - - - ANI6 - - - - - - ANI7 - - - - - - - ANI8 - - - - - - - - - - - ANI9 - - - - - - - - - - - ANI10 - - - - - - - - - - - ANI11 - - - - - - - - - - - ANI12 - - - - - - - - - - - - ANI13 - - - - - - - - - - - - ANI14 - - - - - - - - - - - - ANI16 - - - - ANI17 - - - - ANI18 ANI19 - - - ANI20 - - - - - - - - - - - ANI21 - - - - - - - - - - - - - ANI22 - - - - - - - - - - - - - ANI23 - - - - - - - - - - - - - ANI24 - - - - - - - - - - - - - ANI25 - - - - - - - - - - - - - ANI26 - - - - - - - - - - - - - INTP0 INTP1 - INTP2 - - - INTP3 INTP4 - INTP5 INTP6 - - - - - - - - INTP7 - - - - - - - - - - INTP8 - - - - - - - - INTP9 - - - - - - - - INTP10 - - - - - - - - - INTP11 - - - - - - - - - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 76 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/5) Function 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin 24-pin 20-pin Name KR0 - - - - - - KR1 - - - - - - KR2 - - - - - - KR3 - - - - - - KR4 - - - - - - - - KR5 - - - - - - - - KR6 - - - - - - - - - KR7 - - - - - - - - - PCLBUZ0 - PCLBUZ1 - - - REGC RTC1HZ - - - - - - RESET RxD0 RxD1 RxD2 - - - RxD3 - - - - - - - - - - - TxD0 TxD1 TxD2 - - - TxD3 - - - - - - - - - - - SCK00 SCK01 - - - - - - - - SCK10 - - - - - - - - - - SCK11 SCK20 - - - SCK21 - - - - - SCK30 - - - - - - - - - - - SCK31 - - - - - - - - - - - SCL00 SCL01 - - - - - - - - SCL10 - - - - - - - - - - SCL11 SCL20 - - - SCL21 - - - - - SCL30 - - - - - - - - - - - SCL31 - - - - - - - - - - - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 77 RL78/G13 CHAPTER 2 PIN FUNCTIONS (3/5) Function 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin 24-pin 20-pin Name SDA00 SDA01 - - - - - - - - SDA10 - - - - - - - - - - SDA11 SDA20 - - - SDA21 - - - - - SDA30 - - - - - - - - - - - SDA31 - - - - - - - - - - - SI00 SI01 - - - - - - - - SI10 - - - - - - - - - - SI11 SI20 - - - SI21 - - - - - SI30 - - - - - - - - - - - SI31 - - - - - - - - - - - SO00 SO01 - - - - - - - - SO10 - - - - - - - - - - SO11 SO20 - - - SO21 - - - - - SO30 - - - - - - - - - - - SO31 - - - - - - - - - - - SCLA0 - SCLA1 - - - - - - - - - - - SDAA0 - SDAA1 - - - - - - - - - - - TI00 TI01 TI02 TI03 - TI04 () () () () () () () - - - TI05 () () () () () () () - - - TI06 () () () () () () () - - - TI07 () () () () - - - <R> Remark The checked function is available only when the bit corresponding to the function in the peripheral I/O redirection register (PIOR) is set to 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 78 RL78/G13 CHAPTER 2 PIN FUNCTIONS (4/5) Function 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin 24-pin 20-pin Name TI10 - - - - - - - - - - - TI11 - - - - - - - - - - - TI12 - - - - - - - - - - - TI13 - - - - - - - - - - - TI14 - - - - - - - - - - - - - TI15 - - - - - - - - - - - - - TI16 - - - - - - - - - - - - - TI17 - - - - - - - - - - - - - TO00 TO01 TO02 TO03 - TO04 () () () () () () () - - - TO05 () () () () () () () - - - TO06 () () () () () () () - - - TO07 () () () () - - - TO10 - - - - - - - - - - - TO11 - - - - - - - - - - - TO12 - - - - - - - - - - - TO13 - - - - - - - - - - - TO14 - - - - - - - - - - - - - TO15 - - - - - - - - - - - - - TO16 - - - - - - - - - - - - - TO17 - - - - - - - - - - - - - X1 X2 EXCLK XT1 - - - - - - XT2 - - - - - - EXCLKS - - - - - - <R> Remark The checked function is available only when the bit corresponding to the function in the peripheral I/O redirection register (PIOR) is set to 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 79 RL78/G13 CHAPTER 2 PIN FUNCTIONS (5/5) Function 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin 24-pin 20-pin Name VDD EVDD0 - - - - - - - - - - EVDD1 - - - - - - - - - - - - AVREFP AVREFM VSS EVSS0 - - - - - - - - - - EVSS1 - - - - - - - - - - - - TOOLRxD TOOLTxD TOOL0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 80 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.2.2 Pins for each product (pins other than port pins) (1/2) Function Name I/O Function ANI0 to ANI14, ANI16 to ANI26 Input A/D converter analog input (see Figure 11-46. Analog Input Pin Connection) INTP0 to INTP11 Input External interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. KR0 to KR7 Input PCLBUZ0, PCLBUZ1 Output - REGC Key interrupt input Clock output/buzzer output Pin for connecting regulator output stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 F). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. RTC1HZ RESET Output Real-time clock correction clock (1 Hz) output Input This is the active-low system reset input pin. When the external reset pin is not used, connect this pin directly or via a resistor to VDD. When the external reset pin is used, design the circuit based on VDD. RxD0 to RxD3 Input TxD0 to TxD3 Output SCK00, SCK01, SCK10, SCK11, I/O Output Serial clock I/O pins of serial interface CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, Serial clock output pins of serial interface IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31 SCL20, SCL21, SCL30, SCL31 SDA00, SDA01, SDA10, SDA11, Serial data output pins of serial interface UART0 to UART3 CSI30, and CSI31 SCK20, SCK21, SCK30, SCK31 SCL00, SCL01, SCL10, SCL11, Serial data input pins of serial interface UART0 to UART3 I/O Serial data I/O pins of serial interface IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31 SDA20, SDA21, SDA30, SDA31 SI00, SI01, SI10, SI11, SI20, Input SO00, SO01, SO10, SO11, Serial data input pins of serial interface CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, and CSI31 SI21, SI30, SI31 Output Serial data output pins of serial interface CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, and CSI31 SO20, SO21, SO30, SO31 SCLA0, SCLA1 I/O Serial clock I/O pins of serial interface IICA0, IICA1 SDAA0, SDAA1 I/O Serial data I/O pins of serial interface IICA0, IICA1 TI00 to TI07, TI10 to TI17 Input The pins for inputting an external count clock/capture trigger to 16-bit timers 00 to 07, 10 to 17 TO00 to TO07, TO10 to TO17 Output X1, X2 - EXCLK Timer output pins of 16-bit timers 00 to 07, 10 to 17 Resonator connection for main system clock Input External clock input for main system clock XT1, XT2 - Resonator connection for subsystem clock EXCLKS Input External clock input for subsystem clock Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 81 RL78/G13 CHAPTER 2 PIN FUNCTIONS (2/2) Function Name I/O Function - VDD <20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin, 40-pin, 44-pin, 48-pin, 52-pin> Positive power supply for all pins <64-pin, 80-pin, 100-pin, 128-pin > Positive power supply for P20 to P27, P121 to P124, P137, P150 to P156 and other than ports - EVDD0, EVDD1 Positive power supply for ports (other than P20 to P27, P121 to P124, P137, P150 to P156) AVREFP Input A/D converter reference potential (+ side) input AVREFM Input A/D converter reference potential (- side) input - VSS <20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin, 40-pin, 44-pin, 48-pin, 52-pin > Ground potential for all pins <64-pin, 80-pin, 100-pin, 128-pin > Ground potential for P20 to P27, P121 to P124, P137, P150 to P156 and other than ports - EVSS0, EVSS1 TOOLRxD Ground potential for ports (other than P20 to P27, P121 to P124, P137, P150 to P156) UART reception pin for the external device connection used during flash memory Input programming TOOLTxD Output UART transmission pin for the external device connection used during flash memory programming TOOL0 I/O Data I/O for flash memory programmer/debugger Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows. Table 2-2. Relationships Between P40/TOOL0 and Operation Mode After Reset Release P40/TOOL0 Operating mode VDD Normal operation mode 0V Flash memory programming mode For details, see 25.5 Programming Method. Remark Use bypass capacitors (about 0.1 F) as noise and latch up countermeasures with relatively thick wires at the shortest distance to VDD to VSS, EVDD0 to EVSS0 and EVDD1 to EVSS1 lines. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 82 RL78/G13 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-3 shows the types of pin I/O circuits and the recommended connections of unused pins. <R> Remark The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Port Function. Table 2-3. Connection of Unused Pins (128-pin products) (1/4) Pin Name I/O Circuit Type P00/TI00 8-R P01/TO00 5-AN P02/ANI17/SO10/TxD1 11-U P03/ANI16/SI10/RxD1/ 11-V I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Leave open. SDA10 P04/SCK10/SCL10 5-AN P05 8-R P06 P07 P10/SCK00/SCL00/(TI07)/ 5-AN (TO07) P11/SI00/RxD0/ TOOLRxD/SDA00/(TI06)/ (TO06) P12/SO00/TxD0/ 8-R TOOLTxD/(INTP5)/(TI05)/ (TO05) P13/TxD2/SO20/(SDAA0)/ 5-AN (TI04)/(TO04) P14/RxD2/SI20/SDA20/ (SCLA0)/(TI03)/(TO03) P15/SCK20/SCL20/(TI02)/ (TO02) P16/TI01/TO01/INTP5/ (SI00)/(RxD0) P17/TI02/TO02/(SO00)/ (TxD0) P20/ANI0/AVREFP 11-T Independently connect to VDD or VSS via a resistor. Output: Leave open. P21/ANI1/AVREFM P22/ANI2 Input: 11-G P23/ANI3 P24/ANI4 P25/ANI5 P26/ANI6 P27/ANI7 Remarks 1. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 83 RL78/G13 CHAPTER 2 PIN FUNCTIONS Table 2-3. Connection of Unused Pins (128-pin products) (2/4) Pin Name P30/INTP3/RTC1HZ I/O Circuit Type 8-R I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. P31/TI03/TO03/INTP4/ Output: Leave open. (PCLBUZ0) P32 P33 P34 P35/ANI23 11-U P36/ANI22 P37/ANI21 8-R P40/TOOL0 Input: Independently connect to EVDD0, EVDD1 or leave open. Output: Leave open. Input: P41 P43/SCK01/SCL01 Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. P42/TI04/TO04 5-AN Output: Leave open. P44/SI01/SDA01 8-R P45/SO01 P46/INTP1/TI05/TO05 P47/INTP2 P50 P51 P52/SO31 P53/SI31/SDA31 5-AN P54/SCK31/SCL31 P55/(PCLBUZ1)/(SCK00) 8-R P56/(INTP1) P57/(INTP3) <R> P60/SCLA0 13-R Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. P61/SDAA0 Output: Set the port's output latch to 0 and leave the pins open, P62/SCLA1 or set the port's output latch to 1 and independently P63/SDAA1 connect the pins to EVDD0 and EVDD1 or EVSS0 and EVSS1 via a resistor. P64/TI10/TO10 8-R P65/TI11/TO11 P66/TI12/TO12 Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. Output: Leave open. P67/TI13/TO13 Remarks 1. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). 3. For 64-pin products, I/O circuit type for P43, P53 and P54 pins is 8-R. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 84 RL78/G13 CHAPTER 2 PIN FUNCTIONS Table 2-3. Connection of Unused Pins (128-pin products) (3/4) Pin Name P70/KR0/SCK21/SCL21 I/O Circuit Type 8-R I/O I/O Recommended Connection of Unused Pins Input: Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. P71/KR1/SI21/SDA21 Output: Leave open. P72/KR2/SO21 P73/KR3 P74/KR4/INTP8 P75/KR5/INTP9 P76/KR6/INTP10/(RxD2) P77/KR7/INTP11/(TxD2) P80/(SCK10)/(SCL10) 5-AN P81/(SI10)/(RxD1)/ (SDA10) P82/(SO10)/(TxD1) 8-R P83 P84/(INTP6) P85/(INTP7) P86/(INTP8) P87/(INTP9) P90 P91 P92 P93 P94 P95/SCK11/SCL11 P96/SI11/SDA11 P97/SO11 P100/ANI20 11-U P101 8-R P102/TI06/TO06 P103/TI14/TO14 P104/TI15/TO15 P105/TI16/TO16 P106/TI17/TO17 P110/(INTP10) P111/(INTP11) P112 P113 P114 Remarks 1. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 85 RL78/G13 CHAPTER 2 PIN FUNCTIONS Table 2-3. Connection of Unused Pins (128-pin products) (4/4) Pin Name P115/ANI26 I/O Circuit Type 11-U I/O Recommended Connection of Unused Pins Input: I/O Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. P116/ANI25 Output: Leave open. P117/ANI24 P120/ANI19 P121/X1 37-C Input Independently connect to VDD or VSS via a resistor. 8-R I/O Input: P122/X2/EXCLK P123/XT1 P124/XT2/EXCLKS P125 Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 via a resistor. P126 Output: Leave open. P127 P130 3-C Output Leave open. P137/INTP0 2 Input Independently connect to VDD or VSS via a resistor. P140/PCLBUZ0/INTP6 8-R I/O Input: via a resistor. P141/PCLBUZ1/INTP7 P142/SCK30/SCL30 Independently connect to EVDD0, EVDD1 or EVSS0, EVSS1 Output: Leave open. 5-AN P143/SI30/RxD3/SDA30 P144/SO30/TxD3 8-R P145/TI07/TO07 P146/(INTP4) P147/ANI18 11-U P150/ANI8 11-G Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P151/ANI9 P152/ANI10 P153/ANI11 P154/ANI12 P155/ANI13 P156/ANI14 RESET 2 Input - REGC - Connect directly or via a resistor to VDD. Connect to VSS via capacitor (0.47 to 1 F). Remarks 1. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 86 RL78/G13 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 3-C EVDD P-ch IN data OUT N-ch Schmitt-triggered input with hysteresis characteristics EVSS Type 5-AN Type 8-R EVDD EVDD pull-up enable P-ch EVDD data P-ch output disable N-ch pullup enable P-ch EVDD IN/OUT data P-ch EVSS IN/OUT CMOS output disable N-ch EVSS TTL input characteristic Type 13-R Type 37-C X2, XT2 N-ch amp enable P-ch data output disable input enable EVSS N-ch IN/OUT X1, XT1 input enable R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 87 RL78/G13 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 11-G Type 11-T VDD data P-ch VDD IN/OU data P-ch output disable N-ch IN/OU VSS output disable N-ch P-ch Comparator VSS + _ Comparator N-ch P-ch Series resistor string voltage + _ VSS N-ch Series resistor string voltage VSS input enable input enable P-ch AVREFP, AVREFM N-ch Type 11-U Type 11-V EVDD EVDD pull-up enable pull-up enable P-ch EVDD P-ch data P-ch output disable N-ch EVDD data IN/OUT P-ch IN/OUT output disable N-ch EVSS EVSS CMOS input enable P-ch Comparator TTL input characteristic + _ N-ch P-ch Comparator + _ Series resistor string voltage N-ch VSS Series resistor string voltage VSS R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 88 RL78/G13 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/G13 can access a 1 MB memory space. Figures 3-1 to 3-10 show the memory maps. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 89 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (R5F100xA, R5F101xA(x = 6 to 8, A to C, E to G)) 03FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 2 KB FF700H FF6FFH Program area Reserved F4000H F3FFFH F2000H F1FFFH F1000H F0FFFH Mirror 8 KB 01FFFH Data flash memoryNote 5 4 KB 010CEH 010CDH Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010C0H 010BFH 01080H 0107FH F0000H EFFFFH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Program area Reserved 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH Program memory space <R> 04000H 03FFFH 00000H On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 16 KB 00000H Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xA only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 90 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L)) 07FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 2 KB FF700H FF6FFH Program area Reserved F8000H F7FFFH F2000H F1FFFH F1000H F0FFFH Mirror 24 KB 01FFFH Data flash memoryNote 5 4 KB 010CEH 010CDH Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH Program memory space 08000H 07FFFH Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 32KB 00000H 00000H <R> On-chip debug security ID setting areaNote 3 10 bytes Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xC only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 91 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (R5F100xD, R5F101xD(x = 6 to 8, A to C, E to G, J, L)) 0BFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 3 KB FF300H FF2FFH Program area Reserved FC000H FBFFFH Mirror 40 KB F2000H F1FFFH F1000H F0FFFH 01FFFH Data flash memoryNote 5 4 KB 010CEH 010CDH Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 0C000H 0BFFFH Program memory space Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 48 KB 00000H 00000H <R> On-chip debug security ID setting areaNote 3 10 bytes Notes 1. Use of the area FFE20H to FFEDFH and FF300H to FF309H is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xD only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 92 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (R5F100xE, R5F101xE(x = 6 to 8, A to C, E to G, J, L)) 0FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 4 KB Program area FEF00H FEEFFH Mirror 51.75 KB F2000H F1FFFH F1000H F0FFFH 01FFFH Data flash memoryNote 5 4 KB Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 10000H 0FFFFH Program memory space <R> Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 64 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEDFH and FEF00H to FF309H is prohibited when using the selfprogramming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xE only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 93 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (R5F100xF, R5F101xF(x = A to C, E to G, J, L, M, P)) 17FFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 8 KB Program area FDF00H FDEFFH Mirror 43.75 KB F3000H F2FFFH F1000H F0FFFH 01FFFH Data flash memoryNote 5 8 KB Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 18000H 17FFFH Program memory space <R> Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 96 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xF only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 94 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map (R5F100xG, R5F101xG(x = A to C, E to G, J, L, M, P)) 1FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 12 KB Program area FCF00H FCEFFH Mirror 39.75 KB F3000H F2FFFH F1000H F0FFFH 01FFFH Data flash memoryNote 5 8 KB Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 20000H 1FFFFH Program memory space <R> Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 128 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xG only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 95 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Memory Map (R5F100xH, R5F101xH(x = E to G, J, L, M, P, S)) 2FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 16 KB FBF00H FBEFFH F3000H F2FFFH F1000H F0FFFH Program area Mirror 35.75 KB 01FFFH Data flash memoryNote 5 8 KB Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 30000H 2FFFFH Program memory space 00080H 0007FH <R> Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 192 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xH only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 96 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Memory Map (R5F100xJ, R5F101xJ(x = F, G, J, L, M, P, S)) 3FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 20 KB FAF00H FAEFFH F3000H F2FFFH F1000H F0FFFH Program area Mirror 31.75 KB 01FFFH Data flash memoryNote 5 8 KB Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 40000H 3FFFFH Program memory space 00080H 0007FH <R> Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 256 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEDFH and FAF00H to FB309H is prohibited when using the selfprogramming function and data flash function, because this area is used for self-programming library (R5F100xJ, R5F101xJ (x = F, G, J, L, M, P only)). 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xJ only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 97 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Memory Map (R5F100xK, R5F101xK(x = F, G, J, L, M, P, S)) 5FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAMNotes 1, 2 24 KB F9F00H F9EFFH F3000H F2FFFH F1000H F0FFFH Program area Mirror 27.75 KB 01FFFH Data flash memoryNote 5 8 KB Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 60000H 5FFFFH Program memory space 00080H 0007FH <R> Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 384 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xK only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 98 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Memory Map (R5F100xL, R5F101xL(x = F, G, J, L, M, P, S)) 7FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes Program area RAMNotes 1, 2 32 KB F7F00H F7EFFH F3000H F2FFFH F1000H F0FFFH Mirror 19.75 KB 01FFFH Data flash memoryNote 5 8 KB Reserved 010C4H 010C3H F0800H F07FFH Special function register (2nd SFR) 2 KB Data memory space 010CEH 010CDH F0000H EFFFFH 010C0H 010BFH 01080H 0107FH On-chip debug security ID setting areaNote 3 10 bytes Option byte areaNote 3 4 bytes Boot cluster 1 CALLT table area 64 bytes Vector table area 128 bytes 01000H 00FFFH Reserved Program area 000CEH 000CDH 000C4H 000C3H 000C0H 000BFH 80000H 7FFFFH Program memory space 00080H 0007FH <R> Option byte areaNote 3 4 bytes Boot cluster 0Note 4 CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 512 KB 00000H On-chip debug security ID setting areaNote 3 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEDFH and F7F00H to F8309H is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. When boot swap is used: Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH. 4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.6 Security Setting). 5. R5F100xL only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 99 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 0FFFFH Block 3FH 0FC00H 0FBFFH 007FFH 00400H 003FFH Block 01H Block 00H 1 KB 00000H (R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L)) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 100 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (1/4) Address Value Block Address Value 00000H to 003FFH 00H Block Address Value 08000H to 083FFH 20H Block Address Value 10000H to 103FFH 40H Block Number Number Number Number 18000H to 183FFH 60H 00400H to 007FFH 01H 08400H to 087FFH 21H 10400H to 107FFH 41H 18400H to 187FFH 61H 00800H to 00BFFH 02H 08800H to 08BFFH 22H 10800H to 10BFFH 42H 18800H to 18BFFH 62H 00C00H to 00FFFH 03H 08C00H to 08FFFH 23H 10C00H to 10FFFH 43H 18C00H to 18FFFH 63H 01000H to 013FFH 04H 09000H to 093FFH 24H 11000H to 113FFH 44H 19000H to 193FFH 64H 01400H to 017FFH 05H 09400H to 097FFH 25H 11400H to 117FFH 45H 19400H to 197FFH 65H 01800H to 01BFFH 06H 09800H to 09BFFH 26H 11800H to 11BFFH 46H 19800H to 19BFFH 66H 01C00H to 01FFFH 07H 09C00H to 09FFFH 27H 11C00H to 11FFFH 47H 19C00H to 19FFFH 67H 02000H to 023FFH 08H 0A000H to 0A3FFH 28H 12000H to 123FFH 48H 1A000H to 1A3FFH 68H 02400H to 027FFH 09H 0A400H to 0A7FFH 29H 12400H to 127FFH 49H 1A400H to 1A7FFH 69H 02800H to 02BFFH 0AH 0A800H to 0ABFFH 2AH 12800H to 12BFFH 4AH 1A800H to 1ABFFH 6AH 02C00H to 02FFFH 0BH 0AC00H to 0AFFFH 2BH 12C00H to 12FFFH 4BH 1AC00H to 1AFFFH 6BH 03000H to 033FFH 0CH 0B000H to 0B3FFH 2CH 13000H to 133FFH 4CH 1B000H to 1B3FFH 6CH 03400H to 037FFH 0DH 0B400H to 0B7FFH 2DH 13400H to 137FFH 4DH 1B400H to 1B7FFH 6DH 03800H to 03BFFH 0EH 0B800H to 0BBFFH 2EH 13800H to 13BFFH 4EH 1B800H to 1BBFFH 6EH 03C00H to 03FFFH 0FH 0BC00H to 0BFFFH 2FH 13C00H to 13FFFH 4FH 1BC00H to 1BFFFH 6FH 04000H to 043FFH 10H 0C000H to 0C3FFH 30H 14000H to 143FFH 50H 1C000H to 1C3FFH 70H 04400H to 047FFH 11H 0C400H to 0C7FFH 31H 14400H to 147FFH 51H 1C400H to 1C7FFH 71H 04800H to 04BFFH 12H 0C800H to 0CBFFH 32H 14800H to 14BFFH 52H 1C800H to 1CBFFH 72H 04C00H to 04FFFH 13H 0CC00H to 0CFFFH 33H 14C00H to 14FFFH 53H 1CC00H to 1CFFFH 73H 05000H to 053FFH 14H 0D000H to 0D3FFH 34H 15000H to 153FFH 54H 1D000H to 1D3FFH 74H 05400H to 057FFH 15H 0D400H to 0D7FFH 35H 15400H to 157FFH 55H 1D400H to 1D7FFH 75H 05800H to 05BFFH 16H 0D800H to 0DBFFH 36H 15800H to 15BFFH 56H 1D800H to 1DBFFH 76H 05C00H to 05FFFH 17H 0DC00H to 0DFFFH 37H 15C00H to 15FFFH 57H 1DC00H to 1DFFFH 77H 06000H to 063FFH 18H 0E000H to 0E3FFH 38H 16000H to 163FFH 58H 1E000H to 1E3FFH 78H 06400H to 067FFH 19H 0E400H to 0E7FFH 39H 16400H to 167FFH 59H 1E400H to 1E7FFH 79H 06800H to 06BFFH 1AH 0E800H to 0EBFFH 3AH 16800H to 16BFFH 5AH 1E800H to 1EBFFH 7AH 06C00H to 06FFFH 1BH 0EC00H to 0EFFFH 3BH 16C00H to 16FFFH 5BH 1EC00H to 1EFFFH 7BH 07000H to 073FFH 1CH 0F000H to 0F3FFH 3CH 17000H to 173FFH 5CH 1F000H to 1F3FFH 7CH 07400H to 077FFH 1DH 0F400H to 0F7FFH 3DH 17400H to 177FFH 5DH 1F400H to 1F7FFH 7DH 07800H to 07BFFH 1EH 0F800H to 0FBFFH 3EH 17800H to 17BFFH 5EH 1F800H to 1FBFFH 7EH 07C00H to 07FFFH 1FH 0FC00H to 0FFFFH 3FH 17C00H to 17FFFH 5FH 1FC00H to 1FFFFH 7FH <R> Remark R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G) : Block numbers 00H to 0FH R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L) : Block numbers 00H to 1FH R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L) : Block numbers 00H to 2FH R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L) : Block numbers 00H to 3FH R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P) : Block numbers 00H to 5FH R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P) : Block numbers 00H to 7FH R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 101 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (2/4) Address Value Block Address Value Number Block Address Value Number Block Address Value Number Block Number 20000H to 203FFH 80H 28000H to 283FFH A0H 30000H to 303FFH C0H 38000H to 383FFH E0H 20400H to 207FFH 81H 28400H to 287FFH A1H 30400H to 307FFH C1H 38400H to 387FFH E1H 20800H to 20BFFH 82H 28800H to 28BFFH A2H 30800H to 30BFFH C2H 38800H to 38BFFH E2H 20C00H to 20FFFH 83H 28C00H to 28FFFH A3H 30C00H to 30FFFH C3H 38C00H to 38FFFH E3H 21000H to 213FFH 84H 29000H to 293FFH A4H 31000H to 313FFH C4H 39000H to 393FFH E4H 21400H to 217FFH 85H 29400H to 297FFH A5H 31400H to 317FFH C5H 39400H to 397FFH E5H 21800H to 21BFFH 86H 29800H to 29BFFH A6H 31800H to 31BFFH C6H 39800H to 39BFFH E6H 21C00H to 21FFFH 87H 29C00H to 29FFFH A7H 31C00H to 31FFFH C7H 39C00H to 39FFFH E7H 22000H to 223FFH 88H 2A000H to 2A3FFH A8H 32000H to 323FFH C8H 3A000H to 3A3FFH E8H 22400H to 227FFH 89H 2A400H to 2A7FFH A9H 32400H to 327FFH C9H 3A400H to 3A7FFH E9H 22800H to 22BFFH 8AH 2A800H to 2ABFFH AAH 32800H to 32BFFH CAH 3A800H to 3ABFFH EAH 22C00H to 22FFFH 8BH 2AC00H to 2AFFFH ABH 32C00H to 32FFFH CBH 3AC00H to 3AFFFH EBH 23000H to 233FFH 8CH 2B000H to 2B3FFH ACH 33000H to 333FFH CCH 3B000H to 3B3FFH ECH 23400H to 237FFH 8DH 2B400H to 2B7FFH ADH 33400H to 337FFH CDH 3B400H to 3B7FFH EDH 23800H to 23BFFH 8EH 2B800H to 2BBFFH AEH 33800H to 33BFFH CEH 3B800H to 3BBFFH EEH 23C00H to 23FFFH 8FH 2BC00H to 2BFFFH AFH 33C00H to 33FFFH CFH 3BC00H to 3BFFFH EFH 24000H to 243FFH 90H 2C000H to 2C3FFH B0H 34000H to 343FFH D0H 3C000H to 3C3FFH F0H 24400H to 247FFH 91H 2C400H to 2C7FFH B1H 34400H to 347FFH D1H 3C400H to 3C7FFH F1H 24800H to 24BFFH 92H 2C800H to 2CBFFH B2H 34800H to 34BFFH D2H 3C800H to 3CBFFH F2H 24C00H to 24FFFH 93H 2CC00H to 2CFFFH B3H 34C00H to 34FFFH D3H 3CC00H to 3CFFFH F3H 25000H to 253FFH 94H 2D000H to 2D3FFH B4H 35000H to 353FFH D4H 3D000H to 3D3FFH F4H 25400H to 257FFH 95H 2D400H to 2D7FFH B5H 35400H to 357FFH D5H 3D400H to 3D7FFH F5H 25800H to 25BFFH 96H 2D800H to 2DBFFH B6H 35800H to 35BFFH D6H 3D800H to 3DBFFH F6H 25C00H to 25FFFH 97H 2DC00H to 2DFFFH B7H 35C00H to 35FFFH D7H 3DC00H to 3DFFFH F7H 26000H to 263FFH 98H 2E000H to 2E3FFH B8H 36000H to 363FFH D8H 3E000H to 3E3FFH F8H 26400H to 267FFH 99H 2E400H to 2E7FFH B9H 36400H to 367FFH D9H 3E400H to 3E7FFH F9H 26800H to 26BFFH 9AH 2E800H to 2EBFFH BAH 36800H to 36BFFH DAH 3E800H to 3EBFFH FAH 26C00H to 26FFFH 9BH 2EC00H to 2EFFFH BBH 36C00H to 36FFFH DBH 3EC00H to 3EFFFH FBH 27000H to 273FFH 9CH 2F000H to 2F3FFH BCH 37000H to 373FFH DCH 3F000H to 3F3FFH FCH 27400H to 277FFH 9DH 2F400H to 2F7FFH BDH 37400H to 377FFH DDH 3F400H to 3F7FFH FDH 27800H to 27BFFH 9EH 2F800H to 2FBFFH BEH 37800H to 37BFFH DEH 3F800H to 3FBFFH FEH 27C00H to 27FFFH 9FH 2FC00H to 2FFFFH BFH 37C00H to 37FFFH DFH 3FC00H to 3FFFFH FFH <R> Remark R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) : Block numbers 00H to BFH R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S) : Block numbers 00H to FFH R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 102 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (3/4) Address Value Block Address Value Number Block Address Value Number Block Address Value Number Block Number 40000H to 403FFH 100H 48000H to 483FFH 120H 50000H to 503FFH 140H 58000H to 583FFH 160H 40400H to 407FFH 101H 48400H to 487FFH 121H 50400H to 507FFH 141H 58400H to 587FFH 161H 40800H to 40BFFH 102H 48800H to 48BFFH 122H 50800H to 50BFFH 142H 58800H to 58BFFH 162H 40C00H to 40FFFH 103H 48C00H to 48FFFH 123H 50C00H to 50FFFH 143H 58C00H to 58FFFH 163H 41000H to 413FFH 104H 49000H to 493FFH 124H 51000H to 513FFH 144H 59000H to 593FFH 164H 41400H to 417FFH 105H 49400H to 497FFH 125H 51400H to 517FFH 145H 59400H to 597FFH 165H 41800H to 41BFFH 106H 49800H to 49BFFH 126H 51800H to 51BFFH 146H 59800H to 59BFFH 166H 41C00H to 41FFFH 107H 49C00H to 49FFFH 127H 51C00H to 51FFFH 147H 59C00H to 59FFFH 167H 42000H to 423FFH 108H 4A000H to 4A3FFH 128H 52000H to 523FFH 148H 5A000H to 5A3FFH 168H 42400H to 427FFH 109H 4A400H to 4A7FFH 129H 52400H to 527FFH 149H 5A400H to 5A7FFH 169H 42800H to 42BFFH 10AH 4A800H to 4ABFFH 12AH 52800H to 52BFFH 14AH 5A800H to 5ABFFH 16AH 42C00H to 42FFFH 10BH 4AC00H to 4AFFFH 12BH 52C00H to 52FFFH 14BH 5AC00H to 5AFFFH 16BH 43000H to 433FFH 10CH 4B000H to 4B3FFH 12CH 53000H to 533FFH 14CH 5B000H to 5B3FFH 16CH 43400H to 437FFH 10DH 4B400H to 4B7FFH 12DH 53400H to 537FFH 14DH 5B400H to 5B7FFH 16DH 43800H to 43BFFH 10EH 4B800H to 4BBFFH 12EH 53800H to 53BFFH 14EH 5B800H to 5BBFFH 16EH 43C00H to 43FFFH 10FH 4BC00H to 4BFFFH 12FH 53C00H to 53FFFH 14FH 5BC00H to 5BFFFH 16FH 44000H to 443FFH 110H 4C000H to 4C3FFH 130H 54000H to 543FFH 150H 5C000H to 5C3FFH 170H 44400H to 447FFH 111H 4C400H to 4C7FFH 131H 54400H to 547FFH 151H 5C400H to 5C7FFH 171H 44800H to 44BFFH 112H 4C800H to 4CBFFH 132H 54800H to 54BFFH 152H 5C800H to 5CBFFH 172H 44C00H to 44FFFH 113H 4CC00H to 4CFFFH 133H 54C00H to 54FFFH 153H 5CC00H to 5CFFFH 173H 45000H to 453FFH 114H 4D000H to 4D3FFH 134H 55000H to 553FFH 154H 5D000H to 5D3FFH 174H 45400H to 457FFH 115H 4D400H to 4D7FFH 135H 55400H to 557FFH 155H 5D400H to 5D7FFH 175H 45800H to 45BFFH 116H 4D800H to 4DBFFH 136H 55800H to 55BFFH 156H 5D800H to 5DBFFH 176H 45C00H to 45FFFH 117H 4DC00H to 4DFFFH 137H 55C00H to 55FFFH 157H 5DC00H to 5DFFFH 177H 46000H to 463FFH 118H 4E000H to 4E3FFH 138H 56000H to 563FFH 158H 5E000H to 5E3FFH 178H 46400H to 467FFH 119H 4E400H to 4E7FFH 139H 56400H to 567FFH 159H 5E400H to 5E7FFH 179H 46800H to 46BFFH 11AH 4E800H to 4EBFFH 13AH 56800H to 56BFFH 15AH 5E800H to 5EBFFH 17AH 46C00H to 46FFFH 11BH 4EC00H to 4EFFFH 13BH 56C00H to 56FFFH 15BH 5EC00H to 5EFFFH 17BH 47000H to 473FFH 11CH 4F000H to 4F3FFH 13CH 57000H to 573FFH 15CH 5F000H to 5F3FFH 17CH 47400H to 477FFH 11DH 4F400H to 4F7FFH 13DH 57400H to 577FFH 15DH 5F400H to 5F7FFH 17DH 47800H to 47BFFH 11EH 4F800H to 4FBFFH 13EH 57800H to 57BFFH 15EH 5F800H to 5FBFFH 17EH 47C00H to 47FFFH 11FH 4FC00H to 4FFFFH 13FH 57C00H to 57FFFH 15FH 5FC00H to 5FFFFH 17FH <R> Remark R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) : R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Block numbers 00H to 17FH 103 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory (4/4) Address Value Block Address Value Number 60000H to 603FFH 180H Block Address Value Number 68000H to 683FFH 1A0H Block Address Value Number 70000H to 703FFH 1C0H Block Number 78000H to 783FFH 1E0H 60400H to 607FFH 181H 68400H to 687FFH 1A1H 70400H to 707FFH 1C1H 78400H to 787FFH 1E1H 60800H to 60BFFH 182H 68800H to 68BFFH 1A2H 70800H to 70BFFH 1C2H 78800H to 78BFFH 1E2H 60C00H to 60FFFH 183H 68C00H to 68FFFH 1A3H 70C00H to 70FFFH 1C3H 78C00H to 78FFFH 1E3H 61000H to 613FFH 184H 69000H to 693FFH 1A4H 71000H to 713FFH 1C4H 79000H to 793FFH 1E4H 61400H to 617FFH 185H 69400H to 697FFH 1A5H 71400H to 717FFH 1C5H 79400H to 797FFH 1E5H 61800H to 61BFFH 186H 69800H to 69BFFH 1A6H 71800H to 71BFFH 1C6H 79800H to 79BFFH 1E6H 61C00H to 61FFFH 187H 69C00H to 69FFFH 1A7H 71C00H to 71FFFH 1C7H 79C00H to 79FFFH 1E7H 62000H to 623FFH 188H 6A000H to 6A3FFH 1A8H 72000H to 723FFH 1C8H 7A000H to 7A3FFH 1E8H 62400H to 627FFH 189H 6A400H to 6A7FFH 1A9H 72400H to 727FFH 1C9H 7A400H to 7A7FFH 1E9H 62800H to 62BFFH 18AH 6A800H to 6ABFFH 1AAH 72800H to 72BFFH 1CAH 7A800H to 7ABFFH 1EAH 62C00H to 62FFFH 18BH 6AC00H to 6AFFFH 1ABH 72C00H to 72FFFH 1CBH 7AC00H to 7AFFFH 1EBH 63000H to 633FFH 18CH 6B000H to 6B3FFH 1ACH 73000H to 733FFH 1CCH 7B000H to 7B3FFH 1ECH 63400H to 637FFH 18DH 6B400H to 6B7FFH 1ADH 73400H to 737FFH 1CDH 7B400H to 7B7FFH 1EDH 63800H to 63BFFH 18EH 6B800H to 6BBFFH 1AEH 73800H to 73BFFH 1CEH 7B800H to 7BBFFH 1EEH 63C00H to 63FFFH 18FH 6BC00H to 6BFFFH 1AFH 73C00H to 73FFFH 1CFH 7BC00H to 7BFFFH 1EFH 64000H to 643FFH 190H 6C000H to 6C3FFH 1B0H 74000H to 743FFH 1D0H 7C000H to 7C3FFH 1F0H 64400H to 647FFH 191H 6C400H to 6C7FFH 1B1H 74400H to 747FFH 1D1H 7C400H to 7C7FFH 1F1H 64800H to 64BFFH 192H 6C800H to 6CBFFH 1B2H 74800H to 74BFFH 1D2H 7C800H to 7CBFFH 1F2H 64C00H to 64FFFH 193H 6CC00H to 6CFFFH 1B3H 74C00H to 74FFFH 1D3H 7CC00H to 7CFFFH 1F3H 65000H to 653FFH 194H 6D000H to 6D3FFH 1B4H 75000H to 753FFH 1D4H 7D000H to 7D3FFH 1F4H 65400H to 657FFH 195H 6D400H to 6D7FFH 1B5H 75400H to 757FFH 1D5H 7D400H to 7D7FFH 1F5H 65800H to 65BFFH 196H 6D800H to 6DBFFH 1B6H 75800H to 75BFFH 1D6H 7D800H to 7DBFFH 1F6H 65C00H to 65FFFH 197H 6DC00H to 6DFFFH 1B7H 75C00H to 75FFFH 1D7H 7DC00H to 7DFFFH 1F7H 66000H to 663FFH 198H 6E000H to 6E3FFH 1B8H 76000H to 763FFH 1D8H 7E000H to 7E3FFH 1F8H 66400H to 667FFH 199H 6E400H to 6E7FFH 1B9H 76400H to 767FFH 1D9H 7E400H to 7E7FFH 1F9H 66800H to 66BFFH 19AH 6E800H to 6EBFFH 1BAH 76800H to 76BFFH 1DAH 7E800H to 7EBFFH 1FAH 66C00H to 66FFFH 19BH 6EC00H to 6EFFFH 1BBH 76C00H to 76FFFH 1DBH 7EC00H to 7EFFFH 1FBH 67000H to 673FFH 19CH 6F000H to 6F3FFH 1BCH 77000H to 773FFH 1DCH 7F000H to 7F3FFH 1FCH 67400H to 677FFH 19DH 6F400H to 6F7FFH 1BDH 77400H to 777FFH 1DDH 7F400H to 7F7FFH 1FDH 67800H to 67BFFH 19EH 6F800H to 6FBFFH 1BEH 77800H to 77BFFH 1DEH 7F800H to 7FBFFH 1FEH 67C00H to 67FFFH 19FH 6FC00H to 6FFFFH 1BFH 77C00H to 77FFFH 1DFH 7FC00H to 7FFFFH 1FFH <R> Remark R5F100xL, R5F101xL (x = F, G, J, L, M, P, S) : R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Block numbers 00H to 1FFH 104 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/G13 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G) Flash memory Capacity 16384 x 8 bits (00000H to 03FFFH) R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L) 32768 x 8 bits (00000H to 07FFFH) R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L) 49152 x 8 bits (00000H to 0BFFFH) R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L) 65536 x 8 bits (00000H to 0FFFFH) R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P) 98304 x 8 bits (00000H to 17FFFH) R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P) 131072 x 8 bits (00000H to 1FFFFH) R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) 196608 x 8 bits (00000H to 2FFFFH) R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S) 262144 x 8 bits (00000H to 3FFFFH) R5F100xK, R5F101xK (x = F, G, J, L, M, P, S) 393216 x 8 bits (00000H to 5FFFFH) R5F100xL, R5F101xL (x = F, G, J, L, M, P, S) 524288 x 8 bits (00000H to 7FFFFH) The internal program memory space is divided into the following areas. (1) Vector table area The 128-byte area 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump address is a 64 K address of 00000H to 0FFFFH, because the vector code is assumed to be 2 bytes. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. To use the boot swap function, set a vector table also at 01000H to 0107FH. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 105 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (1/2) 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin 24-pin 20-pin RESET, POR, LVD, WDT, 100-pin 0000H <R> Interrupt Source 128-pin Vector Table Address TRAP, IAW, RPE 0004H INTWDTI 0006H INTLVI 0008H INTP0 000AH INTP1 - 000CH INTP2 - - - 000EH INTP3 0010H INTP4 - 0012H INTP5 0014H INTST2/INTCSI20/INTIIC20 0016H INTSR2/INTCSI21/INTIIC21 0018H INTSRE2 INTTM11H - - - - - - 001AH INTDMA0 001CH INTDMA1 001EH INTST0/INTCSI00/INTIIC00 0020H INTSR0/INTCSI01/INTIIC01 0022H INTSRE0 INTTM01H 0024H INTST1/INTCSI10/INTIIC10 0026H INTSR1/INTCSI11/INTIIC11 0028H INTSRE1 INTTM03H 002AH INTIICA0 - 002CH INTTM00 002EH INTTM01 0030H INTTM02 0032H INTTM03 0034H INTAD 0036H INTRTC 0038H INTIT 003AH INTKR - - - - - - 003CH INTST3/INTCSI30/INTIIC30 - - - - - - - - - - - 003EH INTSR3/INTCSI31/INTIIC31 - - - - - - - - - - - 0040H INTTM13 - - - - - - - - - - - - - - - - - - - - - - - - - Note 1 Note 1 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Notes 1. INTSR2 only. 2. INTSR0 only. 3. INTSR1 only. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 106 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (2/2) 128-pin 100-pin 80-pin 64-pin 52-pin 48-pin 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin 24-pin 20-pin 0042H INTTM04 0044H INTTM05 0046H INTTM06 0048H INTTM07 004AH INTP6 - - - - - - - - 004CH INTP7 - - - - - - - - - - 004EH INTP8 - - - - - - - - 0050H INTP9 - - - - - - - - 0052H INTP10 - - - - - - - - - 0054H INTP11 - - - - - - - - - 0056H INTTM10 - - - - - - - - - - - 0058H INTTM11 - - - - - - - - - - - 005AH INTTM12 - - - - - - - - - - - 005CH INTSRE3 - - - - - - - - - - - INTTM13H - - - - - - - - - - - 005EH INTMD 0060H INTIICA1 - - - - - - - - - - - 0062H INTFL 0064H INTDMA2 - - - - - - - - - - - 0066H INTDMA3 - - - - - - - - - - - 0068H INTTM14 - - - - - - - - - - - - - 006AH INTTM15 - - - - - - - - - - - - - 006CH INTTM16 - - - - - - - - - - - - - 006EH INTTM17 - - - - - - - - - - - - - 007EH BRK Vector Table Address Interrupt Source (2) CALLT instruction table area The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes). To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH. (3) Option byte area A 4-byte area of 000C0H to 000C3H can be used as an option byte area. Set the option byte at 010C0H to 010C3H when the boot swap is used. For details, see CHAPTER 24 OPTION BYTE. (4) On-chip debug security ID setting area A 10-byte area of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID setting area. Set the on-chip debug security ID of 10 bytes at 000C4H to 000CDH when the boot swap is not used and at 000C4H to 000CDH and 010C4H to 010CDH when the boot swap is used. For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 107 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The RL78/G13 mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The products with 96 KB or more flash memory mirror the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not mirrored to the SFR, extended SFR, RAM, and use prohibited areas. See 3.1 Memory Space for the mirror area of each product. The mirror area can only be read and no instruction can be fetched from this area. The following show examples. Example R5F100xE (x = 6 to 8, A to C, E-G, J, L) (Flash memory: 64 KB, RAM: 4 KB) FFFFFH Special-function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH FEF00H FEEFFH General-purpose register 32 bytes RAM 4 KB For example, 0E789H is mirrored to FE789H. Data can therefore be read by MOV A, !E789H, instead of MOV Mirror (same data as 02000H to 0EEFFH) ES, #00H and MOV A, ES:!E789H. F2000H F1FFFH Data flash memory F1000H F0FFFH Reserved F0800H F07FFH Special-function register (2nd SFR) 2 KB F0000H EFFFFH Mirror Reserved 10000H 0FFFFH Code flash memory 0EF00H 0EEFFH Code flash memory 02000H 01FFFH Code flash memory 00000H The PMC register is described below. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 108 RL78/G13 CHAPTER 3 CPU ARCHITECTURE * Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 3-11. Format of Configuration of Processor Mode Control Register (PMC) Address: FFFFEH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> PMC 0 0 0 0 0 0 0 MAA MAA Selection of flash memory space for mirroring to area from F0000H to FFFFFH 0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH 1 10000H to 1FFFFH is mirrored to F0000H to FFFFFH Note Note This setting is prohibited in products with 64 KB or less flash memory Cautions 1. In products with 64 KB or less flash memory, be sure to clear bit 0 (MAA) of this register to 0 (default value). 2. Set the PMC register only once during the initial settings prior to operating the DMA controller. Rewriting the PMC register other than during the initial settings is prohibited. 3. After setting the PMC register, wait for at least one instruction and access the mirror area. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 109 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/G13 products incorporate the following RAMs. Table 3-4. Internal RAM Capacity Part Number R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G) Internal RAM 2048 x 8 bits (FF700H to FFEFFH) R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L) R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L) 3072 x 8 bits (FF300H to FFEFFH) R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L) 4096 x 8 bits (FEF00H to FFEFFH) R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P) 8192 x 8 bits (FDF00H to FFEFFH) R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P) 12288 x 8 bits (FCF00H to FFEFFH) R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) 16384 x 8 bits (FBF00H to FFEFFH) R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S) 20480 x 8 bits (FAF00H to FFEFFH) R5F100xK, R5F101xK (x = F, G, J, L, M, P, S) 24576 x 8 bits (F9F00H to FFEFFH) R5F100xL, R5F101xL (x = F, G, J, L, M, P, S) 32768 x 8 bits (F7F00H to FFEFFH) The internal RAM can be used as a data area and a program area where instructions are written and executed. Four general-purpose register banks consisting of eight 8-bit registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM area. However, instructions cannot be executed by using the general-purpose registers. The internal RAM is used as stack memory. Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching instructions or as a stack area. <R> 2. The internal RAM in the following products cannot be used as stack memory when using the selfprogramming function and data flash function. R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G): FFE20H to FFEDFH R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L): FFE20H to FFEDFH R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L): FFE20H to FFEDFH, FF300H to FF309H R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L): FFE20H to FFEDFH, FEF00H to FF309H R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P): FFE20H to FFEDFH R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P): FFE20H to FFEDFH R5F100xH, R5F101xH (x =E to G, J, L, M, P, S): FFE20H to FFEDFH R5F100xJ, R5F101xJ (x = F, G, J, L, M, P): FFE20H to FFEDFH, FAF00H to FB309H R5F100xK, R5F101xK (x = F, G, J, L, M, P, S): FFE20H to FFEDFH R5F100xL, R5F101xL (x = F, G, J, L, M, P, S): FFE20H to FFEDFH, F7F00H to F8309H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 110 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area F0000H to F07FFH (see Table 3-6 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)). SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area. Caution Do not access addresses to which extended SFRs are not assigned. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 111 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G13, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use. Figures 3-12 to 3-21 show correspondence between data memory and addressing. For details of each addressing, see 3.4 Addressing for Processing Data Addresses. Figure 3-12. Correspondence Between Data Memory and Addressing (R5F100xA, R5F101xA(x = 6 to 8, A to C, E to G)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF700H FF6FFH F4000H F3FFFH F2000H F1FFFH F1000H F0FFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 1 2 KB Reserved Mirror 8 KB Data flash memoryNote 2 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H EFFFFH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 04000H 03FFFH Code flash memory 16 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xA only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 112 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Correspondence Between Data Memory and Addressing (R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 1 2 KB F8000H F7FFFH FF700H FF6FFH F2000H F1FFFH F1000H F0FFFH Reserved Mirror 24 KB Data flash memoryNote 2 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 08000H 07FFFH Code flash memory 32 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xC only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 113 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-14. Correspondence Between Data Memory and Addressing (R5F100xD, R5F101xD(x = 6 to 8, A to C, E to G, J, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH Special function register (SFR) 256 bytes General-purpose register 32 bytes FFE20H FFE1FH RAMNote 1 3 KB FF300H FF2FFH FC000H FBFFFH Reserved F2000H F1FFFH F1000H F0FFFH SFR addressing Register addressing Short direct addressing Mirror 40 KB Data flash memoryNote 2 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 0C000H 0BFFFH Code flash memory 48 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH and FF300H to FF309H is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xD only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 114 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Correspondence Between Data Memory and Addressing (R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FEF00H FEEFFH F2000H F1FFFH F1000H F0FFFH Special function register (SFR) 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAMNote 1 4 KB Mirror 51.75 KB Data flash memoryNote 2 4 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 10000H 0FFFFH Code flash memory 64 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH and FEF00H to FF309H is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xE only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 115 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-16. Correspondence Between Data Memory and Addressing (R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P)) FFFFFH Special function register (SFR) 256 bytes FFF20H FFF1FH FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH SFR addressing Register addressing Short direct addressing RAMNote 1 8 KB FFE20H FFE1FH FDF00H FDEFFH Mirror 43.75 KB F3000H F2FFFH Data flash memoryNote 2 8 KB F1000H F0FFFH Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 18000H 17FFFH Code flash memory 96 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xF only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 116 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-17. Correspondence Between Data Memory and Addressing (R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P)) FFFFFH Special function register (SFR) 256 bytes FFF20H FFF1FH FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH SFR addressing Register addressing Short direct addressing RAMNote 1 12 KB FFE20H FFE1FH FCF00H FCEFFH Mirror 39.75 KB F3000H F2FFFH Data flash memoryNote 2 8 KB F1000H F0FFFH Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 20000H 1FFFFH Code flash memory 128 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xG only. Caution <R> When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 117 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-18. Correspondence Between Data Memory and Addressing (R5F100xH, R5F101xH (x = E to G, J, L, M, P, S)) FFFFFH Special function register (SFR) 256 bytes FFF20H FFF1FH FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH SFR addressing Register addressing Short direct addressing RAMNote 1 16 KB FFE20H FFE1FH FBF00H FBEFFH Mirror 35.75 KB F3000H F2FFFH Data flash memoryNote 2 8 KB F1000H F0FFFH Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 30000H 2FFFFH Code flash memory 192 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xH only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 118 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-19. Correspondence Between Data Memory and Addressing (R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FAF00H FAEFFH F3000H F2FFFH F1000H F0FFFH Special function register (SFR) 256 bytes SFR addressing General-purpose register 32 bytes Register addressing Short direct addressing RAMNote 1 20 KB Mirror 31.75 KB Data flash memoryNote 2 8 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 40000H 3FFFFH Code flash memory 256 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH and FAF00H to FB309H is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library (R5F100xJ, R5F101xJ (x = F, G, J, L, M, P) only). 2. R5F100xJ only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 119 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-20. Correspondence Between Data Memory and Addressing (R5F100xK, R5F101xK (x = F, G, J, L, M, P, S)) FFFFFH Special function register (SFR) 256 bytes FFF20H FFF1FH FFF00H FFEFFH General-purpose register 32 bytes FFEE0H FFEDFH SFR addressing Register addressing Short direct addressing RAM Note 1 24 KB FFE20H FFE1FH F9F00H F9EFFH Mirror 27.75 KB F3000H F2FFFH Data flash memoryNote 2 8 KB F1000H F0FFFH Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 60000H 5FFFFH Code flash memory 384 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xK only. <R> Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 120 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-21. Correspondence Between Data Memory and Addressing (R5F100xL, R5F101xL (x = F, G, J, L, M, P, S)) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH F7F00H F7EFFH F3000H F2FFFH F1000H F0FFFH Special function register (SFR) SFR addressing 256 bytes General-purpose register 32 bytes Register addressing Short direct addressing RAMNote 1 32 KB Mirror 19.75 KB Data flash memoryNote 2 8 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB Direct addressing Register indirect addressing F0000H EFFFFH Based addressing Based indexed addressing Reserved 80000H 7FFFFH Code flash memory 512 KB 00000H <R> Notes 1. Use of the area FFE20H to FFEDFH and F7F00H to F8309H is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. R5F100xL only. Caution <R> When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 121 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/G13 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed. In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-22. Format of Program Counter 19 0 PC (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH PSW instruction execution and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset signal generation sets the PSW register to 06H. Figure 3-23. Format of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 ISP1 ISP0 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0, RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 122 RL78/G13 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H, PRn1L, PRn1H, PRn2L, PRn2H) (see 16.3 (3)) can not be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE). Remark n = 0, 1 (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as the stack area. Figure 3-24. Format of Stack Pointer 0 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from the stack memory. Each stack operation saves data as shown in Figure 3-25. Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. 2. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a stack area. <R> 3. The internal RAM in the following products cannot be used as stack memory when using the self-programming function and data flash function. R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G): FFE20H to FFEDFH R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L): FFE20H to FFEDFH R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L): FFE20H to FFEDFH, FF300H to FF309H R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L): FFE20H to FFEDFH, FEF00H to FF309H R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P): FFE20H to FFEDFH R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P): FFE20H to FFEDFH R5F100xH, R5F101xH (x =E to G, J, L, M, P, S): FFE20H to FFEDFH R5F100xJ, R5F101xJ (x = F, G, J, L, M, P): FFE20H to FFEDFH, FAF00H to FB309H R5F100xK, R5F101xK (x = F, G, J, L, M, P, S): FFE20H to FFEDFH R5F100xL, R5F101xL (x = F, G, J, L, M, P, S): FFE20H to FFEDFH, F7F00H to F8309H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 123 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-25. Data to Be Saved to Stack Memory PUSH PSW instruction PUSH rp instruction SPSP-2 SP-2 SP-1 SP Register pair lower Register pair higher SPSP-2 SP-2 SP-1 SP PC7 to PC0 PC15 to PC8 PC19 to PC16 00H PSW Interrupt, BRK instruction (4-byte stack) CALL, CALLT instructions (4-byte stack) SPSP-4 SP-4 SP-3 SP-2 SP-1 SP 00H SPSP-4 SP-4 SP-3 SP-2 SP-1 SP PC7 to PC0 PC15 to PC8 PC19 to PC16 PSW 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. <R> Cautions 1. It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching instructions or as a stack area. 2. The internal RAM in the following products cannot be used as stack memory when using the selfprogramming function and data flash function. R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G): R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L): R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L): R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L): R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P): R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P): R5F100xH, R5F101xH (x =E to G, J, L, M, P, S): R5F100xJ, R5F101xJ (x = F, G, J, L, M, P): R5F100xK, R5F101xK (x = F, G, J, L, M, P, S): R5F100xL, R5F101xL (x = F, G, J, L, M, P, S): R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 FFE20H to FFEDFH FFE20H to FFEDFH FFE20H to FFEDFH, FF300H to FF309H FFE20H to FFEDFH, FEF00H to FF309H FFE20H to FFEDFH FFE20H to FFEDFH FFE20H to FFEDFH FFE20H to FFEDFH, FAF00H to FB309H FFE20H to FFEDFH FFE20H to FFEDFH, F7F00H to F8309H 124 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-26. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FFEFFH H Register bank 0 HL L FFEF8H D Register bank 1 DE E FFEF0H B BC Register bank 2 C FFEE8H A AX Register bank 3 X FFEE0H 15 0 7 0 (b) Absolute name 16-bit processing 8-bit processing FFEFFH R7 Register bank 0 RP3 R6 FFEF8H R5 Register bank 1 RP2 R4 FFEF0H R3 RP1 Register bank 2 R2 FFEE8H R1 RP0 Register bank 3 R0 FFEE0H 15 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 0 7 0 125 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 3-27. Configuration of ES and CS Registers ES CS R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 7 6 5 4 3 2 1 0 0 0 0 0 ES3 ES2 ES1 ES0 7 6 5 4 3 2 1 0 0 0 0 0 CS3 CP2 CP1 CP0 126 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-5 gives a list of the SFRs. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding SFR can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulable bit units "" indicates the manipulable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. Caution Do not access addresses to which extended SFRs are not assigned. Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 127 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (1/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF00H Port register 0 P0 R/W - 00H FFF01H Port register 1 P1 R/W - 00H FFF02H Port register 2 P2 R/W - 00H FFF03H Port register 3 P3 R/W - 00H FFF04H Port register 4 P4 R/W - 00H FFF05H Port register 5 P5 R/W - 00H FFF06H Port register 6 P6 R/W - 00H FFF07H Port register 7 P7 R/W - 00H FFF08H Port register 8 P8 R/W - 00H FFF09H Port register 9 P9 R/W - 00H FFF0AH Port register 10 P10 R/W - 00H FFF0BH Port register 11 P11 R/W - 00H FFF0CH Port register 12 P12 R/W - Undefined FFF0DH Port register 13 P13 R/W - Undefined FFF0EH Port register 14 P14 R/W - 00H FFF0FH Port register 15 P15 R/W - 00H FFF10H Serial data register 00 TXD0/ SDR00 R/W SIO00 - 0000H - - - 0000H - - - 0000H - - - 0000H - - R/W - - 0000H FFF1AH Timer data register 01 TDR01L TDR01 R/W - 00H FFF1BH TDR01H - FFF11H FFF12H Serial data register 01 RXD0/ SDR01 R/W SIO01 - FFF13H FFF14H Serial data register 12 TXD3/ SDR12 R/W SIO30 - FFF15H FFF16H Serial data register 13 RXD3/ SDR13 R/W SIO31 - FFF17H FFF18H Timer data register 00 TDR00 FFF19H - FFF1EH 10-bit A/D conversion result register ADCR R - - 0000H FFF1FH ADCRH R - - 00H 8-bit A/D conversion result register 00H FFF20H Port mode register 0 PM0 R/W - FFH FFF21H Port mode register 1 PM1 R/W - FFH FFF22H Port mode register 2 PM2 R/W - FFH FFF23H Port mode register 3 PM3 R/W - FFH FFF24H Port mode register 4 PM4 R/W - FFH FFF25H Port mode register 5 PM5 R/W - FFH FFF26H Port mode register 6 PM6 R/W - FFH FFF27H Port mode register 7 PM7 R/W - FFH FFF28H Port mode register 8 PM8 R/W - FFH FFF29H Port mode register 9 PM9 R/W - FFH R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 128 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (2/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF2AH Port mode register 10 PM10 R/W - FFH FFF2BH Port mode register 11 PM11 R/W - FFH FFF2CH Port mode register 12 PM12 R/W - FFH FFF2EH Port mode register 14 PM14 R/W - FFH FFF2FH Port mode register 15 PM15 R/W - FFH FFF30H A/D converter mode register 0 ADM0 R/W - 00H FFF31H Analog input channel specification register ADS R/W - FFF32H A/D converter mode register 1 ADM1 R/W - 00H FFF37H Key return mode register KRM R/W - 00H FFF38H External interrupt rising edge EGP0 R/W - 00H EGN0 R/W - 00H EGP1 R/W - 00H EGN1 R/W - 00H TXD1/ SDR02 R/W - 0000H - - - 0000H - - - 0000H - - - 0000H - - 00H enable register 0 FFF39H External interrupt falling edge enable register 0 FFF3AH External interrupt rising edge enable register 1 FFF3BH External interrupt falling edge enable register 1 FFF44H Serial data register 02 SIO10 FFF45H FFF46H Serial data register 03 - RXD1/ SDR03 R/W SIO11 FFF47H FFF48H Serial data register 10 - TXD2/ SDR10 R/W SIO20 FFF49H FFF4AH Serial data register 11 - RXD2/ SDR11 R/W SIO21 FFF4BH - FFF50H IICA shift register 0 IICA0 R/W - - 00H FFF51H IICA status register 0 IICS0 R - 00H FFF52H IICA flag register 0 IICF0 R/W - 00H FFF54H IICA shift register 1 IICA1 R/W - - 00H FFF55H IICA status register 1 IICS1 R - 00H FFF56H IICA flag register 1 IICF1 R/W - 00H FFF64H Timer data register 02 TDR02 R/W - - 0000H FFF66H Timer data register 03 TDR03L TDR03 R/W - 00H FFF67H TDR03H 0000H FFF65H FFF68H Timer data register 04 TDR04 R/W - - - 00H FFF69H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 129 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (3/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit TDR05 R/W - - 0000H TDR06 R/W - - 0000H TDR07 R/W - - 0000H TDR10 R/W - - 0000H FFF72H Timer data register 11 TDR11L TDR11 R/W - 00H FFF73H TDR11H 0000H FFF6AH Timer data register 05 FFF6BH FFF6CH Timer data register 06 FFF6DH FFF6EH Timer data register 07 FFF6FH FFF70H Timer data register 10 FFF71H FFF74H Timer data register 12 TDR12 R/W - - - 00H FFF75H FFF76H Timer data register 13 TDR13L TDR13 R/W - FFF77H TDR13H - FFF78H Timer data register 14 00H 00H TDR14 R/W - - 0000H TDR15 R/W - - 0000H TDR16 R/W - - 0000H TDR17 R/W - - 0000H ITMC R/W - - 0FFFH SEC R/W - - 00H FFF79H FFF7AH Timer data register 15 FFF7BH FFF7CH Timer data register 16 FFF7DH FFF7EH Timer data register 17 FFF7FH FFF90H Interval timer control register FFF91H FFF92H Second count register FFF93H Minute count register MIN R/W - - FFF94H Hour count register HOUR R/W - - FFF95H Week count register WEEK R/W - - 00H FFF96H Day count register DAY R/W - - 01H FFF97H Month count register MONTH R/W - - 01H FFF98H Year count register YEAR R/W - - 00H FFF99H Watch error correction register SUBCUD R/W - - 00H FFF9AH Alarm minute register ALARMWM R/W - - 00H FFF9BH Alarm hour register ALARMWH R/W - - 12H FFF9CH Alarm week register ALARMWW R/W - - 00H FFF9DH Real-time clock control register RTCC0 R/W - 00H RTCC1 R/W - 00H 00H Note 12H 0 FFF9EH Real-time clock control register 1 Note The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1 after reset. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 130 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (4/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit CMC R/W - - 00H CSC R/W - C0H OSTC R - 00H OSTS R/W - - 07H FFFA4H System clock control register CKC R/W - 00H FFFA5H Clock output select register 0 CKS0 R/W - 00H FFFA6H Clock output select register 1 CKS1 R/W - 00H FFFA8H Reset control flag register RESF R - - Undefined FFFA9H Voltage detection register LVIM R/W - 00H FFFAAH Voltage detection level register LVIS R/W - 00H/01H/81H FFFA0H Clock operation mode control register FFFA1H Clock operation status control register FFFA2H Oscillation stabilization time counter status register FFFA3H Oscillation stabilization time select register Note 2 Note 3 FFFABH Watchdog timer enable register WDTE R/W - - FFFACH CRC input register CRCIN R/W - - 00H FFFB0H DMA SFR address register 0 DSA0 R/W - - 00H FFFB1H DMA SFR address register 1 DSA1 R/W - - 00H FFFB2H DMA RAM address register 0L DRA0L DRA0 R/W - 00H FFFB3H DMA RAM address register 0H DRA0H R/W - FFFB4H DMA RAM address register 1L DRA1L DRA1 R/W - 00H FFFB5H DMA RAM address register 1H DRA1H R/W - FFFB6H DMA byte count register 0L DBC0L DBC0 R/W - FFFB7H DMA byte count register 0H DBC0H R/W - FFFB8H DMA byte count register 1L DBC1L DBC1 R/W - FFFB9H DMA byte count register 1H DBC1H R/W - FFFBAH DMA mode control register 0 DMC0 R/W FFFBBH DMA mode control register 1 DMC1 R/W FFFBCH DMA operation control register 0 DRC0 FFFBDH DMA operation control register 1 DRC1 FFFD0H Interrupt request flag register 2L IF2L IF2 FFFD1H Interrupt request flag register 2H IF2H Note 4 1AH/9AH 00H 00H 00H 00H 00H - 00H - 00H R/W - 00H R/W - 00H R/W 00H R/W 00H 00H FFFD2H Interrupt request flag register 3L IF3L IF3 R/W 00H FFFD4H Interrupt mask flag register 2L MK2L MK2 R/W FFH FFFD5H Interrupt mask flag register 2H MK2H R/W FFFD6H Interrupt mask flag register 3L MK3L R/W MK3 Note 1 FFH FFH Notes 1. The reset value of the RESF register varies depending on the reset source. 2. The reset value of the LVIM register varies depending on the reset source. 3. The reset value of the LVIS register varies depending on the reset source and the setting of the option byte. 4. The reset value of the WDTE register is determined by the setting of the option byte. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 131 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-5. SFR List (5/5) Address Special Function Register (SFR) Name Symbol FFFD8H Priority specification flag register PR02L PR02 R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit R/W R/W R/W FFH R/W FFH R/W R/W FFH 00H FFH 02L FFFD9H Priority specification flag register PR02H FFH 02H FFFDAH Priority specification flag register PR03L PR03 02L FFFDCH Priority specification flag register PR12L PR12 12L FFFDDH Priority specification flag register PR12H FFH 12H FFFDEH Priority specification flag register PR13L PR13 13L FFFE0H Interrupt request flag register 0L IF0L IF0 FFFE1H Interrupt request flag register 0H IF0H FFFE2H Interrupt request flag register 1L IF1L IF1 FFFE3H Interrupt request flag register 1H IF1H FFFE4H Interrupt mask flag register 0L MK0L FFFE5H Interrupt mask flag register 0H MK0H FFFE6H Interrupt mask flag register 1L MK1L FFFE7H Interrupt mask flag register 1H MK1H MK0 MK1 FFFE8H Priority specification flag register PR00L PR00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00H 00H FFH 00H FFH FFH FFH FFH 00L FFFE9H Priority specification flag register PR00H FFH 00H FFFEAH Priority specification flag register PR01L PR01 FFH 01L FFFEBH Priority specification flag register PR01H FFH 01H FFFECH Priority specification flag register PR10L PR10 FFH 10L FFFEDH Priority specification flag register PR10H FFH 10H FFFEEH Priority specification flag register PR11L PR11 FFH 11L FFFEFH Priority specification flag register PR11H FFH 11H FFFF0H Multiplication/division data register FFFF1H A (L) MDAL R/W - - 0000H FFFF2H Multiplication/division data register FFFF3H A (H) MDAH R/W - - 0000H FFFF4H Multiplication/division data register FFFF5H B (H) MDBH R/W - - 0000H FFFF6H Multiplication/division data register FFFF7H B (L) MDBL R/W - - 0000H - 00H FFFFEH Processor mode control register PMC nd R/W nd Remark For extended SFRs (2 SFRs), see Table 3-6 Extended SFR (2 SFR) List. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 132 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area. Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When specifying an address, describe an even address. Table 3-6 gives a list of the extended SFRs. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding extended SFR can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulable bit units "" indicates the manipulable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. Caution Do not access addresses to which extended SFRs are not assigned. Remark For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 133 RL78/G13 CHAPTER 3 CPU ARCHITECTURE nd Table 3-6. Extended SFR (2 SFR) List (1/8) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F0010H A/D converter mode register 2 ADM2 R/W - 00H F0011H Conversion result comparison upper limit setting register ADUL R/W - - FFH F0012H Conversion result comparison lower limit setting register ADLL R/W - - 00H F0013H A/D test register ADTES R/W - - 00H F0030H Pull-up resistor option register 0 PU0 R/W - 00H F0031H Pull-up resistor option register 1 PU1 R/W - 00H F0033H Pull-up resistor option register 3 PU3 R/W - 00H F0034H Pull-up resistor option register 4 PU4 R/W - 01H F0035H Pull-up resistor option register 5 PU5 R/W - 00H F0036H Pull-up resistor option register 6 PU6 R/W - 00H F0037H Pull-up resistor option register 7 PU7 R/W - 00H F0038H Pull-up resistor option register 8 PU8 R/W - 00H F0039H Pull-up resistor option register 9 PU9 R/W - 00H F003AH Pull-up resistor option register 10 PU10 R/W - 00H F003BH Pull-up resistor option register 11 PU11 R/W - 00H F003CH Pull-up resistor option register 12 PU12 R/W - 00H F003EH Pull-up resistor option register 14 PU14 R/W - 00H F0040H Port input mode register 0 PIM0 R/W - 00H F0041H Port input mode register 1 PIM1 R/W - 00H F0044H Port input mode register 4 PIM4 R/W - 00H F0045H Port input mode register 5 PIM5 R/W - 00H F0048H Port input mode register 8 PIM8 R/W - 00H F004EH Port input mode register 14 PIM14 R/W - 00H F0050H Port output mode register 0 POM0 R/W - 00H F0051H Port output mode register 1 POM1 R/W - 00H F0054H Port output mode register 4 POM4 R/W - 00H F0055H Port output mode register 5 POM5 R/W - 00H F0057H Port output mode register 7 POM7 R/W - 00H F0058H Port output mode register 8 POM8 R/W - 00H F0059H Port output mode register 9 POM9 R/W - 00H F005EH Port output mode register 14 POM14 R/W - 00H F0060H Port mode control register 0 PMC0 R/W - FFH F0063H Port mode control register 3 PMC3 R/W - FFH F006AH Port mode control register 10 PMC10 R/W - FFH F006BH Port mode control register 11 PMC11 R/W - FFH F006CH Port mode control register 12 PMC12 R/W - FFH F006EH Port mode control register 14 PMC14 R/W - FFH R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 134 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (2/8) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F0070H Noise filter enable register 0 NFEN0 R/W - 00H F0071H Noise filter enable register 1 NFEN1 R/W - 00H F0072H Noise filter enable register 2 NFEN2 R/W - 00H F0073H Input switch control register ISC R/W - 00H F0074H Timer input select register 0 TIS0 R/W - - 00H F0076H A/D port configuration register ADPC R/W - - 00H F0077H Peripheral I/O redirection register PIOR R/W - - 00H F0078H Invalid memory access detection control register IAWCTL R/W - - 00H F007DH Global digital input disable register GDIDIS R/W - 00H F0090H DFLCTL R/W - 00H F00A0H High-speed on-chip oscillator trimming register HIOTRM R/W - - Note F00A8H High-speed on-chip oscillator frequency select register HOCODIV R/W - - Undefined F00E0H Multiplication/division data register C (L) MDCL R/W - - 0000H F00E2H Multiplication/division data register C (H) MDCH R/W - - 0000H F00E8H Multiplication/division control register MDUC R/W - 00H F00F0H Peripheral enable register 0 PER0 R/W - 00H F00F3H Operation speed mode control register OSMC R/W - - 00H R/W - 00H R - - Undefined R - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - Data flash control register F00F5H RAM parity error control register RPECTL F00FEH BCD adjust result register F0100H Serial status register 00 Serial status register 01 Serial status register 02 R SSR02L SSR02 R - F0105H F0106H SSR01L SSR01 - F0103H F0104H SSR00L SSR00 - F0101H F0102H BCDADJ Serial status register 03 SSR03L SSR03 R - F0107H Serial flag clear trigger register 00 SIR00L SIR00 R/W F010AH Serial flag clear trigger register F010BH 01 SIR01L SIR01 R/W F010CH Serial flag clear trigger register F010DH 02 SIR02L SIR02 R/W F010EH Serial flag clear trigger register F010FH 03 SIR03L SIR03 R/W F0108H F0109H - - - - Note The reset value differs for each chip. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 135 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (3/8) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit Serial mode register 00 SMR00 R/W - - 0020H Serial mode register 01 SMR01 R/W - - 0020H Serial mode register 02 SMR02 R/W - - 0020H Serial mode register 03 SMR03 R/W - - 0020H Serial communication operation setting register 00 SCR00 R/W - - 0087H F011AH Serial communication operation F011BH setting register 01 SCR01 R/W - - 0087H F011CH Serial communication operation F011DH setting register 02 SCR02 R/W - - 0087H F011EH Serial communication operation F011FH setting register 03 SCR03 R/W - - 0087H SE0 R 0000H - - SS0 R/W 0000H - - 0000H - - - 0000H - - F0110H F0111H F0112H F0113H F0114H F0115H F0116H F0117H F0118H F0119H Serial channel enable status register 0 SE0L F0121H F0122H Serial channel start register 0 SS0L F0120H - F0123H F0124H Serial channel stop register 0 Serial clock select register 0 ST0 R/W SPS0L SPS0 R/W - F0127H F0128H ST0L - F0125H F0126H - Serial output register 0 SO0 R/W - - 0F0FH SOE0L SOE0 R/W 0000H - - - 0000H 0000H 0000H 0000H 0000H 0000H F0129H F012AH Serial output enable register 0 - F012BH F0134H Serial output level register 0 SOL0L SOL0 R/W - F0135H F0138H Serial standby control register 0 SSC0L SSC0 F0140H Serial status register 10 SSR10L SSR10 Serial status register 11 SSR11L SSR11 R/W - - F0141H F0142H Serial status register 12 SSR12L SSR12 R - F0145H F0146H R - F0143H F0144H R Serial status register 13 F0147H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 SSR13L SSR13 - R - - - - - - - - - - - - - - - - - 136 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (4/8) Address Special Function Register (SFR) Name Symbol R/W Serial flag clear trigger register 10 SIR10L SIR10 R/W F014AH Serial flag clear trigger register F014BH 11 SIR11L SIR11 R/W F014CH Serial flag clear trigger register F014DH 12 SIR12L SIR12 R/W F014EH Serial flag clear trigger register F014FH 13 SIR13L SIR13 R/W F0148H F0149H - - - - Manipulable Bit Range After Reset 1-bit 8-bit 16-bit - 0000H - - - 0000H - - - 0000H - - - 0000H - - Serial mode register 10 SMR10 R/W - - 0020H Serial mode register 11 SMR11 R/W - - 0020H Serial mode register 12 SMR12 R/W - - 0020H Serial mode register 13 SMR13 R/W - - 0020H Serial communication operation setting register 10 SCR10 R/W - - 0087H F015AH Serial communication operation F015BH setting register 11 SCR11 R/W - - 0087H F015CH Serial communication operation F015DH setting register 12 SCR12 R/W - - 0087H F015EH Serial communication operation F015FH setting register 13 SCR13 R/W - - 0087H R 0000H - - 0000H - - 0000H - - - 0000H F0150H F0151H F0152H F0153H F0154H F0155H F0156H F0157H F0158H F0159H Serial channel enable status register 1 SE1L F0161H F0162H Serial channel start register 1 SS1L Serial channel stop register 1 ST1L Serial clock select register 1 SPS1L SPS1 - - Serial output register 1 SO1 R/W - - 0F0FH SOE1L SOE1 R/W 0000H - - - 0000H - - - 0000H - - F0160H ST1 R/W R/W - F0167H F0168H R/W - F0165H F0166H SS1 - F0163H F0164H SE1 - F0169H F016AH Serial output enable register 1 - F016BH F0174H Serial output level register 1 F0178H SOL1L SOL1 R/W - F0175H Serial standby control register 1 SSC1L SSC1 - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 R/W 137 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (5/8) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit Timer counter register 00 TCR00 R - - FFFFH Timer counter register 01 TCR01 R - - FFFFH Timer counter register 02 TCR02 R - - FFFFH Timer counter register 03 TCR03 R - - FFFFH Timer counter register 04 TCR04 R - - FFFFH F018AH Timer counter register 05 TCR05 R - - FFFFH TCR06 R - - FFFFH TCR07 R - - FFFFH Timer mode register 00 TMR00 R/W - - 0000H Timer mode register 01 TMR01 R/W - - 0000H Timer mode register 02 TMR02 R/W - - 0000H Timer mode register 03 TMR03 R/W - - 0000H Timer mode register 04 TMR04 R/W - - 0000H F019AH Timer mode register 05 TMR05 R/W - - 0000H TMR06 R/W - - 0000H TMR07 R/W - - 0000H R - 0000H - - - 0000H - - F0180H F0181H F0182H F0183H F0184H F0185H F0186H F0187H F0188H F0189H F018BH F018CH Timer counter register 06 F018DH F018EH Timer counter register 07 F018FH F0190H F0191H F0192H F0193H F0194H F0195H F0196H F0197H F0198H F0199H F019BH F019CH Timer mode register 06 F019DH F019EH Timer mode register 07 F019FH F01A0H Timer status register 00 F01A1H F01A2H Timer status register 01 F01A3H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 TSR00L TSR00 - TSR01L TSR01 - R 138 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (6/8) Address Special Function Register (SFR) Name F01A4H Timer status register 02 F01A5H F01A6H Timer status register 03 F01A7H F01A8H Timer status register 04 F01A9H F01AAH Timer status register 05 F01ABH F01ACH Timer status register 06 F01ADH F01AEH Timer status register 07 F01AFH Symbol R/W TSR02L TSR02 R - TSR03L TSR03 - TSR04L TSR04 TSR05L TSR05 TSR06L TSR06 TSR07L TSR07 R - TS0L F01B6H Timer clock select register 0 R - F01B2H Timer channel start register 0 F01B5H R - TE0L F01B4H Timer channel stop register 0 R - F01B0H Timer channel enable status F01B1H register 0 F01B3H R TE0 R TS0 R/W TT0 R/W - - TT0L - TPS0 Manipulable Bit Range After Reset 1-bit 8-bit 16-bit - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - 0000H - - 0000H - - 0000H - - R/W - - 0000H R/W - 0000H - - 0000H - - - 0000H - - - 0000H F01B7H F01B8H Timer output register 0 F01B9H F01BAH Timer output enable register 0 F01BBH F01BCH Timer output level register 0 F01BDH F01BEH Timer output mode register 0 F01BFH F01C0H Timer counter register 10 TO0L TO0 - TOE0L TOE0 R/W - TOL0L TOL0 R/W - TOM0L TOM0 R/W - - TCR10 - R - - FFFFH TCR11 R - - FFFFH TCR12 R - - FFFFH TCR13 R - - FFFFH F01C1H F01C2H Timer counter register 11 F01C3H F01C4H Timer counter register 12 F01C5H F01C6H Timer counter register 13 F01C7H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 139 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (7/8) Address Special Function Register (SFR) Name F01C8H Timer counter register 14 Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit TCR14 R - - FFFFH TCR15 R - - FFFFH TCR16 R - - FFFFH TCR17 R - - FFFFH TMR10 R/W - - 0000H TMR11 R/W - - 0000H TMR12 R/W - - 0000H TMR13 R/W - - 0000H TMR14 R/W - - 0000H TMR15 R/W - - 0000H TMR16 R/W - - 0000H TMR17 R/W - - 0000H R - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - 0000H - - 0000H - - F01C9H F01CAH Timer counter register 15 F01CBH F01CCH Timer counter register 16 F01CDH F01CEH Timer counter register 17 F01CFH F01D0H Timer mode register 10 F01D1H F01D2H Timer mode register 11 F01D3H F01D4H Timer mode register 12 F01D5H F01D6H Timer mode register 13 F01D7H F01D8H Timer mode register 14 F01D9H F01DAH Timer mode register 15 F01DBH F01DCH Timer mode register 16 F01DDH F01DEH Timer mode register 17 F01DFH F01E0H Timer status register 10 F01E1H F01E2H Timer status register 11 F01E3H F01E4H Timer status register 12 F01E5H F01E6H Timer status register 13 F01E7H F01E8H Timer status register 14 F01E9H F01EAH Timer status register 15 F01EBH F01ECH Timer status register 16 F01EDH F01EEH Timer status register 17 F01EFH TSR10L TSR10 - TSR11L TSR11 - TSR12L TSR12 R - TSR14L TSR14 R - TSR15L TSR15 R - TSR16L TSR16 R - TSR17L TSR17 R - TE1L F01F2H Timer channel start register 1 TS1L R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 R - TSR13L TSR13 F01F0H Timer channel enable status F01F1H register 1 F01F3H R TE1 R - - TS1 R/W 140 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Extended SFR (2nd SFR) List (8/8) Address Special Function Register (SFR) Name F01F4H Timer channel stop register 1 Symbol TT1L TT1 R/W Manipulable Bit Range 1-bit 8-bit 16-bit 0000H R/W - F01F5H F01F6H Timer clock select register 1 TPS1 After Reset - - R/W - - 0000H R/W - 0000H - - 0000H - - - 0000H - - - 0000H - - F01F7H F01F8H Timer output register 1 TO1L TO1 - F01F9H F01FAH Timer output enable register 1 TOE1L TOE1 R/W - F01FBH F01FCH Timer output level register 1 TOL1L TOL1 R/W - F01FDH F01FEH Timer output mode register 1 TOM1L TOM1 R/W - F01FFH F0200H DMA SFR address register 2 DSA2 R/W - - 00H F0201H DMA SFR address register 3 DSA3 R/W - - 00H F0202H DMA RAM address register 2L DRA2L DRA2 R/W - 00H F0203H DMA RAM address register 2H DRA2H R/W - F0204H DMA RAM address register 3L DRA3L DRA3 R/W - F0205H DMA RAM address register 3H DRA3H R/W - F0206H DMA byte count register 2L DBC2L DBC2 R/W - F0207H DMA byte count register 2H DBC2H R/W - F0208H DMA byte count register 3L DBC3L DBC3 R/W - F0209H DMA byte count register 3H 00H 00H 00H 00H 00H 00H DBC3H R/W - F020AH DMA mode control register 2 DMC2 R/W - 00H F020BH DMA mode control register 3 DMC3 R/W - 00H F020CH DMA operation control register 2 DRC2 R/W - 00H F020DH DMA operation control register 3 DRC3 R/W - 00H F0230H IICA control register 00 IICCTL00 R/W - 00H F0231H IICA control register 01 IICCTL01 R/W - 00H F0232H IICA low-level width setting register 0 IICWL0 R/W - - FFH F0233H IICA high-level width setting register 0 IICWH0 R/W - - FFH F0234H Slave address register 0 SVA0 R/W - - 00H F0238H IICA control register 10 IICCTL10 R/W - 00H F0239H IICA control register 11 IICCTL11 R/W - 00H F023AH IICA low-level width setting register 1 IICWL1 R/W - - FFH F023BH IICA high-level width setting register 1 IICWH1 R/W - - FFH F023CH Slave address register 1 SVA1 R/W - - 00H F02F0H Flash memory CRC control register CRC0CTL R/W - 00H F02F2H Flash memory CRC operation result register PGCRCL R/W - - 0000H F02FAH CRC data register CRCD R/W - - 0000H 00H Remark For SFRs in the SFR area, see Table 3-5 SFR List. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 141 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: -128 to +127 or -32768 to +32767) to the program counter (PC)'s value (the start address of the next instruction), and specifies the program address to be used as the branch destination. Relative addressing is applied only to branch instructions. Figure 3-28. Outline of Relative Addressing PC OP code DISPLACE 8/16 bits 3.3.2 Immediate addressing [Function] Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the program address to be used as the branch destination. For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses. Figure 3-29. Example of CALL !!addr20/BR !!addr20 PC OP code Low Addr. High Addr. Seg Addr. Figure 3-30. Example of CALL !addr16/BR !addr16 PC PCS PCH PCL OP code 0000 Low Addr. High Addr. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 142 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT instructions. In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH. Figure 3-31. Outline of Table Indirect Addressing OP code High Addr. 00000000 10 0 Low Addr. Table address Memory 0000 PC R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 PCS PCH PCL 143 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR AX instructions. Figure 3-32. Outline of Register Direct Addressing OP code rp CS PC R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 PCS PCH PCL 144 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. Implied addressing can be applied only to MULU X. Figure 3-33. Outline of Implied Addressing OP code A register Memory 3.4.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL Figure 3-34. Outline of Register Addressing OP code Register Memory R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 145 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) ES: ADDR16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) Figure 3-35. Example of ADDR16 FFFFFH OP code Low Addr. Target memory High Addr. F0000H Memory Figure 3-36. Example of ES:ADDR16 FFFFFH ES OP code Low Addr. Target memory High Addr. 00000H Memory R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 146 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier SADDR Description Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (only the space from FFE20H to FFF1FH is specifiable) SADDRP Label, FFE20H to FFF1FH immediate data, or 0FE20H to 0FF1FH immediate data (even address only) (only the space from FFE20H to FFF1FH is specifiable) Figure 3-37. Outline of Short Direct Addressing OP code FFF1FH saddr saddr FFE20H Memory Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20bit immediate data. Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH are specified for the memory. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 147 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier SFR SFRP Description SFR name 16-bit-manipulatable SFR name (even address only) Figure 3-38. Outline of SFR Addressing FFFFFH OP code SFR FFF00H SFR Memory R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 148 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description - [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) - ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register) Figure 3-39. Example of [DE], [HL] FFFFFH OP code rp Target memory F0000H Memory Figure 3-40. Example of ES:[DE], ES:[HL] FFFFFH ES OP code rp Target memory 00000H Memory R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 149 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address. [Operand format] Identifier Description - [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable) - word[B], word[C] (only the space from F0000H to FFFFFH is specifiable) - word[BC] (only the space from F0000H to FFFFFH is specifiable) - ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register) - ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register) - ES:word[BC] (higher 4-bit addresses are specified by the ES register) Figure 3-41. Example of [SP+byte] FFFFFH SP Target memory F0000H OP code byte Memory R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 150 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-42. Example of [HL + byte], [DE + byte] FFFFFH rp (HL/DE) Target memory F0000H OP code byte Memory Figure 3-43. Example of word[B], word[C] FFFFFH r (B/C) Target memory F0000H OP code Low Addr. High Addr. Memory Figure 3-44. Example of word[BC] FFFFFH rp (BC) Target memory F0000H OP code Low Addr. High Addr. Memory R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 151 RL78/G13 CHAPTER 3 CPU ARCHITECTURE Figure 3-45. Example of ES:[HL + byte], ES:[DE + byte] FFFFFH ES rp (HL/DE) Target memory OP code 00000H byte Memory Figure 3-46. Example of ES:word[B], ES:word[C] FFFFFH ES r (B/C) Target memory OP code 00000H Low Addr. Memory High Addr. Figure 3-47. Example of ES:word[BC] FFFFFH ES rp (BC) Target memory OP code 00000H Low Addr. Memory High Addr. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 152 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address. [Operand format] Identifier Description - [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable) - ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register) Figure 3-48. Example of [HL+B], [HL+C] FFFFFH OP code rp (HL) Target memory F0000H r (B/C) Memory Figure 3-49. Example of ES:[HL+B], ES:[HL+C] FFFFFH OP code ES rp (HL) Target memory 00000H r (B/C) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Memory 153 RL78/G13 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Stack addressing is applied only to the internal RAM area. [Operand format] Identifier - Description PUSH AX/BC/DE/HL POP AX/BC/DE/HL CALL/CALLT RET BRK RETB (Interrupt request generated) RETI R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 154 RL78/G13 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions <R> The RL78/G13 microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 155 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-1. Port Configuration (1/2) Item Control registers Configuration Port mode registers (PM0 to PM12, PM14, PM15) Port registers (P0 to P15) Pull-up resistor option registers (PU0, PU1, PU3 to PU12, PU14) Port input mode registers (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) Port output mode registers (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) Port mode control registers (PMC0, PMC3, PMC10 to PMC12, PMC14) A/D port configuration register (ADPC) Peripheral I/O redirection register (PIOR) Global digital input disable register (GDIDIS) Port * 20-pin products Total: 16 (CMOS I/O: 13, CMOS input: 3) * 24-pin products Total: 20 (CMOS I/O: 15, CMOS input: 3, N-ch open drain I/O: 2) * 25-pin products Total: 21 (CMOS I/O: 15, CMOS input: 3, CMOS output: 1, N-ch open drain I/O: 2) * 30-pin products Total: 26 (CMOS I/O: 21, CMOS input: 3, N-ch open drain I/O: 2) * 32-pin products Total: 28 (CMOS I/O: 22, CMOS input: 3, N-ch open drain I/O: 3) * 36-pin products Total: 32 (CMOS I/O: 26, CMOS input: 3, N-ch open drain I/O: 3) * 40-pin products Total: 36 (CMOS I/O: 28, CMOS input: 5, N-ch open drain I/O: 3) * 44-pin products Total: 40 (CMOS I/O: 31, CMOS input: 5, N-ch open drain I/O: 4) * 48-pin products Total: 44 (CMOS I/O: 34, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) * 52-pin products Total: 48 (CMOS I/O: 38, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) * 64-pin products Total: 58 (CMOS I/O: 48, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 156 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Configuration (2/2) Item Port Configuration * 80-pin products Total: 74 (CMOS I/O: 64, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) * 100-pin products Total: 92 (CMOS I/O: 82, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) * 128-pin products Total: 120 (CMOS I/O: 110, CMOS input: 5, CMOS output: 1, N-ch open drain I/O: 4) Pull-up resistor R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 * 20-pin products Total: 10 * 24-pin products Total: 12 * 25-pin products Total: 12 * 30-pin products Total: 17 * 32-pin products Total: 18 * 36-pin products Total: 20 * 40-pin products Total: 21 * 44-pin products Total: 23 * 48-pin products Total: 26 * 52-pin products Total: 30 * 64-pin products Total: 40 * 80-pin products Total: 52 * 100-pin products Total: 67 * 128-pin products Total: 95 157 RL78/G13 CHAPTER 4 PORT FUNCTIONS Caution Most of the following descriptions in this chapter use the 128-pin products and set to 00H of peripheral I/O redirection register (PIOR) as an example. 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P07 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). Input to the P01, P03 and P04 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 0 (PIM0). Output from the P00 and P02 to P04 pins can be specified as N-ch open-drain output (VDD tolerance tolerance Note 2 Note 1 /EVDD ) in 1-bit units using port output mode register 0 (POM0). Input to the P00 to P03 pins can be specified as analog input or digital input in 1-bit units, using port mode control register 0 (PMC0). This port can also be used for timer I/O, A/D converter analog input, serial interface data I/O, and clock I/O. When reset signal is generated, the following configuration will be set. * P00 and P01 pins of the 20, 24, 25, 30, and 32-pin products *** Analog input * P00, P01 and P04 to P07 pins of the other products *** Input mode * P02 and P03 pins of the other products *** Analog input Notes 1. 2. When 20- to 52-pin products When 64- to 128-pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 158 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-2. Settings of Registers When Using Port 0 Name I/O P00 PM0x Input PIM0x 1 POM0x - 0 Output 0 0 P01 Input 1 1 Output P02 0 Input P03 Input P07 Notes 1. x 0 0 0 1 0 x 0 0 1 x x 0 0 x 1 1 0 x 1 1 x 0 x 0 0 x 1 Input 1 - - Output 0 Input 1 Output 0 Output P05, P06 0 1 - 0 0 0 Input - 0 0 1 P04 0 0 0 1 Output 1 0 x 1 Output x PMC0x 0 0 0 Note 1 Note 1 Alternate Function Setting x TxD1 output = 1 Note 3 CMOS output Note 1 N-ch O.D. output Note 1 x Note 1 x Note 1 Note 2 Note 2 TO00 output = 0 CMOS input TTL input Note 4 x SO10/TxD1 output = 1 Note 5 Note 2 Note 2 x Note 2 x Note 2 SDA10 output = 1 CMOS input TTL input Note 5 - CMOS output Note 2 - CMOS output N-ch O.D. output N-ch O.D. output x CMOS input x SCK10/SCL10 output = 1 TTL input Note 5 CMOS output N-ch O.D. output - TO05 output, TO06 output = 0 - Remark - Note 6 - 20-, 24-, 25-, 30-, 32-pin products only 2. 52-, 64-, 80-, 100-, 128-pin products only 3. To use P00/TxD1 as a general-purpose port in 20- to 48-pin products, set bits 2 and 3 (SE02, SE03) of serial channel enable status register 0 (SE0), bits 2 and 3 (SO02, SO03) of serial output register 0 (SO0) and bits 2 and 3 (SOE02, SOE03) of serial output enable register 0 (SOE0) to the default status. 4. To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register 0 (TO0) and bit 0 (TOE00) of timer output enable register 0 (TOE0) to "0", which is the same as their default status setting. 5. To use P02/SO10/TxD1/ANI17, P03/SI10/RxD1/SDA10/ANI16, or P04/SCK10/SCL10 as a generalpurpose port, set bits 2 and 3 (SE02, SE03) of serial channel enable status register 0 (SE0), bits 2 and 3 (SO02, SO03) of serial output register 0 (SO0) and bits 2 and 3 (SOE02, SOE03) of serial output enable register 0 (SOE0) to the default status. 64-, 80-pin products only 6. Remark x: don't care PM0x: Port mode register 0 PIM0x: Port input mode register 0 POM0x: Port output mode register 0 PMC0x: Port mode control register 0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 159 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-1 to 4-6 show block diagrams of port 0 for 128-pin products. <R> Figure 4-1. Block Diagram of P00 EVDD WRPU PU0 PU00 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P00) P00/TI00 WRPOM POM0 POM00 WRPM PM0 PM00 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port output mode register 0 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 160 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 WRPIM PIM0 PIM01 EVDD WRPU PU0 PU01 P-ch CMOS Selector Internal bus RD TTL WRPORT P0 Output latch (P01) P01/TO00 WRPM PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 161 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 <R> EVDD WRPU PU0 PU02 P-ch WRPMC PMC0 PMC02 Selector Internal bus RD WRPORT P0 Output latch (P02) P02/SO10/TxD1/ANI17 WRPOM POM0 POM02 WRPM PM0 PM02 Alternate function A/D converter P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port output mode register 0 PMC0: Port mode control register 0 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 162 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P03 <R> WRPIM PIM0 PIM03 EVDD WRPU PU0 PU03 P-ch WRPMC PMC0 PMC03 Alternate function Selector Internal bus CMOS RD TTL WRPORT P0 Output latch (P03) P03/SI10/RxD1/ SDA10/ANI16 WRPOM POM0 POM03 WRPM PM0 PM03 Alternate function A/D converter P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 POM0: Port output mode register 0 PMC0: Port mode control register 0 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 163 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-5. Block Diagram of P04 WRPIM PIM0 PIM04 EVDD WRPU PU0 PU04 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P0 Output latch (P04) P04/SCK10/SCL10 WRPOM POM0 POM04 WRPM PM0 PM04 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 POM0: Port output mode register 0 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 164 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P05 and P07 EVDD WRPU PU0 PU05 to PU07 P-ch Selector Internal bus RD WRPORT P0 Output latch (P05 to P07) P05 to P07 WRPM PM0 PM05 to PM07 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 165 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). Input to the P10, P11, and P13 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 1 (PIM1). Output from the P10 to P15 and P17 pins can be specified as N-ch open-drain output (VDD tolerance tolerance Note 2 Note 1 /EVDD ) in 1-bit units using port output mode register 1 (POM1). This port can also be used for serial interface data I/O, clock I/O, programming UART I/O, timer I/O, and external interrupt request input. Reset signal generation sets port 1 to input mode. Notes 1. 2. When 20- to 52-pin products When 64- to 128-pin products Table 4-3. Settings of Registers When Using Port 1 (1/2) Name P10 I/O PM1x PIM1x POM1x PMCxx 1 0 x - 1 1 x Input Output P11 Input Output P12 Input Output 0 x 0 P14 x 1 1 0 x 1 1 x x 0 x 1 1 - x 0 1 1 x Output 0 x 0 0 x 1 1 0 x 1 1 x 0 P15 Input Output - x 1 0 x 1 1 x x 0 x ) Note 1 Note 6 ) x - Note 6 , Note 7 N-ch O.D. output TTL input Note 1 Note 6 , Note 7 CMOS output N-ch O.D. output ) x CMOS input x TTL input 0 SCK20/SCL20 output = 1 1 PCLBUZ1 output = 0 (TO02 output = 0 CMOS output CMOS input SDA20 output = 1 - N-ch O.D. output ) x SCLA0 output = 0 CMOS output TTL input Note 1 x (TO03 output = 0 N-ch O.D. output CMOS input x (TO04 output = 0 CMOS output CMOS input TxD2/SO20 output = 1 0 1 0 Note 6 SO00/TxD1 output = 1 - N-ch O.D. output TTL input Note 1 x (TO05 output = 0 CMOS output CMOS input SDAA0 output = 0 x 0 (TO06 output = 0 1 x ) x SDA00 output = 1 0 0 Note 6 Note 1 x 0 1 Output TTL input (TO07 output = 0 Input Input x - Remark CMOS input SCK00/SCL00 output = 1 0 P13 x 0 0 Note 9 Alternate Function Setting Note 1 Note 2 Note 6 CMOS output N-ch O.D. output ) (Notes and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 166 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-4. Settings of Registers When Using Port 1 (2/2) Pin Name Name PM1x PIM1x POM1x PMCxx 1 0 x - 1 1 x Alternate Function Setting Note 10 Remark I/O P16 Input Output 0 x x x TO01 output = 0 0 SO11 output = 1 P17 0 x CMOS input - TTL input Note 3 x Input 1 1 1 x Output 0 x 0 TO02 output = 0 CMOS input 0 x 1 SDA11 output = 0 x SO11 output = 0 TTL input Note 3 CMOS output Note 4 N-ch O.D. output Note 4 (SO00/TxD0 output = 1 Notes 1. CMOS output Note 4 Note 8 ) P10/SCK00/SCL00, P11/SI00/RxD0/TOOLRxD/SDA00, P12/SO00/TxD0/TOOLTxD, P13/TxD2/SO20, P14/RxD2/SI20/SDA20, or P15/SCK20/SCL20 as a general-purpose port, set bits 0 and 1 (SEm0, SEm1) of serial channel enable status register m (SEm), bits 0 and 1 (SOm0, SOm1) of serial output register m (SOm) and bits 0 and 1 (SOEm0, SOEm1) of serial output enable register m (SOEm) to the default status (m = 0, 1). 2. To use P15/PCLBUZ1/SCK20/SCL20 as a general-purpose port in 30- to 52-pin products only, set bit 7 (PCLOE1) of clock output select register 1 (CKS1) to "0", which is the same as their default status setting. 3 To use P16/TI01/TO01/INTP5 or P17/TI02/TO02 as a general-purpose port, set bits 1 and 2 (TO01, TO02) of timer output register 0 (TO0) and bits 1 and 2 (TOE01, TOE02) of timer output enable register 0 (TOE0) to "0", which is the same as their default status setting. 4 To use P16/TI01/TO01/INTP5/SO11 or P17/TI02/TO02/SI11/SDA11 as a general-purpose port in 20-pin products only, set bit 3 (SE03) of serial channel enable status register 0 (SE0), bit 3 (SO03) of serial output register 0 (SO0) and bit 3 (SOE03) of serial output enable register 0 (SOE0) to the default status. 5. P17/TI02/TO02/SO11 as a general-purpose port in 24-, 25-pin products only, set set bit 3 (SE03) of serial channel enable status register 0 (SE0), bit 3 (SO03) of serial output register 0 (SO0) and bit 3 (SOE03) of serial output enable register 0 (SOE0) to the default status. 6. If P10 to P15 are used as general-purpose ports and PIOR0 is set to 1, use the corresponding bits in bits 2 to 7 (TO02 to TO07) of timer output register 0 (TO0) and bits 2 to 7 (TOE02 to TOE07) of timer output enable register 0 with "0", which is the same as their initial setting. 7. To use P13 and P14 as a general-purpose port, do not set PIOR2 to 1. 8. If P17 is used as general-purpose port and PIOR1 is set to 1, use bits 0 and 1 (SE00, SE01) of serial channel enable status register 0 (SE0), bits 0 and 1 (SO00, SO01) of serial output register 0 (SO0) and bits 0 and 1 (SOE00, SOE01) of Serial output enable register 0 (SOE0) with the same setting as the initial status. 9. Remark The descriptions in parentheses indicate the case where PIORx = 1. x: don't care PM1x: Port mode register 1 PIM1x: Port input mode register 1 POM1x: Port output mode register 1 PMC1x: Port mode control register 1 PIORx: Peripheral I/O redirection register R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 167 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-7 to 4-12 show block diagrams of port 1 for 128-pin products. Figure 4-7. Block Diagrams of P10 and P11 <R> WRPIM PIM1 PIM10, PIM11 EVDD WRPU PU1 PU10, PU11 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P10, P11) WRPOM POM1 POM10, POM11 P10/SCK00/SCL00/ (TI07)/(TO07), P11/SI00/RxD0/ SDA00/TOOLRxD/ (TI06)/(TO06) WRPM PM1 PM10, PM11 Alternate function 1 (serial array unit) Alternate function 2 (timer array unit) P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 168 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P12 <R> EVDD WRPU PU1 PU12 P-ch Alternate function Selector RD Internal bus WRPORT P1 Output latch (P12) WRPOM POM1 POM12 P12/SO00/ TxD0/TOOLTxD/ (INTP5)/(TI05)/ (TO5) WRPM PM1 PM12 Alternate function 1 (serial array unit) Alternate function 2 (timer array unit) P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 169 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P13 <R> WRPIM PIM1 PIM13 EVDD WRPU PU1 PU13 P-ch Alternate function CMOS Internal bus Selector RD TTL WRPORT P1 Output latch (P13) WRPOM P13/TxD2/SO20/ (SDAA0)/(TI04)/(TO04) POM1 POM13 WRPM PM1 PM13 Alternate function (sirial array unit) Alternate function (timer array unit, IICA) P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 170 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagrams of P14 and P15 <R> WRPIM PIM1 PIM14, PIM15 EVDD WRPU PU1 PU14, PU15 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P14, P15) P14/SI20/RxD2/SDA20, P15/SCK20/SCL20 WRPOM POM1 POM14, POM15 WRPM PM1 PM14, PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 171 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P16 WRPIM PIM1 PIM16 EVDD WRPU PU1 PU16 P-ch Alternate function Selector Internal bus CMOS RD TTL WRPORT P1 Output latch (P16) WRPM P16/TI01/TO01/INTP5/ (SI00/(RxD0)) PM1 PM16 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 172 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P17 <R> WRPIM PIM1 PIM17 EVDD WRPU PU1 PU17 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P17) WRPOM P17/TI02/TO02/ (SO00)/(TxD0) POM1 POM17 WRPM PM1 PM17 Alternate function 1 (serial array unit) Alternate function 2 (timer array unit) P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 173 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input and reference voltage input. To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the upper bit. To use P20/ANI0 to P27/ANI7 as digital output pins, set them in the digital I/O mode by using the ADPC register and in <R> the output mode by using the PM2 register. Use these pins starting from the upper bit. To use P20/ANI0 to P27/ANI7 as analog input pins, set them in the analog input mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit. Table 4-4. Settings of Registers When Using Port 2 Name P2n Remark x: I/O PM2x ADPC Alternate Function Setting Remark Input 1 01 to n+1H - To use P2n as a port, use these Output 0 01 to n+1H pins from a higher bit. don't care PM2x: Port mode register 2 ADPC: A/D port configuration register Table 4-5. Setting Functions of P20/ANI0 to P27/ANI7 Pins ADPC Register PM2 Register Digital I/O selection Input mode Analog input selection Input mode ADS Register - - Output mode Output mode P20/ANI0 to P27/ANI7 Pins Digital input Digital output Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. All P20/ANI0 to P27/ANI7 are set in the analog input mode when the reset signal is generated. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 174 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figure 4-13 shows a block diagram of port 2 for 128-pin products . Figure 4-13. Block Diagram of P20 to P27 WRADPC ADPC 0:Analog input 1:Digital I/O ADPC3 to ADPC0 Selector Internal bus RD WRPORT P2 P20/ANI0/AVREFP, P21/ANI1/AVREFM, P22/ANI2 to P27/ANI7 Output latch (P20 to P27) WRPM PM2 PM20 to PM27 A/D converter ADPC: A/D port configuration register P2: Port register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 175 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P37 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). Input to the P35 to P37 pins can be specified as analog input or digital input in 1-bit units, using port mode control register 3 (PMC3). This port can also be used for external interrupt request input, real-time clock correction clock output, clock/buzzer output, timer I/O, and A/D converter analog input. Reset signal generation sets P30 to P34 to input mode, and sets P35 to P37 to analog input. Table 4-6. Settings of Registers When Using Port 3 Name I/O P30 PM3x PMC3x Input 1 - Output 0 Alternate Function Setting Input 1 RTC1HZ output = 0 Output 0 - Note 1 TO03 output = 0 Note 3 (PCLBUZ0 output = 0 P35 to P37 Notes 1. - Note 2 x PCLBUZ0 output = 0 P32 to P34 Remark x SCK11/SCL11 output = 0 P31 Note 6 Note 4 Note 5 ) x Input 1 Output 0 Input 1 0 x Output 0 0 x x To use P30/RTC1HZ/INTP3 as a general-purpose port, set bit 5 (RCLOE1) of real-time clock control register 0 (RTCC0) to "0", which is the same as its default status setting. 2. To use P30/INTP3/RTC1HZ/SCK11/SCL11 as a general-purpose port in 20-pin to 100-pin products, set bit 3 (SE03) of serial channel enable status register 0 (SE0), bit 3 (SO03) of serial output register 0 (SO0) and bit 3 (SOE03) of serial output enable register 0 (SOE0) to the default status. 3. To use P31/TI03/TO03/INTP4 as a general-purpose port, set bit 3 (TO03) of timer output register 0 (TO0) and bit 3 (TOE03) of timer output enable register 0 (TOE0) to "0", which is the same as their default status setting. 4. To use P31/TI03/TO03/INTP4/PCLBUZ0 as a general-purpose port in 24- to 44-pin products, set bit 7 (PCLOE0) of clock output select register 0 (CKS0) to "0", which is the same as their default status setting. 5. To use P31 as a general-purpose port in 48- to 128-pin products, do not set PIOR3 set to 1. 6. The descriptions in parentheses indicate the case where PIORx = 1. Remark x: don't care PM3x: Port mode register 3 PMC3x: Port mode control register 3 PIORx: Peripheral I/O redirection register R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 176 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-14 to 4-17 show block diagrams of port 3 for 128-pin products. Figure 4-14. Block Diagram of P30 EVDD WRPU PU3 PU30 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P30) P30/RTC1HZ/INTP3 WRPM PM3 PM30 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 177 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P31 EVDD WRPU PU3 PU31 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P31) P31/TI03/TO03/INTP4/ (PCLBUZ0) WRPM PM3 PM31 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 178 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P32 to P34 EVDD WRPU PU3 PU32 to PU34 P-ch Selector Internal bus RD WRPORT P3 Output latch (P32 to P34) P32 to P34 WRPM PM3 PM32 to PM34 P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 179 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P35 to P37 EVDD WRPU PU3 PU35 to PU37 P-ch WRPMC PMC3 Internal bus PMC35 to PMC37 Selector RD WRPORT P3 Output latch (P35 to P37) P35/ANI23 to P37/ANI21 WRPM PM3 PM35 to PM37 A/D converter P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 PMC3: Port mode controlregister 3 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 180 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). Input to the P43 and P44 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 4 (PIM4). Output from the P43 to P45 pins can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units using port output mode register 4 (POM4). This port can also be used for data I/O for a flash memory programmer/debugger, timer I/O, serial interface data I/O, clock I/O, and external interrupt request input. Reset signal generation sets port 4 to input mode. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 181 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-7. Settings of Registers When Using Port 4 Name I/O P40 P41 P42 P43 PM4x PIM4x POM4x Alternate Function Setting Input 1 - - x Output 0 Input 1 Output 0 Input 1 Output 0 Input Output P44 Input P45 P46 P47 Notes 1. x - - x TO07 output = 0 - - 1 0 x x 1 1 x x 0 x 0 0 x 1 1 0 x x 1 1 x x x 0 0 x 1 Input 1 - Output 0 0 0 1 Input 1 Output 0 Input 1 Output 0 - Note 2 CMOS input TTL input SCK01/SCL01 output = 1 Note 3 CMOS output N-ch O.D. output CMOS input TTL input SDA01 output = 1 Note 3 CMOS output N-ch O.D. output x x SO01 output = 1 Note 3 CMOS output N-ch O.D. output - x TO05 output = 0 - Note 1 x TO04 output = 0 0 Output Remark - Note 2 x x P41/TI07/TO07 as a general-purpose port in 44- to 80-pin products, set bit 7 (TO07) of timer output register 0 (TO0) and bit 7 (TOE07) of timer output enable register 7 (TOE7) to "0", which is the same as their default status setting. 2. To use P42/TI04/TO04 or P46/INTP1/TI05/TO05 as a general-purpose port, set bits 4 and 5 (TO04, TO05) of timer output register 0 (TO0) and bits 4 and 5 (TOE04, TOE05) of timer output enable register 0 (TOE0) to "0", which is the same as their default status setting. 3. P43/SCK01/SCL01, P44/SI01/SDA01, P45/SO01 as a general-purpose port, set bit 1 (SE01) of serial channel enable status register 0 (SE0), bit 1 (SO01) of serial output register 0 (SO0) and bit 1 (SOE01) of serial output enable register 0 (SOE0) to the default status. Caution Remark When a tool is connected, the P40 pin cannot be used as a port pin. x: don't care PM4x: Port mode register 4 PIM4x: Port input mode register 4 POM4x: Port output mode register 4 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 182 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-18 to 4-24 show block diagrams of port 4 for 128-pin products. Figure 4-18. Block Diagram of P40 EVDD WRPU PU4 PU40 P-ch Alternate function Selector WRPORT P4 Output latch (P40) WRPM Selector Internal bus RD P40/TOOL0 PM4 PM40 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 183 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of P41 EVDD WRPU PU4 PU41 P-ch Selector Internal bus RD WRPORT P4 Output latch (P41) P41 WRPM PM4 PM41 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 184 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P42 EVDD WRPU PU4 PU42 P-ch Alternate function Selector Internal bus RD WRPORT P4 Output latch (P42) P42/TI04/TO04 WRPM PM4 PM42 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 185 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P43, P44 <R> WRPIM PIM4 PIM43, PIM44 EVDD WRPU PU4 PU43, PU44 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P4 Output latch (P43, P44) WRPOM P43/SCK01/SCL01 P44/SI01/SDA01 POM4 POM43, POM44 WRPM PM4 PM43, PM44 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 PIM4: Port input mode register 4 POM4: Port output mode register 4 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 186 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-22. Block Diagram of P45 EVDD WRPU PU4 PU45 P-ch Internal bus Selector RD WRPORT P4 Output latch (P45) P45/SO01 WRPOM POM4 POM45 WRPM PM4 PM45 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 POM4: Port output mode register 4 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 187 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of P46 EVDD WRPU PU4 PU46 P-ch Alternate function Selector Internal bus RD WRPORT P4 Output latch (P46) P46/TI05/TO05/INTP1 WRPM PM4 PM46 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 188 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P47 EVDD WRPU PU4 PU47 P-ch Alternate function Selector Internal bus RD WRPORT P4 Output latch (P47) P47/INTP2 WRPM PM4 PM47 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 189 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 5 Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5). Input to the P53 to P55 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 5 (PIM5). Output from the P50, and P52 to P55 pin can be specified as N-ch open-drain output (VDD tolerance tolerance Note 2 Note 1 /EVDD ) in 1-bit units using port output mode register 5 (POM5). This port can also be used for serial interface data I/O, clock I/O. Reset signal generation sets port 5 to input mode. Notes 1. 2. When 20- to 52-pin products When 64- to 128-pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 190 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-8. Settings of Registers When Using Port 5 Pin Name Name PM5x PIM5x POM5x Input 1 - x Output 0 0 0 1 Alternate Function Setting Note 5 Remark I/O P50 P51 P52 Input 1 Output 0 Input 1 Output P53 Input Output P54 Input Output P55 Input Output P56, P57 Notes 1. - x SDA11 output = 1 - x x 0 0 0 1 x x 1 1 x x 0 0 x 1 1 0 x 1 1 x SDA31 output = 1 x 0 1 1 0 x x 1 1 x x 0 x 1 Input 1 - - Output 0 TTL input Note 2 CMOS output CMOS input x x 0 CMOS input x 0 x CMOS output N-ch O.D. output 0 0 Note 2 N-ch O.D. output 0 x Note 1 x SO31 output = 1 1 0 CMOS output N-ch O.D. output SO11 output = 1 - Note 1 TTL input SCK31/SCL31 output = 1 Note 1 CMOS output N-ch O.D. output (SCK00 output = 1 CMOS input TTL input Note 3 (PCLBUZ1 output = 0 ) Note 4 CMOS output ) N-ch O.D. output - To use P50 as a general-purpose port in 24- to 100-pin products or to use P51 as a general-purpose port in 30- to 100-pin products, set bit 3 (SE03) of serial channel enable status register 0 (SE0), bit 3 (SO03) of serial output register 0 (SO0) and bit 3 (SOE03) of serial output enable register 0 (SOE0) to the default status. 2. P52/SO31, P53/SI31/SDA31, P54/SCK31/SCL31 as a general-purpose port, set bit 3 (SE13) of serial channel enable status register 1 (SE1), bit 3 (SO13) of serial output register 1 (SO1) and bit 3 (SOE13) of serial output enable register 1 (SOE1) to the default status. 3. To use P55 as a general-purpose port when PIOR1 = 1, set bits 0 and 1 (SE00, SE01) of serial channel enable status register 0 (SE0), bits 0 and 1 (SO00, SO01) of serial output register 0 (SO0) and bits 0 and 1 (SOE00, SOE01) of serial output enable register 0 (SOE0) to the default status. 4. To use P55 as a general-purpose port when PIOR4 = 1, set clock output select registers 1 (CKS1) to the default status. 5. Remark The descriptions in parentheses indicate the case where PIORx = 1. x: don't care PM5x: Port mode register 5 PIM5x: Port input mode register 5 POM5x: Port output mode register 5 PIORx: Peripheral I/O redirection register R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 191 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-25 to 4-30 show block diagrams of port 5 for 128-pin products. Figure 4-25. Block Diagram of P50 <R> EVDD WRPU PU5 PU50 P-ch Selector Internal bus RD WRPORT P5 Output latch (P50) P50 WRPOM POM5 POM50 WRPM PM5 PM50 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 POM5: Port output mode register 5 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 192 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-26. Block Diagram of P51 EVDD WRPU PU5 PU51 P-ch Selector Internal bus RD WRPORT P5 Output latch (P51) P51 WRPM PM5 PM51 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 193 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-27. Block Diagram of P52 EVDD WRPU PU5 PU52 P-ch Internal bus Selector RD WRPORT P5 Output latch (P52) P52/SO31 WRPOM POM5 POM52 WRPM PM5 PM52 Alternate function P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 POM5: Port output mode register 5 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 194 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of P53, P54 <R> WRPIM PIM5 PIM53, PIM54 EVDD WRPU PU5 PU53, PU54 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P5 Output latch (P53, P54) P53/SI31/SDA31, P54/SCK31/SCL31 WRPOM POM5 POM53, POM54 WRPM PM5 PM53, PM54 Alternate function P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PIM5: Port input mode register 5 POM5: Port output mode register 5 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 195 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-29. Block Diagram of P55 WRPIM PIM5 PIM55 EVDD WRPU PU5 PU55 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P5 Output latch (P55) WRPOM P55/(PCLBUZ1)/ (SCK00) POM5 POM55 WRPM PM5 PM55 Alternate function 1 (serial array unit) Alternate function 2 (clock/buzzer output) P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 PIM5: Port input mode register 5 POM5: Port output mode register 5 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 196 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of P56, P57 <R> EVDD WRPU PU5 PU56, PU57 P-ch Alternate function Selector Internal bus RD WRPORT P5 Output latch (P56, P57) P56/(INTP1), P57/(INTP3) WRPM PM5 PM56, PM57 P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 197 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). When the P64 to P67 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 6 (PU6). The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance). This port can also be used for serial interface data I/O and clock I/O, and timer I/O. Reset signal generation sets port 6 to input mode. Table 4-9. Settings of Registers When Using Port 6 Name I/O P60 P61 P62 P63 P64 P65 P66 P67 Notes 1. PM6x Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 Alternate Function Setting SCLA0 output = 0 SDAA0 output = 0 SCLA1 output = 0 SDAA1 output = 0 TO10 output = 0 TO11 output = 0 TO12 output = 0 TO13 output = 0 Remark Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Stop the operation of serial interface IICA when using P60/SCLA0, P61/SDAA0, P62/SCLA1, and P63/SDAA1 as general-purpose ports. 2. To use P64/TI10/TO10 to P67/TI13/TO13 as a general-purpose port, set bits 0 to 3 (TO10 to TO13) of timer output register 1 (TO1) and bits 0 to 3 (TOE10 to TOE13) of timer output enable register 1 (TOE1) to "0", which is the same as their default status setting. Remark x: don't care PM6x: Port mode register 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 198 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-31 and 4-32 show block diagrams of port 6 for 128-pin products Figure 4-31. Block Diagram of P60 to P63 Alternate function Internal bus Selector RD WRPORT P6 Output latch (P60 to P63) WRPM P60/SCLA0, P61/SDAA0, P62/SCLA1, P63/SDAA1 PM6 PM60 to PM63 Alternate function P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 199 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of P64 to P67 EVDD WRPU PU6 PU64 to PU67 P-ch Alternate function Selector Internal bus RD WRPORT P6 Output latch (P64 to P67) P64/TI10/TO10 to P67/TI13/TO13 WRPM PM6 PM64 to PM67 Alternate function P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 200 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). Output from the P71 and P74 pins can be specified as N-ch open-drain output (VDD tolerance Note 1 /EVDD tolerance Note 2 ) in 1-bit units using port output mode register 7 (POM7). This port can also be used for key interrupt input, serial interface data I/O, clock I/O, and external interrupt request input. Reset signal generation sets port 7 to input mode. Notes 1. 2. When 20- to 52-pin products When 64- to 128-pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 201 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-10. Settings of Registers When Using Port 7 Name I/O P70 P71 P72 PM7x POM7x Input 1 - Output 0 Input 1 x Output 0 0 0 1 1 - Input P73 P74 P75 P76 P77 Notes 1. Input 1 Output 0 Input 1 x Output 0 0 0 1 Input 1 - Output 0 Input 1 0 Input 1 Output 0 Remark Note 1 x SDA21 output = 1 Note 1 CMOS output N-ch O.D. output x SO21 output = 1 0 Note 4 x SCK21/SCL21 output = 1 Output Output Alternate Function Setting - Note 1 x SO01 output = 1 Note 2 x SDA01 output = 1 Note 2 CMOS output N-ch O.D. output x SCK01/SCL01 output = 1 - Note 2 x x - x (TxD2 output = 1 Note 3 ) To use P70/KR0/SCK21/SCL21, P71/KR1/SI21/SDA21 or P72/KR2/SO21 as a general-purpose port, set bit 1 (SE11) of serial channel enable status register 1 (SE1), bit 1 (SO11) of serial output register 1 (SO1) and bit 1 (SOE11) of serial output enable register 1 (SOE1) to the default status. 2. To use P73 to P75 as a general-purpose port in 48- to 64-pin products, set bit 1 (SE01) of serial channel enable status register 0 (SE0), bit 1 (SO01) of serial output register 0 (SO0) and bit 1 (SOE01) of serial output enable register 0 (SOE0) to the default status. 3. To use P55 as a general-purpose port when PIOR1 = 1, set bits 0 and 1 (SE10, SE11) of serial channel enable status register 1 (SE1), bits 0 and 1 (SO10, SO11) of serial output register 1 (SO1) and bits 0 and 1 (SOE10, SOE11) of serial output enable register 1 (SOE1) to the default status. 4. Remark The descriptions in parentheses indicate the case where PIORx = 1. x: don't care PM7x: Port mode register 7 POM7x: Port output mode register 7 PIORx: Peripheral I/O redirection register R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 202 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-33 to 4-37 show block diagrams of port 7 for 128-pin products . Figure 4-33. Block Diagram of P70 EVDD WRPU PU7 PU70 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P70) P70/KR0/SCK21/SCL21 WRPM PM7 PM70 Alternate function P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 203 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of P71 <R> EVDD WRPU PU7 PU71 P-ch Alternate function Internal bus Selector RD WRPORT P7 Output latch (P71) P71/KR1/SI21/SDA21 WRPOM POM7 POM71 WRPM PM7 PM71 Alternate function P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 POM7: Port output mode register 7 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 204 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of P72 and P77 <R> EVDD WRPU PU7 PU72, PU77 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P72, P77) WRPM P72/KR2/SO21, P77/KR7/INTP11/ (TxD2) PM7 PM72, PM77 Alternate function P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 205 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-36. Block Diagram of P73, P75 and P76 EVDD WRPU PU7 PU73, PU75, PU76 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P73, P75, P76) WRPM P73/KR3, P75/KR5/INTP9, P76/KR6/INTP10/ (RxD2) PM7 PM73, PM75, PM76 P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 206 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-37. Block Diagram of P74 <R> EVDD WRPU PU7 PU74 P-ch Alternate function Selector Internal bus RD WRPORT P7 Output latch (P74) P74/KR4/INTP8 WRPOM POM7 POM74 WRPM PM7 PM74 P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 POM7: Port output mode register 7 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 207 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 8 Port 8 is an I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (PM8). When the P80 to P87 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 8 (PU8). Input to the P80 and P81 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 8 (PIM8). Output from the P80 to P82 pin can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units using port output mode register 8 (POM8). Reset signal generation sets port 8 to input mode. Table 4-11. Settings of Registers When Using Port 8 Name I/O P80 PIM8x POM8x 1 0 x x 1 1 x x Input Output P81 Input P82 P83 to P87 Notes 1. Alternate Function Setting PM8x 0 x 0 0 x 1 1 0 x x 1 1 x x x Output 0 0 x 1 Input 1 - x Output 0 0 0 1 Input 1 Output 0 - 0 - Note 2 Remark CMOS input TTL input (SCK10/SCL10 output = 1 Note 1 ) CMOS output N-ch O.D. output (SDA10 output = 1 CMOS input TTL input Note 1 ) CMOS output N-ch O.D. output x (TxD1/SO10 output = 1 Note 1 ) CMOS output N-ch O.D. output x x To use P80 to P82 as a general-purpose port when PIOR5 = 1, set bit 2 (SE02) of serial channel enable status register 0 (SE0), bit 2 (SO02) of serial output register 0 (SO0) and bit 2 (SOE02) of serial output enable register 0 (SOE0) to the default status. 2. Remark The descriptions in parentheses indicate the case where PIORx = 1. x: don't care PM8x: Port mode register 8 PIM8x: Port input mode register 8 POM8x: Port output mode register 8 PIORx: Peripheral I/O redirection register R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 208 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-38 to 4-41 show block diagrams of port 8 for 128-pin products . <R> Figure 4-38. Block Diagram of P80 and P81 WRPIM PIM8 PIM80, PIM81 EVDD WRPU PU8 PU80, PU81 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P8 Output latch (P80, P81) WRPOM POM8 P80/(SCK10)/(SCL10), P81/(SI10)/(RxD1)/ (SDA10) POM80, POM81 WRPM PM8 PM80, PM81 Alternate function P8: Port register 8 PU8: Pull-up resistor option register 8 PM8: Port mode register 8 PIM8: Port input mode register 8 POM8: Port output mode register 8 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 209 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-39. Block Diagram of P82 <R> EVDD WRPU PU8 PU82 P-ch Internal bus Selector RD WRPORT P8 Output latch (P82) WRPOM P82/(SO10)/ (TxD1) POM8 POM82 WRPM PM8 PM82 Alternate function P8: Port register 8 PU8: Pull-up resistor option register 8 PM8: Port mode register 8 PIM8: Port input mode register 8 POM8: Port output mode register 8 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 210 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-40. Block Diagram of P83 EVDD WRPU PU8 PU83 P-ch Selector Internal bus RD WRPORT P8 Output latch (P83) P83 WRPM PM8 PM83 P8: Port register 8 PU8: Pull-up resistor option register 8 PM8: Port mode register 8 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 211 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-41. Block Diagram of P84 to P87 <R> EVDD WRPU PU8 PU84 to PU87 P-ch Alternate function Selector Internal bus RD WRPORT P8 Output latch (P84 to P87) P84/(INTP6) to P87/(INTP9) WRPM PM8 PM84 to PM87 P8: Port register 8 PU8: Pull-up resistor option register 8 PM8: Port mode register 8 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 212 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 9 Port 9 is an I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 9 (PU9). Output from the P96 pin can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units using port output mode register 9 (POM9). This port can also be used for serial interface data I/O, clock I/O. Reset signal generation sets port 9 to input mode. Table 4-12. Settings of Registers When Using Port 9 Name I/O PM9x POM9x Alternate Function Setting - - P90 to Input 1 P94 Output 0 P95 P96 P97 Note Remark - - Input 1 Output 0 Input 1 x Output 0 0 0 1 Input 1 - Output 0 x SCK11/SCL11 output = 1 Note x SDA11 output = 1 Note CMOS output N-ch O.D. output x SO11 output = 1 Note P95/SCK11/SCL11, P96/SI11/SDA11 or P97/SO11 as a general-purpose port, set bit 3 (SE03) of serial channel enable status register 0 (SE0), bit 3 (SO03) of serial output register 0 (SO0) and bit 3 (SOE03) of serial output enable register 0 (SOE0) to the default status. Remark x: don't care PM9x: Port mode register 9 POM9x: Port output mode register 9 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 213 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-42 to 4-45 show block diagrams of port 9. Figure 4-42. Block Diagram of P90 to P94 EVDD WRPU PU9 PU90 to PU94 P-ch Selector Internal bus RD WRPORT P9 Output latch (P90 to P94) P90 to P94 WRPM PM9 PM90 to PM94 P9: Port register 9 PU9: Pull-up resistor option register 9 PM9: Port mode register 9 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 214 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-43. Block Diagram of P95 EVDD WRPU PU9 PU95 P-ch Alternate function Internal bus Selector RD WRPORT P9 Output latch (P95) P95/SCK11/SCL11 WRPM PM9 PM95 Alternate function P9: Port register 9 PU9: Pull-up resistor option register 9 PM9: Port mode register 9 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 215 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-44. Block Diagram of P96 EVDD WRPU PU9 PU96 P-ch Alternate function Internal bus Selector RD WRPORT P9 Output latch (P96) P96/SI11/SDA11 WRPOM POM9 POM96 WRPM PM9 PM96 Alternate function P9: Port register 9 PU9: Pull-up resistor option register 9 PM9: Port mode register 9 POM9: Port output mode register 9 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 216 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-45. Block Diagram of P97 EVDD WRPU PU9 PU97 P-ch Selector Internal bus RD WRPORT P9 Output latch (P97) P97/SO11 WRPM PM9 PM97 Alternate function P9: Port register 9 PU9: Pull-up resistor option register 9 PM9: Port mode register 9 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 217 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 10 Port 10 is an I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (PM10). When the P100 to P106 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 10 (PU10). Input to the P100 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 10 (PMC10). This port can also be used for timer I/O and A/D converter analog input. Reset signal generation sets P100 to analog input, P101 to P106 to input mode. Table 4-13. Settings of Registers When Using Port 10 Name I/O PM10x PMC10x Alternate Function Setting Input 1 0 x Output 0 0 x Input 1 - - Output 0 Input 1 - x Output 0 P103 to Input 1 P106 Output 0 P100 P101 P102 Notes 1. TO06 output = 0 - Remark Note 1 x TO14 to TO17 outputs = 0 Note 2 To use P102/TI06/TO06 as a general-purpose port, set bit 6 (TO06) of timer output register 0 (TO0) and bit 6 (TOE06) of timer output enable register 0 (TOE0) to "0", which is the same as their default status setting. 2. To use P103/TI14/TO14 to P106/TI17/TO17 as a general-purpose port, set bits 4 to 7 (TO14 to TO17) of timer output register 1 (TO1) and bits 4 to 7 (TOE14 to TOE17) of timer output enable register 1 (TOE1) to "0", which is the same as their default status setting. Remark x: don't care PM10x: Port mode register 10 PMC10x: Port mode control register 10 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 218 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-46 to 4-48 show block diagrams of port 10. Figure 4-46. Block Diagram of P100 EVDD WRPU PU10 PU100 P-ch WRPMC PMC10 PMC100 Selector Internal bus RD WRPORT P10 Output latch (P100) P100/ANI20 WRPM PM10 PM100 A/D converter P10: Port register 10 PU10: Pull-up resistor option register 10 PM10: Port mode register 10 PMC10: Port mode controlregister 10 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 219 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-47. Block Diagram of P101 EVDD WRPU PU10 PU101 P-ch Selector Internal bus RD WRPORT P10 Output latch (P101) P101 WRPM PM10 PM101 P10: Port register 10 PU10: Pull-up resistor option register 10 PM10: Port mode register 10 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 220 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-48. Block Diagram of P102 to P106 EVDD WRPU PU10 PU102 to PU106 P-ch Alternate function Selector Internal bus RD WRPORT P10 Output latch (P102 to P106) WRPM P102/TI06/TO06, P103/TI14/TO14 to P106/TI17/TO17 PM10 PM102 to PM106 Alternate function P10: Port register 10 PU10: Pull-up resistor option register 10 PM10: Port mode register 10 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 221 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.12 Port 11 Port 11 is an I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (PM11). When the P110 to P117 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 11 (PU11). Input to the P115 to P117 pins can be specified as analog input or digital input in 1-bit units, using port mode control register 11 (PMC11). This port can also be used for A/D converter analog input as alternate function. Reset signal generation sets P110 to P114 to input mode, and sets P115 to P117 to analog input. Table 4-14. Settings of Registers When Using Port 11 Pin Name Name Alternate Function Setting PM11x PMC11x - x - - Remark I/O P110, Input 1 P111 Output 0 P112 to Input 1 P114 Output 0 P115 to Input 1 0 x P117 Output 0 0 x Remark Note 3 x: don't care PM11x: Port mode register 11 PMC11x: Port mode control register 11 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 222 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, 4-49 to 4-51 show block diagrams of port 11 for 128-pin products . <R> Figure 4-49. Block Diagram of P110 and P111 EVDD WRPU PU11 PU110, PU111 P-ch Alternate function Selector Internal bus RD WRPORT P11 Output latch (P110 , P111) P110/(INTP10), P111/(INTP11) WRPM PM11 PM110, PM111 P11: Port register 11 PU11: Pull-up resistor option register 11 PM11: Port mode register 11 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 223 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-50. Block Diagram of P112 to P114 <R> EVDD WRPU PU11 PU112 to PU114 P-ch Selector Internal bus RD WRPORT P11 Output latch (P112 to P114) P112 to P114 WRPM PM11 PM112 to PM114 P11: Port register 11 PU11: Pull-up resistor option register 11 PM11: Port mode register 11 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 224 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-51. Block Diagram of P115 to P117 EVDD WRPU PU11 PU115 to PU117 P-ch WRPMC Internal bus PMC11 PMC115 to PMC117 Selector RD WRPORT P11 Output latch (P115 to P117) P115/ANI26 to P117/ANI24 WRPM PM11 PM115 to PM117 A/D converter P11: Port register 11 PU11: Pull-up resistor option register 11 PM11: Port mode register 11 PMC11: Port mode controlregister 11 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 225 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.13 Port 12 P120 and P125 to 127 are an I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). P121 to P124 are 4-bit input only ports. Input to the P120 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 12 (PMC12). This port can also be used for A/D converter analog input, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock. Reset signal generation sets P120 to analog input, and sets P121 to P127 to input mode. Table 4-15. Settings of Registers When Using Port 12 Name I/O PM12x PMC12x Alternate Function Setting Input 1 0 x Output 0 0 x P121 Input - - OSCSEL bit of CMC register = 0 P122 Input - - OSCSEL bit of CMC register = 0 P123 Input - - OSCSELS bit of CMC register = 0 P120 Remark or EXCLK bit = 1 or EXCLKS bit = 1 P124 Input - - OSCSELS bit of CMC register = 0 P125 to Input 1 - - P127 Output 0 Caution The function setting on P121 to P124 is available only once after the reset release. The port once set for connection to an X1, XT1 oscillator, external clock input cannot be used as an input port unless the reset is performed. Remark x: don't care PM12x: Port mode register 12 PMC12x: Port mode control register 12 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 226 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-52 to 4-55 show block diagrams of port 12 for 128-pin products . Figure 4-52. Block Diagram of P120 EVDD WRPU PU12 PU120 P-ch WRPMC Internal bus PMC12 PMC120 Selector RD WRPORT P12 Output latch (P120) P120/ANI19 WRPM PM12 PM120 A/D converter P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 PMC12: Port mode control register 12 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 227 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-53. Block Diagram of P121 and P122 Clock generator CMC OSCSEL RD Internal bus P122/X2/EXCLK CMC EXCLK, OSCSEL RD P121/X1 CMC: Clock operation mode control register RD: Read signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 228 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-54. Block Diagram of P123 and P124 Clock generator CMC OSCSELS RD Internal bus P124/XT2/EXCLKS CMC EXCLKS, OSCSELS RD P123/XT1 CMC: Clock operation mode control register RD: Read signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 229 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-55. Block Diagram of P125 to P127 EVDD WRPU PU12 PU125 to PU127 P-ch Selector Internal bus RD WRPORT P12 Output latch (P125 to P127) P125 to P127 WRPM PM12 PM125 to PM127 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 230 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.14 Port 13 P130 is a 1-bit output-only port with an output latch. P137 is a 1-bit input-only port. P130 is fixed an output port, and P137 is fixed an input ports. This port can also be used for external interrupt request input. Table 4-16. Settings of Registers When Using Port 13 Name I/O Alternate Function Setting P130 Output - P137 Input x Remark Remark x: don't care Figures 4-56 and 4-57 show block diagrams of port 13. Figure 4-56. Block Diagram of P130 Internal bus RD WRPORT P13 Output latch (P130) P13: Port register 13 RD: Read signal P130 WRxx: Write signal Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is effected, the output signal of P130 can be dummy-output as the CPU reset signal. Reset signal P130 Set by software R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 231 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-57. Block Diagram of P137 Internal bus <R> P137/INTP0 Alternate function R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 232 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.15 Port 14 Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P147 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). Input to the P142 and P143 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 14 (PIM14). Output from the P142 to P144 pins can be specified as N-ch open-drain output (EVDD tolerance) in 1-bit units using port output mode register 14 (POM14). Input to the P147 pin can be specified as analog input or digital input in 1-bit units, using port mode control register 14 (PMC14). This port can also be used for clock/buzzer output, external interrupt request input, and A/D converter analog input. Reset signal generation sets P140 to P146 to input mode, and sets P147 to analog input. Table 4-17. Settings of Registers When Using Port 14 Name I/O PM14x PIM14x POM14x PMC14x Alternate Function Setting - - - x Remark P140, Input 1 P141 Output 0 P142, Input 1 1 1 x x TTL input Output 0 x 0 SCK30/SCL30 output = 1, CMOS output 0 x 1 Input 1 - x Output 0 0 0 1 P143 P144 P145 P146 P147 Input 1 Output 0 Input 1 Output 0 Input 1 Output 0 PCLBUZ0 output, Note 1 PCLBUZ1 output = 0 0 - x - - x SDA30 output = 1 - - Note 2 N-ch O.D. output x SO30/TxD3 output = 1 Note 2 CMOS output N-ch O.D. output - x TO07 output = 0 - CMOS input - Note 3 x x - - 0 x 0 x Notes 1. To use P140/PCLBUZ0/INTP6 or P141/PCLBUZ1/INTP7 as a general-purpose port, set bit 7 of clock 2. To use P142/SCK30/SCL30, P143/SI30/RxD3/SDA30, or P144/SO30/TxD3 as a general-purpose port, set output select registers 0 and 1 (CKS0, CKS1) to "0", which is the same as their default status settings. bits 2 and 3 (SE12, SE13) of serial channel enable status register 1 (SE1), bits 2 and 3 (SO12, SO13) of serial output register 1 (SO1) and bits 2 and 3 (SOE12, SOE13) of serial output enable register 1 (SOE1) to the default status. 3. To use P145/TI07/TO07 as a general-purpose port, set bit 7 (TO07) of timer output register 0 (TO0) and bit 7 (TOE07) of timer output enable register 0 (TOE0) to "0", which is the same as their default status setting. Remark x: don't care PM14x: Port mode register 14 PIM14x: Port input mode register 14 POM14x: Port output mode register 14 PMC14x: Port mode control register 14 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 233 RL78/G13 CHAPTER 4 PORT FUNCTIONS For example, figures 4-58 to 4-63 show block diagrams of port 14 for 128-pin products . Figure 4-58. Block Diagram of P140 and P141 EVDD WRPU PU14 PU140, PU141 P-ch Alternate function Selector Internal bus RD WRPORT P14 Output latch (P140, P141) P140/PCLBUZ0/INTP6, P141/PCLBUZ1/INTP7 WRPM PM14 PM140, PM141 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 234 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-59. Block Diagram of P142 and P143 <R> WRPIM PIM14 PIM142, PIM143 EVDD WRPU PU14 PU142, PU143 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P14 Output latch (P142, P143) P142/SCK30/SCL30, P143/SI30/RxD3/SDA30 WRPOM POM14 POM142, POM143 WRPM PM14 PM142, PM143 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 PIM14: Port input mode register 14 POM14: Port output mode register 14 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 235 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> Figure 4-60. Block Diagram of P144 EVDD WRPU PU14 PU144 P-ch Internal bus Selector RD WRPORT P14 Output latch (P144) P144/SO30/TxD3 WRPOM POM14 POM144 WRPM PM14 PM144 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 POM14: Port output mode register 14 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 236 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-61. Block Diagram of P145 EVDD WRPU PU14 PU145 P-ch Alternate function Selector Internal bus RD WRPORT P14 Output latch (P145) P145/TI07/TO07 WRPM PM14 PM145 Alternate function P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 237 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-62. Block Diagram of P146 <R> EVDD WRPU PU14 PU146 P-ch Alternate function Selector Internal bus RD WRPORT P14 Output latch (P146) P146/(INTP4) WRPM PM14 PM146 P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 RD: Read signal WRxx: Write signal <R> Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). Refer to Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 238 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-63. Block Diagram of P147 EVDD WRPU PU14 PU147 P-ch WRPMC PMC14 PMC147 Selector Internal bus RD WRPORT P14 Output latch (P147) P147/ANI18 WRPM PM14 PM147 A/D converter P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 PMC14: Port mode control register 14 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 239 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.2.16 Port 15 Port 15 is an I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (PM15). This port can also be used for A/D converter analog input. To use P150/ANI8 to P156/ANI4 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the upper bit. To use 150/ANI8 to P156/ANI4 as digital output pins, set them in the digital I/O mode by using the ADPC register and <R> in the output mode by using the PM15 register. Use these pins starting from the upper bit. To use 150/ANI8 to P156/ANI4 as analog input pins, set them in the analog input mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM15 register. Use these pins starting from the lower bit. Table 4-18. Settings of Registers When Using Port 15 Pin Name Name PM15x Input Output 2. Alternate Function Setting Remark - To use P15n as a port, use these I/O P15n Remarks 1. ADPC 1 01H to 0 n+9H pins from a higher bit. x: don't care PM15x: Port mode register 15 ADPC: A/D port configuration register n = 0 to 6 Table 4-19. Setting Functions of P150/ANI8 to P156/ANI14 Pins ADPC Register Digital I/O selection Analog input selection PM15 Register ADS Register P150/ANI8 to P156/ANI14 Pins Input mode - Digital input Output mode - Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. All P150/ANI8 to P156/ANI14 are set in the analog input mode when the reset signal is generated. Figure 4-64 shows a block diagram of port 15. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 240 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-64. Block Diagram of P150 to P156 WRADPC ADPC 0:Analog input 1:Digital I/O ADPC3 to ADPC0 Selector Internal bus RD WRPORT P15 Output latch (P150 to P156) P150/ANI8 to P156/ANI14 WRPM PM15 PM150 to PM156 A/D converter ADPC: A/D port cofiguration register P15: Port register 15 PM15: Port mode register 15 RD: Read signal WRxx: Write signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 241 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers. * * * * * * * * * <R> Port mode registers (PMxx) Port registers (Pxx) Pull-up resistor option registers (PUxx) Port input mode registers (PIMxx) Port output mode registers (POMxx) Port mode control registers (PMCxx) A/D port configuration register (ADPC) Peripheral I/O redirection register (PIOR) Global digital input disable register (GDIDIS) Caution The undefined bits in each register vary by product and must be used with their initial value. Table 4-20. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (20-pin products to 64-pin products) (1/3) Port Port 0 Port 1 Port 2 64 52 48 44 40 36 32 30 25 24 20 pin pin pin pin pin pin pin pin pin pin pin Note Note Bit name 0 PMxx Pxx PUxx PIMxx POMxx PMCxx register register register register register register PM00 P00 PU00 - POM00 PMC00 1 PM01 P01 PU01 PIM01 - 2 PM02 P02 PU02 - POM02 PMC02 - - - - - - - - - 3 PM03 P03 PU03 PIM03 POM03 PMC03 - - - - - - - - - 4 PM04 P04 PU04 PIM04 POM04 - - - - - - - - - - - 5 PM05 P05 PU05 - - - - - - - - - - - - - 6 PM06 P06 PU06 - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - - - 0 PM10 P10 PU10 PIM10 POM10 - 1 PM11 P11 PU11 PIM11 POM11 - 2 PM12 P12 PU12 - POM12 - 3 PM13 P13 PU13 PIM13 POM13 - - - - 4 PM14 P14 PU14 PIM14 POM14 - - - - 5 PM15 P15 PU15 PIM15 POM15 - - - - PMC01 6 PM16 P16 PU16 PIM16 - - 7 PM17 P17 PU17 PIM17 POM17 - 0 PM20 P20 - - - - 1 PM21 P21 - - - - 2 PM22 P22 - - - - 3 PM23 P23 - - - - - - - 4 PM24 P24 - - - - - - - - - 5 PM25 P25 - - - - - - - - - 6 PM26 P26 - - - - - - - - - - 7 PM27 P27 - - - - - - - - - - - Note 20-pin, 24-pin, 25-pin, 30-pin, and 32-pin products only. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 242 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-20. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (20-pin products to 64-pin products) (2/3) Port Bit name PMxx register Port 3 Port 4 Port 5 Port 6 Port 7 Pxx register PUxx register PIMxx register POMxx register PMCxx register 64 pin 52 pin 48 pin 44 pin 40 pin 36 pin 32 pin 30 pin 25 pin 24 pin 20 pin 0 PM30 P30 PU30 - - - 1 PM31 P31 PU31 - - - - 2 - - - - - - - - - - - - - - - - - 3 - - - - - - - - - - - - - - - - - 4 - - - - - - - - - - - - - - - - - 5 - - - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - - - 0 PM40 P40 PU40 - - - 1 PM41 P41 PU41 - - - - - - - - - - 2 PM42 P42 PU42 - - - - - - - - - - - - - 3 PM43 P43 PU43 - - - - - - - - - - - - - - 4 - - - - - - - - - - - - - - - - - 5 - - - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - - - 0 PM50 P50 PU50 - POM50 - - 1 PM51 P51 PU51 - - - - - - - 2 PM52 P52 PU52 - - - - - - - - - - - - - 3 PM53 P53 PU53 - - - - - - - - - - - - - 4 PM54 P54 PU54 - - - - - - - - - - - - - 5 PM55 P55 PU55 PIM55 POM55 - - - - - - - - - - - 6 - - - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - - - 0 PM60 P60 - - - - - 1 PM61 P61 - - - - - 2 PM62 P62 - - - - - - - - 3 PM63 P63 - - - - - - - - - - - 4 - - - - - - - - - - - - - - - - - 5 - - - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - - - 0 PM70 P70 PU70 - - - - - - - 1 PM71 P71 PU71 - POM71 - - - - - - 2 PM72 P72 PU72 - - - - - - - - 3 PM73 P73 PU73 - - - - - - - - - 4 PM74 P74 PU74 - POM74 - - - - - - - - - 5 PM75 P75 PU75 - - - - - - - - - - - 6 PM76 P76 PU76 - - - - - - - - - - - - 7 PM77 P77 PU77 - - - - - - - - - - - - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 243 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-20. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (20-pin products to 64-pin products) (3/3) Port Bit name PMxx Pxx PUxx PIMxx POMxx PMCxx register register register register register register 64 52 48 44 40 36 32 30 25 24 20 pin pin pin pin pin pin pin pin pin pin pin Port 8 - - - - - - - - - - - - - - - - - - Port 9 - - - - - - - - - - - - - - - - - - Port 10 - - - - - - - - - - - - - - - - - - Port 11 - - - - - - - - - - - - - - - - - - Port 12 0 PM120 P120 PU120 - - PMC120 - - - 1 - P121 - - - - 2 - P122 - - - - 3 - P123 - - - - - - - - - - 4 - P124 - - - - - - - - - - 5 - - - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - - - 7 - - - - - - - - - - - - - - - - - 0 - P130 - - - - - - - - - - - 1 - - - - - - - - - - - - - - - - - 2 - - - - - - - - - - - - - - - - - 3 - - - - - - - - - - - - - - - - - 4 - - - - - - - - - - - - - - - - - 5 - - - - - - - - - - - - - - - - - 6 - - - - - - - - - - - - - - - - - 7 - P137 - - - - 0 PM140 P140 PU140 - - - - - - - - - - - 1 PM141 P141 PU141 - - - - - - - - - - - - - 2 - - - - - - - - - - - - - - - - - 3 - - - - - - - - - - - - - - - - - 4 - - - - - - - - - - - - - - - - - 5 - - - - - - - - - - - - - - - - - 6 PM146 P146 PU146 - - - - - - - - - - 7 PM147 P147 PU147 - - PMC147 - - - - - - - - - - - - - - - - - - Port 13 Port 14 Port 15 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 244 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (1/4) Port Port 0 Port 1 Port 2 Port 3 Bit name 128 100 80 pin pin pin PMxx Pxx PUxx PIMxx POMxx PMCxx register register register register register register 0 PM00 P00 PU00 - POM00 - 1 PM01 P01 PU01 PIM01 - - 2 PM02 P02 PU02 - POM02 PMC02 3 PM03 P03 PU03 PIM03 POM03 PMC03 4 PM04 P04 PU04 PIM04 POM04 - 5 PM05 P05 PU05 - - - 6 PM06 P06 PU06 - - - 7 PM07 P07 PU07 - - - - - 0 PM10 P10 PU10 PIM10 POM10 - 1 PM11 P11 PU11 PIM11 POM11 - 2 PM12 P12 PU12 - POM12 - 3 PM13 P13 PU13 PIM13 POM13 - 4 PM14 P14 PU14 PIM14 POM14 - 5 PM15 P15 PU15 PIM15 POM15 - 6 PM16 P16 PU16 PIM16 - - 7 PM17 P17 PU17 PIM17 POM17 - 0 PM20 P20 - - - - 1 PM21 P21 - - - - 2 PM22 P22 - - - - 3 PM23 P23 - - - - 4 PM24 P24 - - - - 5 PM25 P25 - - - - 6 PM26 P26 - - - - 7 PM27 P27 - - - - 0 PM30 P30 PU30 - - - 1 PM31 P31 PU31 - - - 2 PM32 P32 PU32 - - - - - 3 PM33 P33 PU33 - - - - - 4 PM34 P34 PU34 - - - - - 5 PM35 P35 PU35 - - PMC35 - - 6 PM36 P36 PU36 - - PMC36 - - 7 PM37 P37 PU37 - - PMC37 - - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 245 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (2/4) Port Port 4 Port 5 Port 6 Port 7 Port 8 Bit name 128 100 80 pin pin PMxx register Pxx register PUxx register PIMxx register POMxx register PMCxx register pin 0 PM40 P40 PU40 - - - 1 PM41 P41 PU41 - - - 2 PM42 P42 PU42 - - - 3 PM43 P43 PU43 PIM43 POM43 - 4 PM44 P44 PU44 PIM44 POM44 - 5 PM45 P45 PU45 - POM45 - 6 PM46 P46 PU46 - - - - 7 PM47 P47 PU47 - - - - 0 PM50 P50 PU50 - POM50 - 1 PM51 P51 PU51 - - - 2 PM52 P52 PU52 - POM52 - 3 PM53 P53 PU53 PIM53 POM53 - 4 PM54 P54 PU54 PIM54 POM54 - 5 PM55 P55 PU55 PIM55 POM55 - 6 PM56 P56 PU56 - - - - 7 PM57 P57 PU57 - - - - 0 PM60 P60 - - - - 1 PM61 P61 - - - - 2 PM62 P62 - - - - 3 PM63 P63 - - - - 4 PM64 P64 PU64 - - - 5 PM65 P65 PU65 - - - 6 PM66 P66 PU66 - - - 7 PM67 P67 PU67 - - - 0 PM70 P70 PU70 - - - 1 PM71 P71 PU71 - POM71 - 2 PM72 P72 PU72 - - - 3 PM73 P73 PU73 - - - 4 PM74 P74 PU74 - POM74 - 5 PM75 P75 PU75 - - - 6 PM76 P76 PU76 - - - 7 PM77 P77 PU77 - - - 0 PM80 P80 PU80 PIM80 POM80 - - 1 PM81 P81 PU81 PIM81 POM81 - - 2 PM82 P82 PU82 - POM82 - - 3 PM83 P83 PU83 - - - - 4 PM84 P84 PU84 - - - - 5 PM85 P85 PU85 - - - - 6 PM86 P86 PU86 - - - - 7 PM87 P87 PU87 - - - - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 246 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (3/4) Port Port 9 Port 10 Port 11 Port 12 Port 13 Bit name 128 100 80 pin pin pin PMxx Pxx PUxx PIMxx POMxx PMCxx register register register register register register 0 PM90 P90 PU90 - - - - - 1 PM91 P91 PU91 - - - - - 2 PM92 P92 PU92 - - - - - 3 PM93 P93 PU93 - - - - - 4 PM94 P94 PU94 - - - - - 5 PM95 P95 PU95 - - - - - 6 PM96 P96 PU96 - POM96 - - - 7 PM97 P97 PU97 - - - - - 0 PM100 P100 PU100 - - PMC100 1 PM101 P101 PU101 - - - - 2 PM102 P102 PU102 - - - - 3 PM103 P103 PU103 - - - - - 4 PM104 P104 PU104 - - - - - 5 PM105 P105 PU105 - - - - - 6 PM106 P106 PU106 - - - - - 7 - - - - - - - - - 0 PM110 P110 PU110 - - - 1 PM111 P111 PU111 - - - 2 PM112 P112 PU112 - - - - - 3 PM113 P113 PU113 - - - - - 4 PM114 P114 PU114 - - - - - 5 PM115 P115 PU115 - - PMC115 - - 6 PM116 P116 PU116 - - PMC116 - - 7 PM117 P117 PU117 - - PMC117 - - 0 PM120 P120 PU120 - - PMC120 1 - P121 - - - - 2 - P122 - - - - 3 - P123 - - - - 4 - P124 - - - - 5 PM125 P125 PU125 - - - - - 6 PM126 P126 PU126 - - - - - 7 PM127 P127 PU127 - - - - - 0 - P130 - - - - 1 - - - - - - - - - 2 - - - - - - - - - 3 - - - - - - - - - 4 - - - - - - - - - 5 - - - - - - - - - 6 - - - - - - - - - 7 - P137 - - - - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 247 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (4/4) Port Port 14 Port 15 Bit name 128 100 80 pin pin PMxx register Pxx register PUxx register PIMxx register POMxx register PMCxx register pin 0 PM140 P140 PU140 - - - 1 PM141 P141 PU141 - - - 2 PM142 P142 PU142 PIM142 POM142 - 3 PM143 P143 PU143 PIM143 POM143 - 4 PM144 P144 PU144 POM144 - 5 PM145 P145 PU145 - - - - 6 PM146 P146 PU146 - - - 7 PM147 P147 PU147 - - PMC147 0 PM150 P150 - - - - 1 PM151 P151 - - - - 2 PM152 P152 - - - - 3 PM153 P153 - - - - 4 PM154 P154 - - - - - 5 PM155 P155 - - - - - 6 PM156 P156 - - - - - 7 - - - - - - - - - The format of each register is described below. The description here uses the 128-pin products as an example. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 248 RL78/G13 CHAPTER 4 PORT FUNCTIONS For the registers mounted on others than 128-pin products, refer to table 4-20 and 4-21. (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 249 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-65. Format of Port Mode Register (128-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FFF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FFF22H FFH R/W PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FFF23H FFH R/W PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 FFF24H FFH R/W PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FFF25H FFH R/W PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 FFF26H FFH R/W PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 FFF27H FFH R/W PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 FFF28H FFH R/W PM9 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 FFF29H FFH R/W PM10 1 PM106 PM105 PM104 PM103 PM102 PM101 PM100 FFF2AH FFH R/W PM11 PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110 FFF2BH FFH R/W PM12 PM127 PM126 PM125 1 1 1 1 PM120 FFF2CH FFH R/W PM14 PM147 PM146 PM145 PM144 PM143 PM142 PM141 PM140 FFF2EH FFH R/W PM15 1 PM156 PM155 PM154 PM153 PM152 PM151 PM150 FFF2FH FFH R/W Pmn pin I/O mode selection PMmn (m = 0 to 12, 14, 15; n = 0 to 7) Caution 0 Output mode (output buffer on) 1 Input mode (output buffer off) Be sure to set bit 7 of the PM10 register, bits 1 to 4 of the PM12 register, and bit 7 of the PM15 register to "1". R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 250 RL78/G13 CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is readNote. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Note If P02, P03, P20 to P27, P35 to P37, P100, P115 to P117, P120, P147, and P150 to P156 are set up as analog inputs of the A/D converter, when a port is read while in the input mode, 0 is always returned, not the pin level. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 251 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-66. Format of Port Register (128-pin products) <R> Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 P07 P06 P05 P04 P03 P02 P01 P00 FFF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W P2 P27 P26 P25 P24 P23 P22 P21 P20 FFF02H 00H (output latch) R/W P3 P37 P36 P35 P34 P33 P32 P31 P30 FFF03H 00H (output latch) R/W P4 P47 P46 P45 P44 P43 P42 P41 P40 FFF04H 00H (output latch) R/W P5 P57 P56 P55 P54 P53 P52 P51 P50 FFF05H 00H (output latch) R/W P6 P67 P66 P65 P64 P63 P62 P61 P60 FFF06H 00H (output latch) R/W P7 P77 P76 P75 P74 P73 P72 P71 P70 FFF07H 00H (output latch) R/W P8 P87 P86 P85 P84 P83 P82 P81 P80 FFF08H 00H (output latch) R/W P9 P97 P96 P95 P94 P93 P92 P91 P90 FFF09H 00H (output latch) R/W P10 0 P106 P105 P104 P103 P102 P101 P100 FFF0AH 00H (output latch) R/W P11 P117 P116 P115 P114 P113 P112 P111 P110 FFF0BH 00H (output latch) R/W P12 P127 P126 P125 P124 P123 P122 P121 P120 FFF0CH Undefined R/W Note P13 P137 0 0 0 0 0 0 P130 FFF0DH Note 2 R/W Note P14 P147 P146 P145 P144 P143 P142 P141 P140 FFF0EH 00H (output latch) R/W P15 0 P156 P155 P154 P153 P152 P151 P150 FFF0FH 00H (output latch) R/W Pmn Output data control (in output mode) Notes 1. <R> 2. Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level P121 to P124, and P137 are read-only. P137 : Undefined P1301: 0 (output latch) Remark m = 0 to 15; n = 0 to 7 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 252 RL78/G13 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode (PMmn = 1 and POMmn = 0) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers. On-chip pull-up resistors cannot be connected to bits <R> set to output mode and bits used as alternate-function output pins and analog setting (PMC = 1, ADPC = 1), regardless of the settings of these registers. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H (Only PU4 is set to 01H). <R> Caution When a port with the PIMn register is input from different potential device to TTL buffer, pull up to the power supply of the different potential device via a external pull-up resistor by setting PUmn = 0. Figure 4-67. Format of Pull-up Resistor Option Register (128-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 PU07 PU06 PU05 PU04 PU03 PU02 PU01 PU00 F0030H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W PU3 PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30 F0033H 00H R/W PU4 PU47 PU46 PU45 PU44 PU43 PU42 PU41 PU40 F0034H 01H R/W PU5 PU57 PU56 PU55 PU54 PU53 PU52 PU51 PU50 F0035H 00H R/W PU6 PU67 PU66 PU65 PU64 0 0 0 0 F0036H 00H R/W PU7 PU77 PU76 PU75 PU74 PU73 PU72 PU71 PU70 F0037H 00H R/W PU8 PU87 PU86 PU85 PU84 PU83 PU82 PU81 PU80 F0038H 00H R/W PU9 PU97 PU96 PU95 PU94 PU93 PU92 PU91 PU90 F0039H 00H R/W PU10 0 PU106 PU105 PU104 PU103 PU102 PU101 PU100 F003AH 00H R/W PU11 PU117 PU116 PU115 PU114 PU113 PU112 PU111 PU110 F003BH 00H R/W PU12 PU127 PU126 PU125 0 0 0 0 PU120 F003CH 00H R/W PU14 PU147 PU146 PU145 PU144 PU143 PU142 PU141 PU140 F003EH 00H R/W Pmn pin on-chip pull-up resistor selection PUmn (m = 0, 1, 3 to 12, 14; n = 0 to 7) 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 253 RL78/G13 CHAPTER 4 PORT FUNCTIONS (4) Port input mode registers (PIMxx) These registers set the input buffer in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-68. Format of Port Input Mode Register (128-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIM0 0 0 0 PIM04 PIM03 0 PIM01 0 F0040H 00H R/W PIM1 PIM17 PIM16 PIM15 PIM14 PIM13 0 PIM11 PIM10 F0041H 00H R/W PIM4 0 0 0 PIM44 PIM43 0 0 0 F0044H 00H R/W PIM5 0 0 PIM55 PIM54 PIM53 0 0 0 F0045H 00H R/W PIM8 0 0 0 0 0 0 PIM81 PIM80 F0048H 00H R/W PIM14 0 0 0 0 PIM143 PM142 0 0 F004EH 00H R/W Pmn pin input buffer selection PIMmn (m = 0, 1, 4, 5, 8, 14; n = 0 to 7) 0 Normal input buffer 1 TTL input buffer R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 254 RL78/G13 CHAPTER 4 PORT FUNCTIONS (5) Port output mode registers (POMxx) These registers set the output mode in 1-bit units. N-ch open drain output (VDD tolerance Note 1 /EVDD tolerance Note 2 ) mode can be selected during serial communication with an external device of the different potential, and for the SDA00, SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, 2 and SDA31 pins during simplified I C communication with an external device of the same potential. <R> In addition, POMxx register is set with PUxx register, whether or not to use the on-chip pull-up resistor. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-69. Format of Port Input Mode Register (128-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM0 0 0 0 POM04 POM03 POM02 0 POM00 F0050H 00H R/W POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 F0051H 00H R/W POM4 0 0 POM45 POM44 POM43 0 0 0 F0054H 00H R/W POM5 0 0 POM55 POM54 POM53 POM52 0 POM50 F0055H 00H R/W POM7 0 0 0 POM74 0 0 POM71 0 F0057H 00H R/W POM8 0 0 0 0 0 POM82 POM81 POM80 F0058H 00H R/W POM9 0 POM96 0 0 0 0 0 0 F0059H 00H R/W POM14 0 0 0 0 0 F005EH 00H R/W POM144 POM143 POM142 Pmn pin output mode selection POMmn (m = 0, 1, 4, 5, 7 to 9, 14; n = 0 to 7) 0 <R> Normal output mode When input mode, enable to the PUmn bit 1 N-ch open-drain output (VDD tolerance Note 1 /EVDD tolerance Note 2 ) mode When input mode, disable to the PUmn bit <R> Notes 1. 2. When 20 to 52 pin products When 64 to 128 pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 255 RL78/G13 CHAPTER 4 PORT FUNCTIONS (6) Port mode control registers (PMCxx) These registers set the digital I/O/analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. Figure 4-70. Format of Port Mode Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMC0 1 1 1 1 PMC03 PMC02 PMC01 PMC00 F0060H FFH R/W Note 2 Note 2 Note 1 Note 1 1 1 1 1 1 F0063H FFH R/W 1 1 1 1 PMC100 F006AH FFH R/W PMC3 PMC37 PMC36 PMC35 Note 3 Note 3 Note 3 1 1 1 PMC10 Note 4 PMC11 PMC117 PMC116 PMC115 Note 3 Note 3 Note 3 1 1 1 PMC12 1 1 1 1 1 F006BH FFH R/W 1 1 1 1 PMC120 F006CH FFH R/W F006EH FFH R/W Note 5 PMC14 PMC147 1 1 1 1 1 1 1 Note 6 Pmn pin digital I/O/analog input selection PMCmn (m = 0, 3, 10 to 12, 14; n = 0 to 3, 5 to 7) Notes 1. 2. 0 Digital I/O (alternate function other than analog input) 1 Analog input 20-, 24-, 25, 30-, 32-pin products only 52-, 64-, 80-, 100, 128-pin products only 3. 128-pin products only 4. 80-, 100-, 128-pin products only 5. 30-, 32-, 36-, 40-, 44-, 48-, 52-, 64-, 80-, 100, 128-pin products only 6. All products <R> Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode registers 0, 3, 10 <R> 2. Do not set the pin set by the PMC register as digital I/O by the analog input channel to 12, 14 (PM0, PM3, PM10 to PM12, PM14). specification register (ADS). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 256 RL78/G13 CHAPTER 4 PORT FUNCTIONS (7) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7, and P150/ANI8 to P156/ANI14 pins to digital I/O of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 4-71. Format of A/D Port Configuration Register (ADPC) Address: F0076H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 ADPC3 ADPC2 ADPC1 ADPC0 <R> ADPC3 ADPC2 ADPC1 ADPC0 ANI14/P156 ANI13/P155 ANI12/P154 ANI11/P153 ANI10/P152 ANI9/P151 ANI8/P150 ANI7/P27 ANI6/P26 ANI5/P25 ANI4/P24 ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20 Analog input (A)/digital I/O (D) switching 0 0 0 0 A A A A A A A A A A A A A A A 0 0 0 1 D D D D D D D D D D D D D D D 0 0 1 0 D D D D D D D D D D D D D D A 0 0 1 1 D D D D D D D D D D D D D A A 0 1 0 0 D D D D D D D D D D D D A A A 0 1 0 1 D D D D D D D D D D D A A A A 0 1 1 0 D D D D D D D D D D A A A A A 0 1 1 1 D D D D D D D D D A A A A A A 1 0 0 0 D D D D D D D D A A A A A A A 1 0 0 1 D D D D D D D A A A A A A A A 1 0 1 0 D D D D D D A A A A A A A A A 1 0 1 1 D D D D D A A A A A A A A A A 1 1 0 0 D D D D A A A A A A A A A A A 1 1 0 1 D D D A A A A A A A A A A A A 1 1 1 0 D D A A A A A A A A A A A A A 1 1 1 1 D A A A A A A A A A A A A A A Cautions 1. Set the port to analog input by ADPC register to the input mode by using port mode registers 2,15 (PM2, PM15). 2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel specification register (ADS). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 257 RL78/G13 CHAPTER 4 PORT FUNCTIONS (8) Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. <R> Use the PIOR register to assign a port to the function to redirect and enable the function. In addition, can be changed the settings for redirection until its function enable operation. The PIOR register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 258 RL78/G13 CHAPTER 4 PORT FUNCTIONS Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR) Address: F0077H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIOR 0 0 PIOR5 PIOR4 PIOR3 PIOR2 PIOR1 PIOR0 Bit PIOR5 PIOR4 Function INTP1 128/100-pin 80-pin Setting value Setting value 0 1 P46 P56 INTP3 P30 P57 INTP4 P31 P146 INTP6 P140 P84 INTP7 P141 P85 INTP8 P74 P86 INTP9 P75 P87 TxD1 P02 P82 0 64-pin 1 52-pin 48-pin Setting value Setting value 0 1 0 1 44-pin 40/36/32/30-pin Setting value Setting value Setting value 0 1 0 1 0 1 This area cannot be used. Be set to 0 (default value). RxD1 P03 P81 SCL10 P04 P80 SDA10 P03 P81 SI10 P03 P81 SO10 P02 P82 SCK10 P04 P80 PCLBUZ1 P141 P55 P141 P55 P141 P55 INTP5 P16 P12 P16 P12 P16 P12 PIOR3 PCLBUZ0 P140 P31 P140 P31 P140 P31 P140 P31 P140 P31 PIOR2 SCLA0 P60 P14 P60 P14 P60 P14 P60 P14 P60 P14 P60 P14 P60 P14 SDAA0 P61 P13 P61 P13 P61 P13 P61 P13 P61 P13 P61 P13 P61 P13 INTP10 P76 P110 P76 P110 P76 P52 P76 - - - - - - - INTP11 P77 P111 P77 P111 P77 P53 P77 - - - - - - - TxD2 P13 P77 P13 P77 P13 P77 P13 P77 P13 - P13 - P13 - RxD2 P14 P76 P14 P76 P14 P76 P14 P76 P14 - P14 - P14 - SCL20 P15 - P15 - P15 - P15 - P15 - P15 - P15 - SDA20 P14 - P14 - P14 - P14 - P14 - P14 - P14 - SI20 P14 - P14 - P14 - P14 - P14 - P14 - P14 - SO20 P13 - P13 - P13 - P13 - P13 - P13 - P13 - SCK20 P15 - P15 - P15 - P15 - P15 - P15 - P15 - TxD0 P12 P17 P12 P17 P12 P17 P12 P17 P12 P17 P12 P17 P12 P17 RxD0 P11 P16 P11 P16 P11 P16 P11 P16 P11 P16 P11 P16 P11 P16 SCL00 P10 - P10 - P10 - P10 - P10 - P10 - P10 - SDA00 P11 - P11 - P11 - P11 - P11 - P11 - P11 - SI00 P11 P16 P11 P16 P11 P16 P11 - P11 - P11 - P11 - SO00 P12 P17 P12 P17 P12 P17 P12 - P12 - P12 - P12 - SCK00 P10 P55 P10 P55 P10 P55 P10 - P10 - P10 - P10 - TI02/TO02 P17 P15 P17 P15 P17 P15 P17 P15 P17 P15 P17 P15 P17 P15 TI03/TO03 P31 P14 P31 P14 P31 P14 P31 P14 P31 P14 P31 P14 P31 P14 TI04/TO04 P42 P13 P42 P13 P42 P13 - P13 - P13 - P13 - P13 TI05/TO05 P46 P12 P05 P12 P05 P12 - P12 - P12 - P12 - P12 TI06/TO06 P102 P11 P06 P11 P06 P11 - P11 - P11 - P11 - P11 TI07/TO07 P145 P10 P41 P10 P41 P10 P41 P10 P41 P10 P41 P10 - P10 PIOR1 PIOR0 Cautions 1. If bit 1 (PIOR1) of the PIOR register is set to 1, the TxD2 and RxD2 pins are redirected, but SCL20, SDA20, SI20, SO20, SCK20 pins are not redirected. Therefore, IIC20 and CSI20 cannot be used in its setting. However, even if the bit is set to 1, CSI21/IIC21 can be used by P70 to P72 if UART2 is not used. 2. For 20- to 25-pin products, PIOR register is not mounted. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 259 RL78/G13 CHAPTER 4 PORT FUNCTIONS (9) Global digital input disable register (GDIDIS) This register is used to prevent through-current flowing from the input buffers when EVDD is 0 V. By setting the GDIDIS0 bit to 1, input to any input buffer connected to EVDD is prohibited, preventing through-current from flowing when the power supply connected to EVDD is turned off. When using the GDIDIS register, be sure to set the GDIDIS0 bit to 1 before turning off the EVDD power supply, and then clear the GDIDIS0 bit to 0 after turning on the EVDD power supply. The GDIDIS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. <R> Remark GDIDIS register is equipped with 64-, 80-, 100-, 128-pin products. Figure 4-73. Format of Global Digital Input Disable Register (GDIDIS) Address: F007DH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 GDIDIS 0 0 0 0 0 0 0 GDIDIS0 GDIDIS0 Setting of input buffers when EVDD is 0 V 0 Input to input buffers permitted (default) 1 Input to input buffers prohibited. No through-current flows to the input buffers. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 260 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not <R> change. Therefore, byte data can be written to the ports used for both input and output. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output <R> latch, but since the output buffer is off, the pin status does not change. Therefore, byte data can be written to the ports used for both input and output. The data of the output latch is cleared when a reset signal is generated. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 261 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) It is possible to connect to an external device with a different potential (1.8 V, 2.5 V or 3 V) by changing EVDD to accord with the power supply of the connected device. In products in which EVDD cannot be specified independently, I/O connection with an external device operating on 1.8 V, 2.5 V or 3 V is still possible via the serial interface and generalpurpose port by using ports 0, 1, 4, 5, 8, and 14. External Device EVDD No EVDD 3V 4.0 V EVDD VDD 5.5 V 4.0 V VDD 5.5 V 2.5 V 3.3 V EVDD < 4.0 V, 3.3 V VDD 5.5 V, EVDD VDD 3.3 V VDD 4.0 V 1.8 V 1.8 V EVDD < 3.3 V, 1.8 V VDD 5.5 V, EVDD VDD 1.8 V VDD 3.3 V Regarding inputs, Normal (CMOS)/TTL input buffer switching is possible on a bit-by-bit basis by the port input mode registers (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14). Moreover, regarding outputs, different potentials can be supported by switching the output buffer to the N-ch open drain Note 1 (VDD tolerance /EVDD tolerance Note 2 ) by the port output mode registers (POM0, POM1, POM4, POM5, POM8, POM14). Following, describes the connection of a serial interface. Notes 1. 2. When 20 to 52 pin products When 64 to 128 pin products (1) Setting procedure when using I/O pins of UART0 to UART3, CSI00, CSI01, CSI10, CSI20, CSI30, and CSI31 functions (a) Use as 1.8 V, 2.5 V, 3 V input port <1> If pull-up is needed, externally pull up the pin to be used up to the power supply of the target device (onchip pull-up resistor cannot be used). <R> Remark In case of UART0: P11 In case of UART1: P03 (P81) In case of UART2: P14 In case of UART3: P143 In case of CSI00: P10, P11 In case of CSI01: P43, P44 In case of CSI10: P03, P04 (P80, P81) In case of CSI20: P14, P15 In case of CSI30: P142, P143 In case of CSI31: P53, P54 Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). <2> After reset release, the port mode is the input mode (Hi-Z). <3> Set the corresponding bit of the PIM0, PIM1, PIM4, PIM5, PIM8, and PIM14 registers to 1 to switch to the TTL input buffer. <4> VIH/VIL operates on 1.8 V, 2.5 V, 3 V operating voltage. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 262 RL78/G13 CHAPTER 4 PORT FUNCTIONS (b) Use as 1.8 V, 2.5 V, 3 V output port <1> Pull up externally the pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used). In case of UART0: <R> Remark P12 In case of UART1: P02 (P82) In case of UART2: P13 In case of UART3: P144 In case of CSI00: P10, P12 In case of CSI01: P43, P45 In case of CSI10: P02, P04 (P80, P82) In case of CSI20: P13, P15 In case of CSI30: P142, P144 In case of CSI31: P52, P54 Functions in parentheses can be assigned via settings in the peripheral I/O redirection register (PIOR). <2> After reset release, the port mode changes to the input mode (Hi-Z). <3> Set the output latch of the corresponding port to 1. <4> Set the corresponding bit of the POM0, POM1, POM4, POM5, POM8, and POM14 registers to 1 to set the N-ch open drain output (VDD tolerance Note 1 /EVDD tolerance Note 2 ) mode. <5> Set the output mode by manipulating the PM0, PM1, PM4, PM5, PM8, and PM14 registers. At this time, the output data is high level, so the pin is in the Hi-Z state. <6> Can be communication by setting the serial array unit. Notes 1. When 20 to 52 pin products 2. When 64 to 128 pin products (2) Setting procedure when using I/O pins of IIC00, IIC01, IIC10, IIC20, IIC30, and IIC31 functions <1> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used). In case of IIC00: P10, P11 In case of IIC01: P43, P44 In case of IIC10: P03, P04 In case of IIC20: P14, P15 In case of IIC30: P142, P143 In case of IIC31: P53, P54 <2> After reset release, the port mode is the input mode (Hi-Z). <3> Set the output latch of the corresponding port to 1. <4> Set the corresponding bit of the POM0, POM1, POM4, POM5, and POM14 registers to 1 to set the N-ch open drain output (VDD tolerance <R> Note 1 /EVDD tolerance Note 2 ) mode. <5> Set the corresponding bit of the PIM0, PIM1, PIM4, PIM5, and PIM14 registers to 1 to switch the TTL input buffer. <6> Set the corresponding bit of the PM0, PM1, PM4, PM5, and PM14 registers to the output mode (data I/O is possible in the output mode). At this time, the output data is high level, so the pin is in the Hi-Z state. 2 <7> Enable the operation of the serial array unit and set the mode to the simplified I C mode. Notes 1. When 20 to 52 pin products 2. When 64 to 128 pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 263 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Related Register When Using Alternate Function To use the alternate function of a port pin, set the port mode register, and output latch as shown in Table 4-22. <R> Caution If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the unused alternate function must be set to its initial state. See 4.6.2 for details about the applicable units and how to handle such pins. Table 4-22. Settings of Port Related Register When Using Alternate Function (1/5) Pin Name Alternate Function PIORx POMxx PMCxx PMxx Pxx Input x x - 1 x Function Name P00 TI00 P01 TO00 P02 ANI17 Note 1 SO10 TxD1 P03 <R> P11 <R> Remarks 1. 2. 3. x - - 0 0 x x 1 1 x Output 0 0/1 0 0 1 Output 0 0/1 0 0 1 Input x x 1 1 x Input 0 x 0 1 x RxD1 Input 0 x 0 1 x SDA10 I/O 0 1 0 0 1 Note 1 Input 0 x - 1 x Output 0 0/1 - 0 1 SCL10 Output 0 0/1 - 0 1 SCK00 Input 0 x - 1 x Output 0 0/1 - 0 1 SCL00 Output 0 0/1 - 0 1 (TI07) Input 1 x - 1 x (TO07) Output 1 0 - 0 0 SI00 Input 0 x - 1 x RxD0 Input 0 x - 1 x TOOLRxD Input x x - 1 x SDA00 I/O 0 1 - 0 1 (TI06) Input 1 x - 1 x (TO06) Output 1 0 - 0 0 SCK10 P10 Output Input SI10 ANI16 P04 I/O x: don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMCxx: Port mode control register PMxx: Port mode register Pxx: Port output latch The relationship between pins and their alternate functions shown in this table indicates the relationship when a 128-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIORx, POMxx, PMCxx, PMxx, and Pxx set in the same way. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The Note 1 is described after the last table.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 264 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-22. Settings of Port Related Register When Using Alternate Function (2/5) Pin Name Alternate Function Function Name P12 SO00 <R> P13 <R> P14 <R> P15 Note 3 P16 P17 Note 3 Note 3 <R> Remarks 1. POMxx PMCxx PMxx Pxx 0 0/1 - 0 1 I/O Output TxD0 Output 0 0/1 - 0 1 TOOLTxD Output x 0/1 - 0 1 (INTP5) Input 1 x - 1 x (TI05) Input 1 x - 1 x (TO05) Output 1 0 - 0 0 TxD2 Output 0 0/1 - 0 1 SO20 Output 0 0/1 - 0 1 (SDAA0) I/O 1 1 - 0 0 (TI04) Input 1 x - 1 x (TO04) Output 1 0 - 0 0 RxD2 Input 0 x - 1 x SI20 Input 0 x - 1 x SDA20 I/O 0 1 - 0 1 (SCLA0) I/O 1 1 - 0 0 (TI03) Input 1 x - 1 x (TO03) Output 1 0 - 0 0 Input 0 x - 1 x Output 0 0/1 - 0 1 SCL20 Output 0 0/1 - 0 1 (TI02) Input 1 x - 1 x SCK20 <R> PIORx (TO02) Output 1 0 - 0 0 TI01 Input x - - 1 x TO01 Output x - - 0 0 INTP5 Input 0 - - 1 x (SI00) Input 1 - - 1 x (RxD0) Input 1 - - 1 x TI02 Input 0 x - 1 x TO02 Output 0 0 - 0 0 (SO00) Output 1 0/1 - 0 1 (TxD0) Output 1 0/1 - 0 1 x: don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMCxx: Port mode control register 2. PMxx: Port mode register Pxx: Port output latch The relationship between pins and their alternate functions shown in this table indicates the relationship when a 128-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIORx, POMxx, PMCxx, PMxx, and Pxx set in the same way. 3. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The Note 3 is described after the last table.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 265 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-22. Settings of Port Related Register When Using Alternate Function (3/5) Pin Name Alternate Function Function Name P20 Note 2 ANI0 Note 2 Note 2 AVREFP P21 Note 2 ANI1 Note 2 Note 2 AVREFM P22 to P27 P30 Note 3 P31 Note 3 Note 2 P35 to P37 POMxx PMCxx PMxx Pxx I/O Input x - - 1 x Input x - - 1 x Input x - - 1 x Input x - - 1 x Input x - - 1 x INTP3 Input 0 - - 1 x RTC1HZ Output x - - 0 0 TI03 Input 0 - - 1 x ANI2 to ANI7 Note 2 TO03 Output 0 - - 0 0 INTP4 Input 0 - - 1 x Output 1 - - 0 0 Input x - 1 1 x (PCLBUZ0) Note 1 PIORx ANI23 to AN21 Note 1 P40 TOOL0 I/O x - - x x P42 TI04 Input 0 - - 1 x TO04 Output 0 - - 0 0 SCK01 Input x x - 1 x Output x 0/1 - 0 1 SCL01 Output x 0/1 - 0 1 SI01 Input x x - 1 x SDA01 I/O x 1 - 0 1 P45 SO01 Output x 0/1 - 0 1 P46 INTP1 Input 0 - - 1 x TI05 Input 0 - - 1 x TO05 Output 0 - - 0 0 P43 P44 P47 INTP2 Input x - - 1 x P52 SO31 Output x 0/1 - 0 1 P53 SI31 Input x x - 1 x SDA31 I/O x 1 - 0 1 SCK31 Input x x - 1 x Output x 0/1 - 0 1 Output x 0/1 - 0 1 P54 SCL31 Remarks 1. x: don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMCxx: Port mode control register 2. PMxx: Port mode register Pxx: Port output latch The relationship between pins and their alternate functions shown in this table indicates the relationship when a 128-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIORx, POMxx, PMCxx, PMxx, and Pxx set in the same way. 3. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). (The Notes 1 to 3 are described after the last table.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 266 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-22. Settings of Port Related Register When Using Alternate Function (4/5) Pin Name Alternate Function Function Name PIORx POMxx PMCxx PMxx Pxx I/O P60 SCLA0 I/O 0 - - 0 0 P61 SDAA0 I/O 0 - - 0 0 P62 SCLA1 I/O x - - 0 0 P63 SDAA1 I/O x - - 0 0 P64 to P67 P70 P71 P72 P73 P74, P75 P76 P77 P80 P81 P82 P84 to P87 Remarks 1. 2. 3. TI10 to TI13 Input x - - 1 x TO10 to TO13 Output x - - 0 0 KR0 Input x - - 1 x SCK21 Input x - - 1 x Output x - - 0 1 SCL21 Output x - - 0 1 KR1 Input x x - 1 x SI21 Input x x - 1 x SDA21 I/O x 1 - 0 1 KR2 Input x - - 1 x SO21 Output x - - 0 1 KR3 Input x - - 1 x KR4, KR5 Input x x - 1 x INTP8, INTP9 Input 0 x - 1 x KR6 Input x x - 1 x INTP10 Input 0 x - 1 x (RxD2) Input 1 x - 1 x KR7 Input x - - 1 x INTP11 Input 0 - - 1 x (TxD2) Output 1 0/1 - 0 1 (SCK10) Input 1 x - 1 x Output 1 0/1 - 0 1 (SCL10) Output 1 0/1 - 0 1 (SI10) Input 1 x - 1 x (RxD1) Input 1 x - 1 x (SDA10) I/O 1 1 - 0 1 (SO10) Output 1 0/1 - 0 1 (TxD1) Output 1 0/1 - 0 1 (INTP6) to (INTP9) Input 1 - - 1 x x: don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMCxx: Port mode control register PMxx: Port mode register Pxx: Port output latch The relationship between pins and their alternate functions shown in this table indicates the relationship when a 128-pin product is used. In other products, alternate functions might be assigned to different pins, but even in this case, the PIORx, POMxx, PMCxx, PMxx, and Pxx set in the same way. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 267 RL78/G13 CHAPTER 4 PORT FUNCTIONS Table 4-22. Settings of Port Related Register When Using Alternate Function (5/5) Pin Name Alternate Function PIORx POMxx PMCxx PMxx Input x - - 1 x Output x - - 0 1 SCL11 Output x - - 0 1 P96 SI11 Input x x - 1 x SDA11 I/O x 1 - 0 1 P97 SO11 Output x - - 0 1 P100 ANI20 Input x - 1 1 x P102 TI06 Input 0 - - 1 x Function Name P95 SCK11 P103 to P106 Note 1 Output 0 - - 0 0 TI14 to TI17 Input x - - 1 x TO14 to TO17 Output x - - 0 0 Input 1 - - 1 x Input x - 1 1 x Input x - 1 1 x INTP0 Input x - - - x PCLBUZ0 Output 0 - - 0 0 P115 to P117 ANI26 to ANI24 P120 ANI19 P137 P140 P141 P142 P143 P144 P145 P146 Note 1 Note 1 INTP6 Input 0 - - 1 x PCLBUZ1 Output 0 - - 0 0 INTP7 Input 0 - - 1 x SCK30 Input x x - 1 x Output x 0/1 - 0 1 SCL30 Output x 0/1 - 0 1 RxD3 Input x x - 1 x SI30 Input x x - 1 x SDA30 I/O x 1 - 0 1 TxD3 Output x 0/1 - 0 1 SO30 Output x 0/1 - 0 1 TI07 Input 0 - - 1 x TO07 Output 0 - - 0 0 Input 1 - - 1 x (INTP4) P147 ANI18 Note 2 P150 to P156 Remarks 1. I/O TO06 (INTP10), (INTP11) P110, P111 Pxx Note 1 ANI8 to ANI14 x: Note 2 Input x - 1 1 x Input x - - 1 x don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMCxx: Port mode control register 2. PMxx: Port mode register Pxx: Port output latch The relationship between pins and their alternate functions shown in this table indicates the relationship when a 128-pin product is used. In other products, alternate functions might be assigned to different 3. pins, but even in this case, the PIORx, POMxx, PMCxx, PMxx, and Pxx set in the same way. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 268 RL78/G13 CHAPTER 4 PORT FUNCTIONS Notes 1. The functions of the ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100, ANI21/P37 to ANI23/P35, and ANI24/P117 to ANI26/P115 pins can be selected by using the port mode control registers 0, 3, 10, 11, 12, 14 (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14), analog input channel specification register (ADS), and port mode registers 0, 3, 10, 11, 12, 14 (PM0, PM3, PM10, PM11, PM12, PM14). Table 4-23. Setting Functions of ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100, ANI21/P37 to ANI23/P35, and ANI24/P117 to ANI26/P115 pins PMC0, PMC3, PMC10, PMC11, PMC12, PMC14 Registers PM0, PM3, PM10, PM11, PM12, PM14 Registers Digital I/O selection Input mode x Digital input Output mode x Digital output Analog input selection Input mode Output mode ADS Register ANI16/P03, ANI17/P02, ANI18/P147, ANI19/P120, ANI20/P100, ANI21/P37 to ANI23/P35, ANI24/P117 to ANI26/P115 Pins Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. 2. The functions of the ANI0/P20 to ANI7/P27, ANI8/P150 to ANI14/P156 pins can be selected by using the A/D port configuration register (ADPC), analog input channel specification register (ADS), and port mode registers 2, 15 (PM2, PM15). Table 4-24. Setting Functions of ANI0/P20 to ANI7/P27, ANI8/P150 to ANI14/P156 pins ADPC Register Digital I/O selection PM2, PM15 Register ADS Register Input mode Output mode Analog input selection ANI0/P20 to ANI7/P27, ANI8/P150 to ANI14/P156 Pins x Digital input x Digital output Input mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Output mode Selects ANI. Setting prohibited Does not select ANI. 3. In the products other than 128-pin products, multiple alternate output functions are assigned to the pins. In such cases, the output from the alternate functions that are not used in any settings except the one indicated in table 4-22 must be set to the same value as the one in the initial status. For more detail about the targets and the method of processing, refer to the section 4.6.2. Remark x: don't care R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 269 RL78/G13 CHAPTER 4 PORT FUNCTIONS 4.6 Cautions When Using Port Function 4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. <Example> When P10 is an output port, P11 to P17 are input ports (all pin statuses are high level), and the port latch value of port 1 is 00H, if the output of output port P10 is changed from low level to high level via a 1-bit manipulation instruction, the output latch value of port 1 is FFH. Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/G13. <1> The Pn register is read in 8-bit units. <2> The targeted one bit is manipulated. <3> The Pn register is written in 8-bit units. In step <1>, the output latch value (0) of P10, which is an output port, is read, while the pin statuses of P11 to P17, which are input ports, are read. If the pin statuses of P11 to P17 are high level at this time, the read value is FEH. The value is changed to FFH by the manipulation in <2>. FFH is written to the output latch by the manipulation in <3>. Figure 4-74. Bit Manipulation Instruction (P10) 1-bit manipulation instruction (set1 P1.0) is executed for P10 bit. P10 Low-level output P11 to P17 P10 High-level output P11 to P17 Pin status: High level Port 1 output latch 0 0 0 Pin status: High level Port 1 output latch 0 0 0 0 0 1 1 1 1 1 1 1 1 1-bit manipulation instruction for P10 bit <1> Port register 1 (P1) is read in 8-bit units. * In the case of P10, an output port, the value of the port output latch (0) is read. * In the case of P11 to P17, input ports, the pin status (1) is read. <2> Set the P10 bit to 1. <3> Write the results of <2> to the output latch of port register 1 (P1) in 8-bit units. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 270 RL78/G13 CHAPTER 4 PORT FUNCTIONS <R> 4.6.2 Notes on specifying the pin settings If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the unused alternate function must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR). For details about the alternate output function, see 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function. No specific setting is required for input pins because the output function of their alternate functions is disabled (the buffer output is Hi-Z). Table 4-25. Handling of Unused Alternate Functions Affected Unit Output or I/O Pins Handling of Unused Alternate Functions of Unused Alternate Functions Timer array units TOmn Make sure that bit m (TOmn) of timer output register m (TOm) and bit n (TOEmn) of timer output enable register m (TOEm) are set to their initial value (0). Clock/buzzer PCLBUZn Serial array units IICA Make sure that bit 7 (PCLOEn) of clock output select register n (CKSn) is set to its initial value (0). output circuit SCKmn, SOmn, Make sure that bit n (SEmn) of serial channel enable status register m (SEm), bit n SCLmn, SDAmn, (SOmn) of serial output register m (SOm), and bit n (SOEmn) of serial output enable TxDn register m (SOEm) are set to their initial value (1 for SOmn and 0 for others) SCAA0, SDAA0 Disable the IICA operation by setting bit 7 (IICE0) of the IICCTL00 register to 0. Note . Note m = 0 for TxD0 and TxD1, and m = 1 for TxD2 and TxD3 Example: P16/TI01/TO01/INTP5/SO11 pin of 20-pin products (1) When the pin is used as SO11 output P16: Specify the output mode by setting PM16 of port mode register 1 to 0. TI01, INTP5: These are input pins, so this note does not apply. TO01: This is an output pin, so set TO01 and TOE01 of timer array unit 0 to 0. (2) When the pin is used as TO01 output P16: Specify the output mode by setting PM16 of port mode register 1 to 0. SO11: This is an output pin, so set SE11, SO11, and SOE11 of serial array unit 1 to 0, 1, and 0, respectively. TI01: This is an input pin, so this note does not apply. Like SCL11 when using the P30/INTP3/SCK11/SCL11 pin as the SCK11 I/O pin, changing the operation mode does not enable alternate functions assigned to pins on the same serial channel, and this note does not apply to such pins. (If the CSI function is specified (MD012 = MD011 = 0), the pin does not function as a simplified I2C pin, and therefore SCL11 output is invalid.) Disabling the unused functions, including blocks that are only used for input or do not have I/O, is recommended to lower power consumption. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 271 RL78/G13 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the product. Note Output pin 20, 24, 25, 30, 32, 36-pin 40, 44, 48, 52, 64, 80, 100, 128-pin X1, X2 pins EXCLK pin XT1, XT2 pins - EXCLKS pin - The 20, 24, 25, 30, 32, and 36-pin products don't have the subsystem clock. 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock operation status control register (CSC)). <2> High-speed on-chip oscillator The frequency at which to oscillate can be selected from among fIH = 32, 24, 16, 12, 8, 4, or 1 MHz (typ.) by using the option byte (000C2H). After a reset release, the CPU always starts operating with this high-speed on-chip oscillator clock. Oscillation can be stopped by executing the STOP instruction or setting the HIOSTOP bit (bit 0 of the CSC register). <R> The frequency specified by using an option byte can be changed by using the high-speed on-chip oscillator frequency select register (HOCODIV). For details about the frequency, see Figure 5-9 Format of High-speed On-chip Oscillator Frequency Select Register (HOCODIV). The frequencies that can be specified for the high-speed on-chip oscillator by using the option byte and the high-speed on-chip oscillator frequency select register (HOCODIV) are shown below. Power Supply Voltage Oscillation Frequency (MHz) 1 2 3 4 6 8 12 16 24 32 2.7 V VDD 5.5 V 2.4 V VDD < 2.7 V - - 1.8 V VDD < 2.4 V - - - - 1.6 V VDD < 1.8 V - - - - - - - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 272 RL78/G13 CHAPTER 5 CLOCK GENERATOR An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK/X2/P122 pin. An external main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed onchip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)). (2) Subsystem clock * XT1 clock oscillator This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2. Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)). <R> An external subsystem clock (fEXT = 32.768 KHz) can also be supplied from the EXCLKS/XT2/P124 pin. An external subsystem clock input can be disabled by the setting of the XTSTOP bit. (3) Low-speed on-chip oscillator clock (Low-speed On-chip oscillator) This circuit oscillates a clock of fIL = 15 kHz (TYP.). The low-speed on-chip oscillator clock cannot be used as the CPU clock. Only the following peripheral hardware runs on the low-speed on-chip oscillator clock. * Watchdog timer * Real-time clock * 12-bit Interval timer This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed mode control register (OSMC), or both are set to 1. However, when WDTON = 1, WUTMMCK0 = 0, and bit 0 (WDSTBYON) of the option byte (000C0H) is 0, oscillation of the low-speed on-chip oscillator stops if the HALT or STOP instruction is executed. Caution The low-speed on-chip oscillator clock (fIL) can only be selected as the real-time clock operation clock when the fixed-cycle interrupt function is used. Remark <R> fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fXT: XT1 clock oscillation frequency fEXT: External subsystem clock frequency fIL: Low-speed on-chip oscillator clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 273 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Peripheral enable register 0 (PER0) Operation speed mode control register (OSMC) High-speed on-chip oscillator frequency select register (HOCODIV) High-speed on-chip oscillator trimming register (HIOTRM) Oscillators X1 oscillator XT1 oscillator High-speed on-chip oscillator Low-speed on-chip oscillator R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 274 RL78/G13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Figure 5-1. Block Diagram of Clock Generator <R> Internal bus Clock operation mode control register (CMC) Clock operation status control register (CSC) AMPH EXCLK OSCSEL System clock control register (CKC) Oscillation stabilization time select register (OSTS) CLS OSTS2 OSTS1 OSTS0 MSTOP CSS MCS MCM0 Standby controller 3 X1/P121 X2/EXCLK /P122 STOP mode X1 oscillation stabilization time counter STOP mode signal HALT mode Normal operation mode MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 High-speed High-speedsystem system clock clockoscillator oscillator Crystal/ceramic oscillation fX External input clock fEX Oscillation stabilization time counter status register (OSTC) fMX Option byte (000C2H) FRQSEL0 to FRQSEL3 Selector High-speed on-chip oscillator Clock output/ buzzer output fMAIN fCLK Oscillation (32 MHz (TYP.)) Oscillation (24MHz (TYP.)) Oscillation (16 MHz (TYP.)) Oscillation (12 MHz (TYP.)) WUTMMCK0 IOscillation (4 MHz (TYP.)) Oscillation (1 MHz (TYP.)) Low-speed on-chip oscillator fIL HALT/STOP mode signal Watchdog timer Oscillation (15 kHz (TYP.)) XT2/EXCLKS /P124 fSUB Crystal oscillation fXT External input clock fEXT Controller CLS AMPHS1 AMPHS0 Clock operation mode control register (CMC) EXCLKS OSCSELS HOCODIV2 HOCODIV1 HOCODIV0 High-speed on-chip oscillator frequency select register (HOCODIV) 6 XTSTOP HIOSTOP Clock operation status control register (CSC) HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 High-speed on-chip oscillator trimming register(HIOTRM) Internal bus (Remark is listed on the next page after next.) Real-time clock, 12-bit Interval timer RTC EN Operation speed mode control register (OSMC) RTCLPC WUTMMCK0 IICA1 EN ADC EN IICA0 EN Peripheral enable register 0 (PER0) SAU1 EN SAU0 EN TAU1 EN TAU0 EN Serial array unit 0 Serial array unit 1 Serial interface IICA A/D converter Serial interface IICA 275 CHAPTER 5 CLOCK GENERATOR XT1/P123 Controller Selector Subsystem clock oscillator Timer array unit 0 Timer array unit 1 Option byte (000C0H) WDTON WDSTBYON Controller Oscillation (8 MHz (TYP.)) CPU CPU clock and peripheral hardware clock source selection Main system clock source selector fIH RL78/G13 Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency <R> fXT: XT1 clock oscillation frequency fEXT: External subsystem clock frequency fSUB: Subsystem clock frequency fCLK: CPU/peripheral hardware clock frequency fIL: Low-speed on-chip oscillator clock frequency 5.3 Registers Controlling Clock Generator The following nine registers are used to control the clock generator. * Clock operation mode control register (CMC) * System clock control register (CKC) * Clock operation status control register (CSC) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) * Peripheral enable register 0 (PER0) * Operation speed mode control register (OSMC) * High-speed on-chip oscillator frequency select register (HOCODIV) * High-speed on-chip oscillator trimming register (HIOTRM) (1) Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121, X2/EXCLK/P122, XT1/P123, and XT2/EXCLKS/P124 pins, and to select a gain of the oscillator. The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 276 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CMC EXCLK OSCSEL EXCLKS OSCSELS 0 AMPHS1 AMPHS0 AMPH EXCLK OSCSEL High-speed system clock pin operation mode 0 0 Input port mode Input port 0 1 X1 oscillation mode Crystal/ceramic resonator connection 1 0 Input port mode Input port 1 1 External clock input mode Input port EXCLKS OSCSELS Subsystem clock pin operation mode 0 0 X1/P121 pin XT1/P123 pin Input port mode Input port X2/EXCLK/P122 pin External clock input XT2/EXCLKS/P124 pin 0 1 XT1 oscillation mode Crystal resonator connection 1 0 Input port mode Input port 1 1 External clock input mode Input port AMPHS1 AMPHS0 0 0 Low power consumption oscillation (default) 0 1 Normal oscillation 1 0 Ultra-low power consumption oscillation 1 1 Setting prohibited External clock input XT1 oscillator oscillation mode selection AMPH Control of X1 clock oscillation frequency 0 1 MHz fX 10 MHz 1 10 MHz < fX 20 MHz Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory manipulation instruction. When using the CMC register with its initial value (00H), be <R> sure to set the register to 00H after a reset ends in order to prevent malfunction due to a program loop. Such a malfunction becomes unrecoverable when a value other than 00H is mistakenly written.. 2. After reset release, set the CMC register before X1 or XT1 oscillation is started as set by the clock operation status control register (CSC). 3. Be sure to set the AMPH bit to 1 if the X1 clock oscillation frequency exceeds 10 MHz. <R> 4. Specify the settings for the AMPH, AMPHS1, and AMPHS0 bits while fIH is selected as <R> <R> 5. Oscillation stabilization time of fXT, counting on the software. fCLK after a reset ends (before fCLK is switched to fMX). 6. Although the maximum system clock frequency is 32 MHz, the maximum frequency of the X1 oscillator is 20 MHz. (Cautions and Remark are given on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 277 RL78/G13 CHAPTER 5 CLOCK GENERATOR Cautions 7. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. * Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems. * When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the mode of the XT1 oscillator, use the recommended resonators described in 5.7 Resonator and Oscillator Constants. * Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected. * Configure the circuit of the circuit board, using material with little wiring resistance. * Place a ground pattern that has the same potential as VSS as much as possible near the XT1 oscillator. * Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due to moisture absorption of the circuit board in a high-humidity environment or dew condensation on the board. When using the circuit board in such an environment, take measures to damp-proof the circuit board, such as by coating. * When coating the circuit board, use material that does not cause capacitance or leakage between the XT1 and XT2 pins. Remark fX: X1 clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 278 RL78/G13 CHAPTER 5 CLOCK GENERATOR (2) System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-3. Format of System Clock Control Register (CKC) Address: FFFA4H After reset: 00H R/W Note 1 Symbol <7> <6> <5> <4> 3 2 1 0 CKC CLS CSS MCS MCM0 0 0 0 0 CLS 0 Main system clock (fMAIN) 1 Subsystem clock (fSUB) CSS 1 Status of CPU/peripheral hardware clock (fCLK) Selection of CPU/peripheral hardware clock (fCLK) 0 Main system clock (fMAIN) Note 2 Subsystem clock (fSUB) MCS Status of Main system clock (fMAIN) 0 High-speed on-chip oscillator clock (fIH) 1 High-speed system clock (fMX) MCM0 Note 2 Main system clock (fMAIN) operation control 0 Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN) 1 Selects the high-speed system clock (fMX) as the main system clock (fMAIN) Notes 1. Bits 7 and 5 are read-only. 2. Changing the value of the MCM0 bit is prohibited while the CSS bit is set to 1. Remark fIH: High-speed on-chip oscillator clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency fSUB: Subsystem clock frequency (Cautions are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 279 RL78/G13 CHAPTER 5 CLOCK GENERATOR Cautions 1. Be sure to set bit 3 to 0 to 0. 2. The clock set by the CSS bit is supplied to the CPU and peripheral hardware. If the CPU clock is changed, therefore, the clock supplied to peripheral hardware (except the real-time clock, 12-bit interval timer, clock output/buzzer output, and watchdog timer) is also changed at the same time. Consequently, stop each peripheral function when changing the CPU/peripheral hardware clock. 3. If the subsystem clock is used as the peripheral hardware clock, the operations of the A/D converter and IICA are not guaranteed. For the operating characteristics of the peripheral hardware, refer to the chapters describing the various peripheral hardware as well as CHAPTER 29 ELECTRICAL SPECIFICATIONS. (3) Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to C0H. Figure 5-4. Format of Clock Operation Status Control Register (CSC) Address: FFFA1H After reset: C0H R/W Symbol <7> <6> 5 4 3 2 1 <0> CSC MSTOP XTSTOP 0 0 0 0 0 HIOSTOP MSTOP High-speed system clock operation control X1 oscillation mode External clock input mode 0 X1 oscillator operating External clock from EXCLK pin is valid 1 X1 oscillator stopped External clock from EXCLK pin is invalid XTSTOP Input port mode Input port Subsystem clock operation control XT1 oscillation mode External clock input mode 0 XT1 oscillator operating External clock from EXCLKS pin is valid 1 XT1 oscillator stopped External clock from EXCLKS pin is invalid HIOSTOP Input port mode Input port High-speed on-chip oscillator clock operation control 0 High-speed on-chip oscillator operating 1 High-speed on-chip oscillator stopped Cautions 1. After reset release, set the clock operation mode control register (CMC) before setting the CSC register. 2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP bit to 0 after releasing reset. Note that if the OSTS register is being used with its default settings, the OSTS register is not required to be set here. 3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization time of the X1 clock by using the oscillation stabilization time counter status register (OSTC). 4. When starting XT1 oscillation by setting the XSTOP bit, wait for oscillation of the subsystem clock to stabilize by setting a wait time using software. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 280 RL78/G13 CHAPTER 5 CLOCK GENERATOR Cautions 5. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the OSC register. 6. The setting of the flags of the register to stop clock oscillation (invalidate the external clock input) and the condition before clock oscillation is to be stopped are as Table 5-2 . Table 5-2. Stopping Clock Method Clock X1 clock External main system clock XT1 clock External subsystem clock High-speed on-chip oscillator clock Condition Before Stopping Clock (Invalidating External Clock Input) CPU and peripheral hardware clocks operate with a clock other than the high-speed system clock. Setting of CSC Register Flags MSTOP = 1 (CLS = 0 and MCS = 0, or CLS = 1) CPU and peripheral hardware clocks operate with a clock other than the subsystem clock. XTSTOP = 1 (CLS = 0) CPU and peripheral hardware clocks operate with a clock other than the high-speed on-chip oscillator clock. HIOSTOP = 1 (CLS = 0 and MCS = 1, or CLS = 1) (4) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case, * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction. When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register (CSC)) = 1 clear the OSTC register to 00H. Remark The oscillation stabilization time counter starts counting in the following cases. * When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 MSTOP = 0) * When the STOP mode is released R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 281 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H Symbol OSTC After reset: 00H 7 6 5 R 4 3 2 1 0 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 8 25.6 s max. 12.8 s max. 8 25.6 s min. 12.8 s min. 9 51.2 s min. 25.6 s min. 10 102.4 s min. 51.2 s min. 11 204.8 s min. 102.4 s min. 13 819.2 s min. 409.6 s min. 15 3.27 ms min. 1.64 ms min. 0 0 0 0 0 0 0 0 2 /fX max. 1 0 0 0 0 0 0 0 2 /fX min. 1 1 0 0 0 0 0 0 2 /fX min. 1 1 1 0 0 0 0 0 2 /fX min. 1 1 1 1 0 0 0 0 2 /fX min. 1 1 1 1 1 0 0 0 2 /fX min. 1 1 1 1 1 1 0 0 2 /fX min. 17 13.11 ms min. 6.55 ms min. 18 26.21 ms min. 13.11 ms min. 1 1 1 1 1 1 1 0 2 /fX min. 1 1 1 1 1 1 1 1 2 /fX min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register (OSTS). In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register. * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released.) 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 282 RL78/G13 CHAPTER 5 CLOCK GENERATOR (5) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS register after the STOP mode is released. When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using the OSTC register. The OSTS register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets the OSTS register to 07H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 283 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 25.6 s 9 51.2 s 25.6 s 10 102.4 s 51.2 s 11 204.8 s 102.4 s 0 0 0 2 /fX 0 0 1 2 /fX 0 1 0 2 /fX 0 1 1 2 /fX 819.2 s 409.6 s 15 3.27 ms 1.64 ms 17 13.11 ms 6.55 ms 18 26.21 ms 13.11 ms 0 0 2 /fX 1 0 1 2 /fX 1 1 0 2 /fX 1 1 12.8 s 13 1 1 fX = 20 MHz 8 2 /fX Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before executing the STOP instruction. 2. Change the setting of the OSTS register before setting the MSTOP bit of the clock operation status control register (CSC) to 0. 3. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 4. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the OSTS register. In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register after the oscillation starts. * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released.) 5. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 284 RL78/G13 CHAPTER 5 CLOCK GENERATOR (6) Peripheral enable register 0 (PER0) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each function before specifying the initial settings of the peripheral functions. * Real-time clock, 12-bit interval timer * Serial interface IICA1 * A/D converter * Serial interface IICA0 * Serial array unit 1 * Serial array unit 0 * Timer array unit 1 * Timer array unit 0 The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/3) Address: F00F0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note 2 Note 3 Note 1 RTCEN Note 1 Control of real-time clock (RTC) and 12-bit interval timer input clock supply Stops input clock supply. 0 * SFR used by the real-time clock (RTC) and 12-bit interval timer cannot be written. * The real-time clock (RTC) and 12-bit interval timer are in the reset status. Enables input clock supply. 1 * SFR used by the real-time clock (RTC) and 12-bit interval timer can be read and written. IICA1EN Control of serial interface IICA1 input clock supply Stops input clock supply. 0 * SFR used by the serial interface IICA1 cannot be written. * The serial interface IICA1 is in the reset status. Enables input clock supply. 1 * SFR used by the serial interface IICA1 can be read and written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Caution Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 285 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/3) Address: F00F0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note 2 Note 3 Note 1 ADCEN Note 1 Control of A/D converter input clock supply Stops input clock supply. 0 * SFR used by the A/D converter cannot be written. * The A/D converter is in the reset status. Enables input clock supply. 1 * SFR used by the A/D converter can be read and written. IICA0EN Control of serial interface IICA0 input clock supply Stops input clock supply. 0 * SFR used by the serial interface IICA0 cannot be written. * The serial interface IICA0 is in the reset status. Enables input clock supply. 1 * SFR used by the serial interface IICA0 can be read and written. SAU1EN Control of serial array unit 1 input clock supply Stops input clock supply. 0 * SFR used by the serial array unit 1 cannot be written. * The serial array unit 1 is in the reset status. Enables input clock supply. 1 * SFR used by the serial array unit 1 can be read and written. SAU0EN Control of serial array unit 0 input clock supply Stops input clock supply. 0 * SFR used by the serial array unit 0 cannot be written. * The serial array unit 0 is in the reset status. Enables input clock supply. 1 * SFR used by the serial array unit 0 can be read and written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Caution Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 286 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (3/3) Address: F00F0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note 2 Note 3 Note 1 TAU1EN Note 1 Control of timer array unit 1 input clock supply Stops input clock supply. 0 * SFR used by timer array unit 1 cannot be written. * Timer array unit 1 is in the reset status. Enables input clock supply. 1 * SFR used by timer array unit 1 can be read and written. TAU0EN Control of timer array unit 0 input clock supply Stops input clock supply. 0 * SFR used by timer array unit 0 cannot be written. * Timer array unit 0 is in the reset status. Enables input clock supply. 1 * SFR used by timer array unit 0 can be read and written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Caution Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 287 RL78/G13 CHAPTER 5 CLOCK GENERATOR (7) Operation speed mode control register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock and 12-bit interval timer, is stopped in STOP mode or HALT mode while subsystem clock is selected as CPU clock. Set bit 7 (RTCEN) of peripheral enable registers 0 (PER0) to 1 before this setting. In addition, the OSMC register can be used to select the operation clock of the real-time clock and 12-bit interval timer. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-8. Format of Operation Speed Mode Control Register (OSMC) Address: F00F3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0 RTCLPC 0 Setting in STOP mode or HALT mode while subsystem clock is selected as CPU clock Enables supply of subsystem clock to peripheral functions (See Table 18-1 for peripheral functions whose operations are enabled.) 1 Stops supply of subsystem clock to peripheral functions other than real-time clock and 12-bit interval timer. WUTMMCK0 Selection of operation clock for real-time clock and 12-bit interval timer. 0 Subsystem clock (fSUB) 1 Low-speed on-chip oscillator clock (fIL) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 288 RL78/G13 CHAPTER 5 CLOCK GENERATOR (8) High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H). The HOCODIV register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to default value (undefined). Figure 5-9. Format of High-speed On-chip Oscillator Frequency Select Register (HOCODIV) Address: F00A8H After reset: undefined R/W Symbol 7 6 5 4 3 HOCODIV 0 0 0 0 0 HOCODIV2 HOCODIV1 HOCODIV0 2 1 HOCODIV2 HOCODIV1 HOCODIV0 High-Speed On-Chip Oscillator Clock Frequency FRQSEL3 Bit is 0 FRQSEL3 Bit of is 1 0 0 0 24 MHz 32 MHz 0 0 1 12 MHz 16 MHz 0 1 0 6 MHz 8 MHz 0 1 1 3 MHz 4 MHz 1 0 0 Setting prohibited 2 MHz 0 1 Setting prohibited 1 MHz 1 0 Other than aboves Setting prohibited Cautions 1. Set the HOCODIV register within the operable voltage range both before and after changing the frequency. 2. Use the device within the voltage of the flash operation mode set by the option byte (000C2H) even after the frequency has been changed by using the HOCODIV register. Option Byte (000C2H) Value CMODE1 <R> Flash Operation Mode Operating Operating Voltage Frequency Range Range CMODE2 0 0 LV (low-voltage main) mode 1 to 4 MHz 1.6 to 5.5 V 1 0 LS (low-speed main) mode 1 to 8 MHz 1.8 to 5.5 V 1 1 HS (high-speed main) mode 1 to 16 MHz 2.4 to 5.5 V 1 to 32 MHz 2.7 to 5.5 V 3. The device operates at the old frequency for the duration of 3 clocks after the frequency value has been changed by using the HOCODIV register. When setting of high-speed on-chip oscillator clock as system clock, and the clock oscillation stabilization wait three minutes further. 4. To change the frequency of the high-speed on-chip oscillator when X1 oscillation, external oscillation input or subclock is set for the system clock, stop the highspeed on-chip oscillator by setting bit 0 (HIOSTOP) of the CSC register to 1 and then change the frequency. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 289 RL78/G13 CHAPTER 5 CLOCK GENERATOR (9) High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted. The HIOTRM register can be set by an 8-bit memory manipulation instruction. Caution The frequency will vary if the temperature and VDD pin voltage change after accuracy adjustment. When the temperature and VDD voltage change, accuracy adjustment must be executed regularly or before the frequency accuracy is required. Figure 5-10. Format of High-Speed On-Chip Oscillator Trimming Register (HIOTRM) Address: F00A0H After reset: Note R/W Symbol 7 6 5 4 3 2 1 0 HIOTRM 0 0 HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 High-speed on-chip Minimum speed oscillator 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 * * * 1 1 1 1 1 0 1 1 1 1 1 1 Maximum speed Note The reset value differs for each chip. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 290 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows. * Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1 * External clock input: EXCLK, OSCSEL = 1, 1 When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0). When the pins are not used as input port pins, either, see Table 2-3 Connection of Unused Pins. Figure 5-11 shows an example of the external circuit of the X1 oscillator. Figure 5-11. Example of External Circuit of X1 Oscillator (a) Crystal or ceramic oscillation (b) External clock VSS X1 X2 External clock EXCLK Crystal resonator or ceramic resonator Cautions are listed on the next page. 5.4.2 XT1 oscillator The XT1 oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. To use the XT1 oscillator, set bit 4 (OSCSELS) of the clock operation mode control register (CMC) to 1. An external clock can also be input. In this case, input the clock signal to the EXCLKS pin. To use the XT1 oscillator, set bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode control register (CMC) as follows. * Crystal or ceramic oscillation: EXCLKS, OSCSELS = 0, 1 * External clock input: EXCLKS, OSCSELS = 1, 1 When the XT1 oscillator is not used, set the input port mode (EXCLKS, OSCSELS = 0, 0). When the pins are not used as input port pins, either, see Table 2-3 Connection of Unused Pins. Figure 5-12 shows an example of the external circuit of the XT1 oscillator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 291 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock VSS XT1 32.768 kHz XT2 External clock EXCLKS Caution 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-10 and 5-11 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. * Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems. * When using the ultra-low power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) as the mode of the XT1 oscillator, use the recommended resonators described in CHAPTER 29 ELECTRICAL SPECIFICATIONS. * Make the wiring between the XT1 and XT2 pins and the resonators as short as possible, and minimize the parasitic capacitance and wiring resistance. Note this particularly when the ultralow power consumption oscillation (AMPHS1, AMPHS0 = 1, 0) is selected. * Configure the circuit of the circuit board, using material with little wiring resistance. * Place a ground pattern that has the same potential as VSS as much as possible near the XT1 oscillator. * Be sure that the signal lines between the XT1 and XT2 pins, and the resonators do not cross with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * The impedance between the XT1 and XT2 pins may drop and oscillation may be disturbed due to moisture absorption of the circuit board in a high-humidity environment or dew condensation on the board. When using the circuit board in such an environment, take measures to damp-proof the circuit board, such as by coating. * When coating the circuit board, use material that does not cause capacitance or leakage between the XT1 and XT2 pins. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 292 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-13 shows examples of incorrect resonator connection. Figure 5-13. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 NG NG NG (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires. VSS VSS X1 X1 X2 X2 Note Power supply/GND pattern Note Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board. Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics. Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 293 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-13. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 B X2 C High current (g) Signals are fetched VSS Caution X1 X2 When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 294 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/G13. The frequency can be selected from among 32, 24, 16, 12, 8, 4, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset release. 5.4.4 Low-speed on-chip oscillator The low-speed on-chip oscillator is incorporated in the RL78/G13. The low-speed on-chip oscillator clock is used only as the watchdog timer, real-time clock, and 12-bit interval timer clock. The low-speed on-chip oscillator clock cannot be used as the CPU clock. This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed mode control register (OSMC), or both are set to 1. Unless the watchdog timer is stopped and WUTMMCK0 is a value other than zero, oscillation of the low-speed on-chip oscillator continues. While the watchdog timer operates, the low-speed on-chip oscillator clock does not stop even if the program freezes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 295 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). * Main system clock fMAIN * High-speed system clock fMX X1 clock fX External main system clock fEX * High-speed on-chip oscillator clock fIH * Subsystem clock fSUB * XT1 clock fXT <R> * External subsystem clock fEXT * Low-speed on-chip oscillator clock fIL * CPU/peripheral hardware clock fCLK The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/G13. When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-14. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 296 RL78/G13 CHAPTER 5 CLOCK GENERATOR Figure 5-14. Clock Generator Operation When Power Supply Voltage Is Turned On Power supply voltage (VDD) 1.6 V 1.51 V (TYP.) 0V <1> Internal reset signal Switched by software Reset processing Note3 <3> <5> high-speed on-chip oscillator clock CPU clock <5> High-speed system clock Subsystem clock <2> High-speed on-chip oscillator clock (fIH) High-speed system clock (fMX) (when X1 oscillation selected) Note 1 Subsystem clock (fSUB) (when XT1 oscillation selected) <4> X1 clock oscillation stabilization timeNote 2 Starting X1 oscillation is specified by software. <4> Starting XT1 oscillation is specified by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit. <2> When the power supply voltage exceeds 1.51 V (TYP.), the reset is released and the high-speed on-chip oscillator automatically starts oscillation. <3> The CPU starts operation on the high-speed on-chip oscillator clock after a reset processing such as waiting for the voltage of the power supply or regulator to stabilize has been performed after reset release. <4> Set the start of oscillation of the X1 or XT1 clock via software (see 5.6.2 Example of setting X1 oscillation clock and 5.6.3 Example of setting XT1 oscillation clock). <5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set switching via software (see 5.6.2 Example of setting X1 oscillation clock and 5.6.3 Example of setting XT1 oscillation clock). Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 2. When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). <R> 3. Reset processing time: 497 to 720 s (When LVD is used) 265 to 407 s (When LVD off) Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK pin is used. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 297 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 4, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H). [Option byte setting] Address: 000C2H Option byte 7 6 5 4 1 0 3 2 1 0 CMODE1 CMODE0 (000C2H) 0/1 0/1 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 0/1 0/1 0/1 0/1 CMODE1 CMODE0 0 0 LV (low voltage main) mode 1 0 LS (low speed main) mode VDD = 1.8 V to 5.5 V @ 1 MHz to 8 MHz 1 1 HS (high speed main) mode VDD = 2.4 V to 5.5 V @ 1 MHz to 16 MHz VDD = 2.7 V to 5.5 V @ 1 MHz to 32 MHz FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 1 0 0 0 32 MHz 0 0 0 0 24 MHz 1 0 0 1 16 MHz 0 0 0 1 12 MHz 1 0 1 0 8 MHz 1 0 1 1 4 MHz 1 1 0 1 1 MHz Setting of flash operation mode Other than above VDD = 1.6 V to 5.5 V @ 1 MHz to 4 MHz Frequency of the high-speed on-chip oscillator Setting prohibited [High-speed on-chip oscillator frequency select register (HOCODIV) setting] Address: F00A8H HOCODIV 7 6 5 4 3 0 0 0 0 0 HOCODIV2 HOCODIV1 HOCODIV0 2 1 HOCODIV2 HOCODIV1 HOCODIV0 Selection of high-speed on-chip oscillator clock frequency FRQSEL3 Bit is 0 FRQSEL3 Bit of is 1 0 0 0 24 MHz 32 MHz 0 0 1 12 MHz 16 MHz 0 1 0 6 MHz 8 MHz 0 1 1 3 MHz 4 MHz 1 0 0 Setting prohibited 2 MHz 1 0 1 Setting prohibited 1 MHz Other than aboves R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 0 Setting prohibited 298 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by using the oscillation stabilization time select register (OSTS) and clock operation mode control register (CMC) and clock operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to fCLK by using the system clock control register (CKC). [Register settings] Set the register in the order of <1> to <5> below. <R> <1> Set (1) the OSCSEL bit of the CMC register, except for the cases where fX > 10 MHz, in such cases set (1) the AMPH bit, to operate the X1 oscillator. CMC 7 6 5 4 EXCLK OSCSEL EXCLKS OSCSELS 0 1 0 0 3 2 1 0 AMPHS1 AMPHS0 AMPH 0 0 1 0 AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less. <2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode. Example: Setting values when a wait of at least 102.4 s is set based on a 10 MHz resonator. 7 OSTS 0 6 0 5 0 4 0 3 2 1 0 OSTS2 OSTS1 OSTS0 0 1 0 0 0 <3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator. CSC 7 6 MSTOP XTSTOP 0 1 5 4 3 2 1 0 0 0 0 0 HIOSTOP 0 <4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize. Example: Wait until the bits reach the following values when a wait of at least 102.4 s is set based on a 10 MHz resonator. OSTC 7 6 5 4 3 2 1 0 MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 1 1 1 0 0 0 0 0 <5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock. CKC 7 6 5 4 CLS CSS MCS MCM0 0 0 0 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 3 2 1 0 0 0 0 0 299 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by using the operation speed mode control register (OSMC), clock operation mode control register (CMC), and clock operation status control register (CSC), set the XT1 oscillation clock to fCLK by using the system clock control register (CKC). [Register settings] Set the register in the order of <1> to <5> below. <1> To run only the real-time clock and 12-bit interval timer on the subsystem clock (ultra-low current consumption) when in the STOP mode or sub-HALT mode, set the RTCLPC bit to 1. 7 6 5 0/1 3 2 1 0 0 0 0 0 2 1 0 AMPHS1 AMPHS0 AMPH 0/1 0/1 0 WUTMMCK0 RTCLPC OSMC 4 0 0 0 <2> Set (1) the OSCSELS bit of the CMC register to operate the XT1 oscillator. CMC 7 6 5 4 EXCLK OSCSEL EXCLKS OSCSELS 0 0 0 1 3 0 AMPHS0 and AMPHS1 bits: These bits are used to specify the oscillation mode of the XT1 oscillator. <3> Clear (0) the XTSTOP bit of the CSC register to start oscillating the XT1 oscillator. CSC 7 6 MSTOP XTSTOP 1 0 5 4 3 2 1 0 0 0 0 0 0 HIOSTOP 0 <4> Use the timer function or another function to wait for oscillation of the subsystem clock to stabilize by using software. <5> Use the CSS bit of the CKC register to specify the XT1 oscillation clock as the CPU/peripheral hardware clock. CKC 7 6 5 4 CLS CSS MCS MCM0 0 1 0 0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 3 2 1 0 0 0 0 0 300 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15. CPU Clock Status Transition Diagram High-speed on-chip oscillator: Woken up X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) Power ON VDD < 1.51 V0.03 (A) Reset release VDD 1.51 V0.03 High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) VDD 1.6 V (operation guaranteed range:Transition voltage is defined by the LVD) <R> High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Selectable by CPU High-speed on-chip oscillator: Selectable by CPU X1 oscillation/EXCLK input: Selectable by CPU XT1 oscillation/EXCLKS input: Operating (B) (H) CPU: Operating with high-speed on-chip oscillator CPU: High-speed on-chip oscillator STOP (D) CPU: Operating with XT1 oscillation or EXCLKS input (J) (E) CPU: High-speed on-chip oscillator HALT (C) (G) CPU: XT1 oscillation/EXCLKS input HALT High-speed on-chip oscillator: Oscillatable X1 oscillation/EXCLK input: Oscillatable XT1 oscillation/EXCLKS input: Operating CPU: Operating with X1 oscillation or EXCLK input High-speed on-chip oscillator: Selectable by CPU X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Selectable by CPU CPU: High-speed on-chip oscillator SNOOZE High-speed on-chip oscillator: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Oscillatable High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Oscillatable High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Oscillatable XT1 oscillation/EXCLKS input: Oscillatable (I) (F) CPU: X1 oscillation/EXCLK input STOP CPU: X1 oscillation/EXCLK input HALT High-speed on-chip oscillator: Stops X1 oscillation/EXCLK input: Stops XT1 oscillation/EXCLKS input: Oscillatable High-speed on-chip oscillator: Oscillatable X1 oscillation/EXCLK input: Operating XT1 oscillation/EXCLKS input: Oscillatable R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 301 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A) Status Transition (A) (B) SFR Register Setting SFR registers do not have to be set (default status after reset release). (2) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).) (Setting sequence of SFR registers) <R> Setting Flag of SFR Register CMC Register Note OSTS CSC Register Register Register MSTOP MCM0 EXCLK OSCSEL AMPH Status Transition (A) (B) (C) 0 1 0 Note 2 Must be 0 (X1 clock: 1 MHz fX 10 MHz) (A) (B) (C) 0 1 1 Note 2 Must be 0 1 checked 1 x 1 Note 2 Must not be 0 1 checked (external main clock) Notes 1. 1 checked (X1 clock: 10 MHz < fX 20 MHz) (A) (B) (C) CKC OSTC Register The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. <R> 2. Set the oscillation stabilization time as follows. * Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS. (3) CPU operating with subsystem clock (D) after reset release (A) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (A) (B) (D) CMC Register Note EXCLKS OSCSELS AMPHS1 AMPHS0 CSC Waiting for CKC Register Oscillation Register XTSTOP Stabilization CSS 0 1 0/1 0/1 0 Necessary 1 1 1 x x 0 Necessary 1 (XT1 clock) (A) (B) (D) (external sub clock) Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. Remarks 1. x: don't care 2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 302 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/5) (4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) CMC Register Setting Flag of SFR Register Status Transition (B) (C) Note 1 OSTS CSC Register Register Register CKC MSTOP MCM0 OSTC Register EXCLK OSCSEL AMPH 0 1 0 Note 2 0 Must be checked 1 0 1 1 Note 2 0 Must be checked 1 1 1 x Note 2 0 Must not be checked 1 (X1 clock: 1 MHz fX 10 MHz) (B) (C) (X1 clock: 10 MHz < fX 20 MHz) (B) (C) (external main clock) Unnecessary if these registers Unnecessary if the CPU is operating with the high-speed system clock are already set Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This setting is not necessary if it has already been set. 2. Set the oscillation stabilization time as follows. * Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS. (5) CPU clock changing from high-speed on-chip oscillator clock (B) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (B) (D) CMC Register Note CSC Waiting for Register Oscillation CKC Register EXCLKS OSCSELS XTSTOP Stabilization CSS 0 1 0 Necessary 1 1 1 0 Necessary 1 (XT1 clock) (B) (D) (external sub clock) Unnecessary if the CPU is operating with the subsystem clock Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. Remarks 1. x: don't care 2. (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 303 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/5) (6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) (B) CSC Register Oscillation accuracy CKC Register HIOSTOP stabilization time MCM0 0 30 s 0 Unnecessary if the CPU is operating with the high-speed on-chip oscillator clock (7) CPU clock changing from high-speed system clock (C) to subsystem clock (D) (Setting sequence of SFR registers) Setting Flag of SFR Register CSC Register Waiting for Oscillation CKC Register XTSTOP Stabilization CSS 0 Necessary 1 Status Transition (C) (D) Unnecessary if the CPU is operating with the subsystem clock (8) CPU clock changing from subsystem clock (D) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (D) (B) CSC Register CKC Register HIOSTOP CSS MCM0 0 0 0 Unnecessary if the CPU Unnecessary if this is operating with the register is already set high-speed on-chip oscillator clock Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 304 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (4/5) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register OSTS CSC Register Register MSTOP Note 0 Note Note OSTC Register CKC Register CSS MCM0 Must be checked 0 1 0 Must be checked 0 1 0 Must not be checked 0 1 Status Transition (D) (C) (X1 clock: 1 MHz fX 10 MHz) (D) (C) (X1 clock: 10 MHz < fX 20 MHz) (D) (C) (external main clock) Unnecessary if the CPU is operating with the high-speed system clock Note Unnecessary if these registers are already set Set the oscillation stabilization time as follows. * Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 29 ELECTRICAL SPECIFICATIONS. (10) * HALT mode (E) set while CPU is operating with high-speed on-chip oscillator clock (B) * HALT mode (F) set while CPU is operating with high-speed system clock (C) * HALT mode (G) set while CPU is operating with subsystem clock (D) Status Transition (B) (E) Setting Executing HALT instruction (C) (F) (D) (G) Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 305 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (5/5) (11) * STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B) * STOP mode (I) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition (B) (H) Setting - Stopping peripheral functions that cannot (C) (I) In X1 oscillation operate in STOP mode Executing STOP instruction Sets the OSTS register External main - system clock (12) CPU changing from STOP mode (H) to SNOOZE mode (J) For details about the setting for switching from the STOP mode to the SNOOZE mode, see 11.8 SNOOZE Mode Function, 12.5.7 SNOOZE mode function and 12.6.3 SNOOZE mode function. Remark (A) to (J) in Table 5-3 correspond to (A) to (J) in Figure 5-15. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 306 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4. Changing CPU Clock (1/2) CPU Clock Before Change Condition Before Change Processing After Change After Change Stabilization of X1 oscillation Operating current can be reduced by chip oscillator * OSCSEL = 1, EXCLK = 0, MSTOP = 0 stopping high-speed on-chip oscillator clock * After elapse of oscillation stabilization time (HIOSTOP = 1). High-speed on- X1 clock External main Enabling input of external clock from the system clock EXCLK pin * OSCSEL = 1, EXCLK = 1, MSTOP = 0 XT1 clock Stabilization of XT1 oscillation * OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 External Enabling input of external clock from the subsystem clock EXCLKS pin * OSCSELS = 1, EXCLKS = 1, XTSTOP = 0 X1 clock <R> High-speed on- Oscillation of high-speed on-chip oscillator chip oscillator * HIOSTOP = 0 clock * After elapse of oscillation accuracy External main Transition not possible system clock (To change the clock, set it again after X1 oscillation can be stopped (MSTOP = 1). stabilization time - executing reset once.) XT1 clock Stabilization of XT1 oscillation X1 oscillation can be stopped (MSTOP = 1). * OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 * After elapse of oscillation stabilization time External Enabling input of external clock from the subsystem clock EXCLKS pin X1 oscillation can be stopped (MSTOP = 1). * OSCSELS = 1, EXCLKS = 1, XTSTOP = 0 <R> External main High-speed on- Oscillation of high-speed on-chip oscillator External main system clock input can be system clock chip oscillator * HIOSTOP = 0 disabled (MSTOP = 1). clock * After elapse of oscillation accuracy X1 clock Transition not possible stabilization time - (To change the clock, set it again after executing reset once.) XT1 clock Stabilization of XT1 oscillation External main system clock input can be * OSCSELS = 1, EXCLKS = 0, XTSTOP = 0 disabled (MSTOP = 1). * After elapse of oscillation stabilization time External Enabling input of external clock from the External main system clock input can be subsystem clock EXCLKS pin disabled (MSTOP = 1). * OSCSELS = 1, EXCLKS = 1, XTSTOP = 0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 307 RL78/G13 CHAPTER 5 CLOCK GENERATOR Table 5-5. Changing CPU Clock (2/2) CPU Clock Before Change XT1 clock Condition Before Change Processing After Change After Change High-speed on- Oscillation of high-speed on-chip oscillator XT1 oscillation can be stopped (XTSTOP = chip oscillator and selection of high-speed on-chip 1) clock oscillator clock as main system clock * HIOSTOP = 0, MCS = 0 X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock * OSCSEL = 1, EXCLK = 0, MSTOP = 0 * After elapse of oscillation stabilization time * MCS = 1 External main Enabling input of external clock from the system clock EXCLK pin and selection of high-speed system clock as main system clock * OSCSEL = 1, EXCLK = 1, MSTOP = 0 * MCS = 1 External Transition not possible - subsystem clock External High-speed on- Oscillation of high-speed on-chip oscillator External subsystem clock input can be subsystem clock chip oscillator and selection of high-speed on-chip disabled (XTSTOP = 1). clock oscillator clock as main system clock * HIOSTOP = 0, MCS = 0 X1 clock Stabilization of X1 oscillation and selection of high-speed system clock as main system clock * OSCSEL = 1, EXCLK = 0, MSTOP = 0 * After elapse of oscillation stabilization time * MCS = 1 External main Enabling input of external clock from the system clock EXCLK pin and selection of high-speed system clock as main system clock * OSCSEL = 1, EXCLK = 1, MSTOP = 0 * MCS = 1 XT1 clock R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Transition not possible - 308 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the highspeed on-chip oscillator clock and the high-speed system clock). The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues on the pre-switchover clock for several clocks (see Table 5-5 to Table 5-7). Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of the CKC register. Whether the main system clock is operating on the high-speed system clock or high-speed on-chip oscillator clock can be ascertained using bit 5 (MCS) of the CKC register. When the CPU clock is switched, the peripheral hardware clock is also switched. Table 5-5. Maximum Time Required for System Clock Switchover Clock A Switching directions Clock B Remark fIH fMX See Table 5-6 fMAIN fSUB See Table 5-7 Table 5-6. Maximum Number of Clocks Required for fIH fMX Set Value Before Switchover Set Value After Switchover MCM0 MCM0 0 1 (f MAIN = f IH ) (f MAIN = f MX ) 0 f MX f IH 2 clock (f MAIN = f IH ) f MX <f IH 2fIH/fMX clock 1 f MX f IH 2fMX/fIH clock (f MAIN = f MX ) f MX <f IH 2 clock Table 5-7. Maximum Number of Clocks Required for fMAIN fSUB Set Value Before Switchover Set Value After Switchover CSS CSS 0 1 (f CLK = f MAIN ) (f CLK = f SUB ) 0 1 + 2fMAIN/fSUB clock (f CLK = f MAIN ) 1 3 clock (f CLK = f SUB) Remarks 1. The number of clocks listed in Table 5-6 and Table 5-7 is the number of CPU clocks before switchover. 2. Calculate the number of clocks in Table 5-6 and Table 5-7 by removing the decimal portion. <R> Example When switching the main system clock from the high-speed system clock to the high-speed onchip oscillator clock (@ oscillation with fIH = 8 MHz, fMX = 10 MHz) 2fMX/fIH = 2 (10/8) = 2.5 3 clocks R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 309 RL78/G13 CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-7. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR (External Clock Input Disabled) Register High-speed on-chip MCS = 1 or CLS = 1 oscillator clock (The CPU is operating on a clock other than the high-speed on-chip HIOSTOP = 1 oscillator clock.) X1 clock MCS = 0 or CLS = 1 External main system clock (The CPU is operating on a clock other than the high-speed system clock.) XT1 clock CLS = 0 External subsystem clock (The CPU is operating on a clock other than the subsystem clock.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 MSTOP = 1 XTSTOP = 1 310 RL78/G13 CHAPTER 5 CLOCK GENERATOR <R> 5.7 Resonator and Oscillator Constants The resonators for which the operation is verified and their oscillator constants are shown below. Cautions 1. The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. If it is necessary to optimize the oscillator characteristics in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. 2. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the RL78/G13 so that the internal operation conditions are within the specifications of the DC and AC characteristics. Figure 5-15. External Circuit Example (a) X1 oscillation VSS X1 X2 Rd (b) XT1 oscillation VSS XT2 XT1 Rd C1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 C2 C4 C3 311 RL78/G13 CHAPTER 5 CLOCK GENERATOR (1) X1 oscillation: As of October, 2011 Manufacturer Resonator Part Number SMD/ Frequency Frash Lead (MHz) operation modeNote 1 Murata Ceramic Manufacturing resonator CSTCC2M00G56-R0 SMD 2.0 CSTCR4M00G55-R0 SMD 4.0 CSTLS4M00G53-B0 Lead CSTCR4M19G55-R0 SMD CSTLS4M19G53-B0 Lead CSTCR4M91G53-R0 SMD CSTLS4M91G53-B0 Lead CSTCR5M00G53-R0 SMD CSTLS5M00G53-B0 Lead CSTCR6M00G53-R0 SMD CSTLS6M00G53-B0 Lead CSTCE8M00G52-R0 SMD CSTLS8M00G53-B0 Lead CSTCE8M38G52-R0 SMD CSTLS8M38G53-B0 Lead CSTCE10M0G52-R0 SMD CSTLS10M0G53-B0 Lead CSTCE12M0G52-R0 SMD 12.0 CSTCE16M0V53-R0 SMD 16.0 CSTLS16M0X51-B0 Lead CSTCE20M0V51-R0 SMD CSTLS20M0X51-B0 Lead LV, LS Recommended Circuit Oscillation Voltage Note 2 Range (V) Constants (reference) C1 (pF) C2 (pF) Rd (k) MIN. MAX. (47) (47) 0 1.6 5.5 (39) (39) 0 (15) (15) 0 (39) (39) 0 1.8 5.5 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (10) (10) 0 (15) (15) 0 (10) (10) 0 2.4 5.5 (15) (15) 0 (10) (10) 0 (15) (15) 0 (10) (10) 0 2.4 5.5 (15) (15) 0 (5) (5) 0 (5) (5) 0 2.7 5.5 (5) (5) 0 Co., Ltd. Nihon Dempa Kogyo Crystal resonator Co., Ltd. Notes 1. 4.194 4.915 5.0 6.0 8.0 8.388 HS 10.0 20.0 Note 3 SMD 8.0 NX5032GA Note 3 SMD 16.0 NX3225HA Note 3 SMD 20.0 NX8045GB LS HS Note 3 Set the flash operation mode by using CMODE1 and CMODE0 bits of the option byte (000C2H/010C2H). 2. Values in parentheses in the C1, C2 columns indicate an internal capacitance. 3. When using these resonators, for details about the matching, contact Nihon Dempa Kogyo Co., Ltd (http://www.ndk.com/en). Remark Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (High speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (Low speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (Low voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 312 RL78/G13 CHAPTER 5 CLOCK GENERATOR (2) XT1 oscillation: Crystal resonator As of October, 2011 Manufacturer Part Number SMD/ Frequency Lead (KHz) Load XT1 oscillation Recommended Circuit Oscillation Voltage Capacitance modeNote1 Constants Range CL (pF) Seiko SSP-T7-F Instruments Note2 SMD 32.768 SSP-T7-FL Inc. 7.0 6.0 4.4 4.4 3.7 6.0 Lead Note2 6.0 4.4 4.4 3.7 Nihon Dempa NX3215SA Kogyo Normal oscillation 11 11 0 9 9 0 9 9 0 6 5 0 6 5 0 4 4 0 Normal oscillation 9 9 0 Low power 9 9 0 6 5 0 6 5 0 4 4 0 6 7 0 6.0 Note2 VT-200-FL C1 (pF) C2 (pF) Rd (k) MIN. (V) MAX. (V) SMD 32.768 6.0 Note3 Low power consumption oscillation Ultra-low power consumption oscillation consumption oscillation Ultra-low power consumption oscillation Normal oscillation 1.6 5.5 1.6 5.5 1.6 5.5 Low power Co., Ltd. consumption oscillation Ultra-low power Note 3 consumption oscillation KYOCERA ST3215SB SMD 32.768 KINSEKI 7.0 Normal oscillation 10 10 0 Low power Corporation consumption oscillation Ultra-low power consumption oscillation Notes 1. Set the XT1 oscillation mode by using AMPHS0, AMPHS1 bits of the Clock Operation Mode Control Register (CMC). 2. When using these resonators, for details about the matching, contact Seiko Instruments Inc., Ltd (http://www.sii-crystal.com). 3. When using this resonator, for details about the matching, contact Nihon Dempa Kogyo Co., Ltd (http://www.ndk.com/en). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 313 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The number of units or channels of the timer array unit differs, depending on the product. Units Channels 20, 24, 25, 30, 32, 36, 80, 100-pin 128-pin 40, 44, 48, 52, 64-pin Unit 0 Unit 1 Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 0 - Channel 1 - Channel 2 - Channel 3 - Channel 4 - - Channel 5 - - Channel 6 - - Channel 7 - - Cautions 1. The presence or absence of timer I/O pins depends on the product. See Table 6-2 Timer I/O Pins provided in Each Product for details. 2. Most of the following descriptions in this chapter use the 128-pin products as an example. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 314 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more "channels" can be used to create a high-accuracy timer. TIMER ARRAY UNIT channel 0 16-bit timers channel 1 channel 2 channel 6 channel 7 For details about each function, see the table below. Independent channel operation function Simultaneous channel operation function * Interval timer ( refer to 6.7.1) * One-shot pulse output( refer to 6.8.1) * Square wave output ( refer to 6.7.1) * PWM output( refer to 6.8.2) * Multiple PWM output( refer to 6.8.3) * External event counter ( refer to 6.7.2) Note ( refer to 6.7.3) * Divider * Input pulse interval measurement ( refer to 6.7.4) * Measurement of high-/low-level width of input signal ( refer to 6.7.5) * Delay counter ( refer to 6.7.6) Note Only channel 0 of unit 0. It is possible to use the 16-bit timer of channels 1 and 3 of the units 0 and 1 as two 8-bit timers (higher and lower). The functions that can use channels 1 and 3 as 8-bit timers are as follows: * Interval timer/square wave output * External event counter (lower 8-bit timer only) * Delay counter (lower 8-bit timer only) Channel 7 of unit 0 can be used to realize LIN-bus communication operating in combination with UART2 of the serial array unit (30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products only). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 315 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels. (1) Interval timer Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals. Operation clock Compare operation Channel n Interrupt signal (INTTMmn) (2) Square wave output A toggle operation is performed each time INTTMmn interrupt is generated and a square wave with a duty factor of 50% is output from a timer output pin (TOmn). Operation clock Compare operation Channel n Timer output (TOmn) (3) External event counter Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid edges of a signal input to the timer input pin (TImn) has reached a specific value. Timer input (TImn) Edge detection Compare operation Interrupt signal (INTTMmn) Channel n (4) Divider function (channel 0 only) A clock input from a timer input pin (TI00) is divided and output from an output pin (TOm0). Timer input (TI00) Compare operation Channel 0 Timer output (TO00) (5) Input pulse interval measurement Counting is started by the valid edge of a pulse signal input to a timer input pin (TImn). The count value of the timer is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be measured. Timer input (TImn) Edge detection Capture operation Channel n xxH 00H Start Capture (Note, Caution, and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 316 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured. Edge detection Capture operation Timer input (TImn) Channel n 00H xxH Start Capture (7) Delay counter Counting is started at the valid edge of the signal input to the timer input pin (TImn), and an interrupt is generated after any delay period. <R> Edge detection Compare operation Timer input (TImn) Channel n Interrupt signal (INTTMmn) Start Remarks 1 n: Channel number (n = 0 to 7) 2. The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer I/O Pins provided in Each Product for details. 6.1.2 Simultaneous channel operation function By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels (timers operating according to the master channel), channels can be used for the following purposes. (1) One-shot pulse output Two channels are used as a set to generate a one-shot pulse with a specified output timing and a specified pulse width. Timer input (TImn) Edge detection Compare operation Interrupt signal (INTTMmn) Channel n (master) Compare operation Channel p (slave) Output timing Timer output (TOmp) Toggle (Master) Start (Master) Pulse width Toggle (Slave) (2) PWM (Pulse Width Modulation) output Two channels are used as a set to generate a pulse with a specified period and a specified duty factor. Operation clock Compare operation Interrupt signal (INTTMmn) Channel n (master) Compare operation Channel p (slave) Timer output (TOmp) Duty Period (Caution is listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 317 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated. Operation clock Compare operation Interrupt signal (INTTMmn) Channel n (master) Compare operation Channel p (slave) Timer output (TOmp) Duty Period Compare operation Channel q (slave) <R> Caution Remark Timer output (TOmq) Duty Period For details about the rules of simultaneous channel operation function, see 6.4.1 Basic rules of simultaneous channel operation function. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7), p, q: Slave channel number (n < p < q 7) 6.1.3 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3. Caution There are several rules for using 8-bit timer operation function. For details, see 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 318 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus communication format. (1) Detection of wakeup signal The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD2) of UART2 and the count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If the lowlevel width is greater than a specific value, it is recognized as a wakeup signal. (2) Detection of break field The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD2) of UART2 after a wakeup signal is detected, and the count value of the timer is captured at the rising edge. In this way, a low-level width is measured. If the low-level width is greater than a specific value, it is recognized as a break field. (3) Measurement of pulse width of sync field After a break field is detected, the low-level width and high-level width of the signal input to the serial data input pin (RxD2) of UART2 are measured. From the bit interval of the sync field measured in this way, a baud rate is calculated. Remark For details about setting up the operations used to implement the LIN-bus, see 6.3 (13) Input switch control register (ISC) and 6.7.5 Operation as input signal high-/low-level width measurement. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 319 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Timer/counter Configuration Timer count register mn (TCRmn) Register Timer data register mn (TDRmn) Timer input TI00 to TI07, TI10 to TI17 Timer output TO00 to TO07, TO10 to TO17 pins Control registers <Registers of unit setting block> * Peripheral enable register 0 (PER0) * Timer clock select register m (TPSm) * Timer channel enable status register m (TEm) * Timer channel start register m (TSm) * Timer channel stop register m (TTm) * Timer input select register 0 (TIS0) * Timer output enable register m (TOEm) * Timer output register m (TOm) * Timer output level register m (TOLm) * Timer output mode register m (TOMm) Note 1 , RxD2 pin (for LIN-bus) Note 1 , output controller <Registers of each channel> * Timer mode register mn (TMRmn) * Timer status register mn (TSRmn) * Input switch control register (ISC) * Noise filter enable registers 1, 2 (NFEN1, NFEN2) Note 2 * Port mode contorol register (PMCxx) Note 2 * Port mode register (PMxx) Note 2 * Port register (Pxx) Notes 1. The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer I/O Pins provided in Each Product for details. 2. The Port mode contorol register (PMCxx), port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. for details, see 6. 3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 320 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel depends on the product. Table 6-2. Timer I/O Pins provided in Each Product I/O Pins of Each Product Timer array unit 128-pin channels 100-pin 80-pin 64-pin 52-pin 44, 48-pin Channel 0 P00/TI00, P01/TO00 Channel 1 P16/TI01/TO01 Channel 2 P17/TI02/TO02 Channel 3 P31/TI03/TO03 40-pin 30, 32, 24, 25- 36-pin pin Note Note - Unit 0 P42/TI04/TO04 Channel 4 (P13) (P13) (P13) (P13) - - (P12) (P12) (P12) (P12) - - (P11) (P11) (P11) (P11) - - (P10) (P10) - - (P13) P46/TI05/TO05 P05/TI05/TO05 (P12) (P12) P102/TI06/TO06 P06/TI06/TO06 (P11) (P11) Channel 5 Channel 6 P145/TI07/TO07 P41/TI07/TO07 (P10) (P10) Channel 7 Channel 0 P64/TI10/TO10 x x x x x x x Channel 1 P65/TI11/TO11 x x x x x x x Channel 2 P66/TI12/TO12 x x x x x x x Channel 3 P67/TI13/TO13 x x x x x x x P103/TI14 Unit 1 20-pin Channel 4 /TO14 P104/TI15 Channel 5 /TO15 P105/TI16 Channel 6 /TO16 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x P106/TI17 Channel 7 /TO17 Note For 30- to 128-pin products, channel 2 and 3 can be set P15 and P14 with setting the bit 0 of the peripheral I/O redirection register (PIOR) to "1". Remarks 1. When timer input and timer output are shared by the same pin, either only timer input or only timer output can be used. 2. -: There is no timer I/O pin, but the channel is available. (However, the channel can only be used as an interval timer.) x: The channel is not available. 3. "(P1x)" indicates an alternate port when the bit 0 of the peripheral I/O redirection register (PIOR) is set to "1". Figure 6-1 shows the block diagrams of the timer array unit. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 321 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-1. Entire Configuration of Timer Array Unit 0 (Example: 64-pin products) Timer clock select register 0 (TPS0) PRS031PRS030 PRS021 PRS020 PRS013 PRS012PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 2 2 4 4 Prescaler fCLK fCLK/21, fCLK/22, fCLK/28, fCLK/210, fCLK/24,fCLK/26, fCLK/212,fCLK/214, Peripheral enable register 0 (PER0) Selector TAU0EN fCLK/20 - fCLK/215 Selector Selector Selector Slave/master controller TI00 TO00 INTTM00 (Timer interrupt) Channel 0 TO01 TI01 Channel 1 Slave/master controller INTTM01 INTTM01H TO02 TI02 Timer input select register 0 (TIS0) Channel 2 INTTM02 Channel 3 INTTM03 INTTM03H TIS2 TIS1 TIS0 TO03 TI03 TO04 TI04 Channel 4 fSUB TO05 Selector fIL TI05 INTTM04 Channel 5 INTTM05 TO06 TI06 Channel 6 INTTM06 TO07 TI07 RxD2 (Serial input pin) Remark Channel 7 (LIN-bus supported) INTTM07 fSUB: Subsystem clock frequency fIL: Low-speed on-chip oscillator clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 322 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Internal Block Diagram of Channels of Timer Array Unit 0, 2, 4, 6 <R> Master channel Slave/master controller CK01 Count clock selection CK00 Operating clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel fMCK Timer controller Output controller TO0n Output latch (Pxx) Mode selection Trigger selection Edge detection TI0n fTCLK PMxx Interrupt controller INTTM0n (Timer interrupt) Timer counter register 0n (TCR0n) Timer status register 0n (TSR0n) Timer data register 0n (TDR0n) Slave/master controller Overflow OVF 0n Note CKS0n CCS0n MAS STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Channel n Timer mode register 0n (TMR0n) Note n = 2, 4, 6 only Remark n = 0, 2, 4, 6 <R> Figure 6-3. Internal Block Diagram of Channels of Timer Array Unit 1 Slave channel Slave/master controller TI01 Count clock selection fMCK Edge detection fTCLK Trigger selection CK00 CK01 CK02 CK03 Operating clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel Timer controller Mode selection Output controller Interrupt controller TO01 Output latch (Pxx) PMxx INTTM01 (Timer interrupt) Timer counter register 01 (TCR01) Timer status register 01 (TSR01) Timer data register 01 (TDR01) Slave/master controller 8-bit timer controller Mode selection CKS01 CCS01 Channel 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Overflow OVF 01 Interrupt controller INTTM01H (Timer interrupt) SPLIT STS012 STS011 STS010 CIS011 CIS010 MD013 MD012 MD011 MD010 01 Timer mode register 01 (TMR01) 323 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-4. Internal Block Diagram of Channels of Timer Array Unit 3 <R> Slave channel Slave/master controller Operating clock selection CK00 CK01 CK02 CK03 Count clock selection Trigger signal to master channel Clock signal to master channel Interrupt signal to master channel fMCK Timer controller Output controller Mode selection Trigger selection Edge detection TI03 fTCLK TO03 Output latch (Pxx) Interrupt controller PMxx INTTM03 (Timer interrupt) Timer counter register 03 (TCR03) Timer status register 03 (TSR03) Timer data register 03 (TDR03) Slave/master controller Overflow 8-bit timer controller Mode selection CKS03 CCS03 OVF 03 Interrupt controller INTTM03H (Timer interrupt) SPLIT STS032 STS031 STS030 CIS031 CIS030 MD033 MD032 MD031 MD030 03 Channel 3 Timer mode register 03 (TMR03) Figure 6-5. Internal Block Diagram of Channels of Timer Array Unit 5 <R> Slave channel Slave/master controller Timer input select register 0 (TIS0) fIL TI05 fMCK Edge detection TIS1 TIS0 fTCLK Timer controller Mode selection Output controller Interrupt controller TO05 Output latch (Pxx) PMxx INTTM05 (Timer interrupt) Timer counter register 05 (TCR05) Timer status register 05 (TSR05) Selector TIS2 Count clock selection CK01 Trigger selection CK00 Operating clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel Slave/master controller Timer data register 05 (TDR05) Overflow OVF 05 CKS05 CCS05 STS052 STS051 STS050 CIS051 CIS050 MD053 MD052 MD051 MD050 Channel 5 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Timer mode register 05 (TMR05) 324 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-6. Internal Block Diagram of Channels of Timer Array Unit 7 <R> Slave channel Slave/master controller Operating clock selection CK00 RxD2 fMCK Edge detection fTCLK Output controller Timer controller Mode selection Trigger selection TI07 Selector CK01 Count clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel TO07 Output latch (Pxx) Interrupt controller PMxx INTTM07 (Timer interrupt) Timer counter register 07 (TCR07) ISC1 Timer status register 07 (TSR07) Input switch control register (ISC) Timer data register 07 (TDR07) Slave/master controller Overflow OVF 07 CKS07 CCS07 STS072 STS071 STS070 CIS071 CIS070 MD073 MD072 MD071 MD070 Timer mode register 07 (TMR07) Channel 7 (1) Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn) (refer to 6.3 (3) Timer mode register mn (TMRmn)). Figure 6-7. Format of Timer Count Register mn (TCRmn) Address: F0180H, F0181H (TCR00) to F018EH, F018FH (TCR07), After reset: FFFFH R F01C0H, F01C1H (TCR10) to F01CEH, F01CFH (TCR17) F0181H (TCR00) 15 14 13 12 11 F0180H (TCR00) 10 9 8 7 6 5 4 3 2 1 0 TCRmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 325 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT The count value can be read by reading timer count register mn (TCRmn). The count value is set to FFFFH in the following cases. * When the reset signal is generated * When the TAUmEN bit of peripheral enable register 0 (PER0) is cleared * When counting of the slave channel has been completed in the PWM output mode * When counting of the slave channel has been completed in the delay count mode * When counting of the master/slave channel has been completed in the one-shot pulse output mode * When counting of the slave channel has been completed in the multiple PWM output mode The count value is cleared to 0000H in the following cases. * When the start trigger is input in the capture mode * When capturing has been completed in the capture mode Caution The count value is not captured to timer data register mn (TDRmn) even when the TCRmn register is read. The TCRmn register read value differs as follows according to operation mode changes and the operating status. Table 6-3. Timer Count Register mn (TCRmn) Read Value in Various Operation Modes Operation Mode Count Mode <R> Timer count register mn (TCRmn) Read Value Note Value if the operation mode was changed after releasing reset Value if the Operation was restarted after count operation paused (TTmn = 1) Value if the operation mode was changed after count operation paused (TTmn = 1) Value when waiting for a start trigger after one count Interval timer mode Count down FFFFH Value if stop Undefined - Capture mode Count up 0000H Value if stop Undefined - Event counter mode Count down FFFFH Value if stop Undefined - One-count mode Count down FFFFH Value if stop Undefined FFFFH Capture & onecount mode Count up 0000H Value if stop Undefined Capture value of TDRmn register + 1 Note This indicates the value read from the TCRmn register when channel n has stopped operating as a timer (TEmn = 0) and has been enabled to operate as a counter (TSmn = 1). The read value is held in the TCRmn register until the count operation starts. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 326 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn). The value of the TDRmn register can be changed at any time. This register can be read or written in 16-bit units. In addition, for the TDRm1 and TDRm3 registers, while in the 8-bit timer mode (when the SPLIT bits of timer mode registers 01 and 03 (TMRm1, TMRm3) are 1), it is possible to rewrite the data in 8-bit units, with TDRm1H and TDRm3H used as the higher 8 bits, and TDRm1L and TDRm3L used as the lower 8 bits. However, reading is only possible in 16-bit units. Reset signal generation clears this register to 0000H. Figure 6-8. Format of Timer Data Register mn (TDRmn) (n = 0, 2, 4 to 7) Address: FFF18H, FFF19H (TDR00), FFF64H, FFF65H (TDR02), After reset: 0000H R/W FFF68H, FFF69H (TDR04) to FFF6EH, FFF6FH (TDR07), FFF70H, FFF71H (TDR10), FFF74H, FFF75H (TDR12), FFF78H, FFF79H (TDR14) to FFF7EH, FFF7FH (TDR17) FFF19H (TDR00) 15 14 13 12 11 10 9 8 FFF18H (TDR00) 7 6 5 4 3 2 1 0 2 1 0 TDRmn Figure 6-9. Format of Timer Data Register mn (TDRmn) (n = 1, 3) Address: FFF1AH, FFF1BH (TDR01), FFF66H, FFF67H (TDR03), After reset: 0000H R/W FFF72H, FFF73H (TDR11), FFF76H, FFF77H (TDR13), FFF1BH (TDR01H) 15 14 13 12 11 10 FFF1AH (TDR01L) 9 8 7 6 5 4 3 TDRmn (i) When timer data register mn (TDRmn) is used as compare register Counting down is started from the value set to the TDRmn register. When the count value reaches 0000H, an interrupt signal (INTTMmn) is generated. The TDRmn register holds its value until it is rewritten. Caution The TDRmn register does not perform a capture operation even if a capture trigger is input, when it is set to the compare function. (ii) When timer data register mn (TDRmn) is used as capture register The count value of timer count register mn (TCRmn) is captured to the TDRmn register when the capture trigger is input. A valid edge of the TImn pin can be selected as the capture trigger. This selection is made by timer mode register mn (TMRmn). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 327 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. * Peripheral enable register 0 (PER0) * Timer clock select register m (TPSm) * Timer mode register mn (TMRmn) * Timer status register mn (TSRmn) * Timer channel enable status register m (TEm) * Timer channel start register m (TSm) * Timer channel stop register m (TTm) * Timer input select register 0 (TIS0) * Timer output enable register m (TOEm) * Timer output register m (TOm) * Timer output level register m (TOLm) * Timer output mode register m (TOMm) * Input switch control register (ISC) * Noise filter enable registers 1, 2 (NFEN1, NFEN2) * Port mode contorol register (PMCxx) * Port mode register (PMxx) * Port register (Pxx) Note Note Note Note The port mode registers (PMxx) and port registers (Pxx) to be set differ depending on the product. For details, see 6. 3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 328 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (1) Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1. When the timer array unit 1 is used, be sure to set bit 1 (TAU1EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-10. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H Symbol PER0 After reset: 00H <7> R/W <6> IICA1EN RTCEN <5> Note 1 ADCEN TAU1EN <4> IICA0EN <3> Note 2 SAU1EN <2> Note 3 SAU0EN <1> TAU1EN <0> Note 1 TAU0EN Control of timer array unit 1 input clock Stops supply of input clock. 0 * SFR used by the timer array unit 1 cannot be written. * The timer array unit 1 is in the reset status. Supplies input clock. 1 * SFR used by the timer array unit 1 can be read/written. TAU0EN 0 Control of timer array 0 unit input clock Stops supply of input clock. * SFR used by the timer array unit 0 cannot be written. * The timer array unit 0 is in the reset status. 1 Supplies input clock. * SFR used by the timer array unit 0 can be read/written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Cautions 1. When setting the timer array unit, be sure to set the TAUmEN bit to 1 first. If TAUmEN = 0, writing to a control register of timer array unit is ignored, and all read values are default values (except for the timer input select register 0 (TIS0), input switch control register <R> (ISC), noise filter enable register 1, 2 (NFEN1, NFEN2), port modecontorol registers 0, 3, 14 (PMC0, PMC3, PMC14), port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14), and port registers 0, 1, 3, 4, 6, 10, 14 (P0, P1, P3, P4, P6, P10, P14)). 2. Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 329 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel from external prescaler. CKm1 is selected by using bits 7 to 4 of the TPSm register, and CKm0 is selected by using bits 3 to 0. In addition, for channel 1 and 3, CKm2 is selected by using bits 9 and 8 of the TPSm register, and CKm3 is selected by using bits 13 and 12. Rewriting of the TPSm register during timer operation is possible only in the following cases. If the PRSm00 to PRSm03 bits can be rewritten (n = 0 to 7): All channels for which CKm0 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 0) are stopped (TEmn = 0). If the PRSm10 to PRSm13 bits can be rewritten (n = 0 to 7): All channels for which CKm1 is selected as the operation clock (CKSmn1, CKSmn0 = 0, 1) are stopped (TEmn = 0). If the PRSm20 and PRSm21 bits can be rewritten (n = 1, 3): All channels for which CKm2 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 0) are stopped (TEmn = 0). If the PRSm30 and PRSm31 bits can be rewritten (n = 1, 3): All channels for which CKm3 is selected as the operation clock (CKSmn1, CKSmn0 = 1, 1) are stopped (TEmn = 0). The TPSm register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 330 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Clock Select register m (TPSm) (1/2) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPSm 0 0 PRS PRS 0 0 PRS PRS PRS PRS PRS PRS PRS PRS PRS PRS m31 m30 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 Note (k = 0, 1) PRS PRS PRS mk3 mk2 mk1 mk0 0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 32 MHz 0 0 0 1 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz 16 MHz 0 0 1 0 fCLK/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz 8 MHz fCLK/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz 4 MHz fCLK/2 4 125 kHz 312.5 kHz 625 kHz 1.25 MHz 2 MHz fCLK/2 5 62.5 kHz 156.2 kHz 312.5 kHz 625 kHz 1 MHz fCLK/2 6 31.25 kHz 78.1 kHz 156.2 kHz 312.5 kHz 500 kHz fCLK/2 7 15.62 kHz 39.1 kHz 78.1 kHz 156.2 kHz 250 kHz 0 0 1 0 1 0 1 0 1 1 0 0 1 1 1 0 1 0 1 fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz 1 0 0 0 fCLK/2 8 7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 125 kHz 1 0 0 1 fCLK/2 9 3.91 kHz 9.76 kHz 19.5 kHz 39.1 kHz 62.5 kHz fCLK/2 10 1.95 kHz 4.88 kHz 9.76 kHz 19.5 kHz 31.25 kHz fCLK/2 11 976 Hz 2.44 kHz 4.88 kHz 9.76 kHz 15.63 kHz fCLK/2 12 488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 7.81 kHz fCLK/2 13 244 Hz 610 Hz 1.22 kHz 2.44 kHz 3.91 kHz fCLK/2 14 122 Hz 305 Hz 610 Hz 1.22 kHz 1.95 kHz fCLK/2 15 61 Hz 153 Hz 305 Hz 610 Hz 976 Hz 1 0 1 0 1 1 1 1 1 1 1 Note Selection of operation clock (CKmk) PRS 0 <R> After reset: 0000H 1 1 1 0 0 1 1 0 1 0 1 0 1 When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), stop timer array unit (TTm = 00FFH). Cautions 1. <R> 2. Be sure to clear bits 15, 14, 11, 10 to "0". If fCLK (undivided) is selected as the operation clock (CKmk) and TDRnm is set to 0000H (n = 0 or 1, m = 0 to 7), interrupt requests output from timer array units are not detected. Remarks 1. fCLK: CPU/peripheral hardware clock frequency <R> 2. Waveform of the clock to be selected in the TPSm register which becomes high level for one period of fCLK from its rising edge (m = 1 to 15). For details, see 6.5.1 Count clock (fTCLK). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 331 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-11. Format of Timer Clock Select register m (TPSm) (2/2) Address: F01B6H, F01B7H (TPS0), F01F6H, F01F7H (TPS1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPSm 0 0 PRS PRS 0 0 PRS PRS PRS PRS PRS PRS PRS PRS PRS PRS m31 m30 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 PRS m21 m20 0 0 fCLK/2 0 1 fCLK/2 2 1 0 fCLK/2 fCLK/2 1 1 PRS PRS m31 m30 0 Note Selection of operation clock (CKm2) PRS 0 Note fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz 1 MHz 2.5 MHz 5 MHz 10 MHz 16 MHz 500 kHz 1.25 MHz 2.5 MHz 5 MHz 8 MHz 4 125 kHz 312.5 kHz 625 MHz 1.25 MHz 2 MHz 6 31.25 kHZ 78.1 kHz 156.2 kHz 312.5 kHz 500 kHZ Selection of operation clock (CKm3) Note fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz fCLK/2 8 7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 125 kHz 0 1 fCLK/2 10 1.95 kHz 4.88 kHz 9.76 kHz 19.5 kHz 31.25 kHz 1 0 fCLK/2 12 488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 7.81 kHz 1 1 fCLK/2 14 122 HZ 305 Hz 610 Hz 1.22 kHz 1.95 kHZ When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), stop timer array unit (TTm = 00FFH). The timer array unit must also be stopped if the operating clock (fMCK) specified by using the CKSmn0, and CKSmn1 bits or the valid edge of the signal input from the TImn pin is selected as the count clock (fTCLK). Caution Be sure to clear bits 15, 14, 11, 10 to "0". By using channels 1 and 3 in the 8-bit timer mode and specifying CKm2 or CKm3 as the operation clock, the interval times shown in Table 6-4 can be achieved by using the interval timer function. Table 6-4. Interval Times Available for Operation Clock CKSm2 or CKSm3 Interval time Clock CKm2 CKm3 Note (fCLK = 32 MHz) 10 s 100 s 1 ms - - - fCLK/2 2 - - - fCLK/2 4 - - fCLK/2 6 - - fCLK/2 8 - - fCLK/2 10 - - fCLK/2 12 - - fCLK/2 14 - - fCLK/2 10 ms Note The margin is within 5 %. Remarks 1. fCLK: CPU/peripheral hardware clock frequency 2. For details of asignal of fCLK/2j selected with the TPSm register, see 6.5.1 Count clock (fTCLK). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 332 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (3) Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (fMCK), select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count). Rewriting the TMRmn register is prohibited when the register is in operation (when TEmn = 1). However, bits 7 and 6 (CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEmn = 1) (for details, see 6.7 Independent Channel Operation Function of Timer Array Unit and 6.8 Simultaneous Channel Operation Function of Timer Array Unit. The TMRmn register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Caution The bits mounted depend on the channels in the bit 11 of TMRmn register. TMRm2, TMRm4, TMRm6: MASTERmn bit (n = 2, 4, 6) TMRm1, TMRm3: SPLITmn bit (n = 1, 3) TMRm0, TMRm5, TMRm7: Fixed to 0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 333 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT <R> Figure 6-12. Format of Timer Mode Register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol 15 14 13 12 11 10 9 8 TMRmn CKS CKS 0 CCS MAST STS STS STS (n = 2, 4, 6 ) mn1 mn0 mn ERmn mn2 mn1 mn0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMRmn CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) mn1 mn0 mn mn mn2 mn1 mn0 mn1 mn0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 mn2 mn1 mn0 mn1 mn0 13 6 5 4 CIS CIS 0 0 mn1 mn0 TMRmn CKS CKS (n = 0, 5, 7) mn1 mn0 CKS CKS mn1 mn0 0 0 Operation clock CKm0 set by timer clock select register m (TPSm) 0 1 Operation clock CKm2 set by timer clock select register m (TPSm) 1 0 Operation clock CKm1 set by timer clock select register m (TPSm) 1 1 Operation clock CKm3 set by timer clock select register m (TPSm) 0 CCS Note 7 mn 0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 Selection of operation clock (fMCK) of channel n Operation clock (fMCK ) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated depending on the setting of the CCSmn bit. The operation clocks CKm2 and CKm3 can only be selected for channels 1 and 3. CCS Selection of count clock (fTCLK) of channel n mn 0 Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits 1 Valid edge of input signal input from the TImn pin In channel 5, Valid edge of input signal selected by TIS0 <R> Count clock (fTCLK) is used for the timer/counter, output controller, and interrupt controller. <R> Note Bit 11 is fixed at 0 of read only, write is ignored. Cautions 1. Be sure to clear bits 13, 5, and 4 to "0". 2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for fCLK is changed (by changing the value of the system clock control register (CKC)), even if the operating clock specified by using the CKSmn0 and CKSmn1 bits (fMCK) or the valid edge of the signal input from the TImn pin is selected as the count clock (fTCLK). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 334 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12. Format of Timer Mode Register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol 15 14 13 12 11 10 9 8 TMRmn CKS CKS 0 CCS MAST STS STS STS (n = 2, 4, 6 ) mn1 mn0 mn ERmn mn2 mn1 mn0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMRmn CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) mn1 mn0 mn mn mn2 mn1 mn0 mn1 mn0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 mn2 mn1 mn0 mn1 mn0 TMRmn CKS CKS (n = 0, 5, 7) mn1 mn0 13 0 CCS 0 Note mn 7 6 5 4 CIS CIS 0 0 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 (Bit 11 of TMRmn (n = 2, 4, 6)) MAS Selection between using channel n independently or TER simultaneously with another channel(as a slave or master) mn Operates in independent channel operation function or as slave channel in simultaneous channel operation 0 function. 1 Operates as master channel in simultaneous channel operation function. Only the channel 2, 4, 6 can be set as a master channel (MASTERmn = 1). Be sure to use channel 0, 5, 7 are fixed to 0 (Regardless of the bit setting, channel 0 operates as master, because it is the highest channel). Clear the MASTERmn bit to 0 for a channel that is used with the independent channel operation function. (Bit 11 of TMRmn (n = 1, 3)) SPLI Selection of 8 or 16-bit timer operation for channels 1 and 3 Tmn 0 Operates as 16-bit timer. (Operates in independent channel operation function or as slave channel in simultaneous channel operation function.) 1 Operates as 8-bit timer. STS STS STS mn2 mn1 mn0 0 0 0 Only software trigger start is valid (other trigger sources are unselected). 0 0 1 Valid edge of the TImn pin input is used as both the start trigger and capture trigger. 0 1 0 Both the edges of the TImn pin input are used as a start trigger and a capture trigger. 1 0 0 Interrupt signal of the master channel is used (when the channel is used as a slave channel Setting of start trigger or capture trigger of channel n with the simultaneous channel operation function). Other than above <R> Setting prohibited Note Bit 11 is fixed at 0 of read only, write is ignored. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 335 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12. Format of Timer Mode Register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol 15 14 13 12 11 10 9 8 TMRmn CKS CKS 0 CCS MAST STS STS STS (n = 2, 4, 6 ) mn1 mn0 mn ERmn mn2 mn1 mn0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMRmn CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) mn1 mn0 mn mn mn2 mn1 mn0 mn1 mn0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 mn2 mn1 mn0 mn1 mn0 TMRmn CKS CKS (n = 0, 5, 7) mn1 mn0 13 0 CCS 0 Note mn 7 6 5 4 CIS CIS 0 0 mn1 mn0 CIS CIS mn1 mn0 0 0 Falling edge 0 1 Rising edge 1 0 Both edges (when low-level width is measured) 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 Selection of TImn pin input valid edge Start trigger: Falling edge, Capture trigger: Rising edge 1 1 Both edges (when high-level width is measured) Start trigger: Rising edge, Capture trigger: Falling edge If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B, set the CISmn1 to CISmn0 bits to 10B. <R> MD MD MD mn3 mn2 mn1 0 0 0 Operation mode of channel n Corresponding function Count operation of TCR Interval timer mode Interval timer / Square wave Counting down output / Divider function / PWM output (master) 0 1 0 Capture mode Input pulse interval Counting up measurement 0 1 1 Event counter mode External event counter Counting down 1 0 0 One-count mode Delay counter / One-shot pulse Counting down output / PWM output (slave) 1 1 0 Capture & one-count mode Measurement of high-/low-level Counting up width of input signal Other than above <R> <R> Setting prohibited The operation of each mode varies depending on MDmn0 bit (see next table). Note Bit 11 is fixed at 0 of read only, write is ignored. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 336 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-12. Format of Timer Mode Register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W F01D0H, F01D1H (TMR10) to F01DEH, F01DFH (TMR17) Symbol 15 14 13 12 11 10 9 8 TMRmn CKS CKS 0 CCS MAST STS STS STS (n = 2, 4, 6 ) mn1 mn0 mn ERmn mn2 mn1 mn0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMRmn CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) mn1 mn0 mn mn mn2 mn1 mn0 mn1 mn0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 mn2 mn1 mn0 mn1 mn0 TMRmn CKS CKS (n = 0, 5, 7) mn1 mn0 13 CCS 0 0 Note 1 mn Operation mode MD (Value set by the MDmn3 to MDmn1 bits mn0 7 6 5 4 CIS CIS 0 0 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 3 2 1 0 MD MD MD MD mn3 mn2 mn1 mn0 Setting of starting counting and interrupt (see table above)) * Interval timer mode 0 Timer interrupt is not generated when counting is started (timer output does not change, either). (0, 0, 0) * Capture mode 1 (0, 1, 0) Timer interrupt is generated when counting is started (timer output also changes). * Event counter mode 0 Timer interrupt is not generated when counting is started (timer output does not change, either). (0, 1, 1) * One-count mode Note 2 0 Start trigger is invalid during counting operation. At that time, interrupt is not generated, either. (1, 0, 0) 1 Note 3 Start trigger is valid during counting operation . At that time, interrupt is also generated. * Capture & one-count mode 0 Timer interrupt is not generated when counting is started (timer output does not change, either). (1, 1, 0) Start trigger is invalid during counting operation. At that time interrupt is not generated, either. Other than above <R> Notes 1. Setting prohibited Bit 11 is fixed at 0 of read only, write is ignored. 2. In one-count mode, interrupt output (INTTMmn) when starting a count operation and TOmn output are not controlled. 3. If the start trigger (TSmn = 1) is issued during operation, the counter is initialaized, an interrupt is generated, and recounting is started (does not occur the interrupt request). <R> Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 337 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (4) Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B). See Table 6-5 for the operation of the OVF bit in each operation mode and set/clear conditions. The TSRmn register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the TSRmn register can be set with an 8-bit memory manipulation instruction with TSRmnL. Reset signal generation clears this register to 0000H. Figure 6-13. Format of Timer Status Register mn (TSRmn) Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07), After reset: 0000H R F01E0H, F01E1H (TSR10) to F01EEH, F01EFH (TSR17) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF OVF Counter overflow status of channel n 0 Overflow does not occur. 1 Overflow occurs. When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) Table 6-5. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode Timer operation mode OVF bit Set/clear conditions * Capture mode clear When no overflow has occurred upon capturing * Capture & one-count mode set When an overflow has occurred upon capturing * Interval timer mode clear * Event counter mode * One-count mode Remark set - (Use prohibited) The OVF bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 338 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (5) Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0. The TEm register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the TEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL. Reset signal generation clears this register to 0000H. Figure 6-14. Format of Timer Channel Enable Status register m (TEm) Address: F01B0H, F01B1H (TE0), F01F0H, F01F1H (TE1) After reset: 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEm 0 0 0 0 TEHm 0 TEHm 0 TEm TEm TEm TEm TEm TEm TEm TEm 7 6 5 4 3 2 1 0 3 1 TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit 03 timer mode 0 Operation is stopped. 1 Operation is enabled. TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit 01 timer mode 0 Operation is stopped. 1 Operation is enabled. TEmn Indication of operation enable/stop status of channel n 0 Operation is stopped. 1 Operation is enabled. This bit displays whether operation of the lower 8-bit timer for TEm1 and TEm3 is enabled or stopped when channel 1 or 3 is in the 8-bit timer mode. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 339 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (6) Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1. The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 = 1), because they are trigger bits. The TSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TSm register can be set with a 1-bit or 8-bit memory manipulation instruction with TSmL. Reset signal generation clears this register to 0000H. Figure 6-15. Format of Timer Channel Start register m (TSm) Address: F01B2H, F01B3H (TS0), F01F2H, F01F3H (TS1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSm 0 0 0 0 TSHm 0 TSHm 0 TSm TSm TSm TSm TSm TSm TSm TSm 7 6 5 4 3 2 1 0 3 1 TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode m3 0 No trigger operation 1 The TEHm3 bit is set to 1 and the count operation becomes enabled. The TCRm3 register count operation start in the interval timer mode in the count operation enabled state (see Table 6-6 in 6.5.2 Start timing of counter). TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode m1 0 No trigger operation 1 The TEHm1 bit is set to 1 and the count operation becomes enabled. The TCRm1 register count operation start in the interval timer mode in the count operation enabled state (see Table 6-6 in 6.5.2 Start timing of counter). TSm Operation enable (start) trigger of channel n n 0 No trigger operation 1 The TEmn bit is set to 1 and the count operation becomes enabled. The TCRmn register count operation start in the count operation enabled state varies depending on each operation mode (see Table 6-6 in 6.5.2 Start timing of counter). This bit is the trigger to enable operation (start operation) of the lower 8-bit timer for TSm1 and TSm3 when channel 1 or 3 is in the 8-bit timer mode. Cautions 1. Be sure to clear bits 15 to 12, 10, 8 to "0" 2. When switching from a function that does not use TImn pin input to one that does, the following wait period is required from when timer mode register mn (TMRmn) is set until the TSmn (TSHm1, TSHm3) bit is set to 1. When the TImn pin noise filter is enabled (TNFENnm = 1): Four cycles of the operation clock (fMCK) When the TImn pin noise filter is disabled (TNFENnm = 0): Two cycles of the operation clock (fMCK) Remarks 1. When the TSm register is read, 0 is always read. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 340 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (7) Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TTHm1, TTHm3 = 0), because they are trigger bits. The TTm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL. Reset signal generation clears this register to 0000H. Figure 6-16. Format of Timer Channel Stop register m (TTm) Address: F01B4H, F01B5H After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTm 0 0 0 0 TTHm 0 TTHm 0 TTm TTm TTm TTm TTm TTm TTm TTm 7 6 5 4 3 2 1 0 3 TTH 1 Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode m3 0 No trigger operation 1 Operation is stopped (stop trigger is generated). TTH Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode m1 0 No trigger operation 1 Operation is stopped (stop trigger is generated). TTm Operation stop trigger of channel n n 0 No trigger operation 1 TEmn bit clear to 0, to be count operation stop enable status. This bit is the trigger to stop operation of the lower 8-bit timer for TTm1 and TTm3 when channel 1 or 3 is in the 8-bit timer mode. Caution Be sure to clear bits 15 to 12, 10, 8 of the TTm register to "0". Remarks 1. 2. When the TTm register is read, 0 is always read. m: Unit number (m = 0, 1),n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 341 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (8) Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 5 of unit 0 timer input.. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-17. Format of Timer Input Select register 0 (TIS0) Address: F0074H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 0 0 TIS02 TIS01 TIS00 TIS02 TIS01 TIS00 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Low-speed on-chip oscillator clock (fIL) 1 0 1 Subsystem clock (fSUB) Other than above <R> Caution Selection of timer input used with channel 5 Input signal of timer input pin (TI05) Setting prohibited High-level width, low-level width of timer input is selected, will require more than 1/fMCK +10 ns. Therefore, when selecting fSUB to fCLK (CSS bit of CKS register = 1), can not TIS02 bit set to 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 342 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (9) Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn). The TOEm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TOEmL. Reset signal generation clears this register to 0000H. Figure 6-18. Format of Timer Output Enable register m (TOEm) Address: F01BAH, F01BBH (TOE0), F01FAH, F01FBH (TOE1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOEm 0 0 0 0 0 0 0 0 TOE TOE TOE TOE TOE TOE TOE TOE m7 m6 m5 m4 m3 m2 m1 m0 TOE Timer output enable/disable of channel n mn <R> 0 Diseble output of timer. Without reflecting on TOmn bit timer operation, to fixed the output. Writing to the TOmn bit is enabled. 1 Enable output of timer. Reflected in the TOmn bit timer operation, to generate the output waveform. Writing to the TOmn bit is disabled (writing is ignored). Caution Be sure to clear bits 15 to 8 to "0". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 343 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (10) Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel. The TOmn bit oh this register can be rewritten by software only when timer output is disabled (TOEmn = 0). When timer output is enabled (TOEmn = 1), rewriting this register by software is ignored, and the value is changed only by the timer operation. To use the P00/TI00, P46/TI05/TO05, P01/TO00, P102/TI06/TO06, P16/TI01/TO01, P145/TI07/TO07, P17/TI02/TO02, P64/TI10/TO10, P31/TI03/TO03, P42/TI04/TO04, P65/TI11/TO11, P66/TI12/TO12, P67/TI13/TO13, P103/TI14/TO14, P104/TI15/TO15, P105/TI16/TO16, or P106/TI17/TO17 pin as a port function pin, set the corresponding TOmn bit to "0". The TOm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOm register can be set with an 8-bit memory manipulation instruction with TOmL. Reset signal generation clears this register to 0000H. Figure 6-19. Format of Timer Output register m (TOm) Address: F01B8H, F01B9H (TO0), F01F8H, F01F9H (TO1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOm 0 0 0 0 0 0 0 0 TOm TOm TOm TOm TOm TOm TOm TOm 7 6 5 4 3 2 1 0 TOm Timer output of channel n n 0 Timer output value is "0". 1 Timer output value is "1". Caution Be sure to clear bits 15 to 8 to "0". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 344 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (11) Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In the master channel output mode (TOMmn = 0), this register setting is invalid. The TOLm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL. Reset signal generation clears this register to 0000H. Figure 6-20. Format of Timer Output Level register m (TOLm) Address: F01BCH, F01BDH (TOL0), F01FCH, F01FDH (TOL1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOLm 0 0 0 0 0 0 0 0 TOL TOL TOL TOL TOL TOL TOL 0 m7 m6 m5 m4 m3 m2 m1 TOL Control of timer output level of channel n mn 0 Positive logic output (active-high) 1 Negative logic output (active-low) Caution Be sure to clear bits 15 to 8, and 0 to "0". Remarks 1. If the value of this register is rewritten during timer operation, the timer output logic is inverted when the timer output signal changes next, instead of immediately after the register value is rewritten. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 345 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (12) Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0. When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave channel to 1. The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset while the timer output is enabled (TOEmn = 1). The TOMm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOMm register can be set with an 8-bit memory manipulation instruction with TOMmL. Reset signal generation clears this register to 0000H. Figure 6-21. Format of Timer Output Mode register m (TOMm) Address: F01BEH, F01BFH (TOM0), F01FEH, F01FFH (TOM1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOMm 0 0 0 0 0 0 0 0 TOM TOM TOM TOM TOM TOM TOM 0 m7 m6 m5 m4 m3 m2 m1 TOM Control of timer output mode of channel n mn 0 Master channel output mode (to produce toggle output by timer interrupt request signal (INTTMmn)) 1 Slave channel output mode (output is set by the timer interrupt request signal (INTTMmn) of the master channel, and reset by the timer interrupt request signal (INTTM0p) of the slave channel) Caution Be sure to clear bits 15 to 8, and 0 to "0". Remark m: Unit number (m = 0, 1) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n<p7 (For details of the relation between the master channel and slave channel, refer to 6.4.1 Basic rules of simultaneous channel operation function.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 346 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (13) Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using channel 7 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input pin (RxD2) is selected as a timer input signal. The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-22. Format of Input Switch Control Register (ISC) Address: F0073H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 0 Switching channel 7 input of timer array unit 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products: Uses the input signal of the TI07 pin as a timer input (normal operation). 20, 24, 25-pin products: Do not use a timer input signal for channel 7. 1 Input signal of the RXD2 pin is used as timer input (detects the wakeup signal and measures the low width of the break field and the pulse width of the sync field). Setting is prohibited in the 20, 24, and 25-pin products. ISC0 Caution Switching external interrupt (INTP0) input 0 Uses the input signal of the INTP0 pin as an external interrupt (normal operation). 1 Uses the input signal of the RXD2 pin as an external interrupt (wakeup signal detection). Be sure to clear bits 7 to 2 to "0". Remark When the LIN-bus communication function is used, select the input signal of the RxD2 pin by setting ISC1 to 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 347 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (14) Noise filter enable registers 1, 2 (NFEN1, NFEN2) The NFEN1, NFEN2 registers is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the CPU/peripheral hardware clock (fMCK). When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware clock (fMCK) Note. The NFEN1, NFEN2 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Note For details, see 6.5.1 (2) When valid edge of input signal input from the TImn pin is selected (CCSmn = 1) and 6.5.2 Start timing of counter. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 348 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-23. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (1/2) Address: F0071H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 Address: F0072H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10 TNFEN07 Enable/disable using noise filter of TI07/TO07/P145 pin or RxD2/P14 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN06 Enable/disable using noise filter of TI06/TO06/P102 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN05 Enable/disable using noise filter of TI05/TO05/P46 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN04 Enable/disable using noise filter of TI04/TO04/P04 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN03 Enable/disable using noise filter of TI03/TO03/P31 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN02 Enable/disable using noise filter of TI02/TO02/P17 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN01 Enable/disable using noise filter of TI01/P01/P16 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN00 Note Note Enable/disable using noise filter of TI00/P00 pin input signal 0 Noise filter OFF 1 Noise filter ON The applicable pin can be switched by setting the ISC1 bit of the ISC register. ISC1 = 0: Whether or not to use the noise filter of the TI07 pin can be selected. ISC1 = 1: Whether or not to use the noise filter of the RxD2 pin can be selected. Remark The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer I/O Pins provided in Each Product for details. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 349 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-23. Format of Noise Filter Enable Registers 1, 2 (NFEN1, NFEN2) (2/2) Address: F0071H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 Address: F0072H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 NFEN2 TNFEN17 TNFEN16 TNFEN15 TNFEN14 TNFEN13 TNFEN12 TNFEN11 TNFEN10 TNFEN17 Enable/disable using noise filter of TI17/TO17/P106 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN16 Enable/disable using noise filter of TI16/TO16/P105 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN15 Enable/disable using noise filter of TI15/TO15/P104 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN14 Enable/disable using noise filter of TI14/TO14/P103 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN13 Enable/disable using noise filter of TI13/TO13/P67 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN12 Enable/disable using noise filter of TI12/TO12/P66 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN11 Enable/disable using noise filter of TI11/P11/P65 pin input signal 0 Noise filter OFF 1 Noise filter ON TNFEN10 Remark Enable/disable using noise filter of TI00/P64 pin input signal 0 Noise filter OFF 1 Noise filter ON The presence or absence of timer I/O pins of channel 0 to 7 depends on the product. See Table 6-2 Timer I/O Pins provided in Each Product for details. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 350 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14) These registers set input/output of ports 0, 1, 3, 4, 6, 10, 14 in 1-bit units. The presence or absence of timer I/O pins depends on the product. When using the timer array unit, set the following port mode registers according to the product used. 20, 24, 25, 30, 32, 36, and 40-pin products: PM0, PM1, PM3 44, 48, 52, and 64-pin products: PM0, PM1, PM3, PM4 80-pin products: PM0, PM1, PM3, PM4, PM6 100 and 128-pin products: PM0, PM1, PM3, PM4, PM6, PM10, PM14 When using the ports (such as P01/TO00 and P17/TO02/TI02) to be shared with the timer output pin for timer <R> output, set the port mode control register (PMCxx) bit, port mode register (PMxx) bit and port register (Pxx) bit corresponding to each port to 0. Example: When using P17/TO02/TI02 for timer output <R> Set the PMC17 bit of port mode contorol register 1 to 0. Set the PM17 bit of port mode register 1 to 0. Set the P17 bit of port register 1 to 0. When using the ports (such as P00/TI00 and P17/TO02/TI02) to be shared with the timer input pin for timer input, <R> set the port mode register (PMxx) bit corresponding to each port to 1. And set the port mode contorol register (PMCxx) bit corresponding to each port to 0. At this time, the port register (Pxx) bit may be 0 or 1. Example: When using P17/TO02/TI02 for timer input <R> Set the PMC17 bit of port mode contorol register 1 to 0. Set the PM17 bit of port mode register 1 to 1. Set the P17 bit of port register 1 to 0 or 1. The PM0, PM1, PM3, PM4, PM6, PM10, PM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Remark In the 20- to 30-pin products, TI00 (P00) and TO00 (P01) pins alternate analog input pins. When using the timer I/O function, the corresponding bit of the PMC0 register for switching digital I/O or analog input is sure to set to "0". R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 351 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-24. Format of Port Mode Registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14) (128-pin products) Address: FFF20H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FFF21H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 Address: FFF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 1 1 PM31 PM30 Address: FFF24H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 1 1 PM43 PM42 PM41 PM40 Address: FFF26H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM6 PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 Address: FFF2AH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM10 1 PM106 PM105 PM104 PM103 PM102 PM101 PM100 Address: FFF2EH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM14 PM147 PM146 PM145 PM144 PM143 PM142 PM141 PM140 PMmn Remark Pmn pin I/O mode selection (m = 0, 1, 3, 4, 6, 10, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) The figure shown above presents the format of port mode registers 0, 1, 3, 4, 6, 10, and 14 of the 128-pin products. The format of the port mode register of other products, see 4.3 (1) Port mode registers (PMxx). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 352 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply. (1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel. (2) Any channel, except channel 0, can be set as a slave channel. (3) The slave channel must be lower than the master channel. Example: If channel 2 is set as a master channel, channel 3 or those that follow (channels 3, 4, 5, etc.) can be set as a slave channel. (4) Two or more slave channels can be set for one master channel. (5) When two or more master channels are to be used, slave channels with a master channel between them may not be set. Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0. (6) The operating clock for a slave channel in combination with a master channel must be the same as that of the master channel. The CKSmn0, CKSmn1 bits (bit 15, 14 of timer mode register mn (TMRmn)) of the slave channel that operates in combination with the master channel must be the same value as that of the master channel. (7) A master channel can transmit INTTMmn (interrupt), start software trigger, and count clock to the lower channels. (8) A slave channel can use INTTMmn (interrupt), a start software trigger, or the count clock of the master channel as a source clock, but cannot transmit its own INTTMmn (interrupt), start software trigger, or count clock to channels with lower channel numbers. (9) A master channel cannot use INTTMmn (interrupt), a start software trigger, or the count clock from the other higher master channel as a source clock. (10) To simultaneously start channels that operate in combination, the channel start trigger bit (TSmn) of the channels in combination must be set at the same time. (11) During the counting operation, a TSmn bit of a master channel or TSmn bits of all channels which are operating simultaneously can be set. It cannot be applied to TSmn bits of slave channels alone. (12) To stop the channels in combination simultaneously, the channel stop trigger bit (TTmn) of the channels in combination must be set at the same time. (13) CKm2/CKm3 cannot be selected while channels are operating simultaneously, because the operating clocks of master channels and slave channels have to be synchronized. (14) Timer mode register m0 (TMRm0) has no master bit (it is fixed as "0"). However, as channel 0 is the highest channel, it can be used as a master channel during simultaneous operation. The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave channels forming one simultaneous channel operation function). If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous channel operation function in 6.4.1 Basic rules of simultaneous channel operation function do not apply to the channel groups. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 353 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Example TAU0 CKm0 Channel 0: Master Channel group 1 (Simultaneous channel operation function) Channel 1: Slave Channel 2: Slave Channel group 2 (Simultaneous channel operation function) Channel 3: independent channel operation function CKm1 CKm0 Channel 4: Master * The operating clock of channel group 1 may be different from that of channel group 2. Channel 5: independent channel operation function * A channel that operates independent channel operation function may be between channel group 1 and channel group 2. Channel 6: Slave Channel 7: independent channel operation function R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 * A channel that operates independent channel operation function may be between a master and a slave of channel group 2. Furthermore, the operating clock may be set separately. 354 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3, and there are several rules for using it. The basic rules for this function are as follows: (1) The 8-bit timer operation function applies only to channels 1 and 3. (2) When using 8-bit timers, set the SPLIT bit of timer mode register mn (TMRmn) to 1. (3) The higher 8 bits can be operated as the interval timer function. (4) At the start of operation, the higher 8 bits output INTTMm1H/INTTMm3H (an interrupt) (which is the same operation performed when MDmn0 is set to 1). (5) The operation clock of the higher 8 bits is selected according to the CKSmn1 and CKSmn0 bits of the lower-bit TMRmn register. (6) For the higher 8 bits, the TSHm1/TSHm3 bit is manipulated to start channel operation and the TTHm1/TTHm3 bit is manipulated to stop channel operation. The channel status can be checked using the TEHm1/TEHm3 bit. (7) The lower 8 bits operate according to the TMRmn register settings. The following three functions support operation of the lower 8 bits: * Interval timer function * External event counter function * Delay count function (8) For the lower 8 bits, the TSm1/TSm3 bit is manipulated to start channel operation and the TTm1/TTm3 bit is manipulated to stop channel operation. The channel status can be checked using the TEm1/TEm3 bit. (9) During 16-bit operation, manipulating the TSHm1, TSHm3, TTHm1, and TTHm3 bits is invalid. The TSm1, TSm3, TTm1, and TTm3 bits are manipulated to operate channels 1 and 3. The TEHm3 and TEHm1 bits are not changed. (10) For the 8-bit timer function, the simultaneous operation functions (one-shot pulse, PWM, and multiple PWM) cannot be used. Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 355 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (fTCLK) The count clock (fTCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register mn (TMRmn). . * Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits * Valid edge of input signal input from the TImn pin Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK) are shown below. (1) When operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0) The count clock (fTCLK) is between fCLK to fCLK /215 by setting of timer clock select register m (TPSm). When a <R> divided fCLK is selected, however, the clock selected in TPSmn register, but a signal which becomes high level for one period of fCLK from its rising edge. When a fCLK is selected, fixed to high level Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock, because of synchronization with fCLK. But, this is described as "counting at rising edge of the count clock", as a matter of convenience. Figure 6-25. Timing of fCLK and count clock (fTCLK) (When CCSmn = 0) fCLK fCLK/2 fCLK/4 fTCLK ( = fMCK = CKmn) fCLK/8 fCLK/16 Remarks 1. : Rising edge of the count clock : Synchronization, increment/decrement of counter 2. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 fCLK: CPU/peripheral hardware clock 356 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (fTCLK) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input signal via the TImn pin (when a noise filter is used, the delay becomes 3 to 4 clock). Counting of timer count register mn (TCRmn) delayed by one period of fCLK from rising edge of the count clock, because of synchronization with fCLK. But, this is described as "counting at valid edge of input signal via the TImn pin", as a matter of convenience. Figure 6-26. Timing of fCLK and count clock (fTCLK) (When CCSmn = 1, noise filter unused) fMCK TSmn(Write) <1> TEmn TImn input <2> Sampling wave Edge detection <3> Edge detection Rising edge detection signal (fTCLK) <1> Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input signal via the TImn pin. <2> The rise of input signal via the TImn pin is sampled by fMCK. <3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output. Remarks 1. : Rising edge of the count clock : Synchronization, increment/decrement of counter 2. fCLK: CPU/peripheral hardware clock fMCK: Operation clock of channel n 3. The waveform of the input signal via TImn pin of the input pulse interval measurement, the measurement of high/low width of input signal, and the delay counter, the one-shot pulse output are the same as that shown in Figure 6-22. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 357 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-6. <R> Table 6-6. Operations from Count Operation Enabled State to Timer count Register mn (TCRmn) Count Start Timer operation mode * Interval timer mode Operation when TSmn = 1 is set No operation is carried out from start trigger detection (TSmn=1) until count clock generation. The first count clock loads the value of the TDRmn register to the TCRmn register and the subsequent count clock performs count down operation (see 6.5.3 (1) Operation of interval timer mode). * Event counter mode Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn register. If detect edge of TImn input. The subsequent count clock performs count down operation (see 6.5.3 (2) Operation of event counter mode). * Capture mode No operation is carried out from start trigger detection (TSmn = 1) until count clock generation. The first count clock loads 0000H to the TCRmn register and the subsequent count clock performs count up operation (see 6.5.3 (3) Operation of capture mode (input pulse interval measurement)). * One-count mode The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the timer is stopped (TEmn = 0). No operation is carried out from start trigger detection until count clock generation. The first count clock loads the value of the TDRmn register to the TCRmn register and the subsequent count clock performs count down operation (see 6.5.3 (4) Operation of one-count mode). * Capture & one-count mode The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the timer is stopped (TEmn = 0). No operation is carried out from start trigger detection until count clock generation. The first count clock loads 0000H to the TCRmn register and the subsequent count clock performs count up operation (see 6.5.3 (5) Operation of capture & one-count mode (high-level interval measurement)). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 358 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT <R> 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation. <2> A start trigger is generated at the first count clock after operation is enabled. <3> When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger. <4> By the first count clock after the operation enable, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and counting starts in the interval timer mode. <5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of timer data register mn (TDRmn) is loaded to the TCRmn register and counting keeps on. Figure 6-27. Operation Timing (In Interval Timer Mode) fMCK (fTCLK) TSmn(Write) <1> TEmn <2> Start trigger detection signal TCRmn TDRmn Initial value <3> m 0001 m-1 <4> 0000 m m <5> INTTMmn When MDmn0 = 1 setting Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one clock is generated since count start delays until count clock has been generated. When the information on count start timing is necessary, an interrupt can be generated at count start by setting MDmn0 = 1. <R> Remark fMCK, the start trigger detection signal, and INTTMmn become active between one clock in synchronization with fCLK. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 359 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data register mn (TDRmn) is loaded to the TCRmn register to start counting. <4> After that, the TCRmn register value is counted down according to the count clock of the valid edge of the TImn input . Figure 6-28. Operation Timing (In Event Counter Mode) fMCK TSmn(Write) <1> TEmn <2> TImn input Edge detection Edge detection Count clock Start trigger detection signal <4> <1> TCRmn <3> Initial value m-1 m m-2 <3> TDRmn m Remark The timing is shown in Figure 6-24 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 360 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation. <3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded to the TCRmn register and counting starts in the capture mode. (When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger.) <4> On detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data register mn (TDRmn) and INTTMmn is generated. However, this capture value is nomeaning. The TCRmn register keeps on counting from 0000H. <5> On next detection of the valid edge of the TImn input, the value of the TCRmn register is captured to timer data register mn (TDRmn) and INTTMmn is generated. <R> Figure 6-29. Operation Timing (In Capture Mode : Input Pulse Interval Measurement) fMCK (fTCLK) TS0n(Write) <1> TE0n Note <3> TI0n input <4> Start trigger detection signal <2> TCR0n Edge detection Edge detection Rising edge Initial value <5> <3> 0000 TDR0n 0001 0000 0001 Note m-1 m 0000 m INTTM0n <R> Note If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a trigger is detected, even if no edge is detected. Therefore, the first captured value (<4>) does not determine a pulse interval (in the above figure, 0001 just indicates two clock cycles but does not determine the pulse interval) and so the user can ignore it. Caution In the first cycle operation of count clock after writing the TSmn bit, an error at a maximum of one clock is generated since count start delays until count clock has been generated. When the information on count start timing is necessary, an interrupt can be generated at count start by setting MDmn0 = 1. <R> Remark The timing is shown in Figure 6-25 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 361 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and count starts. <5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of the TCRmn register becomes FFFFH and counting stops . Figure 6-30. Operation Timing (In One-count Mode) fMCK (fTCLK) TSmn(Write) <1> TEmn TImn input <3> Edge detection Rising edge <4> Start trigger detection signal <5> <2> TCRmn Initial value m 1 0 FFFF INTTMmn Start trigger input wait status Remark The timing is shown in Figure 6-26 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and that of the count clock (fMCK). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 362 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts. <5> On detection of the falling edge of the TImn input, the value of the TCRmn register is captured to timer data register mn (TDRmn) and INTTMmn is generated. Figure 6-31. Operation Timing (In Capture & One-count Mode : High-level Width Measurement) fMCK (fTCLK) TSmn(Write) <1> TEmn TImn input <3> Edge detection Edge detection Rising edge <4> Falling edge <5> Start trigger detection signal <2> TCRmn Initial value TDRmn 0000 0000 m-1 m m+1 m INTTMmn Remark The timing is shown in Figure 6-27 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal <R> cycle of TImn input. The error per one period occurs be the asynchronous between the period of the TImn input and that of the count clock (fMCK). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 363 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TOmn pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-32. Output Circuit Configuration <5> TOmn register Controller Interrupt signal of the master channel (INTTMmn) Interrupt signal of the slave channel (INTTMmp) Set TOmn pin Reset/toggle <1> <2> <3> <4> TOLmn TOMmn Internal bus TOEmn TOmn write signal The following describes the TOmn pin output circuit. <1> When TOMmn = 0 (master channel output mode), the set value of timer output level register m (TOLm) is ignored and only INTTM0p (slave channel timer interrupt) is transmitted to timer output register m (TOm). <2> When TOMmn = 1 (slave channel output mode), both INTTMmn (master channel timer interrupt) and INTTM0p (slave channel timer interrupt) are transmitted to the TOm register. At this time, the TOLm register becomes valid and the signals are controlled as follows: When TOLmn = 0: Positive logic output (INTTMmn set, INTTM0p reset) When TOLmn = 1: Negative logic output (INTTMmn reset, INTTM0p set) When INTTMmn and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset signal) takes priority, and INTTMmn (set signal) is masked. <3> While timer output is enabled (TOEmn = 1), INTTMmn (master channel timer interrupt) and INTTM0p (slave channel timer interrupt) are transmitted to the TOm register. Writing to the TOm register (TOmn write signal) becomes invalid. When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals. To initialize the TOmn pin output level, it is necessary to set timer operation is stopeed (TOEmn = 0) and to write a value to the TOm register. <4> While timer output is disabeled (TOEmn = 0), writing to the TOmn bit to the target channel (TOmn write signal) becomes valid. When timer output is disabeled (TOEmn = 0), neither INTTMmn (master channel timer interrupt) nor INTTM0p (slave channel timer interrupt) is transmitted to the TOm register. <5> The TOm register can always be read, and the TOmn pin output level can be checked. Remark m: Unit number (m = 0, 1) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n<p7 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 364 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn Pin Output Setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-33. Status Transition from Timer Output Setting to Operation Start TCRmn (Counter) Undefined value (FFFFH after reset) Hi-Z Timer alternate-function pin Timer output signal TOmn TOEmn Write operation enabled period to TOmn <1> Set TOMmn Set TOLmn <2> Set TOmn Write operation disabled period to TOmn <3> Set TOEmn <4> Set the port to <5> Timer operation start output mode <1> The operation mode of timer output is set. * TOMmn bit (0: Master channel output mode, 1: Slave channel output mode) * TOLmn bit (0: Positive logic output, 1: Negative logic output) <2> The timer output signal is set to the initial status by setting timer output register m (TOm). <3> The timer output operation is enabled by writing 1 to the TOEmn bit (writing to the TOm register is disabled). <R> <4> The port is set to digital I/O by port mode control register (PMCxx) (see 6.3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14)). <5> The port I/O setting is set to output (see 6.3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14)). <6> The timer operation is enabled (TSmn = 1). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 365 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on Channel Output Operation (1) Changing values set in the registers TOm, TOEm, and TOLm during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn)) are independent of the TOmn output circuit and changing the values set in timer output register m (TOm), timer output enable register m (TOEm), and timer output level register m (TOLm) does not affect the timer operation, the values can be changed during timer operation. To output an expected waveform from the TOmn pin by timer operation, however, set the TOm, TOEm, TOLm, and TOMm registers to the values stated in the register setting example of each operation shown by 6.7 and 6.8. When the values set to the TOEm, and TOMm registers (but not the TOm register) are changed close to the occurrence of the timer interrupt (INTTMmn) of each channel, the waveform output to the TOmn pin might differ, depending on whether the values are changed immediately before or immediately after the timer interrupt (INTTMmn) occurs. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 366 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below. (a) When operation starts with master channel output mode (TOMmn = 0) setting The setting of timer output level register m (TOLm) is invalid when master channel output mode (TOMmn = 0). When the timer operation starts after setting the default level, the toggle signal is generated and the output level of the TOmn pin is reversed. Figure 6-34. TOmn Pin Output Status at Toggle Output (TOMmn = 0) <R> TOEmn Hi-Z Default status TOmn bit = 0 (Default status : Low) TOmn bit = 1 (Default status : High) TOmn (output) TOmn bit = 0 (Active high) TOmn bit = 0 (Default status : Low) TOmn bit = 1 (Default status : High) TOmn bit = 1 (Active low) Port output is enabled Bold : Active level Toggle Remarks 1. Toggle: Toggle Toggle Toggle Toggle Reverse TOmn pin output status 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 367 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output)) When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m (TOLm) setting. Figure 6-35. TOmp Pin Output Status at PWM Output (TOMmp = 1) <R> TOEmp Hi -Z Default status Active Active Active TOmp bit = 0 (Default status : Low) TOmp bit = 1 (Default status : High) TOmp (output) TOmp bit = 0 (Active high) TOmp bit = 0 (Default status : Low) TOmp bit = 1 (Default status : High) TOmp bit = 1 (Active low) Port output is enabled Reset Set Remarks 1. Set: Reset: Reset Set Set The output signal of the TOmp pin changes from inactive level to active level. The output signal of the TOmp pin changes from active level to inactive level. 2. m: Unit number (m = 0, 1), p: Channel number (p = 1 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 368 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output level of the TOmn pin. The operation when TOMmn is set to 1 and the value of the TOLm register is changed while the timer is operating (TEmn = 1) is shown below. Figure 6-36. Operation when TOLm Register Has Been Changed Contents during Timer Operation <R> TOLm Active Active Active Active TOmn (output) Reset Set Remarks 1. Set: Reset: Reset Reset Set Set Reset Set The output signal of the TOmn pin changes from inactive level to active level. The output signal of the TOmn pin changes from active level to inactive level. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) (b) Set/reset timing To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt (INTTMmn) generation is delayed by 1 count clock by the slave channel. If the set condition and reset condition are generated at the same time, a higher priority is given to the latter. Figure 6-37 shows the set/reset operating statuses where the master/slave channels are set as follows. Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0 Slave channel: TOEmp = 1, TOMmp = 1, TOLmp = 0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 369 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-37. Set/Reset Timing Operating Statuses (1) Basic operation timing fTCLK INTTMmn Master channel Internal reset signal TOmn pin/ TOmn Toggle Toggle Internal set signal 1 clock delay INTTMmp Slave channel Internal reset signal TOmp pin/ TOmp Set Set Reset (2) Operation timing when 0 % duty fTCLK INTTMmn Master channel Internal reset signal TOmn pin/ TOmn Toggle Toggle Internal set signal 1 clock delay TCRmp Slave channel 0000 0001 0000 0001 INTTMmp Set Internal reset signal TOmp pin/ TOmp Reset Set Reset has priority. Reset Reset has priority. Remarks 1. Internal reset signal: TOmn pin reset/toggle signal Internal set signal: TOmn pin set signal 2. m: Unit number (m = 0, 1) n: Channel number n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n<p7 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 370 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively. Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond to the relevant bits of the channel used to perform output (TOmn). Figure 6-38 Example of TO0n Bit Collective Manipulation Before writing TO0 0 0 0 0 0 0 0 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00 0 TOE0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 O O x O x x x x Data to be written 0 0 0 0 0 0 0 0 After writing TO0 0 0 0 0 0 0 0 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00 1 1 1 0 0 0 1 0 Writing is done only to the TOmn bit with TOEmn = 0, and writing to the TOmn bit with TOEmn = 1 is ignored. TOmn (channel output) to which TOEmn = 1 is set is not affected by the write operation. Even if the write operation is done to the TOmn bit, it is ignored and the output change by timer operation is normally done. Figure 6-39. TO0n Pin Statuses by Collective Manipulation of TO0n Bit Two or more TO0n output can be changed simultaneously TO07 Output does not change when value does not change TO06 TO05 TO04 Writing to the TO0n bit is ignored when TOE0n =1 TO03 TO02 TO01 TO00 Before writing Writing to the TO0n bit Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer (INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 371 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer Interrupt and TOmn Pin Output at Operation Start In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start. When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation. In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled. Figure 6-40 shows operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set. Figure 6-40. Operation examples of timer interrupt at count operation start and TOmn output (a) When MDmn0 is set to 1 TCRmn TEmn INTTMmn TOmn Count operation start (b) When MDmn0 is set to 0 TCRmn TEmn INTTMmn TOmn Count operation start When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle operation. When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 372 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7 Independent Channel Operation Function of Timer Array Unit 6.7.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals. The interrupt generation period can be calculated by the following expression. Generation period of INTTMmn (timer interrupt) = Period of count clock x (Set value of TDRmn + 1) (2) Operation as square wave output TOmn performs a toggle operation as soon as INTTMmn has been generated, and outputs a square wave with a duty factor of 50%. The period and frequency for outputting a square wave from TOmn can be calculated by the following expressions. * Period of square wave output from TOmn = Period of count clock x (Set value of TDRmn + 1) x 2 * Frequency of square wave output from TOmn = Frequency of count clock/{(Set value of TDRmn + 1) x 2} Timer count register mn (TCRmn) operates as a down counter in the interval timer mode. The TCRmn register loads the value of timer data register mn (TDRmn) at the first count clock after the channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1. If the MDmn0 bit of timer mode register mn (TMRmn) is 0 at this time, INTTMmn is not output and TOmn is not toggled. If the MDmn0 bit of the TMRmn register is 1, INTTMmn is output and TOmn is toggled. After that, the TCRmn register count down in synchronization with the count clock. When TCRmn = 0000H, INTTMmn is output and TOmn is toggled at the next count clock. At the same time, the TCRmn register loads the value of the TDRmn register again. After that, the same operation is repeated. The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the next period. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 373 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Clock selection Figure 6-41. Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 CKm0 Trigger selection Operation clockNote TSmn Timer counter register mn (TCRmn) Output controller Timer data register mn(TDRmn) Interrupt controller TOmn pin Interrupt signal (INTTMmn) Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Figure 6-42. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MDmn0 = 1) TSmn TEmn TCRmn 0000H TDRmn a b TOmn INTTMmn a+1 a+1 a+1 b+1 b+1 b+1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2. TSmn: TEmn: Bit n of timer channel start register m (TSm) Bit n of timer channel enable status register m (TEm) TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) TOmn: TOmn pin output signal R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 374 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 1/0 12 11 CCSmn M/S 0 0 Note 0/1 10 9 8 7 6 5 4 0 0 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 0 0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 0 0 0 0 1/0 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 0: Neither generates INTTMmn nor inverts timer output when counting is started. 1: Generates INTTMmn and inverts timer output when counting is started. Selection of TImn pin input edge 00B: Sets 00B because these are not used. Start trigger selection 000B: Selects only software start. <R> Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function. Setting of SPLITmn bit (channels 1, 3) 1: 8-bit timer mode Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n. 01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 1/0 1: Outputs 1 from TOmn. (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 1/0 0: Stops the TOmn output operation by counting operation. 1: Enables the TOmn output operation by counting operation. Note TMRm2, TMRm4, TMRm6: MASTERmn bit TMRm1, TMRm3: SPLITmn bit TMRm0, TMRm5, TMRm7: Fixed to 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 375 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode) 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 376 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3. Channel default setting Operation is resumed. Operation start Sets timer mode register mn (TMRmn) (determines operation mode of channel). Sets interval (period) value to timer data register mn (TDRmn). Channel stops operating. (Clock is supplied and some power is consumed.) To use the TOmn output Clears the TOMmn bit of timer output mode register m (TOMm) to 0 (master channel output mode). Clears the TOLmn bit to 0. Sets the TOmn bit and determines default level of the TOmn output. The TOmn pin goes into Hi-Z output state. Sets the TOEmn bit to 1 and enables operation of TOmn. Clears the port register and port mode register to 0. TOmn does not change because channel stops operating. The TOmn pin outputs the TOmn set level. (Sets the TOEmn bit to 1 only if using TOmn output and resuming operation.). Sets the TSmn (TSHm1, TSHm3) bit to 1. The TSmn (TSHm1, TSHm3) bit automatically returns to 0 because it is a trigger bit. The TOmn default setting level is output when the port mode register is in the output mode and the port register is 0. TEmn (TEHm1, TEHm3) = 1, and count operation starts. Value of the TDRmn register is loaded to timer count register mn (TCRmn) at the count clock input. INTTMmn is generated and TOmn performs toggle operation if the MDmn0 bit of the TMRmn register is 1. During operation Set values of the TMRmn register, TOMmn, and TOLmn bits cannot be changed. Set value of the TDRmn register can be changed. The TCRmn register can always be read. The TSRmn register is not used. Set values of the TOm and TOEm registers can be changed. Counter (TCRmn) counts down. When count value reaches 0000H, the value of the TDRmn register is loaded to the TCRmn register again and the count operation is continued. By detecting TCRmn = 0000H, INTTMmn is generated and TOmn performs toggle operation. After that, the above operation is repeated. Operation stop The TTmn (TTHm1, TTHm3) bit is set to 1. The TTmn (TTHm1, TTHm3) bit automatically returns to 0 because it is a trigger bit. TEmn (TEHm1, TEHm3), and count operation stops. The TCRmn register holds count value and stops. The TOmn output is not initialized but holds current status. The TOEmn bit is cleared to 0 and value is set to the TOmn bit. The TOmn pin outputs the TOmn bit set level. (Remark is listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 377 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation TAU stop To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to be held is set to the port register. When holding the TOmn pin output level is not necessary Setting not required. The TAUmEN bit of the PER0 register is cleared to 0. Hardware Status The TOmn pin output level is held by port function. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TOmn bit is cleared to 0 and the TOmn pin is set to port mode.) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 378 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt. The specified number of counts can be calculated by the following expression. Specified number of counts = Set value of TDRmn + 1 Timer count register mn (TCRmn) operates as a down counter in the event counter mode. The TCRmn register loads the value of timer data register mn (TDRmn) by setting any channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) to 1. The TCRmn register counts down each time the valid input edge of the TImn pin has been detected. When TCRmn = 0000H, the TCRmn register loads the value of the TDRmn register again, and outputs INTTMmn. After that, the above operation is repeated. An irregular waveform that depends on external events is output from the TOmn pin. Stop the output by setting the TOEmn bit of timer output enable register m (TOEm) to 0. The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid during the next count period. Noise filter NFEN1 register TSmn Edge detection Trigger selection <R> TImn pin Clock selection Figure 6-45. Block Diagram of Operation as External Event Counter Timer counter register mn (TCRmn) Timer data register mn (TDRmn) Interrupt controller Interrupt signal (INTTMmn) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 379 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn 3 TCRmn 0000H TDRmn 2 3 1 2 0 1 2 0 0003H 1 2 0 1 0002H INTTMmn 4 events 4 events 3 events Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2. TSmn: Bit n of timer channel start register m (TSm) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 380 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 1/0 12 11 CCSmn M/S 0 1 Note 0/1 10 9 8 7 6 5 4 0 0 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 0 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1/0 0 1 1 0 Operation mode of channel n 011B: Event count mode Setting of operation when counting is started 0: Neither generates INTTMmn nor inverts timer output when counting is started. Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 000B: Selects only software start. <R> Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function. Setting of SPLITmn bit (channels 1, 3) 1: 8-bit timer mode Count clock selection 1: Selects the TImn pin input valid edge. Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n. 01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 0 (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 0: Stops the TOmn output operation by counting operation. 0 Note TMRm2, TMRm4, TMRm6: MASTERmn bit TMRm1, TMRm3: SPLITmn bit TMRm0, TMRm5, TMRm7: Fixed to 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 381 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 382 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure When External Event Counter Function Is Used <R> Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3. Channel Sets timer mode register mn (TMRmn) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) setting Sets number of counts to timer data register mn (TDRmn). Clears the TOEmn bit of timer output enable register m (TOEm) to 0. Operation Operation is resumed. start Sets the TSmn bit to 1. TEmn = 1, and count operation starts. The TSmn bit automatically returns to 0 because it is a Value of the TDRmn register is loaded to timer count trigger bit. register mn (TCRmn) and detection of the TImn pin input edge is awaited. During Set value of the TDRmn register can be changed. Counter (TCRmn) counts down each time input edge of operation Sets coresponting bit of noise filtrer enable register 1, 2 the TImn pin has been detected. When count value (NFEN1, NFEN2) to 1. reaches 0000H, the value of the TDRmn register is loaded The TCRmn register can always be read. to the TCRmn register again, and the count operation is The TSRmn register is not used. continued. By detecting TCRmn = 0000H, the INTTMmn Set values of the TMRmn register, TOMmn, TOLmn, output is generated. TOmn, and TOEmn bits cannot be changed. After that, the above operation is repeated. The TTmn bit is set to 1. TEmn = 0, and count operation stops. Operation stop The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops. trigger bit. TAU The TAUmEN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 383 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Operation as frequency divider (channel 0 of unit 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin. The divided clock frequency output from TO00 can be calculated by the following expression. * When rising edge/falling edge is selected: Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) x 2} * When both edges are selected: Divided clock frequency Input clock frequency/(Set value of TDR00 + 1) Timer count register 00 (TCR00) operates as a down counter in the interval timer mode. After the channel start trigger bit (TS00) of timer channel start register 0 (TS0) is set to 1, the TCR00 register loads the value of timer data register 00 (TDR00) when the TI00 valid edge is detected. If the MD000 bit of timer mode register 00 (TMR00) is 0 at this time, INTTM00 is not output and TO00 is not toggled. If the MD000 bit of timer mode register 00 (TMR00) is 1, INTTM00 is output and TO00 is toggled. After that, the TCR00 register counts down at the valid edge of the TI00 pin. When TCR00 = 0000H, it toggles TO00. At the same time, the TCR00 register loads the value of the TDR00 register again, and continues counting. If detection of both the edges of the TI00 pin is selected, the duty factor error of the input clock affects the divided clock period of the TO00 output. The period of the TO00 output clock includes a sampling error of one period of the operation clock. Clock period of TO00 output = Ideal TO00 output clock period Operation clock period (error) The TDR00 register can be rewritten at any time. The new value of the TDR00 register becomes valid during the next count period. Figure 6-49. Block Diagram of Operation as Frequency Divider TI00 pin Noise filter Edge detection TS00 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Trigger selection <R> Clock selection TNFEN00 Timer counter register 00 (TCR00) Output controller TO00 pin Timer data register 00 (TDR00) 384 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1) TS00 TE00 TI00 2 2 1 TCR00 0000H TDR00 2 1 0 1 0 1 0 0002H 1 1 0 0 1 0 0 0001H TO00 INTTM00 Divided by 6 Remark TS00: Divided by 4 Bit n of timer channel start register 0 (TS0) TE00: Bit n of timer channel enable status register 0 (TE0) TI00: TI00 pin input signal TCR00: Timer count register 00 (TCR00) TDR00: Timer data register 00 (TDR00) TO00: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 TO00 pin output signal 385 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers During Operation as Frequency Divider (a) Timer mode register 00 (TMR00) 15 TMR00 14 13 CKS0n1 CKS0n0 1/0 0 0 12 11 CCS00 MAS TER00 1 0 10 9 8 7 6 5 4 0 0 STS002 STS001 STS000 CIS001 CIS000 0 0 0 1/0 3 2 1 0 MD003 MD002 MD001 MD000 1/0 0 0 0 1/0 Operation mode of channel 0 000B: Interval timer Setting of operation when counting is started 0: Neither generates INTTM00 nor inverts timer output when counting is started. 1: Generates INTTM00 and inverts timer output when counting is started. Selection of TI00 pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 000B: Selects only software start. Slave/master selection 0: Independent channel operation Count clock selection 1: Selects the TI00 pin input valid edge. Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel 0. 10B: Selects CK01 as operation clock of channel 0. (b) Timer output register 0 (TO0) Bit 0 TO0 TO00 0: Outputs 0 from TO00. 1/0 1: Outputs 1 from TO00. (c) Timer output enable register 0 (TOE0) Bit 0 TOE0 TOE00 1/0 0: Stops the TO00 output operation by counting operation. 1: Enables the TO00 output operation by counting operation. (d) Timer output level register 0 (TOL0) Bit 0 TOL0 TOL00 0: Cleared to 0 when master channel output mode (TOM00 = 0) 0 (e) Timer output mode register 0 (TOM0) Bit 0 TOM0 TOM00 0: Sets master channel output mode. 0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 386 RL78/G13 <R> CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Operation Procedure When Frequency Divider Function Is Used Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 to CK03. Channel default setting Sets timer mode register 0n (TMR0n) (determines operation mode of channel and selects the detection edge). Sets interval (period) value to timer data register 00 (TDR00). Channel stops operating. (Clock is supplied and some power is consumed.) Clears the TOM00 bit of timer output mode register 0 (TOM0) to 0 (master channel output mode). Clears the TOL00 bit to 0. Sets the TO00 bit and determines default level of the TO00 output. The TO00 pin goes into Hi-Z output state. Operation is resumed. Sets the TOE00 bit to 1 and enables operation of TO00. Clears the port register and port mode register to 0. The TO00 default setting level is output when the port mode register is in output mode and the port register is 0. TO00 does not change because channel stops operating. The TO00 pin outputs the TO00 set level. Operation start Sets the TOE00 bit to 1 (only when operation is resumed). Sets the TS00 bit to 1. The TS00 bit automatically returns to 0 because it is a trigger bit. During operation Set value of the TDR00 register can be changed. Sets coresponting bit of noise filter enable register 1, 2 (NFEN1, NFEN2) to 1. The TCR00 register can always be read. The TSR00 register is not used. Set values of the TO0 and TOE0 registers can be changed. Set values of the TMR00 register, TOM00, and TOL00 bits cannot be changed. Counter (TCR00) counts down. When count value reaches 0000H, the value of the TDR00 register is loaded to the TCR00 register again, and the count operation is continued. By detecting TCR00 = 0000H, INTTM00 is generated and TO00 performs toggle operation. After that, the above operation is repeated. Operation stop The TT00 bit is set to 1. The TT00 bit automatically returns to 0 because it is a trigger bit. TE00 = 0, and count operation stops. The TCR00 register holds count value and stops. The TO00 output is not initialized but holds current status. The TOE00 bit is cleared to 0 and value is set to the TO00 bit. The TO00 pin outputs the TO00 set level. TAU stop To hold the TO00 pin output level Clears the TO00 bit to 0 after the value to be held is set to the port register. When holding the TO00 pin output level is not necessary Setting not required. The TAU0EN bit of the PER0 register is cleared to 0. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 TE00 = 1, and count operation starts. Value of the TDR00 register is loaded to timer count register 00 (TCR00) at the count clock input. INTTM00 is generated and TO00 performs toggle operation if the MD000 bit of the TMR00 register is 1. The TO00 pin output level is held by port function. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TO00 bit is cleared to 0 and the TO00 pin is set to port mode). 387 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.4 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. The pulse interval can be calculated by the following expression. TImn input pulse interval = Period of count clock x ((10000H x TSRmn: OVF) + (Capture value of TDRmn + 1)) Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer mode register mn (TMRmn), so an error of up to one operating clock cycle occurs. Timer count register mn (TCRmn) operates as an up counter in the capture mode. When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register counts up from 0000H in synchronization with the count clock. When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured) to timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the INTTMmn is output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. After that, the above operation is repeated. As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the captured value can be checked. If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more overflows occur. Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a capture trigger. When TEmn = 1, a software operation (TSmn = 1) can be used as a capture trigger, instead of using the TImn pin input. CKm1 Operation clock Note CKm0 TImn pin Noise filter NFEN1 register Edge detection TSmn Trigger selection Clock selection Figure 6-53. Block Diagram of Operation as Input Pulse Interval Measurement Timer counter register mn (TCRmn) Timer data register mn (TDRmn) Interrupt controller Interrupt signal (INTTMmn) Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 388 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH b a TCRmn d c 0000H TDRmn 0000H a b c d INTTMmn OVF Remarks 1. m: Unit number (m = 0, 1)n: Channel number (n = 0 to 7) 2. TSmn: Bit n of timer channel start register m (TSm) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) OVF: Bit 0 of timer status register mn (TSRmn) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 389 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT <R> Figure 6-55. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 0 12 11 CCSmn M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 1 1/0 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 0 1 0 1/0 Operation mode of channel n 010B: Capture mode Setting of operation when counting is started 0: Does not generate INTTMmn when counting is started. 1: Generates INTTMmn when counting is started. Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Capture trigger selection 001B: Selects the TImn pin input valid edge. Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation Setting of SPLITmn bit (channels 1, 3) 0: 16-bit timer mode. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n. 01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 0 (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 0: Stops TOmn output operation by counting operation. 0 (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Note TMRm2, TMRm4, TMRm6: MASTERmn bit TMRm1, TMRm3: SPLITmn bit TMRm0, TMRm5, TMRm7: Fixed to 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 390 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Operation Procedure When Input Pulse Interval Measurement Function Is Used <R> Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3. Channel Sets timer mode register mn (TMRmn) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) Sets TSmn bit to 1. TEmn = 1, and count operation starts. setting Operation start The TSmn bit automatically returns to 0 because it is a Timer count register mn (TCRmn) is cleared to 0000H trigger bit. at the count clock input. When the MDmn0 bit of the TMRmn register is 1, Operation is resumed. INTTMmn is generated. During Set values of only the CISmn1 and CISmn0 bits of the Counter (TCRmn) counts up from 0000H. When the TImn operation TMRmn register can be changed. pin input valid edge is detected, the count value is Sets coreponting bit of noise filter enable register 1, 2 transferred (captured) to timer data register mn (TDRmn). (NFEN1, NFEN2) to 1. At the same time, the TCRmn register is cleared to The TDRmn register can always be read. 0000H, and the INTTMmn signal is generated. The TCRmn register can always be read. If an overflow occurs at this time, the OVF bit of timer The TSRmn register can always be read. status register mn (TSRmn) is set; if an overflow does not Set values of the TOMmn, TOLmn, TOmn, and TOEmn occur, the OVF bit is cleared. bits cannot be changed. After that, the above operation is repeated. The TTmn bit is set to 1. TEmn = 0, and count operation stops. Operation stop TAU The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops. trigger bit. The OVF bit of the TSRmn register is also held. The TAUmEN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 391 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.5 Operation as input signal high-/low-level width measurement Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control register (ISC) to 1. In the following descriptions, read TImn as RxD2. By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the following expression. Signal width of TImn input = Period of count clock x ((10000H x TSRmn: OVF) + (Capture value of TDRmn + 1)) Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer mode register mn (TMRmn), so an error equivalent to one operation clock occurs. Timer count register mn (TCRmn) operates as an up counter in the capture & one-count mode. When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TEmn bit is set to 1 and the TImn pin start edge detection wait status is set. When the TImn pin input start edge (rising edge of the TImn pin input when the high-level width is to be measured) is detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling edge of the TImn pin input when the high-level width is to be measured) is detected later, the count value is transferred to timer data register mn (TDRmn) and, at the same time, INTTMmn is output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCRmn register stops at the value "value transferred to the TDRmn register + 1", and the TImn pin start edge detection wait status is set. After that, the above operation is repeated. As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the captured value can be checked. If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more overflows occur. Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the CISmn1 and CISmn0 bits of the TMRmn register. Because this function is used to measure the signal width of the TImn pin input, the TSmn bit cannot be set to 1 while the TEmn bit is 1. CISmn1, CISmn0 of TMRmn register = 10B: Low-level width is measured. CISmn1, CISmn0 of TMRmn register = 11B: High-level width is measured. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 392 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT CKm1 Operation clock Note CKm0 <R> TImn pin Noise filter NFEN1 register Edge detection Trigger selection Clock selection Figure 6-57. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement Timer counter register mn (TCRmn) Timer data register mn (TDRmn) Interrupt controller Interrupt signal (INTTMmn) Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Figure 6-58. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement TSmn TEmn TImn FFFFH a b TCRmn c 0000H TDRmn 0000H a b c INTTMmn OVF Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2. TSmn: Bit n of timer channel start register m (TSm) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) OVF: Bit 0 of timer status register mn (TSRmn) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 393 RL78/G13 <R> CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 0 12 11 CCSmn M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 1 0 1 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1 1 0 0 Operation mode of channel n 110B: Capture & one-count Setting of operation when counting is started 0: Does not generate INTTMmn when counting is started. Selection of TImn pin input edge 10B: Both edges (to measure low-level width) 11B: Both edges (to measure high-level width) Start trigger selection 010B: Selects the TImn pin input valid edge. Setting of MASTERmn bit (channels 2, 4, 6) 0: Independent channel operation function. Setting of SPLITmn bit (channels 1, 3) 1: 16-bit timer mode. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n. 01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 0 (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 0: Stops the TOmn output operation by counting operation. 0 (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Note TMRm2, TMRm4, TMRm6: MASTERmn bit TMRm1, TMRm3: SPLITmn bit TMRm0, TMRm5, TMRm7: Fixed to 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 394 RL78/G13 <R> CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3. Channel Sets timer mode register mn (TMRmn) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) setting Clears the TOEmn bit to 0 and stops operation of TOmn. Operation Sets the TSmn bit to 1. start The TSmn bit automatically returns to 0 because it is a TEmn = 1, and the TImn pin start edge detection wait status is set. trigger bit. Operation is resumed. Detects the TImn pin input count start valid edge. Clears timer count register mn (TCRmn) to 0000H and starts counting up. During Set value of the TDRmn register can be changed. When the TImn pin start edge is detected, the counter operation Sets coresponting bit of noisefilter enable register 1, 2 (TCRmn) counts up from 0000H. If a capture edge of the (NFEN1, NFEN2) to 1 TImn pin is detected, the count value is transferred to The TCRmn register can always be read. timer data register mn (TDRmn) and INTTMmn is The TSRmn register is not used. generated. Set values of the TMRmn register, TOMmn, TOLmn, If an overflow occurs at this time, the OVF bit of timer TOmn, and TOEmn bits cannot be changed. status register mn (TSRmn) is set; if an overflow does not occur, the OVF bit is cleared. The TCRmn register stops the count operation until the next TImn pin start edge is detected. Operation stop TAU The TTmn bit is set to 1. TEmn = 0, and count operation stops. The TTmn bit automatically returns to 0 because it is a The TCRmn register holds count value and stops. trigger bit. The OVF bit of the TSRmn register is also held. The TAUmEN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 395 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.7.6 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval. It can also generate INTTMmn (timer interrupt) at any interval by making a software set TSmn = 1 and the count down start during the period of TEmn = 1. The interrupt generation period can be calculated by the following expression. Generation period of INTTMmn (timer interrupt) = Period of count clock x (Set value of TDRmn + 1) Timer count register mn (TCRmn) operates as a down counter in the one-count mode. When the channel start trigger bit (TSmn, TSHm1, TSHm3) of timer channel start register m (TSm) is set to 1, the TEmn, TEHm1, TEHm3 bits are set to 1 and the TImn pin input valid edge detection wait status is set. Timer count register mn (TCRmn) starts operating upon TImn pin input valid edge detection and loads the value of timer data register mn (TDRmn). The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next TImn pin input valid edge is detected. The TDRmn register can be rewritten at any time. The new value of the TDRmn register becomes valid from the next period. CKm1 CKm0 TSmn <R> TImn pin Noise filter NFEN1 register Edge detection Trigger selection Operation clockNote Clock selection Figure 6-61. Block Diagram of Operation as Delay Counter Timer counter register mn (TCRmn) Timer data register mn (TDRmn) Interrupt controller Interrupt signal (INTTMmn) Note For using channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 396 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn a b INTTMmn a+1 b+1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) 2. TSmn: Bit n of timer channel start register m (TSm) TEmn: Bit n of timer channel enable status register m (TEm) TImn: TImn pin input signal TCRmn: Timer count register mn (TCRmn) TDRmn: Timer data register mn (TDRmn) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 397 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 1/0 12 11 CCSmn M/S 0 0 Note 0/1 10 9 8 7 6 5 4 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 1 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1/0 0 0 1 0 0 0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. 1: Trigger input is valid. Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 001B: Selects the TImn pin input valid edge. Setting of MASTERmn bit (channels 2, 4, 6) <R> 0: Independent channel operation function. Setting of SPLITmn bit (channels 1, 3) 1: 8-bit timer mode. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n. 01B: Selects CKm2 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CKm3 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 0 (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 0: Stops the TOmn output operation by counting operation. 0 Note TMRm2, TMRm4, TMRm6: MASTERmn bit TMRm1, TMRm3: SPLITmn bit TMRm0, TMRm5, TMRm7: Fixed to 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 398 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 399 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure When Delay Counter Function Is Used <R> Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 to CKm3. Channel Sets timer mode register mn (TMRmn) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) setting INTTMmn output delay is set to timer data register mn (TDRmn). Clears the TOEmn bit to 0 and stops operation of TOmn. Operation start Sets the TSmn bit to 1. The TSmn bit automatically returns to 0 because it is a TEmn = 1, and the TImn pin input valid edge detection wait status is set. trigger bit. Operation is resumed. Detects the TImn pin input valid edge. Value of the TDRmn register is loaded to the timer count register mn (TCRmn). During Set value of the TDRmn register can be changed. The counter (TCRmn) counts down. When TCRmn operation Sets coresponting bit of noisefilter enable register 1, 2 counts down to 0000H, INTTMmn is output, and counting (NFEN1, NFEN2) to 1 stops (which leaves TCRmn at 0000H) until the next TImn The TCRmn register can always be read. pin input. The TSRmn register is not used. Operation stop The TTmn bit is set to 1. The TTmn bit automatically returns to 0 because it is a TEmn = 0, and count operation stops. The TCRmn register holds count value and stops. trigger bit. TAU The TAUmEN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 400 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.8 Simultaneous Channel Operation Function of Timer Array Unit 6.8.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin. The delay time and pulse width can be calculated by the following expressions. Delay time = {Set value of TDRmn (master) + 2} x Count clock period Pulse width = {Set value of TDRmp (slave)} x Count clock period The master channel operates in the one-count mode and counts the delays. Timer count register mn (TCRmn) of the master channel starts operating upon start trigger detection and loads the value of timer data register mn (TDRmn). The TCRmn register counts down from the value of the TDRmn register it has loaded, in synchronization with the count clock. When TCRmn = 0000H, it outputs INTTMmn and stops counting until the next start trigger is detected. The slave channel operates in the one-count mode and counts the pulse width. The TCRmp register of the slave channel starts operation using INTTMmn of the master channel as a start trigger, and loads the value of the TDRmp register. The TCRmp register counts down from the value of The TDRmp register it has loaded, in synchronization with the count value. When count value = 0000H, it outputs INTTMmp and stops counting until the next start trigger (INTTMmn of the master channel) is detected. The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp = 0000H. Instead of using the TImn pin input, a one-shot pulse can also be output using the software operation (TSmn = 1) as a start trigger. Caution The timing of loading of timer data register mn (TDRmn) of the master channel is different from that of the TDRmp register of the slave channel. If the TDRmn and TDRmp registers are rewritten during operation, therefore, an illegal waveform is output. Rewrite the TDRmn register after INTTMmn is generated and the TDRmp register after INTTMmp is generated. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 401 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Block Diagram of Operation as One-Shot Pulse Output Function CKm1 Operation clock CKm0 TSmn <R> TImn pin Noise filter NFEN1 register Edge detection Trigger selection Clock selection Master channel (one-count mode) Timer counter register mn (TCRmn) Timer data register mn (TDRmn) Interrupt controller Timer counter register mp (TCRmp) Output controller Timer data register mp (TDRmp) Interrupt controller Interrupt signal (INTTMmn) CKm1 Operation clock Trigger selection CKm0 Clock selection Slave channel (one-count mode) Remark TOmp pin Interrupt signal (INTTMmp) m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 402 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master channel FFFFH TCRmn 0000H TDRmn a TOmn INTTMmn <R> TSmp TEmp FFFFH TCRmp Slave channel 0000H TDRmp b TOmp INTTMmp a+2 b a+2 b Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) 2. TSmn, TSmp: Bit n, p of timer channel start register m (TSm) TEmn, TEmp: Bit n, p of timer channel enable status register m (TEm) TImn, TImp: TImn and TImp pins input signal TCRmn, TCRmp: Timer count registers mn, mp (TCRmn, TCRmp) TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp) TOmn, TOmp: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 TOmn and TOmp pins output signal 403 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 0 12 CCSmn 0 0 11 10 9 8 7 6 5 4 MAS STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 TERmn 1 0 0 1 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1/0 0 0 1 0 0 0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. Selection of TImn pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 001B: Selects the TImn pin input valid edge. Slave/master selection 1: Master channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channels n. 10B: Selects CKm1 as operation clock of channels n. (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 0 (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 0: Stops the TOmn output operation by counting operation. 0 (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 404 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register mp (TMRmp) 15 TMRmp 14 13 CKSmp1 CKSmp0 1/0 0 12 11 CCSmp M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 1 0 0 0 3 2 1 0 MDmp3 MDmp2 MDmp1 MDmp0 0 1 0 0 0 Operation mode of channel p 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. Selection of TImp pin input edge 00B: Sets 00B because these are not used. Start trigger selection 100B: Selects INTTMmn of master channel. Setting of MASTERmn bit (channels 2, 4, 6) <R> 0: Independent channel operation function. Setting of SPLITmn bit (channels 1, 3) 1: 16-bit timer mode. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel p. 10B: Selects CKm1 as operation clock of channel p. * Make the same setting as master channel. (b) Timer output register m (TOm) Bit p TOm TOmp 0: Outputs 0 from TOmp. 1/0 1: Outputs 1 from TOmp. (c) Timer output enable register m (TOEm) Bit p TOEm TOEmp 1/0 0: Stops the TOmp output operation by counting operation. 1: Enables the TOmp output operation by counting operation. (d) Timer output level register m (TOLm) Bit p TOLm TOLmp 0: Positive logic output (active-high) 1/0 1: Negative logic output (active-low) (e) Timer output mode register m (TOMm) Bit p TOMm TOMmp 1: Sets the slave channel output mode. 1 <R> Note TMRm2, TMRm4, TMRm6: MASTERmn bit TMRm1, TMRm3: SPLITmp bit TMRm5, TMRm7: Fixed to 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 405 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable registers 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 and CKm1. Channel Sets timer mode register mn, mp (TMRmn, TMRmp) of Channel stops operating. default two channels to be used (determines operation mode of (Clock is supplied and some power is consumed.) setting channels). An output delay is set to timer data register mn (TDRmn) of the master channel, and a pulse width is set to the TDRmp register of the slave channel. Sets slave channel. The TOmp pin goes into Hi-Z output state. The TOMmp bit of timer output mode register m (TOMm) is set to 1 (slave channel output mode). Sets the TOLmp bit. Sets the TOmp bit and determines default level of the TOmp output. The TOmp default setting level is output when the port mode register is in output mode and the port register is 0. Sets the TOEmp bit to 1 and enables operation of TOmp. TOmp does not change because channel stops operating. Clears the port register and port mode register to 0. The TOmp pin outputs the TOmp set level. (Note and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 406 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure of One-Shot Pulse Output Function (2/2) <R> Software Operation Sets the TOEmp bit (slave) to 1 (only when operation is resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. The TSmn and TSmp bits automatically return to 0 because they are trigger bits. The TEmn and TEmp bits are set to 1 and the master channel enters the TImn input edge detection wait status. Counter stops operating. Detects the TImn pin input valid edge of master channel. Master channel starts counting. During operation Set values of only the CISmn1 and CISmn0 bits of the TMRmn register can be changed. Sets coresponting bit of noisefilter enable register 1, 2 (NFEN1, NFEN2) to 1. Set values of the TMRmp, TDRmn, TDRmp registers, TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be changed. The TCRmn and TCRmp registers can always be read. The TSRmn and TSRmp registers are not used. Set values of the TOm and TOEm registers by slave channel can be changed. Master channel loads the value of the TDRmn register to timer count register mn (TCRmn) when the TImn pin valid input edge is detected, and the counter starts counting down. When the count value reaches TCRmn = 0000H, the INTTMmn output is generated, and the counter stops until the next valid edge is input to the TImn pin. The slave channel, triggered by INTTMmn of the master channel, loads the value of the TDRmp register to the TCRmp register, and the counter starts counting down. The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel. It becomes inactive when TCRmp = 0000H, and the counting operation is stopped. After that, the above operation is repeated. Operation stop The TTmn (master) and TTmp (slave) bits are set to 1 at the same time. The TTmn and TTmp bits automatically return to 0 because they are trigger bits. Operation is resumed. Operation start Hardware Status TAU stop TEmn, TEmp = 0, and count operation stops. The TCRmn and TCRmp registers hold count value and stop. The TOmp output is not initialized but holds current status. The TOEmp bit of slave channel is cleared to 0 and value is set to the TOmp bit. The TOmp pin outputs the TOmp set level. To hold the TOmp pin output level Clears the TOmp bit to 0 after the value to be held is set to the port register. The TOmp pin output level is held by port function. When holding the TOmp pin output level is not necessary Setting not required. The TAUmEN bit of the PER0 register is cleared to 0. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TOmp bit is cleared to 0 and the TOmp pin is set to port mode.) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 407 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions. Pulse period = {Set value of TDRmn (master) + 1} x Count clock period Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} x 100 0% output: Set value of TDRmp (slave) = 0000H 100% output: Set value of TDRmp (slave) {Set value of TDRmn (master) + 1} Remark The duty factor exceeds 100% if the set value of TDRmp (slave) > (set value of TDRmn (master) + 1), it summarizes to 100% output. The master channel operates in the interval timer mode. If the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, an interrupt (INTTMmn) is output, the value set to timer data register mn (TDRmn) is loaded to timer count register mn (TCRmn), and the counter counts down in synchronization with the count clock. When the counter reaches 0000H, INTTMmn is output, the value of the TDRmn register is loaded again to the TCRmn register, and the counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop register m (TTm) is set to 1. If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the PWM output (TOmp) cycle. The slave channel operates in one-count mode. By using INTTMmn from the master channel as a start trigger, the TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H. When the counter reaches 0000H, it outputs INTTMmp and waits until the next start trigger (INTTMmn from the master channel) is generated. If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the PWM output (TOmp) duty. PWM output (TOmp) goes to the active level one clock after the master channel generates INTTMmn and goes to the inactive level when the TCRmp register of the slave channel becomes 0000H. Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the slave channel, a write access is necessary two times. The timing at which the values of the TDRmn and TDRmp registers are loaded to the TCRmn and TCRmp registers is upon occurrence of INTTMmn of the master channel. Thus, when rewriting is performed split before and after occurrence of INTTMmn of the master channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of the master and the TDRmp register of the slave, therefore, be sure to rewrite both the registers immediately after INTTMmn is generated from the master channel. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 408 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT CKm1 Operation clock CKm0 TSmn Trigger selection Master channel (interval timer mode) Clock selection Figure 6-70. Block Diagram of Operation as PWM Function Timer counter register mn (TCRmn) Timer data register mn (TDRmn) Interrupt controller Timer counter register mp (TCRmp) Output controller Timer data register mp (TDRmp) Interrupt controller Interrupt signal (INTTMmn) CKm1 Operation clock Trigger selection CKm0 Clock selection Slave channel (one-count mode) Remark TOmp pin Interrupt signal (INTTMmp) m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 409 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH Master channel TCRmn 0000H TDRmn a b TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave channel 0000H TDRmp c d TOmp INTTMmp a+1 c a+1 c b+1 d Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) 2. TSmn, TSmp: TEmn, TEmp: Bit n, p of timer channel start register m (TSm) Bit n, p of timer channel enable status register m (TEm) TCRmn, TCRmp: Timer count registers mn, mp (TCRmn, TCRmp) TDRmn, TDRmp: Timer data registers mn, mp (TDRmn, TDRmp) TOmn, TOmp: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 TOmn and TOmp pins output signal 410 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 0 11 10 9 8 7 6 5 4 0 0 MAS CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 TERmn CKSmn1 CKSmn0 1/0 12 0 0 1 0 0 0 0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 0 0 0 0 1 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 1: Generates INTTMmn when counting is started. Selection of TImn pin input edge 00B: Sets 00B because these are not used. Start trigger selection 000B: Selects only software start. Slave/master selection 1: Master channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n. (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 0 (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 0: Stops the TOmn output operation by counting operation. 0 (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 411 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register mp (TMRmp) 15 TMRmp 14 13 CKSmp1 CKSmp0 1/0 0 12 11 CCSmp M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 1 0 0 0 3 2 1 0 MDmp3 MDmp2 MDmp1 MDmp0 0 1 0 0 1 Operation mode of channel p 100B: One-count mode Start trigger during operation 1: Trigger input is valid. Selection of TImp pin input edge 00B: Sets 00B because these are not used. Start trigger selection 100B: Selects INTTMmn of master channel. Setting of SPLITmp bit 0: Slave channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel p. 10B: Selects CKm1 as operation clock of channel p. * Make the same setting as master channel. (b) Timer output register m (TOm) Bit p TOm TOmp 0: Outputs 0 from TOmp. 1/0 1: Outputs 1 from TOmp. (c) Timer output enable register m (TOEm) Bit p TOEm TOEmp 1/0 0: Stops the TOmp output operation by counting operation. 1: Enables the TOmp output operation by counting operation. (d) Timer output level register m (TOLm) Bit p TOLm TOLmp 0: Positive logic output (active-high) 1/0 1: Negative logic output (active-low) (e) Timer output mode register m (TOMm) Bit p TOMm TOMmp 1: Sets the slave channel output mode. 1 Note TMRm5, TMRm7: Fixed to 0 TMRm1, TMRm3: SPLITmp bit Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 412 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 and CKm1. Channel Sets timer mode registers mn, mp (TMRmn, TMRmp) of Channel stops operating. default two channels to be used (determines operation mode of (Clock is supplied and some power is consumed.) setting channels). An interval (period) value is set to timer data register mn (TDRmn) of the master channel, and a duty factor is set to the TDRmp register of the slave channel. Sets slave channel. The TOmp pin goes into Hi-Z output state. The TOMmp bit of timer output mode register m (TOMm) is set to 1 (slave channel output mode). Sets the TOLmp bit. Sets the TOmp bit and determines default level of the TOmp output. The TOmp default setting level is output when the port mode register is in output mode and the port register is 0. Sets the TOEmp bit to 1 and enables operation of TOmp. TOmp does not change because channel stops operating. Clears the port register and port mode register to 0. The TOmp pin outputs the TOmp set level. (Note and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 413 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When PWM Function Is Used (2/2) Software Operation Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). Hardware Status The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. TEmn = 1, TEmp = 1 When the master channel starts counting, INTTMmn is The TSmn and TSmp bits automatically return to 0 generated. Triggered by this interrupt, the slave because they are trigger bits. channel also starts counting. Set values of the TMRmn and TMRmp registers, The counter of the master channel loads the TDRmn operation TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be register value to timer count register mn (TCRmn), and changed. counts down. When the count value reaches TCRmn = Set values of the TDRmn and TDRmp registers can be 0000H, INTTMmn output is generated. At the same time, changed after INTTMmn of the master channel is the value of the TDRmn register is loaded to the TCRmn generated. register, and the counter starts counting down again. The TCRmn and TCRmp registers can always be read. At the slave channel, the value of the TDRmp register is The TSRmn and TSRmp registers are not used. loaded to the TCRmp register, triggered by INTTMmn of Operation is resumed. During the master channel, and the counter starts counting down. The output level of TOmp becomes active one count clock after generation of the INTTMmn output from the master channel. It becomes inactive when TCRmp = 0000H, and the counting operation is stopped. After that, the above operation is repeated. Operation The TTmn (master) and TTmp (slave) bits are set to 1 at stop the same time. TEmn, TEmp = 0, and count operation stops. The TTmn and TTmp bits automatically return to 0 The TCRmn and TCRmp registers hold count value and because they are trigger bits. stop. The TOmp output is not initialized but holds current status. The TOEmp bit of slave channel is cleared to 0 and value is set to the TOmp bit. TAU stop The TOmp pin outputs the TOmp set level. To hold the TOmp pin output level Clears the TOmp bit to 0 after the value to The TOmp pin output level is held by port function. be held is set to the port register. When holding the TOmp pin output level is not necessary Setting not required. The TAUmEN bit of the PER0 register is cleared to 0. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TOmp bit is cleared to 0 and the TOmp pin is set to port mode.) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 414 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions. Pulse period = {Set value of TDRmn (master) + 1} x Count clock period Duty factor 1 [%] = {Set value of TDRmp (slave 1)}/{Set value of TDRmn (master) + 1} x 100 Duty factor 2 [%] = {Set value of TDRmq (slave 2)}/{Set value of TDRmn (master) + 1} x 100 Remark Although the duty factor exceeds 100% if the set value of TDRmp (slave 1) > {set value of TDRmn (master) + 1} or if the {set value of TDRmq (slave 2)} > {set value of TDRmn (master) + 1}, it is summarized into 100% output. Timer count register mn (TCRmn) of the master channel operates in the interval timer mode and counts the periods. The TCRmp register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmp pin. The TCRmp register loads the value of timer data register mp (TDRmp), using INTTMmn of the master channel as a start trigger, and starts counting down. When TCRmp = 0000H, TCRmp outputs INTTMmp and stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmp = 0000H. In the same way as the TCRmp register of the slave channel 1, the TCRmq register of the slave channel 2 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from the TOmq pin. The TCRmq register loads the value of the TDRmq register, using INTTMmn of the master channel as a start trigger, and starts counting down. When TCRmq = 0000H, the TCRmq register outputs INTTMmq and stops counting until the next start trigger (INTTMmn of the master channel) has been input. The output level of TOmq becomes active one count clock after generation of INTTMmn from the master channel, and inactive when TCRmq = 0000H. When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the same time. Caution To rewrite both timer data register mn (TDRmn) of the master channel and the TDRmp register of the slave channel 1, write access is necessary at least twice. Since the values of the TDRmn and TDRmp registers are loaded to the TCRmn and TCRmp registers after INTTMmn is generated from the master channel, if rewriting is performed separately before and after generation of INTTMmn from the master channel, the TOmp pin cannot output the expected waveform. To rewrite both the TDRmn register of the master and the TDRmp register of the slave, be sure to rewrite both the registers immediately after INTTMmn is generated from the master channel (This applies also to the TDRmq register of the slave channel 2). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 <R> n < p < q 7 (Where p and q are integers greater than n) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 415 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT CKm1 Operation clock CKm0 TSmn Trigger selection Master channel (interval timer mode) Clock selection Figure 6-75. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Timer counter register mn (TCRmn) Timer data register mn (TDRmn) Interrupt controller Timer counter register mp (TCRmp) Output controller Timer data register mp (TDRmp) Interrupt controller Timer counter register mq (TCRmq) Output controller Timer data register mq (TDRmq) Interrupt controller Interrupt signal (INTTMmn) Operation clock CKm1 Trigger selection CKm0 Clock selection Slave channel 1 (one-count mode) TOmp pin Interrupt signal (INTTMmp) CKm1 Operation clock Trigger selection CKm0 Clock selection Slave channel 2 (one-count mode) Remark TOmq pin Interrupt signal (INTTMmq) m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 <R> n < p < q 7 (Where p and q are integers greater than n) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 416 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) TSmn TEmn FFFFH Master channel TCRmn 0000H TDRmn a b TOmn INTTMmn TSmp TEmp FFFFH Slave channel 1 TCRmp 0000H TDRmp c d TOmp INTTMmp a+1 a+1 c c b+1 d d TSmq TEmq FFFFH Slave channel 2 TCRmq 0000H TDRmq e f TOmq INTTMmq a+1 e a+1 e b+1 f f (Remark is listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 417 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Remark 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are integers greater than n) 2. TSmn, TSmp, TSmq: TEmn, TEmp, TEmq: Bit n, p, q of timer channel start register m (TSm) Bit n, p, q of timer channel enable status register m (TEm) TCRmn, TCRmp, TCRmq: Timer count registers mn, mp, mq (TCRmn, TCRmp, TCRmq) TDRmn, TDRmp, TDRmq: Timer data registers mn, mp, mq (TDRmn, TDRmp, TDRmq) TOmn, TOmp, TOmq: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 TOmn, TOmp, and TOmq pins output signal 418 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 0 11 10 9 8 7 6 5 4 0 0 MAS CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 TERmn CKSmn1 CKSmn0 1/0 12 0 0 1 0 0 0 0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 0 0 0 0 1 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 1: Generates INTTMmn when counting is started. Selection of TImn pin input edge 00B: Sets 00B because these are not used. Start trigger selection 000B: Selects only software start. Slave/master selection 1: Master channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel n. 10B: Selects CKm1 as operation clock of channel n. (b) Timer output register m (TOm) Bit n TOm TOmn 0: Outputs 0 from TOmn. 0 (c) Timer output enable register m (TOEm) Bit n TOEm TOEmn 0: Stops the TOmn output operation by counting operation. 0 (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 419 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-78. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (a) Timer mode register mp, mq (TMRmp, TMRmq) 15 TMRmp TMRmq 14 13 CKSmp1 CKSmp0 0 0 15 14 13 CKSmq1 CKSmq0 0 11 CCSmp M/S 1/0 1/0 12 0 0 12 11 CCSmq M/S 0 Note 0 Note 0 10 9 8 7 6 5 4 3 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 0 0 0 0 0 0 10 9 8 7 6 5 4 STSmq2 STSmq1 STSmq0 CISmq1 CISmq0 0 0 0 0 1 0 MDmp3 MDmp2 MDmp1 MDmp0 1 1 2 1 0 0 1 3 2 1 0 MDmq3 MDmq2 MDmq1 MDmq0 0 1 0 0 0 1 Operation mode of channel p, q 100B: One-count mode Start trigger during operation 1: Trigger input is valid. Selection of TImp and TImq pins input edge 00B: Sets 00B because these are not used. Start trigger selection 100B: Selects INTTMmn of master channel. <R> Setting of MASTERmp, MASTERmq bits (channels 2, 4, 6) 0: Independent channel operation function. Setting of SPLITmp, SPLITmq bits (channels 1, 3) 1: 16-bit timer mode. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CKm0 as operation clock of channel p, q. 10B: Selects CKm1 as operation clock of channel p, q. * Make the same setting as master channel. (b) Timer output register m (TOm) TOm Bit q Bit p TOmq TOmp 1/0 1/0 0: Outputs 0 from TOmp or TOmq. 1: Outputs 1 from TOmp or TOmq. (c) Timer output enable register m (TOEm) Bit q TOEm Bit p TOEmq TOEmp 1/0 1/0 0: Stops the TOmp or TOmq output operation by counting operation. 1: Enables the TOmp or TOmq output operation by counting operation. (d) Timer output level register m (TOLm) Bit q TOLm Bit p TOLmq TOLmp 1/0 1/0 0: Positive logic output (active-high) 1: Negative logic output (active-low) (e) Timer output mode register m (TOMm) Bit q TOMm Bit p TOMmq TOMmp 1 1: Sets the slave channel output mode. 1 Note TMRm2, TMRm4, TMRm6: MASTERmp, MASTERmq bit TMRm1, TMRm3: SPLITmp, SPLIT0q bit TMRm5, TMRm7: Fixed to 0 Remark <R> m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are integers greater than n) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 420 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Operation Procedure When Multiple PWM Output Function Is Used (1/2) <R> Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm). Determines clock frequencies of CKm0 and CKm1. Channel Sets timer mode registers mn, mp, 0q (TMRmn, TMRmp, Channel stops operating. default TMRmq) of each channel to be used (determines (Clock is supplied and some power is consumed.) setting operation mode of channels). An interval (period) value is set to timer data register mn (TDRmn) of the master channel, and a duty factor is set to the TDRmp and TDRmq registers of the slave channels. Sets slave channels. The TOmp and TOmq pins go into Hi-Z output state. The TOMmp and TOMmq bits of timer output mode register m (TOMm) are set to 1 (slave channel output mode). Sets the TOLmp and TOLmq bits. Sets the TOmp and TOmq bits and determines default level of the TOmp and TOmq outputs. The TOmp and TOmq default setting levels are output when the port mode register is in output mode and the port register is 0. Sets the TOEmp and TOEmq bits to 1 and enables operation of TOmp and TOmq. TOmp and TOmq do not change because channels stop operating. Clears the port register and port mode register to 0. The TOmp and TOmq pins output the TOmp and TOmq set levels. (Note and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 421 RL78/G13 CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.) start The TSmn bit (master), and TSmp and TSmq (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. The TSmn, TSmp, and TSmq bits automatically return to 0 because they are trigger bits. Set values of the TMRmn, TMRmp, TMRmq registers, TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and TOLmq bits cannot be changed. Set values of the TDRmn, TDRmp, and TDRmq registers can be changed after INTTMmn of the master channel is generated. The TCRmn, TCRmp, and TCRmq registers can always be read. The TSRmn, TSRmp, and TSR0q registers are not used. Operation stop The TTmn bit (master), TTmp, and TTmq (slave) bits are set to 1 at the same time. The TTmn, TTmp, and TTmq bits automatically return to 0 because they are trigger bits. Operation is resumed. During operation The TOEmp and TOEmq bits of slave channels are cleared to 0 and value is set to the TOmp and TOmq bits. TAU stop To hold the TOmp and TOmq pin output levels Clears the TOmp and TOmq bits to 0 after the value to be held is set to the port register. When holding the TOmp and TOmq pin output levels are not necessary Setting not required The TAUmEN bit of the PER0 register is cleared to 0. Remark Hardware Status TEmn = 1, TEmp, TEmq = 1 When the master channel starts counting, INTTMmn is generated. Triggered by this interrupt, the slave channel also starts counting. The counter of the master channel loads the TDRmn register value to timer count register mn (TCRmn) and counts down. When the count value reaches TCRmn = 0000H, INTTMmn output is generated. At the same time, the value of the TDRmn register is loaded to the TCRmn register, and the counter starts counting down again. At the slave channel 1, the values of the TDRmp register are transferred to the TCRmp register, triggered by INTTMmn of the master channel, and the counter starts counting down. The output levels of TOmp become active one count clock after generation of the INTTMmn output from the master channel. It becomes inactive when TCRmp = 0000H, and the counting operation is stopped. At the slave channel 2, the values of the TDRmq register are transferred to TCRmq regster, triggered by INTTMmn of the master channel, and the counter starts counting down. The output levels of TOmq become active one count clock after generation of the INTTMmn output from the master channel. It becomes inactive when TCRmq = 0000H, and the counting operation is stopped. After that, the above operation is repeated. TEmn, TEmp, TEmq = 0, and count operation stops. The TCRmn, TCRmp, and TCRmq registers hold count value and stop. The TOmp and TOmq output are not initialized but hold current status. The TOmp and TOmq pins output the TOmp and TOmq set levels. The TOmp and TOmq pin output levels are held by port function. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TOmp and TOmq bits are cleared to 0 and the TOmp and TOmq pins are set to port mode.) m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are a consecutive integer greater than n) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 422 RL78/G13 6.9 CHAPTER 6 TIMER ARRAY UNIT Cautions When Using Timer Array Unit 6.9.1 Cautions When Using Timer output Depends on products, a pin is assigned atimer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status. (1) 20-pin products (a) Using TO01 output assigned to the P16 So that the alternated SO11 output becomes 1, not only set the port mode register (the PM16 bit) and the port register (the P16 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status. (b) Using TO02 output assigned to the P17 So that the alternated SDA11 output becomes 1, not only set the port mode register (the PM17 bit) and the port register (the P17 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status. (2) 24- and 25-pin products (a) Using TO02 output assigned to the P17 So that the alternated SO11 output becomes 1, not only set the port mode register (the PM17 bit) and the port register (the P17 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status. (b) Using TO03 output assigned to the P31 So that the alternated PCLBUZ0 output becomes 0, not only set the port mode register (the PM31 bit) and the port register (the P31 bit) to 0, but also use the bit 7 of the clock output select register 0 (CKS0) with the same setting as the initial status. (3) 30- to 44-pin products (a) Using TO03 output assigned to the P31 (When PIOR = 0) So that the alternated PCLBUZ0 output becomes 0, not only set the port mode register (the PM31 bit) and the port register (the P31 bit) to 0, but also use the bit 7 of the clock output select register 0 (CKS0) with the same setting as the initial status. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 423 RL78/G13 CHAPTER 7 REAL-TIME CLOCK CHAPTER 7 REAL-TIME CLOCK 7.1 Functions of Real-time Clock The real-time clock has the following features. * Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. * Constant-period interrupt function (period: 0.5 seconds, 1 second, 1 minute, 1 hour, 1 day, 1 month) * Alarm interrupt function (alarm: week, hour, minute) * Pin output function of 1 Hz (40, 44, 48, 52, 64, 80, 100, and 128-pin products only) Caution The count of year, month, week, day, hour, minutes and second can only be performed when a subsystem clock (fSUB = 32.768 kHz) is selected as the operation clock of the real-time clock. When the low-speed oscillation clock (fIL = 15 kHz) is selected, only the constant-period interrupt function is available. The 20- to 36-pin products have the constant-period interrupt function only, because these products have no subsystem clock. However, the constant-period interrupt interval when fIL is selected will be calculated with the constant-period (the value selected with RTCC0 register) x fSUB/fIL. 7.2 Configuration of Real-time Clock The real-time clock includes the following hardware. Table 7-1. Configuration of Real-time Clock Item Configuration Counter Counter (16-bit) Control registers Peripheral enable register 0 (PER0) Operation speed mode control register (OSMC) Real-time clock control register 0 (RTCC0) Real-time clock control register 1 (RTCC1) Second count register (SEC) Minute count register (MIN) Hour count register (HOUR) Day count register (DAY) Week count register (WEEK) Month count register (MONTH) Year count register (YEAR) Watch error correction register (SUBCUD) Alarm minute register (ALARMWM) Alarm hour register (ALARMWH) Alarm week register (ALARMWW) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 424 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Figure 7-1. Block Diagram of Real-time Clock Real-time clock control register 1 WALE WALIE WAFG RIFG Real-time clock control register 0 RTCE RCLOE1 AMPM RWST RWAIT Alarm week register (ALARMWW) (7-bit) Alarm hour register (ALARMWH) (6-bit) CT2 CT1 CT0 WUTMM CK0 Operation speed mode control register (OSMC) RTC1HZ Alarm minute register (ALARMWM) (7-bit) INTRTC CT0 to CT2 Selector RIFG AMPM Month count register (MONTH) (5-bit) Week count register (WEEK) (3-bit) Day count register (DAY) (6-bit) 1 hour Hour count register (HOUR) (6-bit) 1 minute Minute count register (MIN) (7-bit) RWST RWAIT 0.5 seconds 1 seconds Second Internal count counter register Wait control (SEC) (16-bit) (7-bit) Count enable/ disable circuit Buffer Buffer Buffer Buffer Buffer Buffer Buffer RTCE fRTC Watch error correction register (SUBCUD) (8-bit) Selector Year count register (YEAR) (8-bit) 1 day 1 month 1 year fSUB fIL WUTMMCK0 Internal bus Caution The count of year, month, week, day, hour, minutes and second can only be performed when a subsystem clock (fSUB = 32.768 kHz) is selected as the operation clock of the real-time clock. When the low-speed oscillation clock (fIL = 15 kHz) is selected, only the constant-period interrupt function is available. The 20- to 36-pin products have the constant-period interrupt function only, because these products have no subsystem clock. However, the constant-period interrupt interval when fIL is selected will be calculated with the constant-period (the value selected with RTCC0 register) x fSUB/fIL. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 425 RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers. * Peripheral enable register 0 (PER0) * Operation speed mode control register (OSMC) * Real-time clock control register 0 (RTCC0) * Real-time clock control register 1 (RTCC1) * Second count register (SEC) * Minute count register (MIN) * Hour count register (HOUR) * Day count register (DAY) * Week count register (WEEK) * Month count register (MONTH) * Year count register (YEAR) * Watch error correction register (SUBCUD) * Alarm minute register (ALARMWM) * Alarm hour register (ALARMWH) * Alarm week register (ALARMWW) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 426 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (1) Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the real-time clock is used, be sure to set bit 7 (RTCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-2. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note 2 Note 3 Note 1 RTCEN Note 1 Control of real-time clock (RTC) and 12-bit interval timer input clock supply Stops input clock supply. 0 * SFR used by the real-time clock (RTC) and 12-bit interval timer cannot be written. * The real-time clock (RTC) and 12-bit interval timer are in the reset status. Enables input clock supply. 1 * SFR used by the real-time clock (RTC) and 12-bit interval timer can be read and written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Cautions 1. When using the real-time clock, first set the RTCEN bit to 1, while oscillation of the input clock (fRTC) is stable. If RTCEN = 0, writing to a control register of the real-time clock or 12-bit interval timer is ignored, and, even if the register is read, only the default value is read. 2. The subsystem clock supply to peripheral functions other than the real-time clock and 12-bit interval timer can be stopped in STOP mode or HALT mode when the subsystem clock is used, by setting the RTCLPC bit of the operation speed mode control register (OSMC) to 1. In this case, set the RTCEN bit of the PER0 register to 1 and the other bits (bits 0 to 6) to 0. 3. Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 427 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (2) Operation speed mode control register (OSMC) The WUTMMCK0 bit can be used to select the real-time clock operation clock (fRTC). In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-3. Format of Operation Speed Mode Control Register (OSMC) Address: F00F3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0 WUTMMCK0 Caution Selection of operation clock (fRTC) for real-time clock and 12-bit interval timer. 0 Subsystem clock (fSUB) 1 Low-speed on-chip oscillator clock (fIL) The count of year, month, week, day, hour, minutes and second can only be performed when a subsystem clock (fSUB = 32.768 kHz) is selected as the operation clock of the real-time clock. When the low-speed oscillation clock (fIL = 15 kHz) is selected, only the constant-period interrupt function is available. The 20- to 36-pin products have the constant-period interrupt function only, because these products have no subsystem clock. However, the constant-period interrupt interval when fIL is selected will be calculated with the constant-period (the value selected with RTCC0 register) x fSUB/fIL. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 428 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (3) Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function. The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-4. Format of Real-time Clock Control Register 0 (RTCC0) Address: FFF9DH After reset: 00H R/W Symbol <7> 6 <5> 4 3 2 1 0 RTCC0 RTCE 0 RCLOE1 0 AMPM CT2 CT1 CT0 RTCE Real-time clock operation control 0 Stops counter operation. 1 Starts counter operation. RCLOE1 RTC1HZ pin output control 0 Disables output of the RTC1HZ pin (1 Hz). 1 Enables output of the RTC1HZ pin (1 Hz). AMPM Selection of 12-/24-hour system 0 12-hour system (a.m. and p.m. are displayed.) 1 24-hour system * Rewrite the AMPM bit value after setting the RWAIT bit (bit 0 of real-time clock control register 1 (RTCC1)) to 1. If the AMPM bit value is changed, the values of the hour count register (HOUR) change according to the specified time system. * Table 7-2 shows the displayed time digits that are displayed. CT2 CT1 CT0 Constant-period interrupt (INTRTC) selection 0 0 0 Does not use constant-period interrupt function. 0 0 1 Once per 0.5 s (synchronized with second count up) 0 1 0 Once per 1 s (same time as second count up) 0 1 1 Once per 1 m (second 00 of every minute) 1 0 0 Once per 1 hour (minute 00 and second 00 of every hour) 1 0 1 Once per 1 day (hour 00, minute 00, and second 00 of every day) 1 1 x Once per 1 month (Day 1, hour 00 a.m., minute 00, and second 00 of every month) When changing the values of the CT2 to CT0 bits while the counter operates (RTCE = 1), rewrite the values of the CT2 to CT0 bits after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, after rewriting the values of the CT2 to CT0 bits, enable interrupt servicing after clearing the RIFG and RTCIF flags. Caution Do not change the value of the RTCLOE1 bit when RTCE = 1. Remark x: don't care R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 429 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (4) Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (1/2) Address: FFF9EH After reset: 00H R/W Symbol <7> <6> 5 <4> <3> 2 <1> <0> RTCC1 WALE WALIE 0 WAFG RIFG 0 RWST RWAIT WALE Alarm operation control 0 Match operation is invalid. 1 Match operation is valid. When setting a value to the WALE bit while the counter operates (RTCE = 1) and WALIE = 1, rewrite the WALE bit after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG and RTCIF flags after rewriting the WALE bit. When setting each alarm register (WALIE flag of real-time clock control register 1 (RTCC1), the alarm minute register (ALARMWM), the alarm hour register (ALARMWH), and the alarm week register (ALARMWW)), set match operation to be invalid ("0") for the WALE bit. WALIE Control of alarm interrupt (INTRTC) function operation 0 Does not generate interrupt on matching of alarm. 1 Generates interrupt on matching of alarm. WAFG Alarm detection status flag 0 Alarm mismatch 1 Detection of matching of alarm This is a status flag that indicates detection of matching with the alarm. It is valid only when WALE = 1 and is set to "1" one clock (32.768 kHz) after matching of the alarm is detected. This flag is cleared when "0" is written to it. Writing "1" to it is invalid. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 430 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag 0 Constant-period interrupt is not generated. 1 Constant-period interrupt is generated. This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is generated, it is set to "1". This flag is cleared when "0" is written to it. Writing "1" to it is invalid. RWST Wait status flag of real-time clock 0 Counter is operating. 1 Mode to read or write counter value This status flag indicates whether the setting of the RWAIT bit is valid. Before reading or writing the counter value, confirm that the value of this flag is 1. RWAIT Wait control of real-time clock 0 Sets counter operation. 1 Stops SEC to YEAR counters. Mode to read or write counter value This bit controls the operation of the counter. Be sure to write "1" to it to read or write the counter value. As the counter (16-bit) is continuing to run, complete reading or writing within one second and turn back to 0. When RWAIT = 1, it takes up to 1 clock (fRTC) until the counter value can be read or written (RWST = 1). When the counter (16-bit) overflowed while RWAIT = 1, it keeps the event of overflow until RWAIT = 0, then counts up. However, when it wrote a value to second count register, it will not keep the overflow event. Caution If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the RIFG flag and WAFG flag may be cleared. Therefore, to perform writing to the RTCC1 register, be sure to use an 8-bit manipulation instruction. To prevent the RIFG flag and WAFG flag from being cleared during writing, disable writing by setting 1 to the corresponding bit. If the RIFG flag and WAFG flag are not used and the value may be changed, the RTCC1 register may be written by using a 1-bit manipulation instruction. Remark Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using these two types of interrupts at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC occurrence. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 431 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (5) Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the counter (16-bit) overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Set a <R> decimal value of 00 to 59 to this register in BCD code. The SEC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-6. Format of Second Count Register (SEC) Address: FFF92H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 SEC 0 SEC40 SEC20 SEC10 SEC8 SEC4 SEC2 SEC1 Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow the procedures described in the section 7.4.3 Reading/writing real-time clock. (6) Minute count register (MIN) The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even if the second count register overflows while this register is being written, this register ignores the overflow and is set <R> to the value written. Set a decimal value of 00 to 59 to this register in BCD code. The MIN register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-7. Format of Minute Count Register (MIN) Address: FFF93H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 MIN 0 MIN40 MIN20 MIN10 MIN8 MIN4 MIN2 MIN1 Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow the procedures described in the section 7.4.3 Reading/writing real-time clock. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 432 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (7) Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even if the minute count register overflows while this register is being written, this register ignores the overflow and is set to the value written. Specify a decimal value of 00 to 23, 01 to 12, or 21 to 32 by using BCD code according to the time system specified using bit 3 (AMPM) of real-time clock control register 0 (RTCC0). If the AMPM bit value is changed, the values of the HOUR register change according to the specified time system. <R> The HOUR register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 12H. However, the value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset. Figure 7-8. Format of Hour Count Register (HOUR) Address: FFF94H After reset: 12H R/W Symbol 7 6 5 4 3 2 1 0 HOUR 0 0 HOUR20 HOUR10 HOUR8 HOUR4 HOUR2 HOUR1 Cautions 1. Bit 5 (HOUR20) of the HOUR register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is selected). 2. When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow the procedures described in the section 7.4.3 Reading/writing real-time clock. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 433 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Table 7-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 7-2. Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 1) Time HOUR Register Time HOUR Register 0 00H 12 a.m. 12H 1 01H 1 a.m. 01H 2 02H 2 a.m. 02H 3 03H 3 a.m. 03H 4 04H 4 a.m. 04H 5 05H 5 a.m. 05H 6 06H 6 a.m. 06H 7 07H 7 a.m. 07H 8 08H 8 a.m. 08H 9 09H 9 a.m. 09H 10 10H 10 a.m. 10H 11 11H 11 a.m. 11H 12 12H 12 p.m. 32H 13 13H 1 p.m. 21H 14 14H 2 p.m. 22H 15 15H 3 p.m. 23H 16 16H 4 p.m. 24H 17 17H 5 p.m. 25H 18 18H 6 p.m. 26H 19 19H 7 p.m. 27H 20 20H 8 p.m. 28H 21 21H 9 p.m. 29H 22 22H 10 p.m. 30H 23 23H 11 p.m. 31H The HOUR register value is set to 12-hour display when the AMPM bit is "0" and to 24-hour display when the AMPM bit is "1". In 12-hour display, the fifth bit of the HOUR register displays 0 for AM and 1 for PM. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 434 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (8) Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows. * 01 to 31 (January, March, May, July, August, October, December) * 01 to 30 (April, June, September, November) * 01 to 29 (February, leap year) * 01 to 28 (February, normal year) When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even if the hour count register overflows while this register is being written, this register ignores the overflow and is set to <R> the value written. Set a decimal value of 01 to 31 to this register in BCD code. The DAY register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 01H. Figure 7-9. Format of Day Count Register (DAY) Address: FFF96H After reset: 01H R/W Symbol 7 6 5 4 3 2 1 0 DAY 0 0 DAY20 DAY10 DAY8 DAY4 DAY2 DAY1 Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow the procedures described in the section 7.4.3 Reading/writing real-time clock. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 435 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (9) Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Set a <R> decimal value of 00 to 06 to this register in BCD code. The WEEK register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-10. Format of Week Count Register (WEEK) Address: FFF95H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 WEEK 0 0 0 0 0 WEEK4 WEEK2 WEEK1 Cautions 1. The value corresponding to the month count register (MONTH) or the day count register (DAY) is not stored in the week count register (WEEK) automatically. After reset release, set the week count register as follow. Day WEEK Sunday 00H Monday 01H Tuesday 02H Wednesday 03H Thursday 04H Friday 05H Saturday 06H 2. When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow the procedures described in the section 7.4.3 Reading/writing real-time clock. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 436 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (10) Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even if the day count register overflows while this register is being written, this register ignores the overflow and is set to <R> the value written. Set a decimal value of 01 to 12 to this register in BCD code. The MONTH register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 01H. Figure 7-11. Format of Month Count Register (MONTH) Address: FFF97H After reset: 01H R/W Symbol 7 6 5 4 3 2 1 0 MONTH 0 0 0 MONTH10 MONTH8 MONTH4 MONTH2 MONTH1 Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow the procedures described in the section 7.4.3 Reading/writing real-time clock. (11) Year count register (YEAR) The YEAR register is an 8-bit register that takes a value of 0 to 99 (decimal) and indicates the count value of years. It counts up when the month count register (MONTH) overflows. Values 00, 04, 08, ..., 92, and 96 indicate a leap year. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (fRTC) later. Even if the MONTH register overflows while this register is being written, this register ignores the overflow and is set to <R> the value written. Set a decimal value of 00 to 99 to this register in BCD code. The YEAR register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-12. Format of Year Count Register (YEAR) Address: FFF98H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 YEAR YEAR80 YEAR40 YEAR20 YEAR10 YEAR8 YEAR4 YEAR2 YEAR1 Caution When it reads or writes from/to the register while the counter is in operation (RTCE = 1), follow the procedures described in the section 7.4.3 Reading/writing real-time clock. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 437 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (12) Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the counter (16-bit) to the second count register (SEC) (reference value: 7FFFH). The SUBCUD register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-13. Format of Watch Error Correction Register (SUBCUD) Address: FFF99H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 SUBCUD DEV F6 F5 F4 F3 F2 F1 F0 DEV Setting of watch error correction timing 0 Corrects watch error when the second digits are at 00, 20, or 40 (every 20 seconds). 1 Corrects watch error only when the second digits are at 00 (every 60 seconds). Writing to the SUBCUD register at the following timing is prohibited. * When DEV = 0 is set: For a period of SEC = 00H, 20H, 40H * When DEV = 1 is set: For a period of SEC = 00H F6 Setting of watch error correction value 0 Increases by {(F5, F4, F3, F2, F1, F0) - 1} x 2. 1 Decreases by {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} x 2. When (F6, F5, F4, F3, F2, F1, F0) = (*, 0, 0, 0, 0, 0, *), the watch error is not corrected. * is 0 or 1. /F5 to /F0 are the inverted values of the corresponding bits (000011 when 111100). Range of correction value: (when F6 = 0) 2, 4, 6, 8, ... , 120, 122, 124 (when F6 = 1) -2, -4, -6, -8, ... , -120, -122, -124 The range of value that can be corrected by using the watch error correction register (SUBCUD) is shown below. DEV = 0 (correction every 20 seconds) DEV = 1 (correction every 60 seconds) Correctable range -189.2 ppm to 189.2 ppm -63.1 ppm to 63.1 ppm Maximum excludes 1.53 ppm 0.51 ppm 3.05 ppm 1.02 ppm quantization error Minimum resolution Remark If a correctable range is -63.1 ppm or lower and 63.1 ppm or higher, set 0 to DEV. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 438 RL78/G13 CHAPTER 7 REAL-TIME CLOCK (13) Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected. Figure 7-14. Format of Alarm Minute Register (ALARMWM) Address: FFF9AH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ALARMWM 0 WM40 WM20 WM10 WM8 WM4 WM2 WM1 (14) Alarm hour register (ALARMWH) This register is used to set hours of alarm. The ALARMWH register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 12H. However, the value of this register is 00H if the AMPM bit (bit 3 of the RTCC0 register) is set to 1 after reset. Caution Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value outside the range is set, the alarm is not detected. Figure 7-15. Format of Alarm Hour Register (ALARMWH) Address: FFF9BH After reset: 12H R/W Symbol 7 6 5 4 3 2 1 0 ALARMWH 0 0 WH20 WH10 WH8 WH4 WH2 WH1 Caution Bit 5 (WH20) of the ALARMWH register indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system is selected). (15) Alarm week register (ALARMWW) This register is used to set date of alarm. The ALARMWW register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-16. Format of Alarm Week Register (ALARMWW) Address: FFF9CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ALARMWW 0 WW6 WW5 WW4 WW3 WW2 WW1 WW0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 439 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Here is an example of setting the alarm. Time of Alarm Day 12-Hour Display Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour Hour 24-Hour Display Hour Hour 10 1 Minute Minute 10 1 10 1 Minute Minute 10 1 W W W W W W W W W W W W W W 0 1 2 3 4 5 6 Every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 Every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 Every day, 11:59 a.m. 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 Monday through 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 Sunday, 1:30 p.m. 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 Monday, Wednesday, 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 Friday, 0:00 p.m. Friday, 11:59 p.m. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 440 RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4 Real-time Clock Operation 7.4.1 Starting operation of real-time clock Figure 7-17. Procedure for Starting Operation of Real-time Clock Start RTCEN = 1Note 1 RTCE = 0 Setting WUTMMCK0 Setting AMPM, CT2 to CT0 Supplies input clock. Stops counter operation. Sets fRTC Selects 12-/24-hour system and interrupt (INTRTC). Setting SEC Sets second count register. Setting MIN Sets minute count register. Setting HOUR Sets hour count register. Setting WEEK Sets week count register. Setting DAY Setting MONTH Setting YEAR Setting SUBCUDNote 2 Sets day count register. Sets month count register. Sets year count register. Sets watch error correction register. Clearing IF flags of interrupt Clears interrupt request flags (RTCIF). Clearing MK flags of interrupt Clears interrupt mask flags (RTCMK). RTCE = 1Note 3 Starts counter operation. Yes No INTRTC = 1? End Notes 1. First set the RTCEN bit to 1, while oscillation of the input clock (fRTC) is stable. 2. Set up the SUBCUD register only if the watch error must be corrected. For details about how to calculate the correction value, see 7.4.6 Example of watch error correction of real-time clock. 3. Confirm the procedure described in 7.4.2 Shifting to HALT/STOP mode after starting operation when shifting to HALT/STOP mode without waiting for INTRTC = 1 after RTCE = 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 441 RL78/G13 CHAPTER 7 REAL-TIME CLOCK <R> 7.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after the INTRTC interrupt has occurred. * Shifting to HALT/STOP mode when at least two input clocks (fRTC) have elapsed after setting the RTCE bit to 1 (see Figure 7-18, Example 1). * Checking by polling the RWST bit to become 1, after setting the RTCE bit to 1 and then setting the RWAIT bit to 1. Afterward, setting the RWAIT bit to 0 and shifting to HALT/STOP mode after checking again by polling that the RWST bit has become 0 (see Figure 7-18, Example 2). Figure 7-18. Procedure for Shifting to HALT/STOP Mode After Setting RTCE bit to 1 Example 2 Example 1 Sets to counter operation RTCE = 1 RTCE = 1 Sets to counter operation start start Sets to stop the SEC to YEAR RWAIT = 1 Waiting at least for 2 HALT/STOP instruction execution counters, reads the counter value, write mode fRTC clocks No RWST = 1? Checks the counter wait status Shifts to HALT/STOP mode Yes RWAIT = 0 No Sets the counter operation RWST = 0 ? Yes HALT/STOP instruction Shifts to HALT/STOP mode execution R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 442 RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. Figure 7-19. Procedure for Reading Real-time Clock Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Reading SEC Reads second count register. Reading MIN Reads minute count register. Reading HOUR Reads hour count register. Reading WEEK Reads week count register. Reading DAY Reading MONTH Reading YEAR RWAIT = 0 No Reads day count register. Reads month count register. Reads year count register. Sets counter operation. RWST = 0?Note Yes End Note Be sure to confirm that RWST = 0 before setting STOP mode. Caution Complete the series of process of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1 second. Remark The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR) may be read in any sequence. All the registers do not have to read and only some registers may be read. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 443 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Figure 7-20. Procedure for Writing Real-time Clock Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Writing SEC Writes second count register. Writing MIN Writes minute count register. Writing HOUR Writes hour count register. Writing WEEK Writes week count register. Writing DAY Writing MONTH No Writes day count register. Writes month count register. Writing YEAR Writes year count register. RWAIT = 0 Sets counter operation. RWST = 0?Note Yes End Note Be sure to confirm that RWST = 0 before setting STOP mode. Cautions 1. Complete the series of operations of setting the RWAIT bit to 1 to clearing the RWAIT bit to 0 within 1 second. 2. When changing the values of the SEC, MIN, HOUR, WEEK, DAY, MONTH, and YEAR register while the counter operates (RTCE = 1), rewrite the values of the MIN register after disabling interrupt servicing INTRTC by using the interrupt mask flag register. Furthermore, clear the WAFG, RIFG and RTCIF flags after rewriting the MIN register. Remark The second count register (SEC), minute count register (MIN), hour count register (HOUR), week count register (WEEK), day count register (DAY), month count register (MONTH), and year count register (YEAR) may be written in any sequence. All the registers do not have to be set and only some registers may be written. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 444 RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE (alarm operation invalid.) first. Figure 7-21. Alarm processing Procedure Start WALE = 0 Match operation of alarm is invalid. WALIE = 1 alarm match interrupts is valid.. Setting ALARMWM Sets alarm minute register. Setting ALARMWH Sets alarm hour register. Setting ALARMWW Sets alarm week register. Match operation of alarm is valid. WALE = 1 No INTRTC = 1? Yes WAFG = 1? No Match detection of alarm Yes Alarm interrupt processing Constant-period interrupt servicing Remarks 1. The alarm week register (ALARMWW), alarm hour register (ALARMWH), and alarm week register (ALARMWW) may be written in any sequence. 2. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When using these two types of interrupts at the same time, which interrupt occurred can be judged by checking the fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon INTRTC occurrence. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 445 RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.5 1 Hz output of real-time clock Figure 7-22. 1 Hz Output Setting Procedure Start RTCE = 0 Stops counter operation. Setting port Sets P30 and PM30 RCLOE1 = 1 Enables output of the RTC1HZ pin (1 Hz). RTCE = 1 Starts counter operation. Output start from RTC1HZ pin Caution First set the RTCEN bit to 1, while oscillation of the input clock (fSUB) is stable. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 446 RL78/G13 CHAPTER 7 REAL-TIME CLOCK 7.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the counter (16-bit) is calculated by using the following expression. Set the DEV bit to 0 when the correction range is -63.1 ppm or less, or 63.1 ppm or more. (When DEV = 0) Correction valueNote = Number of correction counts in 1 minute / 3 = (Oscillation frequency / Target frequency - 1) 32768 60 / 3 (When DEV = 1) Correction valueNote = Number of correction counts in 1 minute = (Oscillation frequency / Target frequency - 1) 32768 60 Note The correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error correction register (SUBCUD). (When F6 = 0) Correction value = {(F5, F4, F3, F2, F1, F0) - 1} 2 (When F6 = 1) Correction value = - {(/F5, /F4, /F3, /F2, /F1, /F0) + 1} 2 When (F6, F5, F4, F3, F2, F1, F0) is (*, 0, 0, 0, 0, 0, *), watch error correction is not performed. "*" is 0 or 1. /F5 to /F0 are bit-inverted values (000011 when 111100). Remarks 1. 2. The correction value is 2, 4, 6, 8, ... 120, 122, 124 or -2, -4, -6, -8, ... -120, -122, -124. The oscillation frequency is the input clock (fRTC). It can be calculated from the output frequency of the RTC1HZ pin 32768 when the watch error correction register is set to its initial value (00H). 3. The target frequency is the frequency resulting after correction performed by using the watch error correction register. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 447 RL78/G13 CHAPTER 7 REAL-TIME CLOCK Correction example Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] The oscillation frequencyNote of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H). Note See 7.4.5 1 Hz output of real-time clock for the setting procedure of outputting about 1 Hz from the RTC1HZ pin. [Calculating the correction value] (When the output frequency from the RTCCL pin is 0.9999817 Hz) Oscillation frequency = 32768 0.9999817 32767.4 Hz Assume the target frequency to be 32768 Hz (32767.4 Hz + 18.3 ppm) and DEV to be 1. The expression for calculating the correction value when DEV is 1 is applied. Correction value = Number of correction counts in 1 minute = (Oscillation frequency / Target frequency - 1) 32768 60 = (32767.4 / 32768 - 1) 32768 60 = -36 [Calculating the values to be set to (F6 to F0)] (When the correction value is -36) If the correction value is 0 or less (when quickening), assume F6 to be 1. Calculate (F5, F4, F3, F2, F1, F0) from the correction value. - {(/F5, /F4, /F3, /F2, /F1, /F0) - 1} 2 = -36 (/F5, /F4, /F3, /F2, /F1, /F0) = 17 (/F5, /F4, /F3, /F2, /F1, /F0) = (0, 1, 0, 0, 0, 1) (F5, F4, F3, F2, F1, F0) = (1, 0, 1, 1, 1, 0) Consequently, when correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm), setting the correction register such that DEV is 1 and the correction value is -36 (bits 6 to 0 of the SUBCUD register: 1101110) results in 32768 Hz (0 ppm). Figure 7-23 shows the operation when (DEV, F6, F5, F4, F3, F2, F1, F0) is (1, 1, 1, 0, 1, 1, 1, 0). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 448 RL78/G13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Figure 7-23. Operation when (DEV, F6, F5, F4, F3, F2, F1, F0) = (1, 1, 1, 0, 1, 1, 1, 0) 7FFFH + 56H (86) 7FFFH + 56H (86) 7FFFH + 56H (86) 7FFFH+56H (86) Count start Counter (16-bit) count value SEC 0000H 8054H 8055H 0000H 0001H 00 01 7FFFH 0000H 0001H 19 7FFFH 0000H 8054H 8055H 20 0000H 0001H 39 7FFFH 0000H 8054H 8055H 40 0000H 0001H 59 7FFFH 0000H 8054H 8055H 00 CHAPTER 7 REAL-TIME CLOCK 449 RL78/G13 CHAPTER 8 12-BIT INTERVAL TIMER CHAPTER 8 12-BIT INTERVAL TIMER <R> 8.1 Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter's SNOOZE mode. 8.2 Configuration of 12-bit Interval Timer The 12-bit interval timer includes the following hardware. Table 8-1. Configuration of 12-bit Interval Timer Item Configuration Counter 12-bit counter Control registers Peripheral enable register 0 (PER0) Operation speed mode control register (OSMC) Interval timer control register (ITMC) Figure 8-1. Block Diagram of 12-bit Interval Timer fSUB fIL Selector Clear Count clock 12-bit counter Interrupt signal (INTIT) Match singnal WUTMM CK0 RINTE Operation speed mode control register (OSMC) ITMCMP11-ITMCMP0 Interval timer control register (ITMC) Internal bus R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 450 RL78/G13 CHAPTER 8 12-BIT INTERVAL TIMER 8.3 Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. * Peripheral enable register 0 (PER0) * Operation speed mode control register (OSMC) * Interval timer control register (ITMC) (1) Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the 12-bit interval timer is used, be sure to set bit 7 (RTCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-2. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PER0 RTCEN IICA1EN ADCEN IICA0EN SAU1EN SAU0EN TAU1EN TAU0EN Note 2 Note 3 Note 1 RTCEN Note 1 Control of real-time clock (RTC) and 12-bit interval timer input clock supply Stops input clock supply. 0 * SFR used by the real-time clock (RTC) and 12-bit interval timer cannot be written. * The real-time clock (RTC) and 12-bit interval timer are in the reset status. Enables input clock supply. 1 * SFR used by the real-time clock (RTC) and 12-bit interval timer can be read and written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Cautions 1. When using the 12-bit interval timer, first set the RTCEN bit to 1, while oscillation of the input clock (fRTC) is stable. If RTCEN = 0, writing to a control register of the realtime clock or 12-bit interval timer is ignored, and, even if the register is read, only the default value is read. 2. Clock supply to peripheral functions other than the real-time clock and 12-bit interval timer can be stopped in STOP mode or HALT mode when the subsystem clock is used, by setting the RTCLPC bit of the operation speed mode control register (OSMC) to 1. In this case, set the RTCEN bit of the PER0 register to 1 and the other bits (bits 0 to 6) to 0. 3. Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 451 RL78/G13 CHAPTER 8 12-BIT INTERVAL TIMER (2) Operation speed mode control register (OSMC) The WUTMMCK0 bit can be used to select the 12-bit interval timer operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-3. Format of Operation Speed Mode Control Register (OSMC) Address: F00F3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 OSMC RTCLPC 0 0 WUTMMCK0 0 0 0 0 WUTMMCK0 Selection of operation clock for real-time clock and 12-bit interval timer. 0 Subsystem clock (fSUB) 1 Low-speed on-chip oscillator clock (fIL) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 452 RL78/G13 CHAPTER 8 12-BIT INTERVAL TIMER (3) Interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0FFFH. Figure 8-4. Format of Interval Timer Control Register (ITMC) Address: FFF90H After reset: 0FFFH R/W Symbol 15 14 13 12 11 to 0 ITMC RINTE 0 0 0 ITMCMP11 to ITMCMP0 RINTE 12-bit Interval timer operation control 0 Count operation stopped (count clear) 1 Count operation started ITMCMP11 to ITMCMP0 001H * Specification of the 12-bit interval timer compare value These bits generate an interrupt at the fixed cycle (count clock cycles x (ITMCMP setting + 1)). * * FFFH 000H Setting prohibit Example interrupt cycles when 001H or FFFH is specified for ITMCMP11 to ITMCMP0 * ITMCMP11 to ITMCMP0 = 001H, count clock: when fSUB = 32.768 kHz 1/32.768 [kHz] x (1 + 1) = 0.06103515625 [ms] 61.03 [s] * ITMCMP11 to ITMCMP0 = FFFH, count clock: when fSUB = 32.768 kHz 1/32.768 [kHz] x (4095 + 1) = 125 [ms] Cautions 1. Before changing the RINTE bit from 1 to 0, use the interrupt mask flag register to disable the INTIT interrupt servicing. When the operation starts (from 0 to 1) again, clear the ITIF flag, and then enable the interrupt servicing. 2. The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit. <R> 3. When setting the RINTE bit after returned from standby mode and entering standby mode again, confirm that the written value of the RINTE bit is reflected, or wait that more than one clock of the count clock has elapsed after returned from standby mode. Then enter standby mode. 4. Only change the setting of the ITMCMP11 to ITMCMP0 bits when RINTE = 0. However, it is possible to change the settings of the ITMCMP11 to ITMCMP0 bits at the same time as when changing RINTE from 0 to 1 or 1 to 0. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 453 RL78/G13 CHAPTER 8 12-BIT INTERVAL TIMER 8.4 12-bit Interval Timer Operation The count value specified for the ITMCMP11 to ITMCMP0 bits is used as an interval to operate an 12-bit interval timer that repeatedly generates interrupt requests (INTIT). When the RINTE bit is set to 1, the 12-bit counter starts counting. When the 12-bit counter value matches the value specified for the ITMCMP11 to ITMCMP0 bits, the 12-bit counter value is cleared to 0, counting continues, and an interrupt request signal (INTIT) is generated at the same time. The basic operation of the 12-bit interval timer is as follows. <R> Figure 8-5. 12-bit Interval Timer Operation Timing (ITMCMP11 to ITMCMP0 = 0FFH, count clock: fSUB = 32.768 kHz) Count clock RINTE After RINTE is changed from 0 to 1, counting starts at the two fall of the count clock signal. 0FFH 12-bit counter 000H When RINTE is changed from 1 to 0, the 12-bit counter is cleared without synchronization with the count clock. ITMCMP11 to ITMCMP0 0FFH INTIT Period (7.81 ms) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 454 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER The number of output pins of the clock output and buzzer output controllers differs, depending on the product. Output pin 20-pin 24, 25-pin 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, 128-pin PCLBUZ0 - PCLBUZ1 - - Caution Most of the following descriptions in this chapter use the 64-pin as an example. 9.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency. One pin can be used to output a clock or buzzer sound. Two output pins, PCLBUZ0 and PCLBUZ1, are available. The PCLBUZn pin outputs a clock selected by clock output select register n (CKSn). Figure 9-1 shows the block diagram of clock output/buzzer output controller. Caution In the low-consumption RTC mode (when the RTCLPC bit of the operation speed mode control register (OSMC) = 1), it is not possible to output the subsystem clock (fSUB) from the PCLBUZn pin. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 455 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller Internal bus Clock output select register 1 (CKS1) PCLOE1 0 fMAIN 0 0 CSEL1 CCS12 CCS11 CCS10 Prescaler PCLOE1 3 fMAIN/211 to fMAIN/213 fMAIN to fMAIN/24 Selector 5 Clock/buzzer controller PCLBUZ1Note/INTP7/P141 fSUB to fSUB/27 Output latch (P141) fMAIN to fMAIN/24 fSUB to fSUB/27 8 fSUB 0 PM141 Clock/buzzer controller PCLBUZ0Note/INTP6/P140 8 PCLOE0 Prescaler PCLOE0 Selector fMAIN/211 to fMAIN/213 0 0 Output latch (P140) PM140 CSEL0 CCS02 CCS01 CCS00 Clock output select register 0 (CKS0) Internal bus Note For output frequencies available from PCLBUZ0 and PCLBUZ1, refer 29.5 AC Characteristics. Remark The clock output/buzzer output pins in above diagram shows the information of 64- to 128-pins products with PIOR3 = 0 and PIOR4 = 0. In other cases, the name of pins, output latches (Pxx) and PMxx should be read differently (xx = 15, 31, 55, 140 or 141). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 456 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 9-1. Configuration of Clock Output/Buzzer Output Controller Item Control registers Configuration Clock output select registers n (CKSn) Port mode register 1, 3, 5, 14 (PM1, PM3, PM5, PM14) Port register 1, 3, 5, 14 (P1, P3, P5, P14) 9.3 Registers Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output select registers n (CKSn) * Port mode register 1, 3, 5, 14 (PM1, PM3, PM5, PM14) (1) Clock output select registers n (CKSn) These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZn), and set the output clock. Select the clock to be output from the PCLBUZn pin by using the CKSn register. The CKSn register are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 457 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-2. Format of Clock Output Select Register n (CKSn) Address: FFFA5H (CKS0), FFFA6H (CKS1) Symbol CKSn After reset: 00H R/W <7> 6 5 4 3 2 1 0 PCLOEn 0 0 0 CSELn CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZn pin output enable/disable specification 0 Output disable (default) 1 Output enable CSELn CCSn2 0 0 CCSn1 0 CCSn0 0 PCLBUZn pin output clock selection fMAIN fMAIN = fMAIN = fMAIN = fMAIN = 5 MHz 10 MHz 20 MHz 32 MHz 5 MHz Note 10 MHz Setting Setting prohibited 0 0 0 1 fMAIN/2 0 0 1 0 fMAIN/2 0 0 1 1 0 0 0 Note prohibited 2.5 MHz 5 MHz 10 MHz 16 MHz 2 1.25 MHz 2.5 MHz 5 MHz 8 MHz fMAIN/2 3 625 kHz 1.25 MHz 2.5 MHz 4 MHz fMAIN/2 4 312.5 kHz 625 kHz 1.25 MHz 2 MHz Note Note Note 0 1 0 1 fMAIN/2 11 2.44 kHz 4.88 kHz 9.76 kHz 15.63 kHz 0 1 1 0 fMAIN/2 12 1.22 kHz 2.44 kHz 4.88 kHz 7.81 kHz 0 1 1 1 fMAIN/2 13 610 Hz 1.22 kHz 2.44 kHz 3.91 kHz 1 0 0 0 fSUB 1 0 0 1 fSUB/2 1 1 1 0 0 1 1 1 0 0 1 0 32.768 kHz 16.384 kHz fSUB/2 2 8.192 kHz fSUB/2 3 4.096 kHz fSUB/2 4 2.048 kHz 1.024 kHz 1 1 0 1 fSUB/2 5 1 1 1 0 fSUB/2 6 512 Hz fSUB/2 7 256 Hz 1 Note 1 Note 1 1 1 Use the output clock within a range of 16 MHz. Furthermore, when using the output clock at 2.7 V VDD < 4.0 V, can be use it within 8 MHz only. See 29.5 AC Characteristics for details. Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0). 2. To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0 before executing the STOP instruction. When the subsystem clock is selected (CSELn = 1), PCLOEn = 1 can be set because the clock can be output in STOP mode. 3. In the low-consumption RTC mode (when the RTCLPC bit of the operation speed mode control register (OSMC) = 1), it is not possible to output the subsystem clock (fSUB) from the PCLBUZn pin. Remarks 1. n = 0, 1 2. fMAIN: Main system clock frequency fSUB: Subsystem clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 458 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 1, 3, 5, 14 (PM1, PM3, PM5, PM14) These registers set input/output of port in 1-bit units. For example in 64-pin products, when using the P140/INTP6/PCLBUZ0 and P141/INTP7/PCLBUZ1 pins for clock output and buzzer output clear PM140 and PM141 bits and the output latches of P140 and P141 to 0. The PM1, PM3, PM5, PM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 9-3. Format of Port Mode Register 14 (PM14) (64-pin products) Address: FFF2EH Symbol PM14 R/W 6 5 4 3 2 1 0 PM147 PM146 1 1 1 1 PM141 PM140 PMmn Remark After reset: FFH 7 Pmn pin I/O mode selection (mn = 140, 141, 146, 147) 0 Output mode (output buffer on) 1 Input mode (output buffer off) For details of the port mode register other than 64-pin products, see 4. 3 Registers Controlling Port Function. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 459 RL78/G13 CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1). 9.4.1 Operation as output pin The PCLBUZn pin is output as the following procedure. <1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn) of the PCLBUZn pin (output in disabled status). <2> Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output. Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or disabling clock output (PCLOEn bit) is switched. At this time, pulses with a narrow width are not output. Figure 9-4 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the clock. 2. n = 0, 1 Figure 9-4. Remote Control Output Application Example PCLOEn 1 clock elapsed Clock output Narrow pulses are not recognized <R> 9.5 Cautions of clock output/buzzer output controller When the main system clock is selected for the PCLBUZn output (CSEL = 0), if STOP or HALT mode is entered within 1.5 main system clock cycles after the output is disabled (PCLOEn = 0), the PCLBUZn output width becomes shorter. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 460 RL78/G13 CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer operates on the low-speed on-chip oscillator clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases. * If the watchdog timer counter overflows * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to the WDTE register * If data is written to the WDTE register during a window close period When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of the RESF register, see CHAPTER 19 RESET FUNCTION. <R> When 75% + 1/2/fIL of the overflow time is reached, an interval interrupt can be generated. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 461 RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte. Table 10-2. Setting of Option Bytes and Watchdog Timer Setting of Watchdog Timer Option Byte (000C0H) Watchdog timer interval interrupt Bit 7 (WDTINT) Window open period Bits 6 and 5 (WINDOW1, WINDOW0) Controlling counter operation of watchdog timer Bit 4 (WDTON) Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0) Controlling counter operation of watchdog timer Bit 0 (WDSTBYON) (in HALT/STOP mode) Remark For the option byte, see CHAPTER 24 OPTION BYTE. Figure 10-1. Block Diagram of Watchdog Timer WDTINT of option byte (000C0H) Interval time controller (Count value overflow time x 3/4) Interval time interrupt WDCS2 to WDCS0 of option byte (000C0H) fIL Clock input controller 17-bit counter fIL/26 to fIL/216 Selector Reset output controller Count clear signal WINDOW1 and WINDOW0 of option byte (000C0H) WDTON of option byte (000C0H) Overflow signal Internal reset signal Window size decision signal Window size check Watchdog timer enable register (WDTE) Write detector to WDTE except ACH Internal bus R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 462 RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing "ACH" to the WDTE register clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 10-2. Format of Watchdog Timer Enable Register (WDTE) Address: FFFABH Symbol After reset: 9AH/1AHNote 7 6 R/W 5 4 3 2 1 0 WDTE Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte (000C0H). To operate watchdog timer, set the WDTON bit to 1. WDTON Bit Setting Value WDTE Register Reset Value 0 (watchdog timer count operation disabled) 1AH 1 (watchdog timer count operation enabled) 9AH Cautions 1. If a value other than "ACH" is written to the WDTE register, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for the WDTE register, an internal reset signal is generated. 3. The value read from the WDTE register is 9AH/1AH (this differs from the written value (ACH)). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 463 RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (000C0H). * Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 24). WDTON Watchdog Timer Counter 0 Counter operation disabled (counting stopped after reset) 1 Counter operation enabled (counting started after reset) * Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 10.4.2 and CHAPTER 24). * Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for details, see 10.4.3 and CHAPTER 24). 2. After a reset release, the watchdog timer starts counting. 3. By writing "ACH" to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. 4. After that, write the WDTE register the second time or later after a reset release during the window open period. If the WDTE register is written during a window close period, an internal reset signal is generated. 5. If the overflow time expires without "ACH" written to the WDTE register, an internal reset signal is generated. An internal reset signal is generated in the following cases. * If a 1-bit manipulation instruction is executed on the WDTE register * If data other than "ACH" is written to the WDTE register Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time, as long as the register is written before the overflow time, and the watchdog timer starts counting again. 2. If the watchdog timer is cleared by writing "ACH" to the WDTE register, the actual overflow time may be different from the overflow time set by the option byte by up to 2/fIL seconds. 3. The watchdog timer can be cleared immediately before the count value overflows. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 464 RL78/G13 CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0 WDSTBYON = 1 Watchdog timer operation stops. In HALT mode Watchdog timer operation continues. In STOP mode In SNOOZE mode If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is cleared to 0 and counting starts. When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts operating after the oscillation stabilization time has elapsed. Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. Consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt. 10.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing "ACH" to the watchdog timer enable register (WDTE) during the window open period before the overflow time. The following overflow times can be set. Table 10-3. Setting of Overflow Time of Watchdog Timer WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer (fIL = 17.25 kHz (MAX.)) Remark 6 0 0 0 2 /fIL (3.71 ms) 0 0 1 2 /fIL (7.42 ms) 0 1 0 2 /fIL (14.84 ms) 0 1 1 2 /fIL (29.68 ms) 1 0 0 2 /fIL (118.72 ms) 1 0 1 2 /fIL (474.90 ms) 1 1 0 2 /fIL (949.80 ms) 1 1 1 2 /fIL (3799.19 ms) 7 8 9 11 13 14 16 fIL: Low-speed on-chip oscillator clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 465 RL78/G13 CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows. * If "ACH" is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer is cleared and starts counting again. * Even if "ACH" is written to the WDTE register during the window close period, an abnormality is detected and an internal reset signal is generated. Example: If the window open period is 50% Counting starts Overflow time Window close period (50%) Window close period (50%) Internal reset signal is generated if "ACH" is written to WDTE. Counting starts again when "ACH" is written to WDTE. Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time, as long as the register is written before the overflow time, and the watchdog timer starts counting again. The window open period can be set is as follows. Table 10-4. Setting Window Open Period of Watchdog Timer Caution WINDOW1 WINDOW0 Window Open Period of Watchdog Timer 0 0 Setting prohibited 0 1 50% 1 0 75% 1 1 100% When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100% regardless of the values of the WINDOW1 and WINDOW0 bits. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 466 RL78/G13 CHAPTER 10 WATCHDOG TIMER 9 Remark If the overflow time is set to 2 /fIL, the window close time and open time are as follows. Setting of Window Open Period <R> 50% 75% + 1/2fIL 100% Window close time 0 to 20.08 ms 0 to 10.04 ms None Window open time 20.08 to 29.68 ms 10.04 to 29.68 ms 0 to 29.68 ms <When window open period is 50%> * Overflow time: 29/fIL (MAX.) = 29/17.25 kHz = 29.68 ms * Window close time: 0 to 29/fIL (MIN.) x (1 - 0.5) = 0 to 29/12.75 kHz x 0.5 = 0 to 20.08 ms * Window open time: 29/fIL (MIN.) x (1 - 0.5) to 29/fIL (MAX.) = 29/12.75 kHz x 0.5 to 29/17.25 kHz = 20.08 to 29.68 ms 10.4.4 Setting watchdog timer interval interrupt Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75% of the overflow time is reached. Table 10-5. Setting of Watchdog Timer Interval Interrupt WDTINT <R> Use of Watchdog Timer Interval Interrupt 0 Interval interrupt is used. 1 Interval interrupt is generated when 75% + 1/2fIL of overflow time is reached. Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts operating after the oscillation stabilization time has elapsed. Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. Consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt. Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time, an internal reset signal is generated. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 467 RL78/G13 CHAPTER 11 A/D CONVERTER CHAPTER 11 A/D CONVERTER The number of analog input channels of the A/D converter differs, depending on the product. 20, 24, 25-pin 30, 32-pin Analog 6 ch 8 ch 36-pin 40-pin 44, 48-pin 52, 64-pin 80-pin 100-pin 128-pin 8 ch 9 ch 10 ch 12 ch 17 ch 20 ch 26 ch input (ANI0 to ANI2, (ANI0 to ANI3, (ANI0 to ANI5, (ANI0 to ANI6, (ANI0 to ANI7, (ANI0 to ANI7, (ANI0 to ANI11, (ANI0 to ANI14, (ANI0 to ANI14, channels ANI16 to ANI18) ANI16 to ANI19) ANI18, ANI19) ANI18, ANI19) ANI18, ANI19) ANI16 to ANI19) ANI16 to ANI20) ANI16 to ANI20) ANI16 to ANI26) 11.1 Function of A/D Converter Note The A/D converter is a 10-bit resolution converter that converts analog input signals into digital values, and is configured to control analog inputs, including up to 26 channels of A/D converter analog inputs (ANI0 to ANI14 and ANI16 to ANI26). The A/D converter has the following function. * 10-bit resolution A/D conversionNote 10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI14 and ANI16 to ANI26. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated (when in the select mode). Note 8-bit resolution can also be selected by using the ADTYP bit of A/D converter mode register 2 (ADM2). Various A/D conversion modes can be specified by using the mode combinations below. Trigger Mode * Software trigger Channel Selection Mode * Select mode Conversion Operation Mode * One-shot conversion mode Conversion is started by specifying a A/D conversion is performed on A/D conversion is performed on software trigger. the analog input of one channel. the selected channel once. * Hardware trigger no-wait mode * Scan mode * Sequential conversion mode Conversion is started by detecting a A/D conversion is performed on A/D conversion is sequentially hardware trigger. the analog input of four channels performed on the selected in order. channels until it is stopped by * Hardware trigger wait mode The power is turned on by detecting a software. hardware trigger while the system is off and in the conversion standby state, and conversion is then started automatically after the stabilization wait time passes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 468 RL78/G13 Internal bus A/D test register (ADTES) A/D port configuration register (ADPC) ADPC3 ADPC2 ADPC1 ADPC0 Conversion result comparison upper limit setting register (ADUL) ADTES1 ADTES0 Conversion result comparison lower limit setting register (ADLL) ADREFP1 and ADREFP0 bits 4 Digital port control Selector R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Figure 11-1. Block Diagram of A/D Converter <R> 2 Port 2 Internal reference voltage (1.45 V) VDD AVREFP/ANI0/P20 ADCS bit Sample & hold circuit A/D voltage comparator Selector Selector Comparison voltage generator VSS ADREFM bit Successive approximation register (SAR) Selector ANI16/P03/SI10/RxD1/SDA10 ANI17/P02/SO10/TxD1 ANI18/P147 ANI19/P120 Temperature sensor Selector ANI0/AVREFP/P20 ANI1/AVREFM/P21 ANI2/P22 ANI3/P23 ANI4/P24 ANI5/P25 ANI6/P26 ANI7/P27 Controller ADREFP1 ADREFP0 ADREFPM ADRCK AWC A/D conversion result upper limit/lower limit comparator ADTYP ADS4 ADS3 ADS2 ADS1 ADS0 6 ADTMD1 ADTMD0 ADSCM ADTRS1 ADTRS0 Analog input channel specification register (ADS) ADCS ADMD A/D converter mode register 1 (ADM1) FR1 FR0 LV1 LV0 ADCE A/D converter mode register 0 (ADM0) Internal bus Remark Analog input pin for figure 11-1 when a 64-pin product is used. FR2 A/D conversion result register (ADCR) INTAD 469 CHAPTER 11 A/D CONVERTER A/D converter mode register 2 (ADM2) ADISS VSS Timer trigger signal (INTRTC) Timer trigger signal (INTIT) Timer trigger signal (INTTM01) Internal reference voltage (1.45 V) 6 AVREFM/ANI1/P21 RL78/G13 CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI14 and ANI16 to ANI26 pins These are the analog input pins of the 26 channels of the A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins. (2) Sample & hold circuit The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D conversion. (3) A/D voltage comparator This A/D voltage comparator compares the voltage generated from the voltage tap of the comparison voltage generator with the analog input voltage. If the analog input voltage is found to be greater than the reference voltage (1/2 AVREF) as a result of the comparison, the most significant bit (MSB) of the successive approximation register (SAR) is set. If the analog input voltage is less than the reference voltage (1/2 AVREF), the MSB bit of the SAR is reset. After that, bit 8 of the SAR register is automatically set, and the next comparison is made. The voltage tap of the comparison voltage generator is selected by the value of bit 9, to which the result has been already set. Bit 9 = 0: (1/4 AVREF) Bit 9 = 1: (3/4 AVREF) The voltage tap of the comparison voltage generator and the analog input voltage are compared and bit 8 of the SAR register is manipulated according to the result of the comparison. Analog input voltage Voltage tap of comparison voltage generator: Bit 8 = 1 Analog input voltage Voltage tap of comparison voltage generator: Bit 8 = 0 Comparison is continued like this to bit 0 of the SAR register. When performing A/D conversion at a resolution of 8 bits, the comparison continues until bit 2 of the SAR register. Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. (4) Comparison voltage generator The comparison voltage generator generates the comparison voltage input from an analog input pin. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 470 RL78/G13 CHAPTER 11 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB). If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the specified A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is generated. (6) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD. (9) AVREFP pin This pin inputs an external reference voltage (AVREFP). If using AVREFP as the + side reference voltage of the A/D converter, set the ADREFP1 and ADREFP0 bits of A/D converter mode register 2 (ADM2) to 1. The analog signals input to ANI0 to ANI14 and ANI16 to ANI26 are converted to digital signals based on the voltage applied between AVREFP and the - side reference voltage (AVREFM/VSS). In addition to AVREFP, it is possible to select VDD or the internal reference voltage (1.45 V) as the + side reference voltage of the A/D converter. (10) AVREFM pin This pin inputs an external reference voltage (AVREFM). If using AVREFM as the - side reference voltage of the A/D converter, set the ADREFM bit of the ADM2 register to 1. In addition to AVREFM, it is possible to select VSS as the - side reference voltage of the A/D converter. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 471 RL78/G13 CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter uses the following registers. * Peripheral enable register 0 (PER0) * A/D converter mode register 0 (ADM0) * A/D converter mode register 1 (ADM1) * A/D converter mode register 2 (ADM2) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) * Analog input channel specification register (ADS) * Conversion result comparison upper limit setting register (ADUL) * Conversion result comparison lower limit setting register (ADLL) * A/D test register (ADTES) * A/D port configuration register (ADPC) * Port mode control registers 0, 3, 10, 11, 12, and 14 (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14) * Port mode registers 0, 2, 3, 10, 11, 12, 14, and 15 (PM0, PM2, PM3, PM10, PM11, PM12, PM14, PM15) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 472 RL78/G13 CHAPTER 11 A/D CONVERTER (1) Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-2. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H Symbol PER0 After reset: 00H <7> RTCEN R/W <6> IICA1EN <5> Note 1 ADCEN ADCEN 0 <4> IICA0EN <3> Note 2 SAU1EN <2> Note 3 SAU0EN <1> TAU1EN <0> Note 1 TAU0EN Control of A/D converter input clock supply Stops input clock supply. * SFR used by the A/D converter cannot be written. * The A/D converter is in the reset status. 1 Enables input clock supply. * SFR used by the A/D converter can be read/written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Cautions 1. When setting the A/D converter, be sure to set the ADCEN bit to 1 first. If ADCEN = 0, writing to a control register of the A/D converter is ignored, and, even if the register is read, only the default value is read (except for port mode registers 0, 2, 12, and 14 (PM0, PM2, PM12, PM14), port mode control registers 0, 12, and 14 (PMC0, PMC12, PMC14), and A/D port configuration register (ADPC)). 2. Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 473 RL78/G13 CHAPTER 11 A/D CONVERTER (2) A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-3. Format of A/D Converter Mode Register 0 (ADM0) Address: FFF30H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> ADM0 ADCS ADMD FR2Note 1 FR1Note 1 FR0Note 1 LV1Note 1 LV0Note 1 ADCE ADCS 0 A/D conversion operation control Stops conversion operation [When read] Conversion stopped/standby status 1 Enables conversion operation [When read] While in the software trigger mode: Conversion operation status While in the hardware trigger wait mode: Stabilization wait status + conversion operation status ADMD Specification of the A/D conversion channel selection mode 0 Select mode 1 Scan mode ADCE A/D voltage comparator operation controlNote 2 0 Stops A/D voltage comparator operation 1 Enables A/D voltage comparator operation Notes 1. For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 11-3 A/D Conversion Time 2. While in the software trigger mode or hardware trigger no-wait mode, the operation of the A/D voltage Selection. comparator is controlled by the ADCS and ADCE bits, and it takes 1 s from the start of operation for the operation to stabilize. Therefore, when the ADCS bit is set to 1 after 1 s or more has elapsed from the time ADCE bit is set to 1, the conversion result at that time has priority over the first conversion result. <R> Otherwise, ignore data of the first conversion. <R> Cautions 1. <R> 2. Change the ADMD, FR2 to FR0, LV1, LV0, and ADCE bits while conversion is stopped or on standby (ADCS = 0). Do not change the ADCE and ADCS bits from 0 to 1 at the same time by using an 8-bit manipulation instruction. Be sure to set these bits in the order described in 11.7 A/D Converter Setup Flowchart. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 474 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation 0 0 Stop status (DC power consumption path does not exist) 0 1 Conversion standby mode (only A/D voltage comparator consumes power 1 0 Setting prohibited 1 1 Conversion mode (A/D voltage comparator: enables operation) Note ) Note In hardware trigger wait mode, there is no DC power consumption path even during conversion standby mode. Table 11-2. Setting and Clearing Conditions for ADCS Bit A/D Conversion Mode Software Select mode trigger Set Conditions Sequential conversion When 1 is mode written to ADCS Clear Conditions When 0 is written to ADCS One-shot conversion * When 0 is written to ADCS mode * The bit is automatically cleared to 0 when A/D conversion ends. Scan mode Sequential conversion When 0 is written to ADCS mode One-shot conversion * When 0 is written to ADCS mode * The bit is automatically cleared to 0 when conversion ends on the specified four channels. Hardware Select mode Sequential conversion trigger no-wait mode mode One-shot conversion When 0 is written to ADCS When 0 is written to ADCS mode Scan mode Sequential conversion When 0 is written to ADCS mode One-shot conversion When 0 is written to ADCS mode Hardware Sequential conversion When a trigger wait mode hardware trigger mode One-shot conversion is input Select mode mode When 0 is written to ADCS * When 0 is written to ADCS * The bit is automatically cleared to 0 when A/D conversion ends. Scan mode Sequential conversion When 0 is written to ADCS mode One-shot conversion * When 0 is written to ADCS mode * The bit is automatically cleared to 0 when conversion ends on the specified four channels. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 475 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-4. Timing Chart When A/D Voltage Comparator Is Used <R> A/D voltage comparator: enables operation ADCE A/D voltage comparator Conversion start time Note 2 Conversion Conversion operation standby Conversion stopped 0 is written to ADCS. Conversion start time Note 2 Conversion Conversion operation standby Conversion stopped Hardware trigger detection 0 is written 1 is written to ADCS. to ADCS. Conversion start time Note 2 A/D power supply stabilization wait time Conversion Conversion Conversion standby operation standby Conversion stopped Conversion standby Software trigger mode ADCS Note 1 1 is written to ADCS. Conversion standby Hardware trigger no-wait mode Hardware trigger wait mode ADCS Trigger standby Note 1 ADCS Hardware trigger detection Notes 1. 0 is written to ADCS. While in the software trigger mode or hardware trigger no-wait mode, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 s or longer to stabilize the internal circuit. <R> 2. In starting conversion, the longer will take up to following time FR2 ADM0 Conversion Clock FR1 (fAD) FR0 Conversion Start Time (Number of fCLK Clock Software Trigger Mode/ Hardware Trigger Wait Mode Hardware Trigger No-wait Mode 0 0 0 fCLK/64 63 0 0 1 fCLK/32 31 0 1 0 fCLK/16 15 0 1 1 fCLK/8 7 1 0 0 fCLK/6 5 1 0 1 fCLK/5 4 1 1 0 fCLK/4 3 1 1 1 fCLK/2 1 1 However, for the second and subsequent conversion in sequential conversion mode and for conversion of the channel specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected. Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is automatically switched to 1 when the hardware trigger signal is detected). However, it is possible to clear the ADCS bit to 0 to specify the A/D conversion standby status. 2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 476 RL78/G13 CHAPTER 11 A/D CONVERTER Cautions 3 Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion stopped/conversion standby status). <R> 4. To complete A/D conversion, specify at least the following time as the hardware trigger interval: Hardware trigger no wait mode: 2 fCLK clock + A/D conversion time Hardware trigger wait mode: 2 fCLK clock + stabilization wait time + A/D conversion time Remark fCLK: CPU/peripheral hardware clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 477 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (1/4) <R> (1) When there is no stabilization wait time Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 Mode (ADM0) FR2 FR1 FR0 Clock (fAD) Conversion LV1 Clock LV0 Normal 1 fCLK/64 76 s 38 s 19 s 9.5 s 152/fCLK 38 s 19 s 9.5 s 4.75 s 114/fCLK 28.5 s 14.25 s 7.125 s 3.5625 s 23.75 s 11.875 s 5.938 s 2.9688 s fCLK/32 1216/fCLK of 608/fCLK 0 1 0 fCLK/16 sampling 304/fCLK 1 fCLK/8 0 0 fCLK/6 7 fAD) 1 0 1 fCLK/5 Setting Setting Setting prohibited prohibited prohibited (number 1 fCLK = 32 MHz 19 s 1 1 fCLK = 16 MHz 38 s 0 0 fCLK = 8 MHz 76 s 0 clock: fCLK = 4 MHz 38 s 0 19 fAD fCLK = 1 MHz 76 s 0 0 2.7 V VDD 5.5 V Time 0 0 Conversion Time Selection Conversion Number of Conversion 95/fCLK 95 s Note 1 1 1 0 fCLK/4 76/fCLK 76 s 19 s 9.5 s 4.75 s 2.375 s Note 1 1 0 1 1 0 0 fCLK/2 0 1 Normal 2 fCLK/64 38/fCLK 17 fAD 1088/fCLK 38 s Setting 9.5 s Setting 4.75 s Setting 2.375 s Setting Notes 1, 2 prohibited 68 s 34 s prohibited prohibited prohibited (number 0 0 1 fCLK/32 of 544/fCLK 68 s 34 s 17 s 0 1 0 fCLK/16 sampling 272/fCLK 68 s 34 s 17 s 8.5 s 0 1 1 fCLK/8 clock: 136/fCLK 34 s 17 s 8.5 s 4.25 s fCLK/6 5 fAD) 102/fCLK 25.5 s 12.75 s 6.375 s 1 0 0 3.1875 s Note 2 1 0 1 fCLK/5 85/fCLK 85 s 21.25 s 10.625 s 5.3125 s 2.6563 s Notes 1, 2 1 1 0 fCLK/4 68/fCLK 68 s 17 s 8.5 s 4.25 s 2.125 s Notes 1, 2 1 1 1 fCLK/2 34/fCLK 34 s 8.5 s 4.25 s 2.125 s Notes 1, 2 Setting prohibited Notes 1. Setting prohibited in the 3.6 V 2. This value is prohibited when using the temperature sensor Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped/conversion standby status (ADCS = 0). 2. The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. Remark fCLK: CPU/peripheral hardware clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 478 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (2/4) <R> (2) When there is no stabilization wait time Note 1 Low-voltage mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 Mode (ADM0) FR2 FR1 FR0 Clock (fAD) Conversion LV1 Conversion Time Selection Conversion Number of Conversion Time 1.6 V VDD 5.5 V Clock LV0 Note 2 fCLK = fCLK = fCLK = fCLK = fCLK = 4 MHz 8 MHz 16 MHz 32 MHz 76 s 38 s 76 s 38 s 19 s 38 s 19 s 19 s 9.5 s (number 1 of 608/fCLK 0 fCLK/16 sampling 304/fCLK 76 s 152/fCLK 38 s 114/fCLK 28.5 s Note 7 14.25 s 0 0 0 0 0 1 1 0 19 fAD 0 1 1 fCLK/8 clock: 1 0 0 fCLK/6 7 fAD) 1216/fCLK Setting Setting Setting prohibited prohibited prohibited Note 7 Note 6 1 1 0 1 1 fCLK/5 0 95/fCLK fCLK/4 Note 4 1 MHz Low- fCLK/64 voltage 1 fCLK/32 0 Note 3 76/fCLK 95 s 76 s 9.5 s Note 6 7.125 s 4.75 s 3.5625 s Note 6 23.75 s 11.875 s 5.938 s 2.9688 s Note 7 Note 66 Note 6 Note 5 19 s Note 7 9.5 s Note 6 4.75 s Note 6 2.375 s Note 5 1 1 1 fCLK/2 38/fCLK 68 s 34 s 17 s 34 s 17 s 17 s 8.5 s 544/fCLK 0 fCLK/16 sampling 272/fCLK 68 s 136/fCLK 34 s 102/fCLK 25.5 s Note 7 12.75 s 0 0 1 1 1 17 fAD 0 1 1 fCLK/8 clock: 5 1 0 0 fCLK/6 fAD) 1 1 34 s of 0 1 68 s (number 0 0 prohibited 1 0 0 fCLK/5 fCLK/4 1088/fCLK Setting Setting s Setting Note 5 Low- fCLK/64 voltage 2 fCLK/32 0 1 38 s Note 7 9.5 s Note 6 4.75 s Note 6 2.375 Setting prohibited prohibited prohibited 85/fCLK 68/fCLK 85 s 68 s Note 7 8.5 s Note 6 6.375 s 4.25 s 3.1875 s Note 6 Note 6 21.25 s 10.625 s 5.3125 s 2.6563 s Note 7 Note 6 Note 6 Note 5 17 s Note 7 8.5 s Note 6 4.25 s Note 6 2.125 s Note 5 1 1 1 fCLK/2 34/fCLK 34 s Note 7 8.5 s Note 6 4.25 s Note 6 2.125 s Note 5 Setting prohibited Notes 1. This mode is prohibited when using the temperature sensor 2. 1.8 V VDD 5.5 V 3. 2.4 V VDD 5.5 V 4. 2.7 V VDD 5.5 V 5. Setting prohibited in the 3.6 V 6. Setting prohibited in the 2.7 V 7. Setting prohibited in the 1.8 V Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped/conversion standby status (ADCS = 0). 2. The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. Remark fCLK: CPU/peripheral hardware clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 479 RL78/G13 CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (3/4) <R> (3) When there is stabilization wait time Normal mode 1, 2 (hardware trigger wait mode A/D Converter Mode Mode Conversion Number of Number of Stabilization Register 0 (ADM0) Note 1 Conversion Time Selection 2.7 V VDD 5.5 V Clock (fAD) Stabilization Conversion Wait Cock + Wait Cock Clock Conversion fCLK = fCLK = fCLK = fCLK = fCLK = Time 1 MHz 4 MHz 8 MHz 16 MHz 32 MHz FR FR FR LV LV 2 1 0 1 0 0 0 0 0 0 0 0 1 fCLK/32 of 864/fCLK 0 1 0 fCLK/16 sampling 432/fCLK 0 1 1 fCLK/8 1 0 0 fCLK/6 1 0 1 fCLK/5 Normal fCLK/64 8 fAD 1 19 fAD 108 s 54 s 108 s 54 s 27 s 108 s 54 s 27 s 13.5 s 216/fCLK 54 s 27 s 13.5 s 6.75 s 162/fCLK 40.5 s 20.25 s 10.125 s 5.0625 s 33.75 s 16.875 s 8.4375 s 4.21875 s 1728/fCLK Setting 7 fAD) Setting Setting prohibited prohibited prohibited (number clock: ) 135/fCLK 135 s Note 3 1 1 0 fCLK/4 108/fCLK 108 s 27 s 13.5 s 6.75 s 3.375 s Note 2 1 0 1 0 1 0 fCLK/2 0 1 Normal fCLK/64 54/fCLK 8 fAD 17 fAD 1600/fCLK Setting (number 2 54 s 13.5 s Setting 6.75 s Setting 3.375 s Setting Notes 2, 3 prohibited 100 s 50 s prohibited prohibited prohibited 0 0 1 fCLK/32 of 800/fCLK 100 s 50 s 25 s 0 1 0 fCLK/16 sampling 400/fCLK 100 s 50 s 25 s 12.5 s 0 1 1 fCLK/8 clock: 200/fCLK 50 s 25 s 12.5 s 6.25 s fCLK/6 5 fAD) 150/fCLK 37.5 s 18.75 s 9.375 s 4.6875 s 1 0 0 Note 3 1 0 1 fCLK/5 125/fCLK 125 s 31.25 s 15.625 s 7.8125 s 3.90625 s Notes 2, 3 1 1 0 fCLK/4 100/fCLK 100 s 25 s 12.5 s 6.25 s 3.125 s Notes 2, 3 1 1 1 fCLK/2 50/fCLK 50 s 12.5 s 6.25 s 3.125 s Notes 2, 3 Setting prohibited Notes 1. For the second and subsequent conversion in sequential conversion mode and for conversion of the channel specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see table 11-3 (1/4)). 2. Setting prohibited in the 3.6 V 3. This value is prohibited when using the temperature sensor Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped/conversion standby status (ADCS = 0). 2. The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. 3. When hardware trigger wait mode, specify the conversion time, including the stabilization wait time from the hardware trigger detection. Remark fCLK: CPU/peripheral hardware clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 480 RL78/G13 CHAPTER 11 A/D CONVERTER <R> Table 11-3. A/D Conversion Time Selection (4/4) (4) When there is no stabilization wait time Low-voltage mode 1, 2 A/D Converter Mode FR FR LV (hardware trigger wait mode Mode Conversion Number of Number of Stabilization Wait Cock LV 2 1 0 1 0 0 0 0 0 0 Normal fCLK/64 2 fAD 1 Clock 19 fAD Conversion fCLK = Time 1 MHz 1344/fCLK Setting fCLK = 4 MHz Setting 0 1 fCLK/32 of 672/fCLK 1 0 fCLK/16 sampling 336/fCLK 84 s fCLK/8 clock: 168/fCLK 42 s 1 Note 3 Note 4 Note 5 fCLK = fCLK = fCLK = 8 MHz 1 1 0 0 1 0 fCLK/6 1 84 s 42 s 21 s 42 s 21 s Note 8 10.5 s 10.5 s 5.25 s 21 s 0 Note 7 126/fCLK fCLK/5 105/fCLK fCLK/4 84/fCLK 105 s 84 s 31.25 s 15.75 s 7.875 s Note 8 Note 7 Note 7 26.25 s 13.125 s 6.5625 s 3.238125 s Note 8 Note 7 Note 7 1 1 fCLK/2 42/fCLK 21 s Note 8 10.5 s Note 7 5.25 s 42 s Note 8 10.5 s 0 0 0 0 1 Normal fCLK/64 2 fAD 17 fAD 1216/fCLK Setting (number 2 Setting prohibited 76 s 38 s 76 s 38 s 19 s 38 s 19 s Setting prohibited prohibited prohibited 0 0 1 fCLK/32 0 1 0 fCLK/16 sampling 152/fCLK 38 s 19 s 9.5 s 114/fCLK 28.5 s 14.25 s 7.125 s Note 8 Note 7 Note7 23.75 s 12 s Note 7 5.938 s 0 1 1 fCLK/8 1 0 0 fCLK/6 5 fAD) 1 0 1 fCLK/5 608/fCLK 304/fCLK 76 s 96/fCLK 96 s Note 8 Note 8 1 1 1 1 0 fCLK/4 1 fCLK/2 Setting Note 6 of clock: 2.625 s Note 6 5.25 s Note 7 2.625 s Note 7 3.9375 s Note 6 Note 7 1 32 MHz 42 s 7 fAD) 1 16 MHz 84 s Setting prohibited prohibited prohibited (number 0 1 ) Conversion Time Selection 0 0 Note 2 Clock (fAD) Stabilization Conversion Wait Cock + 1.6 V VDD 5.5 V Register 0 (ADM0) FR Note 1 76/fCLK 38/fCLK 76 s 9.5 s Note 7 Note 7 19 s Note 8 9.5 s Note 7 4.75 s 38 s Note 8 9.5 s Note 7 4.75 s Note 7 4.75 s 3.5625 s 2.9688 s Note 6 2.375 s Note 7 Note 6 2.375 s Setting Note 6 prohibited Notes 1. This mode is prohibited when using the temperature sensor 2. For the second and subsequent conversion in sequential conversion mode and for conversion of the channel specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see table 11-3 (2/4)). 3. 1.8 V VDD 5.5 V 4. 2.4 V VDD 5.5 V 5. 2.7 V VDD 5.5 V 6. Setting prohibited in the 3.6 V 7. Setting prohibited in the 2.7 V 8. Setting prohibited in the 1.8 V Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped/conversion standby status (ADCS = 0). 2. The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. 3. Remark When hardware trigger wait mode, specify the conversion time, including the stabilization wait time from the hardware trigger detection. fCLK: CPU/peripheral hardware clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 481 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ADCS 1 or ADS rewrite ADCS Sampling timing INTAD SAR clear Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time Sampling Conversion time (3) A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-6. Format of A/D Converter Mode Register 1 (ADM1) Address: FFF32H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADM1 ADTMD1 ADTMD0 ADSCM 0 0 0 ADTRS1 ADTRS0 ADTMD1 ADTMD0 0 x Software trigger mode 1 0 Hardware trigger no-wait mode 1 1 Hardware trigger wait mode Selection of the A/D conversion trigger mode ADSCM Specification of the A/D conversion mode 0 Sequential conversion mode 1 One-shot conversion mode ADTRS1 ADTRS0 Selection of the hardware trigger signal 0 0 End of timer channel 01 count or capture interrupt signal (INTTM01) 0 1 Setting prohibited 1 0 Real-time clock interrupt signal (INTRTC) 1 1 12-bit interval timer interrupt signal (INTIT) Cautions 1. Only rewrite the value of the ADM1 register while conversion operation is stopped (which is indicated by the ADCS bit of A/D converter mode register 0 (ADM0) being 0). <R> 2. To complete A/D conversion, specify at least the following time as the hardware trigger interval: Hardware trigger no wait mode: 2 fCLK clock + A/D conversion time Hardware trigger wait mode: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 2 fCLK clock + stabilization wait time + A/D conversion time 482 RL78/G13 <R> CHAPTER 11 A/D CONVERTER Cautions 3. In modes other than SNOOZE mode, input of the next INTRTC or INTIT will not be recognized as a valid hardware trigger for up to four fCLK cycles after the first INTRTC or INTIT is input. x: don't care Remarks 1. 2. fCLK: CPU/peripheral hardware clock frequency (4) A/D converter mode register 2 (ADM2) This register is used to select the A/D converter reference voltage, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (1/2) Address: F0010H After reset: 00H R/W Symbol 7 6 5 4 <3> <2> 1 <0> ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP ADREFP1 ADREFP0 0 0 Selection of the + side reference voltage source of the A/D converter Supplied from VDD 0 1 Supplied from P20/AVREFP/ANI0 1 0 Supplied from the internal reference voltage (1.45 V) 1 1 Setting prohibited Note * When ADREFP1 or ADREFP0 bit is rewritten, this must be configured in accordance with the following procedures. (1) Set ADCE = 0 (2) Change the values of ADREFP1 and ADREFP0 (3) Stabilization wait time (A) (4) Set ADCE = 1 (5) Stabilization wait time (B) <R> When ADREFP1 and ADREFP0 are set to 1 and 0, the setting is changed to A = 5 s, B = 1 s. When ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1, A needs no wait and B = 1 s. After (5) stabilization time, start the A/D conversion. * When ADREFP1 and ADREFP0 are set to 1 and 0, respectively, A/D conversion cannot be performed on the <R> temperature sensor output and internal reference voltage output. Be sure to perform A/D conversion while ADISS = 0. Selection of the - side reference voltage source of the A/D converter ADREFM <R> 0 Supplied from VSS 1 Supplied from P21/AVREFM/ANI1 Note This setting can be used only in HS (high-speed main) mode. Cautions 1. Only rewrite the value of the ADM2 register while conversion operation is stopped (which is indicated by the ADCS bit of A/D converter mode register 0 (ADM0) being 0). <R> 2. Do not set the ADREFP1 bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is operating on the subsystem clock. Also, if the ADREFP1 bit is set to 1, the temperature sensor operating current indicated in 29.4.2 Supply current characteristics (ITMPS) will be added to the current consumption when shifting to HALT mode while the CPU is operating on the main system clock. <R> 3. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify input mode by using the port mode register. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 483 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H <R> After reset: 00H R/W Symbol 7 6 5 4 <3> <2> 1 <0> ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP ADRCK Checking the upper limit and lower limit conversion result values 0 The interrupt signal (INTAD) is output when the ADLL register the ADCR register the ADUL register (<1>). 1 The interrupt signal (INTAD) is output when the ADCR register < the ADLL register (<2>) or the ADUL register < the ADCR register (<3>). Figure 11-8 shows the generation range of the interrupt signal (INTAD) for <1> to <3>. AWC Specification of the SNOOZE mode 0 Do not use the SNOOZE mode function. 1 Use the SNOOZE mode function. When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed without operating the CPU (the SNOOZE mode). * The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited. * Using the SNOOZE mode function in the software trigger mode or hardware trigger no-wait mode is prohibited. * Using the SNOOZE mode function in the sequential conversion mode is prohibited. <R> * When using the SNOOZE mode function, specify a hardware trigger interval of at least "shift time to SNOOZE mode Note + A/D power supply stabilization wait time + A/D conversion time +2 fCLK clock" <R> * Even when using SNOOZE mode, be sure to set the AWC bit to 0 in normal operation mode and change it to 1 just before shifting to STOP mode. Also, be sure to change the AWC bit to 0 after returning from STOP mode to normal operation mode. If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or normal operation mode. ADTYP <R> Selection of the A/D conversion resolution 0 10-bit resolution 1 8-bit resolution Note Refer to "From STOP to SNOOZE" in 18.2.3 SNOOZE mode Caution Only rewrite the value of the ADM2 register while conversion operation is stopped (which is indicated by the ADCS bit of A/D converter mode register 0 (ADM0) being 0). Figure 11-8. ADRCK Bit Interrupt Signal Generation Range ADCR register value (A/D conversion result) 1111111111 Area 3 (ADUL < ADCR) INTAD is generated when ADRCK = 1. ADUL register setting Area 1 (ADLL ADCR ADUL) INTAD is generated when ADRCK = 0. ADLL register setting 0000000000 <R> Area 2 (ADCR < ADLL) INTAD is generated when ADRCK = 1. Remark If INTAD does not occur, the A/D conversion result is not stored in the ADCR or ADCRH register. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 484 RL78/G13 CHAPTER 11 A/D CONVERTER (5) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of Note FFF1EH . The ADCR register can be read by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. <R> Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 11-8), the result is not stored. Figure 11-9. Format of 10-bit A/D Conversion Result Register (ADCR) Address: FFF1FH, FFF1EH After reset: 0000H R FFF1FH Symbol FFF1EH ADCR 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR register may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion result to be read. 2. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (ADCR1 and ADCR0). 3. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result are read in order starting at bit 15. (6) 8-bit A/D conversion result register (ADCRH) Note This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored . The ADCRH register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. <R> Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the value specified by the ADRCK bit of the ADM2 register and ADUL/ADLL registers; see Figure 11-8), the result is not stored. Figure 11-10. Format of 8-bit A/D Conversion Result Register (ADCRH) Address: FFF1FH Symbol 7 After reset: 00H 6 5 R 4 3 2 1 0 ADCRH Caution When writing to the A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of the ADCRH register may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion result to be read. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 485 RL78/G13 CHAPTER 11 A/D CONVERTER (7) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-11. Format of Analog Input Channel Specification Register (ADS) (1/2) Address: FFF31H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0 { Select mode (ADMD = 0) ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input channel Input source 0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin 0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin 0 0 0 0 1 0 ANI2 P22/ANI2 pin 0 0 0 0 1 1 ANI3 P23/ANI3 pin 0 0 0 1 0 0 ANI4 P24/ANI4 pin 0 0 0 1 0 1 ANI5 P25/ANI5 pin 0 0 0 1 1 0 ANI6 P26/ANI6 pin 0 0 0 1 1 1 ANI7 P27/ANI7 pin 0 0 1 0 0 0 ANI8 P150/ANI8 pin 0 0 1 0 0 1 ANI9 P151/ANI9 pin 0 0 1 0 1 0 ANI10 P152/ANI10 pin 0 0 1 0 1 1 ANI11 P153/ANI11 pin 0 0 1 1 0 0 ANI12 P154/ANI12 pin 0 0 1 1 0 1 ANI13 P155/ANI13 pin 0 0 1 1 1 0 ANI14 P156/ANI14 pin 0 0 1 1 1 1 Setting prohibited 0 1 0 0 0 0 ANI16 P03/ANI16 pin Note 1 0 1 0 0 0 1 ANI17 P02/ANI17 pin Note 2 0 1 0 0 1 0 ANI18 P147/ANI18 pin 0 1 0 0 1 1 ANI19 P120/ANI19 pin 0 1 0 1 0 0 ANI20 P100/ANI20 pin 0 1 0 1 0 1 ANI21 P37/ANI21 pin 0 1 0 1 1 0 ANI22 P36/ANI22 pin 0 1 0 1 1 1 ANI23 P35/ANI23 pin 0 1 1 0 0 0 ANI24 P117/ANI24 pin 0 1 1 0 0 1 ANI25 P116/ANI25 pin P115/ANI26 pin 0 1 1 0 1 0 ANI26 0 1 1 0 1 1 Setting prohibited 1 0 0 0 0 0 - Temperature sensor output Note 3 1 0 0 0 0 1 Other than the above <R> Notes 1. 2. 3. - Internal reference voltage Note 3 output (1.45 V) Setting prohibited 20-, 24-, 25-, 30-, 32-pin products: P01/ANI16 pin 20-, 24-, 25-, 30-, 32-pin products: P00/ANI17 pin This setting can be used only in HS (high-speed main) mode. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 486 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-11. Format of Analog Input Channel Specification Register (ADS) (2/2) Address: FFF31H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0 { Scan mode (ADMD = 1) ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input channel Scan 0 2 Scan 2 Scan 3 0 0 0 0 0 0 ANI0 ANI1 ANI2 ANI3 0 0 0 0 0 1 ANI1 ANI2 ANI3 ANI4 0 0 0 0 1 0 ANI2 ANI3 ANI4 ANI5 0 0 0 0 1 1 ANI3 ANI4 ANI5 ANI6 0 0 0 1 0 0 ANI4 ANI5 ANI6 ANI7 0 0 0 0 0 0 ANI5 ANI6 ANI7 ANI8 0 0 0 0 0 1 ANI6 ANI7 ANI8 ANI9 0 0 0 0 1 0 ANI7 ANI8 ANI9 ANI10 0 0 0 0 1 1 ANI8 ANI9 ANI10 ANI11 0 0 0 0 1 0 ANI9 ANI10 ANI11 ANI12 0 0 0 0 1 1 ANI10 ANI11 ANI12 ANI13 0 0 0 1 0 0 ANI11 ANI12 ANI13 ANI14 Other than the above Cautions 1. Scan 1 Setting prohibited Be sure to clear bits 5 and 6 to 0. Set a channel to be set the analog input by ADPC and PMC registers in the input mode by using port mode registers 0, 2, 3, 10 to 12, 14, or 15 (PM0, PM2, PM3, PM10 t o PM12, PM14, PM15). 3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the ADS register. 4. Do not set the pin that is set by port mode control register 0, 3, 10 to 12, or 14 (PMC0, PMC3, PMC10 to PMC12, PMC14) as digital I/O by the ADS register. 5. Only rewrite the value of the ADISS bit while conversion operation is stopped (which is indicated by the ADCE bit of A/D voltage cooperator mode register 0 (ADM0) being 0). 6. If using AVREFP as the + side reference voltage source of the A/D converter, do not select ANI0 as an A/D conversion channel. 7. If using AVREFM as the - side reference voltage source of the A/D converter, do not select ANI1 as an A/D conversion channel. 8. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side reference voltage source. <R> 9. Do not set the ADISS bit to 1 when shifting to STOP mode, or to HALT mode while the CPU is operating on the subsystem clock. Also, if the ADREFP1 bit is set to 1, the A/D converter reference voltage current (IADREF) indicated in 29.3.2 Supply current characteristics will be added to the current consumption when shifting to HALT mode while the CPU is operating on the main system clock. <R> 10. Ignore the conversion result if the corresponding ANI pin does not exist in the product used. Remark x: don't care R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 487 RL78/G13 CHAPTER 11 A/D CONVERTER (8) Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 11-8). The ADUL register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Caution When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D conversion result register (ADCR) are compared with the ADUL register. Figure 11-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL) Address: F0011H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0 (9) Conversion result comparison lower limit setting register (ADLL) This register is used to specify the setting for checking the lower limit of the A/D conversion results. The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 11-8). The ADLL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-13. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL) Address: F0012H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0 Caution When 10-bit resolution A/D conversion is selected, the higher eight bits of the 10-bit A/D conversion result register (ADCR) are compared with the ADLL register. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 488 RL78/G13 CHAPTER 11 A/D CONVERTER (10) A/D test register (ADTES) This register is used to select the + side reference voltage (AVREFP) or - side reference voltage (AVREFM) of the A/D converter, or the analog input channel (ANIxx) as the A/D conversion target for the A/D test function. The ADTES register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-14. Format of A/D Test Register (ADTES) Address: F0013H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTES 0 0 0 0 0 0 ADTES1 ADTES0 ADTES1 ADTES0 0 0 ANIxx (This is specified using the analog input channel specification register (ADS).) 1 0 AVREFM 1 1 AVREFP Other than the above <R> A/D conversion target Setting prohibited Caution For details of the A/D test function, see CHAPTER 22 SAFETY FUNCTIONS. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 489 RL78/G13 CHAPTER 11 A/D CONVERTER (11) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI14/P156 pins to analog input of A/D converter or digital I/O of port. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-15. Format of A/D Port Configuration Register (ADPC) Address: F0076H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 ADPC3 ADPC2 ADPC1 ADPC0 <R> ADPC3 ADPC2 ADPC1 ADPC0 ANI14/P156 ANI13/P155 ANI12/P154 ANI11/P153 ANI10/P152 ANI9/P151 ANI8/P150 ANI7/P27 ANI6/P26 ANI5/P25 ANI4/P24 ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20 Analog input (A)/digital I/O (D) switching 0 0 0 0 A A A A A A A A A A A A A A A 0 0 0 1 D D D D D D D D D D D D D D D 0 0 1 0 D D D D D D D D D D D D D D A 0 0 1 1 D D D D D D D D D D D D D A A 0 1 0 0 D D D D D D D D D D D D A A A 0 1 0 1 D D D D D D D D D D D A A A A 0 1 1 0 D D D D D D D D D D A A A A A 0 1 1 1 D D D D D D D D D A A A A A A 1 0 0 0 D D D D D D D D A A A A A A A 1 0 0 1 D D D D D D D A A A A A A A A 1 0 1 0 D D D D D D A A A A A A A A A 1 0 1 1 D D D D D A A A A A A A A A A 1 1 0 0 D D D D A A A A A A A A A A A 1 1 0 1 D D D A A A A A A A A A A A A 1 1 1 0 D D A A A A A A A A A A A A A 1 1 1 1 D A A A A A A A A A A A A A A Cautions 1. Set the port to analog input by ADPC register to the input mode by using port mode registers 2, 15 (PM2, PM15). 2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel specification register (ADS). 3. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify input mode by using the port mode register. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 490 RL78/G13 CHAPTER 11 A/D CONVERTER (12) Port mode control registers 0, 3, 10, 11, 12, 14 (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14) This register switches the ANI16 to ANI26 pins to digital I/O of port or analog input of A/D converter. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. Figure 11-16. Format of Port Mode Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMC0 1 1 1 1 PMC03 PMC02 PMC01 PMC00 F0060H FFH R/W Note 2 Note 2 Note 1 Note 1 1 1 1 1 1 F0063H FFH R/W 1 1 1 1 PMC100 F006AH FFH R/W PMC3 PMC37 PMC36 PMC35 Note 3 Note 3 Note 3 1 1 1 PMC10 Note 4 PMC11 PMC117 PMC116 PMC115 Note 3 Note 3 Note 3 1 1 1 PMC12 1 1 1 1 1 F006BH FFH R/W 1 1 1 1 PMC120 F006CH FFH R/W F006EH FFH R/W Note 5 PMC14 PMC147 1 1 1 1 1 1 1 Note 6 Pmn pin digital I/O/analog input selection PMCmn (m = 0, 3, 10 to 12, 14; n = 0 to 3, 5 to 7) Notes 1. 2. <R> 0 Digital I/O (alternate function other than analog input) 1 Analog input 20-, 24-, 25-, 30-, 32-pin products only 52-, 64-, 80-, 100-, 128-pin products only 3. 128-pin products only 4. 80-, 100-, 128-pin products only 5. 30-, 32-, 36-, 40-, 44-, 48-, 52-, 64-, 80-, 100-, 128-pin products only 6. All products Caution Set the port to analog input by PMC register to the input mode by using port mode registers x (PMx). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 491 RL78/G13 CHAPTER 11 A/D CONVERTER (13) Port mode register 0, 2, 3, 10, 11, 12, 14, 15 (PM0, PM2, PM3, PM10, PM11, PM12, PM14, PM15) When using the ANI0 to ANI14 or ANI16 to ANI26 pin for an analog input port, set the PMmn bit to 1. The output latches of Pnm at this time may be 0 or 1. If the PMmn bits are set to 0, they cannot be used as analog input port pins. The PMmn registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Caution If a pin is set as an analog input port, not the pin level but "0" is always read. Remark m = 0, 2, 3, 10, 11, 12, 14, 15, n = 0 to 7 Figure 11-17. Formats of Port Mode Registers 0, 2, 3, 10, 11, 12, 14, 15 <R> (PM0, PM2, PM3, PM10, PM11, PM12, PM14, PM15) (128-pin products) Address: FFF20H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FFF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 Address: FFF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 Address: FFF2AH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM10 1 PM106 PM105 PM104 PM103 PM102 PM101 PM100 Address: FFF2BH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM11 PM117 PM116 PM115 PM114 PM113 PM112 PM111 PM110 Address: FFF2CH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM12 PM127 PM126 PM125 1 1 1 1 PM120 Address: FFF2EH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM14 PM147 PM146 PM145 PM144 PM143 PM142 PM141 PM140 Address: FFF2FH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM15 1 PM156 PM155 PM154 PM153 PM152 PM151 PM150 PMmn <R> Caution Pmn pin I/O mode selection (m = 0, 2, 3, 10 to 12, 14, 15, n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify input mode by using the port mode register. Remark For details of the port mode register other than 128-pin products, see 4. 3 Registers Controlling Port Function. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 492 RL78/G13 CHAPTER 11 A/D CONVERTER The ANI0/P20 to ANI7/P27 and ANI8/P150 to ANI14/P156 pins are as shown below depending on the settings of the A/D port configuration register (ADPC), analog input channel specification register (ADS), PM2 and PM15 registers. Table 11-4. Setting Functions of ANI0/P20 to ANI7/P27, ANI8/P150 to ANI14/P156 Pins ADPC PM2, PM15 ADS ANI0/P20 to ANI7/P27, ANI8/P150 to ANI14/P156 Pins Digital I/O selection Analog input selection Input mode - Digital input Output mode - Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. The ANI16 to ANI26 pins are as shown below depending on the settings of port mode control registers 0, 3, 10, 11, 12, and 14 (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14), analog input channel specification register (ADS), PM0, PM3, PM10, PM11, PM12, and PM14 registers. Table 11-5. Setting Functions of ANI16 to ANI26 Pins PMC0, PMC3, PMC10, PM0, PM3, PM10, PMC11, PMC12, and PM11, PM12, and PMC14 PM14 Digital I/O selection Analog input selection ADS ANI16 to ANI26 Pins Input mode - Digital input Output mode - Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 493 RL78/G13 CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. <3> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <4> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB bit of the SAR register remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB bit is reset to 0. <5> Next, bit 8 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as follows. * Sampled voltage Voltage tap: Bit 8 = 1 * Sampled voltage < Voltage tap: Bit 8 = 0 <6> Comparison is continued in this way up to bit 0 of the SAR register. <7> Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched Note 1. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated Note 1. Note 2 <8> Repeat steps <1> to <7>, until the ADCS bit is cleared to 0 . To stop the A/D converter, clear the ADCS bit to 0. <R> Notes 1. If the A/D conversion result is outside the A/D conversion result range specified by the ADRCK bit and the ADUL and ADLL registers (see Figure 11-8), the A/D conversion result interrupt request signal is not generated and no A/D conversion results are stored in the ADCR and ADCRH registers. 2. While in the sequential conversion mode, the ADCS flag is not automatically cleared to 0. This flag is not automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode, either. Instead, 1 is retained. Remarks 1. Two types of the A/D conversion result registers are available. * ADCR register (16 bits): Store 10-bit A/D conversion value * ADCRH register (8 bits): Store 8-bit A/D conversion value 2. AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 494 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-18. Conversion Operation of A/D Converter (Software Trigger Mode) ADCS 1 or ADS rewrite Conversion time Sampling time A/D converter operation SAR SAR clear Sampling A/D conversion Undefined ADCR Conversion result Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 495 RL78/G13 CHAPTER 11 A/D CONVERTER 11.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI14, ANI16 to ANI26) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or ( ADCR 64 - 0.5) x where, INT( ): AVREF 1024 VAIN < ( ADCR 64 + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCR: A/D conversion result register (ADCR) value SAR: Successive approximation register Figure 11-19 shows the relationship between the analog input voltage and the A/D conversion result. Figure 11-19. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 FF40H 3 00C0H 2 0080H 1 0040H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 496 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 11.7 A/D Converter Setup Flowchart. 11.6.1 Software trigger mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS). <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts. <4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. Figure 11-20. Example of Software Trigger Mode (Select Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE ADCS The trigger is not acknowledged. ADCE is cleared to 0. <8> <2> ADCS is set to 1 while in the conversion standby status. <4> <3> A/D conversion <3> ends and the next conversion starts. Stop Conversion status standby Data 0 (ANI0) ADCR, ADCRH Data 0 (ANI0) Data 0 (ANI0) Data 0 (ANI0) <6> ADCS is cleared to <7> 0 during A/D conversion operation. A hardware trigger is generated (and ignored). ADS is rewritten during <5> A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) <3> Data 0 (ANI0) ADS A/D conversion status ADCS is overwritten with 1 during A/D conversion operation. Conversion is <3> interrupted and restarts. Data 0 Data 0 (ANI0) (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 0 (ANI0) Data 1 (ANI1) Data 1 (ANI1) The trigger is not acknowledged. Conversion is interrupted. <3> Data 1 (ANI1) Conversion Stop standby status Data 1 (ANI1) INTAD R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 497 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS). <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion standby status. <5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D conversion does not start even if a hardware trigger is input while in the A/D conversion standby status. Figure 11-21. Example of Software Trigger Mode (Select Mode, One-Shot Conversion Mode) Operation Timing ADCE is cleared to 0. <8> <1> ADCE is set to 1. ADCE The trigger is not acknowledged. ADCS is ADCS is set to <2> 1 while in the <4> automatically <2> cleared to conversion 0 after standby status. <2> conversion ends. ADCS Stop Conversion status standby Data 0 (ANI0) A/D <3> conversion ends. Conversion Data 0 standby (ANI0) ADCR, ADCRH <4> <6> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) Data 0 (ANI0) ADS A/D conversion status ADCS is overwritten <4> <5> with 1 during A/D conversion operation. Data 0 (ANI0) Conversion is interrupted and restarts. Data 0 (ANI0) <2> ADCS is <7> cleared to 0 during A/D conversion operation. Conversion is interrupted. <3> <3> Conversion standby Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) The trigger is not acknowledged. Conversion Data 1 standby (ANI1) Conversion standby Stop status Data 1 (ANI1) INTAD R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 498 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D conversion of the channel following the specified channel automatically starts (until all four channels are finished). <4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. Figure 11-22. Example of Software Trigger Mode (Scan Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE The trigger is not acknowledged. ADCS ADCE is cleared to 0. <8> <2> ADCS is set to 1 while in the conversion standby status. <4> ADCS is overwritten with 1 during A/D conversion operation. ADCS is cleared A hardware trigger is <6> <7> to 0 during A/D generated (and ignored). conversion operation. The trigger is not acknowledged. <5> ADS is rewritten during A/D conversion operation. ADS ANI0 to ANI3 ANI4 to ANI7 A/D conversion ends and the <3> next conversion starts. A/D conversion status Stop Conversion Data 0 Data 1 status standby (ANI0) (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) ADCR, ADCRH Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) <3> Conversion is interrupted and restarts. Data 1 (ANI1) Data 0 Data 1 Data 2 (ANI0) (ANI1) (ANI2) Data 0 (ANI0) Data 3 Data 0 (ANI3) (ANI0) Conversion is interrupted and restarts. Data 1 (ANI1) Data 1 Data 2 Data 3 (ANI1) (ANI2) (ANI3) Data 4 (ANI4) Data 0 (ANI0) Conversion is interrupted. <3> Data 5 (ANI5) Data 6 (ANI6) Data 7 (ANI7) Data 4 (ANI4) Data 4 (ANI4) Data 5 (ANI5) Data 6 (ANI6) Data 7 (ANI7) Data 5 (ANI5) Conversion standby Stop status Data 4 (ANI4) INTAD The interrupt is generated four times. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 The interrupt is generated four times. The interrupt is generated four times. 499 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion of the four channels ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion standby status. <5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D conversion does not start even if a hardware trigger is input while in the A/D conversion standby status. Figure 11-23. Example of Software Trigger Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE ADCS The trigger is not acknowledged. ADCE is cleared to 0. <8> <2> ADCS is set to 1 while in the conversion standby status. <4> ADCS is automatically<2> cleared to 0 after conversion ends. <5> ADCS is overwritten with 1 during A/D conversion operation. <4> ADCS is cleared <7> to 0 during A/D conversion operation. <2> The trigger is not acknowledged. <6> ADS is rewritten during A/D conversion operation. ADS ANI4 to ANI7 ANI0 to ANI3 <3> A/D conversion A/D conversion status Stop Conversion Data 0 Data 1 status standby (ANI0) (ANI1) Data 2 (ANI2) Data 3 (ANI3) ADCR, ADCRH Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) ends. Conversion Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 Conversion Data 0 standby (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) Data 3 (ANI3) Conversion is interrupted and restarts. Conversion is <3> interrupted and restarts. Data 0 (ANI0) Data 1 Data 2 (ANI1) (ANI2) Data 3 (ANI3) Data 1 (ANI1) Data 4 (ANI4) Data 0 (ANI0) Data 5 (ANI5) Data 4 (ANI4) Data 6 (ANI6) Data 5 (ANI5) Conversion is interrupted. Data 7 Conversion Stop standby status (ANI7) Data 6 (ANI6) INTAD The interrupt is generated four times. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 The interrupt is generated four times. 500 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). <4> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not stop in this status. <9> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 11-24. Example of Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing ADCE is cleared to 0. <9> <1> ADCE is set to 1. ADCE <2> ADCS is set to 1. <5> A hardware trigger is generated during A/D conversion operation. <3> A hardware trigger is generated. Hardware trigger Trigger The trigger is not standby acknowledged. status ADCS Data 0 (ANI0) <4> A/D conversion ends and the next conversion<4> starts. ADS A/D conversion status Stop status Conversion standby Data 0 (ANI0) ADCR, ADCRH Data 0 (ANI0) Data 0 (ANI0) Data 0 (ANI0) The trigger is not acknowledged. ADCS is overwritten <7> ADCS is cleared <8> with 1 during A/D to 0 during A/D conversion operation. conversion operation. <6> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) Conversion is interrupted and Conversion Conversion is Conversion is is interrupted. restarts. <4> interrupted <4> interrupted <4> and restarts. and restarts. Data 1 Data 1 Data 1 Data 0 Data 1 Conversion Data 0 (ANI1) (ANI1) (ANI1) (ANI0) (ANI1) standby (ANI0) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Stop status Data 1 (ANI1) INTAD R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 501 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). <4> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. <5> After A/D conversion ends, the ADCS bit remains set to 1, and the system enters the A/D conversion standby status. <6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not stop in this status. <10> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 11-25. Example of Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing ADCE is cleared to 0. <10> <1> ADCE is set to 1. <2> ADCS is set to 1. ADCE <3>A hardware trigger <3> is generated. Hardware trigger <6> A hardware trigger is generated during A/D conversion operation. The trigger is not Trigger ADCS retains<5> acknowledged. standby the value 1. status <3> <5> ADCS <3> <3> ADCS is overwritten with 1 during <8> A/D conversion <5> operation. <5> <7>ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). <4> A/D conversion ends. A/D conversion status Stop status Conversion standby <9> ADCS is cleared to 0 during A/D conversion operation. Data 1 (ANI1) Data 0 (ANI0) ADS Trigger standby status Data 0 (ANI0) ADCR, ADCRH Conversion standby Conversion is interrupted and restarts. Data 0 (ANI0) Data 0 (ANI0) Data 0 (ANI0) <4> Conversion standby Conversion is interrupted and restarts. <4> Conversion is interrupted and restarts. <4> Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Conversion Data 1 standby (ANI1) Data 1 (ANI1) Data 1 (ANI1) Conversion standby Conversion is interrupted. Data 1 Conversion Stop (ANI1) standby status Data 1 (ANI1) INTAD R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 502 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D conversion of the channel following the specified channel automatically starts. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not stop in this status. <9> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. Figure 11-26. Example of Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE ADCE is cleared to 0. <9> <2> ADCS is set to 1. <5> A hardware trigger is generated during A/D conversion operation. <3> A hardware trigger is generated. Hardware trigger The trigger is not acknowledged. Trigger The trigger standby is not status acknowledged. Trigger standby status ADCS is overwritten <7> with 1 during A/D conversion operation. ADCS is cleared to 0 <8> during A/D conversion operation. ADCS <6> ADS is rewritten during A/D conversion operation. A/D conversion status ADCR, ADCRH ANI4 to ANI7 ANI0 to ANI3 ADS A/D conversion <4> ends and the next conversion starts. Stop status Conversion Data 0 standby (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 1 (ANI1) Conversion is interrupted and restarts. <4> Data 0 Data 1 Data 2 (ANI0) (ANI1) (ANI2) Data 3 Data 0 (ANI3) (ANI0) Data 0 (ANI0) Conversion is interrupted and restarts. Data 1 (ANI1) Data 1 Data 2 Data 3 (ANI1) (ANI2) (ANI3) Data 4 (ANI4) Data 0 (ANI0) Conversion is interrupted and restarts. <4> Data 5 (ANI5) Data 6 (ANI6) Data 7 (ANI7) Data 4 (ANI4) Data 5 (ANI5) Data 4 (ANI4) Data 5 (ANI5) Data 6 (ANI6) Data 7 (ANI7) Data 4 (ANI4) Data 6 (ANI6) Data 4 (ANI4) Data 5 (ANI5) Data 5 (ANI5) <4> Data 6 Data 7 (ANI6) (ANI7) Data 4 Data 5 Data 6 (ANI4) (ANI5) (ANI6) Conversion is interrupted. Data 4 Conversion Stop (ANI4) standby status Data 7 (ANI7) INTAD The interrupt is generated four times. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. 503 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. <5> After A/D conversion of the four channels ends, the ADCS bit remains set to 1, and the system enters the A/D conversion standby status. <6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not stop in this status. <10> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 11-27. Example of Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE Hardware trigger ADCE is cleared to 0. <10> <2> ADCS is set to 1. <3> A hardware trigger is generated. The trigger is not Trigger acknowledged. standby status <3> <6> A hardware trigger is generated during A/D conversion operation. <5> ADCS retains <5> the value 1. ADS is rewritten <7> during A/D conversion operation. ANI0 to ANI3 ANI4 to ANI7 <4> A/D Conversion is interrupted and restarts. conversion ends. A/D conversion status ADCR, ADCRH Stop Conversion status standby Conversion standby status <8> ADCS is overwritten <9> ADCS is cleared with 1 during A/D to 0 during A/D conversion operation. conversion operation. <5> ADCS ADS <3> <3> Data 0 Data 1 Data 2 Data 3 Conversion Data 0 (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) Data 0 Data 1 Data 2 (ANI0) (ANI1) (ANI2) Data 3 (ANI3) Data 1 (ANI1) Conversion is interrupted and restarts. <4> Data 0 Data 1 Data 2 Data 3 Conversion Data 0 (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) Data 0 (ANI0) Data 1 Data 2 (ANI1) (ANI2) Data 3 (ANI3) Data 1 (ANI1) Conversion is Conversion is interrupted. interrupted and restarts. <4> Data 4 Data 5 Data 6 Data 7 Conversion Data 4 (ANI4) (ANI5) (ANI6) (ANI7) standby (ANI4) Data 0 (ANI0) Data 4 Data 5 Data 6 (ANI4) (ANI5) (ANI6) Data 7 (ANI7) Data 5 (ANI5) Data 4 Data 5 (ANI4) (ANI5) Data 4 (ANI4) Data 6 (ANI6) Conversion Stop standby status Data 5 (ANI5) INTAD The interrupt is generated four times. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 The interrupt is generated four times. The interrupt is generated four times. 504 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts. (At this time, no hardware trigger is necessary.) <4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 11-28. Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <2> A hardware trigger is generated. Hardware trigger The trigger is not acknowledged. ADCS Trigger standby status Data 0 (ANI0) ADS A/D conversion status <4> A hardware trigger is generated during A/D conversion operation. <3> A/D conversion ends and the next conversion<3> starts. Stop status Data 0 (ANI0) ADCR, ADCRH Data 0 (ANI0) Data 0 (ANI0) Data 0 (ANI0) Trigger The trigger standby is not status acknowledged. ADCS is overwritten <6> ADCS is cleared <7> to 0 during A/D with 1 during A/D conversion operation. conversion operation. <5> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) Conversion is Conversion is Conversion is interrupted and Conversion is interrupted interrupted. restarts. interrupted <3> and restarts.<3> <3> and restarts. Data 0 Data 0 Data 1 Data 1 Data 1 Data 1 Stop status (ANI0) (ANI0) (ANI1) (ANI1) (ANI1) (ANI1) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 1 (ANI1) INTAD R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 505 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop status. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is initialized. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 11-29. Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <2> A hardware trigger is generated. Hardware trigger <2> <5> A hardware trigger is generated during A/D conversion operation. Trigger ADCS is automatically The trigger is not standby <4> acknowledged. status cleared to 0 after conversion ends. ADCS <2> <2> <4> <4> Trigger standby status <2> <7> ADCS is overwritten<4> with 1 during A/D conversion operation. is rewritten <6> ADS during A/D conversion <8> ADCS is cleared to 0 during A/D conversion operation. operation (from ANI0 to ANI1). Data 0 (ANI0) ADS <3> A/D conversion ends. A/D conversion status Stop status Data 0 (ANI0) ADCR, ADCRH Stop status Data 0 (ANI0) Conversion is interrupted <3> and restarts. Stop Data 0 status (ANI0) Data 0 (ANI0) Data 1 (ANI1) Conversion is interrupted and restarts.<3> Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Stop status Conversion is interrupted and restarts. <3> Data 1 (ANI1) Data 1 (ANI1) Data 1 (ANI1) Conversion is interrupted. Stop Data 1 status (ANI1) Stop status Data 1 (ANI1) INTAD R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 506 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D conversion of the channel following the specified channel automatically starts. <4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 11-30. Example of Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <4> A hardware trigger is generated during A/D conversion operation. <2> A hardware trigger is generated. Hardware trigger The trigger is not acknowledged. Trigger The trigger standby is not status acknowledged. Trigger standby status ADCS is overwritten <6> with 1 during A/D conversion operation. ADCS is cleared <7> to 0 during A/D conversion operation. ADCS <5> ADS is rewritten during A/D conversion operation. ADS A/D conversion status ADCR, ADCRH ANI4 to ANI7 ANI0 to ANI3 A/D conversion <3> ends and the next conversion starts. Stop status Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) <3> Conversion is interrupted and restarts. Data 1 (ANI1) Data 0 Data 1 Data 2 (ANI0) (ANI1) (ANI2) Data 0 (ANI0) Data 3 Data 0 (ANI3) (ANI0) <3> Conversion is interrupted and restarts. Data 1 (ANI1) Data 1 Data 2 Data 3 (ANI1) (ANI2) (ANI3) Data 4 (ANI4) Data 0 (ANI0) <3> Conversion is interrupted and restarts. Data 5 (ANI5) Data 6 (ANI6) Data 7 (ANI7) Data 4 (ANI4) Data 5 (ANI5) Data 4 (ANI4) Data 5 (ANI5) Data 6 (ANI6) Data 7 (ANI7) Data 4 (ANI4) Data 6 (ANI6) Data 4 (ANI4) Data 5 (ANI5) Data 5 (ANI5) Data 6 Data 7 (ANI6) (ANI7) Data 4 Data 5 Data 6 (ANI4) (ANI5) (ANI6) Conversion is interrupted. Data 4 (ANI4) Stop status Data 7 (ANI7) INTAD The interrupt is generated four times. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. 507 RL78/G13 CHAPTER 11 A/D CONVERTER 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop status. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 11-31. Example of Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <2> A hardware trigger is generated. <2> Hardware trigger The trigger is not Trigger acknowledged. standby ADCS status ADS <5> A hardware trigger is generated during A/D conversion operation. ADCS is automatically <4> cleared to 0 after conversion ends. <4> ANI0 to ANI3 ADCR, ADCRH Stop status <7>ADCS is overwritten<8> ADCS is cleared with 1 during A/D conversion operation. to 0 during A/D conversion operation. <4> ADS is rewritten <6> during A/D conversion operation. ANI4 to ANI7 Conversion is interrupted and restarts. <3> A/D conversion ends. A/D conversion status Conversion standby The trigger is not status acknowledged. <2> <2> Data 0 Data 1 Data 2 Data 3 (ANI0) (ANI1) (ANI2) (ANI3) Data 0 Data 1 Data 2 (ANI0) (ANI1) (ANI2) Stop status Data 0 (ANI0) Data 3 (ANI3) Data 1 (ANI1) Data 0 Data 1 Data 2 Data 3 (ANI0) (ANI1) (ANI2) (ANI3) Data 0 (ANI0) Conversion is interrupted and restarts. <4> Data 1 Data 2 (ANI1) (ANI2) Stop status Data 0 (ANI0) Data 3 (ANI3) Data 1 (ANI1) Data 4 Data 5 Data 6 Data 7 (ANI4) (ANI5) (ANI6) (ANI7) Data 0 (ANI0) Conversion is Conversion is interrupted. interrupted and restarts. <4> Data 4 Data 5 Data 6 (ANI4) (ANI5) (ANI6) Stop status Data 4 (ANI4) Data 7 (ANI7) Data 5 (ANI5) Data 4 Data 5 (ANI4) (ANI5) Data 4 (ANI4) Data 6 (ANI6) Stop status Data 5 (ANI5) INTAD The interrupt is generated four times. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 The interrupt is generated four times. The interrupt is generated four times. 508 RL78/G13 CHAPTER 11 A/D CONVERTER 11.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. 11.7.1 Setting up software trigger mode Figure 11-32. Setting up Software Trigger Mode <R> Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMC register settings PM register setting ANI0 to ANI14 pins: Set using the ADPC register ANI16 to ANI26 pins: Set using the PMC register The ports are set to the input mode. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is irrelevant.) * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. * ADS register ADS4 to ADS0 bits: These are used to select the analog input channels. Stabilization wait time count A ADCE bit setting Stabilization wait time count B ADCS bit setting The stabilization wait time indicated by stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: A=5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. The stabilization wait time (1 s) is counted by the software. After counting up to the stabilization wait time B ends, the ADCS bit of the ADM0 register is set (1), and A/D conversion starts. Start of A/D conversion The A/D conversion operations are performed. End of A/D conversion Note The A/D conversion end interrupt (INTAD) is generated. Storage of conversion results in the ADCR and ADCRH registers The conversion results are stored in the ADCR and ADCRH registers. Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 509 RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.2 Setting up hardware trigger no-wait mode Figure 11-33. Setting up Hardware Trigger No-Wait Mode <R> Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMC register settings PM register setting ANI0 to ANI14 pins: Set using the ADPC register ANI16 to ANI26 pins: Set using the PMC register The ports are set to the input mode. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. irrelevant.) * ADS register ADS4 to ADS0 bits: These are used to select the analog input channels. Stabilization wait time count A ADCE bit setting Stabilization wait time count B ADCS bit setting The stabilization wait time indicated by stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: A=5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. The stabilization wait time (1 s) is counted by the software. After counting up to the stabilization wait time B ends, the ADCS bit of the ADM0 register is set (1), and the system enters the hardware trigger standby status. Hardware trigger standby status Start of A/D conversion by generating a hardware trigger The A/D conversion operations are performed. End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated. Note The conversion results are stored in the ADCR and ADCRH registers. Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 510 RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.3 Setting up hardware trigger wait mode Figure 11-34. Setting up Hardware Trigger Wait Mode <R> Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMC register settings PM register setting ANI0 to ANI14 pins: Set using the ADPC register ANI16 to ANI26 pins: Set using the PMC register The ports are set to the input mode. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is irrelevant.) * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal. * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. AWC bit: This is used to set up the SNOOZE mode function. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. * ADS register ADS4 to ADS0 bits: These are used to select the analog input channels. Stabilization wait time count A ADCE bit setting The stabilization wait time indicated by stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: A=5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. Hardware trigger generation Stabilization wait time for A/D power supply Start of A/D conversion The system automatically counts up to the stabilization wait time for A/D power supply. After counting up to the stabilization wait time ends, A/D conversion starts The A/D conversion operations are performed. End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated.Note The conversion results are stored in the ADCR and ADCRH registers. Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 511 RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode) <R> Figure 11-35. Setup When Using Temperature Sensor Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: This is used to specify the select mode. * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is irrelevant.) * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. * ADS register ADISS and ADS4 to ADS0 bits: These are used to select temperature sensor 0 output or internal reference voltage output. Second A/D conversion time First A/D conversion time Stabilization wait time count A The stabilization wait time indicated by stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait If change the ADREFP1 and ADREFP0 = 1, 0: Setting prohibited ADCE bit setting The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. Stabilization wait time count B If a temperature sensor output/internal reference voltage output (ADISS bit of ADS register = 1) are selected as the analog input channel: B=1s ADCS bit setting After counting up to the stabilization wait time B ends, the ADCS bit of the ADM0 register is set (1), and A/D conversion starts Start of A/D conversion End of A/D conversion ADCS bit setting The A/D conversion end interrupt (INTAD) will be generated. After ADISS is set (1), the initial conversion result cannot be used. The ADCS bit of the ADM0 register is set (1), and A/D conversion starts. Start of A/D conversion End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated. Note The conversion results are stored in the ADCR and ADCRH registers. Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. <R> Caution This setting can be used only in HS (high-speed main) mode. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 512 RL78/G13 CHAPTER 11 A/D CONVERTER 11.7.5 Setting up test mode <R> Figure 11-36. Setting up Test Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: This is used to specify the select mode. * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode. ADSCM bit: This is used to specify the one-shot conversion mode. * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting * ADTES register setting (The order of the settings is irrelevant.) * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select for the reference voltage source. ADRCK bit: This is used to set the range for the A/D conversion result comparison value generated by the interrupt signal to AREA2. ADTYP bit: This is used to specify 10-bit resolution. * ADUL/ADLL register These set ADUL to FFH and ADLL to 00H (initial values). * ADS register ADS4 to ADS0 bits: These are used to set to ANI0. * ADTES register ADTES1, ADTES0 bits: AVREFM/AVREFP Stabilization wait time count A ADCE bit setting Stabilization wait time count B ADCS bit setting The stabilization wait time indicated by stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: A=5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: No wait The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. Counting 1 s for the stabilization wait time After counting up to the stabilization wait time B ends, the ADCS bit of the ADM0 register is set (1), and A/D conversion starts. Start of A/D conversion The A/D conversion operations are performed. End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated. Note The conversion results are stored in the ADCR and ADCRH registers. Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 513 RL78/G13 CHAPTER 11 A/D CONVERTER 11.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger. This is effective for reducing the operation current. <R> If the A/D conversion result range is specified using the ADUL and ADLL registers, A/D conversion results can be judged at a certain interval of time in SNOOZE mode. Using this function enables power supply voltage monitoring and input key judgment based on A/D inputs. In the SNOOZE mode, only the following two conversion modes can be used: * Hardware trigger wait mode (select mode, one-shot conversion mode) * Hardware trigger wait mode (scan mode, one-shot conversion mode) <R> Caution That the SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for fCLK. Figure 11-37. Block Diagram When Using SNOOZE Mode Function Real-time clock (RTC), 12-bit interval timer Hardware trigger input Clock request signal (internal signal) Clock generator A/D converter A/D conversion end interrupt request signalNote 1 (INTAD) High-speed on-chip oscillator clock When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP mode (for details about these settings, see 11.7.3 Setting up hardware trigger wait mode Note 2 ). Just before move to STOP mode, bit 2 (AWC) of A/D converter mode register 2 (ADM2) is set to 1. After the initial settings are specified, bit 0 (ADCE) of A/D converter mode register 0 (ADM0) is set to 1. If a hardware trigger is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to the A/D converter. After supplying this clock, the system automatically counts up to the stabilization wait time, and then A/D conversion starts. The SNOOZE mode operation after A/D conversion ends differs depending on whether an interrupt signal is generatedNote 1. Notes 1. Depending on the setting of the A/D conversion result comparison function (ADRCK bit, ADUL/ADLL register), there is a possibility of no interrupt signal being generated. 2. Be sure to set the ADM1 register to E2H or E3H. Remark The hardware trigger is INTRTC or INTIT. Specify the hardware trigger by using the A/D Converter Mode Register 1 (ADM1). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 514 RL78/G13 CHAPTER 11 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated. * While in the select mode When A/D conversion ends and an A/D conversion end interrupt request signal (INTAD) is generated, the A/D <R> converter returns to normal operation mode from SNOOZE mode. At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of the A/D converter mode register 2 (ADM2). If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZE or normal operation mode. * While in the scan mode If even one A/D conversion end interrupt request signal (INTAD) is generated during A/D conversion of the four channels, the clock request signal remains at the high level, and the A/D converter switches from the SNOOZE <R> mode to the normal operation mode. At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of A/D converter mode register 2 (ADM2) to 0. If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZE or normal operation mode. Figure 11-38. Operation Example When Interrupt Is Generated After A/D Conversion Ends (While in Scan Mode) INTRTC Clock request signal (internal signal) The clock request signal remains at the high level. ADCS Conversion channels Channel 1 Channel 2 Channel 3 Channel 4 Interrupt signal (INTAD) An interrupt is generated when conversion on one of the channels ends. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 515 RL78/G13 CHAPTER 11 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated. * While in the select mode If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE mode. * While in the scan mode If the A/D conversion end interrupt request signal (INTAD) is not generated even once during A/D conversion of the four channels, the clock request signal (an internal signal) is automatically set to the low level after A/D conversion of the four channels ends, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE mode. Figure 11-39. Operation Example When No Interrupt Is Generated After A/D Conversion Ends (While in Scan Mode) INTRTC Clock request signal (internal signal) The clock request signal is set to the low level. ADCS Conversion channels Channel 1 Channel 2 Channel 3 Channel 4 Interrupt signal (INTAD) No interrupt is generated when conversion ends for any channel. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 516 RL78/G13 CHAPTER 11 A/D CONVERTER 11.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 11-40. Overall Error Figure 11-41. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 AVREF 0 Analog input 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 517 RL78/G13 CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zeroscale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 11-42. Zero-Scale Error Figure 11-43. Full-Scale Error Full-scale error Ideal line 011 010 001 Zero-scale error Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 000 111 110 101 Ideal line 000 0 1 2 3 AVREF AVREF-3 0 Analog input (LSB) AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 11-44. Integral Linearity Error Figure 11-45. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Integral linearity error 0......0 0 Analog input Differential linearity error 0......0 0 AVREF Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Conversion time 518 RL78/G13 CHAPTER 11 A/D CONVERTER 11.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start operation. (2) Input range of ANI0 to ANI14 and ANI16 to ANI26 pins Observe the rated range of the ANI0 to ANI14 and ANI16 to ANI26 pins input voltage. If a voltage of VDD and AVREFP or higher and VSS and AVREFM or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. When internal reference voltage (1.45 V) is selected reference voltage source for the + side of the A/D converter, do not input internal reference voltage or higher voltage to a pin selected by the ADS register. However, it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage. <R> Caution Internal reference voltage (1.45 V) can be used only in HS (high-speed main) mode. (3) Conflicting operations <1> Conflict between the A/D conversion result register (ADCR, ADCRH) write and the ADCR or ADCRH register read by instruction upon the end of conversion The ADCR or ADCRH register read has priority. After the read operation, the new conversion result is written to the ADCR or ADCRH registers. <2> Conflict between the ADCR or ADCRH register write and the A/D converter mode register 0 (ADM0) write, the analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion The ADM0, ADS, or ADPC registers write has priority. The ADCR or ADCRH register write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREFP, VDD, ANI0 to ANI14, and ANI16 to ANI26 pins. <1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting external C as shown in Figure 11-46 is recommended. <3> Do not switch these pins with other pins during conversion. <4> The accuracy is improved if the HALT mode is set immediately after the start of conversion. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 519 RL78/G13 CHAPTER 11 A/D CONVERTER Figure 11-46. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREFP and VDD or equal to or lower than AVREFM and VSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREFP or VDD ANI0 to ANI14, ANI16 to ANI26 C = 100 to 1,000 pF (5) Analog input (ANIn) pins <R> <1> The analog input pins (ANI0 to ANI14) are also used as input port pins (P20 to P27, P150 to P156). When A/D conversion is performed with any of the ANI0 to ANI14 pins selected, do not change to output value P20 to P27, P150 to P156 while conversion is in progress; otherwise the conversion resolution may be degraded. <R> <2> If a pin adjacent to a pin that is being A/D converted is used as a digital I/O port pin, the A/D conversion result might differ from the expected value due to a coupling noise. Be sure to prevent such a pulse from being input or output. (6) Input impedance of analog input (ANIn) pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 1 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI14 and ANI16 to ANI26 pins (see Figure 11-46). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 520 RL78/G13 CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may be set just before the ADS register rewrite. Caution is therefore required since, at this time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D conversion for the post-change analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed. Figure 11-47. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ANIn ADCR ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF (8) Conversion results just after A/D conversion start While in the software trigger mode or hardware trigger no-wait mode, the first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (9) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), A/D port configuration register (ADPC), and port mode control register (PMC), the contents of the ADCR and ADCRH registers may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, ADPC, or PMC register. Using a timing other than the above may cause an incorrect conversion result to be read. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 521 RL78/G13 CHAPTER 11 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 11-48. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 11-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) <R> <R> AVREFP, VDD ANIn Pins R1 [k] C1 [pF C2 [pF] 3.6 V VDD 5.5 V ANI0 to ANI14 14 8 2.5 ANI16 to ANI26 18 8 7.0 ANI0 to ANI14 39 8 2.5 ANI16 to ANI26 53 8 7.0 ANI0 to ANI14 231 8 2.5 ANI16 to ANI26 321 8 7.0 ANI0 to ANI14 632 8 2.5 ANI16 to ANI26 902 8 7.0 2.7 V VDD 3.6 V 1.8 V VDD 2.7 V 1.6 V VDD < 2.7 V Remark The resistance and capacitance values shown in Table 11-6 are not guaranteed values. (11) Starting the A/D converter Start the A/D converter after the AVREFP and VDD voltages stabilize. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 522 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT CHAPTER 12 SERIAL ARRAY UNIT Serial array unit 0 has up to four serial channels, and serial array unit 1 has two. Each channel can achieve 3-wire serial (CSI), UART, and simplified I2C communication. Function assignment of each channel supported by the RL78/G13 is as shown below. * 20, 24, 25-pin products 0 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 Unit Channel - UART1 - IIC11 * 30, 32-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 1 - Unit Channel - UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 - * 36, 40, 44-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 1 CSI21 Unit Channel - UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 * 48, 52-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 Unit Channel 2 - 3 CSI11 0 CSI20 1 CSI21 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 IIC01 UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 523 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT * 64-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 2 CSI10 3 CSI11 Unit Channel 0 CSI20 1 CSI21 IIC01 UART1 IIC10 IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 * 80, 100, 128-pin products Unit 0 Channel 0 1 2 Used as CSI Used as UART Used as Simplified I C CSI00 UART0 IIC00 UART1 IIC10 1 CSI01 2 CSI10 3 CSI11 0 CSI20 1 CSI21 2 CSI30 3 CSI31 IIC01 IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 UART3 IIC30 IIC31 When "UART0" is used for channels 0 and 1 of the unit 0, CSI00 and CSI01 cannot be used, but CSI10, UART1, or IIC10 can be used. Caution Most of the following descriptions in this chapter use the units and channels of the 128-pin products as an example. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 524 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G13 has the following features. 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel. 3-wire serial communication is clocked communication performed by using three communication lines: one for the serial clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI). For details about the settings, see 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication. [Data transmission/reception] * Data length of 7 or 8 bits * Phase control of transmit/receive data * MSB/LSB first selectable * Level setting of transmit/receive data [Clock control] * Master/slave selection * Phase control of I/O clock * Setting of transfer period by prescaler and internal counter of each channel * Maximum transfer rate During master communication (CSI00): Max. fMCK/2 Notes 1, 2 During master communication (other than CSI00): Max. fMCK/4 Note 2 During slave communication: Max. fMCK/6 Note 2 [Interrupt function] * Transfer end interrupt/buffer empty interrupt [Error detection flag] * Overrun error In addition, CSIs of following channels supports the SNOOZE mode. When SCK input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only following CSIs can be specified for asynchronous reception. <R> * 20 to 64-pin products: CSI00 * 80 to 128-pin products: CSI00 and CSI20 Notes 1. In master communication (CSI00), maximum transfer rate become fMCK/2 when the following conditions. * 2.7 V EVDD0 = EVDD1 VDD 5.5 V * fMCK 24 MHz * PIOR1 = 0 Other cases, maximum transfer rate become fMCK/4. 2. Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 29 ELECTRICAL SPECIFICATIONS. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 525 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.1.2 UART (UART0 to UART3) This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered channel). The LIN-bus can be implemented by using timer array unit with an external interrupt (INTP0). For details about the settings, see 12.6 Operation of UART (UART0 to UART3) Communication. [Data transmission/reception] * Data length of 7, 8, or 9 bits Note * Select the MSB/LSB first * Level setting of transmit/receive data and select of reverse * Parity bit appending and parity check functions * Stop bit appending [Interrupt function] * Transfer end interrupt/buffer empty interrupt * Error interrupt in case of framing error, parity error, or overrun error [Error detection flag] * Framing error, parity error, or overrun error In addition, UARTs of following channels supports the SNOOZE mode. When RxD input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only following UARTs can be specified for asynchronous reception. * 20 to 64-pin products: UART0 * 80 to 128-pin products: UART0 and UART2 The LIN-bus is accepted in UART2 (0 and 1 channels of unit 1) (30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products only). [LIN-bus functions] * Wakeup signal detection Using the external interrupt (INTP0) and * Break field (BF) detection * Sync field measurement, baud rate calculation <R> timer array unit Note Only following UARTs can be specified for the 9-bit data length. 20 to 64-pin products: UART0 80 to 128-pin products: UART0 and UART2 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 526 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 12.1.3 Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master. Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop conditions are observed. For details about the settings, see 12.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) [Data transmission/reception] * Master transmission, master reception (only master function with a single master) * ACK output functionNote and ACK detection function * Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) * Manual generation of start condition and stop condition [Interrupt function] * Transfer end interrupt [Error detection flag] * ACK error, or overrun error * [Functions not supported by simplified I2C] * Slave transmission, slave reception * Arbitration loss detection function * Wait detection functions Note When receiving the last data, ACK will not be output if 0 is written to the SOEmn bit (serial output enable register m (SOEm)) and serial communication data output is stopped. See the processing flow in 12.8.3 (2) for details. Remarks 1. To use an I2C bus of full function, see CHAPTER 13 SERIAL INTERFACE IICA. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 527 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 12-1. Configuration of Serial Array Unit Item Configuration Note 1 Shift register 8 bits or 9 bits Buffer register Lower 8 bits or 9 bits of serial data register mn (SDRmn) Serial clock I/O SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31 pins (for 3-wire serial I/O), 2 SCL00, SCL01, SCL10, SCL11, SCL20, SCL21, SCL30, SCL31 pins (for simplified I C) Serial data input Notes 1, 2 SI00, SI01, SI10, SI11, SI20, SI21, SI30, SI31 pins (for 3-wire serial I/O), RXD0, RxD1, RxD3 pins (for UART), RXD2 pin (for UART supporting LIN-bus) Serial data output SO00, SO01, SO10, SO11, SO20, SO21, SO30, SO31 pins (for 3-wire serial I/O), TXD0, TxD1, TxD3 pins (for UART), TXD2 pin (for UART supporting LIN-bus), output controller Serial data I/O Control registers 2 SDA00, SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, SDA31 pins (for simplified I C) <Registers of unit setting block> * Peripheral enable register 0 (PER0) * Serial clock select register m (SPSm) * Serial channel enable status register m (SEm) * Serial channel start register m (SSm) * Serial channel stop register m (STm) * Serial output enable register m (SOEm) * Serial output register m (SOm) * Serial output level register m (SOLm) * Serial standby control register m (SSCm) * Input switch control register (ISC) * Noise filter enable register 0 (NFEN0) <Registers of each channel> * Serial data register mn (SDRmn) * Serial mode register mn (SMRmn) * Serial communication operation setting register mn (SCRmn) * Serial status register mn (SSRmn) * Serial flag clear trigger register mn (SIRmn) * Port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) * Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) * Port mode control registers 0, 3, 14 (PMC0, PMC3, PMC14) * Port mode registers 0, 1, 3 to 5, 7 to 9, 14 (PM0, PM1, PM3 to PM5, PM7 toPM9, PM14) * Port registers 0, 1, 3 to 5, 7 to 9, 14 (P0, P1, P3 to P5, P7 to P9, P14) (Notes and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 528 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Notes 1. The number of bits used as the shift register and buffer register differs depending on the unit and channel. * 20 to 64-pin products and mn = 00, 01: lower 9 bits * 80 to 128-pin products and mn = 00, 01, 10, 11: lower 9 bits * Other than above: lower 8 bits 2. The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending on the communication mode. * CSIp communication ... SIOp (CSIp data register) * UARTq reception ... RXDq (UARTq receive data register) * UARTq transmission ... TXDq (UARTq transmit data register) * IICr communication ... SIOr (IICr data register) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), q: UART number (q = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 529 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-1 shows the block diagram of the serial array unit 0. Figure 12-1. Block Diagram of Serial Array Unit 0 Noise filter enable register 0 (NFEN0) Serial output register 0 (SO0) 0 Peripheral enable register 0 (PER0) 0 CKO03 CKO02 CKO01 CKO00 0 PRS 012 PRS 011 PRS 003 PRS 010 PRS 002 4 0 0 0 SO03 SO02 SO01 PRS 001 PRS 000 4 SE02 SE01 SE00 SS03 SS02 SS01 SS00 Serial channel start register 0 (SS0) ST00 Serial channel stop register 0 (ST0) ST02 CK00 fCLK/20 to fCLK/215 0 (Clock division setting block) Clock controller fSCK Edge detection Output latch (P11 or P12) (Buffer register block) Shift register Output controller Mode selection CSI00 or IIC00 or UART0 (for transmission) Noise elimination enabled/ disabled Interrupt controller CKS00 CCS00 STS00 MD002 MD001 Serial mode register 00 (SMR00) DAP 00 CKP 00 When UART0 Serial data input pin (when CSI10: SI10) (when IIC10: SDA10) (when UART1: RXD1) PTC 000 DIR 00 SLC 001 SLC 000 PECT OVCT 00 00 Clear Error controller DLS 001 DLS 000 TSF 00 BFF 00 PEF 00 OVF 00 Serial status register 00 (SSR00) CK00 Serial data output pin (when CSI01: SO01) (when IIC01: SDA01) Channel 1 Communication controller Synchronous circuit Edge/level detection Selector Channel 2 Synchronous circuit Noise elimination enabled/ disabled Mode selection CSI01 or IIC01 or UART0 (for reception) Serial transfer end interrupt (when CSI01: INTCSI01) (when IIC01: INTIIC01) (when UART0: INTSR0) Error controller Serial transfer error interrupt (INTSRE0) CK00 CK01 Serial clock I/O pin (when CSI10: SCK10) (when IIC10: SCL10) PTC 001 Serial transfer end interrupt (when CSI00: INTCSI00) (when IIC00: INTIIC00) (when UART0: INTST0) Error information Serial communication operation setting register 00 (SCR00) CK01 Serial data input pin (when CSI01: SI01) (when IIC01: SDA01) EOC 00 Serial flag clear trigger register 00 (SIR00) Communication status Edge/level detection SNFEN00 Serial clock I/O pin (when CSI01: SCK01) (when IIC01: SCL01) Serial output level register 0 (SOL0) PM11 or P12 fTCLK Output latch (P10) PM10 RXE 00 SOL00 Serial data output pin (when CSI00: SO00) (when IIC00: SDA00) (when UART0: TXD0) Communication controller TXE 00 0 SOL02 fMCK Selector Selector CK01 Synchronous circuit SSEC0 SWC0 Serial data register 00 (SDR00) Channel 0 Serial data input pin (when CSI00: SI00) (when IIC00: SDA00) (when UART0: RxD0) ST01 Serial standby control register 0 (SSC0) Selector Selector Synchronous circuit SE03 Serial output SOE03 SOE02 SOE01 SOE00 enable register 0 (SOE0) fCLK/20 to fCLK/215 <R> SNFEN SNFEN 10 00 SO00 Serial channel enable status register 0 (SE0) ST03 Prescaler fCLK Serial clock I/O pin (when CSI00: SCK00) (when IIC00: SCL00) 0 Serial clock select register 0 (SPS0) PRS 013 SAU0EN 0 Serial data output pin (when CSI10: SO10) (when IIC10: SDA10) (when UART1: TXD1) Communication controller Edge/level detection Mode selection CSI10 or IIC10 or UART1 (for transmission) Serial transfer end interrupt (when CSI10: INTCSI10) (when IIC10: INTIIC10) (when UART1: INTST1) SNFEN10 CK01 When UART1 Serial clock I/O pin (when CSI11: SCK11) (when IIC11: SCL11) Serial data input pin (when CSI11: SI11) (when IIC11: SDA11) CK00 Channel 3 Synchronous circuit Selector R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Serial data output pin (when CSI11: SO11) (when IIC11: SDA11) Communication controller Edge/level detection Mode selection CSI11 or IIC11 or UART1 (for reception) Serial transfer end interrupt (when CSI11: INTCSI11) (when IIC11: INTIIC11) (when UART1: INTSR1) Error controller Serial transfer error interrupt (INTSRE1) 530 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-2 shows the block diagram of the serial array unit 1. Figure 12-2. Block Diagram of Serial Array Unit 1 Noise filter enable register 0 (NFEN0) Serial output register 1 (SO1) 0 Peripheral enable register 0 (PER0) 0 0 0 0 0 CKO13 CKO12 CKO11 CKO10 0 0 Serial clock select register 1 (SPS1) PRS 113 SAU1EN PRS 112 PRS 111 PRS 110 PRS 101 PRS 102 PRS 103 4 SE13 SE12 SE11 SE10 Serial channel enable status register 1 (SE1) Serial standby control register 1 (SSC1) SS13 SS12 SS11 SS10 Serial channel start register 1 (SS1) SSEC1 SWC1 ST10 Serial channel stop register 1 (ST1) ST12 ST11 Serial output SOE13 SOE12 SOE11 SOE10 enable register 1 (SOE1) fCLK/20 to fCLK/215 fCLK/20 to fCLK/215 <R> SO10 ST13 Prescaler fCLK SO12 SO11 PRS 100 4 SNFEN SNFEN 30 20 SO13 0 0 SOL12 SOL10 Serial output level register 1 (SOL1) Selector Selector Serial data register 10 (SDR10) (Clock division setting block) Selector CK10 Serial clock I/O pin (when CSI20: SCK20) (when IIC20: SCL20) Synchronous circuit fSCK Edge detection Output latch (P14 or P13) (Buffer register block) Serial data output pin (when CSI20: SO20) (when IIC20: SDA20) (when UART2: TxD2) fTCLK Shift register Output controller Interrupt controller Communication controller Synchronous circuit Noise elimination enabled/ disabled Edge/level detection SNFEN20 Serial flag clear trigger register 10 (SIR10) CKS10 CCS10 MD102 MD101 Serial mode register 10 (SMR10) Serial transfer end interrupt (when CSI20: INTCSI20) (when IIC20: INTIIC20) (when UART2: INTST2) PECT OVCT 10 10 Communication status Serial data input pin (when CSI20: SI20) (when IIC20: SDA20) (when UART2: RxD2) Mode selection CSI20 or IIC20 or UART2 (for transmission) Output latch (P15) PM15 PM14 or PM13 fMCK Clock controller CK11 Selector Channel 0 (LIN-bus supported) Error controller Error information TXE 10 RXE 10 DAP 10 When UART2 CKP 10 PTC 101 EOC 10 Serial data input pin (when CSI21: SI21) (when IIC21: SDA21) Serial data input pin (when CSI10: SI30) (when IIC10: SDA30) (when UART1: RXD3) SLC 101 SLC 100 Synchronous circuit Edge/level detection Selector Noise elimination enabled/ disabled DLS 100 TSF 10 BFF 10 PEF 10 OVF 10 Serial status register 10 (SSR10) Serial data output pin (when CSI21: SO21) (when IIC21: SDA21) Communication controller Mode selection CSI21 or IIC21 or UART2 (for reception) Serial transfer end interrupt (when CSI21: INTCSI21) (when IIC21: INTIIC21) (when UART2: INTSR2) Error controller Serial transfer error interrupt (INTSRE2) CK10 Channel 2 Synchronous circuit DLS 101 CK10 Channel 1 (LIN-bus supported) CK11 Serial clock I/O pin (when CSI10: SCK30) (when IIC10: SCL30) DIR 10 Serial communication operation setting register 10 (SCR10) CK11 Serial clock I/O pin (when CSI21: SCK21) (when IIC21: SCL21) PTC 100 Serial data output pin (when CSI30: SO30) (when IIC30: SDA30) (when UART3: TXD3) Communication controller Edge/level detection Mode selection CSI30 or IIC30 or UART3 (for transmission) Serial transfer end interrupt (when CSI30: INTCSI30) (when IIC30: INTIIC30) (when UART3: INTST3) SNFEN30 CK11 When UART3 Serial clock I/O pin (when CSI11: SCK31) (when IIC11: SCL31) Serial data input pin (when CSI11: SI31) (when IIC11: SDA31) CK10 Channel 3 Synchronous circuit Selector R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Serial data output pin (when CSI31: SO31) (when IIC31: SDA31) Communication controller Edge/level detection Mode selection CSI31 or IIC31 or UART3 (for reception) Serial transfer end interrupt (when CSI31: INTCSI31) (when IIC31: INTIIC31) (when UART3: INTSR3) Error controller Serial transfer error interrupt (INTSRE3) 531 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used Note 1. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin. The shift register cannot be directly manipulated by program. To read or write the shift register, use the lower 8/9 bits of serial data register mn (SDRmn). 8 7 6 5 4 3 2 1 0 Shift register (2) Lower 8/9 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) Note 1 or bits 7 to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets <R> the division ratio of the operation clock (fMCK, fSCK). When data is received, parallel data converted by the shift register is stored in the lower 8/9 bits. When data is to be transmitted, set transmit to be transferred to the shift register to the lower 8/9 bits. The data stored in the lower 8/9 bits of this register is as follows, depending on the setting of bits 0 and 1 (DLSmn0, DLSmn1) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data. * 7-bit data length (stored in bits 0 to 6 of SDRmn register) * 8-bit data length (stored in bits 0 to 7 of SDRmn register) * 9-bit data length (stored in bits 0 to 8 of SDRmn register) Note 1 The SDRmn register can be read or written in 16-bit units. The lower 8/9 bits of the SDRmn register can be read or written Note 2 as the following SFR, depending on the communication mode. * CSIp communication ... SIOp (CSIp data register) * UARTq reception ... RXDq (UARTq receive data register) * UARTq transmission ... TXDq (UARTq transmit data register) * IICr communication ... SIOr (IICr data register) Reset signal generation clears the SDRmn register to 0000H. Notes 1. Only following UARTs can be specified for the 9-bit data length. * 20 to 64-pin products: UART0 * 80 to 128-pin products: UART0, UART2 2. Writing in 8-bit units is prohibited when the operation is stopped (SEmn = 0). Remarks 1. After data is received, "0" is stored in bits 0 to 8 in bit portions that exceed the data length. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), q: UART number (q = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 532 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-3. Format of Serial Data Register mn (SDRmn) (mn = 00, 01, 10, 11) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) FFF48H, FFF49H (SDR10) After reset: 0000H Note , FFF4AH, FFF4BH (SDR11) FFF11H (SDR00) 15 14 13 12 11 10 R/W Note FFF10H (SDR00) 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 SDRmn Shift register Note 80 to 128-pin products Remark For the function of the higher 7 bits of the SDRmn register, see 12.3 Registers Controlling Serial Array Unit. Figure 12-4. Format of Serial Data Register mn (SDRmn) (mn = 02, 03, 10, 11, 12, 13) Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), FFF48H, FFF49H (SDR10) After reset: 0000H Note , FFF4AH, FFF4BH (SDR11) R/W Note FFF14H, FFF15H (SDR12), FFF16H, FFF17H (SDR13) FFF44H (SDR02) FFF45H (SDR02) 15 14 13 12 11 10 9 SDRmn 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 8 Shift register Note 20 to 64-pin products Caution Be sure to clear bit 8 to "0". Remark For the function of the higher 7 bits of the SDRmn register, see 12.3 Registers Controlling Serial Array Unit. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 533 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. * Peripheral enable register 0 (PER0) * Serial clock select register m (SPSm) * Serial mode register mn (SMRmn) * Serial communication operation setting register mn (SCRmn) * Serial data register mn (SDRmn) * Serial flag clear trigger register mn (SIRmn) * Serial status register mn (SSRmn) * Serial channel start register m (SSm) * Serial channel stop register m (STm) * Serial channel enable status register m (SEm) * Serial output enable register m (SOEm) * Serial output level register m (SOLm) * Serial output register m (SOm) * Serial standby control register m (SSCm) * Input switch control register (ISC) * Noise filter enable register 0 (NFEN0) * Port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) * Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) * Port mode contorol registers 0, 3, 14 (PMC0, PMC3, PMC14) * Port mode registers 0, 1, 3 to 5, 7 to 9, 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, PM14) * Port registers 0, 1, 3 to 5, 7 to 9, 14 (P0, P1, P3 to P5, P7 to P9, P14) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 534 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1. When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the PER0 register to 00H. Figure 12-5. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H Symbol PER0 After reset: 00H <7> R/W <6> IICA1EN RTCEN <5> Note 1 IICA0EN ADCEN SAUmEN 0 <4> <3> Note 2 SAU1EN <2> Note 3 SAU0EN <1> TAU1EN <0> Note 1 TAU0EN Control of serial array unit m input clock supply Stops supply of input clock. * SFR used by serial array unit m cannot be written. * Serial array unit m is in the reset status. 1 Enables input clock supply. * SFR used by serial array unit m can be read/written. Notes 1. 80 to 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Cautions 1. When setting serial array unit m, be sure to set the SAUmEN bit to 1 first. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the default value is read (except for the input switch control register (ISC), noise filter enable register 0 (NFEN0), port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14), port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14), port mode registers 0, 1, 3 to 5, 7 to 9, 14 (PM0, PM1, PM3 to PM5, <R> PM7 to PM9, PM14), port mode contorol registers 0, 3, 14 (PMC0, PMC3, PMC14), and port registers 0, 1, 3 to 5, 7 to 9, 14 (P0, P1, P3 to P5, P7 to P9, P14)). 2. Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 535 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected by bits 3 to 0. Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1). The SPSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL. Reset signal generation clears the SPSm register to 0000H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 536 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6. Format of Serial Clock Select Register m (SPSm) Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPSm 0 0 0 0 0 0 0 0 PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 PRS PRS PRS mk3 mk2 mk1 mk0 0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 32 MHz 0 0 0 1 fCLK/2 1 MHz 2.5 MHz 5 MHz 10 MHz 16 MHz 0 0 1 0 fCLK/2 2 500 kHz 1.25 MHz 2.5 MHz 5 MHz 8 MHz fCLK/2 3 250 kHz 625 kHz 1.25 MHz 2.5 MHz 4 MHz fCLK/2 4 125 kHz 313 kHz 625 kHz 1.25 MHz 2 MHz fCLK/2 5 62.5 kHz 156 kHz 313 kHz 625 kHz 1 MHz fCLK/2 6 31.3 kHz 78.1 kHz 156 kHz 313 kHz 500 kHz fCLK/2 7 15.6 kHz 39.1 kHz 78.1 kHz 156 kHz 250 kHz 0 0 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 Section of operation clock (CKmk) fCLK = 2 MHz fCLK = 5 MHz fCLK = 10 MHz fCLK = 20 MHz fCLK = 32 MHz 1 0 0 0 fCLK/2 8 7.81 kHz 19.5 kHz 39.1 kHz 78.1 kHz 125 kHz 1 0 0 1 fCLK/2 9 3.91 kHz 9.77 kHz 19.5 kHz 39.1 kHz 62.5 kHz fCLK/2 10 1.95 kHz 4.88 kHz 9.77 kHz 19.5 kHz 31.3 kHz fCLK/2 11 977 Hz 2.44 kHz 4.88 kHz 9.77 kHz 15.6 kHz fCLK/2 12 488 Hz 1.22 kHz 2.44 kHz 4.88 kHz 7.81 kHz fCLK/2 13 244 Hz 610 Hz 1.22 kHz 2.44 kHz 3.91 kHz fCLK/2 14 122 Hz 305 Hz 610 Hz 1.22 kHz 1.95 kHz fCLK/2 15 61 Hz 153 kHz 305 Hz 610 Hz 977 Hz 1 1 1 1 1 1 Note Note 1 PRS 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU). Caution Be sure to clear bits 15 to 8 to "0". Remarks 1. fCLK: CPU/peripheral hardware clock frequency 2. m: Unit number (m = 0, 1) 3. k = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 537 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or simplified I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART mode. Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit can be rewritten during operation. The SMRmn register can be set by a 16-bit memory manipulation instruction. Reset signal generation sets the SMRmn register to 0020H. Figure 12-7. Format of Serial Mode Register mn (SMRmn) (1/2) Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13) Symbol 15 14 13 12 11 10 9 SMRmn CKS CCS 0 0 0 0 0 mn mn CKS 8 7 STS 0 mn Note 6 SIS mn0 5 4 3 1 0 0 Note 2 1 0 MD MD MD mn2 mn1 mn0 Selection of operation clock (fMCK) of channel n mn 0 Operation clock CKm0 set by the SPSm register 1 Operation clock CKm1 set by the SPSm register Operation clock (fMCK) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the higher 7 bits of the SDRmn register, a transfer clock (fTCLK) is generated. CCS Selection of transfer clock (fTCLK) of channel n mn 0 Divided operation clock fMCK specified by the CKSmn bit 1 Clock input fSCK from the SCKp pin (slave transfer in CSI mode) Transfer clock fTCLK is used for the shift register, communication controller, output controller, interrupt controller, and error controller. When CCSmn = 0, the division ratio of operation clock (fMCK) is set by the higher 7 bits of the SDRmn register. STS Selection of start trigger source mn 2 0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I C). 1 Valid edge of the RXDq pin (selected for UART reception) Transfer is started when the above source is satisfied after 1 is set to the SSm register. Note The SMR01, SMR03, SMR11, and SMR13 registers only. Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or SMR12 register) to "0". Be sure to set bit 5 to "1". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), q: UART number (q = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 538 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W F0150H, F0151H (SMR10) to F0156H, F0157H (SMR13) Symbol 15 14 13 12 11 10 9 SMRmn CKS CCS 0 0 0 0 0 mn mn 8 7 STS 0 mn SIS Note 6 SIS mn0 5 4 3 1 0 0 Note 2 1 0 MD MD MD mn2 mn1 mn0 Controls inversion of level of receive data of channel n in UART mode mn0 Falling edge is detected as the start bit. 0 The input communication data is captured as is. Rising edge is detected as the start bit. 1 The input communication data is inverted and captured. MD MD mn2 mn1 0 0 CSI mode 0 1 UART mode 1 0 Simplified I C mode 1 1 Setting prohibited Setting of operation mode of channel n 2 MD Selection of interrupt source of channel n mn0 0 Transfer end interrupt 1 Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.) For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has run out. Note The SMR01, SMR03, SMR11, and SMR13 registers only. Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or SMR12 register) to "0". Be sure to set bit 5 to "1". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), q: UART number (q = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31) (4) Serial communication operation setting register mn (SCRmn) The SCRmn register is a communication operation setting register of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length. Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1). The SCRmn register can be set by a 16-bit memory manipulation instruction. Reset signal generation sets the SCRmn register to 0087H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 539 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H R/W F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13) Symbol 15 14 13 12 11 10 9 8 7 6 SCRmn TXE RXE DAP CKP 0 EOC PTC PTC DIR 0 mn mn mn mn mn mn1 mn0 mn TXE RXE mn mn 0 0 5 4 SLCm SLC n1 Note 1 3 2 0 1 1 DLSm DLS n1 mn0 0 Note 2 mn0 Setting of operation mode of channel n Disable communication. 0 1 Reception only 1 0 Transmission only 1 1 Transmission/reception DAP CKP mn mn 0 0 Selection of data and clock phase in CSI mode Type SCKp 1 SOp D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIp input timing 0 SCKp 1 2 SOp SIp input timing 1 SCKp 0 3 SOp D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIp input timing 1 SCKp 1 4 SOp SIp input timing 2 Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I C mode. EOC Selection of masking of error interrupt signal (INTSREx (x = 0 to 3)) mn <R> 0 Masks error interrupt INTSREx (INTSRx is not masked). 1 Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs). 2 Set EOCmn = 0 in the CSI mode, simplified I C mode, and during UART transmission Note 3 . Notes 1. The SCR00, SCR02, SCR10, and SCR12 registers only. 2. The SCR00 and SCR01 registers and SCR10 and SCR11 registers for 80- to 128-pins products only. Others are fixed to 1. 3. When using CSImn not with EOCmn = 0, error interrupt INTSREn may be generated. Caution Be sure to clear bits 3, 6, and 11 to "0" (Also clear bit 5 of the SCR01, SCR03, SCR11, or SCR13 register to 0). Be sure to set bit 2 to "1". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 540 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H R/W F0158H, F0159H (SCR10) to F015EH, F015FH (SCR13) Symbol 15 14 13 12 11 10 9 8 7 6 SCRmn TXE RXE DAP CKP 0 EOC PTC PTC DIR 0 mn mn mn mn mn mn1 mn0 mn PTC PTC mn1 mn0 0 0 5 4 SLCm SLC n1 Note 1 3 2 0 1 mn0 1 0 DLSm DLS n1 Note 2 mn0 Setting of parity bit in UART mode Transmission Reception Does not output the parity bit. Receives without parity Note 3 0 1 Outputs 0 parity . No parity judgment 1 0 Outputs even parity. Judged as even parity. 1 1 Outputs odd parity. Judges as odd parity. 2 Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I C mode. DIR Selection of data transfer sequence in CSI and UART modes mn 0 Inputs/outputs data with MSB first. 1 Inputs/outputs data with LSB first. 2 Be sure to clear DIRmn = 0 in the simplified I C mode. SLCm SLC n1 Note 1 Setting of stop bit in UART mode mn0 0 0 No stop bit 0 1 Stop bit length = 1 bit 1 0 Stop bit length = 2 bits (mn = 00, 02, 10, 12 only) 1 1 Setting prohibited When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely transferred. 2 Set 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I C mode. Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode. DLSm DLS n1 Note 2 Setting of data length in CSI and UART modes mn0 0 1 9-bit data length (stored in bits 0 to 8 of the SDRmn register) (settable in UART mode only) 1 0 7-bit data length (stored in bits 0 to 6 of the SDRmn register) 1 1 8-bit data length (stored in bits 0 to 7 of the SDRmn register) Other than above Setting prohibited 2 Be sure to set DLSmn1, DLSmn0 = 1, 1 in the simplified I C mode. Notes 1. The SCR00, SCR02, SCR10, and SCR12 registers only. 2. The SCR00 and SCR01 registers and SCR10 and SCR11 registers for 80 to 128-pins products only. Others are fixed to 1. 3. 0 is always added regardless of the data contents. Caution Be sure to clear bits 3, 6, and 11 to "0" (Also clear bit 5 of the SCR01, SCR03, SCR11, or SCR13 register to 0). Be sure to set bit 2 to "1". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 541 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (5) Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00, SDR01, SDR10 Note 1 , SDR11 Note 1 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10 Note 2, SDR11 Note 2, SDR12 and SDR13 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the <R> division ratio of the operation clock (fMCK, fSCK). If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operating clock by the higher 7 bits of the SDRmn register is used as the transfer clock. The lower 8/9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel data converted by the shift register is stored in the lower 8/9 bits, and during transmission, the data to be transmitted to the shift register is set to the lower 8/9 bits. The SDRmn register can be read or written in 16-bit units. However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation (SEmn = 1), a value is written only to the lower 8/9 bits of the SDRmn register. When the SDRmn register is read during operation, 0 is always read. Reset signal generation clears the SDRmn register to 0000H. Figure 12-9. Format of Serial Data Register mn (SDRmn) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) FFF48H, FFF49H (SDR10) After reset: 0000H Note 1 , FFF4AH, FFF4BH (SDR11) FFF10H (SDR00) FFF11H (SDR00) Symbol 15 14 13 12 11 10 9 SDRmn 8 7 6 5 FFF48H, FFF49H (SDR10) Note 2 FFF14H, FFF15H (SDR12) Note 1 After reset: 0000H , FFF4AH, FFF4BH (SDR11) 3 2 1 0 , FFF16H, FFF17H (SDR13) 15 14 13 12 11 2 1 0 R/W Note 2 Note 1 FFF44H (SDR02) FFF45H (SDR02) 10 9 SDRmn 8 7 6 5 4 3 0 SDRmn[15:9] <R> 4 0 Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), Symbol R/W Note 1 Transfer clock setting by dividing the operating clock (fMCK) 0 0 0 0 0 0 0 fMCK/2, fSCK/2 (in CSI slave) 0 0 0 0 0 0 1 fMCK/4 0 0 0 0 0 1 0 fMCK/6 0 0 0 0 0 1 1 fMCK/8 * * * * * * * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 0 fMCK/254 1 1 1 1 1 1 1 fMCK/256 Notes 1. 80 to 128-pin products 2. 30 to 64-pin products (Cautions and remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 542 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Cautions 1. Be sure to clear bit 8 of the SDR02, SDR03, SDR12, SDR13, and SDR10, and SDR11 of 30 to 64-pin products to "0". 2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used. 3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set SDRmn[15:9] to 0000001B or greater. 4. Do not write eight bits to the lower eight bits if operation is stopped (SEmn = 0). (If these bits are written to, the higher seven bits are cleared to 0.) Remarks 1. For the function of the lower 8/9 bits of the SDRmn register, see 12.2 Configuration of Serial Array Unit. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 543 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (6) Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared immediately when the corresponding bit of the SSRmn register is cleared. The SIRmn register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL. Reset signal generation clears the SIRmn register to 0000H. Figure 12-10. Format of Serial Flag Clear Trigger Register mn (SIRmn) Address: F0108H, F0109H (SIR00) to F010EH, F010FH (SIR03), After reset: 0000H R/W F0148H, F0149H (SIR10) to F014EH, F014FH (SIR13) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 2 FECT PEC mn FEC 1 Note Tmn 0 OVC Tmn Clear trigger of framing error of channel n Tmn 0 Not cleared 1 Clears the FEFmn bit of the SSRmn register to 0. PEC Clear trigger of parity error flag of channel n Tmn 0 Not cleared 1 Clears the PEFmn bit of the SSRmn register to 0. OVC Clear trigger of overrun error flag of channel n Tmn 0 Not cleared 1 Clears the OVFmn bit of the SSRmn register to 0. Note The SIR01, SIR03, SIR11, and SIR13 registers only. Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR00, SIR02, SIR10, or SIR12 register) to "0". Remarks 1. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) When the SIRmn register is read, 0000H is always read. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 544 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (7) Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error. The SSRmn register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SSRmn register can be set with an 8-bit memory manipulation instruction with SSRmnL. Reset signal generation clears the SSRmn register to 0000H. Figure 12-11. Format of Serial Status Register mn (SSRmn) (1/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SSRmn 0 0 0 0 0 0 0 0 0 TSF BFF 0 0 mn mn TSF 2 1 FEFm PEF n Note mn 0 OVF mn Communication status indication flag of channel n mn 0 Communication is stopped or suspended. 1 Communication is in progress. <Clear conditions> * The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set to 1 (communication is suspended). * Communication ends. <Set condition> * Communication starts. BFF Buffer register status indication flag of channel n mn 0 Valid data is not stored in the SDRmn register. 1 Valid data is stored in the SDRmn register. <Clear conditions> * Transferring transmit data from the SDRmn register to the shift register ends during transmission. * Reading receive data from the SDRmn register ends during reception. * The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set to 1 (communication is enabled). <Set conditions> * Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1 (transmission or transmission and reception mode in each communication mode). * Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and reception mode in each communication mode). * A reception error occurs. Note The SSR01, SSR03, SSR11, and SSR13 registers only. Caution If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is discarded and an overrun error (OVEmn = 1) is detected. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 545 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-11. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R F0140H, F0141H (SSR10) to F0146H, F0147H (SSR13) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SSRmn 0 0 0 0 0 0 0 0 0 TSF BFF 0 0 mn mn FEFm n 2 1 FEFm PEF n Note mn 0 OVF mn Framing error detection flag of channel n Note 0 No error occurs. 1 An error occurs (during UART reception). <Clear condition> * 1 is written to the FECTmn bit of the SIRmn register. <Set condition> * A stop bit is not detected when UART reception ends. PEF Parity/ACK error detection flag of channel n mn 0 No error occurs. 1 Parity error occurs (during UART reception) or ACK is not detected (during I C transmission). 2 <Clear condition> * 1 is written to the PECTmn bit of the SIRmn register. <Set condition> * The parity of the transmit data and the parity bit do not match when UART reception ends (parity error). * No ACK signal is returned from the slave channel at the ACK reception timing during I C transmission (ACK is 2 not detected). OVF Overrun error detection flag of channel n mn 0 No error occurs. 1 An error occurs <Clear condition> * 1 is written to the OVCTmn bit of the SIRmn register. <Set condition> * Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and reception mode in each communication mode). * Transmit data is not ready for slave transmission or transmission and reception in CSI mode. Note The SSR01, SSR03, SSR11, and SSR13 registers only. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 546 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (8) Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately when SEmn = 1. The SSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSm register can be set with an 1-bit or 8-bit memory manipulation instruction with SSmL. Reset signal generation clears the SSm register to 0000H. Figure 12-12. Format of Serial Channel Start Register m (SSm) Address: F0122H, F0123H (SS0) After reset: 0000H 15 14 13 12 11 10 9 8 7 6 5 4 SS0 0 0 0 0 0 0 0 0 0 0 0 0 After reset: 0000H R/W Address: F0162H, F0163H (SS1) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 SS1 0 0 0 0 0 0 0 0 0 0 0 0 SSmn <R> R/W Symbol Note 3 2 1 0 SS03 SS02 SS01 SS00 3 2 1 0 SS13 SS12 SS11 SS10 Operation start trigger of channel n 0 No trigger operation 1 Sets the SEmn bit to 1 and enters the communication wait status Note . If set the SSmn = 1 to during a communication operation, will wait status to stop the communication. At this time, holding status value of control register and shift register, SCKmn and SOmn pins, and FEFmn, PEFmn, OVFmn flags. Cautions 1. Be sure to clear bits 15 to 4 of the SS0 register, bits 15 to 4 of the SS1 register for 20 to 64-pin products and bits 15 to 4 of the SS1 register for 80 to 128-pin products to "0". 2. <R> For the UART reception, set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after 4 or more fMCK clocks have elapsed. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) 2. When the SSm register is read, 0000H is always read. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 547 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (9) Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0. The STm register can set written by a 16-bit memory manipulation instruction. The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction with STmL. Reset signal generation clears the STm register to 0000H. Figure 12-13. Format of Serial Channel Stop Register m (STm) Address: F0124H, F0125H (ST0) After reset: 0000H W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 ST0 0 0 0 0 0 0 0 0 0 0 0 0 Address: F0164H, F0165H (ST1) After reset: 0000H 2 1 0 ST03 ST02 ST01 ST00 W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 ST1 0 0 0 0 0 0 0 0 0 0 0 0 STm 3 3 2 1 0 ST13 ST12 ST11 ST10 Operation stop trigger of channel n n <R> 0 No trigger operation 1 Clears the SEmn bit to 0 and stops the communication operation Note . Note Holding status value of the control register and shift register, the SCKmn and SOmn pins, and FEFmn, PEFmn, OVFmn flags. Caution Be sure to clear bits 15 to 4 of the ST0 register, bits 15 to 2 of the ST1 register for 20 to 64-pin products and bits 15 to 4 of the ST1 register for 80 to 128-pin products to "0". Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) 2. When the STm register is read, 0000H is always read. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 548 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (10) Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0. Channel n that is enabled to operate cannot rewrite by software the value of the CKOmn bit (serial clock output of channel n) of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial clock pin. Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its value from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be created by software. The SEm register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SEmL. Reset signal generation clears the SEm register to 0000H. Figure 12-14. Format of Serial Channel Enable Status Register m (SEm) Address: F0120H, F0121H (SE0) After reset: 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 SE0 0 0 0 0 0 0 0 0 0 0 0 0 Address: F0160H, F0161H (SE1) After reset: 0000H 2 1 0 SE03 SE02 SE01 SE00 R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 SE1 0 0 0 0 0 0 0 0 0 0 0 0 SEm 3 3 2 1 0 SE13 SE12 SE11 SE10 Indication of operation enable/stop status of channel n n 0 Operation stops 1 Operation is enabled. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 549 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (11) Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin. For channel n, whose serial output is stopped, the SOmn bit value of the SOm register can be set by software, and that value can be output from the serial data output pin. In this way, any waveform of the start condition and stop condition can be created by software. The SOEm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SOEm register can be set with a 1-bit or 8-bit memory manipulation instruction with SOEmL. Reset signal generation clears the SOEm register to 0000H. Figure 12-15. Format of Serial Output Enable Register m (SOEm) Address: F012AH, F012BH (SOE0) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOE0 0 0 0 0 0 0 0 0 0 0 0 0 SOE SOE SOE SOE 03 02 01 00 Address: F016AH, F016BH (SOE1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOE1 0 0 0 0 0 0 0 0 0 0 0 0 SOE SOE SOE SOE 13 12 11 10 SOE Serial output enable/stop of channel n mn 0 Stops output by serial communication operation. 1 Enables output by serial communication operation. Caution Be sure to clear bits 15 to 4 of the SOE0 register, bits 15 to 2 of the SOE1 register for 20 to 64-pin products and bits 15 to 4 of the SOE1 register for 80 to 128-pin products to "0". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 550 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (12) Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n. The value of the CKOmn bit of this register is output from the serial clock output pin of channel n. The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When serial output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be changed only by a serial communication operation. The CKOmn bit of this register can be rewritten by software only when the channel operation is stopped (SEmn = 0). While channel operation is enabled (SEmn = 1), rewriting by software is ignored, and the value of the CKOmn bit can be changed only by a serial communication operation. To use the pin for serial interface as a port function pin, set the corresponding CKOmn and SOmn bits to "1". The SOm register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears the SOm register to 0F0FH. Figure 12-16. Format of Serial Output Register m (SOm) Address: F0128H, F0129H (SO0) After reset: 0F0FH R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO0 0 0 0 0 CKO CKO CKO CKO 0 0 0 0 SO SO SO SO 03 02 01 00 03 02 01 00 After reset: 0F0FH R/W Address: F0168H, F0169H (SO1) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SO1 0 0 0 0 CKO CKO CKO CKO 0 0 0 0 SO SO SO SO 13 12 11 10 13 12 11 10 CKO Serial clock output of channel n mn 0 Serial clock output value is "0". 1 Serial clock output value is "1". SO Serial data output of channel n mn 0 Serial data output value is "0". 1 Serial data output value is "1". Caution Be sure to clear bits 15 to 12 and 7 to 4 of the SO0 register to "0". Be sure to clear bits 15 to 10 and 7 to 2 of the SO1 register for 20 to 64-pin and bits 15 to 12 and 7 to 4 of the SO1 register for 80 to 128-pin to "0". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 551 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (13) Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode and 2 simplifies I C mode. Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn = 1). When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is. Rewriting the SOLm register is prohibited when the register is in operation (when SEmn = 1). The SOLm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SOLm register can be set with an 8-bit memory manipulation instruction with SOLmL. Reset signal generation clears the SOLm register to 0000H. Figure 12-17. Format of Serial Output Level Register m (SOLm) Address: F0134H, F0135H (SOL0) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOL0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL 0 SOL 02 Address: F0174H, F0175H (SOL1) After reset: 0000H 00 R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOL1 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL 0 SOL 12 SOL 10 Selects inversion of the level of the transmit data of channel n in UART mode mn Caution 0 Communication data is output as is. 1 Communication data is inverted and output. Be sure to clear bits 15 to 3, and 1 of the SOL0 register, bits 15 to 1 of the SOL1 register for 20 to 64-pin products, and 15 to 3, and 1 of the SOL1 register for 80 to 128-pin products to "0". Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 552 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (14) Serial standby control register m (SSCm) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSC1 Note register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI20 or UART2 serial data. The SSCm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSCm register can be set with an 8-bit memory manipulation instruction with SSCmL. Reset signal generation clears the SSCm register to 0000H. Note The SSC1 register is provided in the 80 to 128-pin products only. Caution The maximum transfer rate in the SNOOZE mode is as follows. * When using CSI00, CSI20 : 1 Mbps * When using UART0, UART2 : 9600 bps Figure 12-18. Format of Serial Standby Control Register m (SSCm) Address: F0138H (SSC0), F0178H (SSC1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SSCm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS 1 0 SS SWC ECm m Selection of whether to enable or stop the generation of transfer end interrupts ECm 0 Enable the generation of error interrupts (INTSRE0/INTSRE2). In the following cases, the clock request signal (an internal signal) to the clock generator is also cleared: * When the SWC bit is cleared to 0 * When the UART reception start bit is mistakenly detected 1 Stop the generation of error interrupts (INTSRE0/INTSRE2). In the following cases, the clock request signal (an internal signal) to the clock generator is also cleared: * When the SWCm bit is cleared to 0 * When the UART reception start bit is mistakenly detected * When the transfer end interrupt generation timing is based on a parity error or framing error <R> SWC Setting of the SNOOZE mode m 0 Do not use the SNOOZE mode function. 1 Use the SNOOZE mode function. * When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed without operating the CPU (the SNOOZE mode). * The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited. * Even when using SNOOZE mode, be sure to set the SWCm bit to 0 in normal operation mode and change it to 1 just before shifting to STOP mode. Also, be sure to change the SWCm bit to 0 after returning from STOP mode to normal operation mode. <R> Caution Setting SSECm, SWCm = 1, 0 is prohibited. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 553 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (15) Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to realize a LIN-bus communication operation by UART2 in coordination with an external interrupt and the timer array unit. When bit 0 is set to 1, the input signal of the serial data input (RXD2) pin is selected as an external interrupt (INTP0) that can be used to detect a wakeup signal. When bit 1 is set to 1, the input signal of the serial data input (RXD2) pin is selected as a timer input, so that wake up signal can be detected, the low width of the break field, and the pulse width of the sync field can be measured by the timer. The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the ISC register to 00H. Figure 12-19. Format of Input Switch Control Register (ISC) Address: F0073H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ISC 0 0 0 0 0 0 ISC1 ISC0 ISC1 0 Switching channel 7 input of timer array unit 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products: Uses the input signal of the TI07 pin as a timer input (normal operation). 20, 24, and 25-pin products: Do not use a timer input signal for channel 7. 1 Input signal of the RXD2 pin is used as timer input (detects the wakeup signal and measures the low width of the break field and the pulse width of the sync field). Setting is prohibited in the 20, 24, and 25-pin products. ISC0 Caution Switching external interrupt (INTP0) input 0 Uses the input signal of the INTP0 pin as an external interrupt (normal operation). 1 Uses the input signal of the RXD2 pin as an external interrupt (wakeup signal detection). Be sure to clear bits 7 to 2 to "0". R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 554 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (16) Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. 2 Disable the noise filter of the pin used for CSI or simplified I C communication, by clearing the corresponding bit of this register to 0. Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1. When the noise filter is enabled, CPU/peripheral hardware clock (fCLK) is synchronized with 2-clock match detection. When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware clock (fMCK). The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the NFEN0 register to 00H. Figure 12-20. Format of Noise Filter Enable Register 0 (NFEN0) Address: F0070H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 NFEN0 0 SNFEN30 0 SNFEN20 0 SNFEN10 0 SNFEN00 SNFEN30 Use of noise filter of RXD2 pin (RXD2/SDA20/SI20/P14) 0 Noise filter OFF 1 Noise filter ON Set SNFEN30 to 1 to use the RXD3 pin. Clear SNFEN30 to 0 to use the other than RxD3 pin. SNFEN20 Use of noise filter of RXD2 pin (RXD2/SDA20/SI20/P14) 0 Noise filter OFF 1 Noise filter ON Set SNFEN20 to 1 to use the RXD2 pin. Clear SNFEN20 to 0 to use the other than RxD2 pin. SNFEN10 Use of noise filter of RXD1 pin (RXD1/ANI16/SI10/SDA10/P03) 0 Noise filter OFF 1 Noise filter ON Set the SNFEN10 bit to 1 to use the RXD1 pin. Clear the SNFEN10 bit to 0 to use the other than RxD1 pin. SNFEN00 Use of noise filter of RXD0 pin (RXD0/TOOLRXD/SDA00/SI00/P11) 0 Noise filter OFF 1 Noise filter ON Set the SNFEN00 bit to 1 to use the RXD0 pin. Clear the SNFEN00 bit to 0 to use the other than RxD0 pin. Caution Be sure to clear bits 7 to 3, and 1 for 20 to 25-pin products, bits 7 to 5, 3, and 1 for 30 to 64-pin products and bits 7, 5, 3, and 1 for 80 to 128-pin products to "0". R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 555 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (17) Port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) These registers set the input buffer of ports 0, 1, 4, 5, 8, and 14 in 1-bit units. The PIM0, PIM1, PIM4, PIM5, PIM8, and PIM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the PIM0, PIM1, PIM4, PIM5, PIM8 and PIM14 registers to 00H. Refer to Tables 4-5 and 4-6 to see which PIMxx registers are provided for each product. Figure 12-21. Format of Port Input Mode Registers 0, 1, 4, 5, 8 and 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) (128-pin products) Address F0040H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIM0 0 0 0 PIM04 PIM03 0 PIM01 0 Address F0041H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIM1 PIM17 PIM16 PIM15 PIM14 PIM13 0 PIM11 PIM10 Address F0044H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIM4 0 0 0 PIM44 PIM43 0 0 0 Address F0045H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIM5 0 0 PIM55 PIM54 PIM53 0 0 0 Address F0048H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIM8 0 0 0 0 0 0 PIM81 PIM80 Address F004EH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PIM14 0 0 0 0 PIM143 PIM142 0 0 PIMmn Pmn pin input buffer selection (m = 0, 1, 4, 5, 8, 14; n = 0 to 7) 0 Normal input buffer 1 TTL input buffer R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 556 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (18) Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) These registers set the output mode of ports 0, 1, 4, 5, 7 to 9, and 14 in 1-bit units. The POM0, POM1, POM4, POM5, POM7 to POM9, and POM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction. <R> In addition, POM0, POM1, POM4, POM5, POM7 to POM9, POM14 register is set with PUxx register, whether or not to use the on-chip pull-up resistor. Reset signal generation clears the POM0, POM1, POM4, POM5, POM7 to POM9, and POM14 registers to 00H. Refer to Tables 4-5 and 4-6 to see which POMxx registers are provided for each product. Figure 12-22. Format of Port Output Mode Registers 0, 1, 4, 5, 7 to 9, and 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) (128-pin products) Address F0050H After reset: 00H Symbol 7 6 5 4 3 2 1 0 POM0 0 0 0 POM04 POM03 POM02 0 POM00 Address F0051H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 Address F0054H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 POM4 0 0 POM45 POM44 POM43 0 0 0 Address F0055H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 POM5 0 0 POM POM54 POM53 POM52 0 POM50 Address F0057H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 POM7 0 0 0 POM74 0 0 POM71 0 Address F0058H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 POM8 0 0 0 0 0 POM82 POM81 POM 80 Address F0059H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 POM9 0 POM 96 0 0 0 0 0 0 Address F005EH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 POM14 0 0 0 POM144 POM 143 POM142 0 0 POMmn 0 <R> Pmn pin output buffer selection (m = 0, 1, 4, 5, 7 to 9, 14; n = 0 to 7) Normal output mode When the input, enable to the PUmn bit 1 <R> R/W N-ch open-drain output (VDD tolerance Note 1 /EVDD tolerance Note 2 ) mode When the input, disable to the PUmn bit Notes 1. 20 to 52-pin products 2. 64 to 128-pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 557 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (19) Port mode registers 0, 1, 3 to 5, 7 to 9, and 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, and PM14) These registers set input/output of ports 0, 1, 3 to 5, 7 to 9, and 14 in 1-bit units. When using the ports (such as P02/ANI17/SO10/TXD1, P04/SCK10/SCL10) to be shared with the serial data output pin or serial clock output pin for serial data output or serial clock output, set the port mode register (PMxx) <R> bit and port mode control register (PMCxx) bit corresponding to each port to 0. And set the port register (Pxx) bit corresponding to each port to 1 Example: When using P02/ANI17/SO10/TXD1 for serial data output <R> Set the PMC02 bit of the port mode control register 0 to 0. Set the PM02 bit of the port mode register 0 to 0. Set the P02 bit of the port register 0 to 1. When using the ports (such as P04/SCK10/SCL10, P50/INTP1/SI11/SDA11) to be shared with the serial data input pin or serial clock input pin for serial data input or serial clock input, set the port mode register (PMxx) bit <R> corresponding to each port to 1. And set the port mode control register (PMCxx) bit to 0. At this time, the port register (Pxx) bit may be 0 or 1. Example: When using P50/INTP1/SI11/SDA11 for serial data input <R> Set the PMC50 bit of port mode control register 5 to 0. Set the PM50 bit of port mode register 5 to 1. Set the P50 bit of port register 5 to 0 or 1. The PM0, PM1, PM3 to PM5, PM7 to PM9, and PM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the PM0, PM1, PM3 to PM5, PM7 to PM9, and PM14 registers to FFH. Refer to Tables 4-5 and 4-6 to see which PMxx registers are provided for each product. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 558 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-23. Format of Port Mode Registers 0, 1, 3 to 5, 7 to 9, and 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, and 14) (128-pin products) Address: FFF20H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM0 1 PM06 PM05 PM04 PM03 PM02 PM01 PM00 Address: FFF21H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 Address: FFF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 1 1 PM31 PM30 Address: FFF24H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM4 PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40 Address: FFF25H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM5 1 1 PM55 PM54 PM53 PM52 PM51 PM50 Address: FFF27H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 Address: FFF28H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM8 PM87 PM86 PM85 PM84 PM83 PM82 PM81 PM80 Address: FFF29H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM9 PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 Address: FFF2EH After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM14 PM147 PM146 PM145 PM144 PM143 PM142 PM141 PM140 PMmn Pmn pin I/O mode selection (m = 0, 1, 3 to 5, 7 to 9, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 559 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.4 Operation stop mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 560 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0). The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. To stop the operation of serial array unit 0, set bit 2 (SAU0EN) to 0. To stop the operation of serial array unit 1, set bit 3 (SAU1EN) to 0. Figure 12-24. Peripheral Enable Register 0 (PER0) Setting When Stopping the Operation by Units (a) Peripheral enable register 0 (PER0) ... Set only the bit of SAUm to be stopped to 0. 7 PER0 6 RTCEN IICA1EN x x 5 Note 1 ADCEN 4 IICA0EN x 3 Note 2 SAU1EN x 2 Note 3 0/1 SAU0EN 0/1 1 TAU1EN x 0 Note 1 TAU0EN x Control of SAUm input clock 0: Stops supply of input clock 1: Supplies input clock Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Cautions 1. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the default value is read Note that this does not apply to the following registers. * Input switch control register (ISC) * Noise filter enable register 0 (NFEN0) <R> * Port input mode registers 0, 1, 4, 5, 8, 14 (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) * Port output mode registers 0, 1, 4, 5, 7 to 9, 14 (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) * Port mode control registers 0, 3, 14 (PMC0, PMC3, PMC14) * Port mode registers 0, 1, 3 to 5, 7 to 9, 14 (PM0, PM1, PM3 to PM5, PM7 to PM9, PM14) * Port registers 0, 1, 3 to 5, 7 to 9, 14 (P0, P1, P3 to P5, P7 to P9, P14) 2. Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 Remark x: Bits not used with serial array units (depending on the settings of other peripheral functions) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 561 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 12-25. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register m (STm) ... This register is a trigger register that is used to enable stopping communication/count by each channel. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 STm 3 2 1 STm3Note STm2 Note STm1 0/1 0/1 0/1 0 STm0 0/1 1: Clears the SEmn bit to 0 and stops the communication operation * Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0. (b) Serial Channel Enable Status Register m (SEm) ... This register indicates whether data transmission/reception operation of each channel is enabled or stopped. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SEm 3 SEm3 2 Note 0/1 SEm2 Note 0/1 1 0 SEm1 SEm0 0/1 0/1 0: Operation stops * The SEm register is a read-only status register, whose operation is stopped by using the STm register. With a channel whose operation is stopped, the value of the CKOmn bit of the SOm register can be set by software. (c) Serial output enable register m (SOEm) ... This register is a register that is used to enable or stop output of the serial communication operation of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SOEm3 SOEm2 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 Note Note 0/1 0/1 1 0 SOEm1 SOEm0 0/1 0/1 0: Stops output by serial communication operation * For channel n, whose serial output is stopped, the SOmn bit value of the SOm register can be set by software. (d) Serial output register m (SOm) ...This register is a buffer register for serial output of each channel. 15 14 13 12 11 10 CKOm3 CKOm2 SOm 0 0 0 0 1: Serial clock output value is "1" Note Note 0/1 0/1 9 8 7 6 5 4 CKOm1 CKOm0 0/1 0/1 0 0 0 0 3 2 SOm3 SOm2 1 0 Note Note SOm1 SOm0 0/1 0/1 0/1 0/1 1: Serial data output value is "1" * When using pins corresponding to each channel as port function pins, set the corresponding CKOmn, SOmn bits to "1". Note When Serial array unit 1, 80 to 128-pin products only. Remarks 1. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) : Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 562 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] * Data length of 7 or 8 bits * Phase control of transmit/receive data * MSB/LSB first selectable * Level setting of transmit/receive data [Clock control] * Master/slave selection * Phase control of I/O clock * Setting of transfer period by prescaler and internal counter of each channel * Maximum transfer rate During master communication (CSI00): Max. fMCK/2 Notes 1, 2 During master communication (other than CSI00): Max. fMCK/4 Note 2 During slave communication: Max. fMCK/6 Note 2 [Interrupt function] * Transfer end interrupt/buffer empty interrupt [Error detection flag] * Overrun error In addition, CSIs of following channels supports the SNOOZE mode. When SCK input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only following CSIs can be specified. <R> * 24 to 64-pin products: CSI00 * 80 to 128-pin products: CSI00 and CSI20 Notes 1. In master communication (CSI00), maximum transfer rate become fMCK/2 when the following conditions. * 2.7 V EVDD0 = EVDD1 VDD 5.5 V * fMCK 24 MHz * PIOR1 = 0 Other cases, maximum transfer rate become fMCK/4. 2. Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 563 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) are channels 0 to 3 of SAU0 and channels 0 to 3 of SAU1. * 20, 24, 25-pin products 0 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 Unit Channel - UART1 - IIC11 * 30, 32-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 1 - Unit Channel - UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 - * 36, 40, 44-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 1 CSI21 Unit Channel - UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 * 48, 52-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 2 - 3 CSI11 0 CSI20 1 CSI21 Unit Channel R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 IIC01 UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 564 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT * 64-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 Unit Channel 2 CSI10 3 CSI11 0 CSI20 1 CSI21 IIC01 UART1 IIC10 IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 * 80, 100, 128-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 2 CSI10 3 CSI11 0 CSI20 1 CSI21 2 CSI30 3 CSI31 Unit Channel IIC01 UART1 IIC10 IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 UART3 IIC30 IIC31 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) performs the following seven types of communication operations. * Master transmission (See 12.5.1.) * Master reception (See 12.5.2.) * Master transmission/reception (See 12.5.3.) * Slave transmission (See 12.5.4.) * Slave reception (See 12.5.5.) * Slave transmission/reception (See 12.5.6.) * SNOOZE mode function (See 12.5.7.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 565 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.1 Master transmission Master transmission is that the RL78/G13 outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O Target channel Pins used Interrupt CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Channel Channel Channel Channel Channel Channel Channel Channel 0 of SAU0 1 of SAU0 2 of SAU0 3 of SAU0 0 of SAU1 1 of SAU1 2 of SAU1 3 of SAU1 SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31, SO00 SO01 SO10 SO11 SO20 SO21 SO30 SO31 INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag None Transfer data length 7 or 8 bits Transfer rate Max. fMCK/2 [Hz] (CSI00), fMCK/4 [Hz] (other than CSI00) Min. fCLK/(2 x 2 x 128) [Hz] 15 Data phase Note fCLK: System clock frequency Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data output starts from the start of the operation of the serial clock. * DAPmn = 1: Data output starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-reverse (data output at the falling edge and data input at the rising edge of SCK) * CKPmn = 1: Reverse (data output at the rising edge and data input at the falling edge of SCK) Data direction Note MSB or LSB first Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 566 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) <R> (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0/1 0/1 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 Note 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 12.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 SDRmn 14 13 12 11 10 9 Baud rate setting (Operation clock (fMCK) division setting) 8 7 6 5 4 3 2 1 0 3 2 1 0 SOm3 SOm2 SOm1 SOm0 0/1 0/1 0/1 0/1 Transmit data (Transmit data setting) 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 0/1 0/1 0/1 0/1 Communication starts when these bits are 1 if the clock phase is non-reversed (the CKPmn bit of the SCRmn = 0). If the clock phase is reversed (CKPmn = 1), communication starts when these bits are 0. Note Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128pin product. This bit is fixed to 1 for the other registers. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 567 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 0/1 0/1 0/1 0/1 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 568 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-27. Initial Setting Procedure for Master Transmission Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Setting the SOm register Set the initial output level of the serial clock (CKOmn) and serial data (SOmn). Setting of the SOEm register Set the SOEmn bit to 1 and enable data output of the target channel. Setting a port register and a port mode Setting port register (Enable data output and clock output of the target channel by) Writing to the SSm register Completing initial setting Set the SSmn bit of the target channel to 1 (SEmn bit = 1 : to enable operation). Setting of SAU is completed. Write transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 569 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-28. Procedure for Stopping Master Transmission <R> Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 570 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-29. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target No (Essential) Master ready? (slave) or communication operation completed Yes Disable data output and clock output of Port manipulation (Essential) the target channel by setting a port register and a port mode register. (Selective) Re-set the register to change the operation Changing setting of the SPSm register clock setting. Re-set the register to change the (Selective) Changing setting of the SDRmn register transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register communication operation setting register mn (SCRmn) setting. Set the SOEmn bit to 0 to stop output (Selective) Changing setting of the SOEm register (Selective) Changing setting of the SOm register (Selective) from the target channel. Set the initial output level of the serial Changing setting of the SOEm register clock (CKOmn) and serial data (SOmn). Set the SOEmn bit to 1 and enable output from the target channel. Enable data output and clock output of (Essential) Port manipulation the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (Essential) Writing to the SSm register Completing resumption setting (SEmn = 1 : to enable operation). Setting is completed Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (slave) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 571 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-30. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin Transmit data 1 Shift register mn INTCSIp Shift operation Data transmission (8-bit length) Transmit data 2 Shift operation Data transmission (8-bit length) Transmit data 3 Shift operation Data transmission (8-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 572 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-31. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 12-27. (Select Transfer end interrupt) Main routine Set data for transmission and the number of data. Clear communication end flag Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Writing transmit data to SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) Wait for transmit completes When Transfer end interrupt is generated, it moves to interrupt processing routine Interrupt processing routine Transfer end interrupt No Transmitting next data? Yes Writing transmit data to SIOp (=SDRmn[7:0]) Sets communication completion flag Read transmit data, if any, from storage area and write it to SIOp. Update transmit data pointer. If not, set transmit end flag RETI Check completion of transmission by No Transmission completed? verifying transmit end flag Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 573 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-32. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <6> STmn SEmn SDRmn Transmit data 2 Transmit data 1 Transmit data 3 SCKp pin Transmit data 1 SOp pin Shift register mn INTCSIp Transmit data 2 Shift operation Transmit data 3 Shift operation Data transmission (8-bit length) Shift operation Data transmission (8-bit length) Data transmission (8-bit length) MDmn0 <4> TSFmn BFFmn <2><3> (Note) <2> <3> <2> <3> <5> Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 574 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-33. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting For the initial setting, refer to Figure 12-27. (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Main routine Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Writing transmit data to <2> SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) Wait for transmit completes When transfer end interrupt is generated, it moves to <3><5> interrupt processing routine. Buffer empty/transfer end interrupt Interrupt processing routine If transmit data is left, read them from storage area then write into SIOp, and update transmit data pointer and Number of communication data > 0? No number of transmit data. If no more transmit data, clear MDmn bit if it's set. If not, finish. Yes Writing transmit data to SIOp (=SDRmn[7:0]) No MDmn = 1? Yes <4> Subtract -1 from number of transmit data Clear MDmn0 bit to 0 Sets communication completion interrupt flag RETI No Check completion of transmission by Transmission completed? verifying transmit end flag Main routine Yes Write MDmn0 bit to 1 Disable interrupt (MASK) Yes Communication continued? No <6> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 12-32 Timing Chart of Master Transmission (in Continuous Transmission Mode). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 575 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.2 Master reception Master reception is that the RL78/G13 outputs a transfer clock and receives data from other device. 3-Wire Serial I/O Target channel Pins used Interrupt CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Channel Channel Channel Channel Channel Channel Channel Channel 0 of SAU0 1 of SAU0 2 of SAU0 3 of SAU0 0 of SAU1 1 of SAU1 2 of SAU1 3 of SAU1 SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31, SI00 SI01 SI10 SI11 SI20 SI21 SI30 SI31 INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 7 or 8 bits Transfer rate Max. fMCK/2 [Hz] (CSI00), fMCK/4 [Hz] (other than CSI00) Min. fCLK/(2 x 2 x 128) [Hz] 15 Data phase Note fCLK: System clock frequency Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data input starts from the start of the operation of the serial clock. * DAPmn = 1: Data input starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-reverse * CKPmn = 1: Reverse Data direction Note MSB or LSB first Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 576 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O <R> (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 1 0/1 0/1 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn TXEmn RXEmn DAPmn CKPmn 0 10 0 0 0 0 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 1Note 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 12.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 SDRmn 14 13 12 11 10 9 Baud rate setting (Operation clock (fMCK) division setting) 8 7 6 5 4 3 2 1 0 Receive data (Write FFH as dummy data.) 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 0/1 0/1 0/1 0/1 3 2 1 0 SOm3 SOm2 SOm1 SOm0 x x x x Communication starts when these bits are 1 if the clock phase is non-reversed (the CKPmn bit of the SCRmn = 0). If the clock phase is reversed (CKPmn = 1), communication starts when these bits are 0. Note Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128pin product. This bit is fixed to 1 for the other registers. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the CSI master reception mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 577 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) ...The register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 x x x x (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 578 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-35. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the transfer clock by dividing the operation Setting the SDRmn register clock (fMCK)). Set the initial output level of the serial Setting the SOm register clock (CKOmn). Enable clock output of the target channel by setting a port register and a port mode Setting port register. Set the SSmn bit of the target channel to 1 Writing to the SSm register (SEmn bit = 1: to enable operation). Set dummy data to the SIOp register (bits End of initial setting 7 to 0 of the SDRmn register) and start communication. <R> Figure 12-36. Procedure for Stopping Master Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 579 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-37. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target Completing master preparations? (Essential) No Yes Port manipulation (Essential) (slave) or communication operation completed Disable clock output of the target channel by setting a port register and a port mode register. (Selective) Re-set the register to change the operation Changing setting of the SPSm register clock setting. Re-set the register to change the (Selective) Changing setting of the SDRmn register transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register communication operation setting register mn (SCRmn) setting. (Selective) Changing setting of the SOm register (Selective) Clearing error flag Set the initial output level of the serial clock (CKOmn). If the OVF flag remain set, clear this using serial flag clear trigger register mn (SIRmn). Enable clock output of the target channel Port manipulation (Essential) by setting a port register and a port mode register. (Essential) Writing to the SSm register Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Setting is completed Completing resumption setting Sets dummy data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (slave) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 580 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-38. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Dummy data for reception Write Receive data 1 Dummy data Write Read Receive data 2 Receive data 3 Dummy data Write Read Read SCKp pin SIp pin Shift register mn Receive data 1 Receive data 2 Reception & shift operation Reception & shift operation Receive data 3 Reception & shift operation INTCSIp Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 581 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-39. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting Setting receive data Enables interrupt Writing dummy data to SIOp (=SDRmn[7:0]) For the initial setting, refer to Figure 12-35. (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing to SIOp makes SCKp signals out (communication starts) Wait for receive completes Interrupt processing routine When transfer end interrupt is generated, it moves to interrupt processing routine Transfer end interrupt generated? Reading receive data to SIOp (=SDRmn[7:0]) Read receive data then writes to storage area. Update receive data pointer and number of communication data. RETI No All reception completed? Check the number of communication data Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 582 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 12-40. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <8> STmn SEmn SDRmn Receive data 3 Dummy data Dummy data <2> Write <2> Write Receive data 2 Receive data 1 Dummy data <2> Write Read Read Read SCKp pin SIp pin Receive data 2 Receive data 1 Shift register mn Reception & shift operation Receive data 3 Reception & shift operation Reception & shift operation INTCSIp Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length) MDmn0 <5> TSFmn BFFmn <3> Caution <3> <4> <3> <4> <6> <7> The MDmn0 bit can be rewritten even during operation. However, rewrite it before receive of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last receive data. Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-41 Flowchart of Master Reception (in Continuous Reception Mode). 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 583 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-41. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 12-35. (Select buffer empty interrupt) <1> Main routine <2> Setting receive data Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing to SIOp makes SCKp signals out (communication starts) Writing dummy data to SIOp (=SDRmn[7:0]) Wait for receive completes When interrupt is generated, it moves to <3> <6> interrupt processing routine Buffer empty/transfer end interrupt BFFmn = 1? No Interrupt processing routine Yes Read receive data, if any, then write them to storage area, and update receive data pointer (also subtract -1 from number of transmit data) <4> Reading receive data to SIOp (=SDRmn[7:0]) <7> Subtract -1 from number of transmit data =0 Number of communication data? =1 <5> Clear MDmn0 bit to 0 2 <2> Writing dummy data to SIOp (=SDRmn[7:0]) RETI No Number of communication data = 0? When number of communication data becomes 0, receive completes Yes Main routine Disable interrupt (MASK) Write MDmn0 bit to 1 Yes Communication continued? No <8> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-40 Timing Chart of Master Reception (in Continuous Reception Mode). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 584 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.3 Master transmission/reception Master transmission/reception is that the RL78/G13 outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O Target channel Pins used Interrupt CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Channel Channel Channel Channel Channel Channel Channel Channel 0 of SAU0 1 of SAU0 2 of SAU0 3 of SAU0 0 of SAU1 1 of SAU1 2 of SAU1 3 of SAU1 SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31, SI00, SO00 SI01, SO01 SI10, SO10 SI11, SO11 SI20, SO20 SI21, SO21 SI30, SO30 SI31, SO31 INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 7 or 8 bits Transfer rate Max. fMCK/2 [Hz] (CSI00), fMCK/4 [Hz] (other than CSI00) Min. fCLK/(2 x 2 x 128) [Hz] 15 Data phase Note fCLK: System clock frequency Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data I/O starts at the start of the operation of the serial clock. * DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-reverse * CKPmn = 1: Reverse Data direction Note MSB or LSB first Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 585 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting <R> Figure 12-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 1 0/1 0/1 10 9 8 7 6 5 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 Note 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 12.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 SDRmn 14 13 12 11 10 9 Baud rate setting (Operation clock (fMCK) division setting) 8 7 6 5 4 3 2 1 0 Transmit data setting/receive data register 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 0/1 0/1 0/1 0/1 3 2 1 0 SOm3 SOm2 SOm1 SOm0 0/1 0/1 0/1 0/1 Communication starts when these bits are 1 if the clock phase is non-reverse (the CKPmn bit of the SCRmn = 0). If the clock phase is reversed (CKPmn = 1), communication starts when these bits are 0. Note Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128pin product. This bit is fixed to 1 for the other registers. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the CSI master transmission/reception mode : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 586 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 0/1 0/1 0/1 0/1 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm Note 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Serial array unit 0 only. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 587 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-43. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Set the initial output level of the serial Setting the SOm register clock (CKOmn) and serial data (SOmn). Set the SOEmn bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output and clock output of Setting port the target channel by setting a port register and a port mode register. Writing to the SSm register Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Set transmit data to the SIOp register (bits Completing initial setting 7 to 0 of the SDRmn register) and start communication. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 588 RL78/G13 <R> CHAPTER 12 SERIAL ARRAY UNIT Figure 12-44. Procedure for Stopping Master Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 589 RL78/G13 <R> CHAPTER 12 SERIAL ARRAY UNIT Figure 12-45. Procedure for Resuming Master Transmission/Reception Starting setting for resumption (Essential) Completing slave preparations? No Yes (Selective) Port manipulation Wait until stop the communication target (slave) or communication operation completed Disable data output and clock output of the target channel by setting a port register and a port mode register. (Essential) Changing setting of the SPSm register Re-set the register to change the operation clock setting. (Selective) Changing setting of the SDRmn register Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. (Selective) Changing setting of the SCRmn register Re-set the register to change serial communication operation setting register mn (SCRmn) setting. (Selective) Changing setting of the SOEm register Set the SOEmn bit to 0 to stop output from the target channel. (Selective) Changing setting of the SOm register Set the initial output level of the serial clock (CKOmn) and serial data (SOmn). (Selective) Changing setting of the SOEm register (Essential) Port manipulation (Essential) Writing to the SSm register Completing resumption setting R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Set the SOEmn bit to 1 and enable output from the target channel. Enable data output and clock output of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (SEmn = 1 : to enable operation). Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. 590 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-46. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Write Receive data 1 Transmit data 2 Write Read Receive data 2 Receive data 3 Transmit data 3 Write Read Read SCKp pin SIp pin Shift register mn SOp pin Receive data 1 Reception & shift operation Transmit data 1 Receive data 2 Reception & shift operation Transmit data 2 Receive data 3 Reception & shift operation Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 591 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-47. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 12-43. SAU default setting Main routine Setting transmission/reception data Enables interrupt (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data (Storage area, Transmission data pointer, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing transmit data to SIOp (=SDRmn[7:0]) Wait for transmission/reception completes Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) When transfer end interrupt is generated, it moves to interrupt processing routine. Interrupt processing routine Transfer end interrupt Read receive data to SIOp (=SDRmn[7:0]) Read receive data then writes to storage area, update receive data pointer RETI No Transmission/reception completed? If there are the next data, it continues Yes Main routine Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 592 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <8> STmn SEmn Receive data 3 SDRmn Transmit data 1 Transmit data 2 Write Write Receive data 1 Transmit data 3 Write Read Receive data 2 Read Read SCKp pin SIp pin Receive data 1 Shift register mn SOp pin Receive data 2 Reception & shift operation Transmit data 1 Receive data 3 Reception & shift operation Reception & shift operation Transmit data 2 Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) MDmn0 <5> TSFmn BFFmn <2><3> Note 1 <2> Note 2 <2> <4> <2> Note 2 <2> <4> <6> <7> Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. 2. The transmit data can be read by reading the SDRmn register during this period. At this time, the transfer operation is not affected. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-49 Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode). 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 593 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-49. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting For the initial setting, refer to Figure 12-43. (Select buffer empty interrupt) Main routine Setting transmission/reception data Enables interrupt Setting storage data and number of data for transmission/reception data (Storage area, Transmission data pointer, Reception data, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing dummy data to <2> SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) Wait for transmission/reception completes When transmission/reception interrupt is generated, it moves to interrupt processing routine <3> <6> Interrupt processing routine Buffer empty/transfer end interrupt No BFFmn = 1? Yes <4> Except for initial interrupt, read data received then write them to storage area, and update receive data pointer Reading reception data to SIOp (=SDRmn[7:0]) <7> Subtract -1 from number of transmit data If transmit data is left (number of communication data is equal or grater than 2), read them from storage area then =0 Number of communication data? =1 write into SIOp, and update transmit data pointer. If it's waiting for the last data to receive (number of communication data is equal to 1), change interrupt timing to communication end 2 Writing transmit data to SIOp (=SDRmn[7:0]) <5> Clear MDmn0 bit to 0 RETI No Number of communication data = 0? Yes Disable interrupt (MASK) Main routine Write MDmn0 bit to 1 Yes Continuing Communication? No <8> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-48 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 594 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.4 Slave transmission Slave transmission is that the RL78/G13 transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O Target channel Pins used Interrupt CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Channel Channel Channel Channel Channel Channel Channel Channel 0 of SAU0 1 of SAU0 2 of SAU0 3 of SAU0 0 of SAU1 1 of SAU1 2 of SAU1 3 of SAU1 SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31, SO00 SO01 SO10 SO11 SO20 SO21 SO30 SO31 INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 7 or 8 bits Transfer rate Max. fMCK/6 [Hz] Data phase Notes 1, 2 . Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data output starts from the start of the operation of the serial clock. * DAPmn = 1: Data output starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-reverse * CKPmn = 1: Reverse Data direction MSB or LSB first Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, and <R> SCK31 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least fSCK/2 as set by the SDRmn register. 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remarks 1. fMCK: Operation clock frequency of target channel fSCK: Serial clock frequency 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 595 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting <R> Figure 12-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 1 8 7 STSmn 6 5 4 3 1 0 0 2 SISmn0 0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0/1 0/1 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 1Note 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 12.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 14 SDRmn 13 12 11 10 9 0000000 Baud rate setting 8 7 6 5 4 3 2 1 0 3 2 1 0 SOm3 SOm2 SOm1 SOm0 0/1 0/1 0/1 0/1 Transmit data setting 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 x x x x Note Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128-pin product. This bit is fixed to 1 for the other registers. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the CSI slave transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 596 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 0/1 0/1 0/1 0/1 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 597 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-51. Initial Setting Procedure for Slave Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Setting the SDRmn register Set bits 15 to 9 to 0000000B for baud rate setting. Setting the SOm register Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output of the target channel Setting port by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 Writing to the SSm register Completing initial setting (SEmn bit = 1 : to enable operation). Initial setting is completed. Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 598 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-52. Procedure for Stopping Slave Transmission <R> Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 599 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-53. Procedure for Resuming Slave Transmission <R> Starting setting for resumption (Essential) Completing master preparations? No Yes (Selective) Port manipulation Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register. Re-set the register to change the operation (Selective) Changing setting of the SPSm register clock setting. Re-set the register to change serial (Selective) Changing setting of the SMRmn register mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register (Selective) Clearing error flag communication operation setting register mn (SCRmn) setting. If the OVF flag remain set, clear this using serial flag clear trigger register mn (SIRmn). (Selective) Changing setting of the SOEm register (Essential) Changing setting of the SOm register (Essential) Changing setting of the SOEm register Set the SOEmn bit to 0 to stop output from the target channel. Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable output from the target channel. Enable data output of the target channel (Essential) Port manipulation by setting a port register and a port mode register. (Essential) Writing to the SSm register (Essential) Starting communication Set the SSmn bit of the target channel to 1 (SEmn = 1 : to enable operation). Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. Completing resumption setting Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (master) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 600 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-54. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin Shift register mn INTCSIp Transmit data 1 Transmit data 2 Shift operation Shift operation Data transmission (8-bit length) Data transmission (8-bit length) Transmit data 3 Shift operation Data transmission (8-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 601 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-55. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 12-51. (Select transfer end interrupt) Set storage area and the number of data for transmit data Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Writing transmit data to SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Start communication when master start providing the clock Wait for transmit completes When transmit end, interrupt is generated No Transfer end interrupt? Yes Clear interrupt request flag Yes Transmitting next data? Determine if it completes by counting number of communication data No Disable interrupt (MASK) Yes Continuing transmit? No Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 602 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-56. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> STmn <6> SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin Transmit data 1 Shift register mn INTCSIp Transmit data 2 Shift operation Transmit data 3 Shift operation Data transmission (8-bit length) Shift operation Data transmission (8-bit length) Data transmission (8-bit length) MDmn0 <4> TSFmn BFFmn <2> <3> (Note) <2> <3> <2> <3> <5> Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 603 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-57. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting Main routine Setting transmit data For the initial setting, refer to Figure 12-51. (Select buffer empty interrupt) Set storage area and the number of data for transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) <2> Writing transmit data to SIOp (=SDRmn[7:0]) Read transmit data from buffer and write it to SIOp. Update transmit data pointer Start communication when master start providing the clock Wait for transmit completes When buffer empty/transfer end interrupt is generated, <3> <5> it moves to interrupt processing routine Interrupt processing routine Buffer empty/transfer end interrupt If transmit data is left, read them from storage area then write into Number of transmit data > 1? No SIOp, and update transmit data pointer. If not, change the interrupt to transmission complete Yes Reading transmit data Writing transmit data to SIOp (=SDRmn[7:0]) Subtract -1 from number of transmit data Clear MDmn0 bit to 0 It is determined as follows depending on the number of communication data. RETI No <4> +1: Transmit data completion 0: During the last data received -1: All data received completion Number of communication data = -1? Main routine Yes Disable interrupt (MASK) Write MDmn0 bit to 1 Yes Communication continued? No <6> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 12-56 Timing Chart of Slave Transmission (in Continuous Transmission Mode). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 604 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.5 Slave reception Slave reception is that the RL78/G13 receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O Target channel Pins used Interrupt CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Channel Channel Channel Channel Channel Channel Channel Channel 0 of SAU0 1 of SAU0 2 of SAU0 3 of SAU0 0 of SAU1 1 of SAU1 2 of SAU1 3 of SAU1 SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31, SI00 SI01 SI10 SI11 SI20 SI21 SI30 SI31 INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 7 or 8 bits Transfer rate Max. fMCK/6 [Hz] Data phase Notes 1, 2 Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data input starts from the start of the operation of the serial clock. * DAPmn = 1: Data input starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-reverse * CKPmn = 1: Reverse Data direction MSB or LSB first Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, and <R> SCK31 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least fSCK/2 as set by the SDRmn register. 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remarks 1. fMCK: Operation clock frequency of target channel fSCK: Serial clock frequency 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 605 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O <R> (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 1 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0 Interrupt source of channel n 0: Transfer end interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 1 0/1 0/1 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn TXEmn RXEmn DAPmn CKPmn 0 10 0 0 0 0 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 0 DLSmn1 DLSmn0 Note 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 12.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 14 SDRmn 13 12 11 10 9 0000000 Baud rate setting 8 7 6 5 4 3 2 1 0 3 2 1 0 SOm3 SOm2 SOm1 SOm0 x x x x Receive data 0 SIOp (d) Serial output register m (SOm) ...The Register that not used in this mode. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 x x x x Note Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128pin product. This bit is fixed to 1 for the other registers. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the CSI slave transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 606 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) ...The Register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 x x x x (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 607 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-59. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set baud rate setting (bits 15 to 9) to Setting the SDRmn register 0000000B. Enable data input and clock input of the target channel by setting a port register Setting port and a port mode register. Set the SSmn bit of the target channel to 1 Writing to the SSm register (SEmn bit = 1: to enable operation). Wait for a clock from the master. Completing initial setting <R> Figure 12-60. Procedure for Stopping Slave Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. (Essential) Changing setting of the SOEm register (Selective) Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 608 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-61. Procedure for Resuming Slave Reception <R> Starting setting for resumption Wait until stop the communication target Completing master preparations? (Essential) No Yes (Essential) Port manipulation (Selective) Changing setting of the SPSm register (Selective) Changing setting of the SMRmn register (Selective) Changing setting of the SCRmn register (master) Disable clock output of the target channel by setting a port register and a port mode register. Re-set the register to change the operation clock setting. Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial communication operation setting register mn (SCRmn) setting. If the OVF flag remain set, clear this (Selective) Clearing error flag using serial flag clear trigger register mn (SIRmn). Enable clock output of the target channel (Essential) Port manipulation by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (Essential) Writing to the SSm register (SEmn bit = 1: to enable operation). Wait for a clock from the master. Completing resumption setting Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (master) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 609 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-62. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Receive data 1 Receive data 3 Receive data 2 Read Read Read SCKp pin SIp pin Shift register mn INTCSIp Receive data 1 Reception & shift operation Data reception (8-bit length) Receive data 2 Reception & shift operation Data reception (8-bit length) Receive data 3 Reception & shift operation Data reception (8-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 610 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-63. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting Ready for reception For the initial setting, refer to Figure 12-59. (Select transfer end interrupt only) Clear storage area setting and the number of receive data (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Wait for recieve completes Start communication when master start providing the clock Interrupt processing routine When transmit end, interrupt is generated Transfer end interrupt Reading receive data to SIOp (=SDRmn[7:0]) Read receive data then writes to storage area, and counts up the number of receive data. Update receive data pointer. RETI No Reception completed? Check completion of number of receive data Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 611 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.6 Slave transmission/reception Slave transmission/reception is that the RL78/G13 transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O Target channel Pins used Interrupt CSI00 CSI01 CSI10 CSI11 CSI20 CSI21 CSI30 CSI31 Channel Channel Channel Channel Channel Channel Channel Channel 0 of SAU0 1 of SAU0 2 of SAU0 3 of SAU0 0 of SAU1 1 of SAU1 2 of SAU1 3 of SAU1 SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, SCK31, SI00, SO00 SI01, SO01 SI10, SO10 SI11, SO11 SI20, SO20 SI21, SO21 SI30, SO30 SI31, SO31 INTCSI00 INTCSI01 INTCSI10 INTCSI11 INTCSI20 INTCSI21 INTCSI30 INTCSI31 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 7 or 8 bits Transfer rate Max. fMCK/6 [Hz] Data phase Notes 1, 2 . Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data I/O starts from the start of the operation of the serial clock. * DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-reverse * CKPmn = 1: Reverse Data direction MSB or LSB first Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK10, SCK11, SCK20, SCK21, SCK30, and <R> SCK31 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least fSCK/2 as set by the SDRmn register. 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remarks 1. fMCK: Operation clock frequency of target channel fCLK: Serial clock frequency 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 612 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting <R> Figure 12-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 1 8 7 STSmn 6 5 4 3 1 0 0 2 SISmn0 0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 1 0/1 0/1 10 9 8 7 6 5 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 1 Note 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 12.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 14 SDRmn 13 12 11 10 9 0000000 Baud rate setting 8 7 6 5 4 3 2 1 0 Transmit data setting/receive data register 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 x x x x 3 2 1 0 SOm3 SOm2 SOm1 SOm0 0/1 0/1 0/1 0/1 Note Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128pin product. This bit is fixed to 1 for the other registers. Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the CSI slave transmission/reception mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 613 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 0/1 0/1 0/1 0/1 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 614 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-65. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set bits 15 to 9 to 0000000B for baud Setting the SDRmn register Setting the SOm register rate setting. Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output of the target channel Setting port by setting a port register and a port mode register. Writing to the SSm register Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Initial setting is completed. Completing initial setting Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 615 RL78/G13 <R> CHAPTER 12 SERIAL ARRAY UNIT Figure 12-66. Procedure for Stopping Slave Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 616 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-67. Procedure for Resuming Slave Transmission/Reception <R> Starting setting for resumption Completing master preparations? (Essential) No Yes (Essential) Port manipulation Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register. (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting. (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register communication operation setting register mn (SCRmn) setting. If the OVF flag remain set, clear this using Clearing error flag (Selective) serial flag clear trigger register mn (SIRmn). (Selective) Changing setting of the SOEm register Set the SOEmn bit to 0 to stop output from the target channel. Set the initial output level of the serial (Selective) Changing setting of the SOm register (Selective) Changing setting of the SOEm register (Essential) Port manipulation data (SOmn). Set the SOEmn bit to 1 and enable output from the target channel. Enable data output of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (Essential) Writing to the SSm register (SEmn = 1 : to enable operation). Sets transmit data to the SIOp register (Essential) Starting communication (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. Completing resumption setting Cautions 1. 2. Be sure to set transmit data to the SlOp register before the clock from the master is started. If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (master) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 617 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-68. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Write Receive data 1 Transmit data 2 Write Read Receive data 2 Receive data 3 Transmit data 3 Write Read Read SCKp pin SIp pin Shift register mn SOp pin Receive data 1 Reception & shift operation Transmit data 1 Receive data 2 Reception & shift operation Transmit data 2 Receive data 3 Reception & shift operation Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 618 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-69. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication SAU default setting Setting transmission/reception data Main routine Enables interrupt Writing transmit data to SIOp (=SDRmn[7:0]) For the initial setting, refer to Figure 12-65 (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data (Storage area, Transmission/reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Start communication when master start providing the clock Wait for transmission/reception completes Interrupt processing routine When transfer end interrupt is generated, it moves to interrupt processing routine Transfer end interrupt Reading receive data to SIOp (=SDRmn[7:0]) Read receive data and write it to storage area. Update receive data pointer. RETI No Transmission/reception completed? Yes Yes Transmission/reception next data? Update the number of communication data and confirm if next transmission/reception data is available No Disable interrupt (MASK) Main routine Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 619 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-70. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <8> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Write Write Receive data 1 Transmit data 3 Write Read Receive data 3 Receive data 2 Read Read SCKp pin SIp pin Receive data 1 Shift register mn SOp pin Receive data 2 Reception & shift operation Transmit data 1 Receive data 3 Reception & shift operation Reception & shift operation Transmit data 2 Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) MDmn0 <5> TSFmn BFFmn <2> <3> Note 1 <2> Note 2 <3> <4> <2> Note 2 <3> <4> <6> <7> Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. 2. The transmit data can be read by reading the SDRmn register during this period. At this time, the transfer operation is not affected. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 12-71 Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode). 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 620 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-71. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting Main routine Setting transmission/reception data Enables interrupt For the initial setting, refer to Figure 12-59 (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data (Storage area, Transmission/reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Start communication when master start providing the clock Wait for transmission completes When buffer empty/transfer end is generated, it moves interrupt processing routine <3> <6> Buffer empty/transfer end interrupt No Interrupt processing routine BFFmn = 1? Yes <4> Other than the first interrupt, read reception data then writes to storage area, update receive data pointer Read receive data to SIOp (=SDRmn[7:0]) <7> Subtract -1 from number of transmit data =0 Number of communication data? Yes =1 If transmit data is remained, read it from storage area and write it to SIOp. Update storage pointer. If transmit completion (number of communication data = 1), Change the transmission completion interrupt 2 <5> Writing transmit data to SIOp (=SDRmn[7:0]) Clear MDmn0 bit to 0 RETI No Number of communication data = 0? Yes Main routine Disable interrupt (MASK) Write MDmn0 bit to 1 Yes Communication continued? No <8> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 12-70 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 621 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 SNOOZE mode function <R> SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU operation by detecting SCKp pin input. Only following channels can be set to the SNOOZE mode. * 24 to 64-pin products: CSI00 * 80 to 128-pin products: CSI00 and CSI20 When using the SNOOZE mode function, set the SWCm bit of serial standby control register m (SSCm) to 1 just before switching to the STOP mode. Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for fCLK. 2. The maximum transfer rate when using CSIp in the SNOOZE mode is 1 Mbps. (1) SNOOZE mode operation (once startup) Figure 12-72. Timing Chart of SNOOZE Mode Operation (once startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation status Normal peration STOP mode SNOOZE mode Normal peration <4> <3> SS00 <11> ST00 <1> <9> SE00 SWC0 SSEC0 <10> L Clock request signal (internal signal) Receive data 2 SDR00 Receive data 1 <8> Read Note 1 SCK00 pin SI00 pin Receive data 1 Shift register 00 INTCSI00 Receive data 2 Reception & shift operation Reception & shift operation Note 2 Data reception (8-bit length) Data reception (8-bit length) TSF00 <2> Notes 1. 2. <7> <5><6> Only read received data while SWCm = 1 and before the next edge of the SCKp pin input is detected. The transfer end interrupt (INTCSIp) is cleared either when SWCm is cleared to 0 or when the next edge of the SCKp pin input is detected. <R> Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm0 bit to 1 (clear the SEm0 bit, and stop the operation). And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release). Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-73. Flowchart of SNOOZE Mode Operation (once startup). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; p = 00 m = 0, 1; p = 00, 20 622 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-73. Flowchart of SNOOZE Mode Operation (once startup) SNOOZE mode operation No TSFmn = 0 for all channels? Yes Normal operation <1> Write STm0 bit to 1 Become the operation STOP status (SEm0 = 0) SAU default setting SMRm0, SCRm0 : SDRm0[15:9] : <2> Setting SSCm register (SWCm = 1, SSECm = 0) <3> Write SSm0 bit to 1 Enables interrupt <4> Entered the STOP mode Communication setting Setting 0000000B Setting SNOOZE mode Become the communication wait status (SEm0 = 1) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). fCLK supplied to the SAU is stopped. STOP mode <5> SCKp edge detected (Entered the SNOOZE mode) SNOOZE mode Supplying a clock to CSIp (CSIp is receive operation) <6> Transfer interrupt (INTCSIp) is generated (CSIp is receive completion) <7> Normal operation <8> Reading receive data to SIOp (=SDRmn[7:0]) <9> Write STm0 bit to 1 Become the operation STOP status (SEm0 = 0) <10> Write SWCm bit to 1 Reset SNOOZE mode setting <11> Write SSm0 bit to 1 It becomes communication ready state (SEm0 = 1) under normal operation The mode switches from SNOOZE to normal operation. End of SNOOZE mode Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-72. Timing Chart of SNOOZE Mode Operation (once startup). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; p = 00 m = 0, 1; p = 00, 20 623 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 12-74. Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation status STOP mode Normal peration <3> SS00 SNOOZ mode Normal peration <4> <3> ST00 <1> STOP mode SNOOZ mode <4> <9> SE00 SWC0 SSEC0 <10> L Clock request signal (internal signal) Receive data 2 SDR00 Receive data 1 <8> Read Note 2 SCK00 pin SI00 pin Shift register 00 INTCSI00 Receive data 1 Receive data 2 Reception & shift operation Reception & shift operation Note 2 Data reception (8-bit length) Data reception (8-bit length) TSF00 <2> Notes 1. 2. <5><6> <7> <2> <5><6> Only read received data while SWCm = 1 and before the next edge of the SCKp pin input is detected. The transfer end interrupt (INTCSIp) is cleared either when SWCm is cleared to 0 or when the next edge of the SCKp pin input is detected. <R> Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm0 bit to 1 (clear the SEm0 bit, and stop the operation). And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE release). Remarks 1. <1> to <10> in the figure correspond to <1> to <10> in Figure 12-75. Flowchart of SNOOZE Mode Operation (continuous startup). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; p = 00 m = 0, 1; p = 00, 20 624 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-75. Flowchart of SNOOZE Mode Operation (continuous startup) SNOOZE mode operatopn No TSFmn = 0 for all channels? Normal operation Yes <1> Become the operation STOP status (SEm0 = 0) Write STm0 bit to 1 SMRm0, SCRm0 : SAU default setting Communication setting SDRm0[15:9] : <2> <3> Setting SSCm register (SWCm = 1, SSECm = 0) Write SSm0 bit to 1 Enables interrupt STOP mode <4> Entered the STOP mode Setting 0000000B Setting SNOOZE mode Become the communication wait status (SEm0 = 1) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). fCLK supplied to the SAU is stopped. SCKp edge detected (Entered the SNOOZE mode) <5> SNOOZE mode Supplying a clock to CSIp (CSIp is receive operation) <6> Transfer interrupt (INTCSIp) is generated (CSIp is receive completion) <7> Normal operation <8> Reading receive data to SIOp (=SDRmn[7:0]) <9> Write STm0 bit to 1 <10> Clear SWCm bit to 0 The mode switches from SNOOZE to normal operation. Reset SNOOZE mode setting Remarks 1. <1> to <10> in the figure correspond to <1> to <10> in Figure 12-74. Timing Chart of SNOOZE Mode Operation (continuous startup). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; p = 00 m = 0, 1; p = 00, 20 625 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} / (SDRmn[15:9] + 1) / 2 [Hz] (2) Slave (Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master} Note [Hz] Note The permissible maximum transfer clock frequency is fMCK/6. Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to 1111111B) and therefore is 0 to 127. The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 626 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Table 12-2. Selection of Operation Clock For 3-Wire Serial I/O SMRmn Register SPSm Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 <R> Operation Clock (fMCK) Note fCLK = 32 MHz X X X X 0 0 0 0 fCLK 32 MHz X X X X 0 0 0 1 fCLK/2 16 MHz X X X X 0 0 1 0 fCLK/2 2 8 MHz X X X X 0 0 1 1 fCLK/2 3 4 MHz 2 MHz X X X X 0 1 0 0 fCLK/2 4 X X X X 0 1 0 1 fCLK/2 5 1 MHz 500 kHz X X X X 0 1 1 0 fCLK/2 6 X X X X 0 1 1 1 fCLK/2 7 250 kHz 125 kHz X X X X 1 0 0 0 fCLK/2 8 X X X X 1 0 0 1 fCLK/2 9 62.5 kHz X X X X 1 0 1 0 fCLK/2 10 31.25 kHz X X X X 1 0 1 1 fCLK/2 11 15.63 kHz X X X X 1 1 0 0 fCLK/2 12 7.81 kHz 3.91 kHz <R> X X X X 1 1 0 1 fCLK/2 13 <R> <R> X X X X 1 1 1 0 fCLK/2 14 1.95 kHz 15 977 Hz 1 X X X X 1 1 1 1 fCLK/2 0 0 0 0 X X X X fCLK 0 0 0 1 X X X X fCLK/2 0 0 1 0 X X X X fCLK/2 2 8 MHz 0 0 1 1 X X X X fCLK/2 3 4 MHz 2 MHz 32 MHz 16 MHz 0 1 0 0 X X X X fCLK/2 4 0 1 0 1 X X X X fCLK/2 5 1 MHz 500 kHz 0 1 1 0 X X X X fCLK/2 6 0 1 1 1 X X X X fCLK/2 7 250 kHz 125 kHz 1 0 0 0 X X X X fCLK/2 8 1 0 0 1 X X X X fCLK/2 9 62.5 kHz 31.25 kHz 1 0 1 0 X X X X fCLK/2 10 1 0 1 1 X X X X fCLK/2 11 15.63 kHz <R> <R> 1 1 0 0 X X X X fCLK/2 12 7.81 kHz 1 1 0 1 X X X X fCLK/2 13 3.91 kHz <R> 1 1 1 0 X X X X fCLK/2 14 1.95 kHz fCLK/2 15 977 Hz 1 <R> 1 1 1 X Other than above Note X X X Setting prohibited When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU). Remarks 1. X: Don't care 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 627 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) communication is described in Figure 12-76. Figure 12-76. Processing Procedure in Case of Overrun Error Software Manipulation Reads serial data register mn (SDRmn). Hardware Status Remark The BFFmn bit of the SSRmn register is This is to prevent an overrun error if the set to 0 and channel n is enabled to receive data. next reception is completed during error processing. Reads serial status register mn Error type is identified and the read (SSRmn). value is used to clear error flag. Writes 1 to serial flag clear trigger register mn (SIRmn). Error flag is cleared. Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 628 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6 Operation of UART (UART0 to UART3) Communication This is a start-stop synchronization function using two lines: serial/data transmission (TXD) and serial/data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party. Full-duplex asynchronous communication UART communication can be performed by using a channel dedicated to transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered channel). The LIN-bus can be implemented by using UART2 with an external interrupt (INTP0). [Data transmission/reception] * Data length of 7, 8, or 9 bits Note * Select the MSB/LSB first * Level setting of transmit/receive data (selecting whether to reverse the level) * Parity bit appending and parity check functions * Stop bit appending, stop bit check function [Interrupt function] * Transfer end interrupt/buffer empty interrupt * Error interrupt in case of framing error, parity error, or overrun error [Error detection flag] * Framing error, parity error, or overrun error In addition, UART0 reception (channel 1 of unit 0) supports the SNOOZE mode. When RxD0 pin input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only following UARTs can be specified for the reception baud rate adjustment function. * 24 to 64-pin products: UART0 * 80 to 128-pin products: UART0 and UART2 The LIN-bus is accepted in UART2 (channels 0 and 1 of unit 1) (30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products only). [LIN-bus functions] * Wakeup signal detection Using the external interrupt (INTP0) and * Break field (BF) detection timer array unit 0 * Sync field measurement, baud rate calculation Note Only following UARTs can be specified for the 9-bit data length. * 24 to 64-pin products: UART0 * 80 to 128-pin products: UART0 and UART2 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 629 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0. UART1 uses channels 2 and 3 of SAU0. UART2 uses channels 0 and 1 of SAU1. UART3 uses channels 2 and 3 of SAU1. * 20, 24, and 25-pin products 0 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 Unit Channel - UART1 - IIC11 * 30, 32-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 UART2 (supporting LIN- IIC20 1 - bus) - Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 UART2 (supporting LIN- IIC20 CSI21 bus) IIC21 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 2 - 3 CSI11 Unit Channel - UART1 - IIC11 * 36, 40, 44-pin products Unit 0 1 Channel 1 2 - UART1 - IIC11 * 48, 52-pin products Unit 0 1 Channel 2 IIC01 UART1 - IIC11 0 CSI20 UART2 (supporting LIN- IIC20 1 CSI21 bus) IIC21 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 630 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT * 64-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 Unit Channel IIC01 UART1 2 CSI10 3 CSI11 0 CSI20 UART2 (supporting LIN- IIC20 CSI21 bus) IIC21 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 2 CSI10 3 CSI11 0 CSI20 1 IIC10 IIC11 * 80, 100, 128-pin products Unit 0 1 Channel 2 IIC01 UART1 IIC10 IIC11 UART2 (supporting LIN- IIC20 bus) <R> 1 CSI21 2 CSI30 3 CSI31 IIC21 UART3 IIC30 IIC31 Select any function for each channel. Only the selected function is possible. If UART0 is selected for channels 0 and 1 of unit 0, for example, these channels cannot be used for CSI00 and CSI01. At this time, however, channel 2, 3, or other channels of the same unit can be used for a function other than UART0, such as CSI10, UART1, and IIC10. Caution When using a serial array unit for UART, both the transmitter side (even-numbered channel) and the receiver side (odd-numbered channel) can only be used for UART. UART performs the following four types of communication operations. * UART transmission (See 12.6.1.) * UART reception (See 12.6.2.) * LIN transmission (UART2 only) (See 12.7.1.) * LIN reception (UART2 only) (See 12.7.2.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 631 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.1 UART transmission UART transmission is an operation to transmit data from the RL78/G13 to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission. UART UART0 UART1 UART2 UART3 Target channel Channel 0 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1 Channel 2 of SAU1 Pins used TxD0 TxD1 TxD2 TxD3 Interrupt INTST0 INTST1 INTST2 INTST3 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. <R> Error detection flag None Transfer data length 7, 8, or 9 bits Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 x 2 x 128) [bps] Data phase Non-reverse output (default: high level) Reverse output (default: low level) Parity bit Note 1 15 Note 2 The following selectable * No parity bit * Appending 0 parity * Appending even parity * Appending odd parity Stop bit The following selectable * Appending 1 bit * Appending 2 bits Data direction MSB or LSB first Notes 1. Only following UARTs can be specified for the 9-bit data length. * 24 to 64-pin products: UART0 * 80 to 128-pin products: UART0 and UART2 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remarks 1. fMCK: Operation clock frequency of target channel fCLK: System clock frequency 2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 632 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-77. Example of Contents of Registers for UART Transmission of UART (UART0 to UART3) (1/2) <R> (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 1 0 0 CKSmn CCSmn 0/1 0 2 1 0 MDmn2 MDmn1 MDmn0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 1 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0/1 0/1 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0/1 0/1 1 0 DLSmn1 DLSmn0 0/1 0/1 Note Setting of stop bit 01B: Appending 1 bit 10B: Appending 2 bits Setting of parity bit 00B: No parity 01B: Appending 0 parity 10B: Appending Even parity 11B: Appending Odd parity Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. (c) Serial data register mn (SDRmn) (lower 8 bits: TXDq) 15 14 SDRmn 13 12 11 10 9 Baud rate setting 8 7 6 5 4 3 2 1 0 1 0 Transmit data setting 0 Note TXDq (d) Serial output level register m (SOLm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 0 0 0 0 0 SOLm 2 SOLm2 0/1 SOLm0 0 0/1 0: Non-reverse (normal) transmission 1: Reverse transmission Notes 1. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128-pin product. This bit is fixed to 1 for the other registers. 2. When UART0 performs 9-bit communication (by setting the DLS001 and DLS000 bits of the SCR00 register to 1), bits 0 to 8 of the SDR00 register are used as the transmission data specification area. Only following UARTs can be specified for the 9-bit data length. * 24 to 64-pin products: UART0 * 80 to 128-pin products: UART0 and UART2 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3), mn = 00, 02, 10, 12 2. : Setting is fixed in the UART transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 633 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-77. Example of Contents of Registers for UART Transmission of UART (UART0 to UART3) (2/2) (e) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 x x x x 3 2 1 0 Som3 SOm2 SOm1 SOm0 x 0/1Note x 0/1Note 0: Serial data output value is "0" 1: Serial data output value is "1" (f) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 x 0/1 x 0/1 (g) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm Note 3 2 1 0 SSm3 SSm2 SSm1 SSm0 x 0/1 x 0/1 Before transmission is started, be sure to set to 1 when the SOLmn bit of the target channel is set to 0, and set to 0 when the SOLmn bit of the target channel is set to 1. The value varies depending on the communication data during communication operation. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3) mn = 00, 02, 10, 12 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 634 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-78. Initial Setting Procedure for UART Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Changing setting of the SOLm register Setting the SOm register Set an output data level. Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output of the target channel Setting port by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 Writing to the SSm register and set the SEmn bit to 1 (to enable operation). Initial setting is completed. Completing initial setting Set transmit data to the TXDq register (bits 7 to 0 of the SDRmn register) and start communication. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 635 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-79. Procedure for Stopping UART Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 636 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-80. Procedure for Resuming UART Transmission Starting setting for resumption Completing master preparations? (Essential) Yes (Selective) Port manipulation No Wait until stop the communication target or communication operation completed Disable data output of the target channel by setting a port register and a port mode register. Re-set the register to change the (Selective) Changing setting of the SPSm register operation clock setting. Re-set the register to change the (Selective) Changing setting of the SDRmn register transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register (Selective) Changing setting of the SCRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change the serial communication operation setting register mn (SCRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SOLm register (Selective) Changing setting of the SOEm register output level register m (SOLm) setting. Clear the SOEmn bit to 0 and stop output. (Selective) Changing setting of the SOm register Set the initial output level of the serial data (SOmn). (Essential) Changing setting of the SOEm register (Essential) Port manipulation Set the SOEmn bit to 1 and enable output. Enable data output of the target channel by setting a port register and a port mode register. (Essential) Writing to the SSm register Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Setting is completed Completing resumption setting Sets transmit data to the TXDq register (bits 7 to 0 of the SDRmn register) and start communication. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 637 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-81. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn TxDq pin Shift register mn Transmit data 1 ST Transmit data 1 Transmit data 2 P SP Shift operation ST Transmit data 2 Shift operation Transmit data 3 P SP ST Transmit data 3 P SP Shift operation INTSTq Data transmission (8-bit length) Data transmission (8-bit length) Data transmission (8-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3) mn = 00, 02, 10, 12 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 638 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-82. Flowchart of UART Transmission (in Single-Transmission Mode) <R> Starting UART communication SAU default setting For the initial setting, refer to Figure 12-78. (Select transfer end interrupt) Main routine Set data for transmission and the number of data. Setting transmit data Clear communication end flag (Storage area, transmission data pointer, number of communication data and communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Writing transmit data to TxDq (=SDRmn[7:0]) Read transmit data from storage area and write it to TxDq. Update transmit data pointer. Communication starts by writing to SDR4n[7:0] Wait for transmit completes When Transfer end interrupt is generated, it moves to interrupt processing routine Interrupt processing routine Transfer end interrupt No Transmitting next data? Yes Writing transmit data to TxDq (=SDRmn[7:0]) Read transmit data, if any, from storage area and write it to TxDq. Update transmit data pointer. If not, set transmit end flag Sets communication completion flag RETI Check completion of transmission by No Transmission completed? verifying transmit end flag Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 639 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-83. Timing Chart of UART Transmission (in Continuous Transmission Mode) SSmn <1> <6> STmn SEmn SDRmn Transmit data 1 TxDq pin ST Shift register mn Transmit data 1 Transmit data 2 P SP ST Transmit data 3 Transmit data 2 P SP ST Shift operation Shift operation Transmit data 3 P SP Shift operation INTSTq Data transmission (7-bit length) Data transmission (7-bit length) Data transmission (7-bit length) MDmn0 <4> TSFmn BFFmn <2><3> Note <2> <3> <2> <3> <5> Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. Caution The MDmn0 bit of serial mode register mn (SSRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), q: UART number (q = 0 to 3) mn = 00, 02, 10, 12 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 640 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-84. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication <1> SAU default setting For the initial setting, refer to Figure 12-78. (Select buffer empty interrupt) Set data for transmission and the number of data. Setting transmit data Clear communication end flag (Storage area, Transmission data pointer, Number of communication data and Main routine Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). <2> Writing transmit data to TXDqp (=SDRmn[7:0]) Read transmit data from storage area and write it to TXDq. Update transmit data pointer. Communication starts by writing to SDRmn [7:0] Wait for transmit completes When transfer end interrupt is generated, it moves to interrupt processing routine. <3> Buffer empty/transfer end interrupt Interrupt processing routine If transmit data is left, read them from storage area then write into SIOp, and update transmit data pointer and No Number of communication data > 0? number of transmit data. If no more transmit data, clear MDmn bit if it's set. If not, finish. Yes <2> Writing transmit data to No MDmn = 1? SIOp (=SDRmn[7:0]) Yes <5> <4> Subtract -1 from number of transmit data Sets communication Clear MDmn0 bit to 0 completion interrupt flag RETI No Check completion of transmission by Transmission completed? verifying transmit end flag Main routine Yes Write MDmn0 bit to 1 Disable interrupt (MASK) Yes Communication continued? No <6> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 12-83 Timing Chart of UART Transmission (in Continuous Transmission Mode). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 641 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 UART reception UART reception is an operation wherein the RL78/G13 asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set. UART UART0 UART1 UART2 UART3 Target channel Channel 1 of SAU0 Channel 3 of SAU0 Channel 1 of SAU1 Channel 3 of SAU1 Pins used RxD0 RxD1 RxD2 RxD3 Interrupt INTSR0 INTSR1 INTSR2 INTSR3 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error interrupt INTSRE0 INTSRE1 Error detection flag * Framing error detection flag (FEFmn) INTSRE2 INTSRE3 * Parity error detection flag (PEFmn) * Overrun error detection flag (OVFmn) <R> Note 1 Transfer data length 7, 8 or 9 bits Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 x 2 x 128) [bps] Data phase 15 Note 2 Non-reverse output (default: high level) Reverse output (default: low level) Parity bit The following selectable * No parity bit (no parity check) * No parity judgment (0 parity) * Even parity check * Odd parity check Stop bit 1 bit check Data direction MSB or LSB first Notes 1. Only following UARTs can be specified for the 8-bit data length. * 24 to 64-pin products: UART0 only * 80 to 128-pin products: UART0 and UART2 only 2. Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remarks 1. fMCK: Operation clock frequency of target channel fCLK: System clock frequency 2. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 642 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting <R> Figure 12-85. Example of Contents of Registers for UART Reception of UART (UART0 to UART3) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 1 6 5 4 3 1 0 0 SISmn0 0 2 1 0 MDmn2 MDmn1 MDmn0 0/1 0: Normal reception 1: Reverse reception 0 1 0 Operation mode of channel n 0: Transfer end interrupt (b) Serial mode register mr (SMRmr) 15 SMRmr 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 1 0 0 CKSmr CCSmr 0/1 0 2 1 0 MDmr2 MDmr1 MDmr0 Same setting value as CKSmn bit 0 1 0/1 Operation mode of channel r 0: Transfer end interrupt 1: Buffer empty interrupt (c) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 0 1 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0/1 0/1 0/1 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 1 1 0 DLSmn1 DLSmn0 0/1 0/1 Note 1 Setting of parity bit Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. 00B: No parity check 01B: No parity judgment 10B: Even parity check 11B: Odd parity check Setting of data length (d) Serial data register mn (SDRmn) (lower 8 bits: RXDq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting Receive data register 0 Note 2 RXDq Notes 1. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128-pin product. This bit is fixed to 1 for the other registers. 2. When UART performs 9-bit communication, bits 0 to 8 of the SDRm1 register are used as the transmission data specification area. Only following UARTs can be specified for the 8-bit data length. Caution * 24 to 64-pin products: UART0 * 80 to 128-pin products: UART0 and UART2 For the UART reception, be sure to set the SMRmr register of channel r to UART transmission mode that is to be paired with channel n. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13 r: Channel number (r = n - 1), q: UART number (q = 0 to 3) 2. : Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 643 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-85. Example of Contents of Registers for UART Reception of UART (UART0 to UART3) (2/2) (e) Serial output register m (SOm) ... The register that not used in this mode. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 x x x x 3 2 1 0 SOm3 SOm2 SOm1 SOm0 x x x x 1 0 (f) Serial output enable register m (SOEm) ...The register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 SOEm3 SOEm2 SOEm1 SOEm0 x x x x (g) Serial channel start register m (SSm) ... Sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm Caution 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 x 0/1 x For the UART reception, be sure to set the SMRmr register of channel r to UART Transmission mode that is to be paired with channel n. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13 r: Channel number (r = n - 1), q: UART number (q = 0 to 3) 2. : Setting is fixed in the UART reception mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 644 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-86. Initial Setting Procedure for UART Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Set an operation mode, etc. Setting the SMRmn and SMRmr registers Set a communication format. Setting the SCRmn register Setting the SDRmn register Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)). Setting port Enable data input of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Become wait for start bit detection. Writing to the SSm register Completing initial setting <R> Caution Set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after 4 or more fMCK clocks have elapsed. Figure 12-87. Procedure for Stopping UART Reception <R> Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Selective) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 to operation stop status) Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 645 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-88. Procedure for Resuming UART Reception Starting setting for resumption Completing master preparations? (Essential) No Stop the target for communication or wait until completes its communication operation. Yes (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting. (Selective) Changing setting of the SDRmn Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). Changing setting of the SMRmn (Selective) <R> and SMRmr registers (Selective) Changing setting of the SCRmn register (Selective) Clearing error flag (Essential) Setting port (Essential) Writing to the SSm register (Essential) Completing resumption setting Caution Re-set the registers to change serial mode registers mn, mr (SMRmn, SMRmr) setting. Re-set the register to change serial communication operation setting register mn (SCRmn) setting. If the FEF, PEF, and OVF flags remain set, clear them using serial flag clear trigger register mn (SIRmn). Enable data input of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Become wait for start bit detection. After is set RXEmn bit to 1 of SCRmn register, set the SSmn = 1 from an interval of at least four clocks of fMCK. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (slave) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 646 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-89. Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn RxDq pin Shift register mn INTSRq Receive data 1 ST Receive data 1 Shift operation Data reception (7-bit length) P SP ST Receive data 2 Receive data 2 P SP Shift operation Data reception (7-bit length) ST Receive data 3 P SP Shift operation Data reception (7-bit length) TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13 r: Channel number (r = n - 1), q: UART number (q = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 647 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-90. Flowchart of UART Reception <R> Starting UART communication SAU default setting Setting receive data Enables interrupt For the initial setting, refer to Figure 12-86. (setting to mask for error interrupt) Setting storage area of the receive data, number of communication data (storage area, reception data pointer, number of communication data and communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set Wait for receive completes Starting reception if start bit is detected When receive complete, transfer end interrupt is generated, Transfer end interrupt Reading receive data to RXDq (=SDRmn[7:0]) Read receive data then writes to storage area. Update receive data pointer and number of communication data. Indicating normal reception? No Yes RETI Error processing No Reception completed? Yes Check the number of communication data, determine the completion of reception Writing 1 to the STmn bit Clearing the SAUmEN bit of the PER0 register to 0 End of UAR T R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 648 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.3 SNOOZE mode function <R> SNOOZE mode makes UART operate reception by RxDq pin input detection while the STOP mode. Normally UART stops communication in the STOP mode. But, using the SNOOZE mode makes reception UART operate unless the CPU operation by detecting RxDq pin input. Only following channels can be set to the SNOOZE mode. * 24 to 64-pin products: UART0 * 80 to 128-pin products: UART0 and UART2 When using the SNOOZE mode function, set the SWCm bit of serial standby control register m (SSCm) to 1 just before switching to the STOP mode. Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for fCLK. <R> 2. The maximum transfer rate when using UARTq in the SNOOZE mode is 9600 bps. (1) SNOOZE mode operation (Normal operation) Figure 12-91. Timing Chart of SNOOZE Mode Operation (Normal operation mode) CPU operation status Normal peration <3> SS01 Normal peration SNOOZ mode STOP mode <4> <12> <10> ST01 <1> SE01 SWC0 SSEC0 <11> L Clock request signal (internal signal) Receive data 2 SDR01 Receive data 1 <9> RxD0 pin ST Shift register 01 Receive data 1 P Read SP ST Receive data 2 P SP Shift operation Shift operation INTSR0 Data reception (7-bit length) <7> INTSRE0 L Data reception (7-bit length) TSF01 <2> <R> Note <R> Caution <5><6> <8> Read the received data when SWCm is 1 Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm1 bit to 1 (clear the SEm1 bit, and stop the operation). And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release). Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; q = 0 m = 0, 1; q = 0, 2 649 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (Abnormal Operation <1>) Abnormal operation <1> is the operation performed when a communication error occurs while SSECm = 0. Because SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs. Figure 12-92. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <1>) CPU operation status Normal peration <3> SS01 STOP mode Normal peration SNOOZ mode <4> <12> ST01 <1> <10> SE01 SWC0 SSEC0 <11> L Clock request signal (internal signal) SDR01 Receive data 2 Receive data 1 RxD0 pin ST Shift register 01 Receive data 1 P SP ST Receive data 2 Shift operation P SP Shift operation INTSR0 Data reception (7-bit length) <7> INTSRE0 L Data reception (7-bit length) TSF01 <2> <R> Caution <5> <6> <8> Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm1 bit to 1 (clear the SEm1 bit, and stop the operation). And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release). Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; q = 0 m = 0, 1; q = 0, 2 650 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>) <R> Setting start No Does TSFmn = 0 on all channels? Yes <1> Writing 1 to the STmn bit SEmn = 0 Normal operation SAU default setting <2> Setting SSCm register The operation of all channels is also stopped to switch to the STOP mode. Channel 1 is specified for UART reception. (EOCmn: set to enable error interrupt) SNOOZE mode setting (SWCm = 1, SSECm = 0) <3> Writing 1 to the SSmn bit SEmn = 1 Communication wait status Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI = 1). Enable interrupt <4> STOP mode Entered the STOP mode fCLK supplied to the SAU is stopped. SNOOZE mode <5> RxDq edge detected (Entered the SNOOZE mode) <6> Clock supply (UART receive operation) <7> Transfer end interrupt (INTSRq) or error interrupt (INTSREq) generated? <8> INTSREq Reading receive data to INTSRq <9> Reading receive data to RxDq (=SDRm1[7:0]) RxDq (=SDRm1[7:0]) Normal operation Writing 1 to the STm1 bit <10> Writing 1 to the STmn bit Clear SWCm bit to 0 <11> Clear SWCm bit to 0 Writing 1 to the SSmn bit Writing 1 to the SSmn bit Error processing The mode switches from SNOOZE to normal operation. To operation stop status (SEm1 = 0) Reset SNOOZE mode setting To communication wait status (SEmn = 1) Normal processing Remarks 1. <1> to <11> in the figure correspond to <1> to <11> in Figure 12-91. Timing Chart of SNOOZE Mode Operation (Normal operation mode) and Figure 12-92. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <1>). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; q = 0 m = 0, 1; q = 0, 2 651 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) SNOOZE mode operation (Abnormal Operation <2>) Abnormal operation <2> is the operation performed when a communication error occurs while SSECm = 1. Because SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error occurs. Figure 12-94. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <2>) Normal peration CPU operation status Normal peration <3> SS01 SNOOZ mode STOP mode <4> SNOOZ mode STOP mode <10> ST01 <1> SE01 SWC0 SSEC0 Shift operation Clock request signal (internal signal) Receive data 2 SDR01 Receive data 1 Read RxD0 pin Receive data 1 ST Shift register mn P SP Receive data 2 ST <9> P SP Shift operation Shift operation Data reception (7-bit length) Data reception (7-bit length) INTSR0 INTSRE0 L Note2 TSF01 <2> <R> Notes 1. 2. <5> <6> <7> <5> <6> <7>, <11> <8> Only read received data while SWCm = 1. After UARTq successfully finishes reception in the SNOOZE mode, it is possible to continue to perform normal reception operations without changing the settings, but, because SSECm = 1, the PEFm1 and FEFm1 bits are not set even if a framing error or parity error occurs. In addition, no error interrupt (INTSREq) is generated. <R> Cautions 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the STm1 bit to 1 (clear the SEm1 bit, and stop the operation). And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release). 2. When using the SNOOZE mode while SSECm is set to 1, no overrun errors occur. Therefore, when using the SNOOZE mode, read bits 7 to 0 (RxDq) of the SDRm1 register before switching to the STOP mode. Remarks 1. <1> to <9> in the figure correspond to <1> to <9> in Figure 12-95. Flowchart of SNOOZE Mode Operation (Abnormal Operation <2>). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; q = 0 m = 0, 1; q = 0, 2 652 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-95. Flowchart of SNOOZE Mode Operation (Abnormal Operation <2>) Setting start Does TSFmn = 0 on all channels? No Yes SIRm1 = 0007H <1> Writing 1 to the STmn bit Normal operation SEmn = 0 SAU default setting <2> Setting SSCm register Clear the all error flags The operation of all channels is also stopped to switch to the STOP mode. Channel 1 is specified for UART reception. (EOCmn: set to enable error interrupt) SNOOZE mode setting (error interrupt generation stop) (SWCm = 1, SSECm = 1) <3> Writing 1 to the SSmn bit SEmn = 1 Setting interrupt <4> Entered the STOP mode Communication wait status Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt disable (EI = 0). fCLK supplied to the SAU is stopped. STOP mode <5> SNOOZE mode STOP mode RxDq edge detected (Entered the SNOOZE mode) <6> Clock supply (UART receive operation) <7> Reception error detected If an error occurs, because the CPU switches to the STOP status again, the error flag is not set. SNOOZE mode RxDq edge detected (Entered the SNOOZE mode) Clock supply (UART receive operation) <7> Transfer end interrupt (INTSRq) generated <8> <9> Normal operation Reading receive data to The mode switches from SNOOZE to normal operation. RxDq (=SDRm1[7:0]) Writing 1 to the STm1 bit Setting SSCm register To operation stop status (SEm1 = 0) Reset SNOOZE mode setting (SWCm = 0, SSECm = 0) Nomarl processing (Caution and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 653 RL78/G13 Caution CHAPTER 12 SERIAL ARRAY UNIT When using the SNOOZE mode while SSECm is set to 1, no overrun errors occur. Therefore, when using the SNOOZE mode, read bits 7 to 0 (RxDq) of the SDRm1 register before switching to the STOP mode. Remarks 1. <1> to <9> in the figure correspond to <1> to <9> in Figure 12-94. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <2>). 2. 24 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 m = 0; q = 0 m = 0, 1; q = 0, 2 654 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0 to UART3) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (fMCK) frequency of target channel} / (SDRmn[15:9] + 1) / 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited. Remarks 1. When UART is used, the value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000010B to 1111111B) and therefore is 2 to 127. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 655 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Table 12-3. Selection of Operation Clock For UART SMRmn Register SPSm Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 <R> <R> <R> <R> 1 <R> <R> <R> <R> Note fCLK = 32 MHz X X X X 0 0 0 0 fCLK 32 MHz X X X X 0 0 0 1 fCLK/2 16 MHz X X X X 0 0 1 0 fCLK/2 2 8 MHz X X X X 0 0 1 1 fCLK/2 3 4 MHz 2 MHz X X X X 0 1 0 0 fCLK/2 4 X X X X 0 1 0 1 fCLK/2 5 1 MHz 500 kHz X X X X 0 1 1 0 fCLK/2 6 X X X X 0 1 1 1 fCLK/2 7 250 kHz 125 kHz X X X X 1 0 0 0 fCLK/2 8 X X X X 1 0 0 1 fCLK/2 9 62.5 kHz X X X X 1 0 1 0 fCLK/2 10 31.25 kHz X X X X 1 0 1 1 fCLK/2 11 15.63 kHz X X X X 1 1 0 0 fCLK/2 12 7.81 kHz 3.91 kHz X X X X 1 1 0 1 fCLK/2 13 X X X X 1 1 1 0 fCLK/2 14 1.95 kHz 15 977 Hz X X X X 1 1 1 1 fCLK/2 0 0 0 0 X X X X fCLK 0 0 0 1 X X X X fCLK/2 0 0 1 0 X X X X fCLK/2 2 8 MHz 0 0 1 1 X X X X fCLK/2 3 4 MHz 2 MHz 32 MHz 16 MHz 0 1 0 0 X X X X fCLK/2 4 0 1 0 1 X X X X fCLK/2 5 1 MHz 500 kHz 0 1 1 0 X X X X fCLK/2 6 0 1 1 1 X X X X fCLK/2 7 250 kHz 125 kHz 1 0 0 0 X X X X fCLK/2 8 1 0 0 1 X X X X fCLK/2 9 62.5 kHz 31.25 kHz 1 0 1 0 X X X X fCLK/2 10 1 0 1 1 X X X X fCLK/2 11 15.63 kHz 1 1 0 0 X X X X fCLK/2 12 7.81 kHz 3.91 kHz 1 1 0 1 X X X X fCLK/2 13 1 1 1 0 X X X X fCLK/2 14 1.95 kHz fCLK/2 15 977 Hz 1 1 1 1 X Other than above Note Operation Clock (fMCK) X X X Setting prohibited When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU). Remarks 1. X: Don't care 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 656 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0 to UART3) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. (Baud rate error) = (Calculated baud rate value) / (Target baud rate) x 100 - 100 [%] Here is an example of setting a UART baud rate at fCLK = 32 MHz. UART Baud Rate (Target Baud Rate) fCLK = 32 MHz Operation Clock (fMCK) Calculated Baud Rate Error from Target Baud Rate 103 300.48 bps +0.16 % 103 600.96 bps +0.16 % 103 1201.92 bps +0.16 % 103 2403.85 bps +0.16 % 5 103 4807.69 bps +0.16 % fCLK/2 4 103 9615.38 bps +0.16 % fCLK/2 3 103 19230.8 bps +0.16 % fCLK/2 3 63 31250.0 bps 0.0 % 38400 bps fCLK/2 2 103 38461.5 bps +0.16 % 76800 bps fCLK/2 103 76923.1 bps +0.16 % 153600 bps fCLK 103 153846 bps +0.16 % 312500 bps fCLK 50 312500 bps 0.39 % fCLK/2 9 fCLK/2 8 fCLK/2 7 2400 bps fCLK/2 6 4800 bps fCLK/2 300 bps 600 bps 1200 bps 9600 bps 19200 bps 31250 bps Remark SDRmn[15:9] m: Unit number (m = 0, 1), n: Channel number (n = 0, 2), mn = 00, 02, 10, 12 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 657 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0 to UART3) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. 2 x k x Nfr (Maximum receivable baud rate) = x Brate 2 x k x Nfr - k + 2 2 x k x (Nfr - 1) (Minimum receivable baud rate) = x Brate 2 x k x Nfr - k - 2 Brate: Calculated baud rate value at the reception side (See 12.6.4 (1) Baud rate calculation expression.) k: SDRmn[15:9] + 1 Nfr: 1 data frame length [bits] = (Start bit) + (Data length) + (Parity bit) + (Stop bit) Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11, 13 Figure 12-96. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits) Latch timing Data frame length of SAU Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Permissible minimum data frame length Start bit Bit 0 Bit 1 Parity bit Bit 7 Stop bit (11 x FL) min. Permissible maximum data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit (11 x FL) max. As shown in Figure 12-96, the timing of latching receive data is determined by the division ratio set by bits 15 to 9 of serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this latch timing, the data can be correctly received. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 658 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.6.5 Procedure for processing errors that occurred during UART (UART0 to UART3) communication The procedure for processing errors that occurred during UART (UART0 to UART3) communication is described in Figures 12-97 and 12-98. Figure 12-97. Processing Procedure in Case of Parity Error or Overrun Error Software Manipulation Hardware Status Remark Reads serial data register mn The BFFmn bit of the SSRmn register This is to prevent an overrun error if the (SDRmn). is set to 0 and channel n is enabled to receive data. next reception is completed during error processing. Reads serial status register mn (SSRmn). Writes 1 to serial flag clear trigger register mn (SIRmn). Error type is identified and the read value is used to clear error flag. Error flag is cleared. Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Figure 12-98. Processing Procedure in Case of Framing Error Software Manipulation Hardware Status Remark Reads serial data register mn The BFFmn bit of the SSRmn register This is to prevent an overrun error if the (SDRmn). is set to 0 and channel n is enabled to receive data. next reception is completed during error processing. Reads serial status register mn Error type is identified and the read (SSRmn). value is used to clear error flag. Writes serial flag clear trigger register mn Error flag is cleared. (SIRmn). Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Sets the STmn bit of serial channel stop The SEmn bit of serial channel enable register m (STm) to 1. status register m (SEm) is set to 0 and channel n stops operating. Synchronization with other party of Synchronization with the other party of communication communication is re-established and communication is resumed because it is considered that a framing error has occurred because the start bit has been shifted. Sets the SSmn bit of serial channel start The SEmn bit of serial channel enable register m (SSm) to 1. status register m (SEm) is set to 1 and channel n is enabled to operate. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 659 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.7 LIN Communication Operation 12.7.1 LIN transmission Of UART transmission, UART2 of the 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products support LIN communication. For LIN transmission, channel 0 of unit 1 is used. UART Support of LIN communication UART0 UART1 Not supported Not supported UART2 Supported UART3 Not supported Target channel - - Channel 0 of SAU1 - Pins used - - TxD2 - Interrupt - - INTST2 - Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. <R> Error detection flag None Transfer data length 8 bits Transfer rate Max. fMCK/6 [bps] (SDR10 [15:9] = 2 or more), Min. fCLK/(2 x 2 x 128) [bps] Data phase 15 Note Non-reverse output (default: high level) Reverse output (default: low level) <R> Parity bit No parity bit <R> Stop bit Appending 1 bit <R> Data direction LSB first Note <R> Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). In addition, LIN communication is usually 2.4/9.6/19.2 kbps is often used. Remark fMCK: Operation clock frequency of target channel fCLK: System clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 660 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. Communication of LIN is single-master communication and up to 15 slaves can be connected to one master. The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN. Usually, the master is connected to a network such as CAN (Controller Area Network). A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141. According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave receives this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within 15%, communication can be established. Figure 12-99 outlines a master transmission operation of LIN. <R> Figure 12-99. Master Transmission Operation of LIN Break field Sync field 13-bit BF transmissionNote 2 55H transmission Wakeup signal frame Identification Data field field Data field Checksum field LIN Bus 8 bitsNote 1 Data Data Data Data transmission transmission transmission transmission TXD2 (output) INTST2Note 3 Notes 1. Data of 80H is transmitted. 2. A break field is defined to have a width of 13 bits and output a low level. Where the baud rate for main transfer is N [bps], therefore, the baud rate of the break field is calculated as follows. (Baud rate of break field) = 9/13 x N By transmitting data of 00H at this baud rate, a break field is generated. 3. INTST2 is output upon completion of transmission. Remark The interval between fields is controlled by software. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 661 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-100. Flowchart for LIN Transmission Starting LIN communication Operation of the hardware (Reference) Transmitting wakeup signal frame (80H TxD2) No TSF10 = 0? Yes UART2 stop (1 ST10 bit) Wakeup signal frame generation Transmitting wakeup Note signal frame TxD2 8 bit Waiting for completion of transmission Transmit data Changing baud rate for BF Changing UART2 baud rate (zz SDR [15:9]) UART2 restart (1 SS10 bit) BF transmission 00 TxD2 BF generation No Waiting for completion of BF transmission TSF10 = 0? Yes UART2 stop (1 ST10 bit) Changing UART2 baud rate (xx SDR[15:9]) TxD2 13-bit length Transmit data Return the baud rate UART2 restart (1 SS10 bit) Transmitting sync field 55H TxD2 BFF10 = 0? Yes Transmitting sync field No Waiting for buffer empty TxD2 55H Transmitting ID to checksum Data TxD2 BFF10 = 0? Sync field data generation No Waiting for buffer empty Yes No Waiting for transmission ID to checksum Completing all data transmission? Yes TSF10 = 0? Yes No Waiting for completion of transmission (transmission completed to the LIN bus) End of LIN communication Note When LIN-bus start from sleep status only Remark Default setting of the UART is complete, and the flow from the transmission enable status. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 662 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.7.2 LIN reception Of UART reception, UART2 of the 30, 32, 36, 40, 44, 48, 52, 64, 80, 100, and 128-pin products support LIN communication. For LIN reception, channel 1 of unit 1 is used. UART Support of LIN communication UART0 UART1 Not supported Not supported UART2 Supported UART3 Not supported Target channel - - Channel 1 of SAU1 - Pins used - - RxD2 - Interrupt - - INTSR2 - Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) - Error interrupt - - INTSRE2 Error detection flag * Framing error detection flag (FEF11) * Overrun error detection flag (OVF11) Transfer data length 8 bits Transfer rate Max. fMCK/6 [bps] (SDR11 [15:9] = 2 or more), Min. fCLK/(2 x 2 x 128) [bps] Data phase Non-reverse output (default: high level) Reverse output (default: low level) <R> Parity bit No parity bit (The parity bit is not checked.) <R> Stop bit Check the first bit <R> Data direction LSB first <R> Note 15 Note Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in the electrical specifications (see CHAPTER 29 ELECTRICAL SPECIFICATIONS). Remark fMCK: Operation clock frequency of target channel fCLK: System clock frequency Figure 12-101 outlines a reception operation of LIN. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 663 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-101. Reception Operation of LIN <R> Wakeup signal frame Break field Sync field Identification Data filed field Data filed Checksum field LIN Bus BF reception Message header SF reception ID reception Data reception Message Data reception Data reception <5> <2> RXD2 UART2 STOP Reception stop INTSR2 <1> Edge detection (INTP0) <3> TM07 STOP <4> Pulse width measurement Pulse interval measurement Pulse width measurement INTTM07 Here is the flow of signal processing. <R> <1> The wakeup signal is detected by detecting an interrupt edge (INTP0) on a pin. When the wakeup signal is detected, change TM07 to pulse width measurement upon detection of the wakeup signal to measure the lowlevel width of the BF signal. Then wait for BF signal reception. <2> TM07 starts measuring the low-level width upon detection of the falling edge of the BF signal, and then captures the data upon detection of the rising edge of the BF signal. The captured data is used to judge whether it is the BF signal. <R> <3> When the BF signal has been received normally, change TM07 to pulse interval measurement and measure the interval between the falling edges of the RxD2 signal in the Sync field four times. <4> When BF reception has been correctly completed, start channel 7 of the timer array unit and measure the bit interval (pulse width) of the sync field (see 6.7.4 Operation as input pulse interval measurement). <5> Calculate a baud rate error from the bit interval of sync field (SF). Stop UART2 once and adjust (re-set) the baud rate. <6> The checksum field should be distinguished by software. In addition, processing to initialize UART2 after the checksum field is received and to wait for reception of BF should also be performed by software. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 664 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT <R> Figure 12-102. Flowchart for LIN Reception Status of LIN bus signal and operation of the hardware Starting LIN communication Generate INTP0? No Wakeup signal frame Wait for wakeup frame Note signal RxD2 pin Edge detection Yes The low-level width of RxD2 is measured using TM07 and BF is detected. Starting in low-level width measurement mode for TM07 Generate IN TTM07? INTP0 Break field No Yes No 11 bit lengths or more? If the detected pulse width is 11 bits or more, it is judged as BF. RxD2 pin Channel 7 of TAU0 INTTM07 Pulse width measurement Channel 7 Yes Set up TM07 to measure the interval between the falling edges. Changing TM07 to pulse width measurement Generate INTTM07? No Ignore the first INTTM07 because the first capture value is incorrect. Yes Generate IN TTM07? Sync field No Yes C apture value cumulative Completed 4 times? Measure the intervals between five falling edges of SF, and accumulate the four captured values. RxD2 pin Channel 7 of TAU0 INTTM07 Pulse interval measurement Cumulative four times No Yes Change TM07 to low-level width measurement to detect a Sync break field. Changing TM07 to low-level width measurement Divide the accumulated value by 8 to obtain the bit width. Use this value to determine the setting values of SPS1, SDR10, and SDR11. Calculate the baud rate UART2 default setting L Set up the initial setting of UART2 according to the LIN communication conditions. Starting UART2 reception (1 SS11) Receive the ID, data, and checksum fields (if the ID matches). Data reception Completing all data transmission? No Yes Stop UART2 reception (1 ST11) End of LIN communication Note Required in the sleep status only. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 665 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-103 and figure 12-104 show the configuration of a port that manipulates reception of LIN. The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0). The length of the sync field transmitted from the master can be measured by using the external event capture operation of the timer array unit 0 to calculate a baud-rate error. By controlling switch of port input (ISC0/ISC1), the input source of port input (RxD2) for reception can be input to the external interrupt pin (INTP0) and timer array unit Figure 12-103 Port Configuration for Manipulating Reception of LIN (30, 32, 36, 40-pin) Selector P14/RxD2/SI20/SDA20 RXD2 input Port mode (PM14) Output latch (P14) Selector P137/INTP0 INTP0 input Port input switch control (ISC0) <ISC0> 0: Selects INTP0 (P137) 1: Selects RxD2 (P14) Input controller Channel 7 input of timer array unit Port input switch control (ISC1) <ISC1> 0: Do not use a timer input signal for channel 7. 1: Selects RxD2 (P14) Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (See Figure 12-19.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 666 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-104 Port Configuration for Manipulating Reception of LIN (44, 48, 52, 64-pin) Selector P14/RxD2/SI20/SDA20 RXD2 input Port mode (PM14) Output latch (P14) Selector P137/INTP0 INTP0 input Port input switch control (ISC0) <ISC0> 0: Selects INTP0 (P137) 1: Selects RxD2 (P14) Selector Selector P41/TI07/TO07 Channel 7 input of timer array unit Port mode (PM41) Output latch (P41) Remark Port input switch control (ISC1) <ISC1> 0: Selects TI07 (P41) 1: Selects RxD2 (P14) ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (See Figure 12-19.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 667 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT The peripheral functions used for the LIN communication operation are as follows. <Peripheral functions used> * External interrupt (INTP0); Wakeup signal detection Usage: To detect an edge of the wakeup signal and the start of communication <R> * Channel 7 of timer array unit; Baud rate error detection, break field detection. Usage: To detect the length of the sync field (SF) and divide it by the number of bits in order to detect an error (The interval of the edge input to RxD2 is measured in the capture mode.) Measured the low-level width, determine whether break field (BF). * Channels 0 and 1 (UART2) of serial array unit 1 (SAU1) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 668 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 12.8 Operation of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master. Operate the control registers by software for setting the start and stop conditions while observing the specifications of the I2C bus line [Data transmission/reception] * Master transmission, master reception (only master function with a single master) * ACK output functionNote and ACK detection function * Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) * Gneration of start condition and stop condition for software [Interrupt function] * Transfer end interrupt [Error detection flag] * Parity error (ACK error) * [Functions not supported by simplified I2C] * Slave transmission, slave reception * Multi-master function (arbitration loss detection function) * Wait detection function Note When receiving the last data, ACK will not be output if 0 is written to the SOEmn (SOEm register) bit and serial communication data output is stopped. See the processing flow in 12.8.3 (2) for details. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 669 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 The channel supporting simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) is channels 0 to 3 of SAU0 and channel 0 and 1 of SAU1. * 20, 24, 25-pin products 0 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 Unit Channel - UART1 - IIC11 * 30, 32-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 1 - Unit Channel - UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 - * 36, 40, 44-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 - 2 - 3 CSI11 0 CSI20 1 CSI21 Unit Channel - UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 * 48, 52-pin products 0 1 2 Used as CSI Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 2 - 3 CSI11 0 CSI20 1 CSI21 Unit Channel R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 IIC01 UART1 - IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 670 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT * 64-pin products Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 Channel 0 1 2 Used as CSI Unit 2 CSI10 3 CSI11 0 CSI20 1 CSI21 IIC01 UART1 IIC10 IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 * 80, 100, 128-pin products Used as UART Used as Simplified I C 0 CSI00 UART0 IIC00 1 CSI01 2 CSI10 3 CSI11 0 CSI20 1 CSI21 2 CSI30 3 CSI31 Channel 0 1 2 Used as CSI Unit IIC01 UART1 IIC10 IIC11 UART2 (supporting LIN-bus) IIC20 IIC21 UART3 IIC30 IIC31 2 Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) performs the following four types of communication operations. * Address field transmission (See 12.8.1.) * Data transmission (See 12.8.2.) * Data reception (See 12.8.3.) * Stop condition generation (See 12.8.4.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 671 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.1 Address field transmission Address field transmission is a transmission operation that first executes in I2C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame. 2 Simplified I C Target channel IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31 Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1 Pins used SCL00, Note SDA00 SCL01, Note SDA01 SCL10, Note SDA10 SCL11, Note SDA11 SCL20, Note SDA20 SCL21, Note SDA21 SCL30, Note SDA30 SCL31, Note SDA31 Interrupt INTIIC00 INTIIC01 INTIIC10 INTIIC11 INTIIC20 INTIIC21 INTIIC30 INTIIC31 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) <R> Error detection flag ACK error detection flag (PEFmn) Transfer data length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W control) Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel 2 However, the following condition must be satisfied in each mode of I C. * Max. 1 MHz (fast mode plus) * Max. 400 kHz (fast mode) * Max. 100 kHz (standard mode) Data level Non-reversed output (default: high level) Parity bit No parity bit Stop bit Appending 1 bit (for ACK transmission/reception timing) Data direction MSB first Note 2 To perform communication via simplified I C, set the N-ch open-drain output (VDD tolerance (20 to 52-pin products/ EVDD tolerance (64 to 128-pin products)) mode (POM03, POM11, POM14, POM50, POM53, POM71, POM74, POM143 = 1) for the port output mode registers (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) (see 4.3 Registers Controlling Port Function for details). When IIC00, IIC10, IIC20, IIC30, IIC31 communicating with an external device with a different potential, set the N-ch open-drain output (VDD tolerance (20 to 52-pin products/ EVDD tolerance (64 to 128-pin products)) mode (POM04, POM10, POM15, POM54, POM142 = 1) also for the clock input/output pins (SCL00, SCL10, SCL20, SCL30, SCL31) (see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) for details). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 672 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting <R> 2 Figure 12-105. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 SISmn0 0 2 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 1 0 0 Operation mode of channel n 0: Transfer end interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 0 0 0 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn TXEmn RXEmn DAPmn CKPmn 1 10 0 0 0 0 0 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 1 0 DLSmn1 DLSmn0 1 Setting of parity bit 00B: No parity 1 Note 1 Setting of stop bit 01B: Appending 1 bit (ACK) (c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting Transmit data setting (address + R/W) 0 SIOr (d) Serial output register m (SOm) 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 0/1 0/1 0/1 0/1 3 2 1 0 SOm3 SOm2 SOm1 SOm0 0/1 0/1 0/1 0/1 Start condition is generated by manipulating the SOmn bit. (e) Serial output enable register m (SOEm) 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 0/1 0/1 0/1 0/1 SOEmn = 0 until the start condition is generated, and SOEmn = 1 after generation. Note Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128pin product. This bit is fixed to 1 for the other registers. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 673 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 Figure 12-105. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (2/2) (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 SSmn = 0 until the start condition is generated, and SSmn = 1 after generation. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 674 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-106. Initial Setting Procedure for Simplified I2C <R> Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Setting the SOm register Set the initial output level (1) of the serial data (SOmn) and serial clock (CKOmn). Enable data output, clock output, and N-ch openNote 1 Setting port Note 2 /EVDD tolerance ) drain output (VDD tolerance mode of the target channel by setting the port register, port mode register, and port output mode Starting communication Notes 1. 2. Remark 20 to 52-pin products 64 to 128-pin products At the end of the initial setting, the simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) must be set so that output is disabled and operations are stopped. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 675 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-107. Timing Chart of Address Field Transmission SSmn SEmn SOEmn Address field transmission SDRmn SCLr output CKOmn bit manipulation SDAr output D7 D6 D5 D4 D3 D2 D1 SOmn bit manipulation R/W Address D7 SDAr input Shift register mn D6 D5 D4 D0 D3 D2 D1 D0 ACK Shift operation INTIICr TSFmn Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 676 RL78/G13 <R> CHAPTER 12 SERIAL ARRAY UNIT 2 Figure 12-108. Flowchart of Simplified I C Address Field Transmission Transmitting address field Default setting Writing 0 to the SOmn bit For the initial setting, refer to Figure 12-106 Setting 0 ot the SOmn bit Start condition generate Wait To secure a hold time of SCL signal Writing 0 to the CKOmn bit Prepare to communicate the SCL signal is fall Writing 1 to the SOEmn bit Enable serial output Writing 1 to the SSmn bit Writing address and R/W data to SIOr (SDRmn[7:0]) To serial operation enable status Transmitting address field Wait for address field transmission Transfer end interrupt generated? No Yes Responded ACK? Yes No complete. (Clear the interrupt request flag) ACK response from the slave will be confirmed in PEFmn bit. if ACK (PEFmn = 0), to the next processing, if NACK (PEFmn = 1) to error processing. Communication error processing Address field transmission completed To data transmission flow and data reception flow R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 677 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.2 Data transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released. 2 Simplified I C Target channel Pins used IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31 Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1 SCL00, SCL01, SCL10, SCL11, SCL20, SCL21, SCL30, SCL31, SDA00 Interrupt Note INTIIC00 SDA01 Note INTIIC01 SDA10 Note INTIIC10 SDA11 Note INTIIC11 SDA20 Note SDA21 INTIIC20 Note INTIIC21 SDA30 Note INTIIC30 SDA31 Note INTIIC31 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) <R> Error detection flag ACK error flag (PEFmn) Transfer data length 8 bits Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel 2 However, the following condition must be satisfied in each mode of I C. * Max. 1 MHz (fast mode plus) * Max. 400 kHz (fast mode) * Max. 100 kHz (standard mode) Data level Non-reversed output (default: high level) Parity bit No parity bit Stop bit Appending 1 bit (for ACK reception timing) Data direction MSB first Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance (20 to 52-pin products/ EVDD tolerance (64 to 128-pin products)) mode (POM03, POM11, POM14, POM50, POM53, POM71, POM74, POM143 = 1) for the port output mode registers (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) (see 4.3 Registers Controlling Port Function for details). When IIC00, IIC10, IIC20, IIC30, IIC31 communicating with an external device with a different potential, set the N-ch open-drain output (VDD tolerance (20 to 52-pin products/ EVDD tolerance (64 to 128-pin products)) mode (POM04, POM10, POM15, POM54, POM142 = 1) also for the clock input/output pins (SCL00, SCL10, SCL20, SCL30, SCL31) (see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) for details). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 678 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting 2 <R> Figure 12-109. Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (1/2) (a) Serial mode register mn (SMRmn) ... Do not manipulate this register during data transmission/reception. 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 SISmn0 0 2 1 0 MDmn2 MDmn1 MDmn0 0 1 0 0 (b) Serial communication operation setting register mn (SCRmn) ... Do not manipulate the bits of this register, except the TXEmn and RXEmn bits, during data transmission/reception. 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0 0 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) ... 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 1 1 0 DLSmn1 DLSmn0 1 Note 1 1 During data transmission/reception, valid only lower 8-bits (SIOr) 15 14 13 12 11 SDRmn Baud rate setting 10 9 8 7 6 5 Note 2 4 3 2 1 0 3 2 1 0 SOm3 SOm2 SOm1 SOm0 Transmit data setting 0 SIOr (d) Serial output register m (SOm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 0/1Note3 0/1Note3 0/1Note3 0/1Note3 0/1Note3 0/1Note3 0/1Note3 0/1Note3 (e) Serial output enable register m (SOEm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 1 1 1 1 Notes 1. Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128-pin product. This bit is fixed to 1 for the other registers. 2. Because the setting is completed by address field transmission, setting is not required. 3. The value varies depending on the communication data during communication operation. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 679 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 Figure 12-109. Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (2/2) (f) Serial channel start register m (SSm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 680 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-110. Timing Chart of Data Transmission SSmn SEmn SOEmn "L" "H" "H" Transmit data 1 SDRmn SCLr output SDAr output D7 D6 D5 D4 D3 D2 D1 D0 SDAr input D7 D6 D5 D4 D3 D2 D1 D0 Shift register mn ACK Shift operation INTIICr TSFmn <R> Figure 12-111. Flowchart of Simplified I2C Data Transmission Address field transmission completed Starting data transmission Writing data to SIOr (SDRmn[7:0]) Transfer end interrupt generated? Transmission start by writing No Wait for transmission complete. (Clear the interrupt request flag) Yes ACK acknowledgment from the slave Responded ACK? No If ACK (PEF = 0), to the next process if NACK (PEF = 1), to error handling Yes Communication error processing No Data transfer completed? Yes Data transmission completed Stop condition generation R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 681 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.3 Data reception Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. After all data are received to the slave, a stop condition is generated and the bus is released. 2 Simplified I C Target channel Pins used IIC00 IIC01 IIC10 IIC11 IIC20 IIC21 IIC30 IIC31 Channel 0 Channel 1 Channel 2 Channel 3 Channel 0 Channel 1 Channel 2 Channel 3 of SAU0 of SAU0 of SAU0 of SAU0 of SAU1 of SAU1 of SAU1 of SAU1 SCL00, SCL01, SCL10, SCL11, SCL20, SCL21, SCL30, SCL31, SDA00 Interrupt Note INTIIC00 SDA01 Note INTIIC01 SDA10 Note INTIIC10 SDA11 Note INTIIC11 SDA20 Note SDA21 INTIIC20 Note INTIIC21 SDA30 Note INTIIC30 SDA31 Note INTIIC31 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) <R> Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 8 bits Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel 2 However, the following condition must be satisfied in each mode of I C. * Max. 1 MHz (fast mode plus) * Max. 400 kHz (fast mode) * Max. 100 kHz (standard mode) Data level Non-reversed output (default: high level) Parity bit No parity bit Stop bit Appending 1 bit (ACK transmission) Data direction MSB first Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance (20 to 52-pin products/ EVDD tolerance (64 to 128-pin products)) mode (POM03, POM11, POM14, POM50, POM53, POM71, POM74, POM143 = 1) for the port output mode registers (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) (see 4.3 Registers Controlling Port Function for details). When IIC00, IIC10, IIC20, IIC30, IIC31 communicating with an external device with a different potential, set the N-ch open-drain output (VDD tolerance (20 to 52-pin products/ EVDD tolerance (64 to 128-pin products)) mode (POM04, POM10, POM15, POM54, POM142 = 1) also for the clock input/output pins (SCL00, SCL10, SCL20, SCL30, SCL31) (see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) for details). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 682 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting <R> Figure 12-112. Example of Contents of Registers for Data Reception of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (1/2) (a) Serial mode register mn (SMRmn) ... Do not manipulate this register during data transmission/reception. 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 SISmn0 0 0 2 1 0 MDmn2 MDmn1 MDmn0 1 0 0 (b) Serial communication operation setting register mn (SCRmn) ... Do not manipulate the bits of this register, except the TXEmn and RXEmn bits, during data transmission/reception. 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 0 1 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0 0 5 4 3 2 SLCmn1 SLCmn0 1 0 DLSmn1 DLSmn0 0 0 1 0 1 1 Note 1 1 6 5 4 3 2 1 0 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) 15 14 13 12 11 SDRmn Baud rate setting 10 9 8 7 Note 2 Dummy transmit data setting (FFH) 0 SIOr (d) Serial output register m (SOm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 0/1Note3 0/1Note3 0/1Note3 0/1Note3 3 2 1 0 SOm3 SOm2 SOm1 SOm0 0/1Note3 0/1Note3 0/1Note3 0/1Note3 (e) Serial output enable register m (SOEm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 Notes 1. 0/1 0/1 0/1 0/1 Only provided for the SCR00 and SCR01 registers and the SCR10 and SCR11 registers of an 80- to 128-pin product. This bit is fixed to 1 for the other registers. 2. The baud rate setting is not required because the baud rate has already been set when the address field was transmitted. 3. The value varies depending on the communication data during communication operation. Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 683 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 Figure 12-112. Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) (2/2) (f) Serial channel start register m (SSm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SSm 3 2 1 0 SSm3 SSm2 SSm1 SSm0 0/1 0/1 0/1 0/1 Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 684 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-113. Timing Chart of Data Reception (a) When starting data reception SSmn STmn SEmn SOEmn "H" TXEmn, TXEmn = 1 / RXEmn = 0 RXEmn TXEmn = 0 / RXEmn = 1 SDRmn Dummy data (FFH) Receive data SCLr output SDAr output ACK D7 SDAr input D6 D5 D4 Shift register mn D3 D2 D1 D0 Shift operation INTIICr TSFmn (b) When receiving last data STmn SEmn SOEmn TXEmn, RXEmn Output is enabled by serial communication operation Output is stopped by serial communication operation TXEmn = 0 / RXEmn = 1 SDRmn Dummy data (FFH) Dummy data (FFH) Receive data Receive data SCLr output SDAr output SDAr input Shift register mn ACK D2 D1 D0 Shift operation NACK D7 D6 D5 D4 D3 D2 D1 D0 Shift operation INTIICr TSFmn Reception of last byte SOmn bit SOmn bit manipulation manipulation IIC operation stop CKOmn bit manipulation Step condition Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 685 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT Figure 12-114. Flowchart of Data Reception <R> Address field transmission completed Data reception completed Stop operation for rewriting SCRmn register. Writing 1 to the STmn bit Writing 0 to the TXEmn bit, and 1 to the RXEmn bit mode of the channel. Operation restart Writing 1 to the SSmn bit Last byte received? Set to receive only the operating No Yes Disable output so that not the ACK response to the last received data. Writing 0 to the SOEmn bit Writing dummy data (FFH) to SIOr (SDRmn[7:0]) Transfer end interrupt generated? Starting reception operation No Wait for the completion of reception. (Clear the interrupt request flag) Yes Reading SIOr (SDRmn[7:0]) Reading receive data, perform processing (stored in the RAM etc.). No Data transfer completed? Yes Data reception completed Stop condition generation Caution ACK is not output when the last data is received (NACK). Communication is then completed by setting "1" to the STmn bit of serial channel stop register m (STm) to stop operation and generating a stop condition. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 686 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 12-115. Timing Chart of Stop Condition Generation STmn SEmn SOEmn Note SCLr output SDAr output Operation stop SOmn CKOmn SOmn bit manipulation bit manipulation bit manipulation Stop condition Note During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before receiving the last data. Figure 12-116. Flowchart of Stop Condition Generation <R> Completion of data transmission/data reception Starting generation of stop condition. Writing 1 to the STmn bit to clear (the SEmn bit is cleared to 0) Writing 0 to the SOEmn bit Operation stop status (operable CKOmn manipulation) Operation disable status (operable SOmn manipulation) Writing 0 to the SOmn bit Writing 1 to the CKOmn bit Timing to satisfy the low width standard of SCL 2 for the I C bus. Wait Secure a wait time so that the specifications of 2 I C on the slave side are satisfied. Writing 1 to the SOmn bit End of IIC communication R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 687 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 12.8.5 Calculating transfer rate The transfer rate for simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication can be calculated by the following expressions. (Transfer rate) = {Operation clock (fMCK) frequency of target channel} / (SDRmn[15:9] + 1) / 2 <R> Caution SDRmn[15:9] must not be set to 00000000B. Be sure to set a value of 00000001B or greater for SDRmn[15:9]. The duty ratio of the SCL signal output by the simplified I2C is 50%. The I2C bus specifications define that the low-level width of the SCL signal is longer than the highlevel width. If 400 kbps (fast mode) or 1 Mbps (fast mode plus) is specified, therefore, the lowlevel width of the SCL output signal becomes shorter than the value specified in the I2C bus specifications. Make sure that the SDRmn[15:9] value satisfies the I2C bus specifications. Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to 1111111B) and therefore is 1 to 127. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 688 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 Table 12-4. Selection of Operation Clock For Simplified I C SMRmn Register SPSm Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 1 Operation Clock (fMCK) Note fCLK = 32 MHz X X X X 0 0 0 0 fCLK 32 MHz X X X X 0 0 0 1 fCLK/2 16 MHz X X X X 0 0 1 0 fCLK/2 2 8 MHz X X X X 0 0 1 1 fCLK/2 3 4 MHz 2 MHz X X X X 0 1 0 0 fCLK/2 4 X X X X 0 1 0 1 fCLK/2 5 1 MHz 500 kHz X X X X 0 1 1 0 fCLK/2 6 X X X X 0 1 1 1 fCLK/2 7 250 kHz 125 kHz X X X X 1 0 0 0 fCLK/2 8 X X X X 1 0 0 1 fCLK/2 9 62.5 kHz X X X X 1 0 1 0 fCLK/2 10 31.25 kHz X X X X 1 0 1 1 fCLK/2 11 15.63 kHz 0 0 0 0 X X X X fCLK 0 0 0 1 X X X X fCLK/2 0 0 1 0 X X X X fCLK/2 2 8 MHz 4 MHz 32 MHz 16 MHz 0 0 1 1 X X X X fCLK/2 3 0 1 0 0 X X X X fCLK/2 4 2 MHz 1 MHz 0 1 0 1 X X X X fCLK/2 5 0 1 1 0 X X X X fCLK/2 6 500 kHz 0 1 1 1 X X X X fCLK/2 7 250 kHz 125 kHz 1 0 0 0 X X X X fCLK/2 8 1 0 0 1 X X X X fCLK/2 9 62.5 kHz 31.25 kHz 15.63 kHz 1 0 1 0 X X X X fCLK/2 10 1 0 1 1 X X X X fCLK/2 11 Other than above Setting prohibited Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU). Remarks 1. X: Don't care 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13 2 Here is an example of setting an I C transfer rate where fMCK = fCLK = 32 MHz. 2 I C Transfer Mode (Desired Transfer Rate) <R> fCLK = 32 MHz Operation Clock (fMCK) SDRmn[15:9] Calculated Transfer Rate Error from Desired Transfer Rate 100 kHz fCLK/2 79 100 kHz 0.0% 400 kHz fCLK 41 380 kHz 5.0% 1 MHz fCLK 18 0.84 MHz 16.0% Note Note Note The error cannot be set to about 0% because the duty ratio of the SCL signal is 50%. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 689 RL78/G13 CHAPTER 12 SERIAL ARRAY UNIT 2 12.8.6 Procedure for processing errors that occurred during simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication The procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) communication is described in Figure 12-117. Figure 12-117. Processing Procedure in Case of Parity Error (ACK error) in Simplified I2C Mode <R> Software Manipulation Hardware Status Remark Reads serial data register mn The BFFmn bit of the SSRmn register is This is to prevent an overrun error if the (SDRmn). set to 0 and channel n is enabled to receive data. next reception is completed during error processing. Reads serial status register mn (SSRmn). Error type is identified and the read value is used to clear error flag. Writes serial flag clear trigger register mn Error flag is cleared. (SIRmn). Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Sets the STmn bit of serial channel stop The SEmn bit of serial channel enable Slave is not ready for reception register m (STm) to 1. status register m (SEm) is set to 0 and channel n stops operation. because ACK is not returned. Therefore, a stop condition is created, the bus is released, and communication is started again from the start condition. Or, a restart condition is generated and Creates stop condition. transmission can be redone from address transmission. Creates start condition. Sets the SSmn bit of serial channel start The SEmn bit of serial channel enable register m (SSm) to 1. status register m (SEm) is set to 1 and channel n is enabled to operate. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31) mn = 00 to 03, 10 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 690 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA CHAPTER 13 SERIAL INTERFACE IICA The number of channels of the serial Interface IICA differs, depending on the product. 20-pin 24, 25, 30, 32, 36, 40, 80, 100, 128-pin 44, 48, 52, 56, 64-pin channels Caution - 1 ch 2 ch Most of the following descriptions in this chapter use the 64-pin products as an example. 13.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLAn) line and a serial data bus (SDAAn) line. This mode complies with the I2C bus format and the master device can generated "start condition", "address", "transfer direction specification", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received status and data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCLAn and SDAAn pins are used for open drain outputs, serial interface IICA requires pull-up resistors for the serial clock line and the serial data bus line. (3) Wakeup mode The STOP mode can be released by generating an interrupt request signal (INTIICAn) when an extension code from the master device or a local address has been received while in STOP mode. This can be set by using the WUPn bit of IICA control register n1 (IICCTLn1). Figure 13-1 shows a block diagram of serial interface IICA. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 691 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-1. Block Diagram of Serial Interface IICA0 Internal bus IICA status register 0 (IICS0) WUP0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 00 (IICCTL00) Sub-circuit for standby IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Filter Slave address register 0 (SVA0) SDAA0/ P61 IICA shift register 0 (IICA0) DFC0 TRC0 N-ch opendrain output PM61 Set Match signal Noise eliminator Start condition generator Clear D Q Stop condition generator SO latch IICWL0 Data hold time correction circuit ACK generator Output control Output latch (P61) Wakeup controller ACK detector Start condition detector Filter Stop condition detector SCLA0/ P60 Noise eliminator Interrupt request signal generator Serial clock counter INTIICA0 IICS0.MSTS0, EXC0, COI0 DFC0 N-ch opendrain output PM60 fCLK Output latch (P60) fCLK/2 Selector Serial clock controller Serial clock wait controller IICA shift register 0 (IICA0) IICCTL00.STT0, SPT0 Counter Bus status detector IICS0.MSTS0, EXC0, COI0 Match signal IICCTL01.PRS0 IICA low-level width setting register 0 (IICWL0) IICA high-level width setting register 0 (IICWH0) WUP0 CLD0 DAD0 SMC0 DFC0 PRS0 IICA control register 01 (IICCTL01) STCF0 IICBSY0 STCEN0 IICRSV0 IICA flag register 0 (IICF0) Internal bus R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 692 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-2 shows a serial bus configuration example. Figure 13-2. Serial Bus Configuration Example Using I2C Bus + VDD + VDD Master CPU1 SDAAn Slave CPU1 Address 0 SCLAn Serial data bus Serial clock SDAAn Slave CPU2 SCLAn SDAAn SCLAn SDAAn SCLAn SDAAn SCLAn Remark Master CPU2 Address 1 Slave CPU3 Address 2 Slave IC Address 3 Slave IC Address N n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 693 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 13-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register n (IICAn) Slave address register n (SVAn) Control registers Peripheral enable register 0 (PER0) IICA control register n0 (IICCTLn0) IICA status register n (IICSn) IICA flag register n (IICFn) IICA control register n1 (IICCTLn1) IICA low-level width setting register n (IICWLn) IICA high-level width setting register n (IICWHn) Port mode register 6 (PM6) Port register 6 (P6) (1) IICA shift register n (IICAn) The IICAn register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. The IICAn register can be used for both transmission and reception. The actual transmit and receive operations can be controlled by writing and reading operations to the IICAn register. Cancel the wait state and start data transfer by writing data to the IICAn register during the wait period. The IICAn register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears IICAn to 00H. Figure 13-3. Format of IICA Shift Register n (IICAn) Address: FFF50H (IICA0), FFF54H (IICA1) Symbol 7 6 5 After reset: 00H 4 3 R/W 2 1 0 IICAn Cautions 1. Do not write data to the IICAn register during data transfer. 2. Write or read the IICAn register only during the wait period. Accessing the IICAn register in a communication state other than during the wait period is prohibited. When the device serves as the master, however, the IICAn register can be written only once after the communication trigger bit (STTn) is set to 1. 3. When communication is reserved, write data to the IICAn register after the interrupt triggered by a stop condition is detected. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 694 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) Slave address register n (SVAn) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVAn register can be set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STDn = 1 (while the start condition is detected). Reset signal generation clears the SVAn register to 00H. Figure 13-4. Format of Slave Address Register n (SVAn) Address: F0234H (SVA0), F023DH (SVA1) After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 SVAn A6 A5 A4 A3 A2 A1 A0 0Note Note Bit 0 is fixed to 0. (3) SO latch The SO latch is used to retain the SDAAn pin's output level. (4) Wakeup controller This circuit generates an interrupt request (INTIICAn) when the address received by this register matches the address value set to the slave address register n (SVAn) or when an extension code is received. (5) Serial clock counter This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (6) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICAn). An I2C interrupt request is generated by the following two triggers. * Falling edge of eighth or ninth clock of the serial clock (set by the WTIMn bit) * Interrupt request generated when a stop condition is detected (set by the SPIEn bit) Remark WTIMn bit: Bit 3 of IICA control register n0 (IICCTLn0) SPIEn bit: Bit 4 of IICA control register n0 (IICCTLn0) (7) Serial clock controller In master mode, this circuit generates the clock output via the SCLAn pin from a sampling clock. (8) Serial clock wait controller This circuit controls the wait timing. (9) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (10) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 695 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (11) Start condition generator This circuit generates a start condition when the STTn bit is set to 1. However, in the communication reservation disabled status (IICRSVn bit = 1), when the bus is not released (IICBSYn bit = 1), start condition requests are ignored and the STCFn bit is set to 1. (12) Stop condition generator This circuit generates a stop condition when the SPTn bit is set to 1. (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCENn bit. Remarks 1. 2. STTn bit: Bit 1 of IICA control register n0 (IICCTLn0) SPTn bit: Bit 0 of IICA control register n0 (IICCTLn0) IICRSVn bit: Bit 0 of IICA flag register n (IICFn) IICBSYn bit: Bit 6 of IICA flag register n (IICFn) STCFn bit: Bit 7 of IICA flag register n (IICFn) STCENn bit: Bit 1 of IICA flag register n (IICFn) n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 696 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following eight registers. * Peripheral enable register 0 (PER0) * IICA control register n0 (IICCTLn0) * IICA flag register n (IICFn) * IICA status register n (IICSn) * IICA control register n1 (IICCTLn1) * IICA low-level width setting register n (IICWLn) * IICA high-level width setting register n (IICWHn) * Port mode register 6 (PM6) * Port register 6 (P6) (1) Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial interface IICAn is used, be sure to set bits 6, 4 (IICA1EN, IICA0EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-5. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H Symbol PER0 After reset: 00H <7> RTCEN R/W <6> Note 1 <5> Note 1 IICA1EN <4> IICA0EN ADCEN IICAnEN <3> Note 2 SAU1EN <2> Note 3 SAU0EN <1> <0> Note 1 TAU1EN TAU0EN Control of serial interface IICAn input clock supply Stops input clock supply. 0 * SFR used by serial interface IICAn cannot be written. * Serial interface IICAn is in the reset status. Enables input clock supply. 1 * SFR used by serial interface IICAn can be read/written. Notes 1. 80, 100, and 128-pin products only. 2. This is not provided in the 20-pin products. 3. This is not provided in the 20, 24, and 25-pin products. Cautions 1. When setting serial interface IICAn, be sure to set the IICAnEN bit to 1 first. If IICAnEN = 0, writing to a control register of serial interface IICAn is ignored, and, even if the register is read, only the default value is read (except for port mode register 6 (PM6) and port register 6 (P6)). 2. Be sure to clear the following bits to 0. 20-pin products: bits 1, 3, 4, 6 24, 25-pin products: bits 1, 3, 6 30, 32, 36, 40, 44, 48, 52, 64-pin products: bits 1, 6 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 697 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) IICA control register n0 (IICCTLn0) This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations. The IICCTLn0 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIEn, WTIMn, and ACKEn bits while IICEn = 0 or during the wait period. These bits can be set at the same time when the IICEn bit is set from "0" to "1". Reset signal generation clears this register to 00H. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 698 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register n0 (IICCTLn0) (1/4) Address: F0230H (IICCTL00), F0238H (IICCTL10) After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTLn0 IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn 2 IICEn I C operation enable Note 1 0 Stop operation. Reset the IICA status register n (IICSn) 1 Enable operation. . Stop internal operation. Be sure to set this bit (1) while the SCLAn and SDAAn lines are at high level. Condition for clearing (IICEn = 0) Condition for setting (IICEn = 1) * Cleared by instruction * Set by instruction * Reset Notes 2, 3 LRELn Exit from communications 0 Normal operation 1 This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCLAn and SDAAn lines are set to high impedance. The following flags of IICA control register n0 (IICCTLn0) and the IICA status register n (IICSn) are cleared to 0. * STTn * SPTn * MSTSn * EXCn * COIn * TRCn * ACKDn * STDn The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LRELn = 0) Condition for setting (LRELn = 1) * Automatically cleared after execution * Set by instruction * Reset Notes 2, 3 WRELn Wait cancellation 0 Do not cancel wait 1 Cancel wait. This setting is automatically cleared after wait is canceled. When the WRELn bit is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRCn = 1), the SDAAn line goes into the high impedance state (TRCn = 0). Condition for clearing (WRELn = 0) Condition for setting (WRELn = 1) * Automatically cleared after execution * Set by instruction * Reset Notes 1. The IICA status register n (IICSn), the STCFn and IICBSYn bits of the IICA flag register n (IICFn), and the CLDn and DADn bits of IICA control register n1 (IICCTLn1) are reset. 2. The signal of this bit is invalid while IICEn is 0. 3. When the LRELn and WRELn bits are read, 0 is always read. Caution 2 If the operation of I C is enabled (IICEn = 1) when the SCLAn line is high level, the SDAAn line is low level, and the digital filter is turned on (DFCn bit of IICCTLn1 register = 1), a start condition will be inadvertently detected immediately. In this case, set (1) the LRELn bit by 2 using a 1-bit memory manipulation instruction immediately after enabling operation of I C (IICEn = 1). Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 699 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register n0 (IICCTLn0) (2/4) Note 1 SPIEn Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn = 1. Condition for clearing (SPIEn = 0) Condition for setting (SPIEn = 1) * Cleared by instruction * Reset * Set by instruction Note 1 WTIMn Control of wait and interrupt request generation 0 Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device. An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIMn = 0) Condition for setting (WTIMn = 1) * Cleared by instruction * Set by instruction * Reset Notes 1, 2 ACKEn Acknowledgment control 0 Disable acknowledgment. 1 Enable acknowledgment. During the ninth clock period, the SDAAn line is set to low level. Condition for clearing (ACKEn = 0) Condition for setting (ACKEn = 1) * Cleared by instruction * Set by instruction * Reset Notes 1. The signal of this bit is invalid while IICEn is 0. Set this bit during that period. 2. The set value is invalid during address transfer and if the code is not an extension code. When the device serves as a slave and the addresses match, an acknowledgment is generated regardless of the set value. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 700 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register n0 (IICCTLn0) (3/4) STTn Note Start condition trigger 0 Do not generate a start condition. 1 When bus is released (in standby state, when IICBSYn = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: * When communication reservation function is enabled (IICRSVn = 0) Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSVn = 1) Even if this bit is set (1), the STTn bit is cleared and the STTn clear flag (STCFn) is set (1). No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the ACKEn bit has been cleared to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as stop condition trigger (SPTn). * Once STTn is set (1), setting it again (1) before the clear condition is met is not allowed. Condition for clearing (STTn = 0) Condition for setting (STTn = 1) * Cleared by setting the STTn bit to 1 while * Set by instruction communication reservation is prohibited. * Cleared by loss in arbitration * Cleared after start condition is generated by master device * Cleared by LRELn = 1 (exit from communications) * When IICEn = 0 (operation stop) * Reset Note The signal of this bit is invalid while IICEn is 0. Remarks 1. Bit 1 (STTn) becomes 0 when it is read after data setting. 2. IICRSVn: Bit 0 of IIC flag register n (IICFn) STCFn: Bit 7 of IIC flag register n (IICFn) 3. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 701 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register n0 (IICCTLn0) (4/4) SPTn Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device's transfer). Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the ACKEn bit has been cleared to 0 and slave has been notified of final reception. * For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as start condition trigger (STTn). * The SPTn bit can be set to 1 only when in master mode. * When the WTIMn bit has been cleared to 0, if the SPTn bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIMn bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPTn bit should <R> be set to 1 during the wait period that follows the output of the ninth clock. * Once SPTn is set (1), setting it again (1) before the clear condition is met is not allowed. Condition for clearing (SPTn = 0) Condition for setting (SPTn = 1) * Cleared by loss in arbitration * Set by instruction * Automatically cleared after stop condition is detected * Cleared by LRELn = 1 (exit from communications) * When IICEn = 0 (operation stop) * Reset Caution When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission status), bit 5 (WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and wait is canceled, after which the TRCn bit is cleared (reception status) and the SDAAn line is set to high impedance. Release the wait performed while the TRCn bit is 1 (transmission status) by writing to the IICA shift register n. Remarks 1. 2. Bit 0 (SPTn) becomes 0 when it is read after data setting. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 702 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (3) IICA status register n (IICSn) This register indicates the status of I2C. The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the wait period. Reset signal generation clears this register to 00H. Caution Reading the IICSn register while the address match wakeup function is enabled (WUPn = 1) in STOP mode is prohibited. When the WUPn bit is changed from 1 to 0 (wakeup operation is stopped), regardless of the INTIICAn interrupt request, the change in status is not reflected until the next start condition or stop condition is detected. To use the wakeup function, therefore, enable (SPIEn = 1) the interrupt generated by detecting a stop condition and read the IICSn register after the interrupt has been detected. Remark STTn: bit 1 of IICA control register n0 (IICCTLn0) WUPn: bit 7 of IICA control register n1 (IICCTLn1) Figure 13-7. Format of IICA Status Register n (IICSn) (1/3) Address: FFF51H (IICS0), FFF55H (IICS1) After reset: 00H R Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn MSTSn Master status check flag 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing (MSTSn = 0) Condition for setting (MSTSn = 1) * When a stop condition is detected * When ALDn = 1 (arbitration loss) * Cleared by LRELn = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset * When a start condition is generated ALDn Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a "win". 1 This status indicates the arbitration result was a "loss". The MSTSn bit is cleared. Condition for clearing (ALDn = 0) Condition for setting (ALDn = 1) * Automatically cleared after the IICSn register is Note read * When the IICEn bit changes from 1 to 0 (operation stop) * Reset * When the arbitration result is a "loss". Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than the IICSn register. Therefore, when using the ALDn bit, read the data of this bit before the data of the other bits. Remarks 1. LRELn: Bit 6 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0) 2. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 n = 0, 1 703 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register n (IICSn) (2/3) EXCn Detection of extension code reception 0 Extension code was not received. 1 Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset * When the higher four bits of the received address COIn data is either "0000" or "1111" (set at the rising edge of the eighth clock). Detection of matching addresses 0 Addresses do not match. 1 Addresses match. Condition for clearing (COIn = 0) Condition for setting (COIn = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LRELn = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset * When the received address matches the local TRCn address (slave address register n (SVAn)) (set at the rising edge of the eighth clock). Detection of transmit/receive status 0 Receive status (other than transmit status). The SDAAn line is set for high impedance. 1 Transmit status. The value in the SOn latch is enabled for output to the SDAAn line (valid starting at the falling edge of the first byte's ninth clock). Condition for clearing (TRCn = 0) Condition for setting (TRCn = 1) <Both master and slave> <Master> * When a stop condition is detected * Cleared by LRELn = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) Note * Cleared by WRELn = 1 (wait cancel) * When the ALDn bit changes from 0 to 1 (arbitration loss) * Reset * When not used for communication (MSTSn, EXCn, COIn = 0) <Master> * When "1" is output to the first byte's LSB (transfer direction specification bit) <Slave> * When a start condition is detected * When "0" is input to the first byte's LSB (transfer direction specification bit) * When a start condition is generated * When 0 (master transmission) is output to the LSB (transfer direction specification bit) of the first byte (during address transfer) <Slave> * When 1 (slave transmission) is input to the LSB (transfer direction specification bit) of the first byte from the master (during address transfer) Note When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission status), bit 5 (WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and wait is canceled, after which the TRCn bit is cleared (reception status) and the SDAAn line is set to high impedance. Release the wait performed while the TRCn bit is 1 (transmission status) by writing to the IICA shift register n. Remarks 1. 2. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 LRELn: Bit 6 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0) n = 0, 1 704 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register n (IICSn) (3/3) ACKDn Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1) * When a stop condition is detected * After the SDAAn line is set to low level at the rising edge of SCLAn line's ninth clock * At the rising edge of the next byte's first clock * Cleared by LRELn = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset STDn Detection of start condition 0 Start condition was not detected. 1 Start condition was detected. This indicates that the address transfer period is in effect. Condition for clearing (STDn = 0) Condition for setting (STDn = 1) * When a stop condition is detected * When a start condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LRELn = 1 (exit from communications) * When the IICEn bit changes from 1 to 0 (operation stop) * Reset SPDn Detection of stop condition 0 Stop condition was not detected. 1 Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for clearing (SPDn = 0) Condition for setting (SPDn = 1) * At the rising edge of the address transfer byte's first * When a stop condition is detected clock following setting of this bit and detection of a start condition * When the WUPn bit changes from 1 to 0 * When the IICEn bit changes from 1 to 0 (operation stop) * Reset Remarks 1. 2. LRELn: Bit 6 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0) n = 0, 1 (4) IICA flag register n (IICFn) This register sets the operation mode of I2C and indicates the status of the I2C bus. The IICFn register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STTn clear flag (STCFn) and I2C bus status flag (IICBSYn) bits are read-only. The IICRSVn bit can be used to enable/disable the communication reservation function. The STCENn bit can be used to set the initial value of the IICBSYn bit. The IICRSVn and STCENn bits can be written only when the operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) = 0). When operation is enabled, the IICFn register can be read. Reset signal generation clears this register to 00H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 705 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-8. Format of IICA Flag Register n (IICFn) Address: FFF52H (IICF0), FFF56H (IICF1) R/WNote After reset: 00H Symbol <7> <6> 5 4 3 2 IICFn STCFn IICBSYn 0 0 0 0 <1> <0> STCENn IICRSVn STTn clear flag STCFn 0 Generate start condition 1 Start condition generation unsuccessful: clear the STTn flag Condition for clearing (STCFn = 0) Condition for setting (STCFn = 1) * Cleared by STTn = 1 * When IICEn = 0 (operation stop) * Reset * Generating start condition unsuccessful and the STTn bit cleared to 0 when communication reservation is disabled (IICRSVn = 1). I2C bus status flag IICBSYn 0 Bus release status (communication initial status when STCENn = 1) 1 Bus communication status (communication initial status when STCENn = 0) Condition for clearing (IICBSYn = 0) Condition for setting (IICBSYn = 1) * Detection of stop condition * When IICEn = 0 (operation stop) * Reset * Detection of start condition * Setting of the IICEn bit when STCENn = 0 STCENn Initial start enable trigger 0 After operation is enabled (IICEn = 1), enable generation of a start condition upon detection of a stop condition. 1 After operation is enabled (IICEn = 1), enable generation of a start condition without detecting a stop condition. Condition for clearing (STCENn = 0) Condition for setting (STCENn = 1) * Cleared by instruction * Detection of start condition * Reset * Set by instruction IICRSVn Communication reservation function disable bit 0 Enable communication reservation 1 Disable communication reservation Condition for clearing (IICRSVn = 0) Condition for setting (IICRSVn = 1) * Cleared by instruction * Reset * Set by instruction Note Bits 6 and 7 are read-only. Cautions 1. Write to the STCENn bit only when the operation is stopped (IICEn = 0). 2. As the bus release status (IICBSYn = 0) is recognized regardless of the actual bus status when STCENn = 1, when generating the first start condition (STTn = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. Write to IICRSVn only when the operation is stopped (IICEn = 0). Remarks 1. STTn: Bit 1 of IICA control register n0 (IICCTLn0) IICEn: Bit 7 of IICA control register n0 (IICCTLn0) 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 706 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (5) IICA control register n1 (IICCTLn1) This register is used to set the operation mode of I2C and detect the statuses of the SCLAn and SDAAn pins. The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn bits are read-only. Set the IICCTLn1 register, except the WUPn bit, while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0). Reset signal generation clears this register to 00H. Figure 13-9. Format of IICA Control Register n1 (IICCTLn1) (1/2) Address: F0231H (IICCTL01), F0239H (IICCTL11) After reset: 00H R/W Note 1 Symbol <7> 6 <5> <4> <3> <2> 1 <0> IICCTLn1 WUPn 0 CLDn DADn SMCn DFCn 0 PRSn WUPn Control of address match wakeup 0 Stops operation of address match wakeup function in STOP mode. 1 Enables operation of address match wakeup function in STOP mode. To shift to STOP mode when WUPn = 1, execute the STOP instruction at least three clocks after setting (1) the WUPn bit (see Figure 13-22 Flow When Setting WUPn = 1). Clear (0) the WUPn bit after the address has matched or an extension code has been received. The subsequent communication can be entered by the clearing (0) WUPn bit. (The wait must be released and transmit data must be written after the WUPn bit has been cleared (0).) The interrupt timing when the address has matched or when an extension code has been received, while WUPn = 1, is identical to the interrupt timing when WUPn = 0. (A delay of the difference of sampling by the clock will occur.) Furthermore, when WUPn = 1, a stop condition interrupt is not generated even if the SPIEn bit is set to 1. Condition for clearing (WUPn = 0) Condition for setting (WUPn = 1) * Cleared by instruction (after address match or * Set by instruction (when the MSTSn, EXCn, and extension code reception) COIn bits are "0", and the STDn bit also "0" Note 2 (communication not entered)) Notes 1. Bits 4 and 5 are read-only. 2. The status of the IICA status register n (IICSn) must be checked and the WUPn bit must be set during the period shown below. <1> <2> SCLAn SDAAn A6 A5 A4 A3 A2 A1 A0 R/W The maximum time from reading IICSn to setting WUPn is the period from <1> to <2>. Check the IICSn operation status and set WUPn during this period. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 707 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-9. Format of IICA Control Register n1 (IICCTLn1) (2/2) CLDn Detection of SCLAn pin level (valid only when IICEn = 1) 0 The SCLAn pin was detected at low level. 1 The SCLAn pin was detected at high level. Condition for clearing (CLDn = 0) Condition for setting (CLDn = 1) * When the SCLAn pin is at low level * When the SCLAn pin is at high level * When IICEn = 0 (operation stop) * Reset DADn Detection of SDAAn pin level (valid only when IICEn = 1) 0 The SDAAn pin was detected at low level. 1 The SDAAn pin was detected at high level. Condition for clearing (DADn = 0) Condition for setting (DADn = 1) * When the SDAAn pin is at low level * When the SDAAn pin is at high level * When IICEn = 0 (operation stop) * Reset SMCn Operation mode switching 0 Operates in standard mode (fastest transfer rate: 100 kbps). 1 Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1 Mbps). DFCn <R> Digital filter operation control 0 Digital filter off. 1 Digital filter on. Digital filter can be used only in fast mode and fast mode plus. In fast mode and fast mode plus, the transfer clock does not vary, regardless of the DFCn bit being set (1) or cleared (0). The digital filter is used for noise elimination in fast mode and fast mode plus. PRSn Division of the operation clock 0 Selects fCLK as operation clock. 1 Selects fCLK/2 as operation clock. Caution The fastest operation frequency of the operation clock of the serial interface IICA is 20 MHz (Max.). If the fCLK exceeds 20 MHz, set the clock to fCLK/2 by setting the PRSn bit to 1. Remarks 1. 2. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 IICEn: Bit 7 of IICA control register n0 (IICCTLn0) n = 0, 1 708 RL78/G13 <R> CHAPTER 13 SERIAL INTERFACE IICA (6) IICA low-level width setting register n (IICWLn) This register is used to set the low-level width (tLOW) of the SCLAn pin signal that is output by serial interface IICA. The data hold time is decided by value the higher 6 bits of IICWL register. The IICWLn register can be set by an 8-bit memory manipulation instruction. Set the IICWLn register while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0). Reset signal generation sets this register to FFH. For details about setting the IICWLn register, see 13.4.2 Setting transfer clock by using IICWLn and IICWHn registers. Figure 13-10. Format of IICA Low-Level Width Setting Register n (IICWLn) Address: F0232H (IICWL0), F023AH (IICWL1) Symbol 7 6 5 4 After reset: FFH R/W 3 2 1 0 IICWLn (7) IICA high-level width setting register n (IICWHn) This register is used to set the high-level width of the SCLAn pin signal that is output by serial interface IICA. The IICWHn register can be set by an 8-bit memory manipulation instruction. Set the IICWHn register while operation of I2C is disabled (bit 7 (IICEn) of IICA control register n0 (IICCTLn0) is 0). Reset signal generation sets this register to FFH. Figure 13-11. Format of IICA High-Level Width Setting Register n (IICWHn) Address: F0233H (IICWH0), F023BH (IICWH1) Symbol 7 6 5 4 After reset: FFH R/W 3 2 1 0 IICWHn Remarks 1. For how to set the transfer clock by using the IICWLn and IICWHn registers, see 13.4.2 Setting transfer clock by using IICWLn and IICWHn registers. 2. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 n = 0, 1 709 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (8) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set the IICEn bit (bit 7 of IICA control register n0 (IICCTLn0)) to 1 before setting the output mode because the P60/SCLA0 and P61/SDAA0 pins output a low level (fixed) when the IICEn bit is 0. The PM6 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 13-12. Format of Port Mode Register 6 (PM6) Address: FFF26H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM6 1 1 1 1 PM63 PM62 PM61 PM60 PM6n P6n pin I/O mode selection (n = 0 to 3) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 710 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.4 I2C Bus Mode Functions 13.4.1 Pin configuration The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows. (1) SCLAn .... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDAAn .... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 13-13. Pin Configuration Diagram Slave device VDD Master device SCLAn SCLAn (Clock output) Clock output VDD VSS VSS Clock input (Clock input) SDAAn SDAAn Data output Data output VSS Data input VSS Data input Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 711 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.4.2 Setting transfer clock by using IICWLn and IICWHn registers (1) Setting transfer clock on master side fCLK Transfer clock = IICWL0 + IICWH0 + fCLK (tR + tF) At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows. (The fractional parts of all setting values are rounded up.) * When the fast mode 0.52 x fCLK Transfer clock 0.48 - tR - tF) x fCLK IICWHn = ( Transfer clock IICWLn = * When the normal mode 0.47 x fCLK Transfer clock 0.53 - tR - tF) x fCLK IICWHn = ( Transfer clock IICWLn = * When the fast mode plus 0.50 x fCLK Transfer clock 0.50 - tR - tF) x fCLK IICWHn = ( Transfer clock IICWLn = (2) Setting IICWLn and IICWHn registers on slave side (The fractional parts of all setting values are truncated.) * When the fast mode IICWLn = 1.3 s x fCLK IICWHn = (1.2 s - tR - tF) x fCLK * When the normal mode IICWLn = 4.7 s x fCLK IICWHn = (5.3 s - tR - tF) x fCLK * When the fast mode plus IICWLn = 0.50 s x fCLK IICWHn = (0.50 s - tR - tF) x fCLK (Caution and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 712 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Caution Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK operation frequency for serial interface IICA is determined according to the mode. Fast mode: fCLK = 3.5 MHz (MIN.) Fast mode plus: fCLK = 10 MHz (MIN.) Normal mode: fCLK = 1 MHz (MIN.) In addition, the fastest operation frequency of the operation clock of the serial interface IICA is 20 MHz (Max.). If the fCLK exceeds 20 MHz, set the clock to fCLK/2 by setting the PRSn bit of IICCTLn1 register to 1. Remarks 1. Calculate the rise time (tR) and fall time (tF) of the SDAAn and SCLAn signals separately, because they differ depending on the pull-up resistance and wire load. 2. 3. IICWLn: IICA low-level width setting register n IICWHn: IICA high-level width setting register n tF: SDAAn and SCLAn signal falling times tR: SDAAn and SCLAn signal rising times fCLK: CPU/peripheral hardware clock frequency n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 713 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. Figure 13-14 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the I2C bus's serial data bus. Figure 13-14. I2C Bus Serial Data Transfer Timing SCLAn 1-7 8 9 1-8 9 1-8 9 ACK Data ACK SDAAn Start condition Address R/W ACK Data Stop condition The master device generates the start condition, slave address, and stop condition. The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCLAn) is continuously output by the master device. However, in the slave device, the SCLAn pin low level period can be extended and a wait can be inserted. 13.5.1 Start conditions A start condition is met when the SCLAn pin is at high level and the SDAAn pin changes from high level to low level. The start conditions for the SCLAn pin and SDAAn pin are signals that the master device generates to the slave device when starting a serial transfer. When the device is used as a slave, start conditions can be detected. Figure 13-15. Start Conditions SCLAn H SDAAn A start condition is output when bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set (1) after a stop condition has been detected (SPDn: Bit 0 of the IICA status register n (IICSn) = 1). When a start condition is detected, bit 1 (STDn) of the IICSn register is set (1). Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 714 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the slave address register n (SVAn). If the address data matches the SVAn register values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. Figure 13-16. Address SCLAn 1 2 3 4 5 6 7 8 SDAAn A6 A5 A4 A3 A2 A1 A0 R/W 9 Address Note INTIICAn Note INTIICAn is not issued if data other than a local address or extension code is received during slave device operation. Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in 13.5.3 Transfer direction specification are written to the IICA shift register n (IICAn). The received addresses are written to the IICAn register. The slave address is assigned to the higher 7 bits of the IICAn register. 13.5.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of "1", it indicates that the master device is receiving data from a slave device. Figure 13-17. Transfer Direction Specification SCLAn 1 2 3 4 5 6 7 8 SDAAn A6 A5 A4 A3 A2 A1 A0 R/W 9 Transfer direction specification INTIICAn Note Note INTIICAn is not issued if data other than a local address or extension code is received during slave device operation. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 715 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected can be checked by using bit 2 (ACKDn) of the IICA status register n (IICSn). When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission. If ACK is not returned, the possible causes are as follows. <1> Reception was not performed normally. <2> The final data item was received. <3> The reception side specified by the address does not exist. To generate ACK, the reception side makes the SDAAn line low at the ninth clock (indicating normal reception). Automatic generation of ACK is enabled by setting bit 2 (ACKEn) of IICA control register n0 (IICCTLn0) to 1. Bit 3 (TRCn) of the IICSn register is set by the data of the eighth bit that follows 7-bit address information. Usually, set the ACKEn bit to 1 for reception (TRCn = 0). If a slave can receive no more data during reception (TRCn = 0) or does not require the next data item, then the slave must inform the master, by clearing the ACKEn bit to 0, that it will not receive any more data. When the master does not require the next data item during reception (TRCn = 0), it must clear the ACKEn bit to 0 so that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). Figure 13-18. ACK SCLAn 1 2 3 4 5 6 7 8 9 SDAAn A6 A5 A4 A3 A2 A1 A0 R/W ACK When the local address is received, ACK is automatically generated, regardless of the value of the ACKEn bit. When an address other than that of the local address is received, ACK is not generated (NACK). When an extension code is received, ACK is generated if the ACKEn bit is set to 1 in advance. How ACK is generated when data is received differs as follows depending on the setting of the wait timing. * When 8-clock wait state is selected (bit 3 (WTIMn) of IICCTLn0 register = 0): By setting the ACKEn bit to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of the SCLAn pin. * When 9-clock wait state is selected (bit 3 (WTIMn) of IICCTLn0 register = 1): ACK is generated by setting the ACKEn bit to 1 in advance. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 716 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.5 Stop condition When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 13-19. Stop Condition SCLAn H SDAAn A stop condition is generated when bit 0 (SPTn) of IICA control register n0 (IICCTLn0) is set to 1. When the stop condition is detected, bit 0 (SPDn) of the IICA status register n (IICSn) is set to 1 and INTIICAn is generated when bit 4 (SPIEn) of the IICCTLn0 register is set to 1. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 717 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLAn pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 13-20. Wait (1/2) (1) When master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and ACKEn = 1) Master Master returns to high impedance but slave is in wait state (low level). IICAn Wait after output of ninth clock IICA0 data write (cancel wait) SCLAn 6 7 8 9 1 2 3 Slave Wait after output of eighth clock FFH is written to IICAn or WRELn is set to 1 IICAn SCLAn ACKEn H Transfer lines Wait from slave SCLAn 6 7 8 SDAAn D2 D1 D0 Wait from master 9 ACK 1 2 3 D7 D6 D5 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 718 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-20. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKEn = 1) Master Master and slave both wait after output of ninth clock IICAn data write (cancel wait) IICAn 6 SCLAn 7 8 9 1 2 3 Slave FFH is written to IICAn or WRELn is set to 1 IICAn SCLAn ACKEn H Wait from master and slave Transfer lines SCLAn 6 7 8 9 SDAAn D2 D1 D0 ACK Wait from slave 1 D7 2 3 D6 D5 Generate according to previously set ACKEn value Remark ACKEn: Bit 2 of IICA control register n0 (IICCTLn0) WRELn: Bit 5 of IICA control register n0 (IICCTLn0) A wait may be automatically generated depending on the setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0). Normally, the receiving side cancels the wait state when bit 5 (WRELn) of the IICCTLn0 register is set to 1 or when FFH is written to the IICA shift register n (IICAn), and the transmitting side cancels the wait state when data is written to the IICAn register. The master device can also cancel the wait state via either of the following methods. * By setting bit 1 (STTn) of the IICCTLn0 register to 1 * By setting bit 0 (SPTn) of the IICCTLn0 register to 1 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 719 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.7 Canceling wait The I2C usually cancels a wait state by the following processing. * Writing data to the IICA shift register n (IICAn) * Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) * Setting bit 1 (STTn) of the IICCTLn0 register (generating start condition)Note * Setting bit 0 (SPTn) of the IICCTLn0 register (generating stop condition)Note Note Master only When the above wait canceling processing is executed, the I2C cancels the wait state and communication is resumed. To cancel a wait state and transmit data (including addresses), write the data to the IICAn register. To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WRELn) of the IICCTLn0 register to 1. To generate a restart condition after canceling a wait state, set bit 1 (STTn) of the IICCTLn0 register to 1. To generate a stop condition after canceling a wait state, set bit n (SPTn) of the IICCTLn0 register to 1. Execute the canceling processing only once for one wait state. If, for example, data is written to the IICAn register after canceling a wait state by setting the WRELn bit to 1, an incorrect value may be output to SDAAn line because the timing for changing the SDAAn line conflicts with the timing for writing the IICAn register. In addition to the above, communication is stopped if the IICEn bit is cleared to 0 when communication has been aborted, so that the wait state can be canceled. If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LRELn) of the IICCTLn0 register, so that the wait state can be canceled. Caution If a processing to cancel a wait state is executed when WUPn = 1, the wait state will not be canceled. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 720 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.8 Interrupt request (INTIICAn) generation timing and wait control The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is generated and the corresponding wait control, as shown in Table 13-2. Table 13-2. INTIICAn Generation Timing and Wait Control WTIMn During Slave Device Operation Address 0 1 9 Notes 1, 2 9 Notes 1, 2 Data Reception 8 Note 2 9 Note 2 During Master Device Operation Data Transmission Address Data Reception Data Transmission 8 Note 2 9 8 8 9 Note 2 9 9 9 Notes 1. The slave device's INTIICAn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the slave address register n (SVAn). At this point, ACK is generated regardless of the value set to the IICCTLn0 register's bit 2 (ACKEn). For a slave device that has received an extension code, INTIICAn occurs at the falling edge of the eighth clock. However, if the address does not match after restart, INTIICAn is generated at the falling edge of the 9th clock, but wait does not occur. 2. If the received address does not match the contents of the slave address register n (SVAn) and extension code is not received, neither INTIICAn nor a wait occurs. Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined depending on the conditions described in Notes 1 and 2 above, regardless of the WTIMn bit. * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIMn bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIMn bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * Writing data to the IICA shift register n (IICAn) * Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) * Setting bit 1 (STTn) of IICCTLn0 register (generating start condition)Note * Setting bit 0 (SPTn) of IICCTLn0 register (generating stop condition)Note Note Master only. When an 8-clock wait has been selected (WTIMn = 0), the presence/absence of ACK generation must be determined prior to wait cancellation. (5) Stop condition detection INTIICAn is generated when a stop condition is detected (only when SPIEn = 1). Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 721 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.9 Address match detection method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICAn) occurs when the address set to the slave address register n (SVAn) matches the slave address sent by the master device, or when an extension code has been received. 13.5.10 Error detection In I2C bus mode, the status of the serial data bus (SDAAn) during data transmission is captured by the IICA shift register n (IICAn) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match. 13.5.11 Extension code (1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag (EXCn) is set to 1 for extension code reception and an interrupt request (INTIICAn) is issued at the falling edge of the eighth clock. The local address stored in the slave address register n (SVAn) is not affected. (2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when the SVAn register is set to 11110xx0. Note that INTIICAn occurs at the falling edge of the eighth clock. * Higher four bits of data match: EXCn = 1 * Seven bits of data match: Remark COIn = 1 EXCn: Bit 5 of IICA status register n (IICSn) COIn: Bit 4 of IICA status register n (IICSn) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. If the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. For example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 to set the standby mode for the next communication operation. Table 13-3. Bit Definitions of Major Extension Codes Slave Address R/W Bit 0000 000 0 1111 0xx 0 Description General call address 10-bit slave address specification (during address authentication) 1111 0xx 1 10-bit slave address specification (after address match, when read command is issued) Remarks 1. See the I2C bus specifications issued by NXP Semiconductors for details of extension codes other than those described above. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 722 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STTn bit is set to 1 before the STDn bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (ALDn) in the IICA status register n (IICSn) is set (1) via the timing by which the arbitration loss occurred, and the SCLAn and SDAAn lines are both set to high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALDn = 1 setting that has been made by software. For details of interrupt request timing, see 13.5.8 Interrupt request (INTIICAn) generation timing and wait control. Remark STDn: Bit 1 of IICA status register n (IICSn) STTn: Bit 1 of IICA control register n0 (IICCTLn0) Figure 13-21. Arbitration Timing Example Master 1 SCLAn SDAAn Master 2 Hi-Z Hi-Z Master 1 loses arbitration SCLAn SDAAn Transfer lines SCLAn SDAAn Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 723 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Table 13-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration During address transmission Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer Note 1 Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK transfer period after data transmission When restart condition is detected during data transfer Note 2 When stop condition is detected during data transfer When stop condition is generated (when SPIEn = 1) When data is at low level while attempting to generate a restart At falling edge of eighth or ninth clock following byte transfer Note 1 condition When stop condition is detected while attempting to generate a Note 2 When stop condition is generated (when SPIEn = 1) restart condition When data is at low level while attempting to generate a stop At falling edge of eighth or ninth clock following byte transfer Note 1 condition When SCLAn is at low level while attempting to generate a restart condition Notes 1. When the WTIMn bit (bit 3 of IICA control register n0 (IICCTLn0)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIMn = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. When there is a chance that arbitration will occur, set SPIEn = 1 for master device operation. Remarks 1. 2. SPIEn: Bit 4 of IICA control register n0 (IICCTLn0) n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 724 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.13 Wakeup function The I2C bus slave function is a function that generates an interrupt request signal (INTIICAn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICAn signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. <R> To use the wakeup function in the STOP mode, set the WUPn bit to 1. Addresses can be received regardless of the operation clock. An interrupt request signal (INTIICAn) is also generated when a local address and extension code have been received. Operation returns to normal operation by using an instruction to clear (0) the WUPn bit after this interrupt has been generated. Figure 13-22 shows the flow for setting WUPn = 1 and Figure 13-23 shows the flow for setting WUPn = 0 upon an address match. Figure 13-22. Flow When Setting WUPn = 1 START MSTSn = STDn = EXCn = COIn =0? No Yes WUPn = 1 Wait Waits for 3 clocks. STOP instruction execution Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 725 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-23. Flow When Setting WUPn = 0 upon Address Match (Including Extension Code Reception) STOP mode state No INTIICAn = 1? Yes WUPn = 0 Wait Waits for 5 clocks. Reading IICSn Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA. Use the following flows to perform the processing to release the STOP mode other than by an interrupt request (INTIICAn) generated from serial interface IICA. * Master device operation: Flow shown in Figure 13-24 * Slave device operation: Same as the flow in Figure 13-23 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 726 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICAn START SPIEn = 1 WUPn = 1 STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICAn. WUPn = 0 No INTIICAn = 1? Yes Wait Generates a STOP condition or selects as a slave device. Waits for 5 clocks. Reading IICSn Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 727 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.14 Communication reservation (1) When communication reservation function is enabled (bit n (IICRSVn) of IICA flag register n (IICFn) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released by setting bit 6 (LRELn) of IICA control register n0 (IICCTLn0) to 1 and saving communication). If bit 1 (STTn) of the IICCTLn0 register is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. If an address is written to the IICA shift register n (IICAn) after bit 4 (SPIEn) of the IICCTLn0 register was set to 1, and it was detected by generation of an interrupt request signal (INTIICAn) that the bus was released (detection of the stop condition), then the device automatically starts communication as the master. Data written to the IICAn register before the stop condition is detected is invalid. When the STTn bit has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. * If the bus has been released ........................................ a start condition is generated * If the bus has not been released (standby mode)......... communication reservation Check whether the communication reservation operates or not by using the MSTSn bit (bit 7 of the IICA status register n (IICSn)) after the STTn bit is set to 1 and the wait time elapses. Use software to secure the wait time calculated by the following expression. Wait time from setting STTn = 1 to checking the MSTSn flag: (IICWLn setting value + IICWHn setting value + 4) + tF x 2 x fCLK [clocks] Remarks 1. 2. IICWLn: IICA low-level width setting register n IICWHn: IICA high-level width setting register n tF: SDAAn and SCLAn signal falling times fCLK: CPU/peripheral hardware clock frequency n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 728 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-25 shows the communication reservation timing. Figure 13-25. Communication Reservation Timing Program processing Write to IICAn STTn = 1 CommuniHardware processing cation reservation SCLAn 1 2 3 4 Set SPDn and INTIICAn 5 6 7 8 9 Set STDn 1 2 3 4 5 6 SDAAn Generate by master device with bus mastership Remark IICAn: IICA shift register n STTn: Bit 1 of IICA control register n0 (IICCTLn0) STDn: Bit 1 of IICA status register n (IICSn) SPDn: Bit 0 of IICA status register n (IICSn) Communication reservations are accepted via the timing shown in Figure 13-26. After bit 1 (STDn) of the IICA status register n (IICSn) is set to 1, a communication reservation can be made by setting bit 1 (STTn) of IICA control register n0 (IICCTLn0) to 1 before a stop condition is detected. Figure 13-26. Timing for Accepting Communication Reservations SCLAn SDAAn STDn SPDn Standby mode (Communication can be reserved by setting STTn to 1 during this period.) Figure 13-27 shows the communication reservation protocol. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 729 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-27. Communication Reservation Protocol DI SET1 STTn Define communication reservation Wait (Communication reservation)Note 2 Yes MSTSn = 0? Sets STTn flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait timeNote 1 by software. Confirmation of communication reservation No (Generate start condition) Cancel communication reservation MOV IICAn, #xxH Clear user flag IICAn write operation EI Notes 1. The wait time is calculated as follows. (IICWLn setting value + IICWHn setting value + 4) + tF x 2 x fCLK [clocks] 2. The communication reservation operation executes a write to the IICA shift register n (IICAn) when a stop condition interrupt request occurs. Remarks 1. STTn: Bit 1 of IICA control register n0 (IICCTLn0) MSTSn: Bit 7 of IICA status register n (IICSn) IICAn: IICA shift register n IICWLn: IICA low-level width setting register n IICWHn: IICA high-level width setting register n tF: SDAAn and SCLAn signal falling times fCLK: CPU/peripheral hardware clock frequency 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 730 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1) When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released by setting bit 6 (LRELn) of the IICCTLn0 register to 1 and saving communication) To confirm whether the start condition was generated or request was rejected, check STCFn (bit 7 of the IICFn register). It takes up to 5 clocks until the STCFn bit is set to 1 after setting STTn = 1. Therefore, secure the time by software. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 731 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.15 Cautions (1) When STCENn = 0 Immediately after I2C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. <1> Set IICA control register n1 (IICCTLn1). <2> Set bit 7 (IICEn) of IICA control register n0 (IICCTLn0) to 1. <3> Set bit 0 (SPTn) of the IICCTLn0 register to 1. (2) When STCENn = 1 Immediately after I2C operation is enabled (IICEn = 1), the bus released status (IICBSYn = 0) is recognized regardless of the actual bus status. To generate the first start condition (STTn = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) If other I2C communications are already in progress If I2C operation is enabled and the device participates in communication already in progress when the SDAAn pin is 2 low and the SCLAn pin is high, the macro of I C recognizes that the SDAAn pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this interferes with other I2C communications. To avoid this, start I2C in the following sequence. <1> Clear bit 4 (SPIEn) of the IICCTLn0 register to 0 to disable generation of an interrupt request signal (INTIICAn) when the stop condition is detected. <2> Set bit 7 (IICEn) of the IICCTLn0 register to 1 to enable the operation of I2C. <3> Wait for detection of the start condition. <4> Set bit 6 (LRELn) of the IICCTLn0 register to 1 before ACK is returned (4 to 80 clocks after setting the IICEn bit to 1), to forcibly disable detection. (4) Setting the STTn and SPTn bits (bits 1 and 0 of the IICCTLn0 register) again after they are set and before they are cleared to 0 is prohibited. (5) When transmission is reserved, set the SPIEn bit (bit 4 of the IICCTLn0 register) to 1 so that an interrupt request is generated when the stop condition is detected. Transfer is started when communication data is written to the IICA shift register n (IICAn) after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set the SPIEn bit to 1 when the MSTSn bit (bit 7 of the IICA status register n (IICSn)) is detected by software. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 732 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the RL78/G13 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup. If communication with the slave is required, prepare the communication and then execute communication processing. (2) Master operation in multimaster system In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a certain period (1 frame), the RL78/G13 takes part in a communication with bus released state. This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the RL78/G13 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave. The actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) Slave operation An example of when the RL78/G13 is used as the I2C bus slave is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the INTIICAn interrupt occurrence (communication waiting). When an INTIICAn interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. By checking the flags, necessary communication processing is performed. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 733 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 13-28. Master Operation in Single-Master System START Initializing I2C busNote Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 13.3 (8) Port mode register 6 (PM6)). Setting port IICWLn, IICWHn XXH Sets a transfer clock. SVAn XXH Sets a local address. IICFn 0XH Setting STCENn, IICRSVn = 0 Sets a start condition. <R> Initial setting Setting IICCTLn1 IICCTLn0 0XX111XXB ACKEn = WTIMn = SPIEn = 1 IICCTLn0 1XX111XXB IICEn = 1 2 Set the port from input mode to output mode and enable the output of the I C bus (see 13.3 (8) Port mode register 6 (PM6)). Setting port STCENn = 1? Yes No SPTn = 1 INTIICAn interrupt occurs? Prepares for starting communication (generates a stop condition). No Waits for detection of the stop condition. Yes STTn = 1 Prepares for starting communication (generates a start condition). Writing IICAn Starts communication (specifies an address and transfer direction). INTIICAn interrupt occurs? No Waits for detection of acknowledge. Yes No ACKDn = 1? Yes TRCn = 1? No ACKEn = 1 WTIMn = 0 Communication processing Yes Writing IICAn Starts transmission. WRELn = 1 INTIICAn interrupt occurs? No Waits for data transmission. INTIICAn interrupt occurs? Yes Yes ACKDn = 1? No Starts reception. No Waits for data reception. Reading IICAn Yes No End of transfer? No End of transfer? Yes Yes Restart? Yes ACKEn = 0 WTIMn = WRELn = 1 No SPTn = 1 INTIICAn interrupt occurs? Yes No Waits for detection of acknowledge. END Note Release (SCLAn and SDAAn pins = high level) the I2C bus in conformance with the specifications of the product that is communicating. If EEPROM is outputting a low level to the SDAAn pin, for example, set the SCLAn pin in the output port mode, and output a clock pulse from the output port until the SDAAn pin is constantly at high level. Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 734 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 13-29. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 13.3 (8) Port mode register 6 (PM6)). Setting port IICWLn, IICWHn XXH <R> Selects a transfer clock. SVAn XXH Sets a local address. IICFn 0XH Setting STCENn and IICRSVn Sets a start condition. Setting IICCTLn1 IICCTLn0 0XX111XXB ACKEn = WTIMn = SPIEn = 1 Initial setting IICCTLn0 1XX111XXB IICEn = 1 2 Set the port from input mode to output mode and enable the output of the I C bus (see 13.3 (8) Port mode register 6 (PM6)). Setting port Checking bus statusNote Releases the bus for a specific period. Bus status is being checked. No No STCENn = 1? INTIICAn interrupt occurs? Prepares for starting communication (generates a stop condition). SPTn = 1 Yes Yes SPDn = 1? INTIICAn interrupt occurs? No Yes Yes Slave operation SPDn = 1? No Waits for detection of the stop condition. No Yes 1 Waits for a communication Slave operation * Waiting to be specified as a slave by other master * Waiting for a communication start request (depends on user program) Master operation starts? No (No communication start request) Yes (Communication start request) SPIEn = 0 INTIICAn interrupt occurs? SPIEn = 1 No Waits for a communication request. Yes IICRSVn = 0? No Slave operation Yes A B Enables reserving Disables reserving communication. communication. Note Confirm that the bus is released (CLDn bit = 1, DADn bit = 1) for a specific period (for example, for a period of one frame). If the SDAAn pin is constantly at low level, decide whether to release the I2C bus (SCLAn and SDAAn pins = high level) in conformance with the specifications of the product that is communicating. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 735 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (2/3) A Enables reserving communication. STTn = 1 Secure wait timeNote by software. Wait Communication processing Prepares for starting communication (generates a start condition). MSTSn = 1? No Yes INTIICAn interrupt occurs? No Waits for bus release (communication being reserved). Yes No Wait state after stop condition was detected and start condition was generated by the communication reservation function. EXCn = 1 or COIn =1? Yes C Slave operation B Disables reserving communication. IICBSYn = 0? No Yes D Communication processing STTn = 1 Prepares for starting communication (generates a start condition). WaitNote STCFn = 0? No Yes INTIICAn interrupt occurs? No Waits for bus release Yes C EXCn = 1 or COIn =1? No Detects a stop condition. Yes Slave operation D Note The wait time is calculated as follows. (IICWLn setting value + IICWHn setting value + 4) x fCLK + tF x 2 [clocks] Remarks 1. IICWLn: IICA low-level width setting register n IICWHn: IICA high-level width setting register n 2. tF: SDAAn and SCLAn signal falling times fCLK: CPU/peripheral hardware clock frequency n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 736 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (3/3) C Writing IICAn INTIICAn interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTSn = 1? No Yes No 2 ACKDn = 1? Yes TRCn = 1? No ACKEn = 1 WTIMn = 0 Yes Communication processing WTIMn = 1 WRELn = 1 Writing IICAn Starts transmission. INTIICAn interrupt occurs? INTIICAn interrupt occurs? No Waits for data transmission. Yes MSTSn = 1? No Waits for data reception. Yes MSTSn = 1? No No Yes Yes ACKDn = 1? Starts reception. 2 2 Reading IICAn No Transfer end? No Yes Yes No WTIMn = WRELn = 1 ACKEn = 00 Transfer end? Yes Restart? INTIICAn interrupt occurs? No No Waits for detection of ACK. Yes SPTn = 1 Yes MSTSn = 1? STTn = 1 END Yes No 2 Communication processing C 2 EXCn = 1 or COIn = 1? Yes Slave operation Remarks 1. 2. 3. 4. No 1 Does not participate in communication. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. To use the device as a master in a multi-master system, read the MSTSn bit each time interrupt INTIICAn has occurred to check the arbitration result. To use the device as a slave in a multi-master system, check the status by using the IICA status register n (IICSn) and IICA flag register n (IICFn) each time interrupt INTIICAn has occurred, and determine the processing to be performed next. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 737 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication. It is also assumed that the INTIICAn interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. INTIICAn Flag Interrupt servicing Setting Main processing IICA Data Setting Therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of INTIICAn. <1> Communication mode flag This flag indicates the following two communication statuses. * Clear mode: Status in which data communication is not performed * Communication mode: Status in which data communication is performed (from valid address detection to stop condition detection, no detection of ACK from master, address mismatch) <2> Ready flag This flag indicates that data communication is enabled. Its function is the same as the INTIICAn interrupt for ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> Communication direction flag This flag indicates the direction of communication. Its value is the same as the TRCn bit. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 738 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the master, communication is completed. For reception, the necessary amount of data is received. When communication is completed, ACK is not returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the communication status occurs in this way. Figure 13-30. Slave Operation Flowchart (1) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 13.3 (8) Port mode register 6 (PM6)). Setting port IICWLn, IICWHn XXH Selects a transfer clock. Initial setting SVAn XXH Sets a local address. IICFn 0XH Sets a start condition. Setting IICRSVn <R> Setting IICCTLn1 IICCTLn0 0XX011XXB ACKEn = WTIMn = 1, SPIn = 0 IICCTLn0 1XX011XXB IICEn = 1 Set the port from input mode to output mode and enable the output of the I2C bus (see 13.3 (8) Port mode register 6 (PM6)). Setting port No Communication mode flag = 1? Yes Communication direction flag = 1? No Yes WRELn = 1 Writing IICAn Communication mode flag = 1? Communication processing No Communication mode flag = 1? No Yes Yes No Starts reception. Starts transmission. Communication direction flag = 1? Communication direction flag = 1? No Yes No Yes No Ready flag = 1? Ready flag = 1? Yes Yes Reading IICAn Clearing ready flag Yes Clearing ready flag ACKDn = 1? No Clearing communication mode flag WRELn = 1 Remarks 1. Conform to the specifications of the product that is in communication, regarding the transmission and reception formats. 2.. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 739 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus remaining in the wait state. Remark <1> to <3> above correspond to <1> to <3> in Figure 13-31 Slave Operation Flowchart (2). Figure 13-31. Slave Operation Flowchart (2) INTIICAn generated Yes <1> Yes <2> SPDn = 1? No STDn = 1? No No <3> COIn = 1? Yes Set ready flag Communication direction flag TRCn Set communication mode flag Clear ready flag Clear communication direction flag, ready flag, and communication mode flag Interrupt servicing completed 13.5.17 Timing of I2C interrupt request (INTIICAn) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIICAn, and the value of the IICA status register n (IICSn) when the INTIICAn signal is generated are shown below. Remarks 1. 2. ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK: Acknowledge D7 to D0: Data SP: Stop condition n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 740 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIMn = 0 SPTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICSn = 1000x110B 2: IICSn = 1000x000B 3: IICSn = 1000x000B (Sets the WTIMn bit to 1)Note 4: IICSn = 1000xx00B (Sets the SPTn bit to 1)Note 5: IICSn = 00000001B Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 SPTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICSn = 1000x110B 2: IICSn = 1000x100B 3: IICSn = 1000xx00B (Sets the SPTn bit to 1) 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 741 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIMn = 0 STTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPTn = 1 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICSn = 1000x110B 2: IICSn = 1000x000B (Sets the WTIMn bit to 1)Note 1 3: IICSn = 1000xx00B (Clears the WTIMn bit to 0Note 2, sets the STTn bit to 1) 4: IICSn = 1000x110B 5: IICSn = 1000x000B (Sets the WTIMn bit to 1)Note 3 6: IICSn = 1000xx00B (Sets the SPTn bit to 1) 7: IICSn = 00000001B Notes 1. To generate a start condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. 2. Clear the WTIMn bit to 0 to restore the original setting. 3. To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 STTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 SPTn = 1 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICSn = 1000x110B 2: IICSn = 1000xx00B (Sets the STTn bit to 1) 3: IICSn = 1000x110B 4: IICSn = 1000xx00B (Sets the SPTn bit to 1) 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 742 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIMn = 0 SPTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICSn = 1010x110B 2: IICSn = 1010x000B 3: IICSn = 1010x000B (Sets the WTIMn bit to 1)Note 4: IICSn = 1010xx00B (Sets the SPTn bit to 1) 5: IICSn = 00000001B Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal. Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 SPTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICSn = 1010x110B 2: IICSn = 1010x100B 3: IICSn = 1010xx00B (Sets the SPTn bit to 1) 4: IICSn = 00001001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 743 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIMn = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICSn = 0001x110B 2: IICSn = 0001x000B 3: IICSn = 0001x000B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICSn = 0001x110B 2: IICSn = 0001x100B 3: IICSn = 0001xx00B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 744 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches with SVAn) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICSn = 0001x110B 2: IICSn = 0001x000B 3: IICSn = 0001x110B 4: IICSn = 0001x000B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 (after restart, matches with SVAn) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICSn = 0001x110B 2: IICSn = 0001xx00B 3: IICSn = 0001x110B 4: IICSn = 0001xx00B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 745 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICSn = 0001x110B 2: IICSn = 0001x000B 3: IICSn = 0010x010B 4: IICSn = 0010x000B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 4 ACK SP 5 6 1: IICSn = 0001x110B 2: IICSn = 0001xx00B 3: IICSn = 0010x010B 4: IICSn = 0010x110B 5: IICSn = 0010xx00B 6: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 746 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICSn = 0001x110B 2: IICSn = 0001x000B <R> 3: IICSn = 00000x10B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 1: IICSn = 0001x110B 2: IICSn = 0001xx00B <R> 3: IICSn = 00000x10B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 747 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIMn = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICSn = 0010x010B 2: IICSn = 0010x000B 3: IICSn = 0010x000B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 5 1: IICSn = 0010x010B 2: IICSn = 0010x110B 3: IICSn = 0010x100B 4: IICSn = 0010xx00B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 748 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches SVAn) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICSn = 0010x010B 2: IICSn = 0010x000B 3: IICSn = 0001x110B 4: IICSn = 0001x000B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 (after restart, matches SVAn) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 1: IICSn = 0010x010B 2: IICSn = 0010x110B 3: IICSn = 0010xx00B 4: IICSn = 0001x110B 5: IICSn = 0001xx00B 6: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 749 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICSn = 0010x010B 2: IICSn = 0010x000B 3: IICSn = 0010x010B 4: IICSn = 0010x000B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK 4 D7 to D0 5 ACK SP 6 7 1: IICSn = 0010x010B 2: IICSn = 0010x110B 3: IICSn = 0010xx00B 4: IICSn = 0010x010B 5: IICSn = 0010x110B 6: IICSn = 0010xx00B 7: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 750 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 <R> 1: IICSn = 0010x010B <R> 2: IICSn = 0010x000B <R> 3: IICSn = 00000x10B ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 <R> 1: IICSn = 0010x010B <R> 2: IICSn = 0010x110B <R> 3: IICSn = 0010xx00B <R> 4: IICSn = 00000x10B D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 751 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICSn = 00000001B Remark : Generated only when SPIEn = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (i) When WTIMn = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICSn = 0101x110B 2: IICSn = 0001x000B 3: IICSn = 0001x000B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 752 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIMn = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICSn = 0101x110B 2: IICSn = 0001x100B 3: IICSn = 0001xx00B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (b) When arbitration loss occurs during transmission of extension code (i) When WTIMn = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICSn = 0110x010B 2: IICSn = 0010x000B 3: IICSn = 0010x000B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 753 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIMn = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICSn = 0110x010B 2: IICSn = 0010x110B 3: IICSn = 0010x100B 4: IICSn = 0010xx00B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (when WTIMn = 1) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 ACK SP 2 1: IICSn = 01000110B 2: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 754 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICSn = 0110x010B Sets LRELn = 1 by software 2: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (c) When arbitration loss occurs during transmission of data (i) When WTIMn = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK SP 3 1: IICSn = 10001110B 2: IICSn = 01000000B 3: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 755 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIMn = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICSn = 10001110B 2: IICSn = 01000100B 3: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVAn) ST AD6 to AD0 R/W ACK D7 to Dm ST 1 AD6 to AD0 R/W ACK D7 to D0 2 ACK SP 3 1: IICSn = 1000x110B 2: IICSn = 01000110B 3: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care m = 6 to 0 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 756 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dm ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK SP 3 1: IICSn = 1000x110B 2: IICSn = 01100010B Sets LRELn = 1 by software 3: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care m = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dm SP 1 2 1: IICSn = 10000110B 2: IICSn = 01000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care m = 6 to 0 Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 757 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICSn = 1000x110B 2: IICSn = 1000x000B (Sets the WTIMn bit to 1) 3: IICSn = 1000x100B (Clears the WTIMn bit to 0) 4: IICSn = 01000000B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 STTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICSn = 1000x110B 2: IICSn = 1000x100B (Sets the STTn bit to 1) 3: IICSn = 01000100B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 758 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICSn = 1000x110B 2: IICSn = 1000x000B (Sets the WTIMn bit to 1) 3: IICSn = 1000xx00B (Sets the STTn bit to 1) 4: IICSn = 01000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 STTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK SP 2 3 1: IICSn = 1000x110B 2: IICSn = 1000xx00B (Sets the STTn bit to 1) 3: IICSn = 01000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 759 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIMn = 0 SPTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICSn = 1000x110B 2: IICSn = 1000x000B (Sets the WTIMn bit to 1) 3: IICSn = 1000x100B (Clears the WTIMn bit to 0) 4: IICSn = 01000100B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care (ii) When WTIMn = 1 SPTn = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICSn = 1000x110B 2: IICSn = 1000x100B (Sets the SPTn bit to 1) 3: IICSn = 01000100B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 x: Don't care Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 760 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA 13.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device. Figures 13-32 and 13-33 show timing charts of the data communication. The IICA shift register n (IICAn)'s shift operation is synchronized with the falling edge of the serial clock (SCLAn). The transmit data is transferred to the SO latch and is output (MSB first) via the SDAAn pin. Data input via the SDAAn pin is captured into IICAn at the rising edge of SCLAn. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 761 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICAn <2> <5> ACKDn (ACK detection) WTIMn (8 or 9 clock wait) H ACKEn (ACK control) H MSTSn (communication status) STTn (ST trigger) SPTn (SP trigger) WRELn (wait cancellation) <1> L L INTIICAn (interrupt) TRCn (transmit/receive) Start condition Bus line SCLAn (bus) (clock line) Note 2 SDAAn (bus) (data line) <4> AD6 AD5 AD4 AD3 AD2 Slave address AD1 AD0 W D17 ACK <3> Slave side IICAn ACKDn (ACK detection) STDn (ST detection) SPDn (SP detection) WTIMn (8 or 9 clock wait) H ACKEn (ACK control) H MSTSn (communication status) L WRELn (wait cancellation) <6> Note 3 INTIICAn (interrupt) TRCn (transmit/receive) L : Wait state by slave device : Wait state by master and slave devices Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master device. 2. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 762 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 13-32 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn). When the start condition is subsequently detected, the master device enters the master device communication status (MSTSn = 1). The master device is ready to communicate once the bus clock line goes low (SCLAn = 0) after the hold time has elapsed. <2> The master device writes the address + W (transmission) to the IICA shift register n (IICAn) and transmits the slave address. <3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLAn = 0) and issues an interrupt (INTIICAn: address match)Note. <5> The master device writes the data to transmit to the IICAn register and releases the wait status that it set by the master device. <6> If the slave device releases the wait status (WRELn = 1), the master device starts transferring data to the slave device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remarks 1. <1> to <15> in Figure 13-32 represent the entire procedure for communicating data using the I2C bus. Figure 13-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 1332 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 13-32 (3) Data ~ data ~ stop condition shows the processing from <7> to <15>. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 763 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4) (2) Address ~ data ~ data Master side IICAn Note 1 Note 1 <5> <9> ACKDn (ACK detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) H H MSTSn (communication status) H STTn (ST trigger) SPTn (SP trigger) WRELn (wait cancellation) L L L INTIICAn (interrupt) TRCn (transmit/receive) H Bus line SCLAn (bus) (clock line) <4> SDAAn (bus) (data line) <8> W ACK D 17 D16 D 15 <3> D14 D 13 D12 D 11 D 10 <7> D 27 ACK Slave side IICAn ACKDn (ACK detection) STDn (ST detection) SPDn (SP detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) L H H MSTSn (communication status) L WRELn (wait cancellation) <6> Note 2 <10> Note 2 INTIICAn (interrupt) TRCn (transmit/receive) L : Wait state by slave device : Wait state by master and slave devices Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master device. 2. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 764 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 13-32 are explained below. <3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLAn = 0) and issues an interrupt (INTIICAn: address match)Note. <5> The master device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait status that it set by the master device. <6> If the slave device releases the wait status (WRELn = 1), the master device starts transferring data to the slave device. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <8> The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <9> The master device writes the data to transmit to the IICAn register and releases the wait status that it set by the master device. <10> The slave device reads the received data and releases the wait status (WRELn = 1). The master device then starts transferring data to the slave device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remarks 1. <1> to <15> in Figure 13-32 represent the entire procedure for communicating data using the I2C bus. Figure 13-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 1332 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 13-32 (3) Data ~ data ~ stop condition shows the processing from <7> to <15>. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 765 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4) (3) Data ~ data ~ Stop condition Master side Note 1 IICAn <9> ACKDn (ACK detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) H H MSTSn (communication status) STTn (ST trigger) L SPTn (SP trigger) <14> WRELn (wait cancellation) L INTIICAn (interrupt) TRCn (transmit/receive) Stop condition Bus line SCLAn (bus) (clock line) <8> SDAAn (bus) (data line) D150 ACK <7> <12> D167 D166 D165 D164 D163 D162 D161 D160 ACK <11> Slave side Note 2 <15> IICAn ACKDn (ACK detection) STDn (ST detection) L SPDn (SP detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) H H MSTSn (communication status) L WRELn (wait cancellation) <10> Note 3 <13> Note 3 INTIICAn (interrupt) TRCn (transmit/receive) L : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a master device. 2. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 766 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 13-32 are explained below. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <8> The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <9> The master device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait status that it set by the master device. <10> The slave device reads the received data and releases the wait status (WRELn = 1). The master device then starts transferring data to the slave device. <11> When data transfer is complete, the slave device (ACKEn =1) sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <12> The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <13> The slave device reads the received data and releases the wait status (WRELn = 1). <14> By the master device setting a stop condition trigger (SPTn = 1), the bus data line is cleared (SDAAn = 0) and the bus clock line is set (SCLAn = 1). After the stop condition setup time has elapsed, by setting the bus data line (SDAAn = 1), the stop condition is then generated (i.e. SCLAn =1 changes SDAAn from 0 to 1). <15> When a stop condition is generated, the slave device detects the stop condition and issues an interrupt (INTIICAn: stop condition). Remarks 1. <1> to <15> in Figure 13-32 represent the entire procedure for communicating data using the I2C bus. Figure 13-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 1332 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 13-32 (3) Data ~ data ~ stop condition shows the processing from <7> to <15>. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 767 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4) (4) Data ~ restart condition ~ address Master side IICAn <iii> ACKDn (ACK detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) H H MSTSn (communication status) H STTn (ST trigger) <ii> SPTn (SP trigger) L WRELn (wait cancellation) L INTIICAn (interrupt) TRCn (transmit/receive) H Bus line Restart condition SCLAn (bus) (clock line) <8> SDAAn (bus) (data line) D13 D12 D11 D10 ACK <7> AD6 Note 1 Slave side AD5 AD4 AD3 AD2 AD1 Slave address IICAn ACKDn (ACK detection) STDn (ST detection) SPDn (SP detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) L H H MSTSn (communication status) L WRELn (wait cancellation) <i> Note 2 INTIICAn (interrupt) TRCn (transmit/receive) L : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. Make sure that the time between the rise of the SCLAn pin signal and the generation of the start condition after a restart condition has been issued is at least 4.7 s when specifying standard mode and at least 0.6 s when specifying fast mode. 2. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 768 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The following describes the operations in Figure 13-32 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the processing to step <iii>, the data transmission step. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <8> The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <i> <ii> The slave device reads the received data and releases the wait status (WRELn = 1). The start condition trigger is set again by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 changes SDAAn from 1 to 0) is generated once the bus clock line goes high (SCLAn = 1) and the bus data line goes low (SDAAn = 0) after the restart condition setup time has elapsed. When the start condition is subsequently detected, the master device is ready to communicate once the bus clock line goes low (SCLAn = 0) after the hold time has elapsed. <iii> The master device writing the address + R/W (transmission) to the IICA shift register (IICAn) enables the slave address to be transmitted. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 769 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICAn <2> ACKDn (ACK detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) <5> H MSTSn (communication status) STTn (ST trigger) <1> SPTn (SP trigger) L WRELn (wait cancellation) <7> Note 1 INTIICAn (interrupt) TRCn (transmit/receive) Start condition Bus line SCLAn (bus) (clock line) Note 2 SDAAn (bus) (data line) <4> AD6 AD5 AD4 AD3 AD2 Slave address AD1 AD0 R <3> ACK D17 Slave side Note 3 IICAn <6> ACKDn (ACK detection) STDn (ST detection) SPDn (SP detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) H H MSTSn (communication status) L WRELn (wait cancellation) L INTIICAn (interrupt) TRCn (transmit/receive) : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. For releasing wait state during reception of a master device, write "FFH" to IICAn or set the WRELn bit. 2. Make sure that the time between the fall of the SDAAn pin signal and the fall of the SCLAn pin signal is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a slave device. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 770 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 13-33 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn). When the start condition is subsequently detected, the master device enters the master device communication status (MSTSn = 1). The master device is ready to communicate once the bus clock line goes low (SCLAn = 0) after the hold time has elapsed. <2> The master device writes the address + R (reception) to the IICA shift register n (IICAn) and transmits the slave address. <3> In the slave device if the address received matches the address (SVAn value) of a slave device Note, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLAn = 0) and issues an interrupt (INTIICAn: address match) Note. <5> The timing at which the master device sets the wait status changes to the 8th clock (WTIMn = 0). <6> The slave device writes the data to transmit to the IICAn register and releases the wait status that it set by the slave device. <7> The master device releases the wait status (WRELn = 1) and starts transferring data from the slave device to the master device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remarks 1. <1> to <19> in Figure 13-33 represent the entire procedure for communicating data using the I2C bus. Figure 13-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 1333 (2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 13-33 (3) Data ~ data ~ stop condition shows the processing from <8> to <19>. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 771 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Address ~ data ~ data Master side IICAn ACKDn (ACK detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) <5> H MSTSn (communication status) H STTn (ST trigger) L SPTn (SP trigger) L WRELn (wait cancellation) Note 1 Note 1 <7> INTIICAn (interrupt) TRCn (transmit/receive) <9> L Bus line SCLAn (bus) (clock line) <4> SDAAn (bus) (data line) <11> <8> R ACK <3> D17 D16 D15 D14 D13 D12 D11 D10 ACK D27 <10> Slave side IICAn <6> ACKDn (ACK detection) Note 2 <12> Note 2 STDn (ST detection) SPDn (SP detection) L WTIMn (8 or 9 clock wait) ACKEn (ACK control) H H MSTSn (communication status) L WRELn (wait cancellation) L INTIICAn (interrupt) TRCn (transmit/receive) H : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. For releasing wait state during reception of a master device, write "FFH" to IICAn or set the WRELn bit. 2. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a slave device. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 772 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 13-33 are explained below. <3> In the slave device if the address received matches the address (SVAn value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKDn = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICAn: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLAn = 0) and issues an interrupt (INTIICAn: address match) Note. <5> The master device changes the timing of the wait status to the 8th clock (WTIMn = 0). <6> The slave device writes the data to transmit to the IICA shift register n (IICAn) and releases the wait status that it set by the slave device. <7> The master device releases the wait status (WRELn = 1) and starts transferring data from the slave device to the master device. <8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICAn: end of transfer). Because of ACKEn = 1 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the wait status (WRELn = 1). <10> The ACK is detected by the slave device (ACKDn = 1) at the rising edge of the 9th clock. <11> The slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and the slave device issue an interrupt (INTIICAn: end of transfer). <12> By the slave device writing the data to transmit to the IICAn register, the wait status set by the slave device is released. The slave device then starts transferring data to the master device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAAn = 1). The slave device also does not issue the INTIICAn interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICAn interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remarks 1. <1> to <19> in Figure 13-33 represent the entire procedure for communicating data using the I2C bus. Figure 13-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 1333 (2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 13-33 (3) Data ~ data ~ stop condition shows the processing from <8> to <19>. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 773 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33. Example of Slave to Master Communication (8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition Master side IICAn ACKDn (ACK detection) WTIMn (8 or 9 clock wait) <14> ACKEn (ACK control) MSTSn (communication status) STTn (ST trigger) L SPTn (SP trigger) WRELn (wait cancellation) <15> <9> INTIICAn (interrupt) TRCn (transmit/receive) <17> Note 1 Note 1 L Bus line Stop conditon SCLAn (bus) (clock line) <8> SDAAn (bus) (data line) D150 <13> <11> ACK D167 D166 D165 D164 D163 D162 D161 D160 <16> Note 2 NACK <10> Slave side <19> IICAn <12> Note 3 ACKDn (ACK detection) STDn (ST detection) L SPDn (SP detection) WTIMn (8 or 9 clock wait) ACKEn (ACK control) H H MSTSn (communication status) WRELn (wait cancellation) L <18> Notes 1, 4 INTIICAn (interrupt) TRCn (transmit/receive) Note 4 : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. To cancel a wait state, write "FFH" to IICAn or set the WRELn bit. 2. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a slave device. 4. If a wait state during transmission by a slave device is canceled by setting the WRELn bit, the TRCn bit will be cleared. Remark n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 774 RL78/G13 CHAPTER 13 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 13-33 are explained below. <8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICAn: end of transfer). Because of ACKEn = 0 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the wait status (WRELn = 1). <10> The ACK is detected by the slave device (ACKDn = 1) at the rising edge of the 9th clock. <11> The slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and the slave device issue an interrupt (INTIICAn: end of transfer). <12> By the slave device writing the data to transmit to the IICA register, the wait status set by the slave device is released. The slave device then starts transferring data to the master device. <13> The master device issues an interrupt (INTIICAn: end of transfer) at the falling edge of the 8th clock, and sets a wait status (SCLAn = 0). Because ACK control (ACKEn = 1) is performed, the bus data line is at the low level (SDAAn = 0) at this stage. <14> The master device sets NACK as the response (ACKEn = 0) and changes the timing at which it sets the wait status to the 9th clock (WTIMn = 1). <15> If the master device releases the wait status (WRELn = 1), the slave device detects the NACK (ACK = 0) at the rising edge of the 9th clock. <16> The master device and slave device set a wait status (SCLAn = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICAn: end of transfer). <17> When the master device issues a stop condition (SPTn = 1), the bus data line is cleared (SDAAn = 0) and the master device releases the wait status. The master device then waits until the bus clock line is set (SCLAn = 1). <18> The slave device acknowledges the NACK, halts transmission, and releases the wait status (WRELn = 1) to end communication. Once the slave device releases the wait status, the bus clock line is set (SCLAn = 1). <19> Once the master device recognizes that the bus clock line is set (SCLAn = 1) and after the stop condition setup time has elapsed, the master device sets the bus data line (SDAAn = 1) and issues a stop condition (i.e. SCLAn =1 changes SDAAn from 0 to 1). The slave device detects the generated stop condition and slave device issue an interrupt (INTIICAn: stop condition). Remarks 1. <1> to <19> in Figure 13-33 represent the entire procedure for communicating data using the I2C bus. Figure 13-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 1333 (2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 13-33 (3) Data ~ data ~ stop condition shows the processing from <8> to <19>. 2. n = 0, 1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 775 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. * 16 bits x 16 bits = 32 bits (Unsigned) * 16 bits x 16 bits = 32 bits (Signed) * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (Signed) * 32 bits / 32 bits = 32 bits, 32-bits remainder (Unsigned) 14.2 Configuration of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator consists of the following hardware. Table 14-1. Configuration of Multiplier and Divider/Multiply-Accumulator Item Registers Configuration Multiplication/division data register A (L) (MDAL) Multiplication/division data register A (H) (MDAH) Multiplication/division data register B (L) (MDBL) Multiplication/division data register B (H) (MDBH) Multiplication/division data register C (L) (MDCL) Multiplication/division data register C (H) (MDCH) Control register Multiplication/division control register (MDUC) Figure 14-1 shows a block diagram of the multiplier and divider/multiply-accumulator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 776 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator <R> Internal bus Multiplyaccumulation result (accumulated) Multiplication result (product) or multiplication result (product) while in multiply-accumulator mode Multiplication/division data register B MDBH Division result (remainder) Multiplication/division data register C MDCH MDBL MDCL Multiplication/division control register (MDUC) Division result (quotient) Multiplication/division data register A MDAH DIVMODE MACMODE MDSM MACOF MACSF MDAL DIVST Start INTMD Multiplicand Divisor Multiplier Dividend Clear Controller Controller Counter fPRS Multiplication/division block Addition block Controller Data flow during division Data flow during multiplication and multiply-accumulation R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 777 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR (1) Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator mode, and set the dividend data in the division mode. Furthermore, the operation result (quotient) is stored in the MDAH and MDAL registers in the division mode. The MDAH and MDAL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 14-2. Format of Multiplication/Division Data Register A (MDAH, MDAL) Address: FFFF0H, FFFF1H, FFFF2H, FFFF3H Symbol MDAH FFFF3H FFFF2H MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH 15 14 13 12 11 10 9 8 7 6 5 FFFF1H Symbol MDAL After reset: 0000H, 0000H R/W 4 3 2 1 0 FFFF0H MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cautions 1. Do not rewrite the MDAH and MDAL registers values during division operation processing (when the multiplication/division control register (MDUC) value is 81H or C1H). The operation will be executed in this case, but the operation result will be an undefined value. 2. The MDAH and MDAL registers values read during division operation processing (when the MDUC register value is 81H or C1H) will not be guaranteed. 3. The data is in the two's complement format in either the multiplication mode (signed) or multiply-accumulator mode (signed). The following table shows the functions of the MDAH and MDAL registers during operation execution. Table 14-2. Functions of MDAH and MDAL Registers During Operation Execution Operation Mode Setting Multiplication mode (unsigned) MDAH: Multiplier (unsigned) Multiply-accumulator mode (unsigned) MDAL: Multiplicand (unsigned) Multiplication mode (signed) MDAH: Multiplier (signed) Multiply-accumulator mode (signed) MDAL: Multiplicand (signed) Division mode (unsigned) MDAH: Dividend (unsigned) (higher 16 bits) MDAL: Dividend (unsigned) (lower 16 bits) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Operation Result - - MDAH: Division result (unsigned) Higher 16 bits MDAL: Division result (unsigned) Lower 16 bits 778 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR (2) Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator mode, and set the divisor data in the division mode. The MDBH and MDBL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 14-3. Format of Multiplication/Division Data Register B (MDBH, MDBL) Address: FFFF4H, FFFF5H, FFFF6H, FFFF7H Symbol MDBH FFFF7H FFFF6H MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH 15 14 13 Symbol MDBL After reset: 0000H, 0000H R/W 12 11 10 9 8 7 6 5 FFFF5H 4 3 2 1 0 FFFF4H MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBHL MDBL MDBL MDBL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cautions 1. Do not rewrite the MDBH and MDBL registers values during division operation processing (when the multiplication/division control register (MDUC) value is 81H or C1H) or multiply<R> accumulation operation processing. The operation result will be an undefined value. 2. Do not set the MDBH and MDBL registers to 0000H in the division mode. If they are set, the operation result will be an undefined value. 3. The data is in the two's complement format in either the multiplication mode (signed) or multiply-accumulator mode (signed). The following table shows the functions of the MDBH and MDBL registers during operation execution. Table 14-3. Functions of MDBH and MDBL Registers During Operation Execution Operation Mode Multiplication mode (unsigned) Setting Operation Result - MDBH: Multiplication result (product) (unsigned) Multiply-accumulator mode (unsigned) Higher 16 bits MDBL: Multiplication result (product) (unsigned) Lower 16 bits Multiplication mode (signed) - Multiply-accumulator mode (signed) MDBH: Multiplication result (product) (signed) Higher 16 bits MDBL: Multiplication result (product) (signed) Lower 16 bits Division mode (unsigned) MDBH: Divisor (unsigned) - (higher 16 bits) MDBL: Divisor (unsigned) (lower 16 bits) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 779 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR (3) Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode. The MDCH and MDCL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 14-4. Format of Multiplication/Division Data Register C (MDCH, MDCL) Address: F00E0H, F00E1H, F00E2H, F00E3H Symbol MDCH F00E3H F00E2H MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH 15 14 13 12 11 10 9 8 7 6 5 F00E1H Symbol MDCL After reset: 0000H, 0000H R/W 4 3 2 1 0 F00E0H MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cautions 1. The MDCH and MDCL registers values read during division operation processing (when the multiplication/division control register (MDUC) value is 81H or C1H) will not be guaranteed. <R> 2. During multiply-accumulator processing, do not use software to rewrite the values of the MDCH and MDCL registers. If this is done, the operation result will be undefined. 3. The data is in the two's complement format in the multiply-accumulator mode (signed). Table 14-4. Functions of MDCH and MDCL Registers During Operation Execution Operation Mode Multiplication mode (unsigned Setting Operation Result - - or signed) Multiply-accumulator mode (unsigned) MDCH: Initial accumulated value (unsigned) (higher 16 bits) MDCL: Initial accumulated value (unsigned) (lower 16 bits) Multiply-accumulator mode (signed) MDCH: Initial accumulated value (signed) (higher 16 bits) MDCL: Initial accumulated value (signed) (lower 16 bits) Division mode (unsigned) - MDCH: accumulated value (unsigned) (higher 16 bits) MDCL: accumulated value (unsigned) (lower 16 bits) MDCH: accumulated value (signed) (higher 16 bits) MDCL: accumulated value (signed) (lower 16 bits) MDCH: Remainder (unsigned) (higher 16 bits) MDCL: Remainder (unsigned) (lower 16 bits) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 780 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows. * Register configuration during multiplication <Multiplier A> <Multiplier B> <Product> MDAL (bits 15 to 0) x MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] * Register configuration during multiply-accumulation <Multiplier A> <Multiplier B> < accumulated value > < accumulated result > MDAL (bits 15 to 0) x MDAH (bits 15 to 0) + MDC (bits 31 to 0) = [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] (The multiplication result is stored in the MDBH (bits 15 to 0) and MDBL (bits 15 to 0).) * Register configuration during division <Dividend> <Divisor> [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] / [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] = <Quotient> <Remainder> [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 781 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). (1) Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator. The MDUC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 14-5. Format of Multiplication/Division Control Register (MDUC) Address: F00E8H <R> After reset: 00H R/W Symbol <7> <6> 5 4 <3> <2> <1> <0> MDUC DIVMODE MACMODE 0 0 MDSM MACOF MACSF DIVST DIVMODE MACMODE MDSM 0 0 0 Multiplication mode (unsigned) (default) 0 0 1 Multiplication mode (signed) 0 1 0 Multiply-accumulator mode (unsigned) 0 1 1 Multiply-accumulator mode (signed) 1 0 0 Division mode (unsigned), generation or not generation of a Operation mode selection division completion interrupt (INTMD) 1 1 0 Division mode (unsigned), not generation of a division completion interrupt (INTMD) <R> Other than above MACOF Setting prohibited Overflow flag of multiply-accumulation result (accumulated value) 0 No overflow 1 With over flow <Set condition> * For the multiply-accumulator mode (unsigned) The bit is set when the accumulated value goes outside the range from 00000000h to FFFFFFFFh. * For the multiply-accumulator mode (signed) The bit is set when the result of adding a positive product to a positive accumulated value exceeds 7FFFFFFFh and is negative, or when the result of adding a negative product to a negative accumulated value exceeds 80000000h and is positive. MACSF Sign flag of multiply-accumulation result (accumulated value) 0 The accumulated value is positive. 1 The accumulated value is negative. Multiply-accumulator mode (unsigned): The bit is always 0. Multiply-accumulator mode (signed): The bit indicates the sign bit of the accumulated value. Note DIVST Division operation start/stop 0 Division operation processing complete 1 Starts division operation/division operation processing in progress (Note and Cautions are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 782 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Note The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to multiplication/division data register A (MDAH, MDAL), respectively. Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is 1). If it is rewritten, the operation result will be an undefined value. 2. The DIVST bit cannot be cleared (0) by using software during division operation processing (while the DIVST bit is 1). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 783 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4 Operations of Multiplier and Divider/Multiply-Accumulator 14.4.1 Multiplication (unsigned) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 00H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>. Multiplication operation is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) * During operation processing <4> Wait for at least one clock. The operation will end when one clock has been issued. * Operation end <5> Read the product (lower 16 bits) from multiplication/division data register B (L) (MDBL). <6> Read the product (higher 16 bits) from multiplication/division data register B (H) (MDBH). (There is no preference in the order of executing steps <5> and <6>.) * Next operation <R> <7> The next time multiplication, division, or multiply-accumulation is performed, start with the initial settings of each step. Remark Steps <1> to <7> correspond to <1> to <7> in Figure 14-6. Figure 14-6. Timing Diagram of Multiplication (Unsigned) Operation (2 x 3 = 6) <R> Operation clock MDUC 00H MDSM <1> L MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H 0002H 0003H FFFFH 0002H FFFDH 0000H 0006H <2> R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 FFFFH <4> <3> <5>, <6> FFFEH 0001H <7> 784 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.2 Multiplication (signed) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 08H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>. Multiplication operation is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) * During operation processing <4> Wait for at least one clock. The operation will end when one clock has been issued. * Operation end <5> Read the product (lower 16 bits) from multiplication/division data register B (L) (MDBL). <6> Read the product (higher 16 bits) from multiplication/division data register B (H) (MDBH). (There is no preference in the order of executing steps <5> and <6>.) * Next operation <R> <7> The next time multiplication, division, or multiply-accumulation is performed, start with the initial settings of each step. Caution The data is in the two's complement format in multiplication mode (signed). Remark Steps <1> to <7> correspond to <1> to <7> in Figure 14-7. <R> Figure 14-7. Timing Diagram of Multiplication (Signed) Operation (-2 x 32767 = -65534) Operation clock <1> MDUC 00H 08H MDSM MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H FFFEH 7FFFH FFFFH FFFFH 0002H <2> R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 FFFFH <4> <3> <5>, <6> FFFFH 8001H 0000H 0001H <7> 785 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.3 Multiply-accumulation (unsigned) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 40H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). <3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH). <4> Set the multiplicand to multiplication/division data register A (L) (MDAL). <5> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2>, <3>, and <4>. Multiplication operation is automatically started when the multiplier is set to the MDAH register, respectively.) * During operation processing <6> The multiplication operation finishes in one clock cycle. (The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division data register B (H) (MDBH).) <7> After <6>, the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least two clock cycles after specifying the initial settings is finished (<5>).) * Operation end <8> Read the accumulated value (lower 16 bits) from the MDCL register. <9> Read the accumulated value (higher 16 bits) from the MDCH register. (There is no preference in the order of executing steps <8> and <9>.) (<10> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD signal is occurred.) * Next operation <R> <11> The next time multiplication, division, or multiply-accumulation is performed, start with the initial settings of each step. Remark Steps <1> to <10> correspond to <1> to <10> in Figure 14-8. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 786 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR <R> Figure 14-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 x 3 + 3 = 9 32767 x 2 + 4294901762 = 0 (over flow generated)) Operation clock <1> MDUC 00H 40H 44H MDSM L MDCH 0000H MDCL 0000H 0000H 0000H 0003H FFFFH 0009H 0000H 0000H 0002H <8>, <9> MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H 0002H 7FFFH 0003H 0002H 0000H 0006H 0000H FFFEH <10> INTMD MACOF MACSF L <2> <3> <4> R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 <5> <6> <7> <2> <3> <4> <5> <6> <7> 787 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.4 Multiply-accumulation (signed) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 48H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). (<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) <4> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (L) (MDCL). <5> Set the multiplicand to multiplication/division data register A (L) (MDAL). <6> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2>, <4>, and <5>. Multiplication operation is automatically started when the multiplier is set to the MDAH register of <6>, respectively.) * During operation processing <7> The multiplication operation finishes in one clock cycle. (The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division data register B (H) (MDBH).) <8> After <7>, the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least two clock cycles after specifying the initial settings is finished (<6>).) * Operation end <9> If the accumulated value stored in the MDCL and MDCH registers is positive, the MACSF bit is cleared to 0. <10> Read the accumulated value (lower 16 bits) from the MDCL register. <11> Read the accumulated value (higher 16 bits) from the MDCH register. (There is no preference in the order of executing steps <10> and <11>.) (<12> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD signal is occurred.) * Next operation <R> <13> The next time multiplication, division, or multiply-accumulation is performed, start with the initial settings of each step. Caution The data is in the two's complement format in multiply-accumulation (signed) operation. Remark Steps <1> to <12> correspond to <1> to <12> in Figure 14-9. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 788 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) Operation <R> (2 x 3 + (-4) = 2 32767 x (-1) + (-2147483647) = -2147450882 (overflow occurs.)) Operation clock <1> MDUC 00H 48H 4CH 4AH MDSM L <9> <3> MDCH 0000H MDCL 0000H MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H <3> 0000H FFFFH FFFCH 8000H 0002H 7FFFH 8002H 0001H <10>, <11> 0002H 7FFFH 0003H FFFFH 0000H 0006H 0000H 0001H <12> INTMD MACOF MACSF L <3> <9> <2> <4> <5> <6> <7> <8> R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 <3> <2> <4> <5> <6> <7> <8> 789 RL78/G13 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.5 Division operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 80H. <2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). <3> Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL). <4> Set the divisor (higher 16 bits) to multiplication/division data register B (H) (MDBH). <5> Set the divisor (lower 16 bits) to multiplication/division data register B (L) (MDBL). <6> Set bit 0 (DIVST) of the MDUC register to 1. (There is no preference in the order of executing steps <2> to <5>.) * During operation processing <7> The operation will end when one of the following processing is completed. * A wait of at least 16 clocks (The operation will end when 16 clocks have been issued.) <R> * A check whether the DIVST bit has been cleared (The read values of the MDBL, MDBH, MDCL, and MDCH registers during operation processing are not guaranteed.) * Operation end <R> <8> The DIVST bit is cleared and the operation ends. At this time, an interrupt request signal (INTMD) is generated if the operation was performed with MACMODE = 0. <9> Read the quotient (lower 16 bits) from the MDAL register. <10> Read the quotient (higher 16 bits) from the MDAH register. <11> Read the remainder (lower 16 bits) from multiplication/division data register C (L) (MDCL). <12> Read the remainder (higher 16 bits) from multiplication/division data register C (H) (MDCH). (There is no preference in the order of executing steps <9> to <12>.) * Next operation <R> <13> The next time multiplication, division, or multiply-accumulation is performed, start with the initial settings of each step. Remark Steps <1> to <12> correspond to <1> to <12> in Figure 14-10. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 790 RL78/G13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Figure 14-10. Timing Diagram of Division Operation (Example: 35 / 6 = 5, Remainder 5) <R> Operation clock MDUC 80H 81H 80H <8> DIVST Counter MDBH, MDBL MDCH, MDCL 0H XXXXH XXXXH XXXXH XXXXH 0000H 0000H 0000H 0023H 0000H 0000H XXXXH XXXXH 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 0000H 0000H 0000H 0000H 0000H 0002H 0008H 0023H 008CH 0230H 08C0H 2300H 8C00H 3000H C000H 008CH 0230H 08C0H 2300H 8C00H 3000H C000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0001H 0H 0000H 0005H 0000H 0006H 0000H 0000H 0000H 0002H 0000H 0005H <8> INTMD <1> <2> <3> <4> <5> <6> <7> <9>, <10> <11>, <12> 791 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR MDAH, MDAL Undefined RL78/G13 CHAPTER 15 DMA CONTROLLER CHAPTER 15 DMA CONTROLLER The RL78/G13 has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed. In addition, real-time control using communication, timer, and A/D can also be realized. 15.1 Functions of DMA Controller { Number of DMA channels: 2 channels (20, 24, 25, 30, 32, 36, 40, 44, 48, 52, or 64-pin products) 4 channels (80, 100, or 128-pin products) { Transfer unit: 8 or 16 bits { Maximum transfer unit: 1024 times { Transfer type: 2-cycle transfer (One transfer is processed in 2 clocks and the CPU stops during that processing.) { Transfer mode: Single-transfer mode { Transfer request: Selectable from the following peripheral hardware interrupts * A/D converter * Serial interface (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31, UART0 to UART3) * Timer (channel 0, 1, 2, 3, 10, 11, 12, or 13) { Transfer target: Between SFR and internal RAM Here are examples of functions using DMA. * Successive transfer of serial interface * Batch transfer of analog data * Capturing A/D conversion result at fixed interval * Capturing port value at fixed interval R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 792 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 15-1. Configuration of DMA Controller Item Configuration * DMA SFR address registers 0 to 3 (DSA0 to DSA3) Address registers * DMA RAM address registers 0 to 3 (DRA0 to DRA3) Count register * DMA byte count registers 0 to 3 (DBC0 to DBC3) Control registers * DMA mode control registers 0 to 3 (DMC0 to DMC3) * DMA operation control register 0 to 3 (DRC0 to DRC3) (1) DMA SFR address register n (DSAn) This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA channel n. Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH. This register is not automatically incremented but fixed to a specific value. In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. The DSAn register can be read or written in 8-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 00H. Figure 15-1. Format of DMA SFR Address Register n (DSAn) Address: FFFB0H (DSA0), FFFB1H (DSA1), F0200H (DSA2), F0201H (DSA3) After reset: 00H 7 6 5 4 3 2 1 R/W 0 DSAn Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 793 RL78/G13 CHAPTER 15 DMA CONTROLLER (2) DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (see table 15-2) can be set to this register. Set the lower 16 bits of the RAM address. This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this DRAn register. When the data of the last address has been transferred, the DRAn register stops with the value of the last address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode. In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 0000H. Figure 15-2. Format of DMA RAM Address Register n (DRAn) Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) , After reset: 0000H R/W F0202H, F0203H (DRA2), F0204H, F0205H (DRA3) 15 14 DRA0H: FFFB3H DRA0L: FFFB2H DRA1H: FFFB5H DRA1L: FFFB4H DRA2H: F0203H DRA2L: F0202H DRA3H: F0205H DRA3L: F0204H 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRAn (n = 0 to 3) Table 15-2 Internal RAM Area other than the General-purpose Registers Part Number R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G), Internal RAM Area other than the General-purpose Registers FF700H to FFEDFH R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L) R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L) FF300H to FFEDFH R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L) FEF00H to FFEDFH R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P) FDF00H to FFEDFH R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P) FCF00H to FFEDFH R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) FBF00H to FFEDFH R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S) FAF00H to FFEDFH R5F100xK, R5F101xK (x = F, G, J, L, M, P, S) F9F00H to FFEDFH R5F100xL, R5F101xL (x = F, G, J, L, M, P, S) F7F00H to FFEDFH Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 794 RL78/G13 CHAPTER 15 DMA CONTROLLER (3) DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times). Each time DMA transfer has been executed, this register is automatically decremented. By reading this DBCn register during DMA transfer, the remaining number of times of transfer can be learned. The DBCn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 0000H. Figure 15-3. Format of DMA Byte Count Register n (DBCn) Address: FFFB6H, FFFB7H (DBC0), FFFB8H, FFFB9H (DBC1) After reset: 0000H F0206H, F0207H (DBC2), F0208H, F0209H (DBC3) DBC0H: FFFB7H DBCn R/W DBC0L: FFFB6H DBC1H: FFFB9H DBC1L: FFFB8H DBC2H: F0207H DBC2L: F0206H DBC3H: F0209H DBC3L: F0208H 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 (n = 0 to 3) DBCn[9:0] Number of Times of Transfer (When DBCn is Written) Remaining Number of Times of Transfer (When DBCn is Read) 000H 1024 Completion of transfer or waiting for 1024 times of DMA transfer 001H 1 Waiting for remaining one time of DMA transfer 002H 2 Waiting for remaining two times of DMA transfer 003H 3 Waiting for remaining three times of DMA transfer * * * * * * * * * 3FEH 1022 Waiting for remaining 1022 times of DMA transfer 3FFH 1023 Waiting for remaining 1023 times of DMA transfer Cautions 1. Be sure to clear bits 15 to 10 to "0". 2. If the general-purpose register is specified or the internal RAM space is exceeded as a result of continuous transfer, the general-purpose register or SFR space are written or read, resulting in loss of data in these spaces. Be sure to set the number of times of transfer that is within the internal RAM space. Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 795 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. * DMA mode control register n (DMCn) * DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 796 RL78/G13 CHAPTER 15 DMA CONTROLLER (1) DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA. Rewriting bits 6, 5, and 3 to 0 of the DMCn register is prohibited during operation (when DSTn = 1). The DMCn register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 15-4. Format of DMA Mode Control Register n (DMCn) (1/3) Address: FFFBAH (DMC0), FFFBBH (DMC1), F020AH (DMC2), F020BH (DMC3) After reset: 00H R/W Symbol <7> <6> <5> <4> 3 2 1 0 DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 STGn Note 1 DMA transfer start software trigger 0 No trigger operation 1 DMA transfer is started when DMA operation is enabled (DENn = 1). DMA transfer is performed once by writing 1 to the STGn bit when DMA operation is enabled (DENn = 1). When this bit is read, 0 is always read. DRSn Selection of DMA transfer direction 0 SFR to internal RAM 1 Internal RAM to SFR DSn Specification of transfer data size for DMA transfer 0 8 bits 1 16 bits DWAITn Note 2 Pending of DMA transfer 0 Executes DMA transfer upon DMA start request (not held pending). 1 Holds DMA start request pending if any. DMA transfer that has been held pending can be started by clearing the value of the DWAITn bit to 0. It takes 2 clocks to actually hold DMA transfer pending when the value of the DWAITn bit is set to 1. Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values. 2. When DMA transfer is held pending while using two or more DMA channels, be sure to hold the DMA transfer pending for all channels (by setting the DWAIT0, DWAIT1, DWAIT2, and DWAIT3 bits to 1). Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 797 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-4. Format of DMA Mode Control Register n (DMCn) (2/3) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W Symbol <7> <6> <5> <4> 3 2 1 0 DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 0 or 1) IFCn IFCn IFCn IFCn 3 2 1 0 Trigger signal 0 0 0 0 - Selection of DMA start source Note Trigger contents Disables DMA transfer by interrupt. (Only software trigger is enabled.) 0 0 0 1 INTAD A/D conversion end interrupt 0 0 1 0 INTTM00 End of timer channel 00 count or capture 0 0 1 1 INTTM01 end interrupt End of timer channel 01 count or capture end interrupt 0 1 0 0 INTTM02 End of timer channel 02 count or capture end interrupt 0 1 0 1 INTTM03 End of timer channel 03 count or capture end interrupt 0 1 1 0 INTST0/INTCSI00 UART0 transmission transfer end or buffer empty interrupt/CSI00 transfer end or buffer empty interrupt 0 1 1 1 INTSR0/INTCSI01 UART0 reception transfer end interrupt/CSI01 transfer end or buffer empty interrupt 1 0 0 0 INTST1/INTCSI10 UART1 transmission transfer end or buffer empty interrupt/CSI10 transfer end or buffer empty interrupt 1 0 0 1 INTSR1/INTCSI11 UART1 reception transfer end interrupt/CSI11 transfer end or buffer empty interrupt 1 0 1 0 INTST2/INTCSI20 UART2 transmission transfer end or buffer empty interrupt/CSI20 transfer end or buffer empty interrupt 1 0 1 1 INTSR2/INTCSI21 UART2 reception transfer end interrupt/CSI21 transfer end or buffer empty interrupt Other than above Setting prohibited Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values. Remark n: DMA channel number (n = 0, 1) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 798 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-4. Format of DMA Mode Control Register n (DMCn) (3/3) Address: F020AH (DMC2), F020BH (DMC3) After reset: 00H R/W Symbol <7> <6> <5> <4> 3 2 1 0 DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 2 or 3) IFCn IFCn IFCn IFCn 3 2 1 0 Trigger signal 0 0 0 0 - Selection of DMA start source Note Trigger contents Disables DMA transfer by interrupt. (Only software trigger is enabled.) 0 0 0 1 INTAD A/D conversion end interrupt 0 0 1 0 INTTM10 End of timer channel 10 count or capture 0 0 1 1 INTTM11 end interrupt End of timer channel 11 count or capture end interrupt 0 1 0 0 INTTM12 End of timer channel 12 count or capture end interrupt 0 1 0 1 INTTM13 End of timer channel 13 count or capture end interrupt 0 1 1 0 INTST3/INTCSI30 UART3 transmission transfer end or buffer empty interrupt/CSI30 transfer end or buffer empty interrupt 0 1 1 1 INTSR3/INTCSI31 UART3 reception transfer end interrupt/CSI31 transfer end or buffer empty interrupt 1 0 0 0 INTST1/INTCSI10 UART1 transmission transfer end or buffer empty interrupt/CSI10 transfer end or buffer empty interrupt 1 0 0 1 INTSR1/INTCSI11 UART1 reception transfer end interrupt/CSI11 transfer end or buffer empty interrupt 1 0 1 0 INTST2/INTCSI20 UART2 transmission transfer end or buffer empty interrupt/CSI20 transfer end or buffer empty interrupt 1 0 1 1 INTSR2/INTCSI21 UART2 reception transfer end interrupt/CSI21 transfer end or buffer empty interrupt Other than above Setting prohibited Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values. Remark n: DMA channel number (n = 2, 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 799 RL78/G13 CHAPTER 15 DMA CONTROLLER (2) DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1). The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 15-5. Format of DMA Operation Control Register n (DRCn) Address: FFFBCH (DRC0), FFFBDH (DRC1), F020CH (DRC2), F020DH (DRC3) After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> DRCn DENn 0 0 0 0 0 0 DSTn DENn DMA operation enable flag 0 Disables operation of DMA channel n (stops operating cock of DMA). 1 Enables operation of DMA channel n. DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1). DSTn DMA transfer mode flag 0 DMA transfer of DMA channel n is completed. 1 DMA transfer of DMA channel n is not completed (still under execution). DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1). When a software trigger (STGn) or the start source trigger set by the IFCn3 to IFCn0 bits is input, DMA transfer is started. When DMA transfer is completed after that, this bit is automatically cleared to 0. Write 0 to this bit to forcibly terminate DMA transfer under execution. Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set the DSTn bit to 0 and then the DENn bit to 0 (for details, refer to 15.5.5 Forced termination by software). Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 800 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.4 Operation of DMA Controller 15.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction. <2> Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer to DMA SFR address register n (DSAn), DMA RAM address register n (DRAn), DMA byte count register n (DBCn), and DMA mode control register n (DMCn). <3> The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation instruction. <4> When a software trigger (STGn) or a start source trigger specified by the IFCn3 to IFCn0 bits is input, a DMA transfer is started. <5> Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer is automatically terminated by occurrence of an interrupt (INTDMAn). <6> Stop the operation of the DMA controller by clearing the DENn bit to 0 when the DMA controller is not used. Figure 15-6. Operation Procedure DENn = 1 Set by software program Setting DSAn, DRAn, DBCn, and DMCn DSTn = 1 DMA trigger = 1? No Yes Transmitting DMA request Receiving DMA acknowledge Operation by DMA DMA transfer controller (hardware) DRAn = DRAn + 1 (or + 2) DBCn = DBCn - 1 No DBCn = 0000H ? Yes DSTn = 0 INTDMAn = 1 DENn = 0 Remark Set by software program n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 801 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn). DRSn DSn DMA Transfer Mode 0 0 Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1) 0 1 Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2) 1 0 Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address) 1 1 Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address) By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface, data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed time intervals by using a timer. 15.4.3 Termination of DMA transfer When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request (INTDMAn) is generated and transfer is terminated. When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, DMA byte count register n (DBCn) and DMA RAM address register n (DRAn) hold the value when transfer is terminated. The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated. Remark n: DMA channel number (n = 0 to 3) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 802 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5 Example of Setting of DMA Controller 15.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. * Consecutive transmission of CSI10 (256 bytes) * DMA channel 0 is used for DMA transfer. * DMA start source: INTCSI10 (software trigger (STG0) only for the first start source) * Interrupt of CSI10 is specified by IFC03 to IFC00 = 1000B. * Transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF44H of the data register (SIO10) of CSI. Remark IFC03 to IFC00: Bits 3 to 0 of DMA mode control registers 0 (DMC0) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 803 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 44H DRA0 = FB00H DBC0 = 0100H DMC0 = 48H Setting for CSI transfer DST0 = 1 DMA is started. STG0 = 1 INTCSI10 occurs. User program processing DMA0 transfer CSI transmission Occurrence of INTDMA0 DST0 = 0Note DEN0 = 0 RETI Hardware operation End Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details, refer to 15.5.5 Forced termination by software). The fist trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a software trigger. CSI transmission of the second time and onward is automatically executed. A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 804 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. * Consecutive capturing of A/D conversion results. * DMA channel 1 is used for DMA transfer. * DMA start source: INTAD * Interrupt of A/D is specified by IFC13 to IFC10 = 0001B. * Transfers FFF1EH and FFF1FH (2 bytes) of the 10-bit A/D conversion result register (ADCR) to 512 bytes of FFCE0H to FFEDFH of RAM. Remark IFC13 to IFC10: Bits 3 to 0 of DMA mode control registers 1 (DMC1) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 805 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs. User program processing DMA1 transfer INTDMA1 occurs. DST1 = 0Note DEN1 = 0 RETI Hardware operation End Note The DST1 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN1 flag is enabled only when DST1 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA1 (INTDMA1), set the DST1 bit to 0 and then the DEN1 bit to 0 (for details, refer to 15.5.5 Forced termination by software). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 806 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below. * Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception. * DMA channel 0 is used for DMA transfer. * DMA start source: Software trigger (DMA transfer on occurrence of an interrupt is disabled.) * Transfers FFF12H of UART receive data register 0 (RXD0) to 64 bytes of FFE00H to FFE3FH of RAM. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 807 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-9. Example of Setting for UART Consecutive Reception + ACK Transmission Start INTSR0 interrupt routine DEN0 = 1 DSA0 = 12H STG0 = 1 DRA0 = FE00H DBC0 = 0040H DMC0 = 00H DMA0 transfer P10 = 1 Setting for UART reception P10 = 0 DST0 = 1 INTSR0 occurs. RETI User program processing INTDMA0 occurs. DST0 = 0 DEN0 = 0Note RETI Hardware operation End Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details, refer to 15.5.5 Forced termination by software). Remark This is an example where a software trigger is used as a DMA start source. If ACK is not transmitted and if only data is consecutively received from UART, the UART reception end interrupt (INTSR0) can be used to start DMA for data reception. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 808 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1. The DMA transfer for a transfer trigger that occurred while DMA transfer was held pending is executed after the pending status is canceled. However, because only one transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel during the pending status, only one DMA transfer is executed after the pending status is canceled. To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin, for example, the clock width increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by setting the DWAITn bit to 1. After setting the DWAITn bit to 1, it takes two clocks until a DMA transfer is held pending. Figure 15-10. Example of Setting for Holding DMA Transfer Pending by DWAITn Bit Starting DMA transfer Main program DWAITn = 1 Wait for 2 clocks P10 = 1 Wait for 9 clocks P10 = 0 DWAITn = 0 Caution When DMA transfer is held pending while using two or more DMA channels, be sure to held the DMA transfer pending for all channels (by setting DWAIT0, DWAIT1, DWAIT2, and DWAIT3 to 1). If the DMA transfer of one channel is executed while that of the other channel is held pending, DMA transfer might not be held pending for the latter channel. Remarks 1. n: DMA channel number (n = 0 to 3) 2. 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 809 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes. <When using one DMA channel> * Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling that the DSTn bit has actually been cleared to 0, and then set the DENn bit to 0 (use DRCn = 00H to write with an 8bit manipulation instruction). * Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set the DENn bit to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after. <When using two or more DMA channels> * To forcibly terminate DMA transfer by software when using two or more DMA channels (by setting DSTn to 0), clear the DSTn bit to 0 after the DMA transfer is held pending by setting the DWAITn bits of all using channels to 1. Next, clear the DWAITn bits of all using channels to 0 to cancel the pending status, and then clear the DENn bit to 0. Figure 15-11. Forced Termination of DMA Transfer (1/2) Example 1 Example 2 DSTn = 0 DSTn = 0 No 2 clock wait DSTn = 0 ? Yes DENn = 0 DENn = 0 Remarks 1. n: DMA channel number (n = 0 to 3) 2. 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 810 RL78/G13 CHAPTER 15 DMA CONTROLLER Figure 15-11. Forced Termination of DMA Transfer (2/2) Example 3 * Procedure for forcibly terminating the DMA transfer for one channel if both channels are used * Procedure for forcibly terminating the DMA transfer for both channels if both channels are used DWAIT0 = 1 DWAIT0 = 1 DWAIT1 = 1 DWAIT1 = 1 DSTn = 0 DST0 = 0 DST1 = 0 DWAIT0 = 0 DWAIT1 = 0 DWAIT0 = 0 DWAIT1 = 0 DENn = 0 DEN0 = 0 DEN1 = 0 Caution In example 3, the system is not required to wait two clock cycles after the DWAITn bit is set to 1. In addition, the system does not have to wait two clock cycles after clearing the DSTn bit to 0, because more than two clock cycles elapse from when the DSTn bit is cleared to 0 to when the DENn bit is cleared to 0. Remarks 1. n: DMA channel number (n = 0, 1) 2. 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 811 RL78/G13 CHAPTER 15 DMA CONTROLLER 15.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, their priority are DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3. If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence, and then interrupt servicing is executed. (2) DMA response time The response time of DMA transfer is as follows. Table 15-2. Response Time of DMA Transfer Minimum Time Response time Maximum Time Note 3 clocks 10 clocks Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles. Cautions 1. The above response time does not include the two clock cycles required for a DMA transfer. 2. When executing a DMA pending instruction (see 15.6 (4)), the maximum response time is extended by the execution time of that instruction to be held pending. 3. Do not specify successive transfer triggers for a channel within a period equal to the maximum response time plus one clock cycle, because they might be ignored. Remark 1 clock: 1/fCLK (fCLK: CPU clock) (3) Operation in standby mode The DMA controller operates as follows in the standby mode. Table 15-3. DMA Operation in Standby Mode Status DMA Operation HALT mode Normal operation STOP mode Stops operation. If DMA transfer and STOP instruction execution contend, DMA transfer may be damaged. Therefore, stop DMA before executing the STOP instruction. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 812 RL78/G13 CHAPTER 15 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions. * CALL !addr16 * CALL $!addr20 * CALL !!addr20 * CALL rp * CALLT [addr5] * BRK * Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, and PSW each. * Instruction for accessing the data flash memory (5) Operation if address in general-purpose register area or other than those of internal RAM area is specified The address indicated by DMA RAM address register n (DRAn) is incremented during DMA transfer. If the address is incremented to an address in the general-purpose register area or exceeds the area of the internal RAM, the following operation is performed. z In mode of transfer from SFR to RAM The data of that address is lost. z In mode of transfer from RAM to SFR Undefined data is transferred to SFR. In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that the address is within the internal RAM area other than the general-purpose register area. FFF00H FFEFFH FFEE0H FFEDFH General-purpose registers Internal RAM DMA transfer enabled area (6) Operation if instructions for accessing the data flash area * Because DMA transfer is suspended to access to the data flash area, be sure to add the DMA pending instruction. If the data flash area is accessed after an next instruction execution from start of DMA transfer, a 3-clock wait will be inserted to the next instruction. Instruction 1 DMA transfer Instruction 2 The wait of three clock cycles occurs. MOV A, ! DataFlash area R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 813 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS CHAPTER 16 INTERRUPT FUNCTIONS <R> The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product. 20-pin Maskable interrupts 24, 25- 30, 32, 40, 44- pin 36-pin pin 48-pin 52-pin 64-pin 80, 100- 128-pin pin External 3 5 6 7 10 12 13 13 13 Internal 23 24 27 27 27 27 27 37 41 16.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the default priority of vectored interrupt servicing. Default priority, see Table 16-1. A standby release signal is generated and STOP, HALT, and SNOOZE modes are released. External interrupt requests and internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 16.2 Interrupt Sources and Configuration Interrupt sources include maskable interrupts and software interrupts. In addition, they also have up to seven reset sources (see Table 16-1). The vector codes that store the program start address when branching due to the generation of a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 814 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (1/4) Pin input edge detection 0008H 0006H External 20-pin 24-pin INTP0 25-pin 2 Note 4 30-pin Voltage detection 32-pin INTLVI 36-pin (A) 40-pin 1 Internal 44-pin Watchdog timer interval (75% of overflow time+1/2fIL) 48-pin INTWDTI 52-pin Note 3 0 64-pin 0004H Note 1 Maskable 80-pin Trigger 100-pin Name Vector Table Address 128-pin Internal/ External Interrupt Source Basic Configuration Note 2 Type Default Priority Interrupt Type (B) 3 INTP1 000AH - 4 INTP2 000CH - - - 5 INTP3 000EH 6 INTP4 0010H - 7 INTP5 0012H 8 INTST2/ INTCSI20/ INTIIC20 UART2 transmission transfer end or buffer empty interrupt/CSI20 transfer end or buffer empty interrupt/IIC20 transfer end 9 INTSR2/ INTCSI21/ INTIIC21 UART2 reception transfer end/CSI21 transfer end or buffer empty interrupt/IIC21 transfer end 0016H 10 INTSRE2 UART2 reception communication error occurrence 0018H - - - INTTM11H End of timer channel 11 count or capture (at higher 8-bit timer operation) Internal 0014H (A) - - - Note 5 Note 5 - - - - - - - - - - - - - - INTST0/ INTCSI00/ INTIIC00 UART0 transmission transfer end or buffer empty interrupt/CSI00 transfer end or buffer empty interrupt/IIC00 transfer end 001EH 14 INTSR0/ INTCSI01/ INTIIC01 UART0 reception transfer end/CSI01 transfer end or buffer empty interrupt/IIC01 transfer end 0020H 15 INTSRE0 UART0 reception communication error occurrence 0022H INTTM01H End of timer channel 01 count or capture (at higher 8-bit timer operation) Notes 1. Note 6 Note 6 13 Note 6 Note 6 001CH Note 6 001AH End of DMA1 transfer Note 6 End of DMA0 transfer INTDMA1 Note 6 INTDMA0 12 Note 6 11 The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 53 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 16-1. 3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1. 4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0. 5. INTSR2 only. 6. INTSR0 only. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 815 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (2/4) 44-pin 40-pin 36-pin 32-pin 30-pin 25-pin Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 Note 3 48-pin 20-pin 24-pin 52-pin (A) 64-pin 0024H Note 1 Maskable 80-pin Trigger Vector Table Address 100-pin Name Internal/ External 128-pin Interrupt Source Basic Configuration Note 2 Type Default Priority Interrupt Type 16 INTST1/ INTCSI10/ INTIIC10 UART1 transmission transfer end or buffer empty interrupt/CSI10 transfer end or buffer empty interrupt/IIC10 transfer end 17 INTSR1/ INTCSI11/ INTIIC11 UART1 reception transfer end/CSI11 transfer end or buffer empty interrupt/IIC11 transfer end 0026H 18 INTSRE1 UART1 reception communication error occurrence 0028H INTTM03H End of timer channel 03 count or capture (at higher 8-bit timer operation) 19 INTIICA0 End of IICA0 communication 002AH - 20 INTTM00 End of timer channel 00 count or capture 002CH 21 INTTM01 End of timer channel 01 count or capture (at 16-bit/lower 8-bit timer operation) 002EH 22 INTTM02 End of timer channel 02 count or capture 0030H 23 INTTM03 End of timer channel 03 count or capture (at 16-bit/lower 8-bit timer operation) 0032H 24 INTAD End of A/D conversion 0034H 25 INTRTC Fixed-cycle signal of real-time clock/alarm match detection 0036H 26 INTIT Interval signal of 12-bit interval timer detection 0038H 27 INTKR Key return signal detection External 003AH (C) - - - - - - 28 INTST3/ INTCSI30/ INTIIC30 UART3 transmission transfer end or buffer empty interrupt/CSI30 transfer end or buffer empty interrupt/IIC30 transfer end Internal 003CH (A) - - - - - - - - - - - 29 INTSR3/ INTCSI31/ INTIIC31 UART3 reception transfer end/CSI31 transfer end or buffer empty interrupt/IIC31 transfer end 003EH - - - - - - - - - - - 30 INTTM13 End of timer channel 13 count or capture (at 16-bit/lower 8-bit timer operation) 0040H - - - - - - - - - - - Notes 1. Internal The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 53 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 16-1. 3. INTST1 only. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 816 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (3/4) 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin 44-pin 48-pin 52-pin (A) 64-pin 0042H Note 1 Maskable 80-pin Trigger 100-pin Name Vector Table Address 128-pin Internal/ External Interrupt Source Basic Configuration Note 2 Type Default Priority Interrupt Type 31 INTTM04 End of timer channel 04 count or capture 32 INTTM05 End of timer channel 05 count or capture 0044H 33 INTTM06 End of timer channel 06 count or capture 0046H 34 INTTM07 End of timer channel 07 count or capture 0048H 35 INTP6 Pin input edge detection 36 INTP7 004CH - - - - - - - - - - 37 INTP8 004EH - - - - - - - - 38 INTP9 0050H - - - - - - - - 39 INTP10 0052H - - - - - - - - - Internal External 004AH (B) - - - - - - - - - - - - - - - - - 40 INTP11 41 INTTM10 End of timer channel 10 count or capture 0054H 42 INTTM11 End of timer channel 11 count or capture (at 16-bit/lower 8-bit timer operation) 0058H - - - - - - - - - - - 43 INTTM12 End of timer channel 12 count or capture 005AH - - - - - - - - - - - 44 INTSRE3 UART3 reception communication error occurrence 005CH - - - - - - - - - - - INTTM13H End of timer channel 13 count or capture (at higher 8-bit timer operation) 45 INTMD End of division operation/ Overflow occur 46 INTIICA1 End of IICA1 communication Internal 0056H (A) - - - - - - - - - - - - - - - - - - - - - - 005EH 0060H - - - - - - - - - - - 47 INTFL End of sequencer interrupt 0062H 48 INTDMA2 End of DMA2 transfer 0064H - - - - - - - - - - - 49 INTDMA3 End of DMA3 transfer 0066H - - - - - - - - - - - 50 INTTM14 End of timer channel 14 count or capture 0068H - - - - - - - - - - - - - 51 INTTM15 End of timer channel 15 count or capture 006AH - - - - - - - - - - - - - 52 INTTM16 End of timer channel 16 count or capture 006CH - - - - - - - - - - - - - 53 INTTM17 End of timer channel 17 count or capture 006EH - - - - - - - - - - - - - Notes 1. Note 3 The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 53 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 16-1. 3. Be used only at the self programming library. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 817 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1. Interrupt Source List (4/4) 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin Notes 1. 44-pin Vector Table Address Execution of BRK instruction - 007EH (D) RESET RESET pin input - 0000H - POR Power-on-reset Interrupt Source Note 1 <R> 48-pin - 52-pin Reset 64-pin BRK 80-pin - 100-pin Software 128-pin Default Priority Internal/ External Basic Configuration Note 2 Type Interrupt Type Note 3 LVD Voltage detection WDT Overflow of watchdog timer TRAP Execution of illegal Note 4 instruction IAW Illegal-memory access RPE RAM parity error The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 53 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 16-1. 3. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is set to 1. 4. When the instruction code in FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 818 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus MK Interrupt request IE PR1 PR0 ISP1 ISP0 Vector table address generator Priority controller IF Standby release signal (B) External maskable interrupt (INTPn) Internal bus External interrupt edge enable register (EGP, EGN) INTPn pin input Edge detector MK IF IE PR1 PR0 Priority controller ISP1 ISP0 Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag ISP0: In-service priority flag 0 ISP1: In-service priority flag 1 MK: Interrupt mask flag PR0: Priority specification flag 0 PR1: Priority specification flag 1 Remark 20-pin: n = 0, 3, 5 24, 25-pin: n = 0, 1, 3 to 5 30, 32, 36, 40, 44-pin: n = 0 to 5 48-pin: n = 0 to 6, 8, 9 52-pin: n = 0 to 6, 8 to 11 64, 80, 100, 128-pin: n = 0 to 11 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 819 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Key return mode register (KRM) MK IE PR1 PR0 ISP1 ISP0 KRMn KRn pin input Key interrupt detector Priority controller IF Vector table address generator Standby release signal (D) Software interrupt Internal bus Interrupt request IF: Vector table address generator Interrupt request flag IE: Interrupt enable flag ISP0: In-service priority flag 0 ISP1: In-service priority flag 1 MK: Interrupt mask flag PR0: Priority specification flag 0 PR1: Priority specification flag 1 Remark 40, 44-pin: n = 0 to 4 48-pin: n = 0 to 5 52, 64, 80, 100, 128-pin: n = 0 to 7 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 820 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) * Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) * Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) * External interrupt rising edge enable registers (EGP0, EGP1) * External interrupt falling edge enable registers (EGN0, EGN1) * Program status word (PSW) Table 16-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 16-2. Flags Corresponding to Interrupt Request Sources (1/4) 20-pin 24-pin MK0L 25-pin 30-pin WDTIMK 32-pin IF0L 36-pin 40-pin WDTIIF 44-pin INTWDTI Register 48-pin Register Priority Specification Flag 52-pin 64-pin Interrupt Mask Flag 80-pin Flag 100-pin Interrupt Request Source 128-pin Interrupt Register WDTIPR0, PR00L, WDTIPR1 PR10L INTLVI LVIIF LVIMK LVIPR0, LVIPR1 INTP0 PIF0 PMK0 PPR00, PPR10 INTP1 PIF1 PMK1 PPR01, PPR11 - INTP2 PIF2 PMK2 PPR02, PPR12 - - - INTP3 PIF3 PMK3 PPR03, PPR13 INTP4 PIF4 PMK4 PPR04, PPR14 - INTP5 PIF5 PMK5 PPR05, PPR15 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 821 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (2/4) Note 2 INTSR2 Note 2 INTCSI21 Note 2 INTIIC21 INTSRE2 Note 3 INTTM11H Note 1 IICIF20 Note 2 Note 1 IICMK20 CSIIF21 Note 2 IICIF21 Note 3 Note 3 CSIMK21 Note 2 IICMK21 Note 3 TMMK11H CSIPR020, CSIPR120 Note 1 IICPR020, IICPR120 SRPR02, SRPR12 Note 2 SREMK2 Note 1 Note 2 SRMK2 Note 2 TMIF11H CSIMK20 Note 2 SRIF2 SREIF2 Note 1 Note 1 STPR02, STPR12 Note 3 Note 3 Note 2 CSIPR021, CSIPR121 Note 2 IICPR021, IICPR121 20-pin 24-pin INTIIC20 CSIIF20 MK0H 25-pin 30-pin Note 1 Note 1 Note 1 STMK2 32-pin INTCSI20 IF0H 36-pin 40-pin Note 1 Note 1 STIF2 Register 44-pin Note 1 INTST2 Register 48-pin Register 52-pin 64-pin Priority Specification Flag 80-pin Interrupt Mask Flag 100-pin Interrupt Request Flag Source 128-pin Interrupt PR00H, - - - PR10H - - - - - - - - - - - - - - - - - - - Note 3 SREPR02, SREPR12 - - - TMPR011H, TMPR111H - - - - - - - - - - - Note 3 INTDMA0 DMAIF0 DMAMK0 DMAPR00, DMAPR10 INTDMA1 DMAIF1 DMAMK1 DMAPR01, DMAPR11 Note 4 INTST0 Note 4 INTCSI00 Note 4 INTIIC00 Note 5 INTSR0 Note 5 INTCSI01 Note 5 INTIIC01 Note 6 Note 4 Note 4 STIF0 Note 4 CSIIF00 Note 4 IICIF00 Note 5 CSIIF01 Note 5 IICIF01 Note 6 SREIF0 TMIF01H Note 4 CSIMK00 Note 4 IICMK00 Note 6 CSIMK01 Note 5 IICMK01 SREMK0 Note 6 Note 6 CSIPR000, CSIPR100 Note 4 IICPR000, IICPR100 SRPR00, SRPR10 Note 5 TMMK01H Note 4 Note 5 SRMK0 Note 5 INTTM01H STPR00, STPR10 Note 5 SRIF0 INTSRE0 Note 4 STMK0 Note 6 Note 5 CSIPR001, CSIPR101 - - - - - - - - - - - - - - - - Note 6 SREPR00, SREPR10 TMPR101H Note 5 IICPR001, IICPR101 TMPR001H, Note 6 Notes 1. If one of the interrupt sources INTST2, INTCSI20, and INTIIC20 is generated, bit 0 of the IF0H register is set to 1. Bit 0 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources. 2. If one of the interrupt sources INTSR2, INTCSI21, and INTIIC21 is generated, bit 1 of the IF0H register is set to 1. Bit 1 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources. 3. Do not use UART2 and channel 1 of TAU1 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If one of the interrupt sources INTSRE2 and INTTM11H is generated, bit 2 of the IF0H register is set to 1. Bit 2 of the MK0H, PR00H, and PR10H registers supports these two interrupt sources. 4. If one of the interrupt sources INTST0, INTCSI00, and INTIIC00 is generated, bit 5 of the IF0H register is set to 1. Bit 5 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources. 5. If one of the interrupt sources INTSR0, INTCSI01, and INTIIC01 is generated, bit 6 of the IF0H register is set to 1. Bit 6 of the MK0H, PR00H, and PR10H registers supports these three interrupt sources. 6. Do not use UART0 and channel 1 of TAU0 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If one of the interrupt sources INTSRE0 and INTTM01H is generated, bit 7 of the IF0H register is set to 1. Bit 7 of the MK0H, PR00H, and PR10H registers supports these two interrupt sources. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 822 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (3/4) Note 1 INTST1 Note 1 INTCSI10 Note 1 INTIIC10 Note 2 INTSR1 Note 2 INTCSI11 Note 2 INTIIC11 Note 3 INTSRE1 Note 3 INTTM03H STIF1 Note 1 IF1L Note 1 IICMK11 SREMK1 Note 3 Note 2 Note 3 IICPR011, IICPR111 Note 3 TMMK03H Note 2 CSIPR011, CSIPR111 Note 2 Note 3 - - - - - - - - - - Note 2 CSIMK11 IICIF11 - - - - - - - - - - SRPR01, SRPR11 Note 2 Note 2 PR11L IICPR010, IICPR110 Note 2 CSIIF11 PR01L, Note 1 SRMK1 Note 2 Note 1 STPR01, STPR11 CSIPR010, CSIPR110 IICMK10 Note 2 Register Note 1 Note 1 IICIF10 TMIF03H MK1L CSIMK10 Note 1 SREIF1 Note 1 STMK1 Note 1 CSIIF10 SRIF1 Register SREPR01, SREPR11 Note 3 TMPR003H, TMPR103H 20-pin 24-pin Register 25-pin 30-pin Priority Specification Flag 32-pin 36-pin 40-pin Interrupt Mask Flag 44-pin 48-pin 52-pin 64-pin Interrupt Request Flag Source 80-pin 100-pin 128-pin Interrupt Note 3 INTIICA0 IICAIF0 IICAMK0 IICAPR00, IICAPR10 - INTTM00 TMIF00 TMMK00 TMPR000, TMPR100 INTTM01 TMIF01 TMMK01 TMPR001, TMPR101 INTTM02 TMIF02 TMMK02 TMPR002, TMPR102 INTTM03 TMIF03 TMMK03 TMPR003, TMPR103 INTAD ADIF IF1H ADMK MK1H ADPR0, ADPR1 PR01H, PR11H INTRTC RTCIF RTCMK RTCPR0, RTCPR1 INTIT ITIF ITMK ITPR0, ITPR1 INTKR KRIF Note 4 INTST3 Note 4 INTCSI30 Note 4 INTIIC30 Note 5 INTSR3 Note 5 INTCSI31 STIF3 KRMK Note 4 Note 4 CSIIF30 Note 4 IICIF30 SRIF3 Note 5 Note 5 CSIIF31 - - - - - - KRPR0, KRPR1 Note 4 STMK3 Note 4 CSIMK30 Note 4 IICMK30 Note 5 SRMK3 Note 5 CSIMK31 Note 4 STPR03, STPR13 - - - - - - - - - - - Note 4 - - - - - - - - - - - Note 4 - - - - - - - - - - - CSIPR030, CSIPR130 IICPR030, IICPR130 Note 5 SRPR03, SRPR13 - - - - - - - - - - - Note 5 - - - - - - - - - - - Note 5 CSIPR031, CSIPR131 INTIIC31 IICIF31 IICMK31 IICPR031, IICPR131 - - - - - - - - - - - INTTM13 TMIF13 TMMK13 TMPR013, TMPR113 - - - - - - - - - - - INTTM04 TMIF04 TMMK04 TMPR004, TMPR104 Note 5 Note 5 Note 5 Notes 1. If one of the interrupt sources INTST1, INTCSI10, and INTIIC10 is generated, bit 0 of the IF1L register is set to 1. Bit 0 of the MK1L, PR01L, and PR11L registers supports these three interrupt sources. 2. If one of the interrupt sources INTSR1, INTCSI11, and INTIIC11 is generated, bit 1 of the IF1L register is set to 1. Bit 1 of the MK1L, PR01L, and PR11L registers supports these three interrupt sources. 3. Do not use UART1 and channel 3 of TAU0 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If one of the interrupt sources INTSRE1 and INTTM03H is generated, bit 2 of the IF1L register is set to 1. Bit 2 of the MK1L, PR01L, and PR11L registers supports these two interrupt sources. 4. If one of the interrupt sources INTST3, INTCSI30, and INTIIC30 is generated, bit 4 of the IF1H register is set to 1. Bit 4 of the MK1H, PR01H, and PR11H registers supports these three interrupt sources. 5. If one of the interrupt sources INTSR3, INTCSI31, and INTIIC31 is generated, bit 5 of the IF1H register is set to 1. Bit 5 of the MK1H, PR01H, and PR11H registers supports these three interrupt sources. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 823 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2. Flags Corresponding to Interrupt Request Sources (4/4) INTTM05 INTTM06 IF2L TMIF05 TMIF06 Register MK2L TMMK05 TMMK06 Register TMPR005, PR02L, TMPR105 PR12L 20-pin 24-pin Register 25-pin 30-pin Priority Specification Flag 32-pin 36-pin 40-pin Interrupt Mask Flag 44-pin 48-pin 52-pin 64-pin Interrupt Request Flag Source 80-pin 100-pin 128-pin Interrupt TMPR006, TMPR106 INTTM07 TMIF07 TMMK07 TMPR007, TMPR107 INTP6 PIF6 PMK6 PPR06, PPR16 - - - - - - - INTP7 PIF7 PMK7 PPR07, PPR17 - - - - - - - - - - INTP8 PIF8 PMK8 PPR08, PPR18 - - - - - - - INTP9 PIF9 PMK9 PPR09, PPR19 - - - - - - - INTP10 PIF10 PMK10 PPR010, PPR110 - - - - - - - - INTP11 PIF11 IF2H MK2H PMK11 PPR011, PPR111 PR02H, - - - - - - - - PR12H - - - - - - - - - - - INTTM10 TMIF10 TMMK10 TMPR010, TMPR110 INTTM11 TMIF11 TMMK11 TMPR011, TMPR111 - - - - - - - - - - - INTTM12 TMIF12 TMPR012, TMPR112 - - - - - - - - - - - Note - - - - - - - - - - - Note INTSRE3 SREIF3 TMMK12 Note SREMK3 INTTM13H TMIF13H Note TMMK13H SREPR03, SREPR13 Note TMPR013H, - - - - - - - - - - - Note Note INTMD MDIF MDMK MDPR0, MDPR1 INTIICA1 IICAIF1 IICAMK1 IICAPR01, IICAPR11 - - - - - - - - - - - INTFL FLIF FLMK FLPR0, FLPR1 INTDMA2 DMAIF2 DMAPR02, DMAPR12 PR03L, - - - - - - - - - - - - - - - - - - - - - - TMPR113H IF3L DMAMK2 MK3L Note INTDMA3 DMAIF3 DMAMK3 DMAPR03, DMAPR13 PR13L INTTM14 TMIF14 TMMK14 TMPR014, TMPR114 - - - - - - - - - - - - - INTTM15 TMIF15 TMMK15 TMPR015, TMPR115 - - - - - - - - - - - - - INTTM16 TMIF16 TMMK16 TMPR016, TMPR116 - - - - - - - - - - - - - INTTM17 TMIF17 TMMK17 TMPR017, TMPR117 - - - - - - - - - - - - - Note Do not use UART3 and channel 3 of TAU1 (at higher 8-bit timer operation) at the same time because they share flags for the interrupt request sources. If one of the interrupt sources INTSRE3 and INTTM13H is generated, bit 4 of the IF2H register is set to 1. Bit 4 of the MK2H, PR02H, and PR12H registers supports these two interrupt sources. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 824 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. The IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, and IF3L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the IF0L and IF0H registers, the IF1L and IF1H registers, and the IF2L and IF2H registers are combined to form 16-bit registers IF0, IF1, and IF2, they can be set by a 16-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (128-pin) (1/2) Address: FFFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF0L PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF <5> <4> <3> <2> <1> <0> DMAIF1 DMAIF0 SREIF2 SRIF2 STIF2 TMIF11H CSIIF21 CSIIF20 IICIF21 IICIF20 <1> <0> Address: FFFE1H After reset: 00H Symbol <7> IF0H SREIF0 SRIF0 STIF0 TMIF01H CSIIF01 CSIIF00 IICIF01 IICIF00 Address: FFFE2H <6> R/W After reset: 00H R/W Symbol <7> <6> <5> <4> <3> IF1L TMIF03 TMIF02 TMIF01 TMIF00 IICAIF0 Address: FFFE3H After reset: 00H Symbol <7> <6> IF1H TMIF04 TMIF13 Address: FFFD0H After reset: 00H <2> SREIF1 SRIF1 STIF1 TMIF03H CSIIF11 CSIIF10 IICIF11 IICIF10 R/W <5> <4> <3> <2> <1> <0> KRIF ITIF RTCIF ADIF SRIF3 STIF3 CSIIF31 CSIIF30 IICIF31 IICIF30 R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF2L PIF10 PIF9 PIF8 PIF7 PIF6 TMIF07 TMIF06 TMIF05 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 825 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (128-pin) (2/2) Address: FFFD1H After reset: 00H R/W Symbol <7> <6> <5> IF2H FLIF IICAIF1 MDIF <4> <3> <2> <1> <0> SREIF3 TMIF12 TMIF11 TMIF10 PIF11 TMIF13H Address: FFFD2H After reset: 00H R/W Symbol 7 6 <5> <4> <3> <2> <1> <0> IF3L 0 0 TMIF17 TMIF16 TMIF15 TMIF14 DMAIF3 DMAIF2 XXIFX Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Cautions 1. The above is the bit layout for the 128-pin prducts. The available bits differ depending on the product. For details about the bits available for each product, see Table 16-2. Be sure to clear bits that are not available to 0. <R> 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a In this case, even if the request flag of the another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. The MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, and MK3L registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the MK0L and MK0H registers, the MK1L and MK1H registers, and the MK2L and MK2H registers are combined to form 16-bit registers MK0, MK1, and MK2, they can be set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 826 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L)(128-pin) Address: FFFE4H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK <5> <4> <3> <2> <1> <0> DMAMK1 DMAMK0 SREMK2 SRMK2 STMK2 TMMK11H CSIMK21 CSIMK20 IICMK21 IICMK20 <1> <0> Address: FFFE5H Symbol MK0H After reset: FFH <7> <6> R/W SREMK0 SRMK0 STMK0 TMMK01H CSIMK01 CSIMK00 IICMK01 IICMK00 Address: FFFE6H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> MK1L TMMK03 TMMK02 TMMK01 TMMK00 IICAMK0 Address: FFFE7H After reset: FFH Symbol <7> 6 MK1H TMMK04 TMMK13 Address: FFFD4H After reset: FFH <2> SREMK1 SRMK1 STMK1 TMMK03H CSIMK11 CSIMK10 IICMK11 IICMK10 R/W 5 4 <3> <2> <1> <0> KRMK ITMK RTCMK ADMK SRMK3 STMK3 CSIMK31 CSIMK30 IICMK31 IICMK30 R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK2L PMK10 PMK9 PMK8 PMK7 PMK6 TMMK07 TMMK06 TMMK05 <4> <3> <2> <1> <0> SREMK3 TMMK12 TMMK11 TMMK10 PMK11 Address: FFFD5H After reset: FFH R/W Symbol <7> <6> <5> MK2H FLMK IICAMK1 MDMK TMMK13H Address: FFFD6H After reset: FFH R/W Symbol 7 6 <5> <4> <3> <2> <1> <0> MK3L 1 1 TMMK17 TMMK16 TMMK15 TMMK14 DMAMK3 DMAMK2 XXMKX Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Caution The above is the bit layout for the 128-pin. The available bits differ depending on the product. For details about the bits available for each product, see Table 16-2. Be sure to set bits that are not available to 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 827 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H). The PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, and the PR13L registers can be set by a 1-bit or 8-bit memory manipulation instruction. If the PR00L and PR00H registers, the PR01L and PR01H registers, the PR02L and PR02H registers, the PR10L and PR10H registers, the PR11L and PR11H registers, and the PR12L and PR12H registers are combined to form 16-bit registers PR00, PR01, PR02, PR10, PR11, and PR12, they can be set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. Figure 16-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (128-pin) (1/3) Address: FFFE8H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR00L PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0 Address: FFFECH After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR10L PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1 <5> <4> <3> <2> <1> <0> DMAPR01 DMAPR00 Address: FFFE9H Symbol PR00H <7> PR10H <6> R/W SREPR00 SRPR00 STPR00 TMPR001H CSIPR001 CSIPR000 IICPR001 IICPR000 Address: FFFEDH Symbol After reset: FFH After reset: FFH <7> <6> <5> <4> <3> DMAPR11 DMAPR10 SREPR10 SRPR10 STPR10 CSIPR101 CSIPR100 IICPR101 IICPR100 After reset: FFH <7> <6> <5> <4> <3> PR01L TMPR003 TMPR002 TMPR001 TMPR000 IICAPR00 After reset: FFH IICPR021 IICPR020 <1> <0> <2> SREPR12 SRPR12 STPR12 TMPR111H CSIPR121 CSIPR120 IICPR121 IICPR120 <1> <0> <2> SREPR01 SRPR01 STPR01 TMPR003H CSIPR011 CSIPR010 IICPR011 IICPR010 <1> <0> R/W Symbol <7> <6> <5> <4> <3> PR11L TMPR103 TMPR102 TMPR101 TMPR100 IICAPR10 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 STPR02 CSIPR020 R/W Symbol Address: FFFEEH SRPR02 CSIPR021 R/W TMPR101H Address: FFFEAH SREPR02 TMPR011H <2> SREPR11 SRPR11 STPR11 TMPR103H CSIPR111 CSIPR110 IICPR111 IICPR110 828 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (128-pin) (2/3) Address: FFFEBH After reset: FFH Symbol <7> <6> PR01H TMPR004 TMPR013 Address: FFFEFH After reset: FFH Symbol <7> <6> PR11H TMPR104 TMPR113 Address: FFFD8H After reset: FFH R/W <5> <4> <3> <2> <1> <0> KRPR0 ITPR0 RTCPR0 ADPR0 <4> <3> <2> <1> <0> KRPR1 ITPR1 RTCPR1 ADPR1 SRPR03 STPR03 CSIPR031 CSIPR030 IICPR031 IICPR030 R/W <5> SRPR13 STPR13 CSIPR131 CSIPR130 IICPR131 IICPR130 R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR02L PPR010 PPR09 PPR08 PPR07 PPR06 TMPR007 TMPR006 TMPR005 Address: FFFDCH After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR12L PPR110 PPR19 PPR18 PPR17 PPR16 TMPR107 TMPR106 TMPR105 4 3 2 1 <0> SREPR03 TMPR012 TMPR011 TMPR010 PPR011 4 3 2 1 <0> SREPR13 TMPR112 TMPR111 TMPR110 PPR111 Address: FFFD9H After reset: FFH R/W Symbol <7> 6 <5> PR02H FLPR0 IICAPR01 MDPR0 TMPR013H Address: FFFDDH After reset: FFH R/W Symbol <7> 6 <5> PR12H FLPR1 IICAPR11 MDPR1 TMPR113H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 829 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (128-pin) (3/3) Address: FFFDAH After reset: FFH R/W Symbol 7 6 <5> <4> <3> <2> <1> <0> PR03L 1 1 TMPR017 TMPR016 TMPR015 TMPR014 DMAPR03 DMAPR02 Address: FFFDEH After reset: FFH R/W Symbol 7 6 <5> <4> <3> <2> <1> <0> PR13L 1 1 TMPR117 TMPR116 TMPR115 TMPR114 DMAPR13 DMAPR12 XXPR1X XXPR0X 0 0 Specify level 0 (high priority level) 0 1 Specify level 1 1 0 Specify level 2 1 1 Specify level 3 (low priority level) Priority level selection Caution The above is the bit layout for the 128-pin. The available bits differ depending on the product. For details about the bits available for each product, see Table 16-2. Be sure to set bits that are not available to 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 830 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers (EGN0, EGN1) These registers specify the valid edge for INTP0 to INTP11. The EGP0, EGP1, EGN0, and EGN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 16-5. Format of External Interrupt Rising Edge Enable Registers (EGP0, EGP1) and External Interrupt Falling Edge Enable Registers (EGN0, EGN1) (128-pin) Address: FFF38H Symbol EGP0 After reset: 00H 6 5 4 3 2 1 0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address: FFF39H Symbol EGN0 R/W 7 After reset: 00H R/W 7 6 5 4 3 2 1 0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 Address: FFF3AH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGP1 0 0 0 0 EGP11 EGP10 EGP9 EGP8 Address: FFF3BH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGN1 0 0 0 0 EGN11 EGN10 EGN9 EGN8 EGPn EGNn 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges INTPn pin valid edge selection (n = 0 to 11) Table 16-3 shows the ports corresponding to the EGPn and EGNn bits. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 831 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Table 16-3. Ports Corresponding to EGPn and EGNn bits Interrupt 64, 80, 100, Request Signal 128-pin Detection Enable Bit 52-pin 48-pin 30, 32, 36, 24, 25-pin 20-pin 40, 44-pin EGP0 EGN0 INTP0 EGP1 EGN1 INTP1 - EGP2 EGN2 INTP2 - - EGP3 EGN3 INTP3 EGP4 EGN4 INTP4 - EGP5 EGN5 INTP5 EGP6 EGN6 INTP6 - - - EGP7 EGN7 INTP7 - - - - - EGP8 EGN8 INTP8 - - - EGP9 EGN9 INTP9 - - - EGP10 EGN10 INTP10 - - - - EGP11 EGN11 INTP11 - - - - Caution Select the port mode by clearing the EGPn and EGNn bits to 0 because an edge may be detected when the external interrupt function is switched to the port function. <R> Remarks 1. 2. For edge detection port, see 2.1 Port Function. n = 0 to 11 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 832 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. Reset signal generation sets PSW to 06H. Figure 16-6. Configuration of Program Status Word PSW <7> <6> <5> <4> IE Z RBS1 AC <3> <2> <1> 0 After reset RBS0 ISP1 ISP0 CY 06H Used when normal instruction is executed ISP1 ISP0 0 0 Priority of interrupt currently being serviced Enables interrupt of level 0 (while interrupt of level 1 or 0 is being serviced). 0 1 1 0 Enables interrupt of level 0 and 1 (while interrupt of level 2 is being serviced). Enables interrupt of level 0 to 2 (while interrupt of level 3 is being serviced). 1 1 Enables all interrupts (waits for acknowledgment of an interrupt). IE R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Interrupt request acknowledgment enable/disable 0 Disabled 1 Enabled 833 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt request acknowledgmentv A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request. The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in Table 16-4 below. For the interrupt request acknowledgment timing, see Figures 16-8 and 16-9. Table 16-4. Time from Generation of Maskable Interrupt Until Servicing Minimum Time Servicing time <R> <R> 9 clocks Note Maximum Time 16 clocks Note Maximum time does not apply when an instruction from the internal RAM area is executed. Remark 1 clock: 1/fCLK (fCLK: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 16-7 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 834 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) xxMK = 0? No Yes Interrupt request held pending (xxPR1, xxPR0) (ISP1, ISP0) No (Low priority) Interrupt request held pending Higher priority than other interrupt requests simultaneously generated? No Interrupt request held pending Yes Higher default priorityNote than other interrupt requests simultaneously generated? No Interrupt request held pending Yes IE = 1? Yes No Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR0: Priority specification flag 0 xxPR1: Priority specification flag 1 IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable) ISP0, ISP1: Flag that indicates the priority level of the interrupt currently being serviced (see Figure 16-6) Note For the default priority, refer to Table 16-1 Interrupt Source List. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 835 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction PSW and PC saved, jump to interrupt servicing Instruction Interrupt servicing program xxIF <R> 9 clocks Remark 1 clock: 1/fCLK (fCLK: CPU clock) Figure 16-9. Interrupt Request Acknowledgment Timing (Maximum Time) CPU processing Instruction 8 clocks 6 clocks Previous interrupt instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF <R> 16 clocks Remark 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 836 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS 16.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Can not use the RETI instruction for restoring from the software interrupt. 16.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 16-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 16-10 shows multiple interrupt servicing examples. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 837 RL78/G13 <R> CHAPTER 16 INTERRUPT FUNCTIONS Table 16-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Priority Level 0 (PR = 00) Priority Level 2 (PR = 10) Priority Level 3 (PR = 11) Software Interrupt Request IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0 ISP1 = 0 ISP0 = 0 { x x x x x x x { ISP1 = 0 ISP0 = 1 { x { x x x x x { ISP1 = 1 ISP0 = 0 { x { x { x x x { { x { x { x { x { Interrupt Being Serviced Maskable interrupt Priority Level 1 (PR = 01) Software interrupt Remarks 1. {: Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. ISP0, ISP1, and IE are flags contained in the PSW. ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced. ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced. ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced. ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment. IE = 0: Interrupt request acknowledgment is disabled. IE = 1: Interrupt request acknowledgment is enabled. 4. PR is a flag contained in the PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H registers. PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 838 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing IE = 0 EI INTyy servicing IE = 0 IE = 0 EI INTxx (PR = 11) INTzz servicing EI INTyy (PR = 10) INTzz (PR = 01) RETI IE = 1 IE = 1 RETI RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing EI INTxx servicing INTyy servicing IE = 0 EI INTxx (PR = 10) INTyy (PR = 11) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) IE = 0: Interrupt request acknowledgment is disabled IE = 1: Interrupt request acknowledgment is enabled. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 839 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 EI INTxx (PR = 11) INTyy (PR = 00) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) IE = 0: Interrupt request acknowledgment is disabled IE = 1: Interrupt request acknowledgment is enabled. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 840 RL78/G13 CHAPTER 16 INTERRUPT FUNCTIONS <R> 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV PSW, A * MOV1 PSW. bit, CY * SET1 PSW. bit * CLR1 PSW. bit * RETB * RETI * POP PSW * BTCLR PSW. bit, $addr20 * EI * DI * SKC * SKNC * SKZ * SKNZ * SKH * SKNH * Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, and PR13L registers Figure 16-11 shows the timing at which interrupt requests are held pending. Figure 16-11. Interrupt Request Hold CPU processing Instruction N Instruction M PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 841 RL78/G13 CHAPTER 17 KEY INTERRUPT FUNCTION CHAPTER 17 KEY INTERRUPT FUNCTION The number of key interrupt input channels differs, depending on the product. 20, 24, 25, 30, 32, 36- 40, 44-pin 48-pin - Key interrupt input channels 52, 64, 80, 100, 128pin pin 4 ch 6 ch 8 ch 17.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 17-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0 Controls KR0 signal in 1-bit units. KRM1 Controls KR1 signal in 1-bit units. KRM2 Controls KR2 signal in 1-bit units. KRM3 Controls KR3 signal in 1-bit units. KRM4 Controls KR4 signal in 1-bit units. KRM5 Controls KR5 signal in 1-bit units. KRM6 Controls KR6 signal in 1-bit units. KRM7 Controls KR7 signal in 1-bit units. 17.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 17-2. Configuration of Key Interrupt Item Control register Remark Configuration Key return mode register (KRM) KR0 to KR3: 40, 44-pin products KR0 to KR5: 48-pin products KR0 to KR7: 52, 64, 80, 100, 128-pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 842 RL78/G13 CHAPTER 17 KEY INTERRUPT FUNCTION Figure 17-1. Block Diagram of Key Interrupt KR7 KR6 KR5 KR4 INTKR KR3 KR2 KR1 KR0 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode register (KRM) Remark KR0 to KR3: 40-, 44-pin products KR0 to KR5: 48-pin products KR0 to KR7: 52-, 64-, 80-, 100-, 128-pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 843 RL78/G13 CHAPTER 17 KEY INTERRUPT FUNCTION 17.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) KRM register controls the KR0 to KR7 signals. The KRM register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 17-2. Format of Key Return Mode Register (KRM) <R> Address: FFF37H 7 6 5 4 3 2 KRM6 KRM5 KRM4 KRM3 KRM2 KRMn <R> bits 7 to 5, 1, 0 : R/W, bits 4 to 2 : R KRM7 Symbol KRM After reset: 00H 0 KRM1 KRM0 Key interrupt mode control 0 Does not detect key interrupt signal 1 Detects key interrupt signal Cautions 1. Set the bit corresponding to the key interrupt input pins PU70 to PU77 (bits 0 to 7 of the pull-up resistor register 7 (PU7)). 2. An interrupt will be generated if the target bit of the KRM register is set while a low level is being input to the key interrupt input pin. To ignore this interrupt, set the KRM register after disabling interrupt servicing by using the interrupt mask flag. Afterward, clear the interrupt request flag <R> and enable interrupt servicing after waiting for the key interrupt input low-level width (when 1.8 V EVDD0 5.5 V, 250 ns or more, when 1.6 V EVDD0 < 1.8 V, 1 s or more). 3. The pins not used in the key interrupt mode can be used as normal ports. Remarks 1. n = 0 to 7 2. KR0 to KR3: 40-, 44-pin products KR0 to KR5: 48-pin products KR0 to KR7: 52-, 64-, 80-, 100-, 128-pin products R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 844 RL78/G13 CHAPTER 18 STANDBY FUNCTION CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function and Configuration 18.1.1 Standby function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the highspeed system clock oscillator, high-speed on-chip oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and high-speed on-chip oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. (3) SNOOZE mode In the case of CSIp or UARTq data reception and an A/D conversion request by the timer trigger signal (the interrupt request signal (INTRTC/INTIT)), the STOP mode is exited, the CSIp or UARTq data is received without operating the CPU, and A/D conversion is performed. This can only be specified when the high-speed on-chip oscillator is selected for the CPU/peripheral hardware clock (fCLK). In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The STOP mode cannot be set while the CPU operates with the subsystem clock. The HALT mode can be used when the CPU is operating on either the main system clock or the subsystem clock. 2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating 3. When using CSIp, UARTq, or the A/D converter in the SNOOZE mode, set up serial standby with main system clock before executing STOP instruction (except SNOOZE mode setting unit). control register m (SSCm) and A/D converter mode register 2 (ADM2) before switching to the STOP mode. For details, see 12.3 Registers Controlling Serial Array Unit and 11.3 Registers Used in A/D Converter. 4. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of A/D converter mode register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the STOP instruction. 5. It can be selected by the option byte whether the low-speed on-chip oscillator continues oscillating or stops in the HALT or STOP mode. For details, see CHAPTER 24 OPTION BYTE. Remark 20 to 64-pin products: 80 to 128-pin products: R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 p = 00; q = 0; m = 0 p = 00, 20; q = 0, 2; m = 0, 1 845 RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 846 RL78/G13 CHAPTER 18 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case. * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POR, LVD, WDT, and executing an illegal instruction), the STOP instruction and MSTOP bit (bit 7 of clock operation status control register (CSC)) = 1 clear this register to 00H. Figure 18-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H Symbol OSTC 7 After reset: 00H 6 5 R 4 3 2 1 0 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 Oscillation stabilization time status MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 0 0 0 0 0 0 0 fX = 10 MHz fX = 20 MHz 0 2 /fX max. 25.6 s max. 12.8 s max. 8 1 0 0 0 0 0 0 0 2 /fX min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 /fX min. 51.2 s min. 25.6 s min. 8 9 1 1 1 0 0 0 0 0 2 /fX min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 /fX min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 /fX min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 /fX min. 3.27 ms min. 1 1 1 1 1 1 1 0 2 /fX min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 /fX min. 26.21 ms min. 13.11 ms min. 10 11 13 15 1.64 ms min. 17 18 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register (OSTS). If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC register oscillation stabilization time Oscillation stabilization time set by OSTS register Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 847 RL78/G13 CHAPTER 18 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using the OSTS register after the STOP mode is released. When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using the OSTC register. The OSTS register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 07H. Figure 18-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz fX = 20 MHz 0 0 0 2 /fX 25.6 s 12.8 s 0 0 1 2 /fX 9 51.2 s 25.6 s 10 102.4 s 51.2 s 11 204.8 s 102.4 s 13 819.2 s 409.6 s 15 3.27 ms 1.64 ms 17 13.11 ms 6.55 ms 18 26.21 ms 13.11 ms 8 0 1 0 2 /fX 0 1 1 2 /fX 1 0 0 2 /fX 1 0 1 2 /fX 1 1 0 2 /fX 1 1 1 2 /fX Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before executing the STOP instruction. 2. Before changing the setting of the OSTS register, confirm that the count operation of the OSTC register is completed. 3. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 4. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the OSTS register. If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC register oscillation stabilization time Oscillation stabilization time set by OSTS register Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after STOP mode is released. 5. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 848 RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.2 Standby Function Operation 18.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, or subsystem clock. The operating statuses in the HALT mode are shown below. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 849 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on High-speed On-chip Oscillator Clock (fIH) Item System clock When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEX) Clock supply to the CPU is stopped Main system clock fIH Operation continues (cannot be stopped) Operation disabled fX Operation disabled Operation continues (cannot be stopped) Cannot operate Cannot operate Operation continues (cannot be stopped) fEX Subsystem clock fXT Status before HALT mode was set is retained fEXT fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) * WUTMMCK0 = 1: Oscillates * WUTMMCK0 = 0 and WDTON = 0: Stops * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops CPU Operation stopped Code flash memory Operation stopped Data flash memory RAM Port (latch) Status before HALT mode was set is retained Timer array unit Operable Real-time clock (RTC) 12-bit interval timer Watchdog timer See CHAPTER 10 WATCHDOG TIMER Clock output/buzzer output Operable A/D converter Serial array unit (SAU) Serial interface (IICA) Multiplier and divider/multiplyaccumulator DMA controller Power-on-reset function Voltage detection function External interrupt Key interrupt function CRC <R> operation function High-speed CRC General-purpose CRC RAM parity error detection function In the calculation of the RAM area, operable when DMA is executed only Operable when DMA is executed only RAM guard function SFR guard function Illegal-memory access detection function Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode. Operation disabled: Operation is stopped before switching to the HALT mode. fIH: High-speed on-chip oscillator clock fEX: External main system clock fIL: Low-speed on-chip oscillator clock fXT: XT1 clock fX: X1 clock fEXT: External subsystem clock R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 850 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting Item When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (fXT) System clock When CPU Is Operating on External Subsystem Clock (fEXT) Clock supply to the CPU is stopped Main system clock fIH Operation disabled fX fEX Subsystem clock fXT Operation continues (cannot be stopped) Cannot operate fEXT Cannot operate Operation continues (cannot be stopped) fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) * WUTMMCK0 = 1: Oscillates * WUTMMCK0 = 0 and WDTON = 0: Stops * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops CPU Operation stopped Code flash memory Data flash memory RAM Port (latch) Status before HALT mode was set is retained Timer array unit Operable (Operation is disabled while in the low consumption RTC mode (when the RTCLPC bit of the OSMC register is 1)) Real-time clock (RTC) Operable 12-bit interval timer Watchdog timer See CHAPTER 10 WATCHDOG TIMER Clock output/buzzer output Operable (Operation is disabled while in the low consumption RTC mode (when the RTCLPC bit of the OSMC register is 1)) A/D converter Operation disabled Serial array unit (SAU) Operable (Operation is disabled while in the low consumption RTC mode (when the RTCLPC bit of the OSMC register is 1)) Serial interface (IICA) Operation disabled Multiplier and divider/multiplyaccumulator Operable (Operation is disabled while in the low consumption RTC mode (when the RTCLPC bit of the OSMC register is 1)) DMA controller Power-on-reset function Operable Voltage detection function External interrupt Key interrupt function CRC <R> operation function High-speed CRC Operation disabled General-purpose CRC In the calculation of the RAM area, operable when DMA is executed only RAM parity error detection function Operable when DMA is executed only RAM guard function SFR guard function Illegal-memory access detection function Remark Operation stopped: Operation disabled: Operation is automatically stopped before switching to the HALT mode. Operation is stopped before switching to the HALT mode. fIH: High-speed on-chip oscillator clock fEX: External main system clock fIL: Low-speed on-chip oscillator clock fXT: XT1 clock fX: X1 clock fEXT: External subsystem clock R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 851 RL78/G13 CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-3. HALT Mode Release by Interrupt Request Generation HALT instruction Interrupt request Standby release signal Note 1 Status of CPU Operating mode Notes 1. <R> 2. Operating mode Oscillation High-speed system clock, High-speed on-chip oscillator clock, or subsystem clock <R> Wait Note 2 HALT mode For details of the standby release signal, see Figure 16-1 Wait time for HALT mode release * When vectored interrupt servicing is carried out Main system clock: 15 to 16 clock Subsystem clock (RTCLPC = 0): 10 to 11 clock Subsystem clock (RTCLPC = 1): 11 to 12 clock * When vectored interrupt servicing is not carried out Main system clock: Remark 9 to 10 clock Subsystem clock (RTCLPC = 0): 4 to 5 clock Subsystem clock (RTCLPC = 1): 5 to 6 clock The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 852 RL78/G13 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-4. HALT Mode Release by Reset (1) When high-speed system clock is used as CPU clock HALT instruction Reset processing Note Reset signal Normal operation (high-speed system clock) Status of CPU High-speed system clock (X1 oscillation) HALT mode Normal operation (high-speed on-chip oscillator clock) Reset period Oscillation Oscillation stopped stopped Oscillates Oscillates Oscillation stabilization time (check by using OSTC register) Starting X1 oscillation is specified by software. When high-speed on-chip oscillator clock is used as CPU clock HALT instruction Reset signal Reset processing Note Normal operation (high-speed on-chip Status of CPU oscillator clock) HALT mode Oscillates High-speed on-chip oscillator clock Normal operation (high-speed on-chip oscillator clock) Reset period Oscillation stopped Oscillates Wait for oscillation accuracy stabilization (3) When subsystem clock is used as CPU clock HALT instruction Reset processing Note Reset signal Status of CPU Normal operation (subsystem clock) Subsystem clock (XT1 oscillation) Oscillates Normal operation mode (high-speed on-chip oscillator clock) Reset period Oscillation Oscillation stopped stopped Oscillates Oscillation stabilization time (check by using OSTC register) Starting XT1 oscillation is specified by software. <R> <R> HALT mode Note Reset processing time: 388 to 673 s (When LVD is used) 156 to 360 s (When LVD off) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 853 RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the high-speed on-chip oscillator clock, X1 clock, or external main system clock. Cautions 1. Because the interrupt request signal is used to clear the STOP mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the STOP mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. 2. When using CSIp, UARTq, or the A/D converter in the SNOOZE mode, set up serial standby control register m (SSCm) and A/D converter mode register 2 (ADM2) before switching to the STOP mode. For details, see 12.3 Registers Controlling Serial Array Unit and 11.3 Registers Used in A/D Converter. Remark 20 to 64-pin products: p = 00; q = 0; m = 0 80 to 128-pin products: p = 00, 20; q = 0, 2; m = 0, 1 The operating statuses in the STOP mode are shown below. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 854 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock Item When CPU Is Operating on High-speed on-chip oscillator clock (fIH) System clock Clock supply to the CPU is stopped Main system clock fIH When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEX) Stopped fX fEX Subsystem clock fXT Status before STOP mode was set is retained fEXT fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) * WUTMMCK0 = 1: Oscillates * WUTMMCK0 = 0 and WDTON = 0: Stops * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops Operation stopped CPU Code flash memory <R> Data flash memory RAM Operation stopped Operation stopped Port (latch) Status before STOP mode was set is retained Timer array unit Operation disabled Real-time clock (RTC) Operable 12-bit interval timer Watchdog timer <R> Clock output/buzzer output See CHAPTER 10 WATCHDOG TIMER Operable only when subsystem clock is selected as the count clock (when low-consumption RTC mode (set RTCLPC bit of OSMC register to 1), operation disabled) A/D converter Wakeup operation is enabled (switching to the SNOOZE mode) Serial array unit (SAU) Wakeup operation is enabled only for CSIp and UARTq (switching to the SNOOZE mode) Operation is disabled for anything other than CSIp and UARTq Serial interface (IICA) Wakeup by address match operable Multiplier and divider/multiplyaccumulator Operation disabled DMA controller Power-on-reset function Operable Voltage detection function External interrupt Key interrupt function High-speed CRC CRC operation function Operation stopped General-purpose CRC <R> RAM parity error detection function RAM guard function SFR guard function Illegal-memory access detection function Remarks 1. 2. Operation stopped: Operation is automatically stopped before switching to the STOP mode. Operation disabled: Operation is stopped before switching to the STOP mode. fIL: Low-speed on-chip oscillator clock fIH: High-speed on-chip oscillator clock fEX: External main system clock fX: X1 clock fEXT: External subsystem clock fXT: XT1 clock 20 to 64-pin products: p = 00; q = 0 80 to 128-pin products: p = 00, 20; q = 0, 2 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 855 RL78/G13 CHAPTER 18 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. To stop the low-speed on-chip oscillator clock in the STOP mode, must previously be set an option byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0). 3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the highspeed on-chip oscillator clock before the execution of the STOP instruction. Before changing the CPU clock from the high-speed on-chip oscillator clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC). (2) STOP mode release The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-5. STOP Mode Release by Interrupt Request Generation (1/2) (1) When high-speed system clock (X1 oscillation) is used as CPU clock STOP instruction Interrupt request Standby release signal Note 1 Status of CPU STOP mode Oscillates Oscillation stopped High-speed system clock (X1 oscillation) <R> Notes 1. <R> 2. STOP mode release time Note 2 Normal operation (high-speed system clock) Supply of the clock is stopped Wait Normal operation (high-speed system clock) Oscillates For details of the standby release signal, see Figure 16-1 STOP mode release time Supply of the clock is stopped: 18.96 s to "whichever is longer 28.95 s and the oscillation stabilization time (set by OSTS)" Wait * When vectored interrupt servicing is carried out: 10 to 11 clocks * When vectored interrupt servicing is not carried out: 4 to 5 clocks Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 856 RL78/G13 CHAPTER 18 STANDBY FUNCTION Figure 18-5. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (external clock input) is used as CPU clock Interrupt request STOP instruction Standby release signal Note 1 Status of CPU STOP mode release time Note 2 Normal operation (high-speed system clock) STOP mode Oscillates Oscillation stopped High-speed system clock (X1 oscillation) Supply of the clock is stopped Wait Normal operation (high-speed system clock) Oscillates (3) When high-speed on-chip oscillator clock is used as CPU clock STOP instruction Interrupt request Standby release signal Note 1 Status of CPU STOP mode release time Note 2 Normal operation (high-speed on-chip oscillator clock) STOP mode Oscillates Oscillation stopped High-speed on-chip oscillator clock Supply of the clock is stopped Wait Normal operation (high-speed on-chip oscillator clock) Oscillates Wait for oscillation accuracy stabilization <R> Notes 1. <R> 2. For details of the standby release signal, see Figure 16-1 STOP mode release time Supply of the clock is stopped: 19.08 to 32.99 s Wait * When vectored interrupt servicing is carried out: 7 clocks * When vectored interrupt servicing is not carried out: 1 clock Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 857 RL78/G13 CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-6. STOP Mode Release by Reset (1) When high-speed system clock is used as CPU clock STOP instruction Reset signal Status of CPU Reset processing Note Normal operation (high-speed system clock) High-speed system clock (X1 oscillation) STOP mode Oscillation stopped Oscillates Normal operation (high-speed on-chip oscillator clock) Reset period Oscillation Oscillation stopped stopped Oscillates Oscillation stabilization time (Check by using OSTC register) Starting X1 oscillation is specified by software. (2) When high-speed on-chip oscillator clock is used as CPU clock STOP instruction Reset signal Status of CPU High-speed on-chip oscillator clock Reset processing Note Normal operation (high-speed on-chip oscillator clock) Oscillates STOP mode Reset period Oscillation Oscillation stopped stopped Normal operation (high-speed on-chip oscillator clock) Oscillates Wait for oscillation accuracy stabilization <R> Note Reset processing time: 388 to 673 s (When LVD is used) 156 to 360 s (When LVD off) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 858 RL78/G13 CHAPTER 18 STANDBY FUNCTION 18.2.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSIp, UARTq, or the A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock. When using CSIp or UARTq in the SNOOZE mode, set up serial standby control register m (SSCm) before switching to the STOP mode. For details, see 12.3 Registers Controlling Serial Array Unit. When using the A/D converter in the SNOOZE mode, set up A/D converter mode register 2 (ADM2) before switching to the STOP mode. For details, see 11.3 Registers Used in A/D Converter. Remark 20 to 64-pin products: p = 00; q = 0; m = 0 80 to 128-pin products: p = 00, 20; q = 0, 2; m = 0, 1 <R> In SNOOZE mode transition, wait status to be only following time. From STOP to SNOOZE HS (High-speed main) mode : 18.96 to 28.95 s LS (Low-speed main) mode : 20.24 to 28.95 s LV (Low-voltage main) mode : 20.98 to 28.95 s From SNOOZE to normal operation * When vectored interrupt servicing is carried out: HS (High-speed main) mode : 6.79 to 12.4 s + 7 clocks LS (Low-speed main) mode : 2.58 to 7.8 s + 7 clocks LV (Low-voltage main) mode : 12.45 to 17.3 s + 7 clocks * When vectored interrupt servicing is not carried out: HS (High-speed main) mode : 6.79 to 12.4 s + 1 clock LS (Low-speed main) mode : 2.58 to 7.8 s + 1 clock LV (Low-voltage main) mode : 12.45 to 17.3 s + 1 clock The operating statuses in the SNOOZE mode are shown below. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 859 RL78/G13 CHAPTER 18 STANDBY FUNCTION Table 18-3. Operating Statuses in SNOOZE Mode STOP Mode Setting When Inputting CSIp/UARTq Data Reception Signal or A/D Converter Timer Trigger Signal While in STOP Mode Item When CPU Is Operating on High-speed on-chip oscillator clock (fIH) System clock Clock supply to the CPU is stopped Main system clock fIH Operation started fX Stopped fEX Subsystem clock fXT Use of the status while in the STOP mode continues fEXT fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) * WUTMMCK0 = 1: Oscillates * WUTMMCK0 = 0 and WDTON = 0: Stops * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops CPU Operation stopped Code flash memory Data flash memory RAM Port (latch) Use of the status while in the STOP mode continues Timer array unit Operation disabled Real-time clock (RTC) Operable 12-bit interval timer Watchdog timer <R> Clock output/buzzer output See CHAPTER 10 WATCHDOG TIMER Operable only when subsystem clock is selected as the count clock (when low-consumption RTC mode (set RTCLPC bit of OSMC register to 1), operation disabled) A/D converter Operable Serial array unit (SAU) Operable only CSIp and UARTq only. Operation disabled other than CSIp and UARTq. Serial interface (IICA) Operation disabled Multiplier and divider/multiplyaccumulator DMA controller Power-on-reset function Operable Voltage detection function External interrupt Key interrupt function CRC operation function Operation disabled <R> RAM parity error detection function RAM guard function SFR guard function Illegal-memory access detection function Remarks 1. Operation stopped: Operation disabled: Operation is automatically stopped before switching to the SNOOZE mode. Operation is stopped before switching to the SNOOZE mode. fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock fX: X1 clock fEX: External main system clock fEXT: External subsystem clock fXT: XT1 clock 2. 20 to 64-pin products: p = 00; q = 0 80 to 128-pin products: p = 00, 20; q = 0, 2 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 860 RL78/G13 CHAPTER 19 RESET FUNCTION CHAPTER 19 RESET FUNCTION The following seven operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit (4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage (5) Internal reset by execution of illegal instructionNote (6) Internal reset by RAM parity error (7) Internal reset by illegal-memory access External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is generated. A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD circuit voltage detection, execution of illegal instructionNote, RAM parity error or illegal-memory access, and each item of hardware is set to the status shown in Tables 19-1. When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the high-speed on-chip oscillator clock (see Figures 19-2 to 19-4) after reset processing. Reset by POR and LVD circuit supply voltage detection is automatically released when VDD VPOR or VDD VLVD after the reset, and program execution starts using the high-speed on-chip oscillator clock (see CHAPTER 20 POWER-ON-RESET CIRCUIT and CHAPTER 21 VOLTAGE DETECTOR) after reset processing. Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. (To perform an external reset upon power application, a low level of at least 10 s must be continued during the period in which the supply voltage is within the operating range (VDD 1.6 V).) 2. During reset input, the X1 clock, XT1 clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock stop oscillating. External main system clock input and external subsystem clock input become invalid. 3. When reset is effected, port pin P130 is set to low-level output and other port pins become highimpedance, because each SFR and 2nd SFR are initialized. Remark VPOR: POR power supply rise detection voltage R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 861 RL78/G13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Figure 19-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) TRAP Watchdog timer reset signal Set WDTRF Set Clear Clear RPERF Set LVIRF IAWRF Set Clear Set Clear Clear Reset signal by execution of illegal instruction Reset signal by RAM parity error Reset signal by illegal-memory access RESF register read signal RESET Reset signal to LVIM/LVIS register Power-on reset circuit reset signal Caution An LVD circuit internal reset does not reset the LVD circuit. Remarks 1. LVIM: Voltage detection register 2. LVIS: Voltage detection level register Reset signal 862 CHAPTER 19 RESET FUNCTION Voltage detector reset signal RL78/G13 CHAPTER 19 RESET FUNCTION Figure 19-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization High-speed on-chip oscillator clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset period CPU status <R> Normal operation (high-speed on-chip oscillator clock) Normal operation Reset processing : 388 to 673 s (When LVD is used) 156 to 360 s (When LVD off) RESET Internal reset signal Delay Port pin (except P130) Hi-Z Port pin (P130) Note Figure 19-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow Wait for oscillation accuracy stabilization High-speed on-chip oscillator clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU status Normal operation Reset period (oscillation stop) Reset processing Normal operation (high-speed on-chip oscillator clock) 41 to 69 s Execution of Illegal Instruction/ Watchdog timer overflow Internal reset signal Port pin (except P130) Port pin (P130) Hi-Z Note Note When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummy-output as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a reset signal to an external device, set P130 to high-level output by software. Caution A watchdog timer internal reset resets the watchdog timer. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 863 RL78/G13 CHAPTER 19 RESET FUNCTION Figure 19-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization STOP instruction execution High-speed on-chip oscillator clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU status Normal operation Stop status (oscillation stop) Reset period Normal operation (high-speed on-chip oscillator clock) RESET <R> Reset processing: 388 to 673 s (When LVD is used) 156 to 360 s (When LVD off) Internal reset signal Delay Port pin (except P130) Port pin (P130) Hi-Z Note Note When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummy-output as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a reset signal to an external device, set P130 to high-level output by software. Remark For the reset timing of the power-on-reset circuit and voltage detector, see CHAPTER 20 POWER-ONRESET CIRCUIT and CHAPTER 21 VOLTAGE DETECTOR. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 864 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Subsystem clock fIH Operation stopped fX Operation stopped (the X1 and X2 pins are input port mode) fEX Clock input invalid (the pin is input port mode) fXT Operation stopped (the XT1 and XT2 pins are input port mode) fEXT Clock input invalid (the pin is input port mode) Operation stopped fIL CPU Code flash memory Operation stopped Data flash memory Operation stopped RAM Operation stopped <R> Port (latch) Set P130 to low-level output. The port pins except for P130 become high impedance. Set P40 to pull-up (pin reset, reset except POC reset), become high impedance. Operation stopped Timer array unit Real-time clock (RTC) 12-bit interval timer Watchdog timer Clock output/buzzer output A/D converter Serial array unit (SAU) Serial interface (IICA) Multiplier & divider, multiplyaccumulator DMA controller Power-on-reset function Detection operation possible Voltage detection function Operation stopped External interrupt Operation stopped Key interrupt function CRC High-speed CRC operation General-purpose CRC function RAM parity error detection function RAM guard function SFR guard function Illegal-memory access detection function Remark fIH: fX: High-speed on-chip oscillator clock X1 oscillation clock fEX: External main system clock fXT: XT1 oscillation clock fEXT: External subsystem clock fIL: Low-speed on-chip oscillator clock R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 865 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (1/4) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 06H RAM Data memory Undefined General-purpose registers Undefined Processor mode control register (PMC) 00H Port registers (P0 to P15) (output latches) 00H Port mode registers (PM0 to PM12, PM14, PM15) FFH Port mode control registers (PMC0 to PMC3, PMC10, PMC11, PMC12, PMC14) FFH Port input mode registers (PIM0, PIM1, PIM4, PIM5, PIM8, PIM14) 00H Port output mode registers (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) 00H Pull-up resistor option registers (PU0, PU1, PU3 to PU12, PU14) 00H (PU4 is 01H) Peripheral I/O redirection register (PIOR) 00H Clock operation mode control register (CMC) 00H Clock operation status control register (CSC) C0H System clock control register (CKC) 00H Oscillation stabilization time counter status register (OSTC) 00H Oscillation stabilization time select register (OSTS) 07H Noise filter enable registers 0, 1, 2 (NFEN0, NFEN1, NFEN2) 00H Peripheral enable register 0 (PER0) 00H High-speed on-chip oscillator frequency select register (HOCODIV) Undefined High-speed on-chip oscillator trimming register (HIOTRM) Note 2 Operation speed mode control register (OSMC) 00H Timer array unit Timer data registers 00 to 07, 10 to 17 (TDR00 to TDR07, TDR10 to TDR17) 0000H Timer mode registers 00 to 07, 10 to 17 (TMR00 to TMR07, TMR10 to TMR17) 0000H Timer status registers 00 to 07, 10 to 17 (TSR00 to TSR07, TSR10 to TSR17) 0000H Timer input select register 0, 1 (TIS0, TIS1) 00H Timer counter registers 00 to 07, 10 to 17 (TCR00 to TCR07, TCR10 to TCR17) FFFFH Notes 1. Timer channel enable status register 0, 1 (TE0, TE1) 0000H Timer channel start register 0, 1 (TS0, TS1) 0000H Timer channel stop register 0, 1 (TT0, TT1) 0000H Timer clock select register 0, 1 (TPS0, TPS1) 0000H Timer output register 0, 1 (TO0, TO1) 0000H Timer output enable register 0, 1 (TOE0, TOE1) 0000H Timer output level register 0, 1 (TOL0, TOL1) 0000H Timer output mode registers 0, 1 (TOM0, TOM1) 0000H During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. Remark The reset value differs for each chip. The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers (SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 866 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (2/4) Hardware Real-time clock Status After Reset Note 1 Acknowledgment Second count register (SEC) 00H Minute count register (MIN) 00H Hour count register (HOUR) 12H Week count register (WEEK) 00H Day count register (DAY) 01H Month count register (MONTH) 01H Year count register (YEAR) 00H Watch error correction register (SUBCUD) 00H Alarm minute register (ALARMWM) 00H Alarm hour register (ALARMWH) 12H Alarm week register ALARMWW) 00H Control register 0 (RTCC0) 00H Control register 1 (RTCC1) 00H 12-bit interval timer Control register (ITMC) 0FFFH Clock output/buzzer Clock output select registers 0, 1 (CKS0, CKS1) 00H Watchdog timer Enable register (WDTE) 1AH/9AH A/D converter 10-bit A/D conversion result register (ADCR) 0000H 8-bit A/D conversion result register (ADCRH) 00H output controller Serial array unit (SAU) Notes 1. Note 2 Mode registers 0 to 2 (ADM0 to ADM2) 00H Conversion result comparison upper limit setting register (ADUL) FFH Conversion result comparison lower limit setting register (ADLL) 00H A/D test register (ADTES) 00H Analog input channel specification register (ADS) 00H A/D port configuration register (ADPC) 00H Serial data registers 00 to 03, 10 to 13 (SDR00 to SDR03, SDR10 to SDR13) 0000H Serial status registers 00 to 03, 10 to 13 (SSR00 to SSR03, SSR10, SSR13) 0000H Serial flag clear trigger registers 00 to 03, 10 to 13 (SIR00 to SIR03, SIR10, SIR13) 0000H Serial mode registers 00 to 03, 10 to 13 (SMR00 to SMR03, SMR10, SMR13) 0020H Serial communication operation setting registers 00 to 03, 10 to 13 (SCR00 to SCR03, SCR10 to SCR13) 0087H Serial channel enable status registers 0, 1 (SE0, SE1) 0000H Serial channel start registers 0, 1 (SS0, SS1) 0000H Serial channel stop registers 0, 1 (ST0, ST1) 0000H Serial clock select registers 0, 1 (SPS0, SPS1) 0000H Serial output registers 0, 1 (SO0, SO1) 0F0FH Serial output enable registers 0, 1 (SOE0, SOE1) 0000H Serial output level registers 0, 1 (SOL0, SOL1) 0000H Serial standby control register 0, 1 (SSC0, SSC1) 0000H Input switch control register (ISC) 00H During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. Remark The reset value of WDTE is determined by the option byte setting. The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers (SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 867 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (3/4) Hardware Serial interface IICA Status After Reset Note 1 Acknowledgment IICA shift register 0, 1 (IICA0, IICA1) 00H IICA status register 0, 1 (IICS0, IICS1) 00H IICA flag register 0, 1 (IICF0, IICF1) 00H IICA control register 00, 10 (IICCTL00, IICCTL10) 00H IICA control register 01, 11 (IICCTL01, IICCTL11) 00H IICA low-level width setting register 0, 1 (IICWL0, IICWL1) FFH IICA high-level width setting register 0, 1 (IICWH0, IICWH1) FFH Slave address register 0, 1 (SVA0, SVA1) 00H Multiplier & divider, Multiplication/division data register A (L) (MDAL) 0000H multiply-accumulator Multiplication/division data register A (H) (MDAH) 0000H Multiplication/division data register B (L) (MDBL) 0000H Multiplication/division data register B (H) (MDBH) 0000H Multiplication/division data register C (L) (MDCL) 0000H Multiplication/division data register C (H) (MDCH) 0000H Multiplication/division control register (MDUC) 00H Key return mode register (KRM) 00H Key interrupt Note During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. Remark The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers (SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 868 RL78/G13 CHAPTER 19 RESET FUNCTION Table 19-2. Hardware Statuses After Reset Acknowledgment (4/4) Hardware Status After Reset Acknowledgment Note 2 Reset function Reset control flag register (RESF) Undefined Voltage detector (LVD) Voltage detection register (LVIM) 00H Voltage detection level register (LVIS) 00H/01H/81H SFR address registers 0 to 3 (DSA0 to DSA3) 00H RAM address registers 0 to 3 (DRA0 to DRA3) 0000H Byte count registers 0 to 3 (DBC0 to DBC3) 0000H Mode control registers 0 to 3 (DMC0 to DMC3) 00H Operation control registers 0 to 3 (DRC0 to DRC3) 00H Request flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L (IF0L, IF0H, IF1L, 00H DMA controller Interrupt Note 1 Note 2 Notes 2, 3 IF1H, IF2L, IF2H, IF3L) Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L (MK0L, MK0H, MK1L, FFH MK1H, MK2L, MK2H, MK3L) Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 03L, FFH 10L, 10H, 11L, 11H, 12L, 12H, 13L (PR00L, PR00H, PR01L, PR01H, PR10L, PR10H, PR11L, PR11H, PR02L, PR02H, PR12L, PR12H, PR03L, PR13L) External interrupt rising edge enable registers 0, 1 (EGP0, EGP1) 00H External interrupt falling edge enable registers 0, 1 (EGN0, EGN1) 00H Flash memory CRC control register (CRC0CTL) 00H Flash memory CRC operation result register (PGCRCL) 0000H CRC input register (CCRIN) 00H CRC data register (CRCD) 0000H Invalid memory access detection control register (IAWCTL) 00H RAM parity error control register (RPECTL) 00H Flash memory Data flash control register (DFLCTL) 00H BCD correction circuit BCD correction result register (BCDAJ) Undefined Safety functions (Notes and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 869 RL78/G13 Notes 1. CHAPTER 19 RESET FUNCTION During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. These values vary depending on the reset source. Reset Source RESET Input Register Reset by Reset by Reset by Reset by Reset by Reset by POR Execution of WDT RAM parity illegal- LVD error memory Illegal Instruction RESF TRAP bit Cleared (0) WDTRF bit <R> LVIM Set (1) Held Held Set (1) RPERF bit Held IAWRF bit Held LVIRF bit Held LVISEN bit Cleared (0) LVIOMSK bit Held access Held Held Set (1) Held Set (1) Set (1) Held LVIF bit LVIS Cleared (00H/01H/81H) 3. The generation of reset signal other than an LVD reset sets as follows. * When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H * When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H * When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H Remark The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers (SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 870 RL78/G13 CHAPTER 19 RESET FUNCTION 19.1 Register for Confirming Reset Source Many internal reset generation sources exist in the RL78/G13. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF, IAWRF, and LVIRF flags. Figure 19-5. Format of Reset Control Flag Register (RESF) Address: FFFA8H After reset: 00H Note 1 R Symbol 7 6 5 4 3 2 1 0 RESF TRAP 0 0 WDTRF 0 RPERF IAWRF LVIRF TRAP Internal reset request by execution of illegal instruction 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. RPERF Internal reset request t by RAM parity 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. IAWRF Internal reset request t by illegal-memory access 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. LVIRF Notes 1. 2. Note 2 Internal reset request by voltage detector (LVD) 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. The value after reset varies depending on the reset source. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. Cautions 1. Do not read data by a 1-bit memory manipulation instruction. 2. An instruction code fetched from RAM is not subject to parity error detection while it is being executed. However, the data read by the instruction is subject to parity error detection. 3. Because the RL78's CPU executes lookahead due to the pipeline operation, the CPU might read an uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity <R> error. Therefore, when enabling RAM parity error resets (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 871 RL78/G13 CHAPTER 19 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 19-3. Table 19-3. RESF Register Status When Reset Request Is Generated Reset Source RESET Input Flag Reset by Reset by Reset by Reset by Reset by Reset by POR Execution of WDT RAM parity illegal- LVD error memory Illegal Instruction TRAP bit Cleared (0) WDTRF bit RPERF bit IAWRF bit LVIRF bit R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Cleared (0) access Set (1) Held Held Set (1) Held Held Held Held Set (1) Held Set (1) Held Set (1) 872 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT CHAPTER 20 POWER-ON-RESET CIRCUIT 20.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions. * Generates internal reset signal at power on. The reset signal is released when the supply voltage (VDD) exceeds 1.51 V 0.03 V. * Compares supply voltage (VDD) and detection voltage (VPDR = 1.50 V 0.03 V), generates internal reset signal when VDD < VPDR. Caution If an internal reset signal is generated in the POR circuit, TRAP, WDTRF, RPERF, IAWRF, and LVIRF flags of the reset control flag register (RESF) is cleared. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access. The RESF register is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access. For details of the RESF register, see CHAPTER 19 RESET FUNCTION. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 873 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT 20.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 20-1. Figure 20-1. Block Diagram of Power-on-reset Circuit VDD VDD + Internal reset signal - Reference voltage source 20.3 Operation of Power-on-reset Circuit * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VPDR = 1.51 V 0.03 V), the reset status is released. * The supply voltage (VDD) and detection voltage (VPDR = 1.50 V 0.03 V) are compared. When VDD < VPDR, the internal reset signal is generated. The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 874 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/2) (1) When LVD is OFF (option byte 000C1H: VPOC2 = 1) <R> Supply voltage (VDD) 1.6 V VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) 0V Wait for oscillation accuracy stabilizationNote 1 Wait for oscillation accuracy stabilizationNote 1 High-speed on-chip oscillator clock (fIH) Starting oscillation is specified by software Starting oscillation is specified by software High-speed system clock (fMX) (when X1 oscillation is selected) Reset processing Note 3 Operation CPU stops Normal operation (high-speed on-chip oscillator clock)Note 2 Reset Reset processingNote 2 period (oscillation stop) Normal operation (high-speed on-chip oscillator clock)Note 2 Operation stops Internal reset signal <R> Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 2. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. <R> 3. Remark Reset processing time: 265 to 407 s VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 875 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/2) (2) When LVD is interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0) <R> Supply voltage (VDD) Note 3 VLVDH VLVDL 1.6 V VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) 0V Wait for oscillation accuracy stabilizationNote 2 Wait for oscillation accuracy stabilizationNote 2 High-speed on-chip oscillator clock (fIH) Starting oscillation is specified by software High-speed system clock (fMX) (when X1 oscillation is selected) CPU Operation stops Starting oscillation is specified by software Normal operation (high-speed on-chip oscillator clock)Note 1 Reset processing time Note 4 POR processing time Reset period (oscillation stop) Normal operation (high-speed on-chip oscillator clock)Note 1 Operation stops Reset processing timeNote 4 POR processing time Internal reset signal INTLVI Notes 1. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse of the stabilization time. 2. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on- 3. After the first interrupt request signal (INTLVI) is generated, the LVIL and LVIMD bits of the voltage chip oscillator clock. detection level register (LVIS) are automatically set to 1. If the operating voltage returns to 1.6 V or higher without falling below the voltage detection level (VLVDL), after INTLVI is generated, perform the required <R> backup processing, and then use software to specify the initial settings in order (see Figure 21-8. Initial Setting of Interrupt and Reset Mode). <R> 4. Remark Reset processing time: 497 to 720 s VLVDH, VLVDL: LVD detection voltage VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 876 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT 20.4 Cautions for Power-on-reset Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POR detection voltage (VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer, and then initialize the ports. Figure 20-3. Example of Software Processing After Reset Release (1/2) * If supply voltage fluctuation is 50 ms or less in vicinity of POR detection voltage Reset Initialization processing <1> ; Check the reset source, etc.Note 2 Power-on-reset Setting timer array unit (to measure 50 ms) ; fCLK = High-speed on-chip oscillator clock (4.04 MHz (MAX.)) Source: fMCK = (4.04 MHz (MAX.))/27, where comparison value = 789: 50 ms Timer starts (TSmn = 1). Clearing WDT Note 1 No 50 ms has passed? (TMIFmn = 1?) Yes Initialization processing <2> Notes 1. 2. Remark ; Initial setting for port. Setting of division ratio of system clock, such as setting of timer or A/D converter. If reset is generated again during this period, initialization processing <2> is not started. A flowchart is shown on the next page. m = 0, 1 n = 0 to 7 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 877 RL78/G13 CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-3. Example of Software Processing After Reset Release (2/2) * Checking reset source Check reset source TRAP of RESF register = 1? Yes No Reset processing by illegal instruction execution Note WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer RPERF of RESF register = 1? Yes No Reset processing by RAM parity error IAWRF of RESF register = 1? Yes No Reset processing by illegal-memory access LVIRF of RESF register = 1? Yes No Reset processing by voltage detector Power-on-reset/external reset generated Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 878 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR CHAPTER 21 VOLTAGE DETECTOR 21.1 Functions of Voltage Detector The voltage detector (LVD) has the following functions. * The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL), and generates an internal reset or internal interrupt signal. * The detection level for the power supply detection voltage (VLVDH, VLVDL) can be selected by using the option byte as one of 14 levels (For details, see CHAPTER 24 OPTION BYTE). * Operable in STOP mode. * The following three operation modes can be selected by using the option byte. (a) Interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0) For the two detection voltages selected by the option byte 000C1H, the high-voltage detection level (VLVDH) is used for generating interrupts and ending resets, and the low-voltage detection level (VLVDL) is used for triggering resets. (b) Reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1) The detection voltage (VLVD) selected by the option byte 000C1H is used for triggering and ending resets. (c) Interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1) The detection voltage (VLVD) selected by the option byte 000C1H is used for generating interrupts/reset release. Two detection voltages (VLVDH, VLVDL) can be specified in the interrupt & reset mode, and one (VLVD) can be specified in the reset mode and interrupt mode. The reset and interrupt signals are generated as follows according to the option byte (LVIMDS0, LVIMDS1) selection. Interrupt & reset mode Reset mode Interrupt mode (LVIMDS1, LVIMDS0 = 1, 0) (LVIMDS1, LVIMDS0 = 1, 1) (LVIMDS1, LVIMDS0 = 0, 1) Generates an internal interrupt signal Generates an internal reset signal when when VDD < VLVDH, and an internal reset VDD < VLVD and releases the reset signal when VDD drops lower than VLVD (VDD < when VDD < VLVDL. when VDD VLVD. VLVD) or when VDD becomes VLVD or Releases the reset signal when VDD VLVH. Generates an internal interrupt signal higher (VDD VLVD). Releases the reset signal when VDD VLVD at power on. While the voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is more than or less than the detection level can be checked by reading the voltage detection flag (LVIF: bit 0 of the voltage detection register (LVIM)). Bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of the RESF register, see CHAPTER 19 RESET FUNCTION. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 879 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 21-1. <R> Figure 21-1. Block Diagram of Voltage Detector VDD VDD Controller Internal reset signal + VLVDH VLVDL Selector Voltage detection level selector N-ch Option byte (000C1H) LVIS1, LVIS0 - INTLVI Reference voltage source LVIF LVIOMSK LVISEN Option byte (000C1H) VPOC2 to VPOC0 Voltage detection register (LVIM) LVIMD LVILV Voltage detection level register (LVIS) Internal bus 21.3 Registers Controlling Voltage Detector The voltage detector is controlled by the following registers. * Voltage detection register (LVIM) * Voltage detection level register (LVIS) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 880 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR (1) Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-2. Format of Voltage Detection Register (LVIM) Address: FFFA9H After reset: 00H Note 1 R/W Note 2 Symbol <7> 6 5 4 3 2 <1> <0> LVIM LVISEN 0 0 0 0 0 LVIOMSK LVIF LVISEN Specification of whether to enable or disable rewriting the voltage detection level register (LVIS) 0 Disabling rewriting 1 Enabling rewriting Note 3 LVIOMSK Mask status flag of LVD output 0 Mask is invalid 1 Mask is valid Notes 3, 4 LVIF Notes 1. Voltage detection flag 0 Supply voltage (VDD) detection voltage (VLVD), or when LVD operation is disabled 1 Supply voltage (VDD) < detection voltage (VLVD) The reset value changes depending on the reset source. If the LVIS register is reset by LVD, it is not reset but holds the current value. In other reset, LVISEN is cleared to 0. <R> 2. Bits 0 and 1 are read-only. 3. This can only be set when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset mode) by the option byte (In the other mode is invalid). 4. LVIOMSK bit is automatically set to "1" in the following periods and reset or interruption by LVD is masked. * Period during LVISEN = 1 * Waiting period from the time when LVD interrupt is generated until LVD detection voltage becomes stable * Waiting period from the time when the value of LVILV bit changes until LVD detection voltage becomes stable R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 881 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR (2) Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 00H/01H/81H Note1. Figure 21-3. Format of Voltage Detection Level Select Register (LVIS) Address: FFFAAH After reset: 00H/01H/81H Note 1 R/W Symbol <7> 6 5 4 3 2 1 <0> LVIS LVIMD 0 0 0 0 0 0 LVILV LVIMD Operation mode of voltage detection 0 Interrupt mode 1 Reset mode LVILV Notes 1. Note 2 Note 2 LVD detection level 0 High-voltage detection level (VLVDH) 1 Low-voltage detection level (VLVDL or VLVDL) The reset value changes depending on the reset source and the setting of the option byte. This register is not cleared (00H) by LVD reset. The generation of reset signal other than an LVD reset sets as follows. * When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H * When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H * When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H 2. Writing "0" can only be allowed when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset mode) by the option byte. In other cases, writing is not allowed and the value is switched automatically when reset or interrupt is generated. Cautions 1. 2. Only rewrite the value of the LVIS register after setting the LVISEN bit (bit 7 of the LVIM register) to 1. Specify the LVD operation mode and detection voltage (VLVDH, VLVDL) by using the option byte (000C1H). Table 21-1 shows the option byte (000C1H) settings. For details about the option byte, see CHAPTER 24 OPTION BYTE. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 882 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Table 21-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (1/2) Address: 000C1H/010C1H <R> Note 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 * LVD setting (interrupt & reset mode) Detection voltage VLVDH Option byte Setting Value VLVDL Rising Falling Falling edge edge edge 1.77 V 1.73 V 1.63 V 1.88 V 1.84 V 2.92 V 2.86 V 1.98 V 1.94 V 2.09 V Mode setting LVIMDS1 LVIMDS0 1 0 VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 0 1 0 0 1 0 0 1 0 2.04 V 0 1 3.13 V 3.06 V 0 0 2.61 V 2.55 V 1 0 2.71 V 2.65 V 0 1 3.75 V 3.67 V 0 0 2.92 V 2.86 V 1 0 3.02 V 2.96 V 0 1 4.06 V 3.98 V 0 0 1.84 V 0 2.45 V 0 2.75 V Other than above 0 1 1 0 0 1 1 Setting prohibited * LVD setting (reset mode) Detection voltage Option byte Setting Value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 0 1 1 Rising edge Falling edge LVIMDS1 LVIMDS0 1.67 V 1.63 V 1 1 1.77 V 1.73 V 0 0 0 1 0 1.88 V 1.84 V 0 0 1 1 1 1.98 V 1.94 V 0 0 1 1 0 2.09 V 2.04 V 0 0 1 0 1 2.50 V 2.45 V 0 1 0 1 1 2.61 V 2.55 V 0 1 0 1 0 2.71 V 2.65 V 0 1 0 0 1 2.81 V 2.75 V 0 1 1 1 1 2.92 V 2.86 V 0 1 1 1 0 3.02 V 2.96 V 0 1 1 0 1 3.13 V 3.06 V 0 0 1 0 0 3.75 V 3.67 V 0 1 0 0 0 4.06 V 3.98 V 0 1 1 0 0 Other than above Note Setting prohibited Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is replaced by 010C1H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 883 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Table 21-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (2/2) Address: 000C1H/010C1H <R> Note 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 * LVD setting (interrupt mode) Detection voltage Option byte Setting Value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 0 1 1 Rising edge Falling edge LVIMDS1 LVIMDS0 1.67 V 1.63 V 0 1 1.77 V 1.73 V 0 0 0 1 0 1.88 V 1.84 V 0 0 1 1 1 1.98 V 1.94 V 0 0 1 1 0 2.09 V 2.04 V 0 0 1 0 1 2.50 V 2.45 V 0 1 0 1 1 2.61 V 2.55 V 0 1 0 1 0 2.71 V 2.65 V 0 1 0 0 1 2.81 V 2.75 V 0 1 1 1 1 2.92 V 2.86 V 0 1 1 1 0 3.02 V 2.96 V 0 1 1 0 1 3.13 V 3.06 V 0 0 1 0 0 3.75 V 3.67 V 0 1 0 0 0 4.06 V 3.98 V 0 1 1 0 0 Other than above Setting prohibited * LVD setting (LVDOFF) Detection voltage Option byte Setting Value VLVD Mode setting Rising edge Falling edge LVIMDS1 LVIMDS0 - - 0/1 1 Other than above Note VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 1 x x x x Setting prohibited Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is replaced by 010C1H. Remark x: don't care R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 884 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.4 Operation of Voltage Detector 21.4.1 When used as reset mode * When starting operation Start in the following initial setting state. Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. * Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)) * When the option byte LVIMDS1 and LVIMDS0 are set to 1, the initial value of the LVIS register is set to 81H. Bit 7 (LVIMD) is 1 (reset mode). Bit 0 (LVILV) is 1 (low-voltage detection level: VLVDL or VLVD). Figure 21-4 shows the timing of the internal reset signal generated by the voltage detector. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 885 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Figure 21-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) <R> Supply voltage (VDD) VLVD VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time Cleared LVIF flag LVIMD flag H Not cleared Not cleared LVILV flag H Not cleared Not cleared Cleared LVIRF flag (RESF register) LVD reset signal Cleared by software Cleared by software POR reset signal Internal reset signal Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 886 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.4.2 When used as interrupt mode * When starting operation Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. Start in the following initial setting state. * Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)) * When the option byte LVIMDS1 is clear to 0 and LVIMDS0 is set to 1, the initial value of the LVIS register is set to 00H. Bit 7 (LVIMD) is 0 (interrupt mode). Bit 0 (LVILV) is 1 (low-voltage detection level: VLVDL or VLVD). Figure 21-5 shows the timing of the internal interrupt signal generated by the voltage detector. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 887 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR <R> Figure 21-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Supply voltage (VDD) VLVD VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time LVIMK flag (interrupt MASK) (set by software) H Note Cleared by software Cleared LVIF flag LVIMD flag LVILV flag H INTLVI LVIIF flag LVD reset signal POR reset signal Internal reset signal Note The LVIMK flag is set to "1" by reset signal generation. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 888 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.4.3 When used as interrupt and reset mode * When starting operation Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (VLVDH, VLVDL) by using the option byte 000C1H. Start in the following initial setting state. * Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)) * When the option byte LVIMDS1 is set to 1 and LVIMDS0 is clear to 0, the initial value of the LVIS register is set to 00H. Bit 7 (LVIMD) is 0 (interrupt mode). Bit 0 (LVILV) is 0 (high-voltage detection level: VLVDH). Figure 21-6 shows the timing of the internal reset signal and interrupt signal generated by the voltage detector. Perform the processing according to figure 21-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode and figure 21-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 889 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask, determine that a condition of VDD becomes VDD VLVDH, clear LVIMD bit to 0, and the MCU shift to normal operation. <R> Supply voltage (VDD) VLVDH VLVDL VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time H Note 1 LVIMK flag (set by software) Cleared by Normal software operation Cleared by software Wait for stabilization by software (400 s or 5 clocks of fIL) Note 3 { Operation status RESET Normal operation Save processing Normal operation Save processing RESET RESET Cleared LVIF flag LVISEN flag (set by software) LVIOMSK flag LVIMD flag Cleared by software Note 3 LVILV flag LVIRF flag Cleared by software Note 2 Cleared LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag (Notes and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 890 RL78/G13 Notes 1. 2. CHAPTER 21 VOLTAGE DETECTOR The LVIMK flag is set to "1" by reset signal generation. After an interrupt is generated, perform the processing according to figure 21-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode. 3. After a reset is released, perform the processing according to figure 21-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 891 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of VDD is VDD < VLVIH after releasing the mask, a reset is generated because of LVIMD = 1 (reset mode). <R> Supply voltage (VDD) VLVDH VLVDL VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time LVIMK flag (set by software) H Note 1 Cleared by software Operation status RESET Save Normal operation processing Cleared by software Wait for stabilization by software (400 s or 5 clocks of fIL) Note 3 RESET Normal operation RESET Save processing Cleared LVIF flag LVISEN flag (set by software) LVIOMSK flag LVIMD flag Cleared by software Note 3 LVILV flag LVIRF flag Cleared by software Note 2 Cleared LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag (Notes and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 892 RL78/G13 Notes 1. 2. CHAPTER 21 VOLTAGE DETECTOR The LVIMK flag is set to "1" by reset signal generation. After an interrupt is generated, perform the processing according to figure 21-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode. 3. After a reset is released, perform the processing according to figure 21-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage Figure 21-7. Processing Procedure After an Interrupt Is Generated <R> INTLVI generated Save processing LVISEN = 1 LVILV = 0 LVISEN = 0 No Perform required save processing. Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1). Set the LVILV bit to 0 to set the high-voltage detection level (VLVDH). Set the LVISEN bit to 0 to enable voltage detection. LVIOMSK = 0 Yes Yes LVD reset generated No Reset R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 The MCU returns to normal operation when internal reset by voltage detector (LVD) is not generated, since a condition of VDD becomes VDD VLVDH. LVISEN = 1 Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1) LVIMD = 0 Set the LVIMD bit to 0 to set interrupt mode. LVISEN = 0 Set the LVISEN bit to 0 to enable voltage detection. Normal operation 893 RL78/G13 <R> CHAPTER 21 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400 s or 5 clocks of fIL is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0) clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the LVIMD bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD. Figure 21-8. shows the procedure for initial setting of interrupt and reset mode. Figure 21-8 Initial Setting of Interrupt and Reset Mode <R> Power application Reset source determine Refer to Figure 21-9. Checking reset source. LVIRF = 1? Check internal reset generation by LVD circuit No Yes LVISEN = 1 Voltage detection stabilization Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1) Count 400 s or 5 clocks of fIL by software. wait time LVIMD = 0 Set the LVIMD bit to 0 to set interrupt mode. LVISEN = 0 Set the LVISEN bit to 0 to enable voltage detection. Normal operation Remark fIL: Low-speed on-chip oscillator clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 894 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR 21.5 Cautions for Voltage Detector (1) Checking reset source When a reset occurs, check the reset source by using the following method. Figure 21-9. Checking reset source Check reset source TRAP of RESF register = 1? Yes No Reset processing by illegal instruction execution Note WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer RPERF of RESF register = 1? Yes No Reset processing by RAM parity error IAWRF of RESF register = 1? Yes No Reset processing by illegal-memory access LVIRF of RESF register = 1? No Yes Power-on-reset/external reset generated Reset processing by voltage detector Note When instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 895 RL78/G13 CHAPTER 21 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has been generated. In the same way, there is also some delay from the time LVD detection voltage (VLVD) supply voltage (VDD) until the time LVD reset has been released (see Figure 21-10). Figure 21-10. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released Supply voltage (VDD) VLVD Time <1> <1> LVD reset signal <1>: Detection delay (300 s (MAX.)) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 896 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS CHAPTER 22 SAFETY FUNCTIONS 22.1 Overview of Safety Functions The following safety functions are provided in the RL78/G13 to comply with the IEC60730 and IEC61508 safety standards. These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is detected. (1) Flash memory CRC operation function (high-speed CRC, general-purpose CRC) This detects data errors in the flash memory by performing CRC operations. Two CRC functions are provided in the RL78/G13 that can be used according to the application or purpose of use. * High-speed CRC: The CPU can be stopped and a high-speed check executed on its entire code flash memory area during the initialization routine. * General CRC: This can be used for checking various data in addition to the code flash memory area while the CPU is running. (2) RAM parity error detection function This detects parity errors when the RAM is read as data. (3) RAM guard function This prevents RAM data from being rewritten when the CPU freezes. (4) SFR guard function This prevents SFRs from being rewritten when the CPU freezes. (5) Invalid memory access detection function This detects illegal accesses to invalid memory areas (such as areas where no memory is allocated and areas to which access is restricted). (6) Frequency detection function This uses TAU to detect the oscillation frequency. (7) A/D test function This is used to perform a self-check of A/D conversion by performing A/D conversion on the internal reference voltage. <R> Remark See the application note (R01AN0749) for the features required to comply with the IEC60730 standards. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 897 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.2 Registers Used by Safety Functions The safety functions use the following registers for each function. Register Each Function of Safety Function * Flash memory CRC control register (CRC0CTL) Flash memory CRC operation function * Flash memory CRC operation result register (PGCRCL) (high-speed CRC) * CRC input register (CRCIN) CRC operation function * CRC data register (CRCD) (general-purpose CRC) * RAM parity error control register (RPECTL) RAM parity error detection function * Invalid memory access detection control register (IAWCTL) RAM guard function SFR guard function Invalid memory access detection function * Timer input select register 0 (TIS0) Frequency detection function * A/D test register (ADTES) A/D test function The content of each register is described in 22.3 Operation of Safety Functions. 22.3 Operation of Safety Functions 22.3.1 Flash memory CRC operation function (high-speed CRC) The IEC60730 standard mandates the checking of data in the flash memory, and recommends using CRC to do it. The high-speed CRC provided in the RL78/G13 can be used to check the entire code flash memory area during the initialization routine. The high-speed CRC can be executed only when the program is allocated on the RAM and in the HALT mode of the main system clock. <R> The high-speed CRC performs an operation by reading 32-bit data per clock from the flash memory while stopping the CPU. This function therefore can finish a check in a shorter time (for example, 512 s@32 MHz with 64-KB flash memory). The CRC generator polynomial used complies with "X16 + X12 + X5 + 1" of CRC-16-CCITT. The high-speed CRC operates in MSB first order from bit 31 to bit 0. <R> Caution The CRC operation result might differ during on-chip debugging because the monitor program is allocated. Remark The operation result is different between the high-speed CRC and the general CRC, because the general CRC operates in LSB first order. <Control register> (1) Flash memory CRC control register (CRC0CTL) This register is used to control the operation of the high-speed CRC ALU, as well as to specify the operation range. The CRC0CTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 898 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS Figure 22-1. Format of Flash Memory CRC Control Register (CRC0CTL) Address: F02F0H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CRC0CTL CRC0EN 0 FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 CRC0EN Control of CRC ALU operation 0 Stop the operation. 1 Start the operation according to HALT instruction execution. FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 0 0 0 0 0 0 0000H to 3FFBH (16 K to 4 bytes) 0 0 0 0 0 1 0000H to 7FFBH (32 K to 4 bytes) 0 0 0 0 1 0 0000H to BFFBH (48 K to 4 bytes) 0 0 0 0 1 1 0000H to FFFBH (64 K to 4 bytes) 0 0 0 1 0 0 00000H to 13FFBH (80 K to 4 bytes) 0 0 0 1 0 1 00000H to 17FFBH (96 K to 4 bytes) 0 0 0 1 1 0 00000H to 1BFFBH (112 K to 4 bytes) 0 0 0 1 1 1 00000H to 1FFFBH (128 K to 4 bytes) 0 0 1 0 0 0 00000H to 23FFBH (144 K to 4 bytes) 0 0 1 0 0 1 00000H to 27FFBH (160 K to 4 bytes) 0 0 1 0 1 0 00000H to 2BFFBH (176 K to 4 bytes) 0 0 1 0 1 1 00000H to 2FFFBH (192 K to 4 bytes) 0 0 1 1 0 0 00000H to 33FFBH (208 K to 4 bytes) 0 0 1 1 0 1 00000H to 37FFBH (224 K to 4 bytes) 0 0 1 1 1 0 00000H to 3BFFBH (240 K to 4 bytes) 0 0 1 1 1 1 00000H to 3FFFBH (256 K to 4 bytes) 0 1 0 0 0 0 00000H to 43FFBH (272 K to 4 bytes) 0 1 0 0 0 1 00000H to 47FFBH (288 K to 4 bytes) 0 1 0 0 1 0 00000H to 4BFFBH (304 K to 4 bytes) 0 1 0 0 1 1 00000H to 4FFFBH (320 K to 4 bytes) 0 1 0 1 0 0 00000H to 53FFBH (336 K to 4 bytes) 0 1 0 1 0 1 00000H to 57FFBH (352 K to 4 bytes) 0 1 0 1 1 0 00000H to 5BFFBH (368 K to 4 bytes) 0 1 0 1 1 1 00000H to 5FFFBH (384 K to 4 bytes) 0 1 1 0 0 0 00000H to 63FFBH (400 K to 4 bytes) 0 1 1 0 0 1 00000H to 67FFBH (416 K to 4 bytes) 0 1 1 0 1 0 00000H to 6BFFBH (432 K to 4 bytes) 0 1 1 0 1 1 00000H to 6FFFBH (448 K to 4 bytes) 0 1 1 1 0 0 00000H to 73FFBH (464 K to 4 bytes) 0 1 1 1 0 1 00000H to 77FFBH (480 K to 4 bytes) 0 1 1 1 1 0 00000H to 7BFFBH (496 K to 4 bytes) 0 1 1 1 1 1 00000H to 7FFFBH (512 K to 4 bytes) Other than the above Remark High-speed CRC operation range Setting prohibited Input the expected CRC operation result value to be used for comparison in the lowest 4 bytes of the flash memory. Note that the operation range will thereby be reduced by 4 bytes. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 899 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS (2) Flash memory CRC operation result register (PGCRCL) This register is used to store the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 22-2. Format of Flash Memory CRC Operation Result Register (PGCRCL) Address: F02F2H After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 PGCRCL PGCRC15 PGCRC14 PGCRC13 PGCRC12 PGCRC11 PGCRC10 PGCRC9 PGCRC8 7 6 5 4 3 2 1 0 PGCRC7 PGCRC6 PGCRC5 PGCRC4 PGCRC3 PGCRC2 PGCRC1 PGCRC0 PGCRC15 to 0 0000H to FFFFH High-speed CRC operation results Store the high-speed CRC operation results. Caution The PGCRCL register can only be written if CRC0EN (bit 7 of the CRC0CTL register) = 1. Figure 22-3 shows the flowchart of flash memory CRC operation function (high-speed CRC). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 900 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Operation flow> <R> Figure 22-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits Copied to RAM to HALT instruction and RET instruction, initialize 10 bytes All xxMKx = 1 CRC0EN = 1 PGCRCL = 0000H ; CRC operation range setting ; Copy the HALT and RET instructions to be ; executed on the RAM to the RAM. ; Initialize the 10 bytes after the RET ; instruction. ; Masks all interrupt ; Enables CRC operation ; Initialize the CRC operation result register Execute the CALL instruction ; Call the address of the HALT instruction ; copied to the RAM. Execute the HALT instruction. ; CRC operation starts by HALT insutraction ; execution HALT mode Execute the RET instruction. CRC0EN = 0 Read the value of PGCRCL. Compare the value with the expected CRC value. Match ; When the CRC operation is complete, the HALT ; mode is released and control is returned from RAM ; Prohibits CRC operation ; Read CRC operation result ; Compare the value with the stored expected ; value. Not match Abnormal complete Correctly complete Cautions 1. The CRC operation is executed only on the code flash. 2. Store the expected CRC operation value in the area below the operation range in the code flash. 3. Boot swapping is not performed while the CRC operation is being executed. 4. The CRC operation is enabled by executing the HALT instruction in the RAM area. Be sure to execute the HALT instruction in RAM area. The expected CRC value can be calculated by using tools such as the CubeSuite+ development environment. (See the CubeSuite+ user's manual for details.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 901 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.2 CRC operation function (general-purpose CRC) In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the CPU is operating. In the RL78/G13, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked <R> can be specified by using software (a user-created program). CRC calculation function in the HALT mode can be used only during the DMA transmission. The general CRC operation can be executed in the main system clock operation mode as well as the subsystem clock operation mode. The CRC generator polynomial used is "X16 + X12 + X5 + 1" of CRC-16-CCITT. The data to be input is inverted in bit order and then calculated to allow for LSB-first communication. For example, if the data 12345678H is sent from the LSB, values are written to the CRCIN register in the order of 78H, 56H, 34H, and 12H, enabling a value of 08F6H to be obtained from the CRCD register. This is the result obtained by executing a CRC operation on the bit rows shown below, which consist of the data 12345678H inverted in bit order. CRCIN setting data 78H Bit representation data 0111 1000 56H 34H 12H 0101 0110 0011 0100 0001 0010 Bit reverse Bit reverse data 0001 1110 0110 1010 0010 1100 0100 1000 Operation with polynomial Result data 0110 1111 0001 0000 Bit reverse CRCD data 0000 1000 1111 0110 Obtained result (08F6H) <R> Caution Because the debugger rewrites the software break setting line to a break instruction during program execution, the CRC operation result differs if a software break is set in the CRC operation target area. <Control register> (1) CRC input register (CRCIN) CRCIN register is an 8-bit register that is used to set the CRC operation data of general-purpose CRC. The possible setting range is 00H to FFH. The CRCIN register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-4. Format of CRC Input Register (CRCIN) Address: FFFACH Symbol After reset: 00H 7 6 R/W 5 4 3 2 1 0 CRCIN Bits 7 to 0 00H to FFH R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Function Data input. 902 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS (2) CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register. The CRCD register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 22-5. Format of CRC Data Register (CRCD) Address: F02FAH Symbol 15 After reset: 0000H 14 13 12 R/W 11 10 9 8 7 6 5 4 3 2 1 0 CRCD Cautions 1. Read the value written to CRCD register before writing to CRCIN register. 2. If conflict between writing and storing operation result to CRCD register occurs, the writing is ignored. <Operation flow> Figure 22-6. CRC Operation Function (General-Purpose CRC) START ; Store the start and end addresses in a Specify the start and end addresses Write CRCD register to 0000H Read data Store data to CRCIN register ; general-purpose register. ; Initialize CRCD register ; Read 8-bit data of corresponding address ; Execute CRC calculation for 8-bit data Address+1 Last address? Yes No 1 clock wait (fCLK) <R> Read CRCD register End ; Get CRC result ; Compare the value ; with the stored ; expected value and ; make sure that the ; values match. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 903 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.3 RAM parity error detection function The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/G13's RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error occurs. <Control register> * RAM parity error control register (RPECTL) This register is used to control parity error generation check bit and reset generation due to parity errors. The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-7. Format of RAM Parity Error Control Register (RPECTL) Address: F00F5H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> RPECTL RPERDIS 0 0 0 0 0 0 RPEF RPERDIS Parity error reset mask flag 0 Enable parity error resets. 1 Disable parity error resets. RPEF Parity error status flag 0 No parity error has occurred. 1 A parity error has occurred. Caution The RL78's CPU executes lookahead due to the pipeline operation, the CPU might read an uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error. <R> Therefore, when enabling RAM parity error resets (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. When using the self-programming function while RAM parity error resets are <R> enabled (RPERDIS = 0), be sure to initialize the RAM area to overwrite + 10 bytes before overwriting. The data read by the instruction is subject to parity error detection. Remarks 1. The RAM parity check is always on, and the result can be confirmed by checking the PREF flag. 2. The parity error reset is enabled by default (RPERDIS = 0). Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity error occurs. 3. The RPEF flag is set (1) by RAM parity errors and cleared (0) by writing 0 to it or by any reset source. When RPEF = 1, the value is retained even if RAM for which no parity error has occurred is read. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 904 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space. If the RAM guard function is specified, writing to the specified RAM space is disabled, but reading from the space can be carried out as usual. <Control register> * Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. GRAM1 and GRAM0 bits are used in RAM guard function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-8. Format of Invalid Memory Access Detection Control Register (IAWCTL) Address: F0078H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC GRAM1 GRAM0 0 0 Disabled. RAM can be written to. 0 1 The 128 bytes starting at the lower RAM address 1 0 The 256 bytes starting at the lower RAM address 1 1 The 512 bytes starting at the lower RAM address Note Note RAM guard space The RAM start address differs depending on the size of the RAM provided with the product. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 905 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function. If the SFR guard function is specified, writing to the specified SFRs is disabled, but reading from the SFRs can be carried out as usual. <Control register> * Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. GPORT, GINT and GCSC bits are used in SFR guard function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-9. Format of Invalid Memory Access Detection Control Register (IAWCTL) Address: F0078H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC GPORT Control registers of port function guard 0 Disabled. Control registers of port function can be read or written to. 1 Enabled. Writing to control registers of port function is disabled. Reading is enabled. [Guarded SFR] PMxx, PUxx, PIMxx, POMxx, PMCxx, ADPC, PIOR GINT Note 1 Registers of interrupt function guard 0 Disabled. Registers of interrupt function can be read or written to. 1 Enabled. Writing to registers of interrupt function is disabled. Reading is enabled. [Guarded SFR] IFxx, MKxx, PRxx, EGPx, EGNx GCSC 0 Notes 2 Control registers of clock control function, voltage detector and RAM parity error detection function guard Disabled. Control registers of clock control function, voltage detector and RAM parity error detection function can be read or written to. 1 Enabled. Writing to control registers of clock control function, voltage detector and RAM parity error detection function is disabled. Reading is enabled. [Guarded SFR] CMC, CSC, OSTS, CKC, PERx, OSMC, LVIM, LVIS, RPECTL Notes 1. 2. Pxx (Port register) is not guarded. Clear GCSC bit to 0, during self programming /serial programming. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 906 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed. The illegal memory access detection function applies to the areas indicated by NG in Figure 22-10. Figure 22-10. Invalid access detection area <R> Possibility access Read Write Fetching instructions (execute) FFFFFH Special function register (SFR) 256 byte FFF00H FFEFFH FFEE0H FFEDFH NG General-purpose register 32 byte OK RAMNote OK yyyyyH OK Mirror NG NG Data flash memory F1000H F0FFFH Reserved OK F0800H F07FFH OK Special function register (2nd SFR) 2 Kbyte NG F0000H EFFFFH OK EF000H EEFFFH Reserved NG NG NG xxxxxH Code flash memory Note OK OK 00000H Note Code flash memory and RAM address of each product are as follows. Products R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G) Code flash memory RAM (00000H to xxxxxH) (yyyyyH to FFEFFH) 16384 x 8 bit (00000H to 03FFFH) 2048 x 8 bit (FF700H to FFEFFH) R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L) 32768 x 8 bit (00000H to 07FFFH) 2048 x 8 bit (FF700H to FFEFFH) R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L) 49152 x 8 bit (00000H to 0BFFFH) 3072 x 8 bit (FF300H to FFEFFH) R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L) 65536 x 8 bit (00000H to 0FFFFH) 4096 x 8 bit (FEF00H to FFEFFH) R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P) 98304 x 8 bit (00000H to 17FFFH) 8192 x 8 bit (FDF00H to FFEFFH) R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P) 131072 x 8 bit (00000H to 1FFFFH) 12288 x 8 bit (FCF00H to FFEFFH) R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) 196608 x 8 bit (00000H to 2FFFFH) 16384 x 8 bit (FBF00H to FFEFFH) R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S) 262144 x 8 bit (00000H to 3FFFFH) 20480 x 8 bit (FAF00H to FFEFFH) R5F100xK, R5F101xK (x = F, G, J, L, M, P, S) 393216 x 8 bit (00000H to 5FFFFH) 24576 x 8 bit (F9F00H to FFEFFH) R5F100xL, R5F101xL (x = F, G, J, L, M, P, S) 524288 x 8 bit (00000H to 7FFFFH) 32768 x 8 bit (F7F00H to FFEFFH) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 907 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Control register> * Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-11. Format of Invalid Memory Access Detection Control Register (IAWCTL) Address: F0078H After reset: 00H 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC IAWEN Note <R> R/W Symbol Note Control of invalid memory access detection 0 Disable the detection of invalid memory access. 1 Enable the detection of invalid memory access. Only writing 1 to the IAWEN bit is enabled, not writing 0 to it after setting it to 1. Remark By specifying WDTON = 1 for the option byte (watchdog timer operation enable), the invalid memory access function is enabled even IAWEN = 0. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 908 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. The frequency detection function can detect whether the clock is operating on an abnormal frequency by comparing the internal high-speed oscillation clock or external X1 oscillation clock with the internal low-speed oscillation clock (15 kHz). Figure 22-12. Configuration of Frequency Detection Function High-speed on-chip X1 X1 oscillator X2 (fMX) Selector ossiratopr (fIH) fCLK Timer array unit 0 (TAU0) Selector TI05 Low-speed on-chip oscillator fIL Watchdog timer (WDT) (15 kHz) <Operational overview> Whether the clock frequency is correct or not can be judged by measuring the pulse interval under the following conditions: * The internal high-speed oscillation clock (fIH) or the external X1 oscillation clock (fMX) is selected as the CPU/peripheral hardware clock (fCLK). * The internal low-speed oscillation clock (fIL: 15 kHz) is selected as the timer input for channel 5 of timer array unit 0 (TAU0). If pulse interval measurement results in an abnormal value, it can be concluded that the clock frequency is abnormal. For how to execute pulse interval measurement, see 6.7.4 Operation as input pulse interval measurement. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 909 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Control register> * Timer input select register 0 (TIS0) This register is used to select the timer input of channel 5. By selecting the internal low-speed oscillation clock for the timer input, its pulse width can be measured to determine whether the proportional relationship between the internal low-speed oscillation clock and the timer operation clock is correct. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-13. Format of Timer Input Select Register 0 (TIS0) Address: F0074H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 0 0 TIS02 TIS01 TIS00 TIS02 TIS01 TIS00 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 Low-speed on-chip oscillator clock (fIL) 1 0 1 Subsystem clock (fSUB) Other than the above R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Selection of timer input used with channel 5 Input signal of timer input pin (TI05) Setting prohibited 910 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS 22.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function is used to check whether the A/D converter is operating normally by executing A/D conversions of an internal voltage of 0 V, the AVREF voltage, and the internal reference voltage (1.45 V). <R> The analog multiplexer can be checked using the following procedure. (1) Perform A/D conversion for the ANIx pin (conversion result 1). (2) Select AVREFM using the ADTES register, perform A/D conversion, and then set the voltage potential difference between the terminals of the sampling capacitor of the A/D converter to 0 V. (3) Perform A/D conversion for the ANIx pin (conversion result 2). (4) Select AVREFP using the ADTES register, perform A/D conversion, and then set the voltage potential difference (5) Perform A/D conversion for the ANIx pin (conversion result 3). (6) Make sure that conversion results 1, 2, and 3 are equal. between the terminals of the sampling capacitor of the A/D converter to AVREF. Using the procedure above can confirm that the analog multiplexer is selected and all wiring is connected. Remarks 1. If the analog input voltage is variable during A/D conversion in steps <1> to <5> above, use another method to check the analog multiplexer. 2. The conversion results might contain an error. Consider an appropriate level of error when comparing the conversion results. Figure 22-14. Configuration of A/D Test Function VDD ANI0/AVREFP + side reference voltage source ANI1/AVREFM (AVREF+) ANIx ANIx A/D convertor - side reference voltage source (AVREF-) Temperature Note sensor Internal reference voltage (1.45 V) Note VSS Note This setting can be used only in HS (high-speed main) mode. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 911 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS <Control register> (1) A/D test register (ADTES) This register is used to select the A/D converter's positive reference voltage AVREFP, the A/D converter's negative reference voltage AVREFM, or the analog input channel (ANIxx) as the target of A/D conversion. When using the A/D test function, specify the following settings: * Select AVREFM as the target of A/D conversion when converting the internal 0 V. * Select AVREFP as the target of A/D conversion when converting AVREF. The ADTES register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-15. Format of A/D Test Register (ADTES) Address: F0013H <R> After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTES 0 0 0 0 0 0 ADTES1 ADTES0 ADTES1 ADTES0 0 0 A/D conversion target ANIxx/temperature sensor output Note /internal reference voltage (1.45 V) Note (This is specified using the analog input channel specification register (ADS).) 1 0 AVREFM 1 1 AVREFP Other than the above <R> Setting prohibited Note Temperature sensor output/internal reference voltage (1.45 V) can be used only in HS (high-speed main) mode. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 912 RL78/G13 CHAPTER 22 SAFETY FUNCTIONS (2) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. <R> Set A/D test register (ADTES) to 00H when measuring the ANIxx/temperature sensor output /internal reference voltage (1.45 V). The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-16. Format of Analog Input Channel Specification Register (ADS) (1/2) Address: FFF31H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0 { Select mode (ADMD = 0) ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input channel Input source 0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin 0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin 0 0 0 0 1 0 ANI2 P22/ANI2 pin 0 0 0 0 1 1 ANI3 P23/ANI3 pin 0 0 0 1 0 0 ANI4 P24/ANI4 pin 0 0 0 1 0 1 ANI5 P25/ANI5 pin 0 0 0 1 1 0 ANI6 P26/ANI6 pin 0 0 0 1 1 1 ANI7 P27/ANI7 pin 0 0 1 0 0 0 ANI8 P150/ANI8 pin 0 0 1 0 0 1 ANI9 P151/ANI9 pin 0 0 1 0 1 0 ANI10 P152/ANI10 pin 0 0 1 0 1 1 ANI11 P153/ANI11 pin 0 0 1 1 0 0 ANI12 P154/ANI12 pin 0 0 1 1 0 1 ANI13 P155/ANI13 pin 0 0 1 1 1 0 ANI14 P156/ANI14 pin 0 0 1 1 1 1 Setting prohibited 0 1 0 0 0 0 ANI16 P03/ANI16 pin Note 1 0 1 0 0 0 1 ANI17 P02/ANI17 pin Note 2 0 1 0 0 1 0 ANI18 P147/ANI18 pin 0 1 0 0 1 1 ANI19 P120/ANI19 pin 0 1 0 1 0 0 ANI20 P100/ANI20 pin 0 1 0 1 0 1 ANI21 P37/ANI21 pin 0 1 0 1 1 0 ANI22 P36/ANI22 pin 0 1 0 1 1 1 ANI23 P35/ANI23 pin 0 1 1 0 0 0 ANI24 P117/ANI24 pin 0 1 1 0 0 1 ANI25 P116/ANI25 pin P115/ANI26 pin 0 1 1 0 1 0 ANI26 0 1 1 0 1 1 Setting prohibited 1 0 0 0 0 0 - Temperature sensor output Note 3 1 0 0 0 Other than the above 0 1 - Internal reference voltage Note 3 output (1.45 V) Setting prohibited (Notes and cautions are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 913 RL78/G13 <R> CHAPTER 22 SAFETY FUNCTIONS Notes 1. 20-, 24-, 25-, 30-, 32-pin products: P01/ANI16 pin 2. 20-, 24-, 25-, 30-, 32-pin products: P00/ANI17 pin 3. This setting can be used only in HS (high-speed main) mode. Cautions 1. Be sure to clear bits 5 and 6 to 0. 2. Only rewrite the value of the ADISS bit while A/D voltage comparator operation is stopped (which is indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0). 3. If using AVREFP as the + side reference voltage source of the A/D converter, do not select ANI0 as an A/D conversion channel. 4. If using AVREFM as the - side reference voltage source of the A/D converter, do not select ANI1 as an A/D conversion channel. 5. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side reference R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 914 RL78/G13 CHAPTER 23 REGULATOR CHAPTER 23 REGULATOR 23.1 Regulator Overview The RL78/G13 contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 F). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. <R> REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. The regulator output voltage, see table 23-1. Table 23-1. Regulator Output Voltage Conditions Mode LV (low voltage main) mode Output Voltage Condition 1.8 V - LS (low-speed main) mode HS (high-speed main) mode 1.8 V In STOP mode When both the high-speed system clock (fMX) and the high-speed on-chip oscillator clock (fIH) are stopped during CPU operation with the subsystem clock (fXT) When both the high-speed system clock (fMX) and the high-speed on-chip oscillator clock (fIH) are stopped during the HALT mode when the CPU operation with the subsystem clock (fXT) has been set 2.1 V Other than above (include during OCD mode) Note Note When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator output voltage is kept at 2.1 V (not decline to 1.8 V). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 915 RL78/G13 CHAPTER 24 OPTION BYTE CHAPTER 24 OPTION BYTE 24.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the RL78/G13 form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H). Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set. When using the product, be sure to set the following functions by using the option bytes. To use the boot swap operation during self programming, 000C0H to 000C3H are replaced by 010C0H to 010C3H. Therefore, set the same values as 000C0H to 000C3H to 010C0H to 010C3H. 24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) (1) 000C0H/010C0H { Operation of watchdog timer * Operation is stopped or enabled in the HALT or STOP mode. { Setting of interval time of watchdog timer { Operation of watchdog timer * Operation is stopped or enabled. { Setting of window open period of watchdog timer { Setting of interval interrupt of watchdog timer * Used or not used Caution Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is replaced by 010C0H. (2) 000C1H/010C1H { Setting of LVD operation mode * Interrupt & reset mode. * Reset mode. * Interrupt mode. { Setting of LVD detection level (VLVDH, VLVDL, VLVD) Caution Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is replaced by 010C1H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 916 RL78/G13 CHAPTER 24 OPTION BYTE (3) 000C2H/010C2H { Setting of flash operation mode * LV (low voltage main) mode * LS (low speed main) mode * HS (high speed main) mode { Setting of the frequency of the high-speed on-chip oscillator * Select from 1 MHz, 4 MHz, 8 MHz, 12 MHz, 16 MHz, 24 MHz, and 32 MHz. Caution Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H. 24.1.2 On-chip debug option byte (000C3H/ 010C3H) { Control of on-chip debug operation * On-chip debug operation is disabled or enabled. { Handling of data of flash memory in case of failure in on-chip debug security ID authentication * Data of flash memory is erased or not erased in case of failure in on-chip debug security ID authentication. Caution Set the same value as 000C3H to 010C3H when the boot swap operation is used because 000C3H is replaced by 010C3H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 917 RL78/G13 CHAPTER 24 OPTION BYTE 24.2 Format of User Option Byte The format of user option byte is shown below. Figure 24-1. Format of User Option Byte (000C0H/010C0H) Note 1 Address: 000C0H/010C0H 7 6 5 4 3 2 1 0 WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTINIT <R> Use of interval interrupt of watchdog timer 0 Interval interrupt is not used. 1 Interval interrupt is generated when 75% + 1/2fIL of the overflow time is reached. WINDOW1 WINDOW0 Watchdog timer window open period 0 0 Setting prohibited 0 1 50% 1 0 75% 1 1 100% WDTON Operation control of watchdog timer counter 0 Counter operation disabled (counting stopped after reset) 1 Counter operation enabled (counting started after reset) WDCS2 Note 2 WDCS1 WDCS0 Watchdog timer overflow time (fIL = 17.25 kHz (MAX.)) 0 0 0 2 /fIL (3.71 ms) 0 0 1 2 /fIL (7.42 ms) 0 1 0 2 /fIL (14.84 ms) 0 1 1 2 /fIL (29.68 ms) 1 0 0 2 /fIL (118.72 ms) 1 0 1 2 /fIL (474.90 ms) 1 1 0 2 /fIL (949.80 ms) 1 1 1 2 /fIL (3799.19m s) WDSTBYON Notes 1. 6 7 8 9 11 13 14 16 Operation control of watchdog timer counter (HALT/STOP mode) Note 2 0 Counter operation stopped in HALT/STOP mode 1 Counter operation enabled in HALT/STOP mode Set the same value as 000C0H to 010C0H when the boot swap operation is used because 000C0H is replaced by 010C0H. 2. The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and WINDOW0 bits. Caution The watchdog timer continues its operation during EEPROM emulation. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. Remark fIL: Low-speed on-chip oscillator clock frequency R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 918 RL78/G13 CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (1/2) Address: 000C1H/010C1H Note 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 * LVD setting (interrupt & reset mode) Detection voltage VLVDH Option byte Setting Value VLVDL Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 0 1 0 Rising Falling Falling edge edge edge 1.77 V 1.73 V 1.63 V 1.88 V 1.84 V 0 1 2.92 V 2.86 V 0 0 1.98 V 1.94 V 1 0 2.09 V 2.04 V 0 1 3.13 V 3.06 V 0 0 2.61 V 2.55 V 1 0 2.71 V 2.65 V 0 1 3.75 V 3.67 V 0 0 2.92 V 2.86 V 1 0 3.02 V 2.96 V 0 1 4.06 V 3.98 V 0 0 LVIMDS1 LVIMDS0 1 0 1.84 V 0 2.45 V 0 2.75 V Other than above 0 1 1 0 0 1 1 Setting prohibited * LVD setting (reset mode) Detection voltage Option byte Setting Value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 0 1 1 Rising edge Falling edge LVIMDS1 LVIMDS0 1.67 V 1.63 V 1 1 1.77 V 1.73 V 0 0 0 1 0 1.88 V 1.84 V 0 0 1 1 1 1.98 V 1.94 V 0 0 1 1 0 2.09 V 2.04 V 0 0 1 0 1 2.50 V 2.45 V 0 1 0 1 1 2.61 V 2.55 V 0 1 0 1 0 2.71 V 2.65 V 0 1 0 0 1 2.81 V 2.75 V 0 1 1 1 1 2.92 V 2.86 V 0 1 1 1 0 3.02 V 2.96 V 0 1 1 0 1 3.13 V 3.06 V 0 0 1 0 0 3.75 V 3.67 V 0 1 0 0 0 4.06 V 3.98 V 0 1 1 0 0 Other than above Note Setting prohibited Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is replaced by 010C1H. Caution Be sure to set bit 4 to "1". <R> Remark Refer to LVD setting, see 21.1 Functions of Voltage Detector. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 919 RL78/G13 CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 * LVD setting (interrupt mode) Detection voltage Option byte Setting Value VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 0 1 1 1.73 V 0 0 0 1 0 1.88 V 1.84 V 0 0 1 1 1 1.98 V 1.94 V 0 0 1 1 0 2.09 V 2.04 V 0 0 1 0 1 2.50 V 2.45 V 0 1 0 1 1 2.61 V 2.55 V 0 1 0 1 0 2.71 V 2.65 V 0 1 0 0 1 2.81 V 2.75 V 0 1 1 1 1 2.92 V 2.86 V 0 1 1 1 0 3.02 V 2.96 V 0 1 1 0 1 3.13 V 3.06 V 0 0 1 0 0 3.75 V 3.67 V 0 1 0 0 0 4.06 V 3.98 V 0 1 1 0 0 VLVD Mode setting Rising edge Falling edge LVIMDS1 LVIMDS0 1.67 V 1.63 V 0 1 1.77 V Other than above Setting prohibited * LVD setting (LVDOFF) Detection voltage Option byte Setting Value VLVD Mode setting Rising edge Falling edge LVIMDS1 LVIMDS0 - - 0/1 1 Other than above Note VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 1 x x x x Setting prohibited Set the same value as 000C1H to 010C1H when the boot swap operation is used because 000C1H is replaced by 010C1H. Caution Be sure to set bit 4 to "1". Remarks 1. <R> 2. x: don't care Refer to LVD setting, see 21.1 Functions of Voltage Detector. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 920 RL78/G13 CHAPTER 24 OPTION BYTE Figure 24-3. Format of Option Byte (000C2H/010C2H) Note Address: 000C2H/010C2H 7 6 5 4 3 2 1 0 CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating Operating Voltage Frequency Range Range 0 0 LV (low voltage main) mode 1 to 4 MHz 1.6 to 5.5 V 1 0 LS (low speed main) mode 1 to 8 MHz 1.8 to 5.5 V 1 1 HS (high speed main) mode Other than above 2.4 to 5.5 V 2.7 to 5.5 V Setting prohibited FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 1 0 0 0 32 MHz 0 0 0 0 24 MHz 1 0 0 1 16 MHz 0 0 0 1 12 MHz 1 0 1 0 8 MHz 1 0 1 1 4 MHz 1 0 1 1 MHz 1 1 to 16 MHz 1 to 32 MHz Other than above Frequency of the high-speed on-chip oscillator Setting prohibited Note Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 921 RL78/G13 CHAPTER 24 OPTION BYTE 24.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 24-4. Format of On-chip Debug Option Byte (000C3H/010C3H) Note Address: 000C3H/010C3H 7 6 5 4 3 2 1 0 OCDENSET 0 0 0 0 1 0 OCDERSD OCDENSET OCDERSD 0 0 Disables on-chip debug operation. 0 1 Setting prohibited 1 0 Control of on-chip debug operation Enables on-chip debugging. Erases data of flash memory in case of failures in authenticating on-chip debug security ID. 1 1 Enables on-chip debugging. Does not erases data of flash memory in case of failures in authenticating on-chip debug security ID. Note Set the same value as 000C3H to 010C3H when the boot swap operation is used because 000C3H is replaced by 010C3H. Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value. Be sure to set 000010B to bits 6 to 1. Remark The value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become unstable after the setting. However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 922 RL78/G13 CHAPTER 24 OPTION BYTE 24.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the assembler linker option, in addition to describing to the source. When doing so, the contents set by using the linker option take precedence, even if descriptions exist in the source, as mentioned below. A software description example of the option byte setting is shown below. OPT CSEG OPT_BYTE DB 36H ; Does not use interval interrupt of watchdog timer, ; Enables watchdog timer operation, ; Window open period of watchdog timer is 50%, 9 ; Overflow time of watchdog timer is 2 /fIL, ; Stops watchdog timer operation during HALT/STOP mode DB 1AH ; Select 1.63 V for VLVDL ; Select rising edge 1.77 V, falling edge 1.73 V for VLVDH ; Select the interrupt & reset mode as the LVD operation mode DB 2DH ; Select the LV (low voltage main) mode as the flash operation mode DB 85H ; Enables on-chip debug operation, does not erase flash memory and 1 MHz as the frequency of the high-speed on-chip oscillator data when security ID authorization fails When the boot swap function is used during self programming, 000C0H to 000C3H is switched to 010C0H to 010C3H. Describe to 010C0H to 010C3H, therefore, the same values as 000C0H to 000C3H as follows. OPT2 CSEG AT DB 010C0H 36H ; Does not use interval interrupt of watchdog timer, ; Enables watchdog timer operation, ; Window open period of watchdog timer is 50%, 10 ; Overflow time of watchdog timer is 2 /fIL, ; Stops watchdog timer operation during HALT/STOP mode DB 1AH ; Select 1.63 V for VLVDL ; Select rising edge 1.77 V, falling edge 1.73 V for VLVDH ; Select the interrupt & reset mode as the LVD operation mode DB 2DH ; Select the LV (low main voltage) mode as the flash operation mode DB 85H ; Enables on-chip debug operation, does not erase flash memory and 1 MHz as the frequency of the high-speed on-chip oscillator data when security ID authorization fails Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute name of the CSEG pseudo instruction. To specify the option byte to 010C0H to 010C3H in order to use the boot swap function, use the relocation attribute AT to specify an absolute address. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 923 RL78/G13 CHAPTER 25 FLASH MEMORY CHAPTER 25 FLASH MEMORY The RL78/G13 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the "code flash memory", in which programs can be executed, and the "data flash memory", an area for storing data. FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAM 2 to 32 KB Mirror F1000H F0FFFH Data flash memory 0/4/8 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H EFFFFH Reserved Code flash memory 16 to 512 KB 00000H The following three methods for programming the flash memory are available: * Writing to flash memory by using flash memory programmer (see 25.1) * Writing to flash memory by using external device (that Incorporates UART) (see 25.2) * Self-programming (see 25.7) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 924 RL78/G13 CHAPTER 25 FLASH MEMORY 25.1 Writing to Flash Memory by Using Flash Memory Programmer The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78/G13. * PG-FP5, FL-PR5 * E1 on-chip debugging emulator Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the RL78/G13 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the RL78/G13 is mounted on the target system. Remark FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 925 RL78/G13 CHAPTER 25 FLASH MEMORY Table 25-1. Wiring Between RL78/G13 and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer Signal Name I/O Pin No. Pin Name Pin Function 20-pin 24-pin 25-pin 30-pin 32-pin 36-pin 40-pin 44-pin SSOP WQFN (4x4) FLGA (3x3) SSOP WQFN (5x5) FLGA (4x4) WQFN (6x6) LQFP (10x10) 3 23 A5 5 1 6F 1 2 PG-FP5, E1 on-chip FL-PR5 debugging emulator - TOOL0 I/O Transmit/receiv e signal Transmit/receiv e signal TOOL0/ P40 SI/RxD - I/O SCK - Output - - - - - - - - - - CLK - Output - - - - - - - - - - 4 24 B5 6 2 5E 2 3 - RESET /RESET - FLMD0 - Output Reset signal RESET Output VDD Output Mode signal - - - - - - - - I/O VDD voltage VDD generation/ power monitoring 10 6 B3 12 8 6B 10 11 Ground VSS 9 5 B2 11 7 5C 9 10 EVSS - - - - - - - - 8 4 A2 10 6 5D 8 9 10 6 B3 12 8 6B 10 11 - GND - REGC - EMVDD Driving power for TOOL pin Pin Configuration of Dedicated Flash Memory Programmer Signal Name I/O Note VDD 48-pin LQFP (7x7), Pin Function PG-FP5, E1 on-chip FL-PR5 debugging emulator - TOOL0 WQFN (7x7) I/O Transmit/receiv e signal Transmit/receiv e signal SI/RxD - I/O SCK - Output - CLK - Output TOOL0/ P40 - - - Output RESET Reset signal - RESET 52-pin 64-pin LQFP LQFP (10x10) (12x12), LQFP (10x10), TQFP (7x7) 80-pin FBGA (4x4) 100-pin 128-pin LQFP LQFP LQFP LQFP (14x14), (14x14) (14x20) (14x20) LQFP (12x12) 39 4 5 D6 9 12 89 22 - - - - - - - - - - - - - - - - 40 5 6 E7 10 13 90 26 - - - - - - - - 19 22 99 35 /RESET - Output FLMD0 - Output Mode signal I/O VDD voltage VDD generation/ power monitoring 48 13 15 B7 Ground VSS 47 12 13 C7 17 20 97 33 EVSS - - 14 B8 18 21, 43 98, 20 34, 56 VDD - GND - - EMVDD Note Driving power for TOOL pin Note 46 11 12 D7 16 19 96 32 VDD 48 13 - - - - - - EVDD - - 16 A8 20 23, 53 100, 30 36, 57 REGC <R> Pin No. Pin Name Connect REGC pin to ground via a capacitor (0.47 to 1 F). Remark Pins that are not indicated in the above table can be left open when using the flash memory programmer for flash programming. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 926 RL78/G13 CHAPTER 25 FLASH MEMORY 25.1.1 Programming Environment The environment required for writing a program to the flash memory of the RL78/G13 is illustrated below. Figure 25-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 VDD E1 EVDDNote RS-232C VSS, EVSS USB RESET Dedicated flash TOOL0 (dedicated single-line UART) memory programmer RL78/G13 Host machine Note 64-pin, 80-pin, 100-pin and 128-pin products only. A host machine that controls the dedicated flash memory programmer is necessary. To interface between the dedicated flash memory programmer and the RL78/G13, the TOOL0 pin is used for <R> manipulation such as writing and erasing via a dedicated single-line UART. 25.1.2 Communication Mode Communication between the dedicated flash memory programmer and the RL78/G13 is established by serial communication using the TOOL0 pin via a dedicated single-line UART of the RL78/G13. Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps Figure 25-2. Communication with Dedicated Flash Memory Programmer VDD PG-FP5, FL-PR5 E1 Dedicated flash memory programmer VDD EVDD VDD/EVDDNote 3 GND VSS/EVSSNote 3/REGCNote 4 RESETNote 1, /RESETNote 2 TOOL0Note 1 SI/RxDNote 2 RESET TOOL0 RL78/G13 Notes 1. When using E1 on-chip debugging emulator. 2. When using PG-FP5 or FL-PR5. <R> 3. 64-pin, 80-pin, 100-pin and 128-pin products only. <R> 4. Connect REGC pin to ground via a capacitor (0.47 to 1 F). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 927 RL78/G13 CHAPTER 25 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78/G13. See the manual of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details. Table 25-2. Pin Connection Dedicated Flash Memory Programmer Signal Name PG-FP5, FL-PR5 I/O RL78/G13 Pin Function Pin Name E1 on-chip debugging emulator - FLMD0 VDD - Output Mode signal I/O VDD voltage generation/power monitoring VDD - Ground VSS, EVSS, REGC - Driving power for TOOL pin VDD, EVDD GND EMVDD CLK - Output Clock output /RESET - Output Reset signal RESET - RESET Output - TOOL0 I/O Transmit/receive signal TOOL0 SI/RxD - I/O Transmit/receive signal SCK - Output Transfer clock <R> Note Connection x Note - x - x Connect REGC pin to ground via a capacitor (0.47 to 1 F). Remark : Be sure to connect the pin. x: The pin does not have to be connected. 25.2 Writing to Flash Memory by Using External Device (that Incorporates UART) On-board data writing to the internal flash memory is possible by using the RL78/G13 and an external device (a microcontroller or ASIC) connected to a UART. <R> On the development of flash memory programmer by user, refer to the RL78 Microcontrollers (RL78 Protocol A) Programmer Edition Application Note (R01AN0815). 25.2.1 Programming Environment The environment required for writing a program to the flash memory of the RL78/G13 is illustrated below. Figure 25-3. Environment for Writing Program to Flash Memory VDD, EVDD VSS, EVSS RESET External device (such as microcontroller and ASIC) UART (TOOLTxD, TOOLRxD) RL78/G13 TOOL0 Processing to write data to or delete data from the RL78/G13 by using an external device is performed on-board. Offboard writing is not possible. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 928 RL78/G13 CHAPTER 25 FLASH MEMORY 25.2.2 Communication Mode Communication between the external device and the RL78/G13 is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78/G13. Transfer rate: 1 M, 500 k, 250 k, 115.2kbps Figure 25-4. Communication with External Device VDD GND /RESET External device (such as microcontroller and ASIC) Note VSS/EVSS/REGCNote RESET RxD TOOLTxD TxD TOOLRxD PORT <R> VDD/EVDD RL78/G13 TOOL0 Connect REGC pin to ground via a capacitor (0.47 to 1 F). Caution Make EVDD the same potential as VDD. The external device generates the following signals for the RL78/G13. Table 25-3. Pin Connection External Device Signal Name VDD I/O I/O - GND RL78/G13 Pin Function Pin Name VDD voltage generation/power monitoring VDD, EVDD Ground VSS, EVSS, REGC CLK Output Clock output RESETOUT Output Reset signal output RESET RxD Input Receive signal TOOL0TxD TxD Output Transmit signal TOOL0RxD PORT Output Mode signal TOOL0 SCK Output Transfer clock <R> Note Connection Note - x - x Connect REGC pin to ground via a capacitor (0.47 to 1 F). Caution Make EVDD the same potential as VDD. Remark : Be sure to connect the pin. x: The pin does not have to be connected. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 929 RL78/G13 CHAPTER 25 FLASH MEMORY 25.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. <R> Remark Refer to flash programming mode, see 25.7 Flash Memory Programming by Self-Programming. 25.3.1 P40/TOOL0 pin In the flash memory programming mode, connect this pin to the dedicated flash memory programmer via an external 1 k pull-up resistor. When this pin is used as the port pin, use that by the following method. When used as an input pin: Input of low-level is prohibited for 1 ms period after pin reset release. Furthermore, when this pin is used via pull-down resistors, use the 500 k or more resistors. When used as an output pin: When this pin is used via pull-down resistors, use the 500 k or more resistors. Remark The SAU and IICA pins are not used for communication between the RL78/G13 and dedicated flash memory programmer, because single-line UART (TOOL0 pin) is used. 25.3.2 RESET pin Signal conflict will occur if the reset signal of the dedicated flash memory programmer and external device are connected to the RESET pin that is connected to the reset signal generator on the board. To prevent this conflict, isolate the connection with the reset signal generator. The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash memory programming mode is set. Do not input any signal other than the reset signal of the dedicated flash memory programmer and external device. Figure 25-5. Signal Conflict (RESET Pin) RL78/G13 Signal conflict Input pin Dedicated flash memory programmer connection pin Another device Output pin In the flash memory programming mode, a signal output by another device will conflict with the signal output by the dedicated flash memory programmer. Therefore, isolate the signal of another device. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 930 RL78/G13 CHAPTER 25 FLASH MEMORY 25.3.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to either to VDD or EVDD, or VSS or EVSS, via a resistor. 25.3.4 REGC pin Connect the REGC pin to GND via a capacitor (0.47 to 1 F) in the same manner as during normal operation. Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. 25.3.5 X1 and X2 pins Connect X1 and X2 in the same status as in the normal operation mode. Remark In the flash memory programming mode, the high-speed on-chip oscillator clock (fIH) is used. 25.3.6 Power supply To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory programmer, and the VSS pin to GND of the flash memory programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode. However, when writing to the flash memory by using the flash memory programmer and using the on-board supply voltage, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the power monitor function with the flash memory programmer. Supply the same other power supplies (EVDD, EVSS) as those VDD and VSS. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 931 RL78/G13 CHAPTER 25 FLASH MEMORY 25.4 Data Flash 25.4.1 Data flash overview In addition to 16 to 512 KB of code flash memory, the RL78/G13 with data flash includes 4/8 KB of data flash memory for storing data. FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAM 2 to 32 KB Mirror F1000H F0FFFH Data flash memory 4/8 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H EFFFFH Reserved Code flash memory 16 to 512 KB 00000H R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 932 RL78/G13 CHAPTER 25 FLASH MEMORY An overview of the data flash memory is provided below. * The data flash memory can be written to by using the flash memory programmer or an external device * Programming is performed in 8-bit units * Blocks can be deleted in 1 KB units <R> * The only access by CPU instructions is byte reading (1 clock cycle + wait 3 clock cycles) * Because the data flash memory is an area exclusively used for data, it cannot be used to execute instructions (code fetching) * Instructions can be executed from the code flash memory while rewriting the data flash memory (That is, back ground operation (BGO) is supported) * Accessing the data flash memory is not possible while rewriting the code flash memory (during self programming) * Because the data flash memory is stopped after a reset ends, the data flash control register (DFLCTL) must be set up in order to use the data flash memory * Manipulating the DFLCTL register is not possible while rewriting the data flash memory <R> * Transition the HALT/STOP status is not possible while rewriting the data flash memory <R> Remark Refer to flash programming mode, see 25.7 Flash Memory Programming by Self-Programming. 25.4.2 Register controlling data flash memory (1) Data flash control register (DFLCTL) This register is used to enable or disable accessing to the data flash. The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 00H. Figure 25-6. Format of Data Flash Control Register (DFLCTL) Address: F0090H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 DFLCTL 0 0 0 0 0 0 0 DFLEN DFLEN Data flash access control 0 Disables data flash access 1 Enables data flash access Caution Manipulating the DFLCTL register is not possible while rewriting the data flash memory. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 933 RL78/G13 CHAPTER 25 FLASH MEMORY 25.4.3 Procedure for accessing data flash memory The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To access the memory, perform the following procedure: <1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL). <2> Wait for the setup to finish for software timer.etc. The time setup takes differs for each main clock mode. <Setup time for each main clock mode> * HS (High-speed main): 5 s * LS (Low-speed main): 720 ns * LV (Low-voltage main): 10 s <3> After the wait, the data flash memory can be accessed. Cautions 1. Accessing the data flash memory is not possible during the setup time. 2. Before executing a STOP instruction during the setup time, temporarily clear DFLEN to 0. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 934 RL78/G13 CHAPTER 25 FLASH MEMORY 25.5 Programming Method 25.5.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 25-7. Flash Memory Manipulation Procedure Start Controlling TOOL0 pin and RESET pin Flash memory programming mode is set Manipulate flash memory End? No Yes End R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 935 RL78/G13 CHAPTER 25 FLASH MEMORY 25.5.2 Flash memory programming mode To rewrite the contents of the flash memory, set the RL78/G13 in the flash memory programming mode. To enter the mode, set as follows. <When programming by using the dedicated flash memory programmer> Communication from the dedicated flash memory programmer is performed to automatically switch to the flash memory programming mode. <When programming by using an external device> Set the TOOL0 pin to the low level, and then cancel the reset. Keep the TOOL0 pin at the low level from the reset ends to 1 ms + software processing end, and then use UART communication to send the data "00H" from the external device. Finish UART communication within 100 ms after the reset ends. Figure 25-8. Setting of Flash Memory Programming Mode <R> <1> <2> <4> <3> RESET tHD+ soft processing 00H reception (TOOLRxD, TOOLTxD mode) TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The pins reset ends (POR and LVD reset must end before the pin reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end (except soft processing time) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 936 RL78/G13 CHAPTER 25 FLASH MEMORY Table 25-4. Relationship Between TOOL0 Pin and Operation Mode After Reset Release TOOL0 VDD Operation Mode Normal operation mode 0 Flash memory programming mode There are two flash memory programming modes for which the voltage range in which to write, erase, or verify data differs. <R> Table 25-5. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified Mode Voltages at which data can be written, erased, or verified Writing Clock Frequency Wide voltage mode 1.8 V to 5.5 V 8 MHz (MAX.) 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 32 MHz (MAX.) 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 32 MHz (MAX.) Full speed mode Note Note This can only be specified if the CMODE1 and CMODE0 bits of the option byte 000C2H are 1. Specify the mode that corresponds to the voltage range in which to write data. When programming by using the dedicated flash memory programmer, the mode is automatically selected by the voltage setting on GUI. Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing, deletion, or verification. 2. For details about communication commands, see 25.5.4 Communication commands. 25.5.3 Selecting communication mode Communication mode of the RL78/G13 as follows. Table 25-6. Communication Modes Communication Mode 1-line mode Standard Setting Port UART (when flash memory programmer is used) Dedicated UART (when external device is used) Speed Note 2 115200 bps, Note 1 Pins Used Frequency Multiply Rate - - TOOL0 - - TOOLTxD, 250000 bps, 500000 bps, 1 Mbps UART 115200 bps, 250000 bps, TOOLRxD 500000 bps, 1 Mbps Notes 1. Selection items for Standard settings on GUI of the flash memory programmer. 2. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 937 RL78/G13 CHAPTER 25 FLASH MEMORY 25.5.4 Communication commands The RL78/G13 communicates with the dedicated flash memory programmer or external device by using commands. The signals sent from the flash memory programmer or external device to the RL78/G13 are called commands, and the signals sent from the RL78/G13 to the dedicated flash memory programmer or external device are called response. Figure 25-9. Communication Commands Dedicated flash memory programmer E1 PG-FP5, FL-PR5 Command Response RL78/G13 External device (such as microcontroller and ASIC) The flash memory control commands of the RL78/G13 are listed in the table below. All these commands are issued from the programmer or external device, and the RL78/G13 perform processing corresponding to the respective commands. Table 25-7. Flash Memory Control Commands Classification Verify Command Name Function Compares the contents of a specified area of the flash memory with Verify data transmitted from the programmer. Erase Block Erase Erases a specified area in the flash memory. Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly erased. Write Programming Writes data to a specified area in the flash memory. Getting information Silicon Signature Gets the RL78/G13 information (such as the part number, flash memory configuration, and programming firmware version). Security Others Checksum Gets the checksum data for a specified area. Security Set Sets security information. Security Get Gets security information. Security Release Release setting of prohibition of writing. Reset Used to detect synchronization status of communication. Baud Rate Set Sets baud rate when UART communication mode is selected. The RL78/G13 returns a response for the command issued by the dedicated flash memory programmer or external device. The response names sent from the RL78/G13 are listed below. Table 25-8. Response Names Response Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 938 RL78/G13 CHAPTER 25 FLASH MEMORY 25.5.5 Description of signature data When the "silicon signature" command is performed, the RL78/G13 information (such as the part number, flash memory configuration, and programming firmware version) can be obtained. Table 25-9 and 25-10 show signature data list and example of signature data list. Table 25-9. Signature Data List Field name Number of transmit Description data Device code The serial number assigned to the device 3 bytes Device name Device name (ASCII code) 10 bytes Code flash memory area last address Last address of code flash memory area 3 bytes (Sent from lower address. Example. 00000H to 0FFFFH (64 KB) FFH, 1FH, 00H) Data flash memory area last address Last address of data flash memory area 3 bytes (Sent from lower address. Example. F1000H to F1FFFH (4 KB) FFH, 1FH, 0FH) Firmware version Version information of firmware for programming 3 bytes (Sent from upper address. Example. From Ver. 1.23 01H, 02H, 03H) Table 25-10. Example of Signature Data Field name Description Number of transmit Data (hexadecimal) data <R> Device code RL78 protocol A 3 bytes 10 00 06 Device name RSF100LE 10 bytes 52 = "R" 35 = "5" 46 = "F" 31 = "1" 30 = "0" 30 = "0" 4C = "L" 45 = "E" 20 = " " 20 = " " Code flash memory area last address Code flash memory area 3 bytes 00000H to 0FFFFH (64 KB) FF FF 00 Data flash memory area last address Data flash memory area 3 bytes F1000H to F1FFFH (4 KB) FF 1F 0F Firmware version Ver.1.23 3 bytes 01 02 03 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 939 RL78/G13 CHAPTER 25 FLASH MEMORY 25.6 Security Settings The RL78/G13 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. * Disabling block erase Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-board programming. However, blocks can be erased by means of self programming. * Disabling write Execution of the write command for entire blocks in the flash memory is prohibited during on-board/off-board programming. However, blocks can be written by means of self programming. * Disabling rewriting boot cluster 0 Execution of the block erase command and write command on boot cluster 0 (00000H to 00FFFH) in the flash memory is prohibited by this setting. <R> After the security settings are specified, releasing the security settings by the Security Release command is enabled by a reset. The block erase, write commands and rewriting boot cluster 0 are enabled by the default setting when the flash memory is shipped. Security can be set by on-board/off-board programming and self programming. Each security setting can be used in combination. Table 25-11 shows the relationship between the erase and write commands when the RL78/G13 security function is enabled. <R> Caution The security function of the flash programmer does not support self-programming. Remark To prohibit writing and erasing during self-programming, use the flash sealed window function (see 25.7.2 for detail). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 940 RL78/G13 CHAPTER 25 FLASH MEMORY Table 25-11. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Block Erase Write Note Prohibition of block erase Blocks cannot be erased. Can be performed. Prohibition of writing Blocks can be erased. Cannot be performed. Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Note Confirm that no data has been written to the write area. Because data cannot be erased after block erase is prohibited, do not write data if the data has not been erased. (2) During self programming Valid Security Executed Command Block Erase Prohibition of block erase Write Blocks can be erased. Can be performed. Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Prohibition of writing Prohibition of rewriting boot cluster 0 Remark To prohibit writing and erasing during self-programming, use the flash sealed window function (see 25.7.2 for detail). Table 25-12. Setting Security in Each Programming Mode (1) On-board/off-board programming Security Security Setting How to Disable Security Setting Prohibition of block erase Set via GUI of dedicated flash memory Cannot be disabled after set. Prohibition of writing programmer, etc. Execute security release command Prohibition of rewriting boot cluster 0 Cannot be disabled after set. Caution The security release command can be applied only when the security is not set as the block erase prohibition and the boot cluster 0 rewrite prohibition with code flash memory area and data flash memory area being blanks. (2) Self programming Security Security Setting How to Disable Security Setting Prohibition of block erase Set by using flash self programming Cannot be disabled after set. Prohibition of writing library. Execute security release command during on-board/off-board programming (cannot be disabled during self programming) Prohibition of rewriting boot cluster 0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Cannot be disabled after set. 941 RL78/G13 CHAPTER 25 FLASH MEMORY 25.7 Flash Memory Programming by Self-Programming The RL78/G13 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the RL78/G13 self-programming library, it can be used to upgrade the program in the field. Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock. 2. To prohibit an interrupt during self-programming, in the same way as in the normal operation mode, execute the self-programming library in the state where the IE flag is cleared (0) by the DI instruction. To enable an interrupt, clear (0) the interrupt mask flag to accept in the state where the IE flag is set (1) by the EI instruction, and then execute the self-programming library. <R> 3. When enabling RAM parity error resets (RPERDIS = 0), be sure to initialize the RAM area to use + 10 bytes before overwriting. Remarks 1. For details of the self-programming function and the RL78/G13 self-programming library, refer to RL78 2. For details of the time required to execute self programming, see the notes on use that accompany the Microcontroller Self Programming Library Type01 User's Manual (R01AN0350E). flash self programming library tool. Similar to when writing data by using the flash memory programmer, there are two flash memory programming modes for which the voltage range in which to write, erase, or verify data differs. Table 25-13. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified Mode Voltages at which data can be written, erased, or verified Wide voltage mode 1.8 V to 5.5 V 8 MHz (MAX.) 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 32 MHz (MAX.) <R> <R> Full speed mode Note Writing Clock Frequency 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 32 MHz (MAX.) Note This can only be specified if the CMODE1 and CMODE0 bits of the option byte 000C2H are 1. Specify the mode that corresponds to the voltage range in which to write data. If the argument fsl_flash_voltage_u08 is other than 00H when the FSL_Init function of the self programming library provided by Renesas Electronics is executed, wide-voltage mode is specified. If the argument is 00H, full-speed mode is specified. Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing, deletion, or 2. For details of the self-programming function and the RL78/G13 self-programming library, refer to RL78 verification. Microcontroller Self Programming Library Type01 User's Manual (R01AN0350E). R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 942 RL78/G13 CHAPTER 25 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming library. Figure 25-10. Flow of Self Programming (Rewriting Flash Memory) Flash memory control start Initialize flash environment Flash shield window setting Erase Write Verify * Inhibit access to flash memory * Inhibit shifting STOP mode * Inhibit clock stop Flash information getting Flash information setting Close flash environment End R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 943 RL78/G13 CHAPTER 25 FLASH MEMORY 25.7.1 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot program area, by self-programming, write a new boot program to boot cluster 1 in advance. When the program has been correctly written to boot cluster 1, swap this boot cluster 1 and boot cluster 0 by using the set information function of the firmware of the RL78/G13, so that boot cluster 1 is used as a boot area. After that, erase or write the original boot program area, boot cluster 0. As a result, even if a power failure occurs while the boot programming area is being rewritten, the program is executed correctly because it is booted from boot cluster 1 to be swapped when the program is reset and started next. Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function. Figure 25-11. Boot Swap Function XXXXXH User program Self-programming to boot cluster 1 Execution of boot swap by firmware User program User program Self-programming to boot cluster 0 User program 02000H User program New boot program (boot cluster 1) Boot program (boot cluster 0) Boot program (boot cluster 0) Boot program (boot cluster 0) New boot program (boot cluster 1) 01000H 00000H Boot Boot New user program (boot cluster 0) Boot New boot program (boot cluster 1) Boot In an example of above figure, it is as follows. Boot cluster 0: Boot program area before boot swap Boot cluster 1: Boot program area after boot swap R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 944 RL78/G13 CHAPTER 25 FLASH MEMORY Figure 25-12. Example of Executing Boot Swapping Block number Erasing block 4 Boot cluster 1 Boot cluster 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Program Program Program Program Boot program Boot program Boot program Boot program 01000H 00000H Program Program Program Boot program Boot program Boot program Boot program Erasing block 5 7 6 5 4 3 2 1 0 Program Program Boot program Boot program Boot program Boot program Erasing block 6 Program 7 6 5 4 3 Boot program 2 Boot program 1 Boot program 0 Boot program Erasing block 7 7 6 5 4 3 Boot program 2 Boot program 1 Boot program 0 Boot program Booted by boot cluster 0 Writing blocks 4 to 7 7 New boot program 6 New boot program 5 New boot program 4 New boot program 3 Boot program 2 Boot program 1 Boot program 0 Boot program Boot swap 7 6 5 4 3 2 1 0 Boot program Boot program Boot program Boot program 01000H New boot program New boot program New boot program New boot program 0 0 0 0 0 H Erasing block 4 Erasing block 5 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Boot program Boot program Boot program New boot program New boot program New boot program New boot program Boot program Boot program New boot program New boot program New boot program New boot program Booted by boot cluster 1 Erasing block 6 7 6 5 4 3 2 1 0 Boot program New boot program New boot program New boot program New boot program R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Erasing block 7 7 6 5 4 3 2 1 0 New boot program New boot program New boot program New boot program Writing blocks 4 to 7 7 6 5 4 3 2 1 0 New program New program New program New program 01000H New boot program New boot program New boot program New boot program 0 0 0 0 0 H 945 RL78/G13 CHAPTER 25 FLASH MEMORY 25.7.2 Flash shield window function The flash shield window function is provided as one of the security functions for self programming. It disables writing to and erasing areas outside the range specified as a window only during self programming. The window range can be set by specifying the start and end blocks. The window range can be set or changed during both on-board/off-board programming and self programming. Writing to and erasing areas outside the window range are disabled during self programming. During on-board/offboard programming, however, areas outside the range specified as a window can be written and erased. Figure 25-13. Flash Shield Window Setting Example (Target Devices: R5F100LE, Start Block: 04H, End Block: 06H) 0FFFFH Flash shield range Methods by which writing can be performed Block 3FH : On-board/off-board programming x: Self programming Block 3EH 01C00H 01BFFH Window range Block 06H (end block) : On-board/off-board programming : Self programming Block 05H Flash memory area 01000H 00FFFH Block 04H (start block) Block 03H Block 02H Flash shield range : On-board/off-board programming x: Self programming Block 01H 00000H Block 00H Cautions 1. If the rewrite-prohibited area of the boot cluster 0 overlaps with the flash shield window range, prohibition to rewrite the boot cluster 0 takes priority. 2. The flash shield window can only be used for the code flash memory (and is not supported for the data flash memory). Table 25-14. Relationship between Flash Shield Window Function Setting/Change Methods and Commands Programming conditions Window Range Execution Commands Setting/Change Methods Self-programming Block erase Write Specify the starting and Block erasing is enabled Writing is enabled only ending blocks by the only within the window within the range of flash self programming range. window range. library. On-board/Off-board Specify the starting and Block erasing is enabled Writing is enabled also programming ending blocks on GUI of also outside the window outside the window dedicated flash memory range. range. programmer, etc. Remark See 25.6 Security Settings to prohibit writing/erasing during on-board/off-board programming. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 946 RL78/G13 CHAPTER 26 ON-CHIP DEBUG FUNCTION CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.1 Connecting E1 On-chip Debugging Emulator to RL78/G13 The RL78/G13 uses the VDD, RESET, TOOL0, and VSS pins to communicate with the host machine via an E1 on-chip debugging emulator. Serial communication is performed by using a single-line UART that uses the TOOL0 pin. Caution The RL78/G13 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Figure 26-1. Connection Example of E1 On-chip Debugging Emulator and RL78/G13 E1 target connector VDD VDD VDD/EVDD EVDD RL78/G13 VDD VDD EVDD EMVDD GND GND GND VDD/EVDD GND 1 k TOOL0 TOOL0 RESET RESET TRESET RESET VDD 10 k 1 k Note 2 Note 1 Reset circuit Reset signal Notes 1. Connecting the dotted line is not necessary during flash programming. 2. If the reset circuit on the target system does not have a buffer and generates a reset signal only with resistors and capacitors, this pull-up resistor is not necessary. Caution This circuit diagram is assumed that the reset signal outputs from an N-ch O.D. buffer (output resistor: 100 or less) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 947 RL78/G13 CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.2 On-Chip Debug Security ID The RL78/G13 has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 24 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content. When the boot swap function is used, also set a value that is the same as that of 010C3H and 010C4H to 010CDH in advance, because 000C3H, 000C4H to 000CDH and 010C3H, and 010C4H to 010CDH are switched. Table 26-1. On-Chip Debug Security ID Address 000C4H to 000CDH On-Chip Debug Security ID Any ID code of 10 bytes 010C4H to 010CDH 26.3 Securing of User Resources To perform communication between the RL78/G13 and E1 on-chip debugging emulator, as well as each debug function, the securing of memory space must be done beforehand. If Renesas Electronics assembler or compiler is used, the items can be set by using linker options. (1) Securement of memory space The shaded portions in Figure 26-2 are the areas reserved for placing the debug monitor program, so user programs or data cannot be allocated in these spaces. When using the on-chip debug function, these spaces must be secured so as not to be used by the user program. Moreover, this area must not be rewritten by the user program. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 948 RL78/G13 CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-2. Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area Note 1 (512 bytes or 256 bytes Note 2) Stack area for debugging Internal RAM (4 bytes) Note 4 area Mirror area Code flash area : Area used for on-chip debugging 01000H 000D8H 000CEH Debug monitor area (10 bytes) 000C4H Security ID area (10 bytes) On-chip debug option byte area (1 byte) 000C3H 00002H 00000H Debug monitor area (2 bytes) Note 3 Notes 1. Address differs depending on products as follows. Products (code flash memory capacity) Address of Note 1 R5F100xA, R5F101xA (x = 6 to 8, A to C, E to G) 03FFFH R5F100xC, R5F101xC (x = 6 to 8, A to C, E to G, J, L) 07FFFH R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L) 0BFFFH R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L) 0FFFFH R5F100xF, R5F101xF (x = A to C, E to G, J, L, M, P) 17FFFH R5F100xG, R5F101xG (x = A to C, E to G, J, L, M, P) 1FFFFH R5F100xH, R5F101xH (x = E to G, J, L, M, P, S) 2FFFFH R5F100xJ, R5F101xJ (x = F, G, J, L, M, P, S) 3FFFFH R5F100xK, R5F101xK (x = F, G, J, L, M, P, S) 5FFFFH R5F100xL, R5F101xL (x = F, G, J, L, M, P, S) 7FFFFH 2. When real-time RAM monitor (RRM) function and dynamic memory modification (DMM) function are not used, it is 256 bytes. 3. In debugging, reset vector is rewritten to address allocated to a monitor program. 4. Since this area is allocated immediately before the stack area, the address of this area varies depending on the stack increase and decrease. That is, 4 extra bytes are consumed for the stack area used. When using self-programming, 12 extra bytes are consumed for the stack area used. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 949 RL78/G13 CHAPTER 27 BCD CORRECTION CIRCUIT CHAPTER 27 BCD CORRECTION CIRCUIT 27.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ). 27.2 Registers Used by BCD Correction Circuit The BCD correction circuit uses the following registers. * BCD correction result register (BCDADJ) (1) BCD correction result register (BCDADJ) The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through add/subtract instructions using the A register as the operand. The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. The BCDADJ register is read by an 8-bit memory manipulation instruction. Reset input sets this register to undefined. Figure 27-1. Format of BCD Correction Result Register (BCDADJ) Address: F00FEH Symbol After reset: undefined 7 6 R 5 4 3 2 1 0 BCDADJ R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 950 RL78/G13 CHAPTER 27 BCD CORRECTION CIRCUIT 27.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1> The BCD code value to which addition is performed is stored in the A register. <2> By adding the value of the A register and the second operand (value of one more BCD code to be added) as are in binary, the binary operation result is stored in the A register and the correction value is stored in the BCD correction result register (BCDADJ). <3> Decimal correction is performed by adding in binary the value of the A register (addition result in binary) and the BCDADJ register (correction value), and the correction result is stored in the A register and CY flag. Caution The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. Therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. To perform BCD correction in the interrupt enabled state, saving and restoring the A register is required within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction. An example is shown below. Examples 1: 99 + 89 = 188 Instruction A Register CY Flag AC Flag BCDADJ Register MOV A, #99H ; <1> 99H - - - ADD A, #89H ; <2> 22H 1 1 66H ADD A, !BCDADJ ; <3> 88H 1 0 - A Register CY Flag AC Flag BCDADJ Register ; <1> 85H - - - ADD A, #15H ; <2> 9AH 0 0 66H ADD A, !BCDADJ ; <3> 00H 1 1 - A Register CY Flag AC Flag BCDADJ Register Examples 2: 85 + 15 = 100 Instruction MOV A, #85H Examples 3: 80 + 80 = 160 Instruction MOV A, #80H ; <1> 80H - - - ADD A, #80H ; <2> 00H 1 0 60H ADD A, !BCDADJ ; <3> 60H 1 0 - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 951 RL78/G13 CHAPTER 27 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register. <2> By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is in binary, the calculation result in binary is stored in the A register, and the correction value is stored in the BCD correction result register (BCDADJ). <3> Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A register (subtraction result in binary) in binary, and the correction result is stored in the A register and CY flag. Caution The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. Therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. To perform BCD correction in the interrupt enabled state, saving and restoring the A register is required within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction. An example is shown below. Example: 91 - 52 = 39 Instruction A Register CY Flag AC Flag BCDADJ Register MOV A, #91H ; <1> 91H - - - SUB A, #52H ; <2> 3FH 0 1 06H SUB A, !BCDADJ ; <3> 39H 0 0 - R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 952 RL78/G13 CHAPTER 28 INSTRUCTION SET CHAPTER 28 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Microcontrollers User's Manual: software. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 953 RL78/G13 CHAPTER 28 INSTRUCTION SET 28.1 Conventions Used in Operation List 28.1.1 Operand identifiers and specification methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are keywords and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: 16-bit absolute address specification * !!: 20-bit absolute address specification * $: 8-bit relative address specification * $!: 16-bit relative address specification * [ ]: Indirect address specification * ES:: Extension address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, !!, $, $!, [ ], and ES: symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 28-1. Operand Identifiers and Specification Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special-function register symbol (SFR symbol) FFF00H to FFFFFH sfrp Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses only Note ) FFF00H to FFFFFH saddr FFE20H to FFF1FH Immediate data or labels saddrp FFE20H to FF1FH Immediate data or labels (even addresses only addr20 00000H to FFFFFH Immediate data or labels addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions addr5 0080H to 00BFH Immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label RBn RB0 to RB3 Note Note ) Note ) Bit 0 = 0 when an odd address is specified. Remark The special function registers can be described to operand sfr as symbols. See Table 3-5 SFR List for the symbols of the special function registers. The extended special function registers can be described to operand !addr16 as symbols. See Table 3-6 Extended SFR (2nd SFR) List for the symbols of the extended special function registers. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 954 RL78/G13 CHAPTER 28 INSTRUCTION SET 28.1.2 Description of operation column The operation when the instruction is executed is shown in the "Operation" column using the following symbols. Table 28-2. Symbols in "Operation" Column Symbol Function A A register; 8-bit accumulator X X register B B register C C register D D register E E register H H register L L register ES ES register CS CS register AX AX register pair; 16-bit accumulator BC BC register pair DE DE register pair HL HL register pair PC Program counter SP Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag () Memory contents indicated by address or register contents in parentheses X H, X L 16-bit registers: XH = higher 8 bits, XL = lower 8 bits XS, XH, XL 20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0) Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) - Inverted data addr5 16-bit immediate data (even addresses only in 0080H to 00BFH) addr16 16-bit immediate data addr20 20-bit immediate data jdisp8 Signed 8-bit data (displacement value) jdisp16 Signed 16-bit data (displacement value) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 955 RL78/G13 CHAPTER 28 INSTRUCTION SET 28.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the "Flag" column using the following symbols. Table 28-3. Symbols in "Flag" Column Symbol Change of Flag Value (Blank) Unchanged 0 Cleared to 0 1 Set to 1 x R Set/cleared according to the result Previously saved value is restored 28.1.4 PREFIX instruction Instructions with "ES:" have a PREFIX operation code as a prefix to extend the accessible data area to the 1 MB space (00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a PREFIX operation code is attached as a prefix to the target instruction, only one instruction immediately after the PREFIX operation code is executed as the addresses with the ES register value added. A interrupt and DMA transfer are not acknowledged between a PREFIX instruction code and the instruction immediately after. Table 28-4. Use Example of PREFIX Operation Code Instruction Opcode 1 2 3 !addr16 4 5 #byte - MOV !addr16, #byte CFH MOV ES:!addr16, #byte 11H CFH MOV A, [HL] 8BH - - - - MOV A, ES:[HL] 11H 8BH - - - !addr16 #byte Caution Set the ES register value with MOV ES, A, etc., before executing the PREFIX instruction. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 956 RL78/G13 CHAPTER 28 INSTRUCTION SET 28.2 Operation List Table 28-5. Operation List (1/17) Instruction Mnemonic Group 8-bit data transfer Notes 1. MOV Operands Bytes Clocks Clocks Note 1 Note 2 Z r, #byte 2 1 - r byte PSW, #byte 3 3 - PSW byte CS, #byte 3 1 - CS byte ES, #byte 2 1 - ES byte !addr16, #byte 4 1 - (addr16) byte ES:!addr16, #byte 5 2 - (ES, addr16) byte saddr, #byte 3 1 - (saddr) byte sfr, #byte 3 1 - sfr byte [DE+byte], #byte 3 1 - (DE+byte) byte ES:[DE+byte],#byte 4 2 - ((ES, DE)+byte) byte [HL+byte], #byte 3 1 - (HL+byte) byte ES:[HL+byte],#byte 4 2 - ((ES, HL)+byte) byte [SP+byte], #byte 3 1 - (SP+byte) byte word[B], #byte 4 1 - (B+word) byte ES:word[B], #byte 5 2 - ((ES, B)+word) byte word[C], #byte 4 1 - (C+word) byte ES:word[C], #byte 5 2 - ((ES, C)+word) byte word[BC], #byte 4 1 - (BC+word) byte ES:word[BC], #byte 5 2 - ((ES, BC)+word) byte 1 1 - Ar A, r Note 3 r, A Note 3 Flag 1 1 - rA A, PSW 2 1 - A PSW PSW, A 2 3 - PSW A A, CS 2 1 - A CS CS, A 2 1 - CS A A, ES 2 1 - A ES ES, A 2 1 - ES A A, !addr16 3 1 4 A (addr16) A, ES:!addr16 4 2 5 A (ES, addr16) !addr16, A 3 1 - (addr16) A ES:!addr16, A 4 2 - (ES, addr16) A A, saddr 2 1 - A (saddr) saddr, A 2 1 - (saddr) A AC CY x x x x x x Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 957 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Group 8-bit data transfer Notes 1. MOV Clocks Clocks Note 1 Note 2 Flag Z A, sfr 2 1 - A sfr sfr, A 2 1 - sfr A A, [DE] 1 1 4 A (DE) [DE], A 1 1 - (DE) A A, ES:[DE] 2 2 5 A (ES, DE) ES:[DE], A 2 2 - (ES, DE) A A, [HL] 1 1 4 A (HL) [HL], A 1 1 - (HL) A A, ES:[HL] 2 2 5 A (ES, HL) ES:[HL], A 2 2 - (ES, HL) A A, [DE+byte] 2 1 4 A (DE + byte) [DE+byte], A 2 1 - (DE + byte) A A, ES:[DE+byte] 3 2 5 A ((ES, DE) + byte) ES:[DE+byte], A 3 2 - ((ES, DE) + byte) A A, [HL+byte] 2 1 4 A (HL + byte) [HL+byte], A 2 1 - (HL + byte) A A, ES:[HL+byte] 3 2 5 A ((ES, HL) + byte) ES:[HL+byte], A 3 2 - ((ES, HL) + byte) A A, [SP+byte] 2 1 - A (SP + byte) [SP+byte], A 2 1 - (SP + byte) A A, word[B] 3 1 4 A (B + word) word[B], A 3 1 - (B + word) A A, ES:word[B] 4 2 5 A ((ES, B) + word) ES:word[B], A 4 2 - ((ES, B) + word) A A, word[C] 3 1 4 A (C + word) word[C], A 3 1 - (C + word) A A, ES:word[C] 4 2 5 A ((ES, C) + word) ES:word[C], A 4 2 - ((ES, C) + word) A A, word[BC] 3 1 4 A (BC + word) word[BC], A 3 1 - (BC + word) A A, ES:word[BC] 4 2 5 A ((ES, BC) + word) ES:word[BC], A 4 2 - ((ES, BC) + word) A AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 958 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Group 8-bit data MOV transfer Note 1 Note 2 2 1 4 A (HL + B) [HL+B], A 2 1 - (HL + B) A A, ES:[HL+B] 3 2 5 A ((ES, HL) + B) ES:[HL+B], A 3 2 - ((ES, HL) + B) A A, [HL+C] 2 1 4 A (HL + C) [HL+C], A 2 1 - (HL + C) A A, ES:[HL+C] 3 2 5 A ((ES, HL) + C) ES:[HL+C], A 3 2 - ((ES, HL) + C) A X, !addr16 3 1 4 X (addr16) X, ES:!addr16 4 2 5 X (ES, addr16) X, saddr 2 1 - X (saddr) B, !addr16 3 1 4 B (addr16) B, ES:!addr16 4 2 5 B (ES, addr16) B, saddr 2 1 - B (saddr) C, !addr16 3 1 4 C (addr16) C, ES:!addr16 4 2 5 C (ES, addr16) C, saddr 2 1 - C (saddr) 3 1 - ES (saddr) 1 (r = X) 1 - A r A, r Note 3 Flag Z A, [HL+B] ES, saddr XCH Clocks Clocks AC CY 2 (other than r = X) Notes 1. A, !addr16 4 2 - A (addr16) A, ES:!addr16 5 3 - A (ES, addr16) A, saddr 3 2 - A (saddr) A, sfr 3 2 - A sfr A, [DE] 2 2 - A (DE) A, ES:[DE] 3 3 - A (ES, DE) A, [HL] 2 2 - A (HL) A, ES:[HL] 3 3 - A (ES, HL) A, [DE+byte] 3 2 - A (DE + byte) A, ES:[DE+byte] 4 3 - A ((ES, DE) + byte) A, [HL+byte] 3 2 - A (HL + byte) A, ES:[HL+byte] 4 3 - A ((ES, HL) + byte) Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 959 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Group 8-bit data XCH transfer ONEB CLRB MOVS 16-bit MOVW data Note 1 Note 2 Flag Z AC CY A, [HL+B] 2 2 - A (HL+B) A, ES:[HL+B] 3 3 - A ((ES, HL)+B) A, [HL+C] 2 2 - A (HL+C) A, ES:[HL+C] 3 3 - A ((ES, HL)+C) A 1 1 - A 01H X 1 1 - X 01H B 1 1 - B 01H C 1 1 - C 01H !addr16 3 1 - (addr16) 01H ES:!addr16 4 2 - (ES, addr16) 01H saddr 2 1 - (saddr) 01H A 1 1 - A 00H X 1 1 - X 00H B 1 1 - B 00H C 1 1 - C 00H !addr16 3 1 - (addr16) 00H ES:!addr16 4 2 - (ES,addr16) 00H saddr 2 1 - (saddr) 00H [HL+byte], X 3 1 - (HL+byte) X x x ES:[HL+byte], X 4 2 - (ES, HL+byte) X x x rp, #word 3 1 - rp word saddrp, #word 4 1 - (saddrp) word sfrp, #word transfer Notes 1. Clocks Clocks 4 1 - sfrp word AX, rp Note 3 1 1 - AX rp rp, AX Note 3 1 1 - rp AX AX, !addr16 3 1 4 AX (addr16) !addr16, AX 3 1 - (addr16) AX AX, ES:!addr16 4 2 5 AX (ES, addr16) ES:!addr16, AX 4 2 - (ES, addr16) AX AX, saddrp 2 1 - AX (saddrp) saddrp, AX 2 1 - (saddrp) AX AX, sfrp 2 1 - AX sfrp sfrp, AX 2 1 - sfrp AX Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except rp = AX Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 960 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (5/17) Instruction Mnemonic Operands Bytes Group 16-bit MOVW data Note 1 Note 2 Flag Z AX, [DE] 1 1 4 AX (DE) [DE], AX 1 1 - (DE) AX AX, ES:[DE] 2 2 5 AX (ES, DE) ES:[DE], AX 2 2 - (ES, DE) AX AX, [HL] 1 1 4 AX (HL) [HL], AX 1 1 - (HL) AX AX, ES:[HL] 2 2 5 AX (ES, HL) ES:[HL], AX 2 2 - (ES, HL) AX AX, [DE+byte] 2 1 4 AX (DE+byte) [DE+byte], AX 2 1 - (DE+byte) AX AX, ES:[DE+byte] 3 2 5 AX ((ES, DE) + byte) ES:[DE+byte], AX 3 2 - ((ES, DE) + byte) AX AX, [HL+byte] 2 1 4 AX (HL + byte) [HL+byte], AX 2 1 - (HL + byte) AX AX, ES:[HL+byte] 3 2 5 AX ((ES, HL) + byte) ES:[HL+byte], AX 3 2 - ((ES, HL) + byte) AX AX, [SP+byte] 2 1 - AX (SP + byte) [SP+byte], AX 2 1 - (SP + byte) AX AX, word[B] 3 1 4 AX (B + word) word[B], AX 3 1 - (B+ word) AX AX, ES:word[B] 4 2 5 AX ((ES, B) + word) ES:word[B], AX 4 2 - ((ES, B) + word) AX AX, word[C] 3 1 4 AX (C + word) word[C], AX 3 1 - (C + word) AX AX, ES:word[C] 4 2 5 AX ((ES, C) + word) ES:word[C], AX 4 2 - ((ES, C) + word) AX AX, word[BC] 3 1 4 AX (BC + word) word[BC], AX 3 1 - (BC + word) AX AX, ES:word[BC] 4 2 5 AX ((ES, BC) + word) ES:word[BC], AX 4 2 - ((ES, BC) + word) AX transfer Notes 1. Clocks Clocks AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 961 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Group 16-bit MOVW data Clocks Clocks Note 1 Note 2 3 1 4 BC (addr16) BC, ES:!addr16 4 2 5 BC (ES, addr16) DE, !addr16 3 1 4 DE (addr16) DE, ES:!addr16 4 2 5 DE (ES, addr16) HL, !addr16 3 1 4 HL (addr16) HL, ES:!addr16 4 2 5 HL (ES, addr16) BC, saddrp 2 1 - BC (saddrp) DE, saddrp 2 1 - DE (saddrp) HL, saddrp 2 1 - HL (saddrp) 1 1 - AX rp AX, rp ONEW AX 1 1 - AX 0001H BC 1 1 - BC 0001H AX 1 1 - AX 0000H BC 1 1 - BC 0000H A, #byte 2 1 - A, CY A + byte x x x saddr, #byte 3 2 - (saddr), CY (saddr)+byte x x x Note 4 2 1 - A, CY A + r x x x r, A 2 1 - r, CY r + A x x x A, !addr16 3 1 4 A, CY A + (addr16) x x x A, ES:!addr16 4 2 5 A, CY A + (ES, addr16) x x x A, saddr 2 1 - A, CY A + (saddr) x x x A, [HL] 1 1 4 A, CY A+ (HL) x x x A, ES:[HL] 2 2 5 A,CY A + (ES, HL) x x x A, [HL+byte] 2 1 4 A, CY A + (HL+byte) x x x A, ES:[HL+byte] 3 2 5 A,CY A + ((ES, HL)+byte) x x x A, [HL+B] 2 1 4 A, CY A + (HL+B) x x x A, ES:[HL+B] 3 2 5 A,CY A+((ES, HL)+B) x x x A, [HL+C] 2 1 4 A, CY A + (HL+C) x x x A, ES:[HL+C] 3 2 5 A,CY A + ((ES, HL) + C) x x x ADD operation A, r Notes 1. Note 3 AC CY XCHW CLRW 8-bit Z BC, !addr16 transfer Flag Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except rp = AX 4. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 962 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Group 8-bit ADDC operation Note 2 2 1 - A, CY A+byte+CY x x x saddr, #byte 3 2 - (saddr), CY (saddr) +byte+CY x x x Note 3 2 1 - A, CY A + r + CY x x x r, A 2 1 - r, CY r + A + CY x x x A, !addr16 3 1 4 A, CY A + (addr16)+CY x x x A, ES:!addr16 4 2 5 A, CY A + (ES, addr16)+CY x x x A, saddr 2 1 - A, CY A + (saddr)+CY x x x A, [HL] 1 1 4 A, CY A+ (HL) + CY x x x A, ES:[HL] 2 2 5 A,CY A+ (ES, HL) + CY x x x A, [HL+byte] 2 1 4 A, CY A+ (HL+byte) + CY x x x A, ES:[HL+byte] 3 2 5 A,CY A+ ((ES, HL)+byte) + CY x x x A, [HL+B] 2 1 4 A, CY A+ (HL+B) +CY x x x A, ES:[HL+B] 3 2 5 A,CY A+((ES, HL)+B)+CY x x x A, [HL+C] 2 1 4 A, CY A+ (HL+C)+CY x x x A, ES:[HL+C] 3 2 5 A,CY A+ ((ES, HL)+C)+CY x x x A, #byte 2 1 - A, CY A - byte x x x saddr, #byte 3 2 - (saddr), CY (saddr) - byte x x x Note 3 2 1 - A, CY A - r x x x r, A 2 1 - r, CY r - A x x x A, !addr16 3 1 4 A, CY A - (addr16) x x x A, ES:!addr16 4 2 5 A, CY A - (ES, addr16) x x x A, saddr 2 1 - A, CY A - (saddr) x x x A, [HL] 1 1 4 A, CY A - (HL) x x x A, ES:[HL] 2 2 5 A,CY A - (ES, HL) x x x A, [HL+byte] 2 1 4 A, CY A - (HL+byte) x x x A, ES:[HL+byte] 3 2 5 A,CY A - ((ES, HL)+byte) x x x A, [HL+B] 2 1 4 A, CY A - (HL+B) x x x A, ES:[HL+B] 3 2 5 A,CY A - ((ES, HL)+B) x x x A, [HL+C] 2 1 4 A, CY A - (HL+C) x x x A, ES:[HL+C] 3 2 5 A,CY A - ((ES, HL)+C) x x x A, #byte A, r Notes 1. Flag Note 1 A, rv SUB Clocks Clocks Z AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 963 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Group 8-bit SUBC operation Note 2 2 1 - A, CY A - byte - CY x x x saddr, #byte 3 2 - (saddr), CY (saddr) - byte - CY x x x Note 3 2 1 - A, CY A - r - CY x x x r, A 2 1 - r, CY r - A - CY x x x A, !addr16 3 1 4 A, CY A - (addr16) - CY x x x A, ES:!addr16 4 2 5 A, CY A - (ES, addr16) - CY x x x A, saddr 2 1 - A, CY A - (saddr) - CY x x x A, [HL] 1 1 4 A, CY A - (HL) - CY x x x A, ES:[HL] 2 2 5 A,CY A - (ES, HL) - CY x x x A, [HL+byte] 2 1 4 A, CY A - (HL+byte) - CY x x x A, ES:[HL+byte] 3 2 5 A,CY A - ((ES, HL)+byte) - CY x x x A, [HL+B] 2 1 4 A, CY A - (HL+B) - CY x x x A, ES:[HL+B] 3 2 5 A,CY A - ((ES, HL)+B) - CY x x x A, [HL+C] 2 1 4 A, CY A - (HL+C) - CY x x x A, ES:[HL+C] 3 2 5 A, CY A - ((ES:HL)+C) - CY x x x A, #byte 2 1 - A A byte x saddr, #byte 3 2 - (saddr) (saddr) byte x Note 3 2 1 - AAr x r, A 2 1 - RrA x A, !addr16 3 1 4 A A (addr16) x A, ES:!addr16 4 2 5 A A (ES:addr16) x A, saddr 2 1 - A A (saddr) x A, [HL] 1 1 4 A A (HL) x A, ES:[HL] 2 2 5 A A (ES:HL) x A, [HL+byte] 2 1 4 A A (HL+byte) x A, ES:[HL+byte] 3 2 5 A A ((ES:HL)+byte) x A, [HL+B] 2 1 4 A A (HL+B) x A, ES:[HL+B] 3 2 5 A A ((ES:HL)+B) x A, [HL+C] 2 1 4 A A (HL+C) x A, ES:[HL+C] 3 2 5 A A ((ES:HL)+C) x A, #byte A, r Notes 1. Flag Note 1 A, r AND Clocks Clocks Z AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 964 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Group 8-bit OR operation Note 2 2 1 - A Abyte x saddr, #byte 3 2 - (saddr) (saddr)byte x Note 3 2 1 - A Ar x r, A 2 1 - r rA x A, !addr16 3 1 4 A A(addr16) x A, ES:!addr16 4 2 5 A A(ES:addr16) x A, saddr 2 1 - A A(saddr) x A, [HL] 1 1 4 A A(H) x A, ES:[HL] 2 2 5 A A(ES:HL) x A, [HL+byte] 2 1 4 A A(HL+byte) x A, ES:[HL+byte] 3 2 5 A A((ES:HL)+byte) x A, [HL+B] 2 1 4 A A(HL+B) x A, ES:[HL+B] 3 2 5 A A((ES:HL)+B) x A, [HL+C] 2 1 4 A A(HL+C) x A, ES:[HL+C] 3 2 5 A A((ES:HL)+C) x A, #byte 2 1 - A Abyte x saddr, #byte 3 2 - (saddr) (saddr)byte x Note 3 2 1 - A Ar x r, A 2 1 - r rA x A, !addr16 3 1 4 A A(addr16) x A, ES:!addr16 4 2 5 A A(ES:addr16) x A, saddr 2 1 - A A(saddr) x A, [HL] 1 1 4 A A(HL) x A, ES:[HL] 2 2 5 A A(ES:HL) x A, [HL+byte] 2 1 4 A A(HL+byte) x A, ES:[HL+byte] 3 2 5 A A((ES:HL)+byte) x A, [HL+B] 2 1 4 A A(HL+B) x A, ES:[HL+B] 3 2 5 A A((ES:HL)+B) x A, [HL+C] 2 1 4 A A(HL+C) x A, ES:[HL+C] 3 2 5 A A((ES:HL)+C) x A, #byte A, r Notes 1. Flag Note 1 A, r XOR Clocks Clocks Z AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 965 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Group 8-bit CMP operation CMP0 CMPS Notes 1. Note 1 Note 2 Flag Z AC CY A, #byte 2 1 - A - byte x x x !addr16, #byte 4 1 4 (addr16) - byte x x x ES:!addr16, #byte 5 2 5 (ES:addr16) - byte x x x saddr, #byte 3 1 - (saddr) - byte x x x Note3 2 1 - A-r x x x r, A 2 1 - r-A x x x A, !addr16 3 1 4 A - (addr16) x x x A, ES:!addr16 4 2 5 A - (ES:addr16) x x x A, saddr 2 1 - A - (saddr) x x x A, [HL] 1 1 4 A - (HL) x x x A, ES:[HL] 2 2 5 A - (ES:HL) x x x A, [HL+byte] 2 1 4 A - (HL+byte) x x x A, ES:[HL+byte] 3 2 5 A - ((ES:HL)+byte) x x x A, [HL+B] 2 1 4 A - (HL+B) x x x A, ES:[HL+B] 3 2 5 A - ((ES:HL)+B) x x x A, [HL+C] 2 1 4 A - (HL+C) x x x A, ES:[HL+C] 3 2 5 A - ((ES:HL)+C) x x x A 1 1 - A - 00H x 0 0 X 1 1 - X - 00H x 0 0 B 1 1 - B - 00H x 0 0 C 1 1 - C - 00H x 0 0 !addr16 3 1 4 (addr16) - 00H x 0 0 ES:!addr16 4 2 5 (ES:addr16) - 00H x 0 0 saddr 2 1 - (saddr) - 00H x 0 0 X, [HL+byte] 3 1 4 X - (HL+byte) x x x X, ES:[HL+byte] 4 2 5 X - ((ES:HL)+byte) x x x A, r <R> Clocks Clocks Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 966 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Group 16-bit ADDW operation SUBW CMPW Multiply Notes 1. MULU Clocks Clocks Note 1 Note 2 Flag Z AC CY AX, #word 3 1 - AX, CY AX+word x x x AX, AX 1 1 - AX, CY AX+AX x x x AX, BC 1 1 - AX, CY AX+BC x x x AX, DE 1 1 - AX, CY AX+DE x x x AX, HL 1 1 - AX, CY AX+HL x x x AX, !addr16 3 1 4 AX, CY AX+(addr16) x x x AX, ES:!addr16 4 2 5 AX, CY AX+(ES:addr16) x x x AX, saddrp 2 1 - AX, CY AX+(saddrp) x x x AX, [HL+byte] 3 1 4 AX, CY AX+(HL+byte) x x x AX, ES: [HL+byte] 4 2 5 AX, CY AX+((ES:HL)+byte) x x x AX, #word 3 1 - AX, CY AX - word x x x AX, BC 1 1 - AX, CY AX - BC x x x AX, DE 1 1 - AX, CY AX - DE x x x AX, HL 1 1 - AX, CY AX - HL x x x AX, !addr16 3 1 4 AX, CY AX - (addr16) x x x AX, ES:!addr16 4 2 5 AX, CY AX - (ES:addr16) x x x AX, saddrp 2 1 - AX, CY AX - (saddrp) x x x AX, [HL+byte] 3 1 4 AX, CY AX - (HL+byte) x x x AX, ES: [HL+byte] 4 2 5 AX, CY AX - ((ES:HL)+byte) x x x AX, #word 3 1 - AX - word x x x AX, BC 1 1 - AX - BC x x x AX, DE 1 1 - AX - DE x x x AX, HL 1 1 - AX - HL x x x AX, !addr16 3 1 4 AX - (addr16) x x x AX, ES:!addr16 4 2 5 AX - (ES:addr16) x x x AX, saddrp 2 1 - AX - (saddrp) x x x AX, [HL+byte] 3 1 4 AX - (HL+byte) x x x AX, ES: [HL+byte] 4 2 5 AX - ((ES:HL)+byte) x x x X 1 1 - AX AxX Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 967 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Group Increment/ Note 2 Z AC CY 1 1 - r r+1 x x !addr16 3 2 - (addr16) (addr16)+1 x x ES:!addr16 4 3 - (ES, addr16) (ES, addr16)+1 x x saddr 2 2 - (saddr) (saddr)+1 x x [HL+byte] 3 2 - (HL+byte) (HL+byte)+1 x x ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte)+1 x x r 1 1 - rr-1 x x !addr16 3 2 - (addr16) (addr16) - 1 x x ES:!addr16 4 3 - (ES, addr16) (ES, addr16) - 1 x x saddr 2 2 - (saddr) (saddr) - 1 x x [HL+byte] 3 2 - (HL+byte) (HL+byte) - 1 x x ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte) - 1 x x rp 1 1 - rp rp+1 !addr16 3 2 - (addr16) (addr16)+1 ES:!addr16 4 3 - (ES, addr16) (ES, addr16)+1 saddrp 2 2 - (saddrp) (saddrp)+1 [HL+byte] 3 2 - (HL+byte) (HL+byte)+1 ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte)+1 rp 1 1 - rp rp - 1 !addr16 3 2 - (addr16) (addr16) - 1 ES:!addr16 4 3 - (ES, addr16) (ES, addr16) - 1 saddrp 2 2 - (saddrp) (saddrp) - 1 [HL+byte] 3 2 - (HL+byte) (HL+byte) - 1 ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte) - 1 SHR A, cnt 2 1 - (CY A0, Am-1 Am, A7 0) xcnt x SHRW AX, cnt 2 1 - (CY AX0, AXm-1 AXm, AX15 0) xcnt x SHL A, cnt 2 1 - (CY A7, Am Am-1, A0 0) xcnt x B, cnt 2 1 - (CY B7, Bm Bm-1, B0 0) xcnt x C, cnt 2 1 - (CY C7, Cm Cm-1, C0 0) xcnt x AX, cnt 2 1 - (CY AX15, AXm AXm-1, AX0 0) xcnt x BC, cnt 2 1 - (CY BC15, BCm BCm-1, BC0 0) xcnt x SAR A, cnt 2 1 - (CY A0, Am-1 Am, A7 A7) xcnt x SARW AX, cnt 2 1 - (CY AX0, AXm-1 AXm, AX15 AX15) xcnt x DEC INCW DECW SHLW Notes 1. Note 1 Flag r INC decrement Shift Clocks Clocks Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. Remarks 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. 2. cnt indicates the bit shift count. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 968 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Group Rotate Bit Note 1 Note 2 Flag Z AC CY ROR A, 1 2 1 - (CY, A7 A0, Am-1 Am)x1 x ROL A, 1 2 1 - (CY, A0 A7, Am+1 Am)x1 x RORC A, 1 2 1 - (CY A0, A7 CY, Am-1 Am)x1 x ROLC A, 1 2 1 - (CY A7, A0 CY, Am+1 Am)x1 x ROLWC AX,1 2 1 - (CY AX15, AX0 CY, AXm+1 AXm) x1 x BC,1 2 1 - (CY BC15, BC0 CY, BCm+1 BCm) x1 x CY, A.bit 2 1 - CY A.bit x A.bit, CY 2 1 - A.bit CY CY, PSW.bit 3 1 - CY PSW.bit PSW.bit, CY 3 4 - PSW.bit CY CY, saddr.bit 3 1 - CY (saddr).bit saddr.bit, CY 3 2 - (saddr).bit CY CY, sfr.bit 3 1 - CY sfr.bit sfr.bit, CY 3 2 - sfr.bit CY CY,[HL].bit 2 1 4 CY (HL).bit [HL].bit, CY 2 2 - (HL).bit CY CY, ES:[HL].bit 3 2 5 CY (ES, HL).bit ES:[HL].bit, CY 3 3 - (ES, HL).bit CY CY, A.bit 2 1 - CY CY A.bit x CY, PSW.bit 3 1 - CY CY PSW.bit x CY, saddr.bit 3 1 - CY CY (saddr).bit x CY, sfr.bit 3 1 - CY CY sfr.bit x CY,[HL].bit 2 1 4 CY CY (HL).bit x CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit x CY, A.bit 2 1 - CY CY A.bit x CY, PSW.bit 3 1 - CYX CY PSW.bit x CY, saddr.bit 3 1 - CY CY (saddr).bit x CY, sfr.bit 3 1 - CY CY sfr.bit x CY, [HL].bit 2 1 4 CY CY (HL).bit x CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit x MOV1 manipulate AND1 OR1 Notes 1. Clocks Clocks x x x x x x x Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 969 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Group Bit Note 1 Note 2 Flag Z AC CY CY, A.bit 2 1 - CY CY A.bit x CY, PSW.bit 3 1 - CY CY PSW.bit x CY, saddr.bit 3 1 - CY CY (saddr).bit x CY, sfr.bit 3 1 - CY CY sfr.bit x CY, [HL].bit 2 1 4 CY CY (HL).bit x CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit x A.bit 2 1 - A.bit 1 PSW.bit 3 4 - PSW.bit 1 !addr16.bit 4 2 - (addr16).bit 1 ES:!addr16.bit 5 3 - (ES, addr16).bit 1 saddr.bit 3 2 - (saddr).bit 1 sfr.bit 3 2 - sfr.bit 1 [HL].bit 2 2 - (HL).bit 1 ES:[HL].bit 3 3 - (ES, HL).bit 1 A.bit 2 1 - A.bit 0 PSW.bit 3 4 - PSW.bit 0 !addr16.bit 4 2 - (addr16).bit 0 ES:!addr16.bit 5 3 - (ES, addr16).bit 0 saddr.bit 3 2 - (saddr.bit) 0 sfr.bit 3 2 - sfr.bit 0 [HL].bit 2 2 - (HL).bit 0 ES:[HL].bit 3 3 - (ES, HL).bit 0 SET1 CY 2 1 - CY 1 1 CLR1 CY 2 1 - CY 0 0 NOT1 CY 2 1 - CY CY x XOR1 manipulate SET1 CLR1 Notes 1. Clocks Clocks x x x x x x Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 970 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Group CALL Call/ rp 2 Clocks Clocks Note 1 Note 2 3 - Flag Z AC CY (SP - 2) (PC+2)S, (SP - 3) (PC+2)H, (SP - 4) (PC+2)L, PC CS, rp, return SP SP - 4 $!addr20 3 3 - (SP - 2) (PC+3)S, (SP - 3) (PC+3)H, (SP - 4) (PC+3)L, PC PC+3+jdisp16, SP SP - 4 !addr16 3 3 - (SP - 2) (PC+3)S, (SP - 3) (PC+3)H, (SP - 4) (PC+3)L, PC 0000, addr16, SP SP - 4 !!addr20 4 3 - (SP - 2) (PC+4)S, (SP - 3) (PC+4)H, (SP - 4) (PC+4)L, PC addr20, SP SP - 4 CALLT [addr5] 2 5 - (SP - 2) (PC+2)S , (SP - 3) (PC+2)H, (SP - 4) (PC+2)L , PCS 0000, PCH (0000, addr5+1), PCL (0000, addr5), SP SP - 4 BRK - 2 5 - (SP - 1) PSW, (SP - 2) (PC+2)S, (SP - 3) (PC+2)H, (SP - 4) (PC+2)L, PCS 0000, PCH (0007FH), PCL (0007EH), SP SP - 4, IE 0 RET - 1 6 - PCL (SP), PCH (SP+1), PCS (SP+2), SP SP+4 RETI - 2 6 - PCL (SP), PCH (SP+1), R R R R R R PCS (SP+2), PSW (SP+3), SP SP+4 RETB - 2 6 - PCL (SP), PCH (SP+1), PCS (SP+2), PSW (SP+3), SP SP+4 Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 971 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (16/17) Instruction Group Stack Mnemon Operands Bytes ic PUSH PSW 2 Clocks Clocks Note 1 Note 2 1 - manipulate Flag Z AC CY (SP - 1) PSW, (SP - 2) 00H, SP SP-2 rp 1 1 - (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 2 3 - PSW (SP+1), SP SP + 2 rp 1 1 - rpL (SP), rpH (SP+1), SP SP + 2 SP, #word 4 1 - SP word SP, AX 2 1 - SP AX AX, SP 2 1 - AX SP HL, SP 3 1 - HL SP BC, SP 3 1 - BC SP DE, SP 3 1 - DE SP ADDW SP, #byte 2 1 - SP SP + byte SUBW SP, #byte 2 1 - SP SP - byte BR AX 2 3 - PC CS, AX $addr20 2 3 - PC PC + 2 + jdisp8 $!addr20 3 3 - PC PC + 3 + jdisp16 !addr16 3 3 - PC 0000, addr16 !!addr20 4 3 POP MOVW Unconditio nal branch Conditional BC branch BNC BZ BNZ BH BNH BT - PC addr20 - PC PC + 2 + jdisp8 if CY = 1 $addr20 2 2/4 Note3 $addr20 2 2/4 Note3 - PC PC + 2 + jdisp8 if CY = 0 2/4 Note3 - PC PC + 2 + jdisp8 if Z = 1 2/4 Note3 - PC PC + 2 + jdisp8 if Z = 0 2/4 Note3 - PC PC + 3 + jdisp8 if (ZCY)=0 2/4 Note3 - PC PC + 3 + jdisp8 if (ZCY)=1 3/5 Note3 - PC PC + 4 + jdisp8 if (saddr).bit = 1 3/5 Note3 - PC PC + 4 + jdisp8 if sfr.bit = 1 - PC PC + 3 + jdisp8 if A.bit = 1 $addr20 $addr20 $addr20 $addr20 saddr.bit, $addr20 sfr.bit, $addr20 2 2 3 3 4 4 A.bit, $addr20 3 3/5 Note3 PSW.bit, $addr20 4 3/5 Note3 - PC PC + 4 + jdisp8 if PSW.bit = 1 3/5 Note3 6/7 PC PC + 3 + jdisp8 if (HL).bit = 1 4/6 Note3 7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 1 [HL].bit, $addr20 ES:[HL].bit, 3 4 R R R $addr20 Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. This indicates the number of clocks "when condition is not met/when condition is met". Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 972 RL78/G13 CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Group Condition Note 1 BF saddr.bit, $addr20 al branch sfr.bit, $addr20 A.bit, $addr20 PSW.bit, $addr20 [HL].bit, $addr20 ES:[HL].bit, Clocks Clocks Note 2 Z 3/5 Note3 - PC PC + 4 + jdisp8 if (saddr).bit = 0 3/5 Note3 - PC PC + 4 + jdisp8 if sfr.bit = 0 3/5 Note3 - PC PC + 3 + jdisp8 if A.bit = 0 3/5 Note3 - PC PC + 4 + jdisp8 if PSW.bit = 0 3/5 Note3 6/7 PC PC + 3 + jdisp8 if (HL).bit = 0 4 4/6 Note3 7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 0 4 3/5 Note3 - 3/5 Note3 3/5 Note3 3/5 Note3 3/5 Note3 4/6 Note3 4 4 3 4 3 Flag AC CY $addr20 BTCLR saddr.bit, $addr20 PC PC + 4 + jdisp8 if (saddr).bit = 1 then reset (saddr).bit sfr.bit, $addr20 4 - PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit A.bit, $addr20 3 - PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PSW.bit, $addr20 4 - PC PC + 4 + jdisp8 if PSW.bit = 1 x x x then reset PSW.bit [HL].bit, $addr20 3 - PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit ES:[HL].bit, 4 - $addr20 Conditional skip CPU Notes 1. then reset (ES, HL).bit SKC - 2 1 - Next instruction skip if CY = 1 SKNC - 2 1 - Next instruction skip if CY = 0 SKZ - 2 1 - Next instruction skip if Z = 1 SKNZ - 2 1 - Next instruction skip if Z = 0 SKH - 2 1 - Next instruction skip if (ZCY)=0 SKNH - 2 1 - Next instruction skip if (ZCY)=1 2 1 - RBS[1:0] n SEL control PC PC + 4 + jdisp8 if (ES, HL).bit = 1 Note4 RBn NOP - 1 1 - No Operation EI - 3 4 - IE 1 (Enable Interrupt) DI - 3 4 - IE 0 (Disable Interrupt) HALT - 2 3 - Set HALT Mode STOP - 2 3 - Set STOP Mode Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. This indicates the number of clocks "when condition is not met/when condition is met". Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 973 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS CHAPTER 29 ELECTRICAL SPECIFICATIONS Cautions 1. The RL78/G13 microcontorollers have an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. <R> 2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS. <R> 3. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions Mounted According to Product. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 974 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) (1/2) Parameter Supply voltage Symbols Ratings Unit VDD -0.5 to +6.5 V EVDD0, EVDD1 EVDD0 = EVDD1 -0.5 to +6.5 V VSS -0.5 to +0.3 V -0.5 to +0.3 V EVSS0, EVSS1 REGC pin input voltage VIREGC Conditions EVSS0 = EVSS1 -0.3 to +2.8 REGC V and -0.3 to VDD +0.3 Input voltage VI1 Note 1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, -0.3 to EVDD0 +0.3 P50 to P57, P64 to P67, P70 to P77, P80 to P87, and -0.3 to VDD +0.3 V Note 2 P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VI2 VI3 -0.3 to +6.5 P60 to P63 (N-ch open-drain) -0.3 to VDD +0.3 P20 to P27, P121 to P124, P137, P150 to P156, V Note 2 V EXCLK, EXCLKS, RESET Output voltage VO1 -0.3 to EVDD0 +0.3 P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, and -0.3 to VDD +0.3 V Note 2 P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 Analog input voltage VO2 P20 to P27, P150 to P156 VAI1 ANI16 to ANI26 <R> -0.3 to VDD +0.3 Note 2 -0.3 to EVDD0 +0.3 and -0.3 to AVREF(+) +0.3 VAI2 V Notes 2, 3 -0.3 to VDD +0.3 ANI0 to ANI14 and -0.3 to AVREF(+) +0.3 <R> Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). V V Notes 2, 3 This value regulates the absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it. 2. <R> Must be 6.5 V or lower. 3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. <R> 2. AVREF (+) : + side reference voltage of the A/D converter. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 975 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) (2/2) Parameter Output current, high Symbols IOH1 Conditions Per pin P00 to P07, P10 to P17, Ratings Unit -40 mA -70 mA -100 mA P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 Total of all pins P00 to P04, P07, P32 to P37, -170 mA P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 IOH2 Per pin P20 to P27, P150 to P156 Total of all pins Output current, low IOL1 Per pin P00 to P07, P10 to P17, -0.5 mA -2 mA 40 mA 70 mA 100 mA 1 mA 5 mA -40 to +85 C -65 to +150 C P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 Total of all pins P00 to P04, P07, P32 to P37, 170 mA P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 P05, P06, P10 to P17, P30, P31, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 IOL2 Per pin P20 to P27, P150 to P156 Total of all pins Operating ambient TA temperature Storage temperature In normal operation mode In flash memory programming mode Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 976 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS <R> 29.2 Oscillator Characteristics 29.2.1 X1, XT1 oscillator characteristics (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Resonator Recommended Conditions MIN. TYP. MAX. Unit Circuit X1 clock Ceramic oscillation resonator/ Note frequency (fX) crystal resonator VSS X1 X2 Rd 1.0 20.0 MHz 1.8 V VDD < 2.7 V 1.0 8.0 MHz 1.6 V VDD < 1.8 V 1.0 4.0 MHz 35 kHz C2 C1 XT1 clock 2.7 V VDD 5.5 V Crystal resonator 32 VSS XT2 oscillation Note frequency (fX) 32.768 XT1 Rd C4 C3 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the X1 oscillator, XT1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. 3. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction due to noise than the X1 oscillator. Particular care is therefore required with the wiring method when the XT1 clock is used. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 977 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.2.2 On-chip oscillator characteristics (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Oscillators Parameters High-speed on-chip oscillator clock frequency Conditions MAX. Unit 1 32 MHz 1.8 VVDD5.5 V -1 +1 % 1.6 VVDD<1.8 V -5 +5 % 1.8 VVDD5.5 V -1.5 +1.5 % 1.6 VVDD<1.8 V -5.5 fIH MIN. TYP. Note 1 -20 to +85 C High-speed on-chip oscillator clock frequency accuracy Note 2 -40 to -20 C Low-speed on-chip oscillator +5.5 15 fIL % kHz clock frequency Low-speed on-chip oscillator -15 +15 % clock frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. <R> 2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution time. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 978 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.3 DC Characteristics 29.3.1 Pin characteristics (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Output current, Note 1 high IOH1 IOH2 Notes 1. Conditions MIN. TYP. MAX. Unit -10.0 mA Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 1.6 V EVDD0 5.5 V Total of P00 to P04, P07, P32 to P37, P40 to P47, P102 to P106, P120, P125 to P127, P130, P140 to P145 Note 3 ) (When duty = 70% 4.0 V EVDD0 5.5 V -55.0 2.7 V EVDD0 < 4.0 V -10.0 mA 1.8 V EVDD0 < 2.7 V -5.0 mA 1.6 V EVDD0 < 1.8 V -2.5 mA Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 Note 3 ) (When duty = 70% 4.0 V EVDD0 5.5 V -80.0 mA 2.7 V EVDD0 < 4.0 V -19.0 mA 1.8 V EVDD0 < 2.7 V -10.0 mA 1.6 V EVDD0 < 1.8 V -5.0 mA Total of all pins Note 3 (When duty = 70% ) 1.6 V EVDD0 5.5 V -135.0 mA Per pin for P20 to P27, P150 to P156 1.6 V VDD 5.5 V Total of all pins Note 3 ) (When duty = 70% 1.6 V VDD 5.5 V Note 2 mA Note 4 -0.1 Note 2 -1.5 mA mA Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to an output pin. 2. 3. However, do not exceed the total current value. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 50% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(50 x 0.01) = -14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. <R> 4. The applied current for the products for industrial application (R5F100xxDxx, R5F101xxDxx) is -100 mA. Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 979 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Output current, Note 1 low IOL1 Conditions MIN. TYP. Note 2 mA Per pin for P60 to P63 15.0 Note 2 mA 70.0 mA 15.0 mA 9.0 mA 4.5 mA 4.0 V EVDD0 5.5 V 80.0 mA 2.7 V EVDD0 < 4.0 V 35.0 mA 1.8 V EVDD0 < 2.7 V 20.0 mA 1.6 V EVDD0 < 1.8 V 10.0 mA Total of all pins Note 3 (When duty = 70% ) 150.0 mA Per pin for P20 to P27, P150 to P156 0.4 Total of P05, P06, P10 to P17, P30, P31, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100, P101, P110 to P117, P146, P147 Note 3 ) (When duty = 70% Total of all pins Note 3 ) (When duty = 70% Notes 1. Unit 20.0 Total of P00 to P04, P07, P32 to P37, 4.0 V EVDD0 5.5 V P40 to P47, P102 to P106, P120, 2.7 V EVDD0 < 4.0 V P125 to P127, P130, P140 to P145 Note 3 1.8 V EVDD0 < 2.7 V ) (When duty = 70% 1.6 V EVDD0 < 1.8 V IOL2 MAX. Per pin for P00 to P07, P10 to P17, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P130, P140 to P147 1.6 V VDD 5.5 V Note 2 5.0 mA mA Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0, EVSS1 and VSS pin. 2. However, do not exceed the total current value. 3. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 50% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(50 x 0.01) = 14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 980 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Input voltage, Symbol VIH1 Conditions MIN. P00 to P07, P10 to P17, P30 to P37, Normal input buffer TYP. MAX. Unit 0.8EVDD0 EVDD0 V 2.2 EVDD0 V 2.0 EVDD0 V 1.5 EVDD0 V 0.7VDD VDD V 0.7EVDD0 6.0 V 0.8VDD VDD V 0 0.2EVDD0 V 0 0.8 V 0 0.5 V 0 0.32 V P40 to P47, P50 to P57, P64 to P67, high P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VIH2 P01, P03, P04, P10, P11, TTL input buffer P13 to P17, P43, P44, P53 to P55, 4.0 V EVDD0 5.5 V P80, P81, P142, P143 TTL input buffer 3.3 V EVDD0 < 4.0 V TTL input buffer 1.6 V EVDD0 < 3.3 V Input voltage, VIH3 P20 to P27, P150 to P156 VIH4 P60 to P63 VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET VIL1 P00 to P07, P10 to P17, P30 to P37, Normal input buffer P40 to P47, P50 to P57, P64 to P67, low P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 VIL2 P01, P03, P04, P10, P11, TTL input buffer P13 to P17, P43, P44, P53 to P55, 4.0 V EVDD0 5.5 V P80, P81, P142, P143 TTL input buffer 3.3 V EVDD0 < 4.0 V TTL input buffer 1.6 V EVDD0 < 3.3 V VIL3 P20 to P27, P150 to P156 0 0.3VDD V VIL4 P60 to P63 0 0.3EVDD0 V VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2VDD V Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 981 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Symbol Output voltage, VOH1 Conditions MIN. MAX. P00 to P07, P10 to P17, P30 to P37, 4.0 V EVDD0 5.5 V, EVDD0 - P40 to P47, P50 to P57, P64 to P67, IOH1 = -10.0 mA high TYP. V 1.5 P70 to P77, P80 to P87, P90 to P97, 4.0 V EVDD0 5.5 V, EVDD0 - P100 to P106, P110 to P117, P120, IOH1 = -3.0 mA 0.7 P125 to P127, P130, P140 to P147 2.7 V EVDD0 5.5 V, EVDD0 - IOH1 = -2.0 mA V V 0.6 1.8 V EVDD0 5.5 V, EVDD0 - IOH1 = -1.5 mA V 0.5 1.6 V EVDD0 < 1.8 V, EVDD0 - IOH1 = -1.0 mA VOH2 P20 to P27, P150 to P156 1.6 V VDD 5.5 V, Unit V 0.5 VDD - 0.5 V IOH2 = -100 A Output voltage, VOL1 P00 to P07, P10 to P17, P30 to P37, 4.0 V EVDD0 5.5 V, 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V 0.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.4 V 0.4 V P40 to P47, P50 to P57, P64 to P67, IOL1 = 20 mA low P70 to P77, P80 to P87, P90 to P97, 4.0 V EVDD0 5.5 V, P100 to P106, P110 to P117, P120, IOL1 = 8.5 mA P125 to P127, P130, P140 to P147 4.0 V EVDD0 5.5 V, IOL1 = 3.0 mA 2.7 V EVDD0 5.5 V, IOL1 = 1.5 mA 1.8 V EVDD0 5.5 V, IOL1 = 0.6 mA 1.6 V EVDD0 < 5.5 V, IOL1 = 0.3 mA VOL2 P20 to P27, P150 to P156 1.6 V VDD 5.5 V, IOL2 = 400 A VOL3 P60 to P63 4.0 V EVDD0 5.5 V, IOL3 = 15.0 mA 4.0 V EVDD0 5.5 V, IOL3 = 5.0 mA 2.7 V EVDD0 5.5 V, IOL3 = 3.0 mA 1.8 V EVDD0 5.5 V, IOL3 = 2.0 mA 1.6 V EVDD0 < 5.5 V, IOL3 = 1.0 mA Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and P142 to P144 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 982 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Input leakage Symbol ILIH1 Conditions P00 to P07, P10 to P17, MIN. TYP. MAX. Unit VI = EVDD0 1 A VI = VDD 1 A 1 A 10 A VI = EVSS0 -1 A VI = VSS -1 A -1 A -10 A 100 k P30 to P37, P40 to P47, current, high P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 ILIH2 P20 to P27, P137, P150 to P156, RESET ILIH3 P121 to P124 VI = VDD In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator connection Input leakage ILIL1 P00 to P07, P10 to P17, P30 to P37, P40 to P47, current, low P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 ILIL2 P20 to P27, P137, P150 to P156, RESET ILIL3 P121 to P124 VI = VSS In input port or (X1, X2, XT1, XT2, EXCLK, external clock EXCLKS) input In resonator connection On-chip pll-up RU P00 to P07, P10 to P17, VI = EVSS0, In input port 10 20 P30 to P37, P40 to P47, resistance P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P106, P110 to P117, P120, P125 to P127, P140 to P147 Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 983 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.3.2 Supply current characteristics (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply current IDD1 Note 1 Conditions Operating mode HS (highspeed main) Note 5 mode fIH = 32 MHz Note 3 MIN. (1/2) TYP. Basic operation VDD = 5.0 V VDD = 3.0 V 2.1 Normal operation VDD = 5.0 V 4.6 MAX. 2.1 Unit mA mA 7.0 mA VDD = 3.0 V 4.6 7.0 mA fIH = 24 MHz Note 3 Normal operation VDD = 5.0 V 3.7 5.5 mA VDD = 3.0 V 3.7 5.5 mA fIH = 16 MHz Note 3 Normal operation VDD = 5.0 V 2.7 4.0 mA VDD = 3.0 V 2.7 4.0 mA Normal operation VDD = 3.0 V 1.2 1.8 mA VDD = 2.0 V 1.2 1.8 mA Normal operation VDD = 3.0 V 1.2 1.7 mA VDD = 2.0 V 1.2 1.7 mA Normal operation Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 mA Note 2 Normal operation Square wave input 3.0 4.6 mA Resonator connection 3.2 4.8 mA Note 2 Normal operation Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 mA Normal operation Square wave input 1.9 2.7 mA Resonator connection 1.9 2.7 mA Normal operation Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 mA Normal operation Square wave input 1.1 1.7 mA Resonator connection 1.1 1.7 mA Normal operation Square wave input 4.1 A Resonator connection 4.2 A Normal operation Square wave input 4.1 4.9 A Resonator connection 4.2 5.0 A Normal operation Square wave input 4.2 5.5 A Resonator connection 4.3 5.6 A Normal operation Square wave input 4.2 6.3 A Resonator connection 4.3 6.4 A Normal operation Square wave input 4.8 7.7 A Resonator connection 4.9 7.8 A LS (lowspeed main) Note 5 mode fIH = 8 MHz LV (lowvoltage main) mode fIH = 4 MHz Note 3 Note 3 Note 5 HS (highspeed main) Note 5 mode Note 2 fMX = 20 MHz , VDD = 5.0 V fMX = 20 MHz , VDD = 3.0 V fMX = 10 MHz , VDD = 5.0 V Note 2 fMX = 10 MHz , VDD = 3.0 V LS (lowspeed main) Note 5 mode Note 2 fMX = 8 MHz , VDD = 3.0 V Note 2 fMX = 8 MHz , VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = -40C fSUB = 32.768 kHz Note 4 TA = +25C fSUB = 32.768 kHz Note 4 TA = +50C fSUB = 32.768 kHz Note 4 TA = +70C fSUB = 32.768 kHz Note 4 TA = +85C (Notes and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 984 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). <R> 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 985 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions Supply IDD2 HALT current Note 2 mode Note 1 HS (highspeed main) Note 7 mode LS (lowspeed main) Note 7 mode LV (lowvoltage main) mode MIN. fIH = 32 MHz Note 4 fIH = 24 MHz Note 4 fIH = 16 MHz Note 4 fIH = 8 MHz Note 4 fIH = 4 MHz Note 4 (2/2) TYP. MAX. Unit VDD = 5.0 V 0.54 1.63 mA VDD = 3.0 V 0.54 1.63 mA VDD = 5.0 V 0.44 1.28 mA VDD = 3.0 V 0.44 1.28 mA VDD = 5.0 V 0.40 1.00 mA VDD = 3.0 V 0.40 1.00 mA VDD = 3.0 V 260 530 A VDD = 2.0 V 260 530 A VDD = 3.0 V 420 640 A VDD = 2.0 V 420 640 A Square wave input 0.28 1.00 mA Resonator connection 0.45 1.17 mA Square wave input 0.28 1.00 mA Resonator connection 0.45 1.17 mA Square wave input 0.19 0.60 mA Resonator connection 0.26 0.67 mA Square wave input 0.19 0.60 mA Resonator connection 0.26 0.67 mA Square wave input 95 330 A Resonator connection 145 380 A Square wave input 95 330 A 380 A Note 7 HS (highspeed main) Note 7 mode Note 3 fMX = 20 MHz , VDD = 5.0 V Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 fMX = 10 MHz , VDD = 5.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V Note 3 LS (low- fMX = 8 MHz speed main) VDD = 3.0 V mode , Note 7 Note 3 fMX = 8 MHz , VDD = 2.0 V Resonator connection 145 Note 5 Square wave input 0.25 Resonator connection 0.44 fSUB = 32.768 kHz Note 5 Square wave input 0.30 0.57 A TA = +25C Resonator connection 0.49 0.76 A fSUB = 32.768 kHz Square wave input 0.33 1.17 A TA = +50C Resonator connection 0.52 1.36 A fSUB = 32.768 kHz Square wave input 0.36 1.97 A TA = +70C Resonator connection 0.55 2.16 A fSUB = 32.768 kHz Square wave input 0.97 3.37 A TA = +85C Resonator connection 1.16 3.56 A Subsystem fSUB = 32.768 kHz clock TA = -40C operation Note 5 Note 5 Note 5 Note 6 IDD3 STOP mode A A A TA = -40C 0.18 TA = +25C 0.23 0.50 A TA = +50C 0.26 1.10 A TA = +70C 0.29 1.90 A TA = +85C 0.90 3.30 A Note 8 (Notes and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 986 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When highspeed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. <R> 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD < 2.4 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz <R> 8. If operation of the subsystem clock when STOP mode, same as when HALT mode of subsystem clock operation. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25C R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 987 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply current IDD1 Note 1 Conditions Operating mode HS (highspeed main) Note 5 mode fIH = 32 MHz Note 3 MIN. (1/2) TYP. Basic operation VDD = 5.0 V VDD = 3.0 V 2.3 Normal operation VDD = 5.0 V 5.2 MAX. 2.3 Unit mA mA 8.5 mA VDD = 3.0 V 5.2 8.5 mA fIH = 24 MHz Note 3 Normal operation VDD = 5.0 V 4.1 6.6 mA VDD = 3.0 V 4.1 6.6 mA fIH = 16 MHz Note 3 Normal operation VDD = 5.0 V 3.0 4.7 mA VDD = 3.0 V 3.0 4.7 mA Normal operation VDD = 3.0 V 1.3 2.1 mA VDD = 2.0 V 1.3 2.1 mA Normal operation VDD = 3.0 V 1.3 1.8 mA VDD = 2.0 V 1.3 1.8 mA Normal operation Square wave input 3.4 5.5 mA Resonator connection 3.6 5.7 mA Note 2 Normal operation Square wave input 3.4 5.5 mA Resonator connection 3.6 5.7 mA Note 2 Normal operation Square wave input 2.1 3.2 mA Resonator connection 2.1 3.2 mA Normal operation Square wave input 2.1 3.2 mA Resonator connection 2.1 3.2 mA Normal operation Square wave input 1.2 2.0 mA Resonator connection 1.2 2.0 mA Normal operation Square wave input 1.2 2.0 mA Resonator connection 1.2 2.0 mA Normal operation Square wave input 4.8 A Resonator connection 4.9 A Normal operation Square wave input 4.9 5.9 A Resonator connection 5.0 6.0 A Normal operation Square wave input 4.9 7.6 A Resonator connection 5.0 7.7 A Normal operation Square wave input 5.2 9.3 A Resonator connection 5.3 9.4 A Normal operation Square wave input 6.1 13.3 A Resonator connection 6.2 13.4 A LS (lowspeed main) Note 5 mode fIH = 8 MHz LV (lowvoltage main) mode fIH = 4 MHz Note 3 Note 3 Note 5 HS (highspeed main) Note 5 mode Note 2 fMX = 20 MHz , VDD = 5.0 V fMX = 20 MHz , VDD = 3.0 V fMX = 10 MHz , VDD = 5.0 V Note 2 fMX = 10 MHz , VDD = 3.0 V LS (lowspeed main) Note 5 mode Note 2 fMX = 8 MHz , VDD = 3.0 V Note 2 fMX = 8 MHz , VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = -40C fSUB = 32.768 kHz Note 4 TA = +25C fSUB = 32.768 kHz Note 4 TA = +50C fSUB = 32.768 kHz Note 4 TA = +70C fSUB = 32.768 kHz Note 4 TA = +85C (Notes and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 988 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). <R> 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 989 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (2) Flash ROM: 96 to 256 KB of 30- to 100-pin products (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply current IDD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) Note 7 mode TYP. MAX. Unit fIH = 32 MHz Note 4 VDD = 5.0 V 0.62 1.86 mA VDD = 3.0 V 0.62 1.86 mA fIH = 24 MHz Note 4 VDD = 5.0 V 0.50 1.45 mA VDD = 3.0 V 0.50 1.45 mA fIH = 16 MHz Note 4 VDD = 5.0 V 0.44 1.11 mA LS (lowspeed main) Note 7 mode fIH = 8 MHz LV (lowvoltage main) mode fIH = 4 MHz MIN. (2/2) Note 4 Note 4 VDD = 3.0 V 0.44 1.11 mA VDD = 3.0 V 290 620 A VDD = 2.0 V 290 620 A VDD = 3.0 V 440 680 A VDD = 2.0 V 440 680 A Note 7 HS (highspeed main) Note 7 mode Note 3 fMX = 20 MHz , VDD = 5.0 V Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 fMX = 10 MHz , VDD = 5.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V LS (lowspeed main) Note 7 mode Note 3 fMX = 8 MHz , VDD = 3.0 V Note 3 fMX = 8 MHz , VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz Note 5 TA = -40C fSUB = 32.768 kHz Note 5 TA = +25C fSUB = 32.768 kHz Note 5 TA = +50C fSUB = 32.768 kHz Note 5 TA = +70C fSUB = 32.768 kHz TA = +85C Note 6 IDD3 STOP Note 8 mode Note 5 Square wave input 0.31 1.08 mA Resonator connection 0.48 1.28 mA Square wave input 0.31 1.08 mA Resonator connection 0.48 1.28 mA Square wave input 0.21 0.63 mA Resonator connection 0.28 0.71 mA Square wave input 0.21 0.63 mA Resonator connection 0.28 0.71 mA Square wave input 110 360 A Resonator connection 160 420 A Square wave input 110 360 A Resonator connection 160 420 A Square wave input 0.28 A Resonator connection 0.47 A Square wave input 0.34 0.61 A Resonator connection 0.53 0.80 A Square wave input 0.37 2.30 A Resonator connection 0.56 2.49 A Square wave input 0.61 4.03 A Resonator connection 0.80 4.22 A Square wave input 1.55 8.04 A Resonator connection 1.74 8.23 A A TA = -40C 0.19 TA = +25C 0.25 0.52 A TA = +50C 0.28 2.21 A TA = +70C 0.52 3.94 A TA = +85C 1.46 7.95 A (Notes and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 990 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral <R> operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When highspeed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. <R> 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz <R> 8. If operation of the subsystem clock when STOP mode, same as when HALT mode of subsystem clock operation. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25C R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 991 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS <R> (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply current IDD1 Note 1 Conditions Operating mode HS (highspeed main) Note 5 mode fIH = 32 MHz Note 3 MIN. (1/2) TYP. Basic operation VDD = 5.0 V VDD = 3.0 V 2.6 Normal operation VDD = 5.0 V 6.1 MAX. 2.6 Unit mA mA 9.5 mA VDD = 3.0 V 6.1 9.5 mA fIH = 24 MHz Note 3 Normal operation VDD = 5.0 V 4.8 7.4 mA VDD = 3.0 V 4.8 7.4 mA fIH = 16 MHz Note 3 Normal operation VDD = 5.0 V 3.5 5.3 mA VDD = 3.0 V 3.5 5.3 mA Normal operation VDD = 3.0 V 1.5 2.3 mA VDD = 2.0 V 1.5 2.3 mA Normal operation VDD = 3.0 V 1.5 2.0 mA VDD = 2.0 V 1.5 2.0 mA Normal operation Square wave input 3.9 6.1 mA Resonator connection 4.1 6.3 mA Note 2 Normal operation Square wave input 3.9 6.1 mA Resonator connection 4.1 6.3 mA Note 2 Normal operation Square wave input 2.5 3.7 mA Resonator connection 2.5 3.7 mA Note 2 Normal operation Square wave input 2.5 3.7 mA Resonator connection 2.5 3.7 mA Normal operation Square wave input 1.4 2.2 mA Resonator connection 1.4 2.2 mA Normal operation Square wave input 1.4 2.2 mA Resonator connection 1.4 2.2 mA Normal operation Square wave input 5.4 A Resonator connection 5.5 A Normal operation Square wave input 5.5 6.5 A Resonator connection 5.6 6.6 A Normal operation Square wave input 5.6 9.4 A Resonator connection 5.7 9.5 A Normal operation Square wave input 5.9 12.0 A Resonator connection 6.0 12.1 A Normal operation Square wave input 6.8 16.3 A Resonator connection 6.9 16.4 A LS (lowspeed main) Note 5 mode fIH = 8 MHz LV (lowvoltage main) mode fIH = 4 MHz Note 3 Note 3 Note 5 HS (highspeed main) Note 5 mode Note 2 fMX = 20 MHz , VDD = 5.0 V fMX = 20 MHz , VDD = 3.0 V fMX = 10 MHz , VDD = 5.0 V fMX = 10 MHz , VDD = 3.0 V LS (lowspeed main) Note 5 mode Note 2 fMX = 8 MHz , VDD = 3.0 V Note 2 fMX = 8 MHz , VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz Note 4 TA = -40C fSUB = 32.768 kHz Note 4 TA = +25C fSUB = 32.768 kHz Note 4 TA = +50C fSUB = 32.768 kHz Note 4 TA = +70C fSUB = 32.768 kHz Note 4 TA = +85C (Notes and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 992 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. When high-speed on-chip oscillator and subsystem clock are stopped. 3. When high-speed system clock and subsystem clock are stopped. 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time counter and watchdog timer is stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation). <R> 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V @1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 993 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS <R> (3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Supply current IDD2 Note 2 Conditions HALT mode Note 1 HS (highspeed main) Note 7 mode TYP. MAX. Unit fIH = 32 MHz Note 4 VDD = 5.0 V 0.62 1.89 mA VDD = 3.0 V 0.62 1.89 mA fIH = 24 MHz Note 4 VDD = 5.0 V 0.50 1.48 mA VDD = 3.0 V 0.50 1.48 mA fIH = 16 MHz Note 4 VDD = 5.0 V 0.44 1.12 mA LS (lowspeed main) Note 7 mode fIH = 8 MHz LV (lowvoltage main) mode fIH = 4 MHz MIN. (2/2) Note 4 Note 4 VDD = 3.0 V 0.44 1.12 mA VDD = 3.0 V 290 620 A VDD = 2.0 V 290 620 A VDD = 3.0 V 460 700 A VDD = 2.0 V 460 700 A Note 7 HS (highspeed main) Note 7 mode Note 3 fMX = 20 MHz , VDD = 5.0 V Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 fMX = 10 MHz , VDD = 5.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V LS (lowspeed main) Note 7 mode Note 3 fMX = 8 MHz , VDD = 3.0 V Note 3 fMX = 8 MHz , VDD = 2.0 V Subsystem clock operation fSUB = 32.768 kHz Note 5 TA = -40C fSUB = 32.768 kHz Note 5 TA = +25C fSUB = 32.768 kHz Note 5 TA = +50C fSUB = 32.768 kHz Note 5 TA = +70C fSUB = 32.768 kHz TA = +85C Note 6 IDD3 STOP Note 8 mode Note 5 Square wave input 0.31 1.14 mA Resonator connection 0.48 1.34 mA Square wave input 0.31 1.14 mA Resonator connection 0.48 1.34 mA Square wave input 0.21 0.68 mA Resonator connection 0.28 0.76 mA Square wave input 0.21 0.68 mA Resonator connection 0.28 0.76 mA Square wave input 110 390 A Resonator connection 160 450 A Square wave input 110 390 A Resonator connection 160 450 A Square wave input 0.31 A Resonator connection 0.50 A Square wave input 0.38 0.66 A Resonator connection 0.57 0.85 A Square wave input 0.46 3.49 A Resonator connection 0.65 3.68 A Square wave input 0.75 6.10 A Resonator connection 0.94 6.29 A Square wave input 1.65 10.46 A Resonator connection 1.84 10.65 A A TA = -40C 0.19 TA = +25C 0.26 0.54 A TA = +50C 0.34 3.37 A TA = +70C 0.63 5.98 A TA = +85C 1.53 10.34 A (Notes and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 994 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Notes 1. Total current flowing into VDD, EVDD0 and EVDD1, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral <R> operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. When high-speed on-chip oscillator and subsystem clock are stopped. 4. When high-speed system clock and subsystem clock are stopped. 5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When highspeed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. 6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When watchdog timer is stopped. The values below the MAX. column include the leakage current. <R> 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (low-speed main) mode: 1.8 V VDD 5.5 V @1 MHz to 8 MHz LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz <R> 8. If operation of the subsystem clock when STOP mode, same as when HALT mode of subsystem clock operation. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: High-speed on-chip oscillator clock frequency 3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25C R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 995 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (4) Common to RL78/G13 all products (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter RTC operating Symbol Conditions IRTC Notes 1, 2 IWDT Notes 2, 3 fIL = 15 kHz IADC Note 4 When conversion at maximum speed fSUB = 32.768 kHz current Watchdog timer MIN. TYP. MAX. Unit Real-time clock operation 0.02 A 12-bit Interval timer operation 0.02 A 0.22 A operating current A/D converter operating current Normal mode, AVREFP = VDD = 5.0 V 1.3 1.7 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.5 0.7 mA IADREF 75.0 A Temperature sensor operating current ITMPS 75.0 A LVD operating ILVI 0.08 A <R> A/D converter reference voltage current Note 5 current BGO operating IBGO Note 6 2.50 12.20 mA 0.50 0.60 mA 1.20 1.44 mA 0.70 0.84 mA current <R> SNOOZE ISNOZ ADC operation The mode is performed Note 7 operating The A/D conversion operations are current performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI/UART operation Notes 1. Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The value of the current value of the RL78/G13 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode. IDD2 subsystem clock operation includes the operational current of the real-time clock. 2. When high speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78/G13 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when fCLK = fSUB when the watchdog timer operates in STOP mode. 4. Current flowing only to the A/D converter. The current value of the RL78/G13 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 5. Current flowing only to the LVD circuit. The current value of the RL78/G13 microcontrollers is the sum of IDD1, IDD2 or IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode. 6. Current flowing only to the BGO. The current value of the RL78/G13 microcontrollers are is the sum of IDD1 or IDD2 and IBGO when the BGO operates in an operation mode. <R> 7. Shift time to the SNOOZE mode is 18.96 s to 28.95 s. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency) 3. fCLK: CPU/peripheral hardware clock frequency 4. Temperature condition of the TYP. value is TA = 25C R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 996 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.4 AC Characteristics (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fMAIN) operation MIN. TYP. HS (high-speed 2.7 V VDD 5.5 V 0.03125 main) mode 2.4 V VDD < 2.7 V 0.0625 MAX. Unit 1 s 1 s LV (low-voltage 1.6 V VDD 5.5 V main) mode 0.25 1 s LS (low-speed 1.8 V VDD 5.5 V main) mode 0.125 1 s 1.8 V VDD 5.5 V 28.5 31.3 s Subsystem clock (fSUB) 30.5 operation 1 s 1 s 1 s 0.125 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 1.8 V VDD < 2.7 V 1.0 8.0 MHz 1.6 V VDD < 1.8 V 1.0 4.0 MHz 32 35 kHz 2.7 V VDD 5.5 V 24 ns 1.8 V VDD < 2.7 V 60 ns 1.6 V VDD < 1.8 V 120 ns In the self HS (high-speed 2.7 V VDD 5.5 V 0.03125 programming main) mode 2.4 V VDD < 2.7 V 0.0625 mode 0.25 LV (low-voltage 1.8 V VDD 5.5 V main) mode LS (low-speed 1.8 V VDD 5.5 V main) mode External system clock frequency fEX fEXT External system clock input high-level width, low-level width tEXH, tEXL tEXHS, tEXLS TI00 to TI07, TI10 to TI17 input high-level width, low-level width tTIH, tTIL TO00 to TO07, TO10 to TO17 output frequency fTO PCLBUZ0, PCLBUZ1 output frequency fPCL s 13.7 Note 1/fMCK+10 ns 4.0 V EVDD0 5.5 V 16 MHz 2.7 V EVDD0 < 4.0 V 8 MHz 1.8 V EVDD0 < 2.7 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz LV (low-voltage main) mode 1.6 V EV 5.5 V 2 MHz LS (low-speed main) mode 1.8 V EVDD0 5.5 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz HS (high-speed main) mode 4.0 V EVDD0 5.5 V 16 MHz 2.7 V EVDD0 < 4.0 V 8 MHz 1.8 V EVDD0 < 2.7 V 4 MHz HS (high-speed main) mode DD0 1.6 V EVDD0 < 1.8 V 2 MHz LV (low-voltage main) mode 1.8 V EVDD0 5.5 V 4 MHz 1.6 V EVDD0 < 1.8 V 2 MHz LS (low-speed main) mode 1.8 V EVDD0 5.5 V 4 MHz 2 MHz 1.6 V EVDD0 < 1.8 V Interrupt input high-level width, low-level width tINTH, tINTL INTP0 1.6 V VDD 5.5 V 1 s INTP1 to INTP11 1.6 V EVDD0 5.5 V 1 s Key interrupt input low-level width tKR KR0 to KR7 1.8 V EVDD0 5.5 V 250 ns 1 s RESET low-level width tRSL 10 s 1.6 V EVDD0 < 1.8 V (Note and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 997 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Note The following conditions are required for low voltage interface when EVDD0<VDD 1.8 V EVDD0 < 2.7 V : MIN. 125 ns 1.6 V EVDD0 < 1.8 V : MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)) <R> AC Timing Test Points VIH VIH Test points VIL VIL External System Clock Timing 1/fEX tEXL tEXH 0.7VDD (MIN.) 0.3VDD (MAX.) EXCLK TI/TO Timing tTIH tTIL TI00 to TI07, TI10 to TI17 1/fTO TO00 to TO07, TO10 to TO17 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP11 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 998 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Key Interrupt Input Timing tKR KR0 to KR7 RESET Input Timing tRSL RESET R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 999 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.5 Peripheral Functions Characteristics 29.5.1 Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Transfer rate Symbol Conditions MIN. TYP. Note 1 MAX. fMCK/6 Theoretical value of the Note 2 5.3 Unit bps Mbps maximum transfer rate fCLK = 32 MHz, fMCK = fCLK UART mode connection diagram (during communication at same potential) Rx TxDq RL78/G13 microcontrollers User's device Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Notes 1. Transfer rate in the SNOOZE mode is MAX. 9600 bps, MIN. 4800 bps. 2. The following conditions are required for low voltage interface when EVDD0<VDD. 2.4 V EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V EVDD0 < 1.8 V : MAX. 0.6 Mbps Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1000 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (2) During communication at same potential (CSI mode) (master mode (fMCK/2), SCKp... internal clock output, coresponting CSI00 only) (TA = -40 to +85C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol SCKp cycle time SCKp high-/low-level width SIp setup time (to SCKp) Note 2 Conditions MIN. SIp hold time (from SCKp) Delay time from SCKp to SOp output MAX. Unit tKCY1 2.7 V EVDD0 5.5 V 62.5 tKH1, 4.0 V EVDD0 5.5 V tKCY1/2 - 7 ns tKL1 2.7 V EVDD0 5.5 V tKCY1/2 - 10 ns 23 ns tSIK1 4.0 V EVDD0 5.5 V 2.7 V EVDD0 5.5 V Note 3 TYP. tKSI1 tKSO1 2.7 V EVDD0 5.5 V 33 Note 1 ns Note 5 ns 10 Note 6 C = 20 pF ns 10 ns Note 4 Notes 1. The value must also be 2/fCLK or more. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. Using the fMCK within 24 MHz. 6. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. This specification is valid only when CSI00's peripheral I/O redirect function is not used. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM numbers (g = 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1001 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output) (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol SCKp cycle time tKCY1 Conditions 2.7 V EVDD0 5.5 V 2.4 V EVDD0 5.5 V 1.8 V EVDD0 5.5 V 1.6 V EVDD0 5.5 V SCKp high-/low-level width MIN. TYP. MAX. Unit 125 Note 1 ns 250 Note 1 ns 500 Note 1 ns 1000 Note 1 ns tKH1, 4.0 V EVDD0 5.5 V tKCY1/2 - 12 ns tKL1 2.7 V EVDD0 5.5 V tKCY1/2 - 18 ns 2.4 V EVDD0 5.5 V tKCY1/2 - 38 ns 1.8 V EVDD0 5.5 V tKCY1/2 - 50 ns 1.6 V EVDD0 5.5 V tKCY1/2 - ns 100 SIp setup time (to SCKp) Note 2 SIp hold time (from SCKp) Note 3 Delay time from SCKp to SOp output tSIK1 4.0 V EVDD0 5.5 V 44 ns 2.7 V EVDD0 5.5 V 44 ns 2.4 V EVDD0 5.5 V 75 ns 1.8 V EVDD0 5.5 V 110 ns 1.6 V EVDD0 5.5 V 220 ns 19 ns tKSI1 tKSO1 Note 5 C = 30 pF 25 ns Note 4 Notes 1. The value must also be 4/fCLK or more. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1002 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCKp cycle time Note 5 SCKp high-/low-level width Symbol tKCY2 tKH2, Conditions MIN. TYP. MAX. Unit 4.0 V EVDD0 5.5 V 20 MHz < fMCK 8/fMCK ns fMCK 20 MHz 6/fMCK ns 2.7 V EVDD0 < 4.0 V 16 MHz < fMCK 8/fMCK ns fMCK 16 MHz 6/fMCK ns 1.8 V EVDD0 < 2.7 V 16 MHz < fMCK 8/fMCK ns fMCK 16 MHz 6/fMCK ns 1.6 V EVDD0 < 1.8 V 6/fMCK ns 1.6 V EVDD0 5.5 V tKCY2/2 ns 2.7 V EVDD0 5.5 V 1/fMCK+20 ns 1.8 V EVDD0 < 2.7 V 1/fMCK+30 ns 1.6 V EVDD0 < 1.8 V 1/fMCK+40 ns 2.7 V EVDD0 5.5 V 1/fMCK+31 ns 1.8 V EVDD0 < 2.7 V 1/fMCK+31 ns 1.6 V EVDD0 < 1.8 V 1/fMCK+ ns tKL2 SIp setup time (to SCKp) tSIK2 Note 1 SIp hold time (from SCKp) tKSI2 Note 2 250 Delay time from SCKp to SOp output tKSO2 Note 3 C = 30 pF Note 4 4.0 V EVDD0 5.5 V 2/fMCK+44 ns 2.7 V EVDD0 < 4.0 V 2/fMCK+44 ns 2.4 V EVDD0 < 2.7 V 2/fMCK+75 ns 1.8 V EVDD0 < 2.4 V 2/fMCK+110 ns 1.6 V EVDD0 < 1.8 V 2/fMCK+220 ns Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. 5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps <R> Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1003 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at same potential) SCK SCKp RL78/G13 SIp microcontrollers SO User's device SI SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 Output data SOp CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31) m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1004 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 (5) During communication at same potential (simplified I C mode) (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 2.7 V EVDD0 5.5 V, MAX. Unit 1000 kHz 400 kHz 300 kHz 250 kHz Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "L" tLOW 2.7 V EVDD0 5.5 V, 475 ns 1150 ns 1550 ns 1850 ns 475 ns 1150 ns 1550 ns 1850 ns 1/fMCK + 85 ns Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "H" tHIGH 2.7 V EVDD0 5.5 V, Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Data setup time (reception) tSU:DAT 2.7 V EVDD0 5.5 V, Note Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD 5.5 V, 1/fMCK + 145 ns Note Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, 1/fMCK + 230 ns Note Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, 1/fMCK + 290 ns Note Cb = 100 pF, Rb = 5 k Data hold time (transmission) tHD:DAT 2.7 V EVDD0 5.5 V, 0 305 ns 0 355 ns 0 405 ns 0 405 ns Cb = 50 pF, Rb = 2.7 k 1.8 V EVDD0 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V EVDD0 < 2.7 V, Cb = 100 pF, Rb = 5 k 1.6 V EVDD0 < 1.8 V, Cb = 100 pF, Rb = 5 k Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". (Caution and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1005 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78/G13 microcontrollers User's device SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT <R> Caution tSU:DAT Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register h (POMh). Remarks 1. Rb[]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14), h: POM number (g = 0, 1, 4, 5, 7 to 9, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1006 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Transfer rate Symbol Conditions MIN. Reception 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V TYP. MAX. fMCK/6 Theoretical value of the Note 1 5.3 Unit bps Mbps maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V fMCK/6 Theoretical value of the Note 1 bps 5.3 Mbps fMCK/6 bps maximum transfer rate fCLK = 32 MHz, fMCK = fCLK 1.8 V EVDD0 < 3.3 V, Notes 1 to 3 1.6 V Vb 2.0 V Theoretical value of the 1.3 Mbps maximum transfer rate fCLK = 8 MHz, fMCK = fCLK Notes 1. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps 2. Use it with EVDD0Vb. 3. The following conditions are required for low voltage interface when EVDD0<VDD. 2.4 V EVDD0 < 2.7 V : MAX. 2.6 Mbps 1.8 V EVDD0 < 2.4 V : MAX. 1.3 Mbps 1.6 V EVDD0 < 1.8 V : MAX. 0.6 Mbps Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. 2. 3. Vb[V]: Communication line voltage q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13) <R> 4. UART2 cannnot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1007 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (2/2) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions MIN. TYP. Transmission 4.0 V EVDD0 5.5 V, Transfer rate MAX. Unit Notes bps 1, 2 2.7 V Vb 4.0 V Theoretical value of the 2.8 Note 3 Mbps maximum transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V EVDD0 < 4.0 V, Notes bps 2, 4 2.3 V Vb 2.7 V Theoretical value of the 1.2 Note 5 Mbps maximum transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.8 V EVDD0 < 3.3 V, Notes 1.6 V Vb 2.0 V 2, 6, 7 Theoretical value of the maximum transfer rate 0.43 bps Mbps Note 8 Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.2 )} x 3 Vb [bps] 2.2 1 - {-Cb x Rb x ln (1 - )} Vb Transfer rate x 2 1 ( ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. 3. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. 4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 2.0 )} x 3 Vb [bps] 1 2.0 - {-Cb x Rb x ln (1 - )} Vb Transfer rate x 2 1 ( ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 5. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1008 RL78/G13 Notes 6. 7. CHAPTER 29 ELECTRICAL SPECIFICATIONS Use it with EVDD0 Vb. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V 1 Maximum transfer rate = {-Cb x Rb x ln (1 - Baud rate error (theoretical value) = 1.5 )} x 3 Vb [bps] 1.5 1 - {-Cb x Rb x ln (1 - )} Vb Transfer rate x 2 1 ( ) x Number of transferred bits Transfer rate x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 8. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[]:Communication line (TxDq) pull-up resistance, Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)) <R> 4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. UART mode connection diagram (during communication at different potential) Vb Rb TxDq Rx RL78/G13 microcontrollers RxDq R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 User's device Tx 1009 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. UART2 cannot communicate at different potentia when bit 1 (PIOR1) of peripheral I/O redirection register (PIOR) is 1. 2. Rb[]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage 3. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1010 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (7) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output, coresponting CSI00 only) (TA = -40 to +85C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, MIN. TYP. MAX. Unit 200 Note 1 ns 300 Note 1 ns Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp high-level width tKH1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, tKCY1/2 - 50 ns Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCKp low-level width tKL1 tKCY1/2 - ns 120 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, tKCY1/2 - 7 ns Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, tKCY1/2 - 10 ns Cb = 20 pF, Rb = 2.7 k SIp setup time (to SCKp) tSIK1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 58 ns 121 ns 10 ns 10 ns Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SIp hold time (from SCKp) tKSI1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKp to SOp output tKSO1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 60 ns 130 ns Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k <R> SIp setup time (to SCKp) tSIK1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 21 ns 29 ns 10 ns 10 ns Note 3 Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, <R> Cb = 20 pF, Rb = 2.7 k SIp hold time (from SCKp) tKSI1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Note 3 Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCKp to SOp output tKSO1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 10 ns 10 ns Note 3 Cb = 20 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k (Note, Caution and Remark are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1011 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) <Master> Vb Rb SCKp RL78/G13 SIp microcontrollers SOp Vb Rb SCK SO User's device SI Notes 1. The value must also be 2/fCLK or more. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 1) <R> 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00)) 4. This specification is valid only when CSI00's peripheral I/O redirect function is not used. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1012 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, MIN. TYP. MAX. Unit 300 Note ns 500 Note ns Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, 1150 Note ns Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, tKCY1/2 - 75 ns Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 tKCY1/2 - ns 170 tKCY1/2 - ns 458 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, tKCY1/2 - 12 ns Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, tKCY1/2 - 18 ns Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, tKCY1/2 - 50 ns Cb = 30 pF, Rb = 5.5 k Note The value must also be 4/fCLK or more. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). 2. Use it with EVDD0 Vb. Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) <R> 3. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1013 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SIp setup time Note 1 (to SCKp) Symbol tSIK1 Conditions MIN. TYP. MAX. Unit 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 81 ns 177 ns 479 ns 19 ns 19 ns 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time Note 1 (from SCKp) tKSI1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to Note 1 SOp output tKSO1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 100 ns 195 ns 483 ns Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp setup time Note 2 (to SCKp) tSIK1 4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V, 44 ns 44 ns 110 ns 19 ns 19 ns 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time Note 2 (from SCKp) tKSI1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from SCKp to Note 2 SOp output tKSO1 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 25 ns 25 ns 25 ns Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k (Notes, Cautions and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1014 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) <Master> Vb Rb SCKp RL78/G13 SIp microcontrollers SOp Vb Rb SCK SO User's device SI Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). 2. Use it with EVDD0 Vb. Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) <R> 3. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1015 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp Output data Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 00, 01, 02, 10, 12, 13), n: Channel number (n = 0, 2), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1016 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCKp cycle time Note 1 Symbol tKCY2 SCKp high-/low-level tKH2, width tKL2 Conditions MIN. TYP. MAX. Unit 4.0 V EVDD0 5.5 V, 24 MHz < fMCK 14/fMCK ns 2.7 V Vb 4.0 V 20 MHz < fMCK 24 MHz 12/fMCK ns 8 MHz < fMCK 20 MHz 10/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK ns fMCK 4 MHz 6/fMCK ns 2.7 V EVDD0 < 4.0 V, 24 MHz < fMCK 20/fMCK ns 2.3 V Vb 2.7 V 16/fMCK ns 16 MHz < fMCK 20 MHz 14/fMCK ns 8 MHz < fMCK 16 MHz 12/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK ns fMCK 4 MHz 6/fMCK ns 1.8 V EVDD0 < 3.3 V, 24 MHz < fMCK 48/fMCK ns 1.6 V Vb 2.0 V 20 MHz < fMCK 24 MHz 36/fMCK ns 16 MHz < fMCK 20 MHz 32/fMCK ns 8 MHz < fMCK 16 MHz 26/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 10/fMCK ns tKCY2/2 - ns 20 MHz < fMCK 24 MHz Note 2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V 12 tKCY2/2 - 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V ns 18 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2 - ns 50 <R> SIp setup time (to SCKp) tSIK2 2.7 V EVDD0 5.5 V, 2.3 V Vb 4.0 V Note 2 1/fMCK + Note 3 ns 20 1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK + ns 30 SIp hold time (from SCKp) tKSI2 <R> Delay time from SCKp to SOp output 1/fMCK + 31 ns Note 4 tKSO2 Note 5 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, 2/fMCK + Cb = 30 pF, Rb = 1.4 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V, 2/fMCK + Cb = 30 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Cb = 30 pF, Rb = 5.5 k ns 120 ns 214 Note 2 , 2/fMCK + ns 573 (Notes, Caution and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1017 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) <Slave> Vb Rb SCKp SIp RL78/G13 microcontrollers SOp SCK SO User's device SI Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps 2. Use it with EVDD0 Vb. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 00, 01, 02, 10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13)) <R> 4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1018 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 SIp tKSI2 Input data tKSO2 SOp Output data Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14) 2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for communication at different potential. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1019 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (1/2) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 4.0 V EVDD0 5.5 V, MAX. Unit 1000 kHz 1000 kHz 400 kHz 400 kHz 300 kHz 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1 , Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V EVDD0 5.5 V, 475 ns 475 ns 1150 ns 1150 ns 1550 ns 245 ns 200 ns 675 ns 600 ns 610 ns 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1 , Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V Note 1 , Cb = 100 pF, Rb = 5.5 k (Notes, Caution and Remarks are listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1020 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (2/2) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Data setup time (reception) Data hold time (transmission) Symbol tSU:DAT tHD:DAT Conditions MIN. 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 1/fMCK + 135 MAX. Unit ns Note 2 ns Note 2 1/fMCK + 190 4.0 V EVDD0 5.5 V, Note 2 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k ns 2.7 V EVDD0 < 4.0 V, 1/fMCK + 190 Note 2 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k ns 1.8 V EVDD0 < 3.3 V, 1/fMCK + 190 Note 2 Notes 1 , 1.6 V Vb 2.0 V Cb = 100 pF, Rb = 5.5 k ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 50 pF, Rb = 2.7 k 0 305 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 50 pF, Rb = 2.7 k 0 305 ns 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 0 355 ns 2.7 V EVDD0 < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 0 355 ns 1.8 V EVDD0 < 3.3 V, Note 1 , 1.6 V Vb 2.0 V Cb = 100 pF, Rb = 5.5 k 0 405 ns Notes 1. Use it with EVDD0 Vb. 2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). (Remarks is listed on the next page.) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1021 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 2 Simplified I C mode connection diagram (during communication at different potential) Vb Rb Vb Rb SDA SDAr RL78/G13 microcontrollers User's device SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD:DAT tSU:DAT Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the N-ch open drain output (VDD tolerance (When 20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1. Rb[]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance, Vb[V]: Communication line voltage 2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: <R> Channel number (mn = 00, 01, 02, 10, 12, 13) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1022 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.5.2 Serial interface IICA (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Standard Conditions Fast Mode Fast Mode MIN. SCLA0 clock frequency fSCL MAX. MIN. MAX. Fast mode plus: 2.7 V EVDD0 5.5 V fCLK 10 MHz Fast mode: 1.8 V EVDD0 5.5 V Unit Plus Mode 0 MIN. MAX. 0 1000 400 kHz kHz fCLK 3.5 MHz Normal mode: 1.6 V EVDD0 5.5 V 0 100 kHz fCLK 1 MHz Setup time of restart condition tSU:STA 4.7 0.6 0.26 s tHD:STA 4.0 0.6 0.26 s Hold time when SCLA0 = "L" tLOW 4.7 1.3 0.5 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 0.26 s tSU:DAT 250 100 50 ns tHD:DAT 0 Setup time of stop condition tSU:STO 4.0 0.6 0.26 s Bus-free time tBUF 4.7 1.3 0.5 s Hold time Note 1 Data setup time (reception) <R> Data hold time (transmission) Note 2 Notes 1. 2. Remark 3.45 0 0.9 0 s 0.45 The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at that time in each mode are as follows. Standard mode: Cb = 400 pF, Rb = 2.7 k Fast mode: Cb = 320 pF, Rb = 1.1 k Fast mode plus: Cb = 120 pF, Rb = 1.1 k IICA serial transfer timing tLOW SCL0 tHD:DAT tHD:STA tHIGH tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tLOW Stop condition Start condition R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Restart condition Stop condition 1023 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.5.3 On-chip debug (UART) (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol Conditions Transfer rate MIN. TYP. 115.2 k MAX. Unit 1M bps 29.6 Analog Characteristics 29.6.1 A/D converter characteristics (1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin : ANI2 to ANI14 (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution RES Notes 1, 2 Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error Notes 1, 2 Integral linearity error Note 1 Differential linearity error <R> Conditions Note 1 Analog input voltage VAIN VBGR 10 bit 1.8 V VDD 5.5 V 1.2 3.5 LSB 1.6 V VDD 5.5 V 1.2 7.0 LSB 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s AVREFP = VDD 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 1.8 V VDD 5.5 V 0.25 %FSR 1.6 V VDD 5.5 V 0.50 %FSR EFS AVREFP Unit AVREFP = VDD 10-bit resolution AVREFP = VDD Reference voltage (+) MAX. 10-bit resolution 10-bit resolution AVREFP = VDD DLE TYP. 8 EZS ILE MIN. 1.8 V VDD 5.5 V 0.25 %FSR 1.6 V VDD 5.5 V 0.50 %FSR 10-bit resolution 1.8 V VDD 5.5 V 2.5 LSB AVREFP = VDD 1.6 V VDD 5.5 V 5.0 LSB 10-bit resolution 1.8 V VDD 5.5 V 1.5 LSB AVREFP = VDD 1.6 V VDD 5.5 V 2.0 LSB 1.6 VDD V 0 AVREFP V 1.5 V Select interanal reference voltage output 1.38 1.45 2.4 V VDD 5.5 V, HS (high-speed main) mode Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1024 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (2) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin : ANI16 to ANI26 (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM) Parameter Symbol Resolution Conditions RES Notes 1, 2 Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error EZS Notes 1, 2 Integral linearity error EFS Note 1 Differential linearity error ILE Note 1 DLE Reference voltage (+) AVREFP Analog input voltage VAIN MIN. TYP. 8 MAX. Unit 10 bit 10-bit resolution 1.8 V VDD 5.5 V 1.2 5.0 LSB AVREFP = VDD 1.6 V VDD 5.5 V 1.2 8.5 LSB 10-bit resolution 3.6 V VDD 5.5 V 2.125 39 s AVREFP = VDD 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 1.8 V VDD 5.5 V 0.35 %FSR 1.6 V VDD 5.5 V 0.60 %FSR 1.8 V VDD 5.5 V 0.35 %FSR 1.6 V VDD 5.5 V 0.60 %FSR 10-bit resolution 1.8 V VDD 5.5 V 3.5 LSB AVREFP = VDD 1.6 V VDD 5.5 V 6.0 LSB 10-bit resolution 1.8 V VDD 5.5 V 2.0 LSB AVREFP = VDD 1.6 V VDD 5.5 V 2.5 LSB 1.6 VDD V 0 AVREFP V 10-bit resolution AVREFP = VDD 10-bit resolution AVREFP = VDD and EVDD0 <R> VBGR Select interanal reference voltage output 1.38 1.45 1.5 V 2.4 V VDD 5.5 V, HS (high-speed main) mode Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1025 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (-) = VSS (ADREFM = 0), target ANI pin : ANI0 to ANI14, ANI16 to ANI26 (TA = -40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Resolution RES Notes 1, 2 Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Full-scale error EZS Notes 1, 2 Integral linearity error EFS Note 1 Differential linearity error Analog input voltage <R> Conditions ILE Note 1 DLE VAIN VBGR MIN. TYP. 8 10-bit resolution 10-bit resolution 10-bit resolution 10-bit resolution 10-bit resolution 10-bit resolution MAX. Unit 10 bit 1.8 V VDD 5.5 V 1.2 7.0 LSB 1.6 V VDD 5.5 V 1.2 10.5 LSB 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s 1.6 V VDD 5.5 V 57 95 s 1.8 V VDD 5.5 V 0.60 %FSR 1.6 V VDD 5.5 V 0.85 %FSR 1.8 V VDD 5.5 V 0.60 %FSR 1.6 V VDD 5.5 V 0.85 %FSR 1.8 V VDD 5.5 V 4.0 LSB 1.6 V VDD 5.5 V 6.5 LSB 1.8 V VDD 5.5 V 2.0 LSB 1.6 V VDD 5.5 V 2.5 LSB ANI0 to ANI14 0 VDD V ANI16 to ANI26 0 EVDD0 V 1.5 V Select interanal reference voltage output, 1.38 1.45 2.4 V VDD 5.5 V, HS (high-speed main) mode Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1026 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS (4) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), target ANI pin : ANI0 to ANI14, ANI16 to ANI26 <R> (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VBGR, Reference voltage (-) = AVREFM = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. RES Conversion time Notes 1, 2 Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 TYP. MAX. 8 Unit bit 39 s 2.4 V VDD 5.5 V 0.60 %FSR 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB 1.5 V VBGR V tCONV 8-bit resolution 2.4 V VDD 5.5 V EZS 8-bit resolution ILE DLE 17 Reference voltage (+) VBGR 1.38 Analog input voltage VAIN 0 1.45 Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1027 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.6.2 Temperature sensor characteristics <R> (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode) Parameter Symbol Conditions Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C Reference output voltage VCONST Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that depends on the MIN. TYP. MAX. 1.05 1.38 1.45 Unit V 1.5 -3.6 V mV/C temperature Operation stabilization wait time tAMP 5 s 29.6.3 POR circuit characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Detection voltage Minimum pulse width Detection delay time R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 Symbol Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.48 1.51 1.54 V VPDR Power supply fall time 1.47 1.50 1.53 V TPW s 300 350 s 1028 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85C, VPDR EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Detection Supply voltage level Symbol VLVD0 voltage VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 VLVD12 VLVD13 Minimum pulse width tLW Detection delay time Remark Conditions MIN. TYP. MAX. Unit Power supply rise time 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V Power supply rise time 1.74 1.77 1.81 V Power supply fall time 1.70 1.73 1.77 V Power supply rise time 1.64 1.67 1.70 V Power supply fall time 1.60 1.63 1.66 V s 300 300 s VLVD(n - 1) > VLVDn: n = 1 to 13 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1029 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS LVD Detection Voltage of Interrupt & Reset Mode (TA = -40 to +85C, VPDR EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter Symbol <R> Interrupt and reset VLVD13 mode VLVD12 VLVD11 VLVD4 VLVD11 VLVD10 VLVD9 VLVD2 VLVD8 VLVD7 Conditions VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage: 1.6 V VLVD1 VLVD5 VLVD4 VLVD3 VLVD0 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 TYP. MAX. Unit 1.60 1.63 1.66 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage (+0.1 V) Falling interrupt voltage 1.74 1.77 1.81 V 1.70 1.73 1.77 V LVIS1, LVIS0 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V (+0.2 V) 1.80 1.84 1.87 V LVIS1, LVIS0 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V (+1.2 V) 2.80 2.86 2.91 V 1.80 1.84 1.87 V Falling interrupt voltage Falling interrupt voltage VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V (+0.1 V) 1.90 1.94 1.98 V Falling interrupt voltage LVIS1, LVIS0 = 0, 1 Rising release reset voltage (+0.2 V) Falling interrupt voltage 2.05 2.09 2.13 V 2.00 2.04 2.08 V LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V (+1.2 V) 3.00 3.06 3.12 V 2.40 2.45 2.50 V 2.56 2.61 2.66 V Falling interrupt voltage VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage (+0.1 V) VLVD6 MIN. 2.50 2.55 2.60 V LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V (+0.2 V) 2.60 2.65 2.70 V 3.68 3.75 3.82 V 3.60 3.67 3.74 V 2.70 2.75 2.81 V Falling interrupt voltage Falling interrupt voltage LVIS1, LVIS0 = 0, 0 Rising release reset voltage (+1.2 V) Falling interrupt voltage VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage: 2.7 V LVIS1, LVIS0 = 1, 0 Rising release reset voltage (+0.1 V) Falling interrupt voltage 2.86 2.92 2.97 V 2.80 2.86 2.91 V LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V (+0.2 V) 2.90 2.96 3.02 V LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V (+1.2 V) 3.90 3.98 4.06 V Falling interrupt voltage Falling interrupt voltage 1030 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS Supply Voltage Rise Time (TA = -40 to +85C, VSS = 0 V) Parameter Symbol Maximum time to rise to tPUP1 Conditions MIN. When RESET input is not used TYP. MAX. Unit 3.2 ms Note 1.6 V (VDD (MIN.)) (VDD: 0 V 1.6 V) Note Make sure to raise the power supply in a shorter time than this. Supply Voltage Rise Time Timing * When RESET pin input is not used Supply voltage (VDD) 1.6 V 0V Time POR internal signal tPUP1 R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1031 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol Conditions MIN. VDDDR 1.47 TYP. Note MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected. Operation mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 29.8 Flash Memory Programming Characteristics (TA = -40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) Parameter CPU/peripheral hardware clock Symbol Conditions MIN. fCLK 1.8 V VDD 5.5 V Cerwr 1 erase + 1 write after Retained for 20 years TYP. 1 MAX. Unit 32 MHz frequency Number of code flash rewrites Note 1 1,000 Times the erase is regarded (Self/serial Number of data flash rewrites Note 2 as 1 rewrite. programming) The retaining years Retained for 1 years are until next rewrite (Self/serial after the rewrite. programming) 1,000,000 Note 2 Retained for 5 years 100,000 (Self/serial programming) Note 2 Notes 1. 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products, these specifications show target values, which may change after device evaluation. 2. When using flash memory programmer and Renesas Electronics self programming library Remark When updating data multiple times, use the flash memory as one for updating data. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1032 RL78/G13 CHAPTER 29 ELECTRICAL SPECIFICATIONS 29.9 Timing Specs for Switching Flash Memory Programming Modes Parameter Symbol How long from when a pin reset tSUINIT Conditions MIN. TYP. POR and LVD reset must end before the pin MAX. Unit 100 ms reset ends. ends until the initial communication settings are specified How long from when the TOOL0 tSU POR and LVD reset must end before the pin 10 s 1 ms reset ends. pin is placed at the low level until a pin reset ends How long the TOOL0 pin must be tHD POR and LVD reset must end before the pin reset ends. kept at the low level after a reset ends <R> (except soft processing time) <1> <R> <2> <4> <3> RESET tHD+ soft processing time 00H reception (TOOLRxD, TOOLTxD mode) TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <2> The pins reset ends (POR and LVD reset must end before the pin reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends (MIN. 10 s) tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end (except soft processing time) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1033 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS CHAPTER 30 PACKAGE DRAWINGS 30.1 20-pin products R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP <R> R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP20-0300-0.65 PLSP0020JC-A S20MC-65-5A4-3 0.12 20 11 detail of lead end F G T P L U E 1 10 A H J I S N S K C D M M B NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 6.650.15 B 0.475 MAX. C 0.65 (T.P.) D 0.24 +0.08 -0.07 E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P 3 +5 -3 T 0.25 U 0.60.15 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1034 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.2 24-pin products R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA <R> R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-1 0.04 D DETAIL OF A PART E S A A S y S (UNIT:mm) ITEM D2 A EXPOSED DIE PAD 1 6 D 4.00 0.05 E 4.00 0.05 A 0.75 0.05 b + 0.25 - 0.05 0.07 e 7 24 Lp B DIMENSIONS 0.50 0.40 0.10 x 0.05 y 0.05 E2 ITEM 19 12 18 EXPOSED DIE PAD VARIATIONS 13 D2 E2 MIN NOM MAX MIN NOM MAX A 2.45 2.50 2.55 2.45 2.50 2.55 e Lp b x M S AB 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1035 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.3 25-pin products R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA <R> R5F1008ADLA, R5F1008CDLA, R5F1008DDLA, R5F1008EDLA R5F1018ADLA, R5F1018CDLA, R5F1018DDLA, R5F1018EDLA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA25-3x3-0.50 PWLG0025KA-A P25FC-50-2N2-2 0.01 21x b w S A S AB M A ZD D x e ZE 5 4 B 3 2.27 E 2 C 1 E w S B INDEX MARK y1 S D C B A D 2.27 INDEX MARK A S (UNIT:mm) y S DETAIL OF C PART DETAIL OF D PART R0.170.05 0.430.05 R0.120.05 0.330.05 0.500.05 0.3650.05 b (LAND PAD) 0.340.05 (APERTURE OF SOLDER RESIST) 0.3650.05 ITEM D DIMENSIONS 3.000.10 E 3.000.10 w 0.20 e 0.50 A 0.690.07 b 0.240.05 x 0.05 y 0.08 y1 0.20 ZD 0.50 ZE 0.50 R0.1650.05 0.500.05 0.330.05 R0.2150.05 0.430.05 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1036 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.4 30-pin products R5F100AAASP, R5F100ACASP, R5F100ADASP, R5F100AEASP, R5F100AFASP, R5F100AGASP R5F101AAASP, R5F101ACASP, R5F101ADASP, R5F101AEASP, R5F101AFASP, R5F101AGASP <R> R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP, R5F100AFDSP, R5F100AGDSP R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP, R5F101AFDSP, R5F101AGDSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B M K ITEM A MILLIMETERS 9.850.15 B 0.45 MAX. C 0.65 (T.P.) NOTE D 0.24 +0.08 -0.07 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. E 0.10.05 F 1.30.1 G 1.2 H 8.10.2 I 6.10.2 J 1.00.2 K 0.170.03 L 0.5 M 0.13 N 0.10 P 3 +5 -3 T 0.25 U 0.60.15 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1037 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.5 32-pin products R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA, R5F100BFANA, R5F100BGANA R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA, R5F101BFANA, R5F101BGANA <R> R5F100BADNA, R5F100BCDNA, R5F100BDDNA, R5F100BEDNA, R5F100BFDNA, R5F100BGDNA R5F101BADNA, R5F101BCDNA, R5F101BDDNA, R5F101BEDNA, R5F101BFDNA, R5F101BGDNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN32-5x5-0.50 PWQN0032KB-A P32K8-50-3B4-3 0.06 D DETAIL OF A PART E S A A S y S (UNIT:mm) ITEM D2 A EXPOSED DIE PAD 1 9 32 D 5.00 0.05 E 5.00 0.05 A e 0.75 0.05 + 0.25 - 0.05 0.07 0.50 Lp 0.40 0.10 b 8 B DIMENSIONS x 0.05 y 0.05 E2 ITEM 25 16 17 24 Lp EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 3.45 3.50 3.55 3.45 3.50 3.55 e b x M S AB 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1038 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.6 36-pin products R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA, R5F100CFALA, R5F100CGALA R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA, R5F101CFALA, R5F101CGALA <R> R5F100CADLA, R5F100CCDLA, R5F100CDDLA, R5F100CEDLA, R5F100CFDLA, R5F100CGDLA R5F101CADLA, R5F101CCDLA, R5F101CDDLA, R5F101CEDLA, R5F101CFDLA, R5F101CGDLA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023 32x b S AB e ZE w S A M A ZD D x 6 5 B 4 E 3 2.90 2 C INDEX MARK y1 D w S B S 1 F E D C B A E 2.90 A S y S DETAIL C DETAIL E DETAIL D R0.17 0.05 0.70 0.05 0.55 0.05 R0.12 0.05 0.75 0.55 (UNIT:mm) R0.17 0.05 0.70 0.05 R0.12 0.05 0.55 0.05 0.75 0.55 b (LAND PAD) 0.340.05 (APERTURE OF SOLDER RESIST) 0.55 0.75 0.550.05 0.70 0.05 0.55 0.75 0.550.05 R0.2750.05 R0.350.05 ITEM D DIMENSIONS E 4.000.10 w 0.20 4.000.10 e 0.50 A 0.690.07 b 0.240.05 x 0.05 y 0.08 y1 0.20 ZD 0.75 ZE 0.75 0.700.05 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1039 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.7 40-pin products R5F100EAANA, R5F100ECANA, R5F100EDANA, R5F100EEANA, R5F100EFANA, R5F100EGANA, R5F100EHANA R5F101EAANA, R5F101ECANA, R5F101EDANA, R5F101EEANA, R5F101EFANA, R5F101EGANA, R5F101EHANA <R> R5F100EADNA, R5F100ECDNA, R5F100EDDNA, R5F100EEDNA, R5F100EFDNA, R5F100EGDNA, R5F100EHDNA R5F101EADNA, R5F101ECDNA, R5F101EDDNA, R5F101EEDNA, R5F101EFDNA, R5F101EGDNA, R5F101EHDNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-3 0.09 D DETAIL OF A PART E S A A S y S (UNIT:mm) D2 A 1 EXPOSED DIE PAD 10 DIMENSIONS D 6.00 0.05 E 6.00 0.05 A e 0.75 0.05 + 0.25 - 0.05 0.07 0.50 Lp 0.40 0.10 b 11 40 ITEM B x 0.05 y 0.05 E2 31 20 21 30 Lp e b x M ITEM EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 4.45 4.50 4.55 4.45 4.50 4.55 S AB 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1040 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.8 44-pin products R5F100FAAFP, R5F100FCAFP, R5F100FDAFP, R5F100FEAFP, R5F100FFAFP, R5F100FGAFP, R5F100FHAFP, R5F100FJAFP, R5F100FKAFP, R5F100FLAFP R5F101FAAFP, R5F101FCAFP, R5F101FDAFP, R5F101FEAFP, R5F101FFAFP, R5F101FGAFP, R5F101FHAFP, R5F101FJAFP, R5F101FKAFP, R5F101FLAFP <R> R5F100FADFP, R5F100FCDFP, R5F100FDDFP, R5F100FEDFP, R5F100FFDFP, R5F100FGDFP, R5F100FHDFP, R5F100FJDFP, R5F100FKDFP, R5F100FLDFP R5F101FADFP, R5F101FCDFP, R5F101FDDFP, R5F101FEDFP, R5F101FFDFP, R5F101FGDFP, R5F101FHDFP, R5F101FJDFP, R5F101FKDFP, R5F101FLDFP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36 HD D detail of lead end A3 23 22 33 34 c E L Lp HE L1 (UNIT:mm) 12 11 44 1 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. A1 DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 A2 y ITEM D 0.25 b 0.37 +0.08 -0.07 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.80 x 0.20 y 0.10 ZD 1.00 ZE 1.00 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1041 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.9 48-pin products R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, R5F100GEAFB, R5F100GFAFB, R5F100GGAFB, R5F100GHAFB, R5F100GJAFB, R5F100GKAFB, R5F100GLAFB R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB, R5F101GFAFB, R5F101GGAFB, R5F101GHAFB, R5F101GJAFB, R5F101GKAFB, R5F101GLAFB <R> R5F100GADFB, R5F100GCDFB, R5F100GDDFB, R5F100GEDFB, R5F100GFDFB, R5F100GGDFB, R5F100GHDFB, R5F100GJDFB, R5F100GKDFB, R5F100GLDFB R5F101GADFB, R5F101GCDFB, R5F101GDDFB, R5F101GEDFB, R5F101GFDFB, R5F101GGDFB, R5F101GHDFB, R5F101GJDFB, R5F101GKDFB, R5F101GLDFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16 HD D detail of lead end 36 25 37 A3 24 c E L Lp HE L1 (UNIT:mm) 13 48 12 1 ZE e ZD b x M S A ITEM D DIMENSIONS 7.000.20 E 7.000.20 HD 9.000.20 HE 9.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b A2 c L S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A1 0.25 0.220.05 0.145 +0.055 -0.045 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1042 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS R5F100GAANA, R5F100GCANA, R5F100GDANA, R5F100GEANA, R5F100GFANA, R5F100GGANA, R5F100GHANA, R5F100GJANA, R5F100GKANA, R5F100GLANA R5F101GAANA, R5F101GCANA, R5F101GDANA, R5F101GEANA, R5F101GFANA, R5F101GGANA, R5F101GHANA, R5F101GJANA, R5F101GKANA, R5F101GLANA <R> R5F100GADNA, R5F100GCDNA, R5F100GDDNA, R5F100GEDNA, R5F100GFDNA, R5F100GGDNA, R5F100GHDNA, R5F100GJDNA, R5F100GKDNA, R5F100GLDNA R5F101GADNA, R5F101GCDNA, R5F101GDDNA, R5F101GEDNA, R5F101GFDNA, R5F101GGDNA, R5F101GHDNA, R5F101GJDNA, R5F101GKDNA, R5F101GLDNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN48-7x7-0.50 PWQN0048KB-A P48K8-50-5B4-4 0.13 D DETAIL OF E S A PART A A S y (UNIT:mm ) S ITEM D2 A EXPOSED DIE PAD 1 12 D 7.00 0.05 E 7.00 0.05 A 0.75 0.05 b + 0.25 - 0.05 0.07 e 13 48 DIMENSIONS Lp 0.50 0.40 0.10 x 0.05 y 0.05 B E2 ITEM 37 24 36 25 Lp EXPOSED DIE PAD VARIATIONS D2 E2 MIN NOM MAX MIN NOM MAX A 5.45 5.50 5.55 5.45 5.50 5.55 e b x M S AB 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1043 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.10 52-pin products R5F100JCAFA, R5F100JDAFA, R5F100JEAFA, R5F100JFAFA, R5F100JGAFA, R5F100JHAFA, R5F100JJAFA, R5F100JKAFA, R5F100JLAFA R5F101JCAFA, R5F101JDAFA, R5F101JEAFA, R5F101JFAFA, R5F101JGAFA, R5F101JHAFA, R5F101JJAFA, R5F101JKAFA, R5F101JLAFA <R> R5F100JCDFA, R5F100JDDFA, R5F100JEDFA, R5F100JFDFA, R5F100JGDFA, R5F100JHDFA, R5F100JJDFA, R5F100JKDFA, R5F100JLDFA R5F101JCDFA, R5F101JDDFA, R5F101JEDFA, R5F101JFDFA, R5F101JGDFA, R5F101JHDFA, R5F101JJDFA, R5F101JKDFA, R5F101JLDFA 52-PIN PLASTIC LQFP (10x10) HD D 2 27 39 40 detail of lead end 26 c 1 E HE 52 L 14 1 13 e (UNIT:mm) 3 b x M A A2 y NOTE ITEM D DIMENSIONS 10.000.10 E 10.000.10 HD 12.000.20 HE 12.000.20 A 1.70 MAX. A1 0.100.05 A2 A1 1.40 b 0.320.05 c 0.145 0.055 L 0.500.15 1.Dimensions " 1" and " 2" do not include mold flash. 0 to 8 2.Dimension " 3" does not include trim offset. e 0.65 x 0.13 y 0.10 P52GB-65-GBS R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1044 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS <R> 30.11 64-pin products R5F100LCAFA, R5F100LDAFA, R5F100LEAFA, R5F100LFAFA, R5F100LGAFA, R5F100LHAFA, R5F100LJAFA, R5F100LKAFA, R5F100LLAFA R5F101LCAFA, R5F101LDAFA, R5F101LEAFA, R5F101LFAFA, R5F101LGAFA, R5F101LHAFA, R5F101LJAFA, R5F101LKAFA, R5F101LLAFA <R> R5F100LCDFA, R5F100LDDFA, R5F100LEDFA, R5F100LFDFA, R5F100LGDFA, R5F100LHDFA, R5F100LJDFA, R5F100LKDFA, R5F100LLDFA R5F101LCDFA, R5F101LDDFA, R5F101LEDFA, R5F101LFDFA, R5F101LGDFA, R5F101LHDFA, R5F101LJDFA, R5F101LKDFA, R5F101LLDFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET-2 0.51 HD D detail of lead end 48 33 49 32 A3 c E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M A2 S S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. DIMENSIONS 12.000.20 E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 S A y ITEM D A1 0.25 b 0.32 +0.08 -0.07 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD 1.125 ZE 1.125 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1045 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS R5F100LCAFB, R5F100LDAFB, R5F100LEAFB, R5F100LFAFB, R5F100LGAFB, R5F100LHAFB, R5F100LJAFB, R5F100LKAFB, R5F100LLAFB R5F101LCAFB, R5F101LDAFB, R5F101LEAFB, R5F101LFAFB, R5F101LGAFB, R5F101LHAFB, R5F101LJAFB, R5F101LKAFB, R5F101LLAFB <R> R5F100LCDFB, R5F100LDDFB, R5F100LEDFB, R5F100LFDFB, R5F100LGDFB, R5F100LHDFB, R5F100LJDFB, R5F100LKDFB, R5F100LLDFB R5F101LCDFB, R5F101LDDFB, R5F101LEDFB, R5F101LFDFB, R5F101LGDFB, R5F101LHDFB, R5F101LJDFB, R5F101LKDFB, R5F101LLDFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35 HD D detail of lead end 48 33 49 A3 32 c E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S ITEM D DIMENSIONS 10.000.20 E 10.000.20 HD 12.000.20 HE 12.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 b A A2 c L S y S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. A1 0.25 0.220.05 0.145 +0.055 -0.045 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1046 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS R5F100LCABG, R5F100LDABG, R5F100LEABG, R5F100LFABG, R5F100LGABG, R5F100LHABG, R5F100LJABG R5F101LCABG, R5F101LDABG, R5F101LEABG, R5F101LFABG, R5F101LGABG, R5F101LHABG, R5F101LJABG <R> R5F100LCDBG, R5F100LDDBG, R5F100LEDBG, R5F100LFDBG, R5F100LGDBG, R5F100LHDBG, R5F100LJDBG R5F101LCDBG, R5F101LDDBG, R5F101LEDBG, R5F101LFDBG, R5F101LGDBG, R5F101LHDBG, R5F101LJDBG JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-VFBGA64-4x4-0.40 PVBG0064LA-A P64F1-40-AA2-2 0.03 w D S A ZE ZD A 8 7 6 B 5 4 E 3 2 1 H G F E D C B A INDEX MARK w S B (UNIT:mm) A y1 A2 S S y e S b x M A1 S A B INDEX MARK ITEM D DIMENSIONS E 4.000.10 w 0.15 4.000.10 A 0.890.10 A1 0.20 0.05 A2 0.69 e 0.40 b 0.25 0.05 x 0.05 y 0.08 y1 0.20 ZD 0.60 ZE 0.60 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1047 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.12 80-pin products R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA <R> R5F100MFDFA, R5F100MGDFA, R5F100MHDFA, R5F100MJDFA, R5F100MKDFA, R5F100MLDFA R5F101MFDFA, R5F101MGDFA, R5F101MHDFA, R5F101MJDFA, R5F101MKDFA, R5F101MLDFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP80-14x14-0.65 PLQP0080JB-A P80GC-65-UBT-1 0.69 HD D detail of lead end 60 61 A3 41 40 c E L Lp HE L1 (UNIT:mm) 80 1 21 20 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.13 mm of its true position at maximum material condition. A1 DIMENSIONS 14.000.20 E 14.000.20 HD 17.200.20 HE 17.200.20 A 1.70 MAX. A1 0.1250.075 A2 1.400.05 A3 A2 y ITEM D 0.25 b 0.320.06 c 0.17 +0.03 -0.06 L 0.80 Lp 0.8860.15 L1 1.600.20 3 +5 -3 e 0.65 x 0.13 y 0.10 ZD 0.825 ZE 0.825 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1048 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB, R5F100MKAFB, R5F100MLAFB R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB, R5F101MKAFB, R5F101MLAFB <R> R5F100MFDFB, R5F100MGDFB, R5F100MHDFB, R5F100MJDFB, R5F100MKDFB, R5F100MLDFB R5F101MFDFB, R5F101MGDFB, R5F101MHDFB, R5F101MJDFB, R5F101MKDFB, R5F101MLDFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP80-12x12-0.50 PLQP0080KE-A P80GK-50-8EU-2 0.53 HD D detail of lead end 41 60 61 A3 40 c E L Lp HE L1 (UNIT:mm) 21 80 1 20 ZE e ZD b x M S E 12.000.20 HD 14.000.20 HE 14.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 c L A2 S S DIMENSIONS 12.000.20 A3 b A y ITEM D A1 0.25 0.220.05 0.145 +0.055 -0.045 0.50 Lp 0.600.15 L1 1.000.20 3 +5 -3 e 0.50 x 0.08 y 0.08 ZD 1.25 ZE 1.25 NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1049 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.13 100-pin products R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB, R5F100PKAFB, R5F100PLAFB R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB, R5F101PKAFB, R5F101PLAFB <R> R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB, R5F100PKDFB, R5F100PLDFB R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB, R5F101PKDFB, R5F101PLDFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP100-14x14-0.50 PLQP0100KE-A P100GC-50-GBR-1 0.69 HD D detail of lead end A L1 75 76 51 50 A3 c B L E HE Lp (UNIT:mm) 26 25 100 1 ZE e b ZD x M S AB A A2 ITEM D DIMENSIONS 14.000.20 E 14.000.20 HD 16.000.20 HE 16.000.20 A 1.60 MAX. A1 0.100.05 A2 1.40 0.05 A3 0.25 b 0.22 0.05 c 0.145 + 0.055 0.045 L 0.50 Lp 0.600.15 L1 e 1.000.20 3 + 5 3 0.50 x 0.08 y 0.08 ZD 1.00 ZE 1.00 S y S A1 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1050 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA, R5F100PKAFA, R5F100PLAFA R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA, R5F101PKAFA, R5F101PLAFA <R> R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA, R5F100PKDFA, R5F100PLDFA R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA, R5F101PKDFA, R5F101PLDFA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LQFP100-14x20-0.65 PLQP0100JC-A P100GF-65-GBN-1 0.92 HD D detail of lead end A A3 51 50 80 81 c B E HE L Lp 100 1 L1 31 30 (UNIT:mm) ZE e ZD b x M S AB A A2 S ITEM D DIMENSIONS 20.00 0.20 E 14.00 0.20 HD 22.00 0.20 HE 16.00 0.20 A 1.60 MAX. A1 0.10 0.05 A2 1.40 0.05 A3 0.25 + 0.08 0.32 0.07 0.145 + 0.055 0.045 0.50 b c y S A1 L Lp 0.60 0.15 L1 e 1.00 0.20 3 +5 3 0.65 x 0.13 y 0.10 ZD 0.575 ZE 0.825 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1051 RL78/G13 CHAPTER 30 PACKAGE DRAWINGS 30.14 128-pin products R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB <R> R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP128-14x20-0.50 PLQP0128KD-A P128GF-50-GBP-1 0.92 HD detail of lead end D A A3 102 103 65 64 c B E L HE Lp L1 128 1 39 38 (UNIT:mm) ZE e ZD b x M S AB A A2 ITEM D DIMENSIONS 20.000.20 E 14.000.20 HD 22.000.20 HE 16.000.20 A 1.60 MAX. A1 0.100.05 A2 1.400.05 A3 S y S A1 0.25 b 0.22 0.05 c 0.145 +0.055 -0.045 L 0.50 Lp 0.600.15 L1 e 1.000.20 3 +5 -3 0.50 x 0.08 y 0.08 ZD 0.75 ZE 0.75 2012 Renesas Electronics Corporation. All rights reserved. R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1052 RL78/G13 APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/9) Page Description Though out Classification Renamed interval timer (unit) to 12-bit interval timer (b) Addition of pin name of the peripheral I/O redirection function (c) Renamed VLVI, VLVIH, VLVIL to VLVD, VLVDH, VLVDL (LVD detection voltage) (b) Renamed interrupt source of RAM parity error (RAMTOP) to RPE (b) Renamed fEXS to fEXT (b) CHAPTER 1 OUTLINE p.1 Addition of 1.1 Features (c) p.3 to 6 Modification of 1.2 Ordering Information (c) p.7 Addition of Figure 1-1. Part Number, Memory Size, and Package of RL78/G13 (c) p.19 Modification of 1.3.11 64-pin products (d) p.40 to 45 Addition and Modification of description in 1.6 Outline ofvv Functions (a) CHAPTER 2 PIN FUNCTIONS p.47 to 75 p.76 to 82 Modification of 2.1 Port Function (c) Modification of description in 2.2 Functions other than port pins (Deletion of Description of (c) Port Function) p.83 Addition of remark to 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins (c) p.84 Change of Table 2-3. Connection of Unused Pins (128-pin products) (2/4) (c) CHAPTER 3 CPU ARCHITECTURE p.90, 91, Addition of note 1 to Figures 3-1, 3-2, 3-5 to 3-7, 3-9 (c) p.90 to 99 Addition of caution to Figures 3-1 to 3-10 (c) p.92, 93, 97, Modification of note in Figures 3-3, 3-4, 3-8, 3-10 (c) Addition of remark to Table 3-1. Correspondence Between Address Values and Block (c) 94 to 96, 98 99 p.101 to 104 Numbers in Flash Memory p.110 Modification of caution 2 in 3.1.3 Internal data memory space (c) p.112, 113, Addition of note 1 to Figures 3-12, 3-13, 3-16 to 3-18, 3-20 (c) p.112 to 121 Addition of caution to Figures 3-12 to 3-21 (c) p.114, 115, Addition of note 1 to Figures 3-14, 3-15, 3-19, 3-21 (c) p.123 Modification of caution 3 in 3.2.1 (3) Stack pointer (SP) (c) p.124 Modification of caution 2 in 3.2.2 General-purpose registers (c) 116 to 118, 120 119, 121 Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1053 RL78/G13 APPENDIX A REVISION HISTORY (2/9) Page Description Classification CHAPTER 4 PORT FUNCTIONS p.155 Modification of 4.1 Port Functions p.160, 162 to 164, Modification of block diagrams (c) (a, c) 168 to 171, 173, 186, 187, 192 to 197, 204, 205, 207, 209 to 212, 216, 223, 224, 232, 235, 236, 238 p.174 Addition of description to 4.2.3 Port 2 (c) p.240 Addition of description to 4.2.16 Port 15 (c) p.242 Addition of caution to 4.3 Registers Controlling Port Function (c) p.252 Modification of Figure 4-66. Format of Port Register (128-pin products) (c) p.253 Modification of description and addition of caution to 4.3 (3) Pull-up resistor option (c) registers (PUxx) p.255 Addition of 4.3 (5) Port output mode registers (POMxx) (b) p.256 Addition of cautions 1 and 2 to Figure 4-70. Format of Port Mode Control Register (b) Addition of caution 1 to Figure 4-71. Format of A/D Port Configuration Register (b) p.257 (ADPC) p.258 Modification of description in 4.3 (8) Peripheral I/O redirection register (PIOR) (c) p.260 Addition of remark to 4.3 (9) Global digital input disable register (GDIDIS) (c) p.261 Modification of description in 4.4.1 (2) Input mode and 4.4.3 (2) Input mode (b) p.262, 263 Addition of remark to 4.4.4 (1) (a) Use as 1.8 V, 2.5 V, 3 V input port and (b) Use as 1.8 (c) V, 2.5 V, 3 V output port Addition of description to 4.4.4 (2) Setting procedure when using I/O pins of IIC00, p.263 (c) IIC01, IIC10, IIC20, IIC30, and IIC31 functions Addition of caution to 4.5 Settings of Port Mode Register, and Output Latch When P.264 (c) Using Alternate Function p.264, 265 Modification of Table 4-22. Settings of Port Register When Using Alternate Function (c) p.271 Addition of 4.6.2 Notes on specifying the pin settings (c) CHAPTER 5 CLOCK GENERATOR p.272 Addition of 5.1 (1) <2> High-speed on-chip oscillator (b) p.275 Modification of Figure 5-1. Block Diagram of Clock Generator (b) Modification of caution 1 and addition of cautions 4 to 6 to Figure 5-2. Format of Clock (c) p.277 Operation Mode Control Register (CMC) Modification of caution 3 in Figure 5-9. Format of High-speed On-chip Oscillator p.289 (a) Frequency Select Register (HOCODIV) Modification of note 3 in Figure 5-14. Clock Generator Operation When Power Supply p.297 (c) Voltage Is Turned On Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1054 RL78/G13 APPENDIX A REVISION HISTORY (3/9) Page Description Classification p.299 Addition of description to 5.6.2 Example of setting X1 oscillation clock (c) p.301 Addition of description to Figure 5-15. CPU Clock Status Transition Diagram (c) p.302 Modification of Table 5-3. CPU Clock Transition and SFR Register Setting Examples (c) p.307 Modification and deletion of description in Table 5-4. Changing CPU Clock (c) p.309 Modification of remark 2 to 5.6.6 Time required for switchover of CPU clock and (b) system clock p.311 to 313 Addition of 5.7 Recommended Oscillator Constants (c) CHAPTER 6 TIMER ARRAY UNIT p.317 Modification of description in 6.1.1 (7) Delay counter (a) p.318 Modification of caution in 6.1.2 (3) Multiple PWM (Pulse Width Modulation) output (c) Modification of Figure 6-2. Internal Block Diagram of Channels of Timer Array Unit 0, (a) p.323 2, 4, 6 p.323 to 325 p.326 Addition of Figures 6-3 to 6-6 (c) Modification of Table 6-3. Timer Count Register mn (TCRmn) Read Value in Various (c) Operation Modes p.329 p.331 Modification of caution 1 in Figure 6-10. Format of Peripheral Enable Register 0 (PER0) (c) Modification of note and remark 2 and addition of caution 2 to Figure 6-11. Format of (c) Timer Clock Select register m (TPSm) p.334 to 337 Modification of Figure 6-12. Format of Timer Mode Register mn (TMRmn) (a) p.342 Addition of caution to Figure 6-17. Format of Timer Input Select register 0 (TIS0) (b) p.343 Modification of description in Figure 6-18. Format of Timer Output Enable register m (TOEm) (c) p.351 Modification of description in 6.3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, (c) PM1, PM3, PM4, PM6, PM10, PM14) Modification of description in 6.5.1 (1) When operation clock (fMCK) specified by the p.356 (c) CKSmn0 and CKSmn1 bits is selected (CCSmn = 0) Modification of description in Table 6-6. Operations from Count Operation Enabled p.358 (c) State to Timer count Register mn (TCRmn) Count Start p.359 Addition of title and remark to 6.5.3 Operation of counter (c) p.361 Modification of description, remark and addition note to Figure 6-29. Start Timing (In (a) Capture Mode : Input Pulse Interval Measurement) Modification of remark in Figure 6-31. Operation Timing (In Capture & One-count p.363 (c) Mode : High-level Width Measurement) p.365 Modification of description in 6.6.2 TOmn Pin Output Setting (c) p.367 to 369 Modification of Figures 6-34 to 6-36 (c) p.375, 381, 390, 394, Modification of description in Figures 6-43, 6-47, 6-55, 6-59, 6-63, 6-68, 6-78 Example (a) 398, 405, 420 of Set Contents of Registers p.379, 384, 393, 396, Modification of Figures 6-45, 6-49, 6-57, 6-61, 6-65 Block Diagram (b) Modification of Figures 6-48, 6-52, 6-56, 6-60, 6-64, 6-69, 6-79 Operation Procedure (c) Modification of Figure 6-66. Example of Basic Timing of Operation as One-Shot (a) 402 p.383, 387, 391, 395, 400, 407, 421 p.403 Pulse Output Function p.415, 416, 420 Remark Modification of remark in 6.8.3 Operation as multiple PWM output function (a) "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1055 RL78/G13 APPENDIX A REVISION HISTORY (4/9) Page Description Classification CHAPTER 7 REAL-TIME CLOCK p.432, 433, Modification of description in 7.3 (5) to 7.3 (11) (c) Modification of 7.4.2 Shifting to HALT/STOP mode after starting operation (c) 435 to 437 p.442 CHAPTER 8 INTERVAL TIMER p.453 Addition of caution 3 to Figure 8-4. Format of Interval Timer Control Register (ITMC) (c) p.454 Modification of Figure 8-5. 12-bit Interval Timer Operation Timing (ITMCMP11 to ITMCMP0 = (a) 0FFH, count clock: fSUB = 32.768 kHz) CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER p.460 Addition of 9.5 Cautions of clock output/buzzer output controller (c) CHAPTER 10 WATCHDOG TIMER Modification of description in 10.1 Functions of Watchdog Timer, 10.4.3 Setting window open p.461, 467 (b) period of watchdog timer, 10.4.4 Setting watchdog timer interval interrupt CHAPTER 11 A/D CONVERTER p.469 Modification of Figure 11-1. Block Diagram of A/D Converter (a) p.474 Deletion of note 3 and addition of cautions 1 and 2 to Figure 11-3. Format of A/D Converter (c) Mode Register 0 (ADM0) p.476, 477 Modification of description and addition of note 2 and caution 4 to Figure 11-4. Timing Chart (b) When A/D Voltage Comparator Is Used p.478 to 481 Addition of description to Table 11-3. A/D Conversion Time Selection (c) p.482, 483 Modification of cautions 2, 3 in Figure 11-6. Format of A/D Converter Mode Register 1 (ADM1) (c) Modification of description and addition of note, cautions 2, 3 and remark to Figure 11-7. (c) p.483, 484 Format of A/D Converter Mode Register 2 (ADM2) Addition of note to 11.3 (5) 10-bit A/D conversion result register (ADCR), and 11.3 (6) 8-bit p.485 (c) A/D conversion result register (ADCRH) p.486, 487 Addition of note 3 and cautions 9, 10 to Figure 11-11. Format of Analog Input Channel (c) Specification Register (ADS) p.489 Addition of caution to 11. 3 (10) A/D test register (ADTES) (c) p.490 Addition of caution 3 to 11. 3 (11) A/D port configuration register (ADPC) (c) Addition of caution to 11.3 (12) Port mode control registers 0, 3, 10, 11, 12, 14 (PMC0, PMC3, (c) p.491 PMC10, PMC11, PMC12, PMC14) Modification of description and addition of Caution to 11. 3 (13) Port mode register 0, 2, 3, 10, p.492 (c) 11, 12, 14, 15 (PM0, PM2, PM3, PM10, PM11, PM12, PM14, PM15) p.494 Addition of note 1 to 11.4 A/D Converter Conversion Operations (c) p.509 to 513 Modification of Figures 11-32 to 11-36 (c) p.514, 515 Modification of description in 11.8 SNOOZE Mode Function (c) p.519 Addition of caution to 11.10 (2) Input range of ANI0 to ANI14 and ANI16 to ANI26 pins (c) p.520 Modification of description in 11.10 (5) Analog input (ANIn) pins (c) p.522 Modification of value in Table 11-6. Resistance and Capacitance Values of Equivalent Circuit (c) (Reference Values) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1056 RL78/G13 APPENDIX A REVISION HISTORY (5/9) Page Description Classification CHAPTER 12 SERIAL ARRAY UNIT Addition of note 1 to 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, p.525 (c) CSI21, CSI30, CSI31) p.526 Addition of note to 12.1.2 UART (UART0 to UART3) (c) p.530, 531 Modification of Figures 12-1 and 12-2 block diagram of the serial array unit 0, 1 (a) p.532 Modification of description in 12.2 (2) Lower 8/9 bits of the serial data register mn (c) (SDRmn) Modification of caution 1 in Figure 12-5. Format of Peripheral Enable Register 0 p.535 (c) (PER0) Modification of description in Figure 12-8. Format of Serial Communication Operation p.540 (c) Setting Register mn (SCRmn) Modification of description in 12.3 (5) Higher 7 bits of the serial data register mn p.542 (a) (SDRmn) Addition of note and caution 2 to Figure 12-12. Format of Serial Channel Start p.547 (c) Register m (SSm) p.548 p.553 Addition of note to Figure 12-13. Format of Serial Channel Stop Register m (STm) (c) Modification of description and addition of caution to Figure 12-18. Format of Serial (c) Standby Control Register m (SSCm) Modification of description in 12.3 (18) Port output mode registers 0, 1, 4, 5, 7 to 9, 14 p.557 (c) (POM0, POM1, POM4, POM5, POM7 to POM9, POM14) Addition of description to 12.3 (19) Port mode registers 0, 1, 3 to 5, 7 to 9, and 14 (PM0, p.558 (a) PM1, PM3 to PM5, PM7 to PM9, and PM14) Modification of caution 1 in Figure 12-24. Peripheral Enable Register 0 (PER0) Setting p.561 (a) When Stopping the Operation by Units Modification of note 1 in 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, p.563 (c) CSI11, CSI20, CSI21, CSI30, CSI31) Communication p.567, 577, 586, Modification of description in Figure 12-26, 34, 42, 50, 58, 64, 77, 85, 105, 109, 112 596, 606, 613, 633, (Example of Contents of Registers) (a) 643, 673, 679, 683 p.570, 571, 579, Modification of Figure 12-28, 29, 36, 37, 44, 45, 52, 53, 60, 61, 66, 67, 79, 80, 82, 84, 87, 580, 589, 590, 599, 88, 90, 93, 95, 106, 108, 111, 114, 116 (flow chart) (a) 600, 608, 609, 616, 617, 636, 637, 639, 641, 645, 646, 648, 651, 653, 675, 677, 681, 686, 687 p.595, 605, 612 Addition of description of note to 12.5.4 Slave transmission, 12.5.5 Slave reception, (c) 12.5.6 Slave transmission/reception p.622 Modification of description in 12.5.7 SNOOZE mode function (c) p.622, 624 Modification of caution in Figures 12-72 and 12-74 (c) p.627 Modification of description in Table 12-2. Selection of Operation Clock For 3-Wire (c) Serial I/O Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1057 RL78/G13 APPENDIX A REVISION HISTORY (6/9) Page Description Classification p.631 Addition of description to 12.6 Operation of UART (UART0 to UART3) Communication (c) p.632, 642 Modification of description in 12.6.1 UART transmission and 12.6.2 UART reception (a) p.645 Modification of caution in Figure 12-86. Initial Setting Procedure for UART Reception (c) p.649 Addition of description and modification of caution to 12.6.3 SNOOZE mode function (c) Modification of note and caution in Figure 12-91. Timing Chart of SNOOZE Mode Operation (c) p.649 (Normal operation mode) Modification of caution in Figure 12-92. Timing Chart of SNOOZE Mode Operation p.650 (c) (Abnormal Operation <1>) Modification of note 1 and caution 1 in Figure 12-94. Timing Chart of SNOOZE Mode p.652 (c) Operation (Abnormal Operation <2>) p.656 Modification of description in Table 12-3. Selection of Operation Clock For UART (c) p.660, 663, Modification of description and note in 12.7.1 LIN transmission and 12.7.2 LIN reception (c) p.661 Modification of Figure 12-99. Master Transmission Operation of LIN (c) p.662 Modification of Figure 12-100. Flowchart for LIN Transmission (c) p.664 Modification of Figure 12-101. Reception Operation of LIN (c) p.665 Modification of Figure 12-102. Flowchart for LIN Reception (c) p.672, 678, Modification of description in 12.8.1 Address field transmission, 12.8.2 Data transmission, (c) 682 and 12.8.3 Data reception p.688 Addition of caution of description to 12.8.5 Calculating transfer rate 668 2 (c) p.689 Modification of description in example of setting an I C transfer rate (a) p.690 Modification of description in Figure 12-117. Processing Procedure in Case of Parity Error (c) 2 (ACK error) in Simplified I C Mode CHAPTER 13 SERIAL INTERFACE IICA p.702 Modification of description in Figure 13-6. Format of IICA Control Register n0 (IICCTLn0) (4/4) (c) p.708 Modification of Figure 13-9. Format of IICA Control Register n1 (IICCTLn1) (2/2) (c) p.709 Modification of 13.3 (6) IICA low-level width setting register n (IICWLn) (c) p.725 Modification of 13.5.13 Wakeup function (c) p.734, 735, Modification of Figure 13-28, 13-29, 13-30 (a) p.747 Modification of 13.5.17 (2) (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (c) p.751 Modification of 13.5.17 (3) (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (c) 739 CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR p.777 Modification of Figure 14-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator (a) p.779 Modification of caution 1 to 14. 2 (2) Multiplication/division data register B (MDBL, MDBH) (c) p.780 Modification of caution 2 to 14. 2 (3) Multiplication/division data register C (MDCL, MDCH) (c) p.782 Modification of description in Figure 14-5. Format of Multiplication/Division Control Register (a, c) (MDUC) p.784 Modification of description in 14.4.1 Multiplication (unsigned) operation, and modification of (a) value in Figure 14-6. Timing Diagram of Multiplication (Unsigned) Operation (2 x 3 = 6) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1058 RL78/G13 APPENDIX A REVISION HISTORY (7/9) Page p.785 Description Classification Modification of description in 14.4.2 Multiplication (signed) operation, and modification of value (a) in Figure 14-7. Timing Diagram of Multiplication (Signed) Operation (-2 x 32767 = -65534) p.786 p.787 Modification of description in 14.4.3 Multiply-accumulation (unsigned) operation (c) Modification of value in Figure 14-8. Timing Diagram of Multiply-Accumulation (Unsigned) (c) Operation p.788 p.789 Addition of description to 14.4.4 Multiply-accumulation (signed) operation (c) Modification of value in Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) (c) Operation p.790 Modification of description in 14.4.5 Division operation (c) p.791 Modification of value in Figure 14-10. Timing Diagram of Division Operation (Example: 35 / 6 (c) = 5, Remainder 5) CHAPTER 16 INTERRUPT FUNCTION p.814 p.826 Addition of description (c) Deletion of caution 2 in Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, (c) IF1L, IF1H, IF2L, IF2H, IF3L) (128-pin) p.832 Addition of remark 1 to Table 16-3. Ports Corresponding to EGPn and EGNn bits (b) p.834 Modification of value and addition of note in Table 16-4. Time from Generation of Maskable (b) Interrupt Until Servicing Modification of Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) and p.836 (c) Figure 16-9. Interrupt Request Acknowledgment Timing (Maximum Time) Modification of Table 16-5. Relationship Between Interrupt Requests Enabled for Multiple p.838 (c) Interrupt Servicing During Interrupt Servicing p.841 Deletion of caution in 16.4.4 Interrupt request hold (c) CHAPTER 17 KEY INTERRUPT FUNCTION Addition of caution 1 and modification of description and caution 2 in Figure 17-2. Format of p.844 (c) Key Return Mode Register (KRM) CHAPTER 18 STANDBY FUNCTION p.850, 851 Modification of Table 18-1. Operating Statuses in HALT Mode (a) p.852 Addition of note 1 and modification of note 2 in Figure 18-3. HALT Mode Release by Interrupt (c) Request Generation p.853 Modification of description and note in Figure 18-4. HALT Mode Release by Reset (c) p.855 Modification of description in Table 18-2. Operating Statuses in STOP Mode (c) p.856, 857 Modification of note in Figure 18-5. STOP Mode Release by Interrupt Request Generation (c) p.858 Modification of note in Figure 18-6. STOP Mode Release by Reset (c) p.859 Modification of description in 18.2.3 SNOOZE mode (c) p.860 Modification of description in Table 18-3. Operating Statuses in SNOOZE Mode (c) CHAPTER 19 RESET FUNCTION p.863, 864 Modification of Figures 19-2 to 19-4 (c) p.865 Modification of description in Table 19-1. Operation Statuses During Reset Period (c) p.870 Modification of note 2 in Table 19-2. Hardware Statuses After Reset Acknowledgment (c) p.871 Modification of caution 3 to Figure 19-5. Format of Reset Control Flag Register (RESF) (c) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1059 RL78/G13 APPENDIX A REVISION HISTORY (8/9) Page Description Classification CHAPTER 20 POWER-ON-RESET CIRCUIT p.875, 876 Modification of description and notes in Figure 20-2. Timing of Generation of Internal Reset (c) Signal by Power-on-reset Circuit and Voltage Detector CHAPTER 21 VOLTAGE DETECTOR p.880 Modification of Figure 21-1. Block Diagram of Voltage Detector (a) p.881 Modification of description in Figure 21-2. Format of Voltage Detection Register (LVIM) (a) p.883, 884 Addition of figure to Table 21-1. LVD Operation Mode and Detection Voltage Settings for (a) User Option Byte (000C1H) p.886, 888, Modification of Figures 21-4 to 21-6 (b) Addition of description and Figure 21-7, 21-8 to 21.4.3 When used as interrupt and reset mode (c) 890, 892 p.893, 894 CHAPTER 22 SAFETY FUNCTIONS p.897 Modification of remark in 22.1 Overview of Safety Functions (c) p.898 Addition of description and caution to 22.3.1 Flash memory CRC operation function (high- (c) speed CRC) Modification of Figure 22-3. Flowchart of Flash Memory CRC Operation Function (High- p.901 (b) speed CRC) p.902 Addition of description and caution to 22.3.2 CRC operation function (general-purpose CRC) (c) p.903 Modification of Figure 22-6. CRC Operation Function (General-Purpose CRC) (a) p.904 Modification of caution in Figure 22-7. Format of RAM Parity Error Control Register (c) (RPECTL) p.907 Modification of Figure 22-10. Invalid access detection area (a) p.908 Addition of remark to Figure 22-11. Format of Invalid Memory Access Detection Control (c) Register (IAWCTL) p.911 to 914 Addition of description to 22.3.8 A/D test function (c) CHAPTER 23 REGULATOR p.915 Addition of Figure (move from 2.2 Description to Pin Function (preceding editions)) (c) CHAPTER 24 OPTION BYTE p.918 Modification of description in Figure 24-1. Format of User Option Byte (000C0H/010C0H) (b) p.919, 920 Modification of Figure 24-2. Format of User Option Byte (000C1H/010C1H) (a) CHAPTER 25 FLASH MEMORY Modification of note in Table 25-1. Wiring Between RL78/G13 and Dedicated Flash Memory p.926 (c) Programmer p.927, 928 Modification of description in 25.1.1 Programming Environment and modification of Notes in (a) 25.1.2 Communication Mode p.928 Addition of description to 25.2 Writing to Flash Memory by Using External Device (that (c) Incorporates UART) p.929 Modification of note in 25.2.2 Communication Mode (c) p.930 Addition of remark to 25.3 Connection of Pins on Board (c) p.933 Modification of description and addition of remark to 25.4.1 Data flash overview (c) p.936 Modification of Figure 25-8. Setting of Flash Memory Programming Mode (c) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documentsd R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1060 RL78/G13 APPENDIX A REVISION HISTORY (9/9) Page Description Modification of Table 25-5. Programming Modes and Voltages at Which Data Can Be p.937 Classification (c) Written, Erased, or Verified p.939 Modification of description in Table 25-10. Example of Signature Data (a) p.940 Addition of description and caution to 25.6 Security Settings (a) p.942 Addition of caution 3 to 25.7 Flash Memory Programming by Self-Programming and (c) modification of value in Table 25-13. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified CHAPTER 28 INSTRUCTION SET p.966 Modification of Flag status (a) CHAPTER 29 ELECTRICAL SPECIFICATIONS Addition of cautions 2, 3 to CHAPTER 29 ELECTRICAL SPECIFICATIONS (deletion of p.974 (c) Pins Mounted According to Product) p.975 p.977 Addition of description, note 3, and remark 2 to 29.1 Absolute Maximum Ratings (c) Modification of 29.2 Oscillator Characteristics (Recommended Oscillator Constants move (c) to 5.7 Resonator and Oscillator Constants) p.978 Addition of note 2 to 29.2.2 On-chip oscillator characteristics (c) p.979 Addition of note 4 to 29.3.1 Pin characteristics (c) p.985, 987, 989, Modification of note in 29.3.2 Supply current characteristics (c) Addition of note to 29.3.2 Supply current characteristics (c) Deletion of target, and change to formally standard of 29.3.2 (3) 128-pin products, and (b) 991, 993, 995 p.987, 991, 995 p.992, 994 flash ROM: 384 to 512 KB of 44- to 100-pin products p.996 Addition of description and note 7 to 29.3.2 (4) Common to RL78/G13 all products (c) p.998, 999 Addition of figure to 29.4 AC Characteristics (c) p.1003, 1006 Modification of caution in 29.5.1 Serial array unit (a) p.1007, 1009, Deletion of remark to 29.5.1 Serial array unit (c) Modification of value in 29.5.1 (7) Communication at different potential (2.5 V, 3 V) (c) 1012, 1013, 1015, 1018, 1022 p.1011 (fMCK/2) (CSI mode) (master mode, SCKp... internal clock output, coresponting CSI00 only) Addition of description and deletion of value in 29.5.1 (9) Communication at different p.1017 (c) potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) p.1023 Addition of value to 29.5.2 Serial interface IICA (c) p.1024 to 1028 Addition of description to 29.6.1 A/D converter characteristics and 29.6.2 Temperature (c) sensor characteristics p.1030 Modification of description in 29.6.4 LVD circuit characteristics (c) p.1033 Modification of description in 29.9 Timing Specs for Switching Flash Memory Programming (c) Modes CHAPTER 30 PACKAGE DRAWINGS p.1034 to 1052 Addition of the products of industrial application (d) p.1045 Modification of description in 30.11 64-pin products (d) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documentsd R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1061 RL78/G13 APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/8) Edition Ver.0.07 Description Chapter Change of 1.1 Features CHAPTER 1 PIN Change of 1.6 Outline of Functions FUNCTIONS Change of 2.1 (5) 128-pin products CHAPTER 2 PIN Change of 2.1.12 80-pin products FUNCTIONS Change of 2.1.13 100-pin products Change of 2.1.14 128-pin products Change of 2.1.15 Pins for each product (pins other than port pins) (6/6) Change of caution in 2.2.5 (2) Control mode Change of 2.2.17 VDD, EVDD0, EVDD1, VSS, EVSS0, EVSS1 Change of Type 37-C in Figure 2-1. Pin I/O Circuit List (1/2) Change of Figure 3-1 to Figure 3-10 CHAPTER 3 CPU Change of description of 3.1.2 Mirror area ARCHITECTURE Change of Figure 3-11. Format of Configuration of Processor Mode Control Register (PMC) Change of caution in 3.1.3 Internal data memory space Change of Figure 3-12 to Figure 3-21 Change of caution in 3.2.1 (3) Stack pointer (SP) Change of caution in 3.2.2 General-purpose registers Modification of Table 3-1 Set Values of Internal Memory Size Switching Register (IMS) (78K0/KB2, and 38-pin products and 44-pin products of the 78K0/KC2) and Table 3-2 Set Values of Internal Memory Size Switching Register (IMS) and Internal Expansion RAM Size Switching Register (IXS) (48-pin products of the 78K0/KC2, 78K0/KD2, 78K0/KE2, and 78K0/KF2) CHAPTER 3 CPU ARCHITECTURE Addition of description in 3.2.1 (2) Program status word (PSW) Modification of Notes 2 to 4 in Table 3-8 Special Function Register List (5/5) Change of Table 4-1 (5) 128-pin products CHAPTER 4 PORT Deletion of note and caution 3 in 4.2.5 Port 4 FUNCTIONS Change of Figure 4-56. Block Diagram of P137 Change of Table 4-7. Settings of Port Mode Register, and Output Latch When Using Alternate Function (1/4) Change of 5.1 (2) Subsystem clock Change of Figure 5-1. Block Diagram of Clock Generator CHAPTER 5 CLOCK GENERATOR Change of Figure 5-10. Format of Internal High-Speed Oscillator Trimming Register (HIOTRM) Change of Figure 5-15. CPU Clock Status Transition Diagram R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1062 RL78/G13 APPENDIX A REVISION HISTORY (2/8) Edition Ver.0.07 Description Change of note 2 in Figure 6-8. Format of Timer Mode Register mn (TMRmn) (4/4) Chapter CHAPTER 6 TIMER ARRAY UNIT Change of 6. 3 (6) Timer channel start register m (TSm) Change of Figure 6-42. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Change of Figure 6-46. Operation Procedure When External Event Counter Function Is Used Change of Figure 6-50. Operation Procedure When Frequency Divider Function Is Used Change of Figure 6-62. Operation Procedure When Delay Counter Function Is Used Change of Figure 6-67. Operation Procedure of One-Shot Pulse Output Function (2/2) Change of Figure 6-72. Operation Procedure When PWM Function Is Used (2/2) Change of Figure 6-77. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Addition of cautions to Figure 19-5. Format of Reset Control Flag Register CHAPTER 19 RESET (RESF) FUNCTION Addition of caution to Figure 22-6. Format of RAM Parity Error Control Register CHAPTER 22 (RPECTL) SAFETY FUNCTIONS Change of Table 25-1. Wiring Between RL78/G13 and Dedicated Flash Memory Programmer CHAPTER 25 FLASH MEMORY Change of Figure 25-2. Communication with Dedicated Flash Memory Programmer Change of Table 25-2. Pin Connection Change of description of 25.4.1 Data flash overview Change of description of 25.5.2 Flash memory programming mode Change of Table 25-7. Flash Memory Control Commands Addition of caution to 25.7 Flash Memory Programming by Self-Programming Change of 29.10 Timing Specs for Switching Modes CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET) Ver.1.00 Change the internal high-speed oscillator to high-speed on-chip oscillator Throughout Change the internal low-speed oscillator to low-speed on-chip oscillator Deletion of target in ELECTRICAL SPECIFICATIONS Expose the function for peripheral I/O redirection register (PIOR) CHAPTER 1 OUTLINE Change of note 1 to note 3 Change of note 1 Expose the function for peripheral I/O redirection register (PIOR) Change of 2.1.15 Pins for each product (pins other than port pins) CHAPTER 2 PIN FUNCTIONS Addition of description for digital I/O/analog input to 2.2 Description of Pin Functions Change of description for pull-up resistor option register in 2.2 Description of Pin Functions Addition of remark to 2.2.17 (2) VSS, EVSS0, EVSS1 Change of description in 2.2.19 REGC Addition of remark 3 to Table 2-3. Connection of Unused Pins (128-pin products) (2/4) Change of Figure 2-1. Pin I/O Circuit List R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1063 RL78/G13 APPENDIX A REVISION HISTORY (3/8) Edition Ver.1.00 Description Change of Figure 3-1 to Figure 3-3 Change of note 1 in Figure 3-3, Figure 3-4, Figure 3-8, Figure 3-10 Chapter CHAPTER 3 CPU ARCHITECTURE Change of Table 3-3. Vector Table Change of description in 3.1.2 Mirror area Change of caution 2 in 3.1.3 Internal data memory space Change of Figure 3-12 to Figure 3-14 Change of note 1 in Figure 3-14, Figure 3-15, Figure 3-19, Figure 3-21 Change of caution 3 in 3.2.1 (3) Stack pointer (SP) Change of caution 2 in 3.2.2 General-purpose registers Change and addition of note in Table 3-6. Extended SFR (2nd SFR) List (2/8) Change of Table 3-6. Extended SFR (2nd SFR) List (7/8) Change of Figure 3-31. Outline of Table Indirect Addressing Addition of Table 4-x. Settings of Registers When Using Port x Change of Block Diagram in 4.2 Port Configuration to be corresponded to 128-pin products CHAPTER 4 PORT FUNCTIONS Change of description for Digital I/O/analog input in 4.2 Port Configuration Change of description for reset signal generation in 4.2 Port Configuration Change of Figure 4-10. Block Diagram of P13 Change of Figure 4-15. Block Diagram of P20 to P27 Change of Figure 4-23. Block Diagram of P43, P44 Change of Figure 4-25. Block Diagram of P46 Change of Figure 4-26. Block Diagram of P47 Change of Figure 4-52. Block Diagram of P121 and P122 Change of Figure 4-53. Block Diagram of P123 and P124 Change of description in 4.2.14 Port 13 Change of Figure 4-64. Block Diagram of P150 to P156 Change of Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (20-pin products to 64-pin products) Change of Table 4-22. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits mounted on each product (80-pin products to 128-pin products) (3/4) Change of Figure 4-70. Format of Port Mode Control Register Change of cautions 1 and 2 in Figure 4-72. Format of Peripheral I/O Redirection Register (PIOR) Change of description in 4.3 (9) Global digital input disable register (GDIDIS) Change of description in 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) Change of Table 4-23. Settings of Port Mode Register, and Output Latch When Using Alternate Function Addition of note 3 to Table 4-23. Settings of Port Mode Register, and Output Latch When Using Alternate Function Addition of 4.6 Cautions When Using Port Function Addition of 4.6.2 Cautions on the pin settings on the products other than 128-pin R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1064 RL78/G13 APPENDIX A REVISION HISTORY (4/8) Edition Ver.1.00 Description Change of description in 5.1 (2) Subsystem clock Change of Figure 5-1. Block Diagram of Clock Generator Chapter CHAPTER 5 CLOCK GENERATOR Change and addition of note to Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Change of description and deletion of note 2 in 5.3 (2) System clock control register (CKC) Change of Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Deletion of note 4 in Figure 5-7. Format of Peripheral Enable Register 0 (PER0) Change of description and deletion of caution in 5.3 (7) Operation speed mode control register (OSMC) Change of cautions 2, 3 in Figure 5-9. Format of High-speed On-chip Oscillator Frequency Select Register (HOCODIV) Change of 5.3 (9) High-speed on-chip oscillator trimming register (HIOTRM) Addition of note 3 to Figure 5-14. Clock Generator Operation When Power Supply Voltage Is Turned On Change of 5.6.1 Example of setting high-speed on-chip oscillator Change of description in 5.6.2 Example of setting X1 oscillation clock Change of (6) and (8) in Table 5-3. CPU Clock Transition and SFR Register Setting Examples Change of Table 5-6 and Table 5-7 Change of Table 6-2. Timer I/O Pins provided in Each Product Change of 6.2 (1) Timer count register mn (TCRmn) CHAPTER 6 TIMER ARRAY UNIT Change of caution in 6.3 (2) Timer clock select register m (TPSm) Addition of note to Table 6-4. Interval Times Available for Operation Clock CKSm2 or CKSm3 Change of caution in 6.3 (3) Timer mode register mn (TMRmn) Change of Figure 6-8. Format of Timer Mode Register mn (TMRmn) Change of description in 6.3 (5) Timer channel enable status register m (TEm) Change of description in 6.3 (6) Timer channel start register m (TSm) Change of Figure 6-18. Format of Input Switch Control Register (ISC) Addition of remark to 6.3 (15) Port mode registers 0, 1, 3, 4, 6, 10, 14 (PM0, PM1, PM3, PM4, PM6, PM10, PM14) Change of description in 6.4.1 Basic rules of simultaneous channel operation function Change of description in 6.5.2 (e) Start timing in capture & one-count mode (when high-level width is measured) Change of Figure 6-27. Start Timing (In Capture & One-count Mode) Change of Figure 6-30. TOmn Pin Output Status at Toggle Output (TOMmn = 0) Change of note in Figure 6-37, Figure 6-39, Figure 6-43, Figure 6-51, Figure 6-55, Figure 6-57, Figure 6-59, Figure 6-64, Figure 6-69, Figure 6-74 Change of operation clock (fMCK) selection in Figure 6-39, Figure 6-43, Figure 6-51, Figure 6-55, Figure 6-59 Addition of note to Figure 6-49, Figure 6-53 Change of description in 6.7.6 Operation as delay counter Addition of 6.9 Cautions When Using Timer Array Unit R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1065 RL78/G13 APPENDIX A REVISION HISTORY (5/8) Edition Ver.1.00 Description Change of caution in 7.1 Functions of Real-time Clock Change of figure and caution in Figure 7-1. Block Diagram of Real-time Clock Chapter CHAPTER 7 REAL-TIME CLOCK Deletion of caution 4 of 7.3 (1) Peripheral enable register 0 (PER0) Change of caution in 7.3 (2) Operation speed mode control register (OSMC) Change of Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) Change of description and caution in 7.3 (5) Second count register (SEC) to 7.3 (11) Year count register (YEAR) Change of description in 7.4.3 Reading/writing real-time clock Addition of caution 2 to Figure 7-20. Procedure for Writing Real-time Clock Change of Figure 7-22. 1 Hz Output Setting Procedure Change of description in 8.1 Functions of Interval Timer Change of caution 1 in Figure 8-4. Format of Interval Timer Control Register (ITMC) Change of note and addition of remark to Figure 9-1. Block Diagram of Clock Output/Buzzer Output Controller Change of Figure 9-2. Format of Clock Output Select Register n (CKSn) CHAPTER 8 INTERVAL TIMER CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Change of 9.3 (2) Port mode register 1, 3, 5, 14 (PM1, PM3, PM5, PM14) Change of caution 4 and deletion of caution 5 in 10.4.1 Controlling operation of watchdog timer CHAPTER 10 WATCHDOG TIMER Deletion of caution of Table 10-3. Setting of Overflow Time of Watchdog Timer Deletion of caution 1 and change of remark in Table 10-4. Setting Window Open Period of Watchdog Timer Change of description in 11.1 Function of A/D Converter Change of Figure 11-1. Block Diagram of A/D Converter CHAPTER 11 A/D CONVERTER Change of description in 11.2 Configuration of A/D Converter Change of 11.3 Registers Used in A/D Converter Addition of note to Table 11-1. Settings of ADCS and ADCE Bits Change of Table 11-2. Setting and Clearing Conditions for ADCS Bit Change of Table 11-3. A/D Conversion Time Selection Change of Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) Change of Figure 11-8. ADRCK Bit Interrupt Signal Generation Range Change of Figure 11-11. Format of Analog Input Channel Specification Register (ADS) Change of Figure 11-14. Format of A/D Test Register (ADTES) Change of description in 11.3 (11) A/D port configuration register (ADPC) Change of 11.3 (12) Port mode control registers 0, 3, 10, 11, 12, 14 (PMC0, PMC3, PMC10, PMC11, PMC12, PMC14) Change of 11.3 (13) Port mode register 0, 2, 3, 10, 11, 12, 14, 15 (PM0, PM2, PM3, PM10, PM11, PM12, PM14, PM15) Change from "power down status" to "stop status" in 11.6 A/D Converter Operation Modes Change of 11.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode) Addition of description to 11.8 (1) If an interrupt is generated after A/D conversion ends Change of 11.10 (2) Input range of ANI0 to ANI14 and ANI16 to ANI26 pins Change of Table 11-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1066 RL78/G13 APPENDIX A REVISION HISTORY (6/8) Edition Ver.1.00 Description Addition of description of CSI30, CSI31, UART3, IIC30, IIC31 (corresponding to 128pin products) Chapter CHAPTER 12 SERIAL ARRAY UNIT Change of description to be corresponded to 128-pin products Change of description to CSI-UART channel corresponding SNOOZE mode Change of description to UART channel corresponding 9-bit data communication Change of caution in CHAPTER 12 SERIAL ARRAY UNIT 2 Change of description in 12.1.3 Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Change of note 1 in Table 12-1. Configuration of Serial Array Unit) Change of Figure 12-2. Block Diagram of Serial Array Unit 1 Addition of note to Figure 12-3 and 12-4 Change of caution 1 in Figure 12-5. Format of Peripheral Enable Register 0 (PER0) Change of Figure 12-6. Format of Serial Clock Select Register m (SPSm) Change of note 2 and caution in Figure 12-8. Format of Serial Communication Operation Setting Register mn (SCRmn) Change of description in 12.3 (5) Higher 7 bits of the serial data register mn (SDRmn) Addition of caution 2 to Figure 12-12. Format of Serial Channel Start Register m (SSm) Change of description in 12.3 (13) Serial output level register m (SOLm) Change of note and addition of caution to 12.3 (14) Serial standby control register m (SSCm) Change of Figure 12-19. Format of Input Switch Control Register (ISC) Change of flowchart for each operation mode Change of Figure 12-86. Initial Setting Procedure for UART Reception Change of Figure 12-88. Procedure for Resuming UART Reception Change of note in 12.8.1 Address field transmission to 12.8.3 Data reception Change of Figure 13-6. Format of IICA Control Register 00 (IICCTL00) Change of Figure 13-7. Format of IICA Status Register 0 (IICS0) CHAPTER 13 SERIAL INTERFACE IICA Change of 13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers Change of description in Figure 13-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) Change of Figure 14-6. Timing Diagram of Multiplication (Unsigned) Operation (2 x 3 = 6) Change of description in 14.4.3 Multiply-accumulation (unsigned) operation Change of Figure 14-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 x 3 + 3 = 9 32767 x 2 + 4294901762 = 0 (over flow generated)) CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLYACCUMULATOR Change of description in 14.4.4 Multiply-accumulation (signed) operation Change of Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) Operation (2 x 3 + (-4) = 2 32767 x (-1) + (-2147483647) = -2147450882 (overflow occurs.)) R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1067 RL78/G13 APPENDIX A REVISION HISTORY (7/8) Edition Ver.1.00 Description Change of Table 15-2 Internal RAM Area other than the General-purpose Registers Chapter CHAPTER 15 DMA CONTROLLER Change of (4) and addition of (6) to 15.6 Cautions on Using DMA Controller Change of Table 16-1. Interrupt Source List Change of Table 16-2. Flags Corresponding to Interrupt Request Sources CHAPTER 16 INTERRUPT FUNCTION Change of caution in 16.4.2 Software interrupt request acknowledgment Change of cautions 2, 4 and remark, and addition of caution 3 to 18.1.1 Standby function CHAPTER 18 STANDBY FUNCTION Addition of note to Figure 18-3 and Figure 18-4. Change of remark in 18.2.2 (1) STOP mode setting and operating statuses Change of remark 2, caution 2 in Table 18-2. Operating Statuses in STOP Mode Addition of note to Figure 18-5 and Figure 18-6. Change of remark in 18.2.3 (1) SNOOZE mode setting and operating statuses Change of remark 2 in Table 18-3. Operating Statuses in SNOOZE Mode Change of description and deletion caution 3 in CHAPTER 19 RESET FUNCTION Change of Figure 19-2. to Figure 19-4. CHAPTER 19 RESET FUNCTION Change of Table 19-2. Hardware Statuses After Reset Acknowledgment (1/4) and change of note 2 Change of values of LVIM, LVIS of note 2 in Table 19-2. Hardware Statuses After Reset Acknowledgment (4/4) Change of figure and addition of note 4 to Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/2) CHAPTER 20 POWERON-RESET CIRCUIT Change of note 4 and addition of note 5 to Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/2) Change of Figure 20-3. Example of Software Processing After Reset Release Change of description in 21.1 Functions of Voltage Detector Change of note 2 and addition of notes 3, 4 to Figure 21-2. Format of Voltage Detection Register (LVIM) CHAPTER 21 VOLTAGE DETECTOR Change of Figure 21-3. Format of Voltage Detection Level Select Register (LVIS) Change of Table 21-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H/010C1H) Change of description in 21.4.1 When used as reset mode Change of Figure 21-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Change of description in 21.4.2 When used as interrupt mode Change of Figure 21-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Change of description in 21.4.3 When used as interrupt and reset mode Change of Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) Change of Figure 21-8. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 1068 RL78/G13 APPENDIX A REVISION HISTORY (8/8) Edition Ver.1.00 Description Chapter Change of all CHAPTER 22 SAFETY FUNCTIONS Change of 23.1 Regulator Overview and Table 23-1. Regulator Output Voltage Conditions CHAPTER 23 REGULATOR Change of description in 24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) CHAPTER 24 OPTION BYTE Change of caution in Figure 24-1. Format of User Option Byte (000C0H/010C0H) Change of Figure 24-2. Format of User Option Byte (000C1H/010C1H) (1/2) Change of Figure 24-3. Format of Option Byte (000C2H/010C2H) Change of Table 25-1. Wiring Between RL78/G13 and Dedicated Flash Memory Programmer CHAPTER 25 FLASH MEMORY Change of 25.1.2 Communication Mode Change of description in 25.2.2 Communication Mode Change of description in 25.4.1 Data flash overview Change of description in 25.4.3 Procedure for accessing data flash memory Change of description in 25.5.2 Flash memory programming mode Addition of 25.5.5 Description of signature data Change of Table 25-12. Setting Security in Each Programming Mode Change of Table 25-14. Relationship between Flash Shield Window Function Setting/Change Methods and Commands Change of Figure 26-2. Memory Spaces Where Debug Monitor Programs Are Allocated CHAPTER 26 ON-CHIP DEBUG FUNCTION Change of description and deletion of remark in CHAPTER 28 INSTRUCTION SET CHAPTER 28 INSTRUCTION SET Change of 28.2 Operation List Addition of caution for pins of each products Change of 29.2 Absolute Maximum Ratings Change of 29.3.2 On-chip oscillator characteristics CHAPTER 29 ELECTRICAL SPECIFICATIONS Addition of 29.3.4 Recommended Oscillator Constants Change of 29.4.1 Pin characteristics Change of 29.4.2 Supply current characteristics Change of 29.5.1 Basic operation Change of 29.6.1 Serial array unit Change of 29.7.1 A/D converter characteristics Change of 29.7.2 Temperature sensor characteristics and 29.7.3 POR circuit characteristics Change of Supply Voltage Rise Time Change of 29.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics and 29.9 Flash Memory Programming Characteristics Change of 29.10 Timing Specs for Switching Modes Addition of CHAPTER 30 PACKAGE DRAWINGS R01UH0146EJ0200 Rev.2.00 Feb 27, 2012 CHAPTER 30 PACKAGE DRAWINGS 1069 RL78/G13 User's Manual: Hardware Publication Date: Rev.2.00 Feb 27, 2012 Published by: Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. 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