HI5746KCB-T - Intersil - Datasheet.Directory

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HI5746

10-Bit, 40MSPS A/D Converter

The HI5746 is a monolithic, 10-bit, analog-to-digital

converter fabricated in a CMOS process. It is designed for

high speed applica tions where wide bandwidth and low

power consumption are essential. Its 40MSPS speed is

made possible by a fully differential pipelined architecture

with an internal sample and hold .

The HI5746 has excellent dynamic perform ance while

consuming only 225mW power at 40MSPS. Data output

latches are provided which present valid data to the output

bus with a latency of 7 clock cycles. It is pin-for-pin

functionally compatible with the HI5702 and the HI5703.

F or internal voltage reference, please refer to the HI5767

data sheet.

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 40MSPS

• 8.8 Bits at fIN = 10MHz

• Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 225mW

• Wide Full Power Input Bandwidth . . . . . . . . . . . . 250MHz

• On-Chip Sample and Hold

• Fully Differential or Single-Ended Analog Input

• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Digital Inputs

• CMOS Compatible Digital Outputs. . . . . . . . . . . . 3.0/5.0V

• Offset Binary or Two’s Compleme nt Output Format

•Pb-free Available

Applications

• Professional Video Digitizing

• Medical Imag ing

• Digital Communication Systems

• High Speed Data Acquisition

Pinout HI5746

(SOIC, SSOP)

TOP VIEW

Ordering Information

PART

NUMBER TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

HI5746KCB 0 to 70 28 Ld SOIC (W) M28.3

HI5746KCBZ

(Note) 0 to 70 28 Ld SOIC (W)

(Pb-free) M28.3

HI5746KCBZ-T

(Note) 28 Ld SOIC (W) Tape and Reel

(Pb-free) M28.3

HI5746KCA 0 to 70 28 Ld SSOP M28.15

HI5746KCAZ

(Note) 0 to 70 28 Ld SSOP

(Pb-free) M28.15

HI5746EVAL1 25 Evaluation Board

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J Std-020B.

DVCC1

DGND1

DVCC1

DGND1

AVCC

AGND

VREF+

VREF-

VIN+

VIN-

VDC

AGND

AVCC

DVCC2

DGND2

DFS

CLK

Data Sheet July 2004 FN4129.5

Functional Block Diagram

DVCC2

DGND2

STAGE 1

STAGE 8

CLOCK

BIAS

VDC

VIN-

VIN+

D0 (LSB)

D9 (MSB)

CLK

DFS

AVCC AGND DVCC1 DGND1 VREF+V

REF- (OPTIONAL)

STAGE 9

S/H

∑

2-BIT

FLASH 2-BIT

DAC

2-BIT

FLASH 2-BIT

DAC

2-BIT

FLASH

DIGITAL DELAY

AND

DIGITAL ERROR

CORRECTION

∑

HI5746

Typical Application Schematic

Pin Descriptions

HI5746

ARE PLACED AS CLOSE

10µF AND 0.1µF CAPS

BNC

CLOCK

VIN+

10µF

0.1µF10µF

2.5V

2.0V

VIN-

DGND AGND

VREF- (8)

VREF+ (7)

VIN- (10)

CLK (22)

DFS (15)

DGND1 (4)

DGND2 (21)

DGND1 (2)

AGND (6)

AGND (12)

VIN+ (9) (1) DVCC1

VDC (11)

(LSB) (28) D0

(27) D1

(26) D2

(25) D3

(24) D4

(20) D5

(19) D6

(18) D7

(17) D8

(MSB) (16) D9

(5) AVCC

(13) AVCC

(23) DVCC2

(3) DVCC1 TO PART AS POSSIBLE

OE (14) 0.1µF

+5V

(OPTIONAL)

PIN NO. NAME DESCRIPTION

1DVCC1 Digital Supply (+5.0V).

2DGND1 Digital Ground.

3DVCC1 Digital Supply (+5.0V).

4DGND1 Digital Ground.

5AVCC Analog Supply (+5.0V).

6AGND Analog Ground.

7 VREF++2.5V Positive Reference Voltage

Input.

8 VREF - +2.0V Negative Reference Voltage

Input (Optional).

9 VIN+Positive Analog Input.

10 VIN-Negative Analog Input.

11 VDC DC Bias Voltage Output.

12 AGND Analog Ground.

13 AVCC Analog Supply (+5.0V).

14 OE Digital Output Enable Control Input.

15 DFS Data Format Select Input.

16 D9 Data Bit 9 Output (MSB).

17 D8 Data Bit 8 Output.

18 D7 Data Bit 7 Output.

19 D6 Data Bit 6 Output.

20 D5 Data Bit 5 Output.

21 DGND2 Digital Ground.

22 CLK Sample Clock Input.

23 DVCC2 Digital Output Supply

(+3.0V or +5.0V).

24 D4 Data Bit 4 Output.

25 D3 Data Bit 3 Output.

26 D2 Data Bit 2 Output.

27 D1 Data Bit 1 Output.

28 D0 Data Bit 0 Output (LSB).

PIN NO. NAME DESCRIPTION

HI5746

Absolute Maximum Ratings TA = 25oCThermal Information

Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .6V

DGND to AGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

Digital I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AGND to AVCC

Operating Conditions

Temperature Range

HI5746KCB (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC, SSOP - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operat i onal sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications AVCC = DVCC1 = 5.0V; DVCC2 = 3.0V, VREF+ = 2.5V; VREF - = 2.0V; fS = 40 MSPS at 50% Duty Cycle;

CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,

Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ACCURACY

Resolution 10 - - Bits

Integral Linearity Error, INL fIN = DC -±1.0 ±2.0 LSB

Differential Linearity Error, DNL

(Guaranteed No Missing Codes) fIN = DC -±0.5 ±1.0 LSB

Offset Error, VOS fIN = DC -40 12 40 LSB

Full Scale Error, FSE fIN = DC - 4 - LSB

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate No Missing Codes -0.5 1MSPS

Maximum Conversion Rate No Missing Codes 40 - - MSPS

Effective Number of Bits, ENOB fIN = 10MHz 8.55 8.8 -Bits

Signal to Noise and Distortion Ratio, SINAD fIN = 10MHz 53.2 54.9 -dB

Signal to Noise Ratio, SNR fIN = 10MHz 53.2 55.4 -dB

Total Harmonic Distortion, THD fIN = 10MHz --64.6 -dBc

2nd Harmonic Distortion fIN = 10MHz --67.8 -dBc

3rd Harmonic Distortion fIN = 10MHz --68.3 -dBc

Spurious Free Dynamic Range, SFDR fIN = 10MHz -67.8 -dBc

Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz -64 -dBc

Differential Gain Error fS = 17.72 MSPS, 6 Step, Mod Ramp -0.8 - %

Differential Phase Error fS = 17.72 MSPS, 6 Step, Mod Ramp -0.1 -Degree

Transient Response (Note 2) - 1 - Cycle

Over-Voltage Recovery 0.2V Overdrive (Note 2) - 1 - Cycle

RMS Signal

RMS Noise + Distortion

--------------------------------------------------------------

RMS Signal

RMS Noise

-------------------------------=

HI5746

ANALOG INPUT

Maximum Peak-to-Peak Differential Analog Input

Range (VIN+ - VIN-) -±0.5 - V

Maximum Peak-to-Peak Single-Ended

Analog Input Range -1.0 - V

Analog Input Resistance, RIN (Note 3) - 1 - MΩ

Analog Input Capacitance, CIN -10 -pF

Analog Input Bias Current, IB+ or IB-(Note 3) -10 -+10 µA

Differential Analog Input Bias Current

IBDIFF = (IB+ - IB-) (Note 3) -±0.5 -µA

Full Power Input Bandwidth, FPBW -250 -MHz

Analog Input Common Mode Voltage Range

(VIN+ + VIN-) / 2 Differential Mode (Note 2) 0.25 -4.75 V

REFERENCE INPUT

Total Reference Resistance, RLVREF + to AGND -2.5K -Ω

Positive Reference Current, IREF + - 1.07 -mA

Negative Reference Current, IREF - - 21 -µA

Positive Reference Voltage Input, VREF+(Note 2) -2.5 - V

Negative Reference Voltage Input, VREF - (Note 2) -2.0 - V

Reference Common Mode Voltage

(VREF+ + VREF -) / 2 (Note 2) -2.25 - V

DC BIAS VOLTAGE

DC Bias Voltage Output, VDC -3.2 - V

Maximum Output Current - - 0.4 mA

DIGITAL INPUTS

Input Logic High Voltage, VIH CLK, DFS, OE 2.0 - - V

Input Logic Low Voltage, VIL CLK, DFS, OE - - 0.8 V

Input Logic High Current, IIH CLK, DFS, OE, VIH = 5V -10.0 -+10.0 µA

Input Logic Low Current, IIL CLK, DFS, OE, VIL = 0V -10.0 -+10.0 µA

Input Capacitance, CIN - 7 - pF

DIGITAL OUTPUTS

Output Logic High Voltage, VOH IOH = 100µA; DVCC2 = 5V 4.0 - - V

Output Logic Low Voltage, VOL IOL = 100µA; DVCC2 = 5V - - 0.5 V

Output Three-State Leakage Current, IOZ VO = 0/5V; DVCC2 = 5V -±1±10 µA

Output Logic High Voltage, VOH IOH = 100µA; DVCC2 = 3V 2.4 - - V

Output Logic Low Voltage, VOL IOL = 100µA; DVCC2 = 3V - - 0.5 V

Electrical Specifications AVCC = DVCC1 = 5.0V; DVCC2 = 3.0V, VREF+ = 2.5V; VREF - = 2.0V; fS = 40 MSPS at 50% Duty Cycle;

CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

HI5746

Output Three-State Leakage Current, IOZ VO = 0/5V; DVCC2 = 3V -±1±10 µA

Output Capacitance, COUT -10 -pF

TIMING CHARACTERISTICS

Aperture Delay, tAP - 5 - ns

Aperture Jitter, tAJ - 5 - psRMS

Data Output Hold, tH- 7 - ns

Data Output Delay, tOD - 8 - ns

Data Output Enable Time, tEN - 5 - ns

Data Output Enable Time tDIS - 5 - ns

Data Latency, tLAT For a Valid Sample (Note 2) - - 7 Cycles

Power-Up Initialization Data Invalid Time (Note 2) - - 20 Cycles

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AVCC 4.75 5.0 5.25 V

Digital Supply Voltage DVCC1 4.75 5.0 5.25 V

Digital Output Supply Voltage, DVCC2 At 3.0V 2.7 3.0 3.3 V

At 5.0V 4.75 5.0 5.25 V

Total Supply Current, ICC fIN = 10MHz and DFS = “0” -46 -mA

Analog Supply Current, AICC fIN = 10MHz and DFS = “0” -30 -mA

Digital Supply Current, DICC1 fIN = 10MHz and DFS = “0” -13 -mA

Output Supply Current, DICC2 fIN = 10MHz and DFS = “0” - 3 - mA

Power Dissipation fIN = 10MHz and DFS = “0” -225 275 mW

Offset Error Sensitivity, ∆VOS AVCC or DVCC = 5V ±5% -±0.4 -LSB

Gain Error Sensitivity, ∆FSE AVCC or DVCC = 5V ±5% -±0.8 -LSB

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

Electrical Specifications AVCC = DVCC1 = 5.0V; DVCC2 = 3.0V, VREF+ = 2.5V; VREF - = 2.0V; fS = 40 MSPS at 50% Duty Cycle;

CL = 10pF; TA = 25oC; Differential Analog Input; Typical Values are Test Results at 25oC,

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

HI5746

Timing Waveforms

NOTES:

4. SN : N-th sampling period.

5. HN : N-th holding period.

6. BM , N : M-th stage digital output corresponding to N-th sampled input.

7. DN : Final data output corresponding to N-th sampled input.

FIGURE 1. HI5746 INTERNAL CIRCUIT TIMING

FIGURE 2. INPUT-TO OUTPUT TIMING

DN - 7 DN - 6 DN - 2 DN - 1 DNDN + 1

ANALOG

INPUT

CLOCK

INPUT

S/H

1ST

STAGE

2ND

STAGE

9TH

STAGE

DATA

OUTPUT

SN - 1 HN - 1 SNHNSN + 1 HN + 1 SN + 2 SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8

B1, N - 1 B1, N B1, N + 1 B1, N + 4 B1, N + 5 B1, N + 6 B1, N + 7

B2, N - 2 B2, N - 1 B2, N B2, N + 4 B2, N + 5 B2, N + 6

B9, N - 5 B9, N - 4 B9, N B9, N + 1 B9, N + 2 B9, N + 3

tLAT

tOD

DATA N - 1 DATA N

CLOCK

INPUT

DATA

OUTPUT

1.5V

tAP

ANALOG

INPUT

tAJ

1.5V

2.4V

0.5V

HI5746

Typical Perf ormance Curves

FIGURE 3. EFFECTIVE NUMBER OF BITS (ENOB) vs INPUT

FREQUENCY FIGURE 4. SINAD AND SNR vs INPUT FREQUENCY

NOTE: SFDR depicted here does not include an y harmonic distortion.

FIGURE 5. -2HD , -3HD , -THD AND SFDR vs INPUT

FREQUENCY FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs

ANALOG INPUT LEVEL

FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs

SAMPLE CLOCK DUTY CYCLE FIGURE 8. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF +

61 10 100

INPUT FREQUENCY (MHz)

(

BIT

fS = 40 MSPS, TA = 25oC

37 1 10 100

INPUT FREQUENCY (MHz)

SNR

SINAD

fS = 40 MSPS, TA = 25oC

45 1 10 100

INPUT FREQUENCY (MHz)

dBc

-2HD

-3HD

SFDR

-THD

fS = 40 MSPS, TA = 25oC9

40 -5 -10 -15 -20 -25 -30 -35

INPUT LEVEL (dBFS)

ENOB (BITS)

fS = 40 MSPS, fIN = 10MHz, TA = 25oC

630 35 40 45 50 55 60 70

DUTY CYCLE (%, TH/TCLK)

ENOB (BITS)

9.5

8.5

7.5

6.5

fS = 40 MSPS, fIN = 10MHz, TA = 25oC9

8.8

8.4

8.2

2.25 2.7 2.75

VREF+ (V)

ENOB (BITS)

2.35 2.4 2.45 2.55 2.62.5 2.65

8.6

2.3

fS = 40 MSPS, fIN = 10MHz, TA = 25oC

VREF+ - VREF- = 0.5V

HI5746

FIGURE 9. SINAD AND SNR vs VREF +

NOTE: SFDR depicted he re do es not inclu de a ny harmonic

distortion.

FIGURE 10. -2HD, -3HD, -THD AND SFDR vs VREF +

FIGURE 11. EFFECTIVE NUMBER OF BITS (ENOB) vs VREF +

(VREF - NOT DRIVEN) FIGURE 12. SINAD AND SNR vs VREF + (VREF - NOT DRIVEN)

FIGURE 13. -2HD, -3HD, -THD AND SFDR vs VREF +

(VREF - NOT DRIVEN) FIGURE 14. EFFECTIVE NUMBER OF BITS (ENOB) vs

ANALOG INPUT COMMON MODE VOLTAGE

Typical Perf ormance Curves (Continued)

2.25 2.7 2.75

VREF+ (V)

2.35 2.4 2.45 2.55 2.62.5 2.65

2.3

VREF+ - VREF- = 0.5V, TA = 25oC

SINAD

SNR

fS = 40 MSPS, fIN = 10MHz

2.25 2.7 2.75

VREF+ (V)

dBc

2.35 2.4 2.45 2.55 2.62.5 2.65

2.3

-3HD

SFDR

-THD

-2HD

VREF+ - VREF- = 0.5V, TA = 25oC

fS = 40 MSPS, fIN = 10MHz

8.8

8.6

8.2

2.25 2.7 2.75

VREF+ (V)

2.35 2.4 2.45 2.55 2.62.5 2.65

8.4

2.3

fS = 40 MSPS, fIN = 10MHz

ENOB (BITS)

TA = 25oC

2.25 2.7 2.75

VREF+ (V)

2.35 2.4 2.45 2.55 2.62.5 2.65

2.3

SINAD

SNR

fS = 40 MSPS, fIN = 10MHz

TA = 25oC

2.25 2.7 2.75

VREF+ (V)

dBc

2.35 2.4 2.45 2.55 2.62.5 2.65

2.3

-3HD

SFDR

-THD

-2HD fS = 40 MSPS, fIN = 10MHz

TA = 25oC

9.0

8.8

8.4

8.0

0.25 3.75

VCM (V)

1.25 1.75 2.25 3.252.75

8.6

0.75

8.2

fS = 40 MSPS, TA = 25oC

ENOB (BITS)

fIN = 1MHz

fIN = 10MHz

DIFFERENTIAL ANALOG INPUT

4.25 4.75

HI5746

FIGURE 15. TOTAL SUPPLY CURRENT vs TEMPERATURE FIGURE 16. SUPPLY CURRENT vs SAMPLE CLOCK

FREQUENCY

FIGURE 17. REFERENCE CURRENT vs TEMPERATURE FIGURE 18. DATA OUTPUT DELAY vs TEMPERATURE

FIGURE 19. DIFFERENTIAL GAIN/PHASE vs TEMPERATURE FIGURE 20. DIFFERENTIAL GAIN/PHASE vs SUPPLY VOLTAGE

Typical Perf ormance Curves (Continued)

fS = 40 MSPS, VIN+ = VIN-

45.0

44.5

44.0

43.5

43.0

42.5

42.0

41.5

41.0

40.5

-40-200 20406080

TEMPERATURE (oC)

ICC (mA)

1MHz ≤ fIN ≤ 15MHz, TA = 25oC

010 20 30 40

fS (MSPS)

SUPPLY CURRENT (mA)

ICC (TOTAL)

AICC

DICC1

DICC2

1200

-40-200 20406080

TEMPERATURE (oC)

IREF (µA)

IREF+

1000

800

600

400

200

IREF-

9.5

6.0-40-200 20406080

TEMPERATURE (oC)

tOD (ns)

9.0

8.5

7.5

7.0

6.5

8.0 tOD

0.90

0.40

-40-200 20406080

TEMPERATURE (oC)

DG (%)

DP (DEGREES)

0.85

0.80

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.25

0.2

0.15

0.1

0.05

fS = 17.72 MSPS 0.70

0.40

2.75 3.00 3.75 5.25

DVCC2 (V)

DG (%)

DP (DEGREES)

0.65

0.60

0.55

0.50

0.45

3.25 3.50 4.00 4.25 4.50 4.75 5.00

0.3

0.25

0.2

0.15

0.1

0.05

AVCC/DVCC1 = 5V ±5%, TA = 25oC

fS = 17.72 MSPS

HI5746

Detailed Description

Theory of Operation

The HI5746 is a 10-bit fully differential sampling pipeline A/D

converter with digital error correction logic. Figure 25 depicts

the circuit for the front end differential-in-diff erential-out sample-

and-hold (S/H). The switches are controlled by an internal

sampling clock which is a non-ov erlapping two phase signal, φ1

and φ2 , derived from the master sampling clock. During the

sampling phase, φ1 , the input signal is applied to the sampling

capacitors, CS . At the same time the holding capacitors, CH ,

are discharged to analog ground. At the f alling edge of φ1 the

input signal is sampled on the bottom plates of the sampling

capacitors. In the next clock phase, φ2 , the two bottom plates of

the sampling capacitors are connected together and the

holding capacitors are switched to the op amp output nodes.

The charge then redistributes between CS and CH completing

one sample-and-hold cycle. The front end sample-and-hold

output is a fully-differential, sampled-data representation of the

analog input. The circuit not only performs the sample-and-hold

function but will also convert a single-ended input to a fully-

differential output for the conv erter core. During the sampling

phase, the VIN pins see only the on-resistance of a s witch and

CS . The relatively small v alues of these components result in a

typical full power input bandwidth of 250MHz f or the con v erter .

FIGURE 21. DC BIAS VOLTAGE (VDC) vs TEMPERATURE FIGURE 22. EFFECTIVE NUMBER OF BITS F(ENOB) vs

TEMPERATURE

FIGURE 23. 2048 POINT FFT PLOT FIGURE 24. 2048 POINT FFT SPECTRAL PLOT

Typical Perf ormance Curves (Continued)

3.30

3.00

-40-200 20406080

TEMPERATURE (oC)

VDC (V)

3.20

3.10

9.0

8.8

8.6

8.4

8.2

-40-200 20406080

ENOB (BITS)

TEMPERATURE (oC)

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100 0 512 1023

FREQUENCY BIN

OUTPUT LEVEL (dB)

fIN = 10MHz

fS = 40 MSPS

HI5746

As illustrated in the functional block diagram and the timing

diagram in Figure 1, eight identical pipeline subconverter

stages, each containing a two-bit flash converter and a

two-bit multiplying digital-to-analog converter , follow the S/H

circuit with the ninth stage being a two bit flash converter.

Each converter stage in the pipel ine will be sampling in one

phase and amplifying in the other clock phase. Each

individual subconv erter clock signal is offset by 180 degrees

from the previous stage clock signal resulting in alternate

stages in the pipeline performing the same operation.

The output of each of the eight identical two-bit subconverter

stages is a two-bit digital word contain ing a supplementary bit

to be used b y the digital error correction logi c. The output of

each subcon verter stage is input to a digital dela y line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the eigh t

identical two-bit subco nverter stages with the corresponding

output of the ninth stage flash conv erter before applyin g the

eighteen bit result to the digital error correction lo gic. The

digital error correction logic uses the sup plementary bits to

correct any error that may exist before generating the final ten

bit digital data output of the conv erter .

Because of the pipeline nature of this converter, the digital

data representing an analog input sample is output to the

digital data bus on the 7th cycle of the clock after the analog

sample is taken. This time delay is specified as the data

latency. After the data latency time, the digital data

representing each succeeding analog sample is output

during the following clock cycle. The digital output data is

synchronized to the external sampling clock by a double

buffered latching technique. The output of the digital error

correction circuit is available in two’s complement or offset

binary format depending on the state of the Data Format

Select (DFS) control input (see Table 1, A/D Code Table).

Reference Voltage Inputs, VREF - and VREF+

The HI5746 is designed to acce pt tw o external reference

vol tage sources at the VREF input pins. Typical operation of

the conv erter requires VREF+ to be set at +2.5V and VREF - to

be set at 2.0V. How ever, it should be noted that the input

structure of the VREF+ and VREF - input pins consists of a

resistiv e voltage divider with one resistor of the divider

(nominally 500Ω) connected betw een V REF+ an d VREF - and

the other resistor of the divider (nominally 2000Ω) co nnected

between VREF - and analog ground. This allows the user the

option of supplying only the +2.5V VREF+ voltage reference

with the + 2.0 V VREF - being generated internally by the

voltag e division action of the input structure .

The HI5746 is tested with VREF - equal to +2.0V and VREF+

equal to +2.5V yielding a fully differential analog input voltage

range of ±0.5V. VREF+ and VREF - can differ from the abov e

vo ltages (see the Typical P e rformance Curves, Fi gure 8

through Figure 13).

In order to minimi ze ov erall con verter noise it is recomme nded

that adequate high freq uency deco upling be pro v ided at both

of the ref erence voltage input pins, VREF+ and VREF -.

Analog Input, Differential Connection

The analog input to the HI5746 is a differential input that can

be configured in various ways depending on the signal

source and the required level of performance. A fully

differential connection (Figure 26 and Figure 27) will give the

best performance for the converter.

Since the HI5746 is powered by a single +5V analog supply,

the analog input is limited to be between ground and +5V.

For the differential input connection this implies the analog

input common mode voltage can range from 0.25V to 4.75V.

The performance of the ADC does not change significantly

with the value of the analog input common mode voltage.

A DC voltage source, VDC , equal to 3.2V (typi cal), is made

av ailable to the user to help simplify circuit design when using

an A C cou pled differential input. This low output i mpedance

vo ltage source is not designed to be a ref erence but mak es an

e xcellent DC b ias source and sta ys w ell with in the analog

input common mode v ol tage ra nge o v er temper ature (see the

Typical Performance Curves , Figure 21 ).

For the AC coupled differential input (Figure 26) assume

the difference between VREF+, typically 2.5V, and VREF-,

typically 2.0V, is 0.5V. Full scale is achieved when the VIN

and -VIN input signals are 0.5VP- P , with -VIN being

180 degrees out of phase with VIN . The converter will be

VIN+ VOUT+

VOUT-

VIN-

φ1

φ2

φ1

FIGURE 25. ANALOG INPUT SAMPLE-AND-HOLD

VIN+

VDC

VIN-

HI5746

VIN

-VIN

FIGURE 26. AC COUPLED DIFFER ENTIAL INPUT

HI5746

at positive full scale when the VIN+ inp ut is at

VDC + 0.25V and the VIN- input is at VDC - 0.25V (VIN+ -

VIN- = +0.5V). Conversely, the conver ter will be at

negative fullscale when the VIN+ input is equal to VDC -

0.25V and VIN- is at VDC + 0.25V (VIN+ - VIN- = -0.5V).

The analog input can be DC coupled (Figure 27) as long as

the inputs are within the analog input common mode voltage

range (0.25V ≤ VDC ≤ 4.75V).

The resistors, R, in Figure 27 are not absolutely necessary

but may be used as load setting resistors. A capacitor, C,

connected from VIN+ to VIN- will help filter any high

frequency noise on the inputs, also improving performance.

Values around 20pF are suffic ient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

Analog Input, Single-Ended Connection

The configuration shown in Figure 28 may be used with a

single ended AC coupled input.

Again, assume the difference between VREF+, typically 2.5V,

and VREF-, typically 2V, is 0.5V. If VIN is a 1VP-P sinewave,

then VIN+ is a 1VP-P sinewave riding on a positive voltage

equal to VDC . The converter wil l be at positive full scale

when VIN+ is at VDC + 0.5V (VIN+ - VIN- = +0.5V) and will

be at negative full scale when VIN+ is equal to

VDC - 0.5V (VIN+ - VIN- = -0.5V). Sufficient headroom m ust

be provided such that the input voltage never goes ab ove

+5V or below A GND. In this case, VDC could range betw een

0.5V and 4.5V without a significant change in ADC

perf ormance. The simplest wa y to produce VDC is to use the

DC bias source, VDC , output of the HI5746.

The single ended analog input can be DC coupled

(Figure 27) as long as the inpu t is within the analog input

common mode voltage range.

The resistor, R, in Figure 29 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

connected from VIN+ to VIN- will help filter any high

frequency noise on the inputs, also improving perfor m ance.

Values around 20pF are sufficient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must tak e into account the highest

frequency component of the analog input signal.

A single ended source may give better ov erall system

performance if it is first converted to differential before

driving the HI5746.

Digital Output Control and Clock Requirements

The HI5746 provides a standard high-speed interface to

external TTL logic families.

In order to ensure rated performance of the HI5746, the duty

cycle of the clock should be held at 50% ±5%. It must also

have low jitter and operate at standard TTL levels.

Pe rformance of the HI5746 will only be guaranteed at

conversion rates above 1 MSPS. This ensures proper

performance of the internal dynamic circuits. Similarly, when

power is first applied to the converter, a maximum of 20

cycles at a sample rate above 1 MSPS will have to be

performed before valid data is available.

A Data Form at Select (DFS) pin is provided which will

determine the format of the digital data outputs. When at

logic low, the data will be output in offset binary format.

When at logic high, the data will be output in two’s

complement format. Refer to Table 1 for further information.

VIN+

VDC

VIN-

HI5746

VIN

-VIN R

VDC

FIGURE 27. DC COUPLED DIFFERENTIAL INPUT

VIN+

VIN-

HI5746

VIN

VDC

FIGURE 28. AC COUPLED SINGLE ENDED INPUT

VIN+

VIN-

HI5746

VDC

VIN

VDC

FIGURE 29. DC COUPLED SINGLE ENDED INPUT

HI5746

The output enable pin, OE, when pulled high will three-state

the digital outputs to a high impedance state. Set the OE

input to logic low for normal operation.

Supply and Ground Considerations

The HI5746 has separate analog and digital supply and

ground pins to keep digital noise out of the analog signal

path. The digital data outputs also have a separate supply

pin, DVCC2 , which can be pow ered from a 3V or 5V su pply.

This allows the outputs to interface with 3V logic if so

desired.

The part should be mounted on a bo ard that provides

separate low impedance connections for the analog and

digital supplies and grounds. For best performance, the

supplies to the HI5746 should be driven by clean, linear

regulated supplies. The board should also have good high

frequency decoupling capacitors mounted as close as

possible to the converter. If the part is powered off a single

supply then the analog supply should be isolated with a

ferrite bead from the digital supply.

Refer to the application note “Using In tersil High Speed A/D

Converters” (AN9214) for additional considerations when

using high speed conv erters.

Static Performance Definitions

Offset Error (VOS)

The midscale code transition should occur at a level 1/4 LSB

above half-scale. Offset is defined as the deviation of the

actual code transition from this point.

Full-Scale Error (FSE)

The last code transition should occur f or an analog input that

is 3/4 LSB below positive Full scale (+FS) with the offset

error removed. Fullscale error is defined as the deviation of

the actual code transition from this point.

Differential Linearity Error (DNL)

DNL is the worst case deviation of a code width from the

ideal value of 1 LSB.

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best

fit straight line calculated from the measured data.

Power Supply Sensitivity

Each of the power supplies are moved plus and minus 5%

and the shift in the offset and full scale error (in LSBs) is

noted.

Dynamic Performance Definitions

F ast F ourier Transform (FFT) techniques are used to e valuate

the dynamic performance of the HI5746. A low distortion sine

wa ve is applied to the input, it is coherently sampled, and the

output is stored in RAM. The data is then transf ormed into the

frequency domain with an FFT and analyz ed to evaluate the

dynamic performance of the A/D. The sine wav e input to the

part is -0.5dB down from Fullscale f or all these tests .

TABLE 1. A/D CODE TABLE

CODE CENTER

DESCRIPTION

DIFFERENTIAL

INPUT VOLTAGE

(VIN+ - VIN-)

OFFSET BINARY OUTPUT CODE

(DFS LOW) TWO’S COMPLEMENT OUTPUT CODE

(DFS HIGH)

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

+Full Scale (+FS) -

1/4 LSB 0.499756V 11111111110111111111

+FS - 11/4 LSB 0.498779V 11111111100111111110

+3/4 LSB 732.422µV 10000000000000000000

-1/4 LSB -244.141µV 01111111111111111111

-FS + 13/4 LSB -0.498291V 00000000011000000001

-Full Scale (-FS) +

3/4 LSB -0.499268V 00000000001000000000

NOTES:

8. The voltages listed above represent the ideal center of each output code shown as a function of the reference differential voltage,

(VREF + - VREF -) = 0.5V.

9. VREF+ = 2.5V and VREF - = 2V.

OE INPUT DIGITAL DATA OUTPUTS

0Active

1High Impedance

HI5746

SNR and SINAD are quoted in dB. The distortion numbers are

quoted in dBc (decibels with respect to carrier) and DO NOT

include any correction f actors f or normalizing to full scale.

Effective Number Of Bits (ENOB)

The effective number of bits (ENOB) is calculated from the

SINAD data by:

ENOB = (SINAD - 1.76 + VCORR) / 6.02,

where: VCORR = 0.5 dB.

VCORR adjusts the SINAD, and hence the ENOB, for the

amount the analog input signal is below fullscale.

Signal To Noise and Distortion Ratio (SINAD)

SINAD is the ratio of the measured RMS signal to RMS sum

of all the other spectral components below the Nyquist

frequency, fS/2, excluding DC.

Signal To Noise Ratio (SNR)

SNR is the ratio of the measured RMS signal to RMS noise

at a specified input and sampling frequency. The noise is the

RMS sum of all of the spectral components below fS/2

excluding the fundamental, the first five harmonics and DC.

Total Harmonic Distor tion (THD)

THD is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the fundamental input

signal.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the applicab l e harmonic

component to the RMS v a lue of the fundamental in put si gnal.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamen ta l RMS amplitude to the

RMS amplitude of the next largest spectral component in the

spectrum below fS / 2.

Intermodulation Distortion (IMD)

Nonlinearities in the signal path will tend to generate

intermodulation products when two tones, f1 and f2 , are

present at the inputs. The ratio of the measured signal to

the distortion terms is calculated. The terms included in the

calculation are (f1+f2), (f1-f2), (2f1), (2f2), (2f1+f2), (2f1-f2),

(f1+2f2), (f1-2f2). The ADC is tested with each tone 6dB

below full scale.

Transient Response

Transient response is measured by providing a full scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

10-bit accuracy.

Over-Voltage Recovery

Over-Voltage Recov ery is measured by providing a full scale

transition to the analog i nput of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 10-bit accuracy.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the analog input frequency at

which the amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has an amplitude which swings from

-FS to +FS. The bandwidth given is measured at the

specified sampling frequency.

Video Definitions

Differential Gain and Differential Phase are two commonly

f ound video specifications for characterizing the distortion of

a chrominance signal as it is offset through the input voltage

range of an ADC.

Differential Gain (DG)

Differential Gain is the peak difference in chrominance

amplitude (in percent) relative to the reference burst.

Differential Phase (DP )

Diff erential Phase is the peak difference in chrominance

phase (in degrees) relative to the reference burst.

Timing Definitions

Refer to Figure 1 and Figure 2 for these definitions.

Aperture Delay (tAP)

Aperture delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Aper tu re Ji tt er (tAJ)

Aperture jitter is the RMS variation in the aperture delay due

to variation of internal clock path delays.

Data Hold Time (tH)

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

Data Output Delay Time (tOD)

Data output delay time is the time to where the ne w data (N)

is valid.

Data Latency (tLAT)

After the analog sample is tak en, the digital data representing

an analog input sample is output to the digital data bus on

the 7th cycle of the clock after the analog sample is taken.

This is due to the pipeline nature of the con verter where the

analog sample has to ripple through the internal subconv erter

stages. This delay is specified as the data latency. After the

data latency time, the digital data representing each

succeeding analog sample is output during the following

clock cycle. The di gital data l ags t he ana log in put sa mple by 7

sample clock cycles .

Power-Up Initialization

This time is defined as the maxim um number of cloc k cycles

that are required to initialize the converter at power-up. The

requirement arises from the need to initialize the dynamic

circuits within the converter.

HI5746

HFA1100

HFA1105

HFA1106

HFA1135

HFA1145

HFA1245

HI5703

HI5746

HI5767

HSP9501

HSP48410

HSP48908

HSP48212

HSP43891

HSP43168

HSP43216

HI5780

HI1171

HI3338

HA5020

HA2842

HFA1115

HFA1212

HFA1412

HFA1100: 850MHz Video Op Amp

HFA1105: 300MHz Video Op Amp

HFA1106: 250MHz Video Op Amp with Bandwidth Limit Control

HFA1135: 350MHz Video Op Amp with Output Limiting

HFA1145: 300MHz Video Op Amp with Output Disable

HFA1245: Dual, 350MHz, Video Op Amp with Output Disable

HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter

HI5746: 10-Bit, 40 MSPS, Very Low Power A/D Converter

HI5767: 10-Bit, 40 MSPS A/D Converter with V oltage Reference

HSP9501: Programmable Data Buffer

HSP48410: Histogrammer/Accumulating Buffer, 10-Bit Pixel

Resolution

HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit

HSP48212: Digital Video Mixer

HSP43891: Digital Filter, 30MHz, 9-Bit

HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz

HSP43216: Digital Half Band Filter

HI5780: 10-Bit, 80 MSPS, Video D/A Converter

HI1171: 8-Bit, 40 MSPS, Video D/A Converter

HI3338: 8-Bit, 50 MSPS, Video D/A Converter

HA5020: 100MHz Video Op Amp

HA2842: High Output Current, Video Op Amp

HFA1115: 225MHz Programmable Gain Video Buffer with

Output Limiting

HFA1212: 350MHz Dual Programmable Gain Video Buffer

HFA1412: 350MHz Quad Programmable Gain Video Buffer

In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.

FIGURE 30. 10-BIT VIDEO IMAGING COMPONENTS

HFA1100

HFA1110

HFA3101

HFA3102

HFA3600

HI5703

HI5746

HI5767

HSP43168

HSP43216

HSP43220

HSP43891

HSP50016

HSP50110

HSP50210

HI5721

HI5780

HI20201

HI20203

HFA1112

HFA1113

HFA1100: 850MHz Op Amp

HFA1110: 750MHz Unity Gain Video Buffer

HFA3101: Gilbert Cell Transistor Array

HFA3102: Dual Long-Tailed Pair Transistor Array

HFA3600: Low Noise Amplifier/Mixer

HI5703: 10-Bit, 40 MSPS, Low Power A/D Converter

HI5746: 10-Bit, 40 MSPS, Very Low Power A/D Converter

HI5767: 10-Bit, 40 MSPS A/D Converter with Voltage Reference

HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz

HSP43216: Digital Half Band Filter

HSP43220: Decimating Digital Filter

HSP43891: Digital Filter, 30MHz, 9-Bit

HSP50016: Digital Down Converter

HSP50110: Digital Quadrature Tuner

HSP50210: Digital Costas Loop

HI5721: 10-Bit, 100 MSPS, Communications D/A Converter

HI5780: 10-Bit, 80 MSPS, D/A Converter

HI20201: 10-Bit, 160 MSPS, High Speed D/A Converter

HI20203: 8-Bit, 160 MSPS, High Speed D/A Converter

HFA1112: 850MHz Programmable Gain Video Buffer

HFA1113: 850MHz Programmable Gain Video Buffer with Output Limiting

In addition, CMOS Logic Families in HC/HCT, AC/ACT, FCT and CD4000 are available.

FIGURE 31. 10-BIT COMMUNICATIONS COMPONENTS

DSP/µPAMPAMP D/AA/D

HI5746