SN74LS161A, SN74LS163A BCD Decade Counters/ 4-Bit Binary Counters The LS161A/163A are high-speed 4-bit synchronous counters. They are edge-triggered, synchronously presettable, and cascadable MSI building blocks for counting, memory addressing, frequency division and other applications. The LS161A and LS163A count modulo 16 (binary). The LS161A has an asynchronous Master Reset (Clear) input that overrides, and is independent of, the clock and all other control inputs. The LS163A has a Synchronous Reset (Clear) input that overrides all other control inputs, but is active only during the rising clock edge. http://onsemi.com LOW POWER SCHOTTKY Binary (Modulo 16) Asynchronous Reset LS161A Synchronous Reset LS163A PLASTIC N SUFFIX CASE 648 16 * * * * * * Synchronous Counting and Loading Two Count Enable Inputs for High Speed Synchronous Expansion Terminal Count Fully Decoded Edge-Triggered Operation Typical Count Rate of 35 MHz ESD > 3500 Volts 1 SOIC D SUFFIX CASE 751B 16 1 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 C TA Operating Ambient Temperature Range IOH Output Current - High -0.4 mA IOL Output Current - Low 8.0 mA SOEIAJ M SUFFIX CASE 966 16 1 ORDERING INFORMATION Device Package Shipping SN74LS161AN 16 Pin DIP 2000 Units/Box SN74LS161AD SOIC-16 38 Units/Rail SN74LS161ADR2 SOIC-16 2500/Tape & Reel SN74LS161AM SOEIAJ-16 See Note 1 SN74LS161AMEL SOEIAJ-16 See Note 1 SN74LS163AN 16 Pin DIP 2000 Units/Box SN74LS163AD SOIC-16 38 Units/Rail SN74LS163ADR2 SOIC-16 2500/Tape & Reel SN74LS163AM SOEIAJ-16 See Note 1 SN74LS163AMEL SOEIAJ-16 See Note 1 1. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2001 October, 2001 - Rev. 1 1 Publication Order Number: SN74LS161A/D SN74LS161A, SN74LS163A CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 TC 15 Q0 14 Q1 13 Q2 12 Q3 11 CET PE 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual InLine Package. *MR for LS161A *SR for LS163A 1 *R 2 CP 3 P0 4 P1 5 P2 6 P3 8 7 CEP GND LOADING (Note a) PIN NAMES PE P0 - P3 CEP CET CP MR SR Q0 - Q3 TC Parallel Enable (Active LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trickle Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Synchronous Reset (Active LOW) Input Parallel Outputs Terminal Count Output HIGH LOW 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.5 U.L. 0.5 U.L. 1.0 U.L. 10 U.L. 10 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. LOGIC SYMBOL 9 7 3 4 5 6 PE P0 P1 P2 P3 CEP 10 CET 2 CP TC *R Q0 Q1 Q2 Q3 1 14 13 12 11 VCC = PIN 16 GND = PIN 8 *MR for LS161A *SR for LS163A http://onsemi.com 2 15 SN74LS161A, SN74LS163A STATE DIAGRAM LS161A * LS163A 0 1 2 3 15 5 14 6 13 7 12 11 10 LOGIC EQUATIONS 4 9 Count Enable = CEP * CET * PE TC for LS161A & LS163A = CET * Q0 * Q1 * Q2 * Q3 Preset = PE * CP + (rising clock edge) Reset = MR (LS161A) Reset = SR * CP + (rising clock edge) Reset = (LS163A) 8 FUNCTIONAL DESCRIPTION The Terminal Count (TC) output is HIGH when the Count Enable Trickle (CET) input is HIGH while the counter is in its maximum count state (HLLH for the BCD counters, HHHH for the Binary counters). Note that TC is fully decoded and will, therefore, be HIGH only for one count state. The LS161A and LS163A count modulo 16 following a binary sequence. They generate a TC when the CET input is HIGH while the counter is in state 15 (HHHH). From this state they increment to state 0 (LLLL). The Master Reset (MR) of the LS161A is asynchronous. When the MR is LOW, it overrides all other input conditions and sets the outputs LOW. The MR pin should never be left open. If not used, the MR pin should be tied through a resistor to VCC, or to a gate output which is permanently set to a HIGH logic level. The active LOW Synchronous Reset (SR) input of the LS163A acts as an edge-triggered control input, overriding CET, CEP and PE, and resetting the four counter flip-flops on the LOW to HIGH transition of the clock. This simplifies the design from race-free logic controlled reset circuits, e.g., to reset the counter synchronously after reaching a predetermined value. The LS161A/163A are 4-bit synchronous counters with a synchronous Parallel Enable (Load) feature. The counters consist of four edge-triggered D flip-flops with the appropriate data routing networks feeding the D inputs. All changes of the Q outputs (except due to the asynchronous Master Reset in the LS161A) occur as a result of, and synchronous with, the LOW to HIGH transition of the Clock input (CP). As long as the set-up time requirements are met, there are no special timing or activity constraints on any of the mode control or data inputs. Three control inputs -- Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) -- select the mode of operation as shown in the tables below. The Count Mode is enabled when the CEP, CET, and PE inputs are HIGH. When the PE is LOW, the counters will synchronously load the data from the parallel inputs into the flip-flops on the LOW to HIGH transition of the clock. Either the CEP or CET can be used to inhibit the count sequence. With the PE held HIGH, a LOW on either the CEP or CET inputs at least one set-up time prior to the LOW to HIGH clock transition will cause the existing output states to be retained. The AND feature of the two Count Enable inputs (CET*CEP) allows synchronous cascading without external gating and without delay accumulation over any practical number of bits or digits. MODE SELECT TABLE *SR PE CET CEP L H H H H X L H H H X X H L X X X H X L Action on the Rising Clock Edge ( ) RESET (Clear) LOAD (Pn Qn) COUNT (Increment) NO CHANGE (Hold) NO CHANGE (Hold) *For the LS163A only. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care http://onsemi.com 3 SN74LS161A, SN74LS163A LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage Min Typ Max 2.0 0.8 -0.65 2.7 -1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V V VCC = MIN, IIN = -18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA Input HIGH Current MR, Data, CEP, Clock PE, CET 20 40 A VCC = MAX, VIN = 2.7 V MR, Data, CEP, Clock PE, CET 0.1 0.2 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current MR, Data, CEP, Clock PE, CET -0.4 -0.8 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 2) -100 mA VCC = MAX ICC Power Supply Current Total, Output HIGH Total, Output LOW 31 32 mA VCC = MAX IIH -20 2. Not more than one output should be shorted at a time, nor for more than 1 second. LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Min Typ Max 2.0 0.8 -0.65 2.7 -1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V V VCC = MIN, IIN = -18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA Input HIGH Current Data, CEP, Clock PE, CET, SR 20 40 A VCC = MAX, VIN = 2.7 V Data, CEP, Clock PE, CET, SR 0.1 0.2 mA VCC = MAX, VIN = 7.0 V -0.4 -0.8 mA VCC = MAX, VIN = 0.4 V -100 mA VCC = MAX 31 32 mA VCC = MAX IIL Input LOW Current Data, CEP, Clock, PE, SR CET IOS Short Circuit Current (Note 3) ICC Power Supply Current Total, Output HIGH Total, Output LOW -20 3. Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) http://onsemi.com 4 SN74LS161A, SN74LS163A Limits Symbol Parameter Min Typ 25 32 Max Unit fMAX tPLH tPHL Maximum Clock Frequency Propagation Delay Clock to TC 20 18 35 35 ns tPLH tPHL Propagation Delay Clock to Q 13 18 24 27 ns tPLH tPHL Propagation Delay CET to TC 9.0 9.0 14 14 ns tPHL MR or SR to Q 20 28 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol Min Parameter Typ tWCP tW Clock Pulse Width Low 25 ns MR or SR Pulse Width 20 ns ts ts Setup Time, other* 20 ns Setup Time PE or SR 25 ns th th Hold Time, data 3 ns Hold Time, other 0 ns 15 ns trec Recovery Time MR to CP *CEP, CET, or DATA Test Conditions VCC = 5.0 V DEFINITION OF TERMS continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure AC WAVEFORMS tW(H) CP 1.3 V tPHL Q 1.3 V tW(L) MR 1.3 V 1.3 V tW trec Other conditions: PE = MR (SR) = H CEP = CET = H tPLH CP 1.3 V Q0 Q1 Q2 Q3 Figure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Width 1.3 V Other conditions: PE = L P0 = P1 = P2 = P3 = H tPHL 1.3 V Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time http://onsemi.com 5 SN74LS161A, SN74LS163A AC WAVEFORMS (continued) COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS 1.3 V 1.3 V CET tPHL tPLH The positive TC pulse occurs when the outputs are in the (Q0 * Q1 * Q2 * Q3) state for the LS161 and LS163. OTHER CONDITIONS: CP = PE = CEP = MR = H Figure 3. CLOCK TO TERMINAL COUNT DELAYS 1.3 V 1.3 V TC 1.3 V CP 1.3 V 1.3 V tPLH The positive TC pulse is coincident with the output state (Q0 * Q1 * Q2 * Q3) for the LS161 and LS163. TC 1.3 V 1.3 V OTHER CONDITIONS: PE = CEP = CET = MR = H Figure 4. 1.3 V CP ts(H) SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS P0 P1 P2 P3 The shaded areas indicate when the input is permitted to change for predictable output performance. tPHL 1.3 V th(H) = 0 1.3 V ts(L) 1.3 V th(L) = 0 1.3 V Q0 Q1 Q2 Q3 OTHER CONDITIONS: PE = L, MR = H Figure 5. SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND (CET) AND PARALLEL ENABLE (PE) INPUTS The shaded areas indicate when the input is permitted to change for predictable output performance. CP ts(L) SR or PE 1.3 V th (L) = 0 1.3 V PARALLEL LOAD (See Fig. 5) 1.3 V ts(H) ts(H) th(H) = 0 1.3 V Q RESPONSE TO PE th(H) = 0 CEP COUNT MODE (See Fig. 7) 1.3 V ts(H) Q RESPONSE TO SR COUNT OR LOAD ts(L) 1.3 V ts(L) 1.3 V COUNT 1.3 V th(L) = 0 th(H) = 0 CET 1.3 V RESET 1.3 V 1.3 V CP 1.3 V HOLD Q OTHER CONDITIONS: PE = H, MR = H Figure 6. Figure 7. http://onsemi.com 6 th(L) = 0 1.3 V HOLD SN74LS161A, SN74LS163A PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE -T- K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 7 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 SN74LS161A, SN74LS163A PACKAGE DIMENSIONS M SUFFIX SOEIAJ PACKAGE CASE 966-01 ISSUE O 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 M E HE 1 8 L DETAIL P Z D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 --0.031 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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