Vmarg
Closed Loop
Margining
UCD9090
VMON
GPIO
12V
V33A
V33D
GPIO
3.3V OUT VMON
1.8V OUT
0.8V OUT
I0.8V
TEMP0.8V
VMON
VMON
VMON
VMON
I12V
TEMP12V VMON
VMON
INA196
I12V
12V OUT
3.3V OUT
12V OUT
1.8V OUT
GPIO
GPIO
0.8V OUT
PWM 2MHz
INA196 I0.8V
WDI from main
processor GPIO
WDO GPIO
TEMP IC TEMP0.8V
TEMP IC TEMP12V
POWER_GOOD GPIO
WARN_OC_0.8V_
OR_12V GPIO
SYSTEM RESET GPIO
OTHER
SEQUENCER DONE
(CASCADE INPUT)
GPIO
I2C/
PMBUS
JTAG
/EN DC-DC 1
VOUT
VFB
VIN
/EN
LDO1
VOUT
VIN
/EN DC-DC 2
VOUT
VFB
VIN
3.3V
Supply
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
10-Rail Power Supply Sequencer and Monitor with ACPI Support
Check for Samples: UCD9090
1FEATURES DESCRIPTION
The UCD9090 is a 10-rail PMBus/I2C addressable
2Monitor and Sequence 10 Voltage Rails power-supply sequencer and monitor. The device
All Rails Sampled Every 400 μsintegrates a 12-bit ADC for monitoring up to 10
12-bit ADC With 2.5-V, 0.5% Internal VREF power-supply voltage inputs. Twenty-three GPIO pins
can be used for power supply enables, power-on
Sequence Based on Time, Rail and Pin reset signals, external interrupts, cascading, or other
Dependencies system functions. Ten of these pins offer PWM
Four Programmable Undervoltage and functionality. Using these pins, the UCD9090 offers
Overvoltage Thresholds per Monitor support for margining, and general-purpose PWM
Nonvolatile Error and Peak-Value Logging per functions.
Monitor (up to 30 Fault Detail Entries) Specific power states can be achieved using the
Closed-Loop Margining for 10 Rails Pin-Selected Rail States feature. This feature allows
with the use of up to 3 GPIs to enable and disable
Margin Output Adjusts Rail Voltage to any rail. This is useful for implementing system
Match User-Defined Margin Thresholds low-power modes and the Advanced Configuration
Programmable Watchdog Timer and System and Power Interface (ACPI) specification that is used
Reset for hardware devices.
Flexible Digital I/O Configuration The TI Fusion Digital Powerdesigner software is
Pin-Selected Rail States provided for device configuration. This PC-based
graphical user interface (GUI) offers an intuitive
Multiphase PWM Clock Generator interface for configuring, storing, and monitoring all
Clock Frequencies From 15.259 kHz to system operating parameters.
125 MHz
Capability to Configure Independent Clock
Outputs for Synchronizing Switch-Mode
Power Supplies
JTAG and I2C/SMBus/ PMBusInterfaces
APPLICATIONS
Industrial / ATE
Telecommunications and Networking
Equipment
Servers and Storage Systems
Any System Requiring Sequencing and
Monitoring of Multiple Power Rails
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PMBus, Fusion Digital Power are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Comparators
Monitor
Inputs
12-bit
200ksps,
ADC
(0.5% Int. Ref)
SEQUENCING ENGINE
BOOLEAN
Logic Builder
JTAG
Or
GPIO
I2C/PMBus
FLASH Memory
User Data, Fault
and Peak Logging
11
6
48-pin QFN
23
General Purpose I/O
(GPIO)
Digital Inputs (8 max)
Digital Outputs (10 max)
Rail Enables (10 max)
Margining Outputs (10 max)
Multi-phase PWM (8 max)
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see
the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE UNIT
Voltage applied at V33D to DVSS 0.3 to 3.8 V
Voltage applied at V33A to AVSS 0.3 to 3.8 V
Voltage applied to any other pin (2) 0.3 to (V33A + 0.3) V
Storage temperature (Tstg)40 to 150 °C
Human-body model (HBM) 2.5 kV
ESD rating Charged-device model (CDM) 750 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS
2Copyright ©2011, Texas Instruments Incorporated
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
THERMAL INFORMATION UCD9090
THERMAL METRIC(1) RGZ UNITS
48 PINS
θJA Junction-to-ambient thermal resistance(2) 25
θJCtop Junction-to-case (top) thermal resistance(3) 8.9
θJB Junction-to-board thermal resistance(4) 5.5 °C/W
ψJT Junction-to-top characterization parameter(5) 0.3
ψJB Junction-to-board characterization parameter(6) 1.5
θJCbot Junction-to-case (bottom) thermal resistance(7) 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT
Supply voltage during operation (V33D, V33DIO, V33A) 3 3.3 3.6 V
Operating free-air temperature range, TA40 110 °C
Junction temperature, TJ125 °C
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
SUPPLY CURRENT
IV33A VV33A = 3.3 V 8 mA
IV33DIO VV33DIO = 3.3 V 2 mA
Supply current(1)
IV33D VV33D = 3.3 V 40 mA
VV33D = 3.3 V, storing configuration parameters in
IV33D 50 mA
flash memory
ANALOG INPUTS (MON1MON13)
VMON Input voltage range MON1MON10 0 2.5 V
MON11 0.2 2.5 V
INL ADC integral nonlinearity 4 4 LSB
DNL ADC differential nonlinearity -2 2 LSB
Ilkg Input leakage current 3 V applied to pin 100 nA
IOFFSET Input offset current 1-ksource impedance 5 5 μA
MON1MON10, ground reference 8 MΩ
RIN Input impedance MON11, ground reference 0.5 1.5 3 M
CIN Input capacitance 10 pF
tCONVERT ADC sample period 12 voltages sampled, 3.89 μsec/sample 400 μsec
ADC 2.5 V, internal reference accuracy 0°C to 125°C0.5 0.5 %
VREF 40°C to 125°C1 1 %
ANALOG INPUT (PMBUS_ADDRx)
IBIAS Bias current for PMBus Addr pins 9 11 μA
(1) Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
Copyright ©2011, Texas Instruments Incorporated 3
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
VADDR_OPEN Voltage open pin PMBUS_ADDR0, PMBUS_ADDR1 open 2.26 V
VADDR_SHORT Voltage shorted pin PMBUS_ADDR0, PMBUS_ADDR1 short to ground 0.124 V
DIGITAL INPUTS AND OUTPUTS
VOL Low-level output voltage IOL = 6 mA(2), V33DIO = 3 V Dgnd + V
0.25
VOH High-level output voltage IOH =6 mA(3), V33DIO = 3 V V33DIO V
0.6
VIH High-level input voltage V33DIO = 3 V 2.1 3.6 V
VIL Low-level input voltage V33DIO = 3.5 V 1.4 V
MARGINING OUTPUTS
TPWM_FREQ MARGINING-PWM frequency FPWM1-8 15.260 125000 kHz
PWM1-2 0.001 7800
DUTYPWM MARGINING-PWM duty cycle range 0 100 %
SYSTEM PERFORMANCE
VDDSlew Minimum VDD slew rate VDD slew rate between 2.3 V and 2.9 V 0.25 V/ms
Supply voltage at which device comes
VRESET For power-on reset (POR) 2.4 V
out of reset
tRESET Low-pulse duration needed at RESET pin To reset device during normal operation 2 μS
f(PCLK) Internal oscillator frequency TA= 125°C, TA= 25°C 240 250 260 MHz
tretention Retention of configuration parameters TJ= 25°C 100 Years
Write_Cycles Number of nonvolatile erase/write cycles TJ= 25°C 20 K cycles
(2) The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
(3) The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.
4Copyright ©2011, Texas Instruments Incorporated
Start Stop
Clk ACK Clk ACK
PMB_Clk
PMB_Data
TLOW:SEXT
TLOW:MEXT TLOW:MEXT TLOW:MEXT
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
PMBus/SMBus/I2C
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and
PMBus is shown below.
I2C/SMBus/PMBus TIMING REQUIREMENTS
TA=40°C to 85°C, 3 V <VDD <3.6 V; typical values at TA= 25°C and VCC = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 10 400 kHz
FI2C I2C operating frequency Slave mode, SCL 50% duty cycle 10 400 kHz
t(BUF) Bus free time between start and stop 4.7 μs
t(HD:STA) Hold time after (repeated) start 0.26 μs
t(SU:STA) Repeated-start setup time 0.26 μs
t(SU:STO) Stop setup time 0.26 μs
t(HD:DAT) Data hold time Receive mode 0 ns
t(SU:DAT) Data setup time 50 ns
t(TIMEOUT) Error signal/detect See(1) 35 ms
t(LOW) Clock low period 0.5 μs
t(HIGH) Clock high period See (2) 0.26 50 μs
t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms
tfClock/data fall time See (4) 120 ns
trClock/data rise time See (5) 120 ns
(1) The device times out when any clock low exceeds t(TIMEOUT).
(2) t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t >50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(3) t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Fall time tf= 0.9 VDD to (VILMAX 0.15)
(5) Rise time tr= (VILMAX 0.15) to (VIHMIN + 0.15)
Figure 1. I2C/SMBus Timing Diagram
Figure 2. Bus Timing in Extended Mode
Copyright ©2011, Texas Instruments Incorporated 5
MON9
MON8
UCD9090
48
47
46
45
44
43
42
41
40
39
33
32
31
30
29
28
27
26
25
13
14
15
18
19
21
16
17
3
4
5
6
7
8
9
10
11
12
34
22
20
GPIO1
MON3
GPIO3
PMBUS_CLK
FPWM1/GPIO5
GPIO4
PMBUS_DATA
FPWM2/GPIO6
FPWM3/GPIO7
TCK/GPIO18
FPWM4/GPIO8
FWPM5/GPIO9
FPWM6/GPIO10
PMBUS_CNTRL
GPIO14
PMBUS_ALERT
GPIO17
DVSS
MON10
TMS/GPIO21
TDI/GPIO20
TDO/GPIO19
PWM2/GPI2
PWM1/GPI1
V33D
AVSS2
MON4
PMBUS_ADDR0
RESET
MON6
GPIO2
FPWM7/GPIO11
PMBUS_ADDR1
BPCAP
MON7
V33A
23
24
GPIO15
GPIO16
38
37
MON5
1
2
MON2
MON1
35
36
MON11
AVSS1
FPWM8/GPIO12
GPIO13
TRST
PMBUS_CLK
8
PMBUS_DATA
9
PMBUS_ALERT
19
PMBUS_CNTRL
20
PMBUS_ADDR0
44
PMBUS_ADDR1
43
32
DVSS
33
V33D
34
V33A
35
BPCAP
36
AVSS1
47
AVSS2
RESET 3
UCD9090
PWM1/GPI1
22
PWM2/GPI2
23
TRST 31
TCK/GPIO18 27
TDO/GPIO19 28
TDI/GPIO20 29
TMS/GPIO21 30
GPIO1 4
GPIO2 5
GPIO3 6
GPIO4 7
GPIO13 18
GPIO16 25
GPIO17 26
GPIO14 21
GPIO15 24
FPWM1/GPIO5 10
FPWM2/GPIO6 11
FPWM3/GPIO7 12
FPWM4/GPIO8 13
FPWM5/GPIO9 14
FPWM6/GPIO10 15
FPWM7/GPIO11 16
FPWM8/GPIO12 17
MON1
MON2
1
MON3
2
MON4
MON5
MON6
MON7
41
MON8
42
MON9
45
MON10
46
MON11
48
38
39
40
37
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
DEVICE INFORMATION
Figure 3. UCD9090 PIN ASSIGNMENT
Table 1. PIN FUNCTIONS
PIN NAME PIN NO. I/O TYPE DESCRIPTION
ANALOG MONITOR INPUTS
MON1 1 I Analog input (0 V2.5 V)
MON2 2 I Analog input (0 V2.5 V)
MON3 38 I Analog input (0 V2.5 V)
MON4 39 I Analog input (0 V2.5 V)
MON5 40 I Analog input (0 V2.5 V)
MON6 41 I Analog input (0 V2.5 V)
MON7 42 I Analog input (0 V2.5 V)
MON8 45 I Analog input (0 V2.5 V)
MON9 46 I Analog input (0 V2.5 V)
MON10 48 I Analog input (0 V2.5 V)
MON11 37 I Analog input (0.2 V2.5 V)
GPIO
GPIO1 4 I/O General-purpose discrete I/O
6Copyright ©2011, Texas Instruments Incorporated
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
Table 1. PIN FUNCTIONS (continued)
PIN NAME PIN NO. I/O TYPE DESCRIPTION
GPIO2 5 I/O General-purpose discrete I/O
GPIO3 6 I/O General-purpose discrete I/O
GPIO4 7 I/O General-purpose discrete I/O
GPIO13 18 I/O General-purpose discrete I/O
GPIO14 21 I/O General-purpose discrete I/O
GPIO15 24 I/O General-purpose discrete I/O
GPIO16 25 I/O General-purpose discrete I/O
GPIO17 26 I/O General-purpose discrete I/O
PWM OUTPUTS
FPWM1/GPIO5 10 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6 11 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7 12 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8 13 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9 14 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO10 15 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO11 16 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO12 17 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1 22 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM2/GPI2 23 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI
PMBus COMM INTERFACE
PMBUS_CLK 8 I/O PMBus clock (must have pullup to 3.3 V)
PMBUS_DATA 9 I/O PMBus data (must have pullup to 3.3 V)
PMBUS_ALERT 19 O PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBUS_CNTRL 20 I PMBus control
PMBUS_ADDR0 44 I PMBus analog address input. Least-significant address bit
PMBUS_ADDR1 43 I PMBus analog address input. Most-significant address bit
JTAG
TCK/GPIO18 27 I/O Test clock or GPIO
TDO/GPIO19 28 I/O Test data out or GPIO
TDI/GPIO20 29 I/O Test data in (tie to Vdd with 10-kΩresistor) or GPIO
TMS/GPIO21 30 I/O Test mode select (tie to Vdd with 10-kΩresistor) or GPIO
TRST 31 I Test reset tie to ground with 10-kΩresistor
INPUT POWER AND GROUNDS
RESET 3 Active-low device reset input. Hold low for at least 2 μs to reset the device.
V33A 34 Analog 3.3-V supply. Refer to the Layout Guidelines section.
V33D 33 Digital core 3.3-V supply. Refer to the Layout Guidelines section.
BPCap 35 1.8-V bypass capacitor. Refer to the Layout Guidelines section.
AVSS1 36 Analog ground
AVSS2 47 Analog ground
DVSS 32 Digital ground
QFP ground pad NA Thermal pad tie to ground plane.
FUNCTIONAL DESCRIPTION
TI FUSION GUI
The Texas Instruments Fusion Digital Power Designer is provided for device configuration. This PC-based
Copyright ©2011, Texas Instruments Incorporated 7
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
graphical user interface (GUI) offers an intuitive I2C/PMBus interface to the device. It allows the design engineer
to configure the system operating parameters for the application without directly using PMBus commands, store
the configuration to on-chip nonvolatile memory, and observe system status (voltage, etc). Fusion Digital Power
Designer is referenced throughout the data sheet as Fusion GUI and many sections include screenshots. The
Fusion GUI can be downloaded from www.ti.com.
PMBUS INTERFACE
The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus
interface that is built on the I2C physical specification. The UCD9090 supports revision 1.1 of the PMBus
standard. Wherever possible, standard PMBus commands are used to support the function of the device. For
unique features of the UCD9090, MFR_SPECIFIC commands are defined to configure or activate those features.
These commands are defined in the UCD90xxx Sequencer and System Health Controller PMBUS Command
Reference (SLVU352). The most current UCD90xxx PMBusCommand Reference can be found within the TI
Fusion Digital Power Designer software via the Help Menu (Help, Documentation &Help Center, Sequencers
tab, Documentation section).
This document makes frequent mention of the PMBus specification. Specifically, this document is PMBus Power
System Management Protocol Specification Part II Command Language, Revision 1.1, dated 5 February 2007.
The specification is published by the Power Management Bus Implementers Forum and is available from
www.pmbus.org.
The UCD9090 is PMBus compliant, in accordance with the Compliance section of the PMBus specification. The
firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function.
The hardware can support either 100-kHz or 400-kHz PMBus operation.
THEORY OF OPERATION
Modern electronic systems often use numerous microcontrollers, DSPs, FPGAs, and ASICs. Each device can
have multiple supply voltages to power the core processor, analog-to-digital converter or I/O. These devices are
typically sensitive to the order and timing of how the voltages are sequenced on and off. The UCD9090 can
sequence supply voltages to prevent malfunctions, intermittent operation, or device damage caused by improper
power up or power down. Appropriate handling of under- and overvoltage faults can extend system life and
improve long term reliability. The UCD9090 stores power supply faults to on-chip nonvolatile flash memory for aid
in system failure analysis.
System reliability can be improved through four-corner testing during system verification. During four-corner
testing, the system is operated at the minimum and maximum expected ambient temperature and with each
power supply set to the minimum and maximum output voltage, commonly referred to as margining. The
UCD9090 can be used to implement accurate closed-loop margining of up to 10 power supplies.
The UCD9090 10-rail sequencer can be used in a PMBus- or pin-based control environment. The TI Fusion GUI
provides a powerful but simple interface for configuring sequencing solutions for systems with between one and
10 power supplies using 10 analog voltage-monitor inputs, two GPIs and 21 highly configurable GPIOs. A rail
includes voltage, a power-supply enable and a margining output. At least one must be included in a rail
definition. Once the user has defined how the power-supply rails should operate in a particular system, analog
input pins and GPIOs can be selected to monitor and enable each supply (Figure 4).
8Copyright ©2011, Texas Instruments Incorporated
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
Figure 4. Fusion GUI Pin-Assignment Tab
Copyright ©2011, Texas Instruments Incorporated 9
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
After the pins have been configured, other key monitoring and sequencing criteria are selected for each rail from
the Vout Config tab (Figure 5):
Nominal operating voltage (Vout)
Undervoltage (UV) and overvoltage (OV) warning and fault limits
Margin-low and margin-high values
Power-good on and power-good off limits
PMBus or pin-based sequencing control (On/Off Config)
Rails and GPIs for Sequence On dependencies
Rails and GPIs for Sequence Off dependencies
Turn-on and turn-off delay timing
Maximum time allowed for a rail to reach POWER_GOOD_ON or POWER_GOOD_OFF after being enabled
or disabled
Other rails to turn off in case of a fault on a rail (fault-shutdown slaves)
Figure 5. Fusion GUI VOUT-Config Tab
The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage
of a rail and also update all of the other limits associated with that rail according to the percentages shown to the
right of each entry.
The plot in the upper left section of Figure 5 shows a simulation of the overall sequence-on and sequence-off
configuration, including the nominal voltage, the turnon and turnoff delay times, the power-good on and
power-good off voltages and any timing dependencies between the rails.
After a rail voltage has reached its POWER_GOOD_ON voltage and is considered to be in regulation, it is
compared against two UV and two OV thresholds in order to determine if a warning or fault limit has been
exceeded. If a fault is detected, the UCD9090 responds based on a variety of flexible, user-configured options.
Faults can cause rails to restart, shut down immediately, sequence off using turnoff delay times or shut down a
group of rails and sequence them back on. Different types of faults can result in different responses.
10 Copyright ©2011, Texas Instruments Incorporated
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
Fault responses, along with a number of other parameters including user-specific manufacturing information and
external scaling and offset values, are selected in the different tabs within the Configure function of the Fusion
GUI. Once the configuration satisfies the user requirements, it can be written to device SRAM if Fusion GUI is
connected to a UCD9090 using an I2C/PMBus. SRAM contents can then be stored to data flash memory so that
the configuration remains in the device after a reset or power cycle.
The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard,
for viewing and controlling device and system status.
Figure 6. Fusion GUI Monitor Page
The UCD9090 also has status registers for each rail and the capability to log faults to flash memory for use in
system troubleshooting. This is helpful in the event of a power-supply or system failure. The status registers
(Figure 7) and the fault log (Figure 8) are available in the Fusion GUI. See the UCD90xxx Sequencer and
System Health Controller PMBus Command Reference (SLVU352) and the PMBus Specification for detailed
descriptions of each status register and supported PMBus commands.
Copyright ©2011, Texas Instruments Incorporated 11
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
Figure 7. Fusion GUI Rail-Status Register
12 Copyright ©2011, Texas Instruments Incorporated
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
Figure 8. Fusion GUI Flash-Error Log (Logged Faults)
POWER-SUPPLY SEQUENCING
The UCD9090 can control the turn-on and turn-off sequencing of up to 10 voltage rails by using a GPIO to set a
power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a
sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C
serial bus. In pin-based designs, the PMBUS_CNTRL pin can also be used to sequence-on and sequence-off.
The auto-enable setting ignores the OPERATION command and the PMBUS_CNTRL pin. Sequence-on is
started at power up after any dependencies and time delays are met for each rail. A rail is considered to be on or
within regulation when the measured voltage for that rail crosses the power-good on (POWER_GOOD_ON(1))
(1) In this document, configuration parameters such as Power Good On are referred to using Fusion GUI names. The UCD90xxx
Sequencer and System Health Controller PMBus Command Reference name is shown in parentheses (POWER_GOOD_ON) the first
time the parameter appears.
Copyright ©2011, Texas Instruments Incorporated 13
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
limit. The rail is still in regulation until the voltage drops below power-good off (POWER_GOOD_OFF). In the
case that there isn't voltage monitoring set for a given rail, that rail is considered ON if it is commanded on (either
by OPERATION command, PMBUS CNTRL pin, or auto-enable) and (TON_DELAY +
TON_MAX_FAULT_LIMIT) time passes. Also, a rail is considered OFF if that rail is commanded OFF and
(TOFF_DELAY + TOFF_MAX_WARN_LIMIT) time passes
14 Copyright ©2011, Texas Instruments Incorporated
PMBUS_CNTRL PIN
RAIL 1 EN
RAIL 1 VOLTAGE
RAIL 2 EN
RAIL 2 VOLTAGE
POWER_GOOD_ON[1]
TON_DELAY[2]
Rail 1 and Rail 2 are both sequenced “ON”
and “OFF” by the PMBUS_CNTRL pin
only
Rail 2 has Rail 1 as an “ON” dependency
Rail 1 has Rail 2 as an “OFF” dependency
TON_DELAY[1]
TON_MAX_FAULT_LIMIT[2]
TOFF_DELAY[1]
POWER_GOOD_OFF[1]
TOFF_DELAY[2]
TOFF_MAX_WARN_LIMIT[2]
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
Turn-on Sequencing
The following sequence-on options are supported for each rail:
Monitor only do not sequence-on
Fixed delay time (TON_DELAY) after an OPERATION command to turn on
Fixed delay time after assertion of the PMBUS_CNTRL pin
Fixed time after one or a group of parent rails achieves regulation (POWER_GOOD_ON)
Fixed time after a designated GPI has reached a user-specified state
Any combination of the previous options
The maximum TON_DELAY time is 3276 ms.
Turn-off Sequencing
The following sequence-off options are supported for each rail:
Monitor only do not sequence-off
Fixed delay time (TOFF_DELAY) after an OPERATION command to turn off
Fixed delay time after deassertion of the PMBUS_CNTRL pin
Fixed time after one or a group of parent rails drop below regulation (POWER_GOOD_OFF)
Fixed delay time in response to an undervoltage, overvoltage, or max turn-on fault on the rail
Fixed delay time in response to a fault on a different rail when set as a fault shutdown slave to the faulted rail
Fixed delay time in response to a GPI reaching a user-specified state
Any combination of the previous options
The maximum TOFF_DELAY time is 3276 ms.
Figure 9. Sequence-on and Sequence-off Timing
Sequencing Configuration Options
In addition to the turn-on and turn-off sequencing options, the time between when a rail is enabled and when the
monitored rail voltage must reach its power-good-on setting can be configured using max turn-on
(TON_MAX_FAULT_LIMIT). Max turn-on can be set in 1-ms increments. A value of 0 ms means that there is no
limit and the device can try to turn on the output voltage indefinitely.
Rails can be configured to turn off immediately or to sequence-off according to rail and GPI dependencies, and
user-defined delay times. A sequenced shutdown is configured by selecting the appropriate rail and GPI
dependencies, and turn-off delay (TOFF_DELAY) times for each rail. The turn-off delay times begin when the
PMBUS_CNTRL pin is deasserted, when the PMBus OPERATION command is used to give a soft-stop
command, or when a fault occurs on a rail that has other rails set as fault-shutdown slaves.
Shutdowns on one rail can initiate shutdowns of other rails or controllers. In systems with multiple UCD9090s, it
is possible for each controller to be both a master and a slave to another controller.
Copyright ©2011, Texas Instruments Incorporated 15
UCD9090
SLVSA30A APRIL 2011REVISED AUGUST 2011
www.ti.com
PIN SELECTED RAIL STATES
This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing
system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used
for operating system directed power management in servers and PCs. In up to 8 system states, the power
system designer can define which rails are on and which rails are off. If a new state is presented on the input
pins, and a rail is required to change state, it will do so with regard to its sequence-on or sequence-off
dependencies.
The OPERATION command is modified when this function causes a rail to change its state. This means that the
ON_OFF_CONFIG for a given rail must be set to use the OPERATION command for this function to have any
effect on the rail state. The first 3 pins configured with the GPI_CONFIG command are used to select 1 of 8
system states. Whenever the device is reset, these pins are sampled and the system state, if enabled, will be
used to update each rail state. When selecting a new system state, changes to the status of the GPIs must not
take longer than 1 microsecond. See the UCD90xxx Sequencer and System Health Controller PMBus Command
Reference for complete configuration settings of PIN_SELECTED_RAIL_STATES.
Table 2. GPI Selection of System States
System
GPI 2 State GPI 1 State GPI 0 State State
NOT Asserted NOT Asserted NOT Asserted 0
NOT Asserted NOT Asserted Asserted 1
NOT Asserted Asserted NOT Asserted 2
NOT Asserted Asserted Asserted 3
Asserted NOT Asserted NOT Asserted 4
Asserted NOT Asserted Asserted 5
Asserted Asserted NOT Asserted 6
Asserted Asserted Asserted 7
MONITORING
The UCD9090 has 11 monitor input pins (MONx) that are multiplexed into a 2.5V referenced 12-bit ADC. The
monitor pins can be configured so that they can measure voltage signals to report voltage, current and
temperature type measurements. A single rail can include all three measurement types, each monitored on
separate MON pins. If a rail has both voltage and current assigned to it, then the user can calculate power for the
rail. Digital filtering applied to each MON input depends on the type of signal. Voltage inputs have no filtering.
Current and temperature inputs have a low-pass filter.
Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of
610 μV is fixed by the 2.5-V reference and the 12-bit ADC.
Table 3. Voltage Range and Resolution
VOLTAGE RANGE RESOLUTION
(Volts) (millivolts)
0 to 127.99609 3.90625
0 to 63.99805 1.95313
0 to 31.99902 0.97656
0 to 15.99951 0.48824
0 to 7.99976 0.24414
0 to 3.99988 0.12207
0 to 1.99994 0.06104
0 to 0.99997 0.03052
VOLTAGE MONITORING
Up to 12 voltages can be monitored using the analog input pins. The input voltage range is 0 V2.5 V for all
MONx inputs except MON11 (pin 37) which has a range of 0.2V2.5V. Any voltage between 0 V and 0.2 V on
these pins is read as 0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V.
16 Copyright ©2011, Texas Instruments Incorporated
Analog
Inputs
(12)
Internal
2.5Vref
0.5%
Fast Digital
Comparators
MON1 MON6
MON1
MON2
MON13
.
.
.
.
12-bit
SAR ADC
200ksps
M
U
X
MON1 MON13
Glitch
Filter
UCD9090
www.ti.com
SLVSA30A APRIL 2011REVISED AUGUST 2011
The ADC operates continuously, requiring 3.89 μs to convert a single analog input and 46.7 μs to convert all 12
of the analog inputs. Each rail is sampled by the sequencing and monitoring algorithm every 400 μs. The
maximum source impedance of any sampled voltage should be less than 4 k. The source impedance limit is
particularly important when a resistor-divider network is used to lower the voltage applied to the analog input
pins.
MON1 - MON6 can be configured using digital hardware comparators, which can be used to achieve faster fault
responses. Each hardware comparator has four thresholds (two UV (Fault and Warning) and two OV (Fault and
Warning)). The hardware comparators respond to UV or OV conditions in about 80 μs (faster than 400 µs for the
ADC inputs) and can be used to disable rails or assert GPOs. The only fault response available for the hardware
comparators is to shut down immediately.
An internal 2.5-V reference is used by the ADC. The ADC reference has a tolerance of ±0.5% between 0°C and
125°C and a tolerance of ±1% between 40°C and 125°C. An external voltage divider is required for monitoring
voltages higher than 2.5 V. The nominal rail voltage and the external scale factor can be entered into the Fusion
GUI and are used to report the actual voltage being monitored instead of the ADC input voltage. The nominal
voltage is used to set the range and precision of the reported voltage according to Table 3.
Figure 10. Voltage Monitoring Block Diagram
Although the monitor results can be reported with a resolution of about 15 μV, the real conversion resolution of
610 μV is fixed by the 2.5-V reference and the 12-bit ADC.
CURRENT MONITORING
Current can be monitored using the analog inputs. External circuitry, see Figure 11, must be used in order to
convert the current to a voltage within the range of the UCD9090 MONx input being used.
If a monitor input is configured as a current, the measurements are smoothed by a sliding-average digital filter.
The current for 1 rail is measured every 200μs. If the device is programmed to support 10 rails (independent of
current not being monitored at all rails), then each rail's current will get measured every 2ms. The current
calculation is done with a sliding average using the last 4 measurements. The filter reduces the probability of
false fault detections, and introduces a small delay to the current reading. If a rail is defined with a voltage
monitor and a current monitor, then monitoring for undercurrent warnings begins once the rail voltage reaches
POWER_GOOD_ON. If the rail does not have a voltage monitor, then current monitoring begins after
TON_DELAY.
The device supports multiple PMBus commands related to current, including READ_IOUT, which reads external
currents from the MON pins; IOUT_OC_FAULT_LIMIT, which sets the overcurrent fault limit;
IOUT_OC_WARN_LIMIT, which sets the overcurrent warning limit; and IOUT_UC_FAULT_LIMIT, which sets the
undercurrent fault limit. The UCD90xxx Sequencer and System Health Controller PMBus Command Reference
contains a detailed description of how current fault responses are implemented using PMBus commands.
IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any
amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms.
IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus
commands allows current to be reported in amperes. The example below using the INA196 would require
programming IOUT_CAL_GAIN to Rsense(mΩ)×20.
Copyright ©2011, Texas Instruments Incorporated 17
VOUT
GND
V+
Vin-
Vin+
Current Path
Rsense