CUSTOMER PROCUREMENTSPECIFICATION
216COl/CO2
CPU
CENTRALPROCESSINGUNIT
FEATURES
Part
Zi 6COl
Z16CO2
Memory
Address
8
Mbytes
64
Kbytes
Memory
Extension
48
Mbytes
384 Kbytes
Speed
(MHz)
10
10
H Extendable Register Files
1 Nine Basic Instruction Types
n 40/48-Pin PDIP and 44-Pin PLCC Packages’
n +4.5 I V,, I +5.5-Volt Operating Range
n Low-Power CMOS
n 0°C to +70°C Temperature Range
n Eight User-Selectable Addressing Modes
n Seven Data Types
H Supports Three Interrupt Types and Four Traps
n RISC-Like Load/Store Architecture
GENERAL DESCRIPTION
The Z16COl/CO2 CPU are members of the 16-bit The processor’s resources include seven data types that
processor and controller family. Designed using a range from bits to 32-bit long words, and byte and word
RISC-like Load/Store architecture, the CPU can operate in strings, plus eight user-selectable addressing modes. The
either system or normal modes, permitting privileged nine basic instruction types can be combined with various
operations and improving operating system organization data types and addressing modes to form a powerful set
and implementation. of 414 instructions.
To boost the main CPU’s performance capability, the
processor core includes hardwired control and is a
16-bit real-time processor functioning at register access
speeds. Register flexibility is created by grouping or
overlapping multiple registers, and by allowing extended
register file capabilities as the system expands. Easy
extended register file control is accomplished through a
single instruction stream communication.
TheCPUsupportsthreetypesof interrupts (non-maskable,
vectored, and non-vectored) and four traps (system call,
extended process architecture instruction, privileged
instructions, and segmentation trap). The vectored and
non-vectored interrupts are maskable.
The extended processing architecture features provide a
modular approach to expanding both the hardware and
software capabilities of the Z16COl/CO2.
Notes:
All Signals with a preceding front slash, “/“, are active Low, e.g.:
B/AN (WORD is active Low);
/B/W^(BYTE
is active Low, only).
Power connections follow conventional descriptions below:
Connection Circuit Device
Power
Ground “cc V DO
GND “ss
cPs95scc0103 (3/95) 1
~ziLfli5
216CWCO2 +-
cPs95sccolo3
GENERAL DESCRIPTION (Continued)
internal Data Bus Z-Bus
Z-Bus
0 Interface
Z16COO CPU Functional Block Diagram
3laius
AD13 c)
AD14 c)
AD13 c)
AD12 c)
REAMWRITE AD11 c)
AD10 c)
hwlM4u/sYsTEM ADi ,-
BYTEWORD
~573
AM).-
AD? ,c)
~ ST2 A06 .-
zid~i A& -
ST1 YBw”
3m
AM .-
A03
.-
IWAlT A02
.-
/STOP AD1 ,-
AW -
iNMI : sN4
lnlemlpN M : sN2
INVI : sN2
: SNl
Z16COVCO2 Signal Descriptions
2
Z16COlKO2
cPs95scc0103
PIN DESCRIPTION
216CO2 40-Pin PDIP
AD6
SN6
SN5
AD7
AD6
AD4
SN4
AD5
AD3
iD2
AD1
sN2
GND
CLOCK
IAS
NIC
ww
Nils
WIW
BUSACK
IWAIT
/BUSREP
SNO
SNI
216COl 46-Pin PDIP
Z16CO2 44-Pin PLCC
3
Z16COlKO2 +
cPs95scc0103
ABSOLUTE MAXIMUM RATINGS
Voltages on V,, with respect to V,, . . . . . . . . . . . . . . -0.3V to +7.OV Stresses greater than those listed under Absolute Maxi-
Voltages on all inputs with respect to mum Ratings may cause permanent damage to the de-
V
ss........““............................................. -0.3V to V,,+O.3V vice. This is a stress rating only; operating of the device at
Storage Temperature.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65”C to + 150% any condition above these indicated in the operational
sectionsof these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
STANDARD TEST CONDITIONS
The DC characteristics below apply for the following test All AC parameters assume a total load capacitance
conditions, unless otherwise noted. All voltages are refer- (including parasitic capacitances) or 100 pf max, except
enced to GND (OV). Positive current flows into the refer- for parameter 6 (50 pf max). Timing reference between two
enced pin. output signals assume a load difference of 50 pf max.
Available operating temperature ranges are: The Ordering Information section lists package tempera-
s = 0°C to +7O”C, + 4.5v s V,,I + 5.5v
(Z16COi,Zl6CO2)
ture ranges and product numbers.
E = -4OOC to +lOO”C, + 4.5V IV& + 5.5V
(Z16CO1, Zi 6CO2)
DC CHARACTERISTICS
SYm
Parameter MIN MAX Units Condition
V
CH
V
CL
VI,
V,, RESET
V,, NMI
Vi,
V
OH
V
OL
I
I\ SEGT
I
OL
ICC
Clock input High Voltage
Clock input Low Voltage
Input High Voltage
Input High Voltage on /RESET Pin
Input High Voltage on NMI Pin
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Input Leakage on /SEGT Pin
Output Leakage
V,, Power Supply Current
v&I.4
-0.3
2.0
2.4
2.4
-0.3
2.4
-100
Driven by External Clock Generator
v,,to.3 v
0.45 v Driven by External Clock Generator
v,,to.3 v
v,$o.3 v
v,,tD.3 v
0.8 V
0.4 V I,,=-250uA
L-10 I”J\ b:4;‘:$ +2.4V
100 f#I
*lo p4 0.4V < VIN < t2.4V
35 rnA 10MHz
4
piu3E
FOOTNOTES TO AC CHARACTERISTICS ’
Z16GOllCO2
cPs95sccolo3
No.
11
13
16
17
19
20
21
22
25
27
28
29
30
’
32
33
35
36
38
40
41
43
44
46
48
68
69
ZlGCOlR
10 MHz
Symbol Equation
TdA(DR) 2TcCtTwCh-6On.s
TdDS(A) _ TwClt5ns
TdDW(DS) TcCtTwCh-3Ons
TdA(MR) TwCh-20ns
TwMRh TcC-20ns
TdMR(A) TwCI-20ns
TdDW(DSW) TwCh-25ns
TdMR(DR) 2TcC-60ns
TdA(AS) TwCh-20ns
TdAS(DR) 2TcG60ns
TdDS(AS) TwCI-20ns
TwAS TwCh-5n.s
TdAS(A) * TwCI-7Ons
TdAS(DSR) TwCEns
TdDSR(DR) TcCtTwCh-6Ons
TdDS(DW) TwCI-15ns
TdA(DSR) TcC-35ns
TwDSR TcCtTwCh-3Ons
TwDSW TcC-25n.s
TdDSI(DR) 2TcC-80ns
TwDS 2TcC-40ns
TdAS(DSA) 4TcCtTwCI-30ns
TdDSA(DR) 2TcCtTwCh-75ns
TdS(AS) TwCh-20ns
TWA TcCSOns
TdDS(s) TwCI-1Ons
AC Timing Test Conditions:
VoL= 0.8V
VOH= 2.ov
'I,,= 0.8V
V,,= 2.4V
v,,, =0.45v
yHc = v,, - 0.4v
,
Zl6COlKO2 -
cPs95sccolo3
AC CHARACTERISTICS
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1.7
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
216CO1/2
10 MHz
Symbol Parameter Min Max
TcC Clock Cycle Time 100 **
TwCh Clock Width (High) 40 **
TwCl Clock Width (Low) - 40 **
TfC Clock Fall Time 10
TrC Clock Rise Time 10
TdC(SNv) Clock+ Segment Number Valid (50pf load) 50
TdC(SNn) Clock tsegment Number Not Valid 0
TdC(Bz) , Clock t Bus Float 50
TdC(A) Clock tAddress Valid 50
TdC(Az) Clock + Address Float 50
TdA(DR) Address Valid to Read Data Required Valid 180
TsDR(C) Read Data to Clock Fall Setup Time 20
TdDS(A) /DStAddress Active 45*
TdC(DW)’ Clock + Write Data Valid 60
ThDR(DS) Read Data to /DS Rise Hold Time 0
TdDW(DS) Write Data Valid to /DS Rise Delay 110*
TdA( MR) Address Valid to /MREQ Fall Delay 20
TdC(MR) Clock Fall to /MREQ Fall Delay 50
TwMRh /MREQ Width (High) 80
TdMR(A) /MREQ [ Address Not Active 20
TdDW(DSW)
Write Data Valid to /DS Fall (Write) Delay 15*
TdMR(DR) /MREQ [Read Data Required Valid 140*
TdC(MR) Clock Fall /MREQ Rise Delay 50
TdC(ASf) Clock + /AS Fall Delay 35
TdA(AS) Address Valid to /AS Rise Delay 20
TdC(ASr) Clock [ /AS Rise Delay 25
TdAS( DR) /AS + Read Data Required Valid 140
TdDS(AS) /DS + /AS Fall Delay 20*
TwAS /AS Width (Low) 35*
TdAS(A) /AS t Address Not Active Delay 30
TdAz(DSR) Address Float to /DS (Read) Fall Delay 0
TdAS(DSR) /AS t /DS (Read) Fall Delay 35*
TdDSR(DR) /DS (Read) Fall to Read Data Required Valid 80
TdC(DSr) Clock Fall to /OS Rise Delay 30
TdDS(DW) /DS + Write Data Not Valid 25*
TdA( DSR) Address Valid to /DS (Read) Fall Delay 65*
TdC(DSR) Clock Rise /DS (Read) Fall Delay 45
TwDSR
TdC(DSWj /DS (Read) Width (Low) 110*
Clock Fall to /DS (Write) Fall Delay 45
TwDSW /DS (Write) Width (Low) 75*
TdDSI(DR) /DS (l/O) [ Read Data Required Valid 120*
TdC(DSf) Clock [ /DS (l/O) Fall Delay 45
TwDS /DS (l/O) Width (Low) 160
TdAS(DSA) /AS t /DS (Acknowledge) Fall Delay 410*
TdC(DSA) Clock + /DS (Acknowledge) Fall Delay 45
TdDSA(DR) /DS (Acknowledge) [ Read Data Required Delay 165*
TdC(S) Clock Rise to Status Valid Delay 50
6
I
~ZllJJE Zl6COllCO2
cPs95sccolo3
AC CHARACTERISTICS (Continued)
216CO112
10 MHz
No. Symbol Parameter Min Max
48 TdS(AS) Status Valid to /AS Rise Delay 20*
49 TSR(C) /RESET to Clock Rise Setup Time , 35
50 ThR(C) /RESET to Clock Rise Hold Time 0
51 TwNMl /NMI Width (Low) 35
52 TsNMI(C) /NMI to Clock Rise Setup Time 35
53 TsVI(C) /VI, /NVI to Clock Rise Setup Time 35
54 ThVI(C) /VI, /NVI to Clock Rise Hold Time 10
55 TsSGT(C) /SEGT to Clock Rise Setup Time 35
56 ThSGT(C) /SEGT to Clock Rise Hold Time 10
57 TsMI(C) /Mt to Clock Rise Setup Time 35
58 ThMI(C) /MI to Clock Rise Hold Time . 0
59 TdC(M0) Clock Rise to /MO Delay 50
60 TsSTP(C) /STOP to Clock Fall Setup Time 35
61 ThSTP(C) /STOP to Clock Fall Hold Time 0
62 TsW(C) /WAIT to Clock Fall Setup Time 20
63 ThW(C) /WAIT to Clock Fall Hold Time 5
64 TsBRQ(C) /BUSREQ to Clock Rise Setup Time 35
65 ThBRQ(C) /BUSREQ to Clock Rise Hold Time, 5
66 TdC(BAKr) Clock Rise to /BUSACK Rise Delay 35
67 TdC(BAKf) Clock Rise to /BUSACK Fall Delay 35
68 TWA Address Valid Width ,. 50*
69 TdDS(S) /DS Rise to STATUS Not Valid 30
* Clock-cycle time-dependent characteristics. See Footnotes to AC Characteristics.
** Clock may be stopped.
t Units in nanoseconds (ns).
” ,“ 7
--
@ziuE
COMPOSITE AC TIMING DIAGRAM
Zl6COllCO2
cPs95sccolo3
This composite liming dia.
gram does not show actual
timing sequences. Refer to
this diagram only for the
detailed timing relationships
of indiwdual edges. Use the
precedtng illustrations as an
exolanation of the various
iitiing sequences.
Trming measurements are
made al the followrng
voltages. U.^. I ^...
Clock 4.ov D.8V
oulput 2.ov 0.8V
input 2.ov 0.8V
FlOal V rD.5V
DATA IN
n
I
Y-READ
INTERRUPT
ACKNOWLEWE
Composite AC liming
6
216COllCO2
cPs95scc0103
TIMING DIAGRAMS
i
-5
i
I
1
I
I
\ I
.E
E
.-
I-
%
8
u
-
216COllCO2 '
cPs95scc0103
TIMING DIAGRAMS (Continued) ’
8s
.I
IUWT
uw
I
IDIWT
. .
II
‘co(lT
ADDRESS DATA OUT
II
w
I
OUTWT
J
Y-t-t-
I
Input/Output Timing
WAIT CTCLES ADDEC
(-‘“)
10
C
T
x
L
Z16COVCO2
cPs95sccolo3
TIMING DIAGRAMS (Continued)
ma
. @b-we
L
i
$c Ix
i u.
II
Y <
191
Interrupt and Segment Trap
Request/Acknowledge liming
-
11
Z16COlKO2 -
cPs95scc0103
TIMING DIAGRAMS (Continued)
CLOCU
4
AH CVCLLS ADDED
iiD
Iii /
AD
MAD YDW ABMESS )-- (Z)
S
MAO
ns
WNHE
I
Memory Read and Write Timing
Zi 6COWO2
cPs95scc0103
TIMING DIAGRAMS (Continued)
-E
AVWLL -
;..
;..
J
J
/
/
AD
Bus Request/Acknowledge Timing
13
Zl6COl/C42 * ;
cPs95sccolo3 ’
TIMING DIAGRAMS (Continued) ’
Stop Timing
r
0 1995 byzilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered bywarrantyand patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-8800
Telephone (408) 370-8000
Telex 91 O-338-7821
FAX 408 370-8058
Internet: http://www.zilog.comMlog
General Questions: infoOzilog.com
14
