LTC4217 2A Integrated Hot Swap Controller Features Description Small Footprint nn 33m MOSFET with R SENSE nn Wide Operating Voltage Range: 2.9V to 26.5V nn Adjustable, 5% Accurate Current Limit nn Current and Temperature Monitor Outputs nn Overtemperature Protection nn Adjustable Current Limit Timer Before Fault nn Power Good and Fault Outputs nn Adjustable Inrush Current Control nn 2% Accurate Undervoltage and Overvoltage Protection nn Pin Compatible with LTC4232 (DFN Package Only) nn Available in 20-Lead TSSOP and 16-Lead 5mm x 3mm DFN Packages The LTC(R)4217 is an integrated solution for Hot Swap applications that allows a board to be safely inserted and removed from a live backplane. The part integrates a Hot Swap controller, power MOSFET and current sense resistor in a single package for small form factor applications. A dedicated 12V version (LTC4217-12) contains preset 12V specific thresholds, while the standard LTC4217 allows adjustable thresholds. nn Applications RAID Systems, Solid State Drives Server I/O Cards nn Industrial nn nn The LTC4217 provides separate inrush current control and a 5% accurate 2A current limit with foldback current limiting. The current limit threshold can be adjusted dynamically using an external pin. Additional features include a current monitor output that amplifies the sense resistor voltage for ground referenced current sensing and a MOSFET temperature monitor output. Thermal limit, overvoltage, undervoltage and power good monitoring are also provided. For a 5A pin compatible version, see LTC4232. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application 12V, 1.5A Card Resident Application with Auto-Retry 12V OUT VDD * UV AUTO RETRY LTC4217DHC-12 10k VOUT 12V 330F 1.5A GATE ISET TIMER INTVCC GND VIN 10V/DIV CONTACT BOUNCE IIN 0.1A/DIV PG FLT 1F + Power-Up Waveforms IMON VOUT 10V/DIV ADC 20k 4217 TA01a PG 10V/DIV 25ms/DIV * TVS: DIODES INC. SMAJ17A 4217 TA01b 4217fg For more information www.linear.com/LTC4217 1 LTC4217 Absolute Maximum Ratings (Notes 1, 2) Supply Voltage (VDD).................................. -0.3V to 28V Input Voltages FB, OV, UV...............................................-0.3V to 12V TIMER.................................................... -0.3V to 3.5V SENSE.............................. VDD - 10V or - 0.3V to VDD Output Voltages ISET, IMON.................................................. -0.3V to 3V PG, FLT................................................... -0.3V to 35V OUT............................................. -0.3V to VDD + 0.3V INTVCC................................................... -0.3V to 3.5V GATE (Note 3)......................................... -0.3V to 33V Operating Ambient Temperature Range LTC4217C................................................. 0C to 70C LTC4217I..............................................-40C to 85C LTC4217H........................................... -40C to 125C Junction Temperature (Notes 4, 5)......................... 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) FE Package Only................................................ 300C Pin Configuration LTC4217 LTC4217-12 LTC4217 TOP VIEW TOP VIEW 1 20 SENSE 2 19 VDD VDD 1 16 VDD VDD UV 2 15 ISET UV 3 18 ISET OV 3 14 IMON OV 4 17 IMON TIMER 4 13 FB TIMER 5 12 FLT INTVCC 6 17 SENSE 21 SENSE 16 FB 15 FLT INTVCC 5 GND 6 11 PG GND 7 14 PG OUT 7 10 GATE OUT 8 13 GATE OUT 8 9 OUT 9 12 OUT OUT DHC PACKAGE 16-LEAD (5mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 17) IS SENSE, JA = 43C/W SOLDERED, OTHERWISE JA = 140C/W 2 SENSE SENSE 10 11 SENSE FE PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 38C/W EXPOSED PAD (PIN 21) IS SENSE, JA = 38C/W SOLDERED, OTHERWISE JA = 130C/W 4217fg For more information www.linear.com/LTC4217 LTC4217 Order Information (http://www.linear.com/product/LTC4217#orderinfo) LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4217CDHC-12#PBF LTC4217CDHC-12#TRPBF 421712 16-Lead (5mm x 3mm) Plastic DFN 0C to 70C LTC4217IDHC-12#PBF LTC4217IDHC-12#TRPBF 421712 16-Lead (5mm x 3mm) Plastic DFN -40C to 85C LTC4217CDHC#PBF LTC4217CDHC#TRPBF 4217 16-Lead (5mm x 3mm) Plastic DFN 0C to 70C LTC4217IDHC#PBF LTC4217IDHC#TRPBF 4217 16-Lead (5mm x 3mm) Plastic DFN -40C to 85C LTC4217CFE#PBF LTC4217CFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP 0C to 70C LTC4217IFE#PBF LTC4217IFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP -40C to 85C LTC4217HFE#PBF LTC4217HFE#TRPBF LTC4217FE 20-Lead Plastic TSSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics VDD Input Supply Range IDD Input Supply Current MOSFET On, No Load l VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l VDD(UVTH) Input Supply Undervoltage Threshold LTC4217-12, VDD Rising l VDD(UVHYST) Input Supply Undervoltage Hysteresis LTC4217-12 l 520 VDD(OVTH) LTC4217-12, VDD Rising l 14.7 VDD(OVHYST) Input Supply Overvoltage Hysteresis LTC4217-12 l 183 VOUT(PGTH) LTC4217-12, VOUT Rising l 10.2 VOUT(PGHYST) Output Power Good Hysteresis LTC4217-12 l 127 IOUT OUT Leakage Current VOUT = VGATE = 0V, VDD = 26.5V VOUT = VGATE = 12V, LTC4217 VOUT = VGATE = 12V, LTC4217-12 VOUT = VGATE = 12V, LTC4217H l l l l dVGATE /dt GATE Pin Turn-On Ramp Rate RON MOSFET + Sense Resistor On-Resistance C-Grade, I-Grade H-Grade ILIM(TH) Current Limit Threshold VFB = 1.23V l Input Supply Overvoltage Threshold Output Power Good Threshold 2.9 26.5 V 1.6 3 mA 2.65 2.73 2.85 V 9.6 9.88 10.2 V 640 760 mV 15.05 15.4 V 244 305 mV 10.5 10.8 V 170 213 mV 1 50 1 0 2 70 2 150 4 90 6 A A A A l 0.15 0.3 0.55 V/ms l l 15 15 33 33 50 60 m m 1.9 2 2.1 A VFB = 1.23V l 1.85 2 2.15 A VFB = 0V l 0.35 0.5 0.7 A VFB = 1.23V, RSET = 20k l 0.85 1 1.17 A 4217fg For more information www.linear.com/LTC4217 3 LTC4217 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Inputs IIN OV, UV, FB Input Current V = 1.2V, LTC4217 l 0 1 A RIN OV, UV, FB Input Resistance LTC4217-12 l 13 18 23 k VTH OV, UV, FB Threshold Voltage VPIN Rising l 1.21 1.235 1.26 VOV(HYST) OV Hysteresis l 10 20 30 mV VUV(HYST) UV Hysteresis VUV(RTH) UV Reset Threshold Voltage VFB(HYST) RISET V l 50 80 110 mV l 0.55 0.62 0.7 V FB Power Good Hysteresis l 10 20 30 mV ISET Internal Resistor l 19 20 21 k 0.4 0.4 0.8 0.92 V V 0 10 A 1.235 1.28 V VUV Falling Outputs VOL PG, FLT Pin Output Low Voltage ISINK = 2mA C-Grade, I-Grade H-Grade l l IOH PG, FLT Pin Input Leakage Current 30V l VTIMER(H) TIMER Pin High Threshold VTIMER Rising l VTIMER(L) TIMER Pin Low Threshold VTIMER Falling l 0.1 0.21 0.3 V ITIMER(UP) TIMER Pin Pull-Up Current VTIMER = 0V l -80 -100 -120 A VTIMER = 1.2V l 1.4 2 2.6 A l 1.6 2 2.7 % l 47.5 50 52.5 A/A ITIMER(DN) TIMER Pin Pull-Down Current ITIMER(RATIO) TIMER Pin Current Ratio ITIMER(DN)/ITIMER(UP) AIMON IMON Pin Current Gain BWIMON IMON Bandwidth IOUT = 2A 1.2 250 kHz IOFF(IMON) IMON Pin Offset Current IOUT = 132mA l 0 7.5 A IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l -19 -24 -29 A IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 18V, VOUT = 12V C-Grade, I-Grade H-Grade l l 190 164 250 140 400 500 A A IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 18V, VOUT = 12V 140 mA AC Characteristics tPHL(GATE) Input High (OV), Input Low (UV) to Gate Low Propagation Delay VGATE < 16.5V Falling l 8 10 s tPHL(ILIM) Short-Circuit to Gate Low VFB = 0, Step ISENSE to 1.2A, VGATE < 16.5V Falling l 1 5 s tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l 100 150 ms tD(FAULT) UV Low to Clear Fault Latch Delay tD(CB) Circuit Breaker Filter Delay Time (Internal) 1 VFB = 0V, Step ISENSE to 1.2A C-Grade, I-Grade H-Grade tD(AUTO-RETRY) Auto-Retry Turn-On Delay (Internal) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V above OUT. Driving this pin to voltages beyond the clamp may damage the device. 4 50 s l l 1.5 1.4 2 2 2.7 2.7 ms ms l 50 100 150 ms Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 5: TJ is calculated from the ambient temperature, TA, and power dissipation, PD, according to the formula: LTC4217DHC, LTC4217DHC-12: TJ = TA + (PD * 43C/W) LTC4217FE: TJ = TA + (PD * 38C/W) 4217fg For more information www.linear.com/LTC4217 LTC4217 Typical Performance Characteristics IDD vs VDD 3.5 INTVCC (V) 1.6 25C 1.4 -40C VDD = 3.3V 2.0 1.5 1.0 1.2 0 5 10 15 VDD (V) 20 25 0 30 0 -2 -4 4217 G01 1.230 1.228 -6 -8 ILOAD (mA) -10 -12 0.06 -25 0 25 50 TEMPERATURE (C) 75 -105 -100 -95 -90 -50 100 -25 50 0 25 TEMPERATURE (C) 75 4217 G04 2.5 1.0 0.5 0 0.2 0.4 0.6 0.8 FB VOLTAGE (V) 1.0 1.2 4217 G07 1000 Current Limit Delay (tPHL(ILIM) vs Overdrive) 10 1 0.1 100 Current Limit Adjustment (IOUT vs RSET) 22 2.0 1.5 1.0 100 100 ISET RESISTOR (k) CURRENT LIMIT THRESHOLD VALUE (A) 2.5 1.5 75 0 2 4 6 8 OUTPUT CURRENT (A) 4217 G05 Current Limit Threshold Foldback 2.0 50 0 25 TEMPERATURE (C) 4217 G03 CURRENT LIMIT PROPAGATION DELAY (s) TIMER PULL-UP CURRENT (A) 0.08 -25 4217 G02 -110 0.04 -50 1.226 -50 -14 Timer Pull-Up Current vs Temperature 0.10 CURRENT LIMIT VALUE (A) 1.232 0.5 UV Hysteresis vs Temperature 0 UV LOW-HIGH HRESHOLD (V) 2.5 85C IDD (mA) 1.234 VDD = 5V 3.0 1.8 UV HYSTERESIS (V) UV Low-High Threshold vs Temperature INTVCC Load Regulation 2.0 1.0 TA = 25C, VDD = 12V unless otherwise noted. 10 4217 G06 Internal ISET Resistor (RISET) 21 20 19 0.5 0 1k 10k 100k RSET () 10M 1M 4217 G08 18 -50 -25 50 0 25 TEMPERATURE (C) 75 100 4217 G09 4217fg For more information www.linear.com/LTC4217 5 LTC4217 Typical Performance Characteristics RON vs VDD and Temperature TA = 25C, VDD = 12V unless otherwise noted. PG, FLT VOUT Low vs ILOAD MOSFET SOA Curve 10 60 14 12 VDD = 3.3V, 12V, 24V 1 1ms ID (A) RON (m) 40 30 20 10ms 100ms 0.1 10 0 -50 -25 0 25 50 TEMPERATURE (C) 75 0.01 100 TA = 25C MULTIPLE PULSE DUTY CYCLE = 0.2 0.1 1 85 2 4 6 8 ILOAD (mA) 10 12 4217 G12 Gate Drive vs Gate Pull-Up Current 7 -25.0 -24.5 -25 0 25 50 TEMPERATURE (C) 75 100 -24.0 -50 -25 50 0 25 TEMPERATURE (C) 75 VDD = 12V 5 4 3 VDD = 3.3V 2 Gate Drive vs VDD 5.6 5.4 5 10 15 VDD (V) 20 25 30 4217 G16 -5 -10 -15 -20 IGATE (A) -25 -30 4217 G15 0.9 0.8 6.14 0.7 6.13 VISET (V) VGATE (VGATE - VOUT) (V) 5.8 0 VISET vs Temperature Gate Drive vs Temperature 6.15 6.0 0 0 100 4217 G14 4217 G13 VGATE (VGATE - VOUT) (V) 0 1 80 -50 6 4 4217 G11 VGATE (VGATE - VOUT) (V) IGATE PULL-UP (A) 90 5.2 6 0 100 -25.5 95 6.2 8 6 100 FLT 2 -26.0 VDD = 3.3V, 12V, 24V ILOAD = 2A PG 10 GATE Pull-Up Current vs Temperature IMON vs Temperature and VDD IMON (A) 10 VDS (V) 4217 G10 105 1s 10s DC PG, FLT VOUT LOW (V) 50 6.12 0.6 0.5 6.11 6.10 -50 0.4 -25 0 25 50 TEMPERATURE (C) 75 100 4217 G17 0.3 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 4217 G18 4217fg For more information www.linear.com/LTC4217 LTC4217 Pin Functions FB: Foldback and Power Good Input. Connect this pin to an external resistive divider from OUT for the LTC4217 (adjustable) version. The LTC4217-12 version uses a fixed internal divider with optional external adjustment. Open the pin if the LTC4217-12 thresholds for 12V operation are desired. If the voltage falls below 0.6V, the current limit is reduced using a foldback profile (see the Typical Performance Characteristics section). If the voltage falls below 1.21V, the PG pin will pull low to indicate the power is bad. FLT: Overcurrent Fault Indicator. Open-drain output pulls low when an overcurrent fault has occurred and the circuit breaker trips. For overcurrent auto-retry tie to UV pin (see the Applications Information section for details). GATE: Gate Drive for Internal N-channel MOSFET. An internal 24A current source charges the gate of the Nchannel MOSFET. At start-up the GATE pin ramps up at a 0.3V/ms rate determined by internal circuitry. During an undervoltage or overvoltage condition a 250A pull-down current turns the MOSFET off. During a short-circuit or undervoltage lockout condition, a 140mA pull-down current source between GATE and OUT is activated. GND: Device Ground. IMON: Current Monitor Output. The current in the internal MOSFET switch is divided by 20,000 and sourced from this pin. Placing a 20k resistor from this pin to GND creates a 0V to 2V voltage swing when current ranges from 0A to 2A. INTVCC: Internal 3.1V Supply Decoupling Output. This pin must have a 1F or larger bypass capacitor. Overloading this pin can disrupt internal operation. comparator monitors an internal resistive divider between the OUT pin and GND. OV: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD for the LTC4217 (adjustable) version. The LTC4217-12 version uses a fixed internal divider with optional external adjustment for 12V operation. Open the pin if the LTC4217-12 thresholds are desired. If the voltage at this pin rises above 1.235V, an overvoltage is detected and the switch turns off. Tie to GND if unused. PG: Power Good Indicator. Open-drain output pulls low when the FB pin drops below 1.21V indicating the power is bad. If the FB pin rises above 1.23V and the GATE to OUT voltage exceeds 4.2V, the open-drain pull-down releases the PG pin to go high. SENSE: Current Sense Node and MOSFET Drain. The current limit circuit controls the GATE pin to limit the sense voltage between the VDD and SENSE pins to 15mV (2A) or less depending on the voltage at the FB pin. The exposed pad on DHC and FE packages are connected to SENSE and must be soldered to an electrically isolated printed circuit board trace to properly transfer the heat out of the package. TIMER: Timer Input. Connect a capacitor between this pin and ground to set a 12ms/F duration for current limit before the switch is turned off. If the UV pin is toggled low while the MOSFET switch is off, the switch will turn on again following a cooldown time of 518ms/F duration. Tie this pin to INTVCC for a fixed 2ms overcurrent delay and 100ms auto-retry time. ISET: Current Limit Adjustment Pin. For a 2A current limit value open this pin. This pin is driven by a 20k resistor in series with a voltage source. The pin voltage is used to generate the current limit threshold. The internal 20k resistor (RISET)) and an external resistor (RSET) between ISET and ground create an attenuator that lowers the current limit value. Due to circuit tolerance RSET should not be less than 2k. In order to match the temperature variation of the sense resistor, the voltage on this pin increases at the same rate as the sense resistance increases. Therefore the voltage at ISET pin is made proportional to temperature of the MOSFET switch. UV: Undervoltage Comparator Input. Tie high if unused. Connect this pin to an external resistive divider from VDD for the LTC4217 (adjustable) version. The LTC4217-12 version drives the UV pin with an internal resistive divider from VDD. Open the pin if the preset LTC4217-12 thresholds for 12V operation are desired. If the UV pin voltage falls below 1.15V, an undervoltage is detected and the switch turns off. Pulling this pin below 0.62V resets the overcurrent fault and allows the switch to turn back on (see the Applications Information section for details). If overcurrent auto-retry is desired then tie this pin to the FLT pin. OUT: Output of Internal MOSFET Switch. Connect this pin directly to the load. In the LTC421712 version, the PG VDD: Supply Voltage and Current Sense Input. This pin has an undervoltage lockout threshold of 2.73V. 4217fg For more information www.linear.com/LTC4217 7 LTC4217 Functional Diagram SENSE (EXPOSED PAD) INTERNAL 7.5m SENSE RESISTOR VDD GATE INTERNAL 25m MOSFET 6.15V OUT IMON - CHARGE PUMP AND GATE DRIVER f = 2MHz CS +- CLAMP + ISET INRUSH 0.6V POSITIVE TEMPERATURE COEFFICIENT REFERENCE 0.3V/ms RISET 20k X1 OUT FB CM FOLDBACK 0.6V 1.235V + UV * 20k * 20k * PG - UV - 140k 150k + VDD OUT LOGIC 1.235V PG * 0.62V + RST - VDD 224k 0.2V * INTVCC - + * FLT TM1 OV 20k + 100A OV 1.235V - 2A + VDD TM2 VDD - 1.235V - 3.1V GEN UVLO1 + - 2.73V INTVCC UVLO2 TIMER 2.65V + 4217 BD *LTC4217-12 (DFN) ONLY 8 GND 4217fg For more information www.linear.com/LTC4217 LTC4217 Operation The Functional Diagram displays the main circuits of the device. The LTC4217 is designed to turn a board's supply voltage on and off in a controlled manner allowing the board to be safely inserted and removed from a live backplane. The LTC4217 includes a 25m MOSFET and a 7.5m current sense resistor. During normal operation, the charge pump and gate driver turn on the pass MOSFET's gate to provide power to the load. The inrush current control is accomplished by the INRUSH circuit. This circuit limits the GATE ramp rate to 0.3V/ms and hence controls the voltage ramp rate of the output capacitor. The current sense (CS) amplifier monitors the load current using the voltage sensed across the current sense resistor. The CS amplifier limits the current in the load by reducing the GATE-to-OUT voltage in an active control loop. It is simple to adjust the current limit threshold using the current limit adjustment (ISET) pin. This allows a different threshold during other times such as start-up. A short circuit on the output to ground causes significant power dissipation during active current limiting. To limit this power, the foldback amplifier reduces the current limit value from 2A to 0.5A in a linear manner as the FB pin drops below 0.6V (see the Typical Performance Characteristics section). If an overcurrent condition persists, the TIMER pin ramps up with a 100A current source until the pin voltage exceeds 1.235V (comparator TM2). This indicates to the logic that it is time to turn off the pass MOSFET to prevent overheating. At this point the TIMER pin ramps down using the 2A current source until the voltage drops below 0.21V (Comparator TM1) which tells the logic to start an internal 100ms timer. At this point, the pass transistor has cooled and it is safe to turn it on again. It is suitable for many applications to use an internal 2ms overcurrent timer with a 100ms cooldown period. Tying the TIMER pin to INTVCC sets this default timing. Latchoff is the normal operating condition following overcurrent turnoff. Retry is initiated by pulling the UV pin low for a minimum of 1s then high. Auto retry is implemented by tying the FLT to the UV pin. The fixed 12V version, LTC4217-12, uses two separate internal dividers from VDD to drive the UV and OV pins. This version also features a divider from OUT to drive the FB pin. The LTC4217-12 is available in a DFN package while the LTC4217 (adjustable version) is in a DFN and TSSOP packages. The output voltage is monitored using the FB pin and the PG comparator to determine if the power is available for the load. The power good condition is signaled by the PG pin using an open-drain pull-down transistor. The Functional Diagram also shows the monitoring blocks of the LTC4217. The two comparators on the left side include the UV and OV comparators. These comparators determine if the external conditions are valid prior to turning on the MOSFET. But first the undervoltage lockout circuits UVLO1 and UVLO2 must validate the input supply and the internally generated 3.1V supply (INTVCC) and generate the power up initialization to the logic circuits. If the external conditions remain valid for 100ms the MOSFET is allowed to turn on. Other features include MOSFET current and temperature monitoring. The current monitor (CM) outputs a current proportional to the sense resistor current. This current can drive an external resistor or other circuits for monitoring purposes. A voltage proportional to the MOSFET temperature is output to the ISET pin. The MOSFET is protected by a thermal shutdown circuit. 4217fg For more information www.linear.com/LTC4217 9 LTC4217 Applications Information The typical LTC4217 application is in a high availability system that uses a positive voltage supply to distribute power to individual cards. A complete application circuit is shown in Figure 1. External component selection is discussed in detail in the following sections. OUT VDD 12V Z1* R3 140k FB UV R1 226k R2 20k LTC4217FE GATE RGATE 100k FLT R4 20k CCOMP 3.3nF OV R5 150k + R6 20k CGATE 0.1F VOUT 12V 0.8A INRUSH circuit that maintains a constant slope of GATE voltage versus time (Figure 2). The voltage at the GATE pin rises with a slope of 0.3[V/ms] and the supply inrush current is set at: IINRUSH = CL * 0.3[V/ms] VDD + 6.15V GATE CL 330F SLOPE = 0.3[V/ms] VDD OUT R7 10k PG ISET RSET 20k UV = 9.88V OV = 15.2V PG = 10.5V t1 TIMER CT 0.1F INTVCC C1 1F GND IMON 4217 F02 Figure 2. Supply Turn-On ADC RMON 20k 4217 F01 * TVS Z1: DIODES INC. SMAJ17A Figure 1. 0.8A, 12V Card Resident Application Turn-On Sequence Several conditions must be present before the internal pass MOSFET can be turned on. First the supply VDD must exceed its undervoltage lockout level. Next the internally generated supply INTVCC must cross its 2.65V undervoltage threshold. This generates a 25s power-on-reset pulse which clears the fault register and initializes internal latches. After the power-on-reset pulse, the LTC4217 will go through the following sequence. First, the UV and OV pins must indicate that the input voltage is within the acceptable range. All of these conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during the insertion has ended. The MOSFET is turned on by charging up the GATE with a charge pump generated 24A current source whose value is adjusted by shunting a portion of the pull-up current to ground. The charging current is controlled by the 10 t2 This gate slope is designed to charge up a 1000F capacitor to 12V in 40ms, with an inrush current of 300mA. This allows the inrush current to stay under the current limit threshold (500mA) for capacitors less than 1000F. Included in the Typical Performance Characteristics section is a graph of the Safe Operating Area for the MOSFET. It is evident from this graph that the power dissipation at 12V, 300mA for 40ms is in the safe region. Adding the RGATE, CGATE, and CCOMP network on the GATE pin will lower the inrush current below the default value set by the INRUSH circuit. The GATE is charged with an 24A current source (when INRUSH circuit is not driving the GATE). The voltage at the GATE pin rises with a slope equal to 24A/CGATE and the supply inrush current is set at: IINRUSH = CL CGATE * 24A When the GATE voltage reaches the MOSFET threshold voltage, the switch begins to turn on and the OUT voltage follows the GATE voltage as it increases. Once OUT reaches VDD, the GATE will ramp up until clamped by the 6.15V Zener between GATE and OUT. 4217fg For more information www.linear.com/LTC4217 LTC4217 Applications Information As the OUT voltage rises, so will the FB pin which is monitoring it. Once the FB pin crosses its 1.235V threshold and the GATE to OUT voltage exceeds 4.2V, the PG pin will cease to pull low and indicate that the power is good. If VDD drops below 2.65V for greater than 5s or INTVCC drops below 2.5V for greater than 1s, a fast shutdown of the switch is initiated. The GATE is pulled down with a 170mA current to the OUT pin. Parasitic MOSFET Oscillation Overcurrent Fault When the N-channel MOSFET ramps up the output during power-up it operates as a source follower. The source follower configuration may self-oscillate in the range of 25kHz to 300kHz when the load capacitance is less than 10F, especially if the wiring inductance from the supply to the VDD pin is greater than 3H. The possibility of oscillation will increase as the load current (during power-up) increases. There are two ways to prevent this type of oscillation. The simplest way is to avoid load capacitances below 10F. For wiring inductance larger than 20H, the minimum load capacitance may extend to 100F. A second choice is to connect an external gate capacitor CP >1.5nF as shown in Figure 3. The LTC4217 features an adjustable current limit with foldback that protects against short-circuits and excessive load current. To prevent excessive power dissipation in the switch during active current limit, the available current is reduced as a function of the output voltage sensed by the FB pin. A graph in the Typical Performance Characteristics curves shows the Current Limit Threshold Foldback. LTC4217 GATE CP 2.2nF OPTIONAL RC TO LOWER INRUSH CURRENT 4217 F03 Figure 3. Compensation for Small CLOAD Turn-Off Sequence The switch can be turned off by a variety of conditions. A normal turn-off is initiated by the UV pin going below its 1.235V threshold. Additionally, several fault conditions will turn off the switch. These include an input overvoltage (OV pin), overcurrent circuit breaker (SENSE pin) or over temperature. Normally the switch is turned off with a 250A current pulling down the GATE pin to ground. With the switch turned off, the OUT voltage drops which pulls the FB pin below its threshold. PG then pulls low to indicate output power is no longer good. An overcurrent fault occurs when the current limit circuitry has been engaged for longer than the timeout delay set by the TIMER. Current limiting begins when the MOSFET current reaches 0.5A to 2A (depending on the foldback). The GATE pin is then brought down with a 140mA GATEto-OUT current. The voltage on the GATE is regulated in order to limit the current to less than 2A. At this point, a circuit breaker time delay starts by charging the external timing capacitor with a 100A pull-up current from the TIMER pin. If the TIMER pin reaches its 1.235V threshold, the internal switch turns off (with a 250A current from GATE to ground). Included in the Typical Performance Characteristics curves is a graph of the Safe Operating Area for the MOSFET. From this graph one can determine the MOSFET's maximum time in current limit for a given output power. Tying the TIMER pin to INTVCC will force the part to use the internally generated (circuit breaker) delay of 2ms. In either case the FLT pin is pulled low to indicate an overcurrent fault has turned off the pass MOSFET. For a given circuit breaker time delay, the equation for setting the timing capacitor's value is as follows: CT = tCB * 0.083[F/ms] After the switch is turned off, the TIMER pin begins discharging the timing capacitor with a 2A pull-down current. 4217fg For more information www.linear.com/LTC4217 11 LTC4217 Applications Information When the TIMER pin reaches its 0.21V threshold, an internal 100ms timer is started. After the 100ms delay, the switch is allowed to turn on again if the overcurrent fault latch has been cleared. Bringing the UV pin below 0.6V for a minimum of 1s and then high will clear the fault latch. If the TIMER pin is tied to INTVCC then the switch is allowed to turn on again (after an internal 100ms delay), if the overcurrent fault latch is cleared. Tying the FLT pin to the UV pin allows the part to self-clear the fault and turn the MOSFET on as soon as TIMER pin has ramped below 0.21V. In this auto-retry mode the LTC4217 repeatedly tries to turn on after an overcurrent at a period determined by the capacitor on the TIMER pin. The auto-retry mode also functions when the TIMER pin is tied to INTVCC. The waveform in Figure 4 shows how the output latches off following a short-circuit. The current in the MOSFET is 0.5A as the timer ramps up. An external RSET resistor placed between the ISET pin and ground forms a resistive divider with the internal 20k RISET sourcing resistor. The divider acts to lower the voltage at the ISET pin and therefore lower the current limit threshold. The overall current limit threshold precision is reduced to 16% when using a 20k resistor to halve the threshold. Using a switch (connected to ground) in series with RSET allows the active current limit to change only when the switch is closed. This feature can be used to program a reduced running current while the maximum current limit is used at start-up. Monitor MOSFET Temperature The voltage at the ISET pin increases linearly with increasing temperature. The temperature profile of the ISET pin is shown in the Typical Performance Characteristics section. Using a comparator or ADC to measure the ISET voltage provides an indicator of the MOSFET temperature. The ISET voltage follows the formula: VOUT 10V/DIV VISET = IOUT 1A/DIV The MOSFET temperature is calculated using RISET of 20k. VGATE 10V/DIV T= TIMER 2V/DIV 4217 F04 1ms/DIV Figure 4. Short-Circuit Waveform Current Limit Adjustment The default value of the active current limit is 2A. The current limit threshold can be adjusted lower by placing a resistor between the ISET pin and ground. As shown in the Functional Block Diagram the voltage at the ISET pin (via the clamp circuit) sets the CS amplifier's built-in offset voltage. This offset voltage directly determines the active current limit value. With the ISET pin open, the voltage at the ISET pin is determined by a positive temperature coefficient reference. This voltage is set to 0.618V at room temperature which corresponds to a 2A current limit at room temperature. 12 RSET * (T + 273C) * 2.093[mV/C] RSET +RISET (RSET + 20k) * VISET - 273C RSET * 2.093[mV/C] when RSET is not present, T becomes: T= VISET 2.093[mV/C] - 273C There is an overtemperature circuit in the LTC4217 that monitors an internal voltage similar to the ISET pin voltage. When the die temperature exceeds 145C the circuit turns off the MOSFET until the temperature drops to 125C. Monitor MOSFET Current The current in the MOSFET passes through an internal 7.5m sense resistor. The voltage on the sense resistor is converted to a current that is sourced out of the IMON pin. The gain of ISENSE amplifier is 50A/A from IMON for 1A of MOSFET current. This output current can be converted to a voltage using an external resistor to drive a comparator 4217fg For more information www.linear.com/LTC4217 LTC4217 Applications Information or ADC. The voltage compliance for the IMON pin is from 0V to INTVCC - 0.7V. A microcontroller with a built-in comparator can build a simple integrating single-slope ADC by resetting a capacitor that is charged with this current. When the capacitor voltage trips the comparator and the capacitor is reset, a timer is started. The time between resets will indicate the MOSFET current. Once the PG comparator is high the GATE pin voltage is monitored with respect to the OUT pin. Once the GATE minus OUT voltage exceeds 4.2V the PG pin goes high. This indicates to the system that it is safe to load the OUT pin while the MOSFET is completely turned "on". The PG pin goes low when the GATE is commanded off (using the UV, OV or SENSE pins) or when the PG comparator drives low. 12V Fixed Version Monitor OV and UV Faults Protecting the load from an overvoltage condition is the main function of the OV pin. In the LTC4217-12, an internal resistive divider (driving the OV pin) connects to a comparator to turn off the MOSFET when the VDD voltage exceeds 15.05V. If the VDD pin subsequently falls back below 14.8V, the switch will be allowed to turn on immediately. In the LTC4217 the OV pin threshold is 1.235V when rising, and 1.215V when falling out of overvoltage. The UV pin functions as an undervoltage protection pin or as an "ON" pin. In the LTC4217-12 the MOSFET turns off when VDD falls below 9.23V. If the VDD pin subsequently rises above 9.88V for 100ms, the switch will be allowed to turn on again. The LTC4217 UV turn-on/off thresholds are 1.235V (rising) and 1.115V (falling). In the cases of an undervoltage or overvoltage the MOSFET turns off and there is indication on the PG status pin. When the overvoltage is removed the MOSFET's gate ramps up immediately at the rate determined by the INRUSH block. In the LTC4217-12 the UV, OV and FB pins are driven by internal dividers which may need to be filtered to prevent false faults. By placing a bypass capacitor on these pins the faults are delayed by the RC time constant. Use the RIN value from the electrical characteristics table for this calculation. In cases where the fixed thresholds need a slight adjustment, placing a resistor from the UV or OV pins to VDD or GND will adjust the threshold up or down. Likewise placing a resistor between FB pin to OUT or GND adjusts the threshold. Again use the RIN value from the electrical characteristics table for this calculation. An example in Figure 5 raises the UV turn-on voltage from 9.88V to 10.5V. Increasing the UV level requires adding a resistor between UV and ground. The resistor, RSHUNT1, can be calculated using electrical table parameters as follows: RSHUNT1 = R(IN) * VOLD 18k * 9.88V = = 287k ( VNEW - VOLD ) (10.5V - 9.88V ) Power Good Indication In addition to setting the foldback current limit threshold, the FB pin is used to determine a power good condition. The LTC4217-12 uses an internal resistive divider on the OUT pin to drive the FB pin. The PG comparator indicates logic high when OUT pin rises above 10.5V. If the OUT pin subsequently falls below 10.3V the comparator toggles low. On the LTC4217 the PG comparator drives high when the FB pin rises above 1.235V and low when falls below 1.215V. LTC4217-12 VDD OV RSHUNT2 UV RSHUNT1 4217 F05 Figure 5. Adjusting LTC4217-12 Thresholds 4217fg For more information www.linear.com/LTC4217 13 LTC4217 Applications Information 100mA (or 1.2W) is within the SOA of the pass MOSFET for 40ms (see MOSFET SOA curve in the Typical Performance Characteristics section). In this same figure the OV threshold is lowered from 15.05V to 13.5V. Decreasing the OV threshold requires adding a resistor between VDD and OV. This resistor can be calculated as follows: ( ) R(IN) * VOLD VNEW - VOV ( TH) RSHUNT2 = V( TH) ( VOLD - VNEW ) 18k*15.05V (13.5V-1.235V ) =1.736M 1.235V (15.05V-13.5V ) Next the power dissipated in the MOSFET during overcurrent must be limited. The active current limit uses a timer to prevent excessive energy dissipation in the MOSFET. The worst-case power dissipation occurs when the voltage versus current profile of the foldback current limit is at the maximum. This occurs when the current is 2A and the voltage is one half of the VIN or 6V. See the Current Limit Threshold Foldback in the Typical Performance Characteristics section to view this profile. In order to survive 12W, the MOSFET SOA dictates a maximum time of 10ms (see SOA graph). Use the internal 2ms timer invoked by tying the TIMER pin to INTVCC. After the 2ms timeout the FLT pin needs to pull-down on the UV pin to restart the power-up sequence. = Use the equation for RSHUNT1 for increasing the OV and FB thresholds. Likewise use the equation for RSHUNT2 for decreasing the UV and FB thresholds. Design Example Consider the following design example (Figure 6): VIN = 12V, IMAX = 2A. IINRUSH = 100mA, CL = 330F, VUVON = 9.88V, VOVOFF = 15.05V, VPGTHRESHOLD = 10.5V. A current limit fault triggers an automatic restart of the power-up sequence. Since the default values for overvoltage, undervoltage and power good thresholds for the 12V fixed version match the requirements, no external components are required for the UV, OV and FB pins. The inrush current is defined by the current required to charge the output capacitor using the fixed 0.3V/ms GATE charge-up rate. The inrush current is defined as: The final schematic in Figure 6 results in very few external components. The pull-up resistor, R7, connects to the PG pin while the 20k (RMON) converts the IMON current to a voltage at a ratio: IINRUSH = CL * 0.3[V/ms] = 330F * 0.3[V/ms] = 100mA VIMON = 50[A/A] * 20k * IOUT = 1[V/A] * IOUT As mentioned previously the charge-up time is the output voltage (12V) divided by the output rate of 0.3V/ms resulting in 40ms. The peak power dissipation of 12V at 12V Z1* In addition there is a 1F bypass (C1) on the INTVCC pin. VDD OUT UV GATE LTC4217-12DHC FLT C1 1F + R7 10k VOUT 12V CL 1.5A 330F UV = 9.88V OV = 15.05V PG = 10.5V PG TIMER ISET INTVCC IMON GND ADC RMON 20k 4217 F06 *TVS Z1: DIODES INC. SMAJ17A Figure 6. 1.5A, 12V Card Resident Application 14 4217fg For more information www.linear.com/LTC4217 LTC4217 Applications Information Layout Considerations Although the MOSFET is self protected from overtemperature, it is recommended to solder the backside of the package to a copper trace to provide a good heat sink. Note that the backside is connected to the SENSE pin and cannot be soldered to the ground plane. During normal loads the power dissipated in the MOSFET is as high as 0.23W. A 10mm x 10mm area of 1oz copper should be sufficient. This area of copper can be divided in many layers. In Hot Swap applications where load currents can be 2A, narrow PCB tracks exhibit more resistance than wider tracks and operate at elevated temperatures. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure HEAT SINK VDD OUT It is also important to put C1, the bypass capacitor for the INTVCC pin as close as possible between the INTVCC and GND. VIA TO SINK Additional Applications The LTC4217 has a wide operating range from 2.9V to 26.5V. The UV, OV and PG thresholds are set with few resistors. All other functions are independent of supply voltage. C GND 4217 F07 Figure 7. Recommended Layout Figure 8 shows a 3.3V application with a UV threshold of 2.87V, an OV threshold of 3.77V and a PG threshold of 3.05V. The last page includes a 24V application with a UV threshold of 19.9V, an OV threshold of 26.3V and a PG threshold of 20.75V. the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 0.5m/square. Small resistances add up quickly in high current applications. There are two VDD pins on opposite sides of the package that connect to the sense resistor and MOSFET. The PCB layout should be balanced and symmetrical to each VDD pin to balance current in the MOSFET bond wires. Figure 7 shows a recommended layout for the LTC4217. In addition to Hot Swap applications, the LTC4217 also functions as a backplane resident switch for removable cards (see Figure 9). Z1* R1 17.4k LTC4217FE FB UV R2 3.16k GATE FLT R5 14.7k + R6 10k CL 100F R7 10k OV R3 10k VOUT 3.3V 1.5A OUT VDD 3.3V UV = 2.87V OV = 3.77V PG = 3.05V PG ISET TIMER C1 1F INTVCC GND IMON ADC RMON 20k 4217 F08 *TVS Z1: DIODES INC. SMAJ17A Figure 8. 3.3V, 1.5A Card Resident Application 4217fg For more information www.linear.com/LTC4217 15 LTC4217 Applications Information 12V Z1* R7 10k R1 226k OUT VDD LTC4217DHC PG FB OV GATE R2 20k R5 150k R6 20k FLT 12V R4 20k UV C1 1F TIMER ISET INTVCC IMON GND VOUT 12V 2A R3 140k LOAD UV = 9.88V OV = 15.2V PG = 10.5V ADC RMON 20k 4217 F09 *TVS Z1: DIODES INC. SMAJ17A Figure 9. 12V, 2A Backplane Resident Application with Insertion Activated Turn-On 16 4217fg For more information www.linear.com/LTC4217 LTC4217 Package Description Please refer to http://www.linear.com/product/LTC4217#packaging for the most recent package drawings. DHC Package 16-Lead Plastic DFN (5mm x 3mm) (Reference LTC DWG # 05-08-1706 Rev O) 0.65 0.05 3.50 0.05 1.65 0.05 2.20 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 4.40 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 5.00 0.10 (2 SIDES) R = 0.20 TYP 3.00 0.10 (2 SIDES) 9 R = 0.115 TYP 0.40 0.10 16 1.65 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH 0.200 REF 0.75 0.05 0.00 - 0.05 8 1 0.25 0.05 0.50 BSC (DHC16) DFN 1103 4.40 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WJED-1) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4217fg For more information www.linear.com/LTC4217 17 LTC4217 Package Description Please refer to http://www.linear.com/product/LTC4217#packaging for the most recent package drawings. FE Package 20-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663 Rev K) Exposed Pad Variation CA 6.07 (.239) 6.40 - 6.60* (.252 - .260) 4.95 (.195) 4.95 (.195) DETAIL A 1.98 (.078) REF 20 1918 17 16 15 14 13 12 11 6.60 0.10 4.50 0.10 DETAIL A 2.74 (.108) 6.40 2.74 (.252) (.108) BSC SEE NOTE 4 0.45 0.05 1.05 0.10 0.65 BSC 1 2 3 4 5 6 7 8 9 10 6.07 (.239) RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.25 REF 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE 18 0.56 (.022) REF DETAIL A IS THE PART OF THE LEAD FRAME FEATURE FOR REFERENCE ONLY NO MEASUREMENT PURPOSE 1.20 (.047) MAX 0 - 8 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE20 (CA) TSSOP REV K 0913 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 4217fg For more information www.linear.com/LTC4217 LTC4217 Revision History (Revision history begins at Rev C) REV DATE DESCRIPTION C 12/09 Revise Features, Description and Typical Application PAGE NUMBER Revise Absolute Maximum Ratings Storage Temperature Range and Pin Configuration Revise Electrical Characteristics 1 2 3, 4 Revise Graph G11 6 Update Pin Functions 7 Update Functional Diagram 8 Update Operation Section Revise Figure 1 and Update Values and Equation in Applications Information Section 9 10-12, 14 D 1/11 Added H-grade to Absolute Maximum Ratings, Order Information, and Electrical Characteristics sections. E 6/11 Revised RISET in the Electrical Characteristics section. 4 F 02/16 Typical Application: Added SMAJ22A; increased INTVCC capacitor to 1F 1 Raised IGATE(DN) maxima from 340A to 400A (C-, I-grade) and from 355A to 500A (H-grade) Updated TPCs G08, G11 Increased bypass capacitance on INTVCC to 1F from 0.1F ISET Pin Function: Recommended minimum resistor value to be 2k Figure 1: Added Z1, CCOMP; updated C1, R1, RGATE Figures 6, 8: Added Z1; updated C1 to 1F Added Figure 9 G 04/16 2-4 4 5, 6 Multiple 7 10 14, 15 16 Changed TVS to SMAJ17A in application circuits 1, 10, 14, 15, 16 Clarified that operating temperature range refers to ambient 2 Added BWIMON and tD(FAULT) specifications 4 Updated INTVCC and ISET pin functions 7 Added equations to calculate MOSFET temperature 12 4217fg Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTC4217 19 LTC4217 Typical Application 24V, 1.5A Card Resident Application with Auto-Retry 24V * OUT VDD 158k LTC4217FE + FB 200k GATE UV 10k FLT 3.24k VOUT 24V 100F 1.5A UV = 19.9V OV = 26.3V PG = 20.75V 10k OV 10k PG TIMER ISET INTVCC IMON GND 1F ADC 20k *TVS: DIODES INC. SMAJ24A 4217 TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 LTC4211 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 LTC4212 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10 LTC4214 Negative Voltage, Hot Swap Controller Operates from 0V to -16V, MSOP-10 LTC4215 Hot Swap Controller with I2C Compatible Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage LTC4218 Single Channel, Hot Swap Controller Operates from 2.9V to 26.5V, Adjustable Current Limit, SSOP-16, and DFN-16 LT4220 Positive and Negative Voltage, Dual Channels, Hot Swap Controller Operates from 2.7V to 16.5V, SSOP-16 LTC4221 Dual Hot Swap Controller/Sequencer Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16 LTC4230 Triple Channels, Hot Swap Controller Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20 LTC4232 5A Integrated Hot Swap Controller Operates from 2.9V to 15V, Adjustable 10% Current Limit LTC4233 10A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Current Limit LTC4234 20A Guaranteed SOA Hot Swap Controller Operates from 2.9V to 15V, Adjustable 11% Current Limit Monitoring 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC4217 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC4217 4217fg LT 0416 REV G * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 2008