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1.0 Features
• Just-in-time customization of clock frequencies via internal non-volatile 128-bit serial EEPROM
• I2C™-bus serial interface
• Three on-chip PLLs with programmable reference and feedback dividers
• Four independently programmable muxes and post dividers
• Programmable power-down of all PLLs and output clock drivers
• Tristate outputs for board testing
• One PLL and two mux/post-divider combinations can be modified via SEL_CD input
• 5V to 3.3V operation
• Accepts 5MHz to 27MHz crystal resonators
2.0 Description
The FS6370 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three EEPROM-
programmable phase-locked loops (PLLs) driving four programmable muxes and post dividers provide a high degree of flexibility.
An internal EEPROM permits just-in-time factory programming of devices for end user requirements.
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
VSS
SEL_CD
PD/SCL
VSS
XIN
XOUT
OE/SDA
VDD MODE
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
VDD
FS6370
Figure 1: Pin Configuration
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I2C-bus
Interface
EEPROM
Power Down
Control
Post
Divider C
Post
Divider B
FS6370
PD/SCL
OE/SDA
Post
Divider A CLK_A
CLK_B
CLK_C
Reference
Oscillator PLL A
PLL B
MODE
XOUT
XIN
Mux B
Mux C
PLL C
Post
Divider D CLK_D
Mux D
Mux A
SEL_CD
Figure 2: Block Diagram
Table 1: Pin Descriptions
PPiinnTTyyppeeNNaammeeDDeessccrriippttiioonn
1 P VSS Ground
2DIUSEL_CD Selects one of two programmed PLL C, Mux C/D and post divider C/D combinations
3DI
UPD/SCL Power-down input (run mode) or serial interface clock input (program mode)
4 P VSS Ground
5 AI XIN Crystal oscillator feedback
6AO XOUT Crystal oscillator drive
7DI
UO OE/SDA Output enable input (run mode) or serial interface data input/output (program mode)
8 P VDD Power supply (5V to 3.3V)
9DI
UMODE Selects either program mode (low) or run mode (high)
10 DO CLK_D D clock output
11 P VSS Ground
12 DO CLK_C C clock output
13 DO CLK_B B clock output
14 PVDD Power supply (5V to 3.3V)
15 DO CLK_A A clock output
16 PVDD Power supply (5V to 3.3V)
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU= Input with Internal Pull-Up; DID= Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
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3.0 Functional Block Description
3
3.
.1
1 P
Ph
ha
as
se
e L
Lo
oc
ck
ke
ed
d L
Lo
oo
op
ps
s (
(P
PL
LL
Ls
s)
)
Each of the three on-chip PLLs is a standard phase- and frequency-locked loop architecture that multiplies a reference frequency to a desired frequency by
a ratio of integers. This frequency multiplication is exact.
As shown in Figure 3, each PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled
oscillator (VCO), and a feedback divider.
During operation, the reference frequency (fREF), generated by the on-board crystal oscillator, is first reduced by the reference divider. The divider value is
often referred to as the modulus, and is denoted as NRfor the reference divider. The divided reference is fed into the PFD.
The PFD controls the frequency of the VCO (fVCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable
frequency clock source for the PLL. The output of the VCO is fed back to the PFD through the feedback divider (the modulus is denoted by NF) to close
the loop.
Reference
Divider
(NR)Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider (NF)
Loop
Filter
REFDIV[7:0]
FBKDIV[10:0]
LFTC
CP
fREF
fVCO
Voltage
Controlled
Oscillator
fPD
Figure 3: PLL Block Diagram
The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the
PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is:
÷
÷
ø
ö
ç
ç
è
æ
=
R
F
REFVCO
N
N
ff
3.1.1 Reference Divider
The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to
the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value.
A divide-by-256 can also be achieved by programming the eight bits to 00h.
3.1.2 Feedback Divider
The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a pre-scaler) is placed between the VCO and
the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at
any speed that the VCO can achieve and reduces the overall power consumption of the divider.
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For example, a fixed divide-by-eight pre-scaler could have been used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective
modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input-frequency-to-
output-frequency ratio without making both the reference and feedback divider values comparatively large. Generally, very large values are undesirable
as they degrade the bandwidth of the PLL, increasing phase jitter and acquisition time.
To understand the operation of the feedback divider, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded with the dual-
modulus pre-scaler. The A-counter controls the modulus of the pres-caler. If the value programmed into the A-counter is A, the pre-scaler will be set to
divide by N+1 for A pre-scaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the A-counter, and the cycle begins again.
Note that N=8, and A and M are binary numbers.
Dual
Modulus
Prescaler
A
Counter
M
Counter
fVCO fPD
FBKDIV[10:3]FBKDIV[2:0]
Figure 4: Feedback Divider
Suppose that the A-counter is programmed to zero. The modulus of the pre-scaler will always be fixed at N; and the entire modulus of the feedback divider
becomes MxN.
Next, suppose that the A-counter is programmed to a one. This causes the pre-scaler to switch to a divide-by-N+1 for its first divide cycle and then revert
to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the feedback divider. The overall modulus is
now seen to be equal to MxN+1.
This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A<M.
3.1.3 Feedback Divider Programming
For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the M-counter. Therefore,
not all divider moduli below 56 are available for use. This is shown in Table 2.
Above a modulus of 56, the feedback divider can be programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
MM--CCoouunntteerr::
FFBBKKDDIIVV[[1100::33]]
AA--CCoouunntteerr:: FFBBKKDDIIVV[[22::00]]
000000000011001100001111110000110011111100111111
00000001 8 9 - - - - - -
00000010 16 17 18 -----
00000011 24 25 26 27 - - - -
00000100 32 33 34 35 36 ---
00000101 40 41 42 43 44 45 - -
00000110 48 49 50 51 52 53 54 -
00000111 56 57 58 59 60 61 62 63
FFeeeeddbbaacckk DDiivviiddeerr MMoodduulluuss
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3
3.
.2
2 P
Po
os
st
t D
Di
iv
vi
id
de
er
r M
Mu
ux
xe
es
s
As shown in Figure 2, a mux in front of each post divider stage can select from any one of the three PLL frequencies or the reference frequency. The mux
selection is controlled by bits in the EEPROM or the control registers.
The input frequency on two of the four multiplexers (muxes C and D in Figure 2) can be altered without reprogramming by a logic-level input on the
SEL_CD pin.
3
3.
.3
3 P
Po
os
st
t D
Di
iv
vi
id
de
er
rs
s
A post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output
clock speeds that the device is required to generate. Second, it changes the basic PLL equation to:
where NP is the post divider modulus. The extra integer in the denominator permits more flexibility in the programming of the loop for many applications
where frequencies must be achieved exactly.
The modulus on two of the four post dividers (post dividers C and D in Figure 2) can be altered without reprogramming by a logic level on the SEL_CD
pin.
÷
÷
ø
ö
ç
ç
è
æ
÷
÷
ø
ö
ç
ç
è
æ
=
P
R
F
REFCLK NN
N
ff 1
4.0 Device Operation
The FS6370 has two modes of operation:
• P
Pr
ro
og
gr
ra
am
m m
mo
od
de
e:
:during which either the EEPROM or the FS6370 control registers can be programmed directly with the desired PLL settings
• R
Ru
un
n m
mo
od
de
e:
:where the PLL settings stored the EEPROM are transferred to the FS6370 control registers on power-up, and the device then operates based
on those settings
Note that the EEPROM locations are not physically the same registers used to control the FS6370.
Direct access to either the EEPROM or the FS6370 control registers is achieved in program mode. The EEPROM register contents are automatically
transferred to the FS6370 control registers in normal device operation (run mode).
4
4.
.1
1 M
MO
OD
DE
E P
Pi
in
n
The MODE pin controls the mode of operation. A logic-low places the FS6370 in program mode. A logic-high puts the device in run mode. A pull-up on
this pin defaults the device into run mode.
Reprogramming of either the control registers or the EEPROM is permitted at any time if the MODE pin is a logic-low.
Note, however, that a logic-high state on the MODE pin is latched so that only one transfer of EEPROM data to the FS6370 control registers can occur.
If a second transfer of EEPROM data into the FS6370 is desired, power (VDD) must be removed and reapplied to the device.
The MODE pin also controls the function of the PD/SCL and OE/SDA pins. In run mode, these two pins function as power-down (PD) and output enable
(OE) controls. In program mode, the pins function as the I2C interface for clock (SCL) and data (SDA).
4
4.
.2
2 S
SE
EL
L_
_C
CD
D P
Pi
in
n
The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D, and post dividers C and D without having to reprogram the device. A
logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the SEL_CD pin selects the control bits with
"C2" or "D2" notation, per Table 3.
Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output, especially if the post-divider(s) is/are
altered.
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4
4.
.3
3 O
Os
sc
ci
il
ll
la
at
to
or
r O
Ov
ve
er
rd
dr
ri
iv
ve
e
For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT
and XIN must be left unconnected (float).
For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times, and can swing rail-to-
rail.
If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01µF or 0.1µF capacitor. A minimum 1V peak-to-
peak signal is required to drive the internal differential oscillator buffer.
5.0 Run Mode
If the MODE pin is set to a logic-high, the device enters the run mode. The high state is latched (see MODE pin). The FS6370 then copies the stored
EEPROM data into its control registers and begins normal operation based on that data when the self-load is complete.
The self-load process takes about 89,000 clocks of the crystal oscillator. During the self-load time, all clock outputs are held low. At a reference frequency
of 27MHz, the self-load takes about 3.3ms to complete.
If the EEPROM is empty (all zeros), the crystal reference frequency provides the clock for all four outputs.
No external programming access to the FS6370 is possible in run mode. The dual-function PD/SCL and OE/SDA pins become a power-down (PD) and
output enable (OE) control, respectively.
5
5.
.1
1 P
Po
ow
we
er
r-
-D
Do
ow
wn
n a
an
nd
d O
Ou
ut
tp
pu
ut
t E
En
na
ab
bl
le
e
A logic-high on the PD/SCL pin powers down only those portions of the FS6370 which have their respective power-down control bits enabled. Note that
the PD/SCL pin has an internal pull-up.
When a post divider is powered down, the associated output driver is forced low. When all PLLs and post dividers are powered down the crystal oscillator
is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high.
A logic-low on the OE/SDA pin tristates all output clocks. Note that this pin has an internal pull-up.
6.0 Program Mode
If the MODE pin is logic-low, the device enters the program mode. All internal registers are cleared to zero, delivering the crystal frequency to all outputs.
The device allows programming of either the internal 128-bit EEPROM or the on-chip control registers via I2C control over the PD/SCL and OE/SDA pins.
The EEPROM and the FS6370 act as two separate parallel devices on the same on-chip I2C-bus. Choosing either the EEPROM or the device control registers
is done via the I2C device address.
The dual-function PD/SCL and OE/SDA pins become the serial data I/O (SDA) and serial clock input (SCL) for normal I2C communications. Note that power-
down and output enable control via the PD/SCL and OE/SDA pins is not available.
6
6.
.1
1 E
EE
EP
PR
RO
OM
MP
Pr
ro
og
gr
ra
am
mm
mi
in
ng
g
Data must be loaded into the EEPROM in a most-significant-bit (MSB) to least-significant-bit (LSB) order. The register map of the EEPROM is noted in
Table 3.
The device address of the EEPROM is:
AA66AA55AA44AA33AA22AA11AA00
1 0 1 0 X X X
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6.1.1 Write Operation
The EEPROM can only be written to with the random register write procedure (see Section 8.2.2). The procedure consists of the device address, the
register address, a R/W bit, and one byte of data.
Following the STOP condition, the EEPROM initiates its internally timed 4ms write cycle, and commits the data byte to memory. No acknowledge signals
are generated during the EEPROM internal write cycle.
If a stop bit is transmitted before the entire write command sequence is complete, then the command is aborted and no data is written to memory.
If more than eight bits are transmitted before the stop bit is sent, then the EEPROM will clear the previously loaded data byte and will begin loading the
data buffer again.
6.1.2 Acknowledge Polling
The EEPROM does not acknowledge while it internally commits data to memory. This feature can be used to increase data throughput by determining
when the internal write cycle is complete.
The process is to initiate the random register write procedure with a START condition, the EEPROM device address, and the write command bit (R/W=0).
If the EEPROM has completed its internal 4ms write cycle, the EEPROM will acknowledge on the next clock, and the write command can continue.
If the EEPROM has not completed the internal 4ms write cycle, the random register write procedure must be restarted by sending the START condition,
device address and R/W bit. This sequence must be repeated until the EEPROM acknowledges.
6.1.3 Read Operation
The EEPROM supports both the random register read procedure and the sequential register read procedure (both are outlined in Section 6).
For sequential read operations, the EEPROM has an internal address pointer that increments by one at the end of each read operation. The pointer directs
the EEPROM to transmit the next sequentially addressed data byte, allowing the entire memory contents to be read in one operation.
6
6.
.2
2 D
Di
ir
re
ec
ct
t R
Re
eg
gi
is
st
te
er
r P
Pr
ro
og
gr
ra
am
mm
mi
in
ng
g
The FS6370 control registers may be directly accessed by simply using the FS6370 device address in the read or write operations. The operation of the
device will follow the register values. The register map of the FS6370 is identical to that of the EEPROM shown in Table 3.
The FS6370 supports the random read and write procedures, as well as the sequential read and write procedures described in Section 8.
The device address for the FS6370 is:
AA66AA55AA44AA33AA22AA11AA00
1011100
7.0 Cost Reduction Migration Path
The FS6370 is compatible with the programmable register-based FS6377 or a fixed-frequency ROM-based clock generator. Attention should be paid to
the board layout if a migration path to either of these devices is desired.
7
7.
.1
1 P
Pr
ro
og
gr
ra
am
mm
mi
in
ng
g M
Mi
ig
gr
ra
at
ti
io
on
n P
Pa
at
th
h
If the design can support I2C programming overhead, a cost reduction from the EEPROM-based FS6370 to the register-based FS6377 is possible.
Figure 5 shows the five pins that may not be compatible between the various devices if programming of the FS6370 or the FS6377 is desired.
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1 16
2
3
4
5
6
7
8
15
14
13
12
11
10
9
VSS
(FS6370)
SEL_CD
VSS
XIN
XOUT
VDD
CLK_D
VSS
CLK_C
CLK_B
VDD
CLK_A
FS6370 / FS6377
SDA
(FS6377)
PD/SCL
(FS6370)
PD
(FS6377)
OE/SDA
(FS6370)
OE
(FS6377)
MODE
(FS6370)
ADDR
(FS6377)
VDD
(FS6370)SCL
(FS6377)
Figure 5: FS6370 to FS6377
7
7.
.2
2 N
No
on
n-
-P
Pr
ro
og
gr
ra
am
mm
mi
in
ng
g M
Mi
ig
gr
ra
at
ti
io
on
n P
Pa
at
th
h
If the design has solidified on a particular EEPROM programming pattern, the EEPROM pattern can be hard-coded into a ROM-based device. For high-
volume requirements, a ROM-based device offers significant cost savings over the FS6370. Contact an AMIS sales representative for more detail.
8.0 I2C-bus Control Interface
This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be controlled by a master
device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a
slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device
that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver.
I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-
low corresponds to ground (VSS).
8
8.
.1
1 B
Bu
us
s C
Co
on
nd
di
it
ti
io
on
ns
s
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the
clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following
bus conditions are defined by the I2C-bus protocol.
8.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.
8.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START
condition.
8.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP
condition.
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8.1.4 Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs.
The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and
STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first 16 bytes
will overflow into the first register, then the second, and so on, in a first-in, first-overwritten fashion.
8.1.5 Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock
pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock
pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave.
In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
8
8.
.2
2 I
I2
2C
C-
-b
bu
us
s O
Op
pe
er
ra
at
ti
io
on
n
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The device accepts the following
I2C-bus commands.
8.2.1 Device Address
After generating a START condition, the bus master broadcasts a seven-bit device address followed by a R/W bit.
The device address of the FS6370 is:
Any one of eight possible addresses are available for the EEPROM. The least significant three bits are don't care's.
AA66AA55AA44AA33AA22AA11AA00
1011100
AA66AA55AA44AA33AA22AA11AA00
1 0 1 0 X X X
8.2.2 Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-
bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its
device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight
bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
8.2.3 Random Register Read Procedure
Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-
bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave
device acknowledges its device address. The register address is then written into the slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not
until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but
does generate a STOP condition.
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8.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This
procedure is more efficient than the random register write if several registers must be written.
To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device
that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer.
Following an acknowledge by the slave, the master is allowed to write up to 16 bytes of data into the addressed register before the register address
pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent.
Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur.
Registers are therefore updated at different times during a sequential register write.
8.2.5 Sequential Register Read Procedure
Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read.
This procedure is more efficient than the random register read if several registers must be read.
To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates
to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written
into the slave's address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not
until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address, and then transmits all 16 bytes of data starting with the initial addressed register. The register
address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer
but does generate a STOP condition.
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AAAWS P
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Data
Acknowledge
Data
STOP Command
AcknowledgeAcknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS DATA DATA DATA
Figur e 8: Sequential Register Write Procedur e
AWS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge READ Command
NO Acknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address 7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS AR A PS DEVICE ADDRESS DATA DATA
Repeat START
Figur e 9: Sequential Register Read Pr ocedur e
AA DATAW A
From bus host
to device
SREGISTER ADDRESS P
From device
to bus host
DEVICE ADDRESS
Register Address
Acknowledge STOP Condition
Data
Acknowledge
Acknowledge
START
Command WRITE Command
7-bit Receive
Device Address
Figur e 6: Random Register Write Procedur e
AR AAAWS REGISTER ADDRESS PS DEVICE ADDRESS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge READ Command
Acknowledge
Data
NO Acknowledge
STOP Condition
From bus host
to device From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS DATA
Repeat START
Figur e 7: Random Register Read Pr ocedur e
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AAddddrreessssBBiitt 77BBiitt 66BBiitt 55BBiitt 44BBiitt 33BBiitt 22BBiitt 11 BBiitt 00
BByyttee 1155MUX_D2[1:0]
(selected via SEL_CD = 1)
MUX_C2[1:0]
(selected via SEL_CD = 1) PDPOST_D PDPOST_C PDPOST_B PDPOST_A
BByyttee 1144POST_D2[3:0]
(selected via SEL_CD = 1)
POST_C2[3:0]
(selected via SEL_CD = 1)
BByyttee 1133POST_D1[3:0]
(selected via SEL_CD = 0)
POST_C1[3:0]
(selected via SEL_CD = 0)
BByyttee 1122POST_B[3:0] POST_A[3:0]
BByyttee 1111MUX_D1[1:0]
(selected via SEL_CD = 0) Reserved (0) LFTC_C2
(SEL_CD=1)
CP_C2
(SEL_CD=1)
FBKDIV_C2[10:8]
M-Counter
(selected via SEL_CD pin = 1)
BByyttee 1100FBKDIV_C2[7:3]
M-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C2[2:0]
A-Counter
(selected via SEL_CD pin = 1)
BByyttee 99REFDIV_C2[7:0]
(selected via SEL_CD pin = 1)
BByyttee 88MUX_C1[1:0]
(selected via SEL_CD = 0) PDPLL_C LFTC_C1
(SEL_CD=0)
CP_C1
(SEL_CD=0)
FBKDIV_C1[10:8]
M-Counter
(selected via SEL_CD = 0)
BByyttee 77FBKDIV_C1[7:3]
M-Counter
(selected via SEL_CD = 0)
FBKDIV_C1[2:0]
A-Counter
(selected via SEL_CD = 1)
BByyttee 66REFDIV_C1[7:0]
(selected via SEL_CD = 0)
BByyttee 55MUX_B[1:0] PDPLL_B LFTC_B CP_B FBKDIV_B[10:8]
M-Counter
BByyttee 44FBKDIV_B[7:3]
M-Counter
FBKDIV_B[2:0]
A-Counter
BByyttee 33REFDIV_B[7:0]
BByyttee 22MUX_A[1:0] PDPLL_A LFTC_A CP_A FBKDIV_A[10:8]
M-Counter
BByyttee 11FBKDIV_A[7:3]
M-Counter
FBKDIV_A[2:0]
A-Counter
BByyttee 00REFDIV_A[7:0]
9.0 Programming Information
Table 3: Register Map (Note: All register bits are cleared to zero on power-up.)
9
9.
.1
1 C
Co
on
nt
tr
ro
ol
l B
Bi
it
t A
As
ss
si
ig
gn
nm
me
en
nt
ts
s
If any PLL control bit is altered during device operation, including those bits controlling the reference and feedback dividers, the output frequency will
slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed loop filter time constant.
However, any programming changes to any mux or post divider control bits will cause a glitch on an operating clock output.
9.1.1 Power-Down
All power-down functions are controlled by enable bits. That is, the bits select which portions of the FS6370 to power-down when the PD input is asserted.
If the power-down bit contains a one, the related circuit will shut down if the PD pin is high (run mode only). When the PD pin is low, power is enabled
to all circuits.
If the power-down bit contains a zero, the related circuit will continue to function regardless of the PD pin state.
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Table 4: Power-Down Bits
NNaammeeDDeessccrriippttiioonn
PPoowweerr--DDoowwnn PPLLLL AA
PPDDPPLLLL__AA
(Bit 21)
Bit = 0 Power on
Bit = 1 Power off
PPoowweerr--DDoowwnn PPLLLL BB
PPDDPPLLLL__BB
(Bit 45)
Bit = 0 Power on
Bit = 1 Power off
PPoowweerr--DDoowwnn PPLLLL CC
PPDDPPLLLL__CC
(Bit 69)
Bit = 0 Power on
Bit = 1 Power off
Reserved (0)
(Bit 69) Set these reserved bits to zero (0)
PPoowweerr--DDoowwnn PPOOSSTT ddiivviiddeerr AA
PPDDPPOOSSTT__AA
(Bit 120)
Bit = 0 Power on
Bit = 1 Power off
PPoowweerr--DDoowwnn PPOOSSTT ddiivviiddeerr BB
PPDDPPOOSSTT__BB
(Bit 121)
Bit = 0 Power on
Bit = 1 Power off
PPoowweerr--DDoowwnn PPOOSSTT ddiivviiddeerr CC
PPDDPPOOSSTTCC
(Bit 122)
Bit = 0 Power on
Bit = 1 Power off
PPoowweerr--DDoowwnn PPOOSSTT ddiivviiddeerr DD
PPDDPPOOSSTTDD
(Bit 123)
Bit = 0 Power on
Bit = 1 Power off
Table 5: Divider Control Bits
NNaammeeDDeessccrriippttiioonn
RREEFFDDIIVV__AA[[77::00]]
(Bits 7-0) RReeffeerreennccee DDiivviiddeerr AA ((NNRR))
RREEFFDDIIVV__BB[[77::00]]
(Bits 31-24) RReeffeerreennccee DDiivviiddeerr BB ((NNRR))
RREEFFDDIIVV__CC11[[77::00]]
(Bits 55-48)
RReeffeerreennccee DDiivviiddeerr CC11 ((NNRR))
selected when the SEL-CD pin = 0
RREEFFDDIIVV__CC22[[77::00]]
(Bits 79-72)
RReeffeerreennccee DDiivviiddeerr CC22 ((NNRR))
selected when the SEL-CD pin = 1
FFeeeeddbbaacckk DDiivviiddeerr AA ((NNFF))
FFBBKKDDIIVV__AA[[1100::00]]
(Bits 18-8)
FBKDIV_A[2:0] A-Counter value
FBKDIV_A[10:3] M-Counter value
FFeeeeddbbaacckk DDiivviiddeerr BB ((NNFF))
FFBBKKDDIIVV__BB[[1100::00]]
(Bits 42-32)
FBKDIV_B[2:0] A-Counter value
FBKDIV_B[10:3] M-Counter value
FFeeeeddbbaacckk DDiivviiddeerr CC11 ((NNFF))
selected when the SEL-CD pin = 0
FFBBKKDDIIVV__CC11[[1100::00]]
(Bits 66-56)
FBKDIV_C1[2:0] A-Counter value
FBKDIV_C1[10:3] M-Counter value
FFeeeeddbbaacckk DDiivviiddeerr CC22 ((NNFF))
selected when the SEL-CD pin = 1
FFBBKKDDIIVV__CC22[[1100::00]]
(Bits 90-80)
FBKDIV_C2[2:0] A-Counter value
FBKDIV_C2[10:3] M-Counter value
Table 6: Post Divider Control Bits
NNaammeeDDeessccrriippttiioonn
PPOOSSTT__AA[[33::00]
(Bits 99-96) PPOOSSTT ddiivviiddeerr AA (see Table 7)
PPOOSSTT__BB[[33::00]]
(Bits 103-100) PPOOSSTT ddiivviiddeerr BB(see Table 7)
PPOOSSTT__CC11[[33::00]]
(Bits 107-104)
PPOOSSTT ddiivviiddeerr CC11(see Table 7)
selected when the SEL_CD pin = 0
PPOOSSTT__CC22[[33::00]]
(Bits 115-112)
PPOOSSTT ddiivviiddeerr CC22(see Table 7)
selected when the SEL_CD pin = 1
PPOOSSTT__DD11[[33::00]]
(Bits 111-108)
PPOOSSTT ddiivviiddeerr DD11(see Table 7)
selected when the SEL_CD pin = 0
PPOOSSTT__DD22[[33::00]]
(Bits 119-116)
PPOOSSTT ddiivviiddeerr DD22(see Table 7)
selected when the SEL_CD pin = 1
Table 7: Post Divider Modulus
BBiitt [[33]]BBiitt [[22]]BBiitt [[11]]BBiitt [[00]]DDiivviiddee BByy
00001
00012
00103
00114
01005
01016
01108
01119
100010
100112
101015
101116
110018
110120
111025
111150
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NNaammeeDDeessccrriippttiioonn
LLoooopp FFiilltteerr TTiimmee CCoonnssttaanntt AA
LLFFTTCC__AA
(Bit 20)
Bit = 0 Short time constant: 7ms
Bit = 1 Long time constant: 20ms
LLoooopp FFiilltteerr TTiimmee CCoonnssttaanntt BB
LLFFTTCC__BB
(Bit 44)
Bit = 0 Short time constant: 7ms
Bit = 1 Long time constant: 20ms
LLoooopp FFiilltteerr TTiimmee CCoonnssttaanntt CC11
selected when the SEL_CD pin = 0
LLFFTTCC__CC11
(Bit 68)
Bit = 0 Short time constant: 7ms
Bit = 1 Long time constant: 20ms
LLoooopp FFiilltteerr TTiimmee CCoonnssttaanntt CC22
selected when the SEL_CD pin = 1
LLFFTTCC__CC22
(Bit 92)
Bit = 0 Short time constant: 7ms
Bit = 1 Long time constant: 20ms
CChhaarrggee PPuummpp AA
CCPP__AA
(Bit 19)
Bit = 0 Current = 2mA
Bit = 1 Current = 10mA
CChhaarrggee PPuummpp BB
CCPP__BB
(Bit 43)
Bit = 0 Current = 2mA
Bit = 1 Current = 10mA
CChhaarrggee PPuummpp CC11
selected when the SEL_CD pin = 0
CCPP__CC11
(Bit 67)
Bit = 0 Current = 2mA
Bit = 1 Current = 10mA
CChhaarrggee PPuummpp CC22
selected when the SEL_CD pin = 1
CCPP__CC22
(Bit 91)
Bit = 0 Current = 2mA
Bit = 1 Current = 10mA
NNaammeeDDeessccrriippttiioonn
MMUUXX AA FFrreeqquueennccyy SSeelleecctt
MMUUXX__AA[[11::00]]
(Bits 23-22)
Bit 23 Bit 22
0 0 Reference frequency
0 1 PLL A frequency
1 0 PLL B frequency
1 1 PLL C frequency
MMUUXX BB FFrreeqquueennccyy SSeelleecctt
MMUUXX__BB[[11::00]]
(Bits 47-46)
Bit 47 Bit 46
0 0 Reference frequency
0 1 PLL A frequency
1 0 PLL B frequency
1 1 PLL C frequency
MMUUXX CC11 FFrreeqquueennccyy SSeelleecctt
selected when the SEL_CD pin = 0
MMUUXX__CC11[[11::00]]
(Bits 71-70)
Bit 71 Bit 70
0 0 Reference frequency
0 1 PLL A frequency
1 0 PLL B frequency
1 1 PLL C frequency
MMUUXX CC22 FFrreeqquueennccyy SSeelleecctt
selected when the SEL_CD pin = 1
MMUUXX__CC22[[11::00]]
(Bits 125-124)
Bit 125 Bit 124
0 0 Reference frequency
0 1 PLL A frequency
1 0 PLL B frequency
1 1 PLL C frequency
MMUUXX DD11 FFrreeqquueennccyy SSeelleecctt
selected when the SEL_CD pin = 0
MMUUXX__DD11[[11::00]]
(Bits 95-94)
Bit 95 Bit 94
0 0 Reference frequency
0 1 PLL A frequency
1 0 PLL B frequency
1 1 PLL C frequency
MMUUXX DD22 FFrreeqquueennccyy SSeelleecctt
selected when the SEL_CD pin = 1
MMUUXX__DD22[[11::00]]
(Bits 127-126)
Bit 127 Bit 126
0 0 Reference frequency
0 1 PLL A frequency
1 0 PLL B frequency
1 1 PLL C frequency
Table 8: PLL Tuning Bits Table 9: Mux Select Bits
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10.0 Electrical Specifications
Table 10: Absolute Maximum Ratings
PPaarraammeetteerrSSyymmbboollMMiinn..MMaaxx..UUnniittss
Supply Voltage, dc (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc V1VSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (VI< 0 or VI> VDD) IIK -50 50 mA
Output Clamp Current, dc (VI< 0 or VI> VDD) IOK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ150 °C
Re-Flow Solder Profile Per IPC/JEDEC
J-STD-020B
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a
high-energy electrostatic discharge.
PPaarraammeetteerrSSyymmbboollCCoonnddiittiioonnss//DDeessccrriippttiioonnMMiinn..TTyypp..MMaaxx..UUnniittss
Supply Voltage VDD
5V ± 10% 4.5 55.5 V
3.3V ± 10% 33.3 3.6
Ambient Operating Temperature Range TA070 °C
Crystal Resonator Frequency fXIN 527 MHz
Crystal Resonator Load Capacitance CXL Parallel resonant, AT cut 18 pF
Serial Data Transfer Rate Standard mode 10 100 kb/s
Output Driver Load Capacitance CL15 pF
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the
device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect
device performance, functionality and reliability.
Table 11: Operating Conditions
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Table 12: DC Electrical Specifications
PPaarraammeetteerrSSyymmbboollCCoonnddiittiioonnss//DDeessccrriippttiioonnMMiinn..TTyypp..MMaaxx..UUnniittss
OOvveerraallll
Supply Current, Dynamic IDD VDD = 5.5V, fCLK = 50MHz, CL= 15pF
See Figure 11 for more information
43 mA
Supply Current, Write IDD(write)
Additional operating current demand,
EEPROM program mode, VDD = 5.5V 2mA
Supply Current, Read IDD(read)
Additional operating current demand,
EEPROM program mode, VDD = 5.5V 1mA
Supply Current, Static IDDL VDD = 5.5V, powered down via PD pin 0.3 mA
DDuuaall FFuunnccttiioonn II//OO ((PPDD//SSCCLL,, OOEESSDDAA))
High-Level Input Voltage VIH
Run mode (PD, OE) VDD = 5.5V 3.85 VDD+0.3
V
VDD = 3.6V 2.52 VDD+0.3
Register program mode (SDA, SCL) VDD = 5.5V 3.85 VDD+0.3
VDD = 3.6V 2.52 VDD+0.3
EEPROM program mode (SDA, SCL) VDD = 5.5V 3.85 VDD+0.3
VDD = 3.6V 2.52 VDD+0.3
Low-Level Input Voltage VIL
Run mode (PD, OE) VDD = 5.5V VSS-0.3 1.65
V
VDD = 3.6V VSS-0.3 1.08
Register program mode (SDA, SCL) VDD = 5.5V VSS-0.3 1.65
VDD = 3.6V VSS-0.3 1.08
EEPROM program mode (SDA, SCL) VDD = 5.5V VSS-0.3 1.65
VDD = 3.6V VSS-0.3 1.08
Hysteresis Voltage Vhys
Run mode (PD, OE) VDD = 5.5V 2.20
V
VDD = 3.6V 1.44
Register program mode (SDA, SCL) VDD = 5.5V 2.20
VDD = 3.6V 1.44
EEPROM program mode (SDA, SCL) VDD = 5.5V 0.275
VDD = 3.6V 0.18
High-Level Input Current IIH
Run/register program mode -1 1mA
EEPROM program mode -1 1
Low-Level Input Current (pull-up) IIL VIL = 0V -20 -36 -80 mA
Low-Level Output Sink Current (SDA) IOL
Run/register program mode, VOL = 0.4V 26 mA
EEPROM program mode, VOL = 0.4V 3.0
MMooddee aanndd FFrreeqquueennccyy SSeelleecctt IInnppuuttss ((MMOODDEE,, SSEELL__CCDD))
High-Level Input Voltage VIH
VDD = 5.5V 2.4 VDD+0.3 V
VDD = 3.6V 2.0 VDD+0.3
Low-Level Input Voltage VIL
VDD = 5.5V VSS-0.3 0.8 V
VDD = 3.6V VSS-0.3 0.8
High-Level Input Current IIH -1 1 mA
Low-Level Input Current (pull-up) IIL -20 -36 -80 mA
CCrryyssttaall OOsscciillllaattoorr FFeeeeddbbaacckk ((XXIINN))
Threshold Bias Voltage VTH
VDD = 5.5V 2.9 V
VDD = 3.6V 1.7
High-Level Input Current IIH
VDD = 5.5V 54 mA
VDD = 5.5V, oscillator powered down 515 mA
Low-Level Input Current IIL -25 -54 -75 mA
Crystal Loading Capacitance* CL(xtal) As seen by an external crystal connected to XIN and XOUT 18 pF
Input Loading Capacitance* CL(XIN) As seen by an external clock driver on XOUT; XIN
unconnected 36 pF
CCrryyssttaall OOsscciillllaattoorr DDrriivvee ((XXOOUUTT))
High-Level Output Source Current IOH VDD = V(XIN) = 5.5V, VO= 0V 10 21 30 mA
Low-Level Output Sink Current IOL VDD = 5.5V, V(XIN) = V0= 5.5V -10 -21 -30 mA
CClloocckk OOuuttppuuttss ((CCLLKK__AA,, CCLLKK__BB,, CCLLKK__CC,, CCLLKK__DD))
High-Level Output Source Current IOH VO= 2.4V -125 mA
Low-Level Output Sink Current IOL VO= 0.4V 23 mA
Output Impedance ZOH VO= 0.5VDD; output driving high 29 W
ZOL VO= 0.5VDD; output driving low 27
Tristate Output Current IZ-10 10 mA
Short Circuit Source Current* ISCH VDD = 5.5V, VO= 0V; shorted for 30s, max -150 mA
Short Circuit Sink Current* ISCL VDD = VO= 5.5V; shorted for 30s, max 123 mA
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not
currently production tested to any specific limits. Min. and Max. characterization data are ± 3sfrom typical. Negative currents indicate current flows out of the device.
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FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
VVoollttaaggee
((VV))
LLooww DDrriivvee CCuurrrreenntt ((mmAA))VVoollttaaggee
((VV))
HHiigghh DDrriivvee CCuurrrreenntt ((mmAA))
MMiinn..TTyypp..MMaaxx..MMiinn..TTyypp..MMaaxx..
0 0 0 0 0 -87 -112 -150
0.2 911 12 0.5 -85 -110 -147
0.5 22 25 29 1-83 -108 -144
0.7 29 34 40 1.5 -80 -104 -139
139 46 55 2-74 -97 -131
1.2 44 52 64 2.5 -65 -88 -121
1.5 51 61 76 2.7 -61 -84 -116
1.7 55 66 83 3-53 -77 -108
260 73 92 3.2 -48 -71 -102
2.2 62 77 97 3.5 -39 -62 -92
2.5 65 81 104 3.7 -32 -55 -85
2.7 65 83 108 4-21 -44 -74
366 85 112 4.2 -13 -36 -65
3.5 67 87 117 4.5 0-24 -52
468 88 119 4.7 -15 -43
4.5 69 89 120 5 0 -28
591 121 5.2 -11
5.5 123 5.5 0
-200
-150
-100
-50
0
50
100
150
- 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Output Current (mA)
MIN
TYP
MAX
The data in this table represents nominal characterization data only.
Figure 10: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs
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FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
0
10
20
30
40
50
60
70
80
90
100
110
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200
Output Frequency (MHz)
Dynamic Current (mA)
Figure 11: Dynamic Current vs. Output Frequency
VDD = 5.0V; Reference Frequency = 27.00MHz; VCO Frequency = 200MHz, CL= 17pF except where noted
Output Frequency (MHz)
Dynamic Current (mA)
VDD = 3.3V; Reference Frequency = 27.00MHz; VCO Frequency = 100MHz, CL= 17pF except where noted
All outputs at the same frequency
All outputs at 200MHz
except output under test
All outputs at the same
frequency, CL = OpF
All outputs at 4MHz
except output under test
All outputs off except output under test
All outputs off except output under test, CL= OpF
All outputs at the same frequency
All outputs at 100MHz
except output under test
All outputs off except
output under test
All outputs at the same
frequency, CL= OpF
All outputs at 2MHz
except output under test
All outputs off except output under test, CL= OpF
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FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
Table 13: AC Timing Specifications
PPaarraammeetteerrSSyymmbboollCCoonnddiittiioonnss//DDeessccrriippttiioonnCClloocckk ((MMHHzz))MMiinn..TTyypp..MMaaxx..UUnniittss
OOvveerraallll
EEPROM Write Cycle Time twc 4ms
Output Frequency* fO
VDD = 5.5V 0.8 150 MHz
VDD = 3.6V 0.8 100
VCO Frequency* fVCO
VDD = 5.5V 40 230 MHz
VDD = 3.6V 40 170
VCO Gain* AVCO 400 MHz/V
Loop Filter Time Constant* LFTC bit = 0 7ms
LFTC bit = 1 20
Rise Time* tr
VO = 0.5V to 4.5V; CL= 15pF 2.0 ns
VO = 0.3V to 3.0V; CL= 15pF 2.1
Fall Time* tf
VO = 4.5V to 0.5V; CL= 15pF 1.8 ns
VO = 3.0V to 0.3V; CL= 15pF 1.9
Tristate Enable Delay* tPZL, tPZH 1 8 ns
Tristate Disable Delay* tPZL, tPZH 18ns
Clock Stabilization Time* tSTB
Output active from power-up, RUN mode via PD pin 100 ms
After last register is written, register program mode 1ms
DDiivviiddeerr MMoodduulluuss
Feedback Divider NFSee also Table 2 82047
Reference Divider NR1255
Post Divider NPSee also Table 8 150
CClloocckk OOuuttppuuttss ((PPLLLL AA cclloocckk vviiaa CCLLKK__AA ppiinn))
Duty Cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 45 55 %
Jitter, Long Term (sy(t))* tj(LT)
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPX=50, no other PLLs active 100 45
ps
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, =14.318MHz, NF=220, NR=63,
NPX=50, all other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) 50 165
Jitter, Period (peak-peak)* tj(DP)
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no
other PLLs active 100 110
ps
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, all
other PLLs active (B=60MHz, C=40MHz, D=14.318MHz) 50 390
CClloocckk OOuuttppuuttss ((PPLLLL BB cclloocckk vviiaa CCLLKK__BB ppiinn))
Duty Cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 45 55 %
Jitter, Long Term (sy(t))* Tj(LT)
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, no other PLLs active 100 45
ps
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, all other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) 60 75
Jitter, Period (peak-peak)* TJ(DP)
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no
other PLLs active 100 120
ps
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all
other PLLs active (A=50MHz, C=40MHz, D=14.318MHz) 60 400
CClloocckk OOuuttppuuttss ((PPLLLL__CC cclloocckk vviiaa CCLLKK__CC ppiinn))
Duty Cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 100 45 55 %
Jitter, Long Term (sy(t))* Tj(LT)
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, no other PLLs active 100 45
ps
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, all other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) 40 105
Jitter, Period (peak-peak)* TJ(DP)
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, no
other PLLs active 100 120
ps
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50, all
other PLLs active (A=50MHz, B=60MHz, D=14.318MHz) 40 440
CClloocckk OOuuttppuuttss ((CCrryyssttaall OOsscciillllaattoorr vviiaa CCLLKK__DD ppiinn))
Duty Cycle* Ratio of pulse width (as measured from rising edge to next falling edge at 2.5V) to one clock period 14.318 45 55 %
Jitter, Long Term (sy(t))* Tj(LT)
On rising edges 500ms apart at 2.5V relative to an ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, no other PLLs active 14.318 20
ps
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active
(A=50MHz, B=60MHz, C=40MHz) 14.318 40
Jitter, Period (peak-peak)* TJ(DP)
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, no other PLLs active 14.318 90
ps
From rising edge to the next rising edge at 2.5V, CL=15pF, fXIN=14.318MHz, all other PLLs active
(A=50MHz, B=60MHz, C=40MHz) 14.318 450
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not
currently production tested to any specific limits. Min. and Max. characterization data are ± 3sfrom typical.
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FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
Table 14: Serial Interface Timing Specifications
PPaarraammeetteerrSSyymmbboollCCoonnddiittiioonnss//DDeessccrriippttiioonnSSttaannddaarrdd MMooddeeUUnniittss
MMiinn..MMaaxx..
Clock Frequency fSCL SCL 0100 kHz
Bus Free Time Between STOP and START tBUF 4.7 ms
Set-up Time, START (repeated) tsu:STA 4.7 ms
Hold Time, START thd:STA 4.0 ms
Set-up Time, Data Input tsu:DAT SDA 250 ns
Hold Time, Data Input thd:DAT SDA 0ms
Output Data Valid From Clock tAA Minimum delay to bridge undefined region of the falling edge of
SCL to avoid unintended START or STOP 3.5 ms
Rise Time, Data and Clock tRSDA, SCL 1000 ns
Fall Time, Data and Clock tFSDA, SCL 300 ns
High Time, Clock tHI SCL 4.0 ms
Low Time, Clock tLO SCL 4.7 ms
Set-up Time, STOP tsu:STO 4.0 ms
SCL
SDA
~
~~
~~
~
STOP
t
su:STO
t
hd:STA
START
t
su:STA
ADDRESS OR
DATA VALID DATA CAN
CHANGE
Figure 12: Bus Timing Data
SCL
SDA
IN
thd:DAT
~
~
thd:STA
tsu:STA tsu:STO
tLO
tHI
SDA
OUT
tsu:DAT
~
~~
~
tBUF
tR
tF
tAA tAA
Figure 13: Data Transfer Sequence
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FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
DDiimmeennssiioonnss
IInncchheessMMiilllliimmeetteerrss
MMiinn..MMaaxx..MMiinn..MMaaxx..
A0.061 0.068 1.55 1.73
A1 0.004 0.0098 0.102 0.249
A2 0.055 0.061 1.40 1.55
B0.013 0.019 0.33 0.49
C0.0075 0.0098 0.191 0.249
D0.386 0.393 9.80 9.98
E0.150 0.157 3.81 3.99
e0.050 BSC 1.27 BSC
H0.230 0.244 5.84 6.20
h0.010 0.016 0.25 0.41
L0.016 0.035 0.41 0.89
Q0° 8° 0° 8°
Table 15: 16-pin SOIC (0.150”) Package Dimensions
11.0 Package Information For Both ‘Green’ and ‘Non-Green’
Table 16: 16-pin SOIC (0.150”) Package Characteristics
PPaarraammeetteerrSSyymmbboollCCoonnddiittiioonnss//DDeessccrriippttiioonnTTyypp..UUnniittss
Thermal Impedance, Junction to Free-Air
16-pin 0.150" SOIC QJA Air flow = 0 m/s 109 °C/W
Lead Inductance, Self L11
Corner lead 4.0
nH
Center lead 3.0
Lead Inductance, Mutual L12 Any lead to any adjacent lead 0.4 nH
Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF
12.0 Ordering Information
Table 17: Device Ordering Codes
OOrrddeerriinngg CCooddeeDDeevviiccee NNuummbbeerrPPaacckkaaggee TTyyppeeOOppeerraattiinngg
TTeemmppeerraattuurree RRaannggee
SShhiippppiinngg
CCoonnffiigguurraattiioonn
11575-801-XTP (or -XTD) FS6370-01 16-pin (0.150") SOIC
(small outline package) 0°C to 70°C (Commercial) -XTP (Tape & Reel)
-XTD (Tube/Tray)
11575-819-XTP (or - XTD) FS6370-01g
16-pin (0.150") SOIC
(small outline package)
'Green' or lead-free packaging
0°C to 70°C (Commercial) -XTP (Tape & Reel)
-XTD (Tube/Tray)
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FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
1
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• PC running MS Windows 3.1x or 95/98. Software also runs on Windows NT in a calculation mode only.
• 1.8MB available space on hard drive C.
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st
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At the appropriate disk drive prompt (A:\) unzip the compressed demo files to a directory of your choice. Run setup.exe to install the software.
1
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Launch the fs6370.exe program. Note that the parallel port can not be accessed if your machine is running Windows NT. A warning message will appear
stating: "This version of the demo program cannot communicate with the FS6370 hardware when running on a Windows NT operating system. Do you
want to continue anyway, using just the calculation features of this program?" Clicking OK starts the program for calculation only.
The FS6370 demonstration hardware is no longer available nor supported.
The opening screen is shown in Figure 14.
Figure 14: Opening Screen
13.0 Demonstration Software
Windows 3.1x/95/98-based software is available from AMIS that illustrates the capabilities of the FS6370. The software can operate under Windows NT.
Contact your local sales representative for more information.
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FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
Figure 15: PLL Screen
For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as small as possible. In
this example, highlight solution #7. Notice the VCO operates at 200MHz with a post divider of 2 to obtain an optimal 50 percent duty cycle.
Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv value in solution
#7 into post divider A and switches mux A to take the output of PLL A.
The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in solution #7. Note that mux A has been switched
to PLL A and the post divider A has the chosen 100MHz output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C and mux D are also affected by the logic level
on the SEL_CD pin, as are the post dividers C and D (see Section 4.2 for more detail).
13.3.1 Example Programming
Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that
follow.
Next, click on the PLL A box. A pop-up screen similar to Figure 15 should appear. Type in a desired output clock frequency in MHz, set the operating
voltage (3.3V or 5V), and the desired maximum output frequency error. Pressing calculate solutions generates several possible divider and VCO-speed
combinations.
FFSS66337700--0011//FFSS66337700--0011gg EEEEPPRROOMM PPrrooggrraammmmaabbllee 33--PPLLLL CClloocckk GGeenneerraattoorr IICCData Sheet
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Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider
box has split in two (as shown in Figure 16). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long
as mux B is the PLL C output.
Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL screen. A typical
menu is shown in Figure 16. The range of possible post divider values is also given in Table 7.
The EEPROM settings are shown to the left in the screen shown in Figure 14. Clicking on a register location displays a screen shown in Figure 17. Individual
bits can be poked, or the entire register value can be changed.
Figure 17: Register Screen
Production Technical Data - The information contained in this document applies to a product in production. AMI Semiconductor and its subsidiaries ("AMIS") have made every effort to ensure that the information is accurate and
reliable. However, the characteristics and specifications of the product are subject to change without notice and the information is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain
the latest version of relevant information to verify that data being relied on is the most current and complete. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice.
Products sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no other warranty, express or implied, and disclaims the warranties of noninfringement,
merchantability, or fitness for a particular purpose. AMI Semiconductor's products are intended for use in ordinary commercial applications. These products are not designed, authorized, or warranted to be suitable for use in life-
support systems or other critical applications where malfunction may cause personal injury. Inclusion of AMIS products in such applications is understood to be fully at the customer's risk. Applications requiring extended temperature
range, operation in unusual environmental conditions, or high reliability, such as military or medical life-support, are specifically not recommended without additional processing by AMIS for such applications. Copyright ©2005 AMI
Semiconductor, Inc.
Figure 16: Post Divider Menu