MTC-20135 ADSL DMT Transceiver with ATM Framer Data Sheet Preliminary Information Rev. 3 - October 1998 Features General Description * ANSI TI.413 issue 2 standard DMT modem with embedded , bypassable, ATM framer * Byte interface or Standard Utopia level 1 and level 2 ATM interfaces * Main functions: The MTC-20135 is the DMT modem and ATM Framer chip of the MTK20131 Rate adaptive ADSL DynaMiTe chipset. Receive Direction: * Rotor and Adaptive Frequency domain Equalizing * Demapping of DMT carriers into a digital bitstream, including 4D trellis coding * Error and noise monitoring on individual carriers and pilot tones * Reed-Solomon decoding and deinterleaving * ADSL Deframing * ATM cell-specific Deframing (can be bypassed) * 144 Pin PQFP Package * Power consumption 1 Watt at 3.3V Transmit Direction: * ATM cell-specific Framing * ADSL Framing * Reed-Solomon encoding * Mapping of digital bitstream onto DMT carriers * Rotor and frequency domain gain correction When used in conjunction with the MTC-20134 analog front-end and an external controller running Alcatel firmware, the product supports ANSI TI.413 release 2 ADSL specification. The MTC-20135 may be used in both central office (ATU-C) and remote (ATUR) applications. It provides both a cell based UTOPIA Level 1 and 2 ATM data interface to the host and a non ATM synchronous bit stream. The MTC-20135 performs the DMT modulation, demodulation, Reed Solomon encoding, bit interleaving and 4D trellis coding. The ATM section provides framing functions for the generic and ATM Transmission Convergence (TC) layers. The generic TC consists of data scrambling and Reed- Solomon error corrections, with and without interleaving. The MTC-20135 is controlled and configured by an external Transceiver Controller. All programmable coefficients and parameters are loaded by the Controller. The latter also controls the initialization procedure and performs the monitoring and adaptive functions during operation. UTOPIA 2 ATM X non-ATM bitstream MTC-20135 X DMT Modem and ATM Framer MTC-20134 Analog Front-end X A/B MTC-20136 Ordering Information Part number Package Temp MTC-20135PQ-I 144 pin PQFP -40 + 85C MTC-20135PQ-C 144 pin PQFP 0 + 70C Can also be ordered using kit number MTK-20131 POTS Splitter CTRL-E Fig. 1: General Block Diagram RAM Line MTC-20135 Test signals Clock Test Module VCXO Data Symbol Timing Unit AFE Interface DSP Front-end FFT / IFFT Rotor Reset Reset Trellis coding Mapper/ Demapper Generic TC Reed / Solomon ATM Specific TC Interface Module Interface Module SLAP * Utopia Controller interface Controller bus General purpose I/Os * Synchronous Link Access Protocol Fig. 2: MTC-20135 Block Diagram 2 MTC-20135 Main Blocks Description The following essentially describes the sequence of actions for the receive direction, corresponding functions for the transmit direction are readily derived. DSP Front-End Bypass Analog Interface IN Select To DMT modem AFE I/F DEC TEQ Fig. 3: DSP Front-End The DSP Front-End contains 4 parts in the receive direction: the Input Selector, the Analog Front-End Interface, the Decimator and the Time Equalizer. The input selector is used internally to enable test loopbacks inside the chip. The Analog Front-End Interface transfers 16-bits word, multiplexed on 4 input/output signals. As a result, 4 clock cycles are needed to transfer 1 word. The Decimator receives the 16-bits samples at 8.8 MHz (as sent by the Analog Front-End chip) and reduces this rate to 2.2 MHz. The Time Equalizer (TEQ) module is an FIR filter with programmable coefficients. Its main purpose is to reduce the effect of Inter-Symbol Interferences (ISI) by shortening the channel impulse response. Both the Decimator and TEQ can be bypassed. In the transmit direction, the DSP FrontEnd includes: sidelobe filtering, clipping, delay equalization and interpolation. The sidelobe filtering and delay equalization are implemented by IIR filters, reducing the effect of echo in FDM systems. 3 Clipping is a statistical process limiting the amplitude of the output signal, optimizing the dynamic range of the AFE. The interpolator receives data at 2.2 MHz and generates samples at a rate of 8.8 MHz. MTC-20135 DMT Modem Trellis Coding From DSP FE To TC FFT FEQ ROTOR Rotor Demapper Monitor FEQ Coefficients FEQ Update Fig. 4: DMT Modem This computational module is a programmable DSP unit. Its instruction set enables functions like FFT, IFFT, Scaling, Rotor and Frequency Equalization (FEQ). This block implements the core of the DMT algorithm as specified in ANSI T1.413. In the RX path, the 512-point FFT transforms the time-domain DMT symbol into a frequency domain representation which can be further decoded by the subsequent demapping stages. After the first stage time -domain equalization and FFT block an essentially ICI (InterCarrier Interference)- free carrier information stream has been obtained. This stream is still affected by carrier-specific channel distortion resulting in an Monitor Indications DMT Codec attenuation of the signal amplitude and a rotation of the signal phase. To compensate for these effects, the FFT is followed by a Frequency domain equalizer (FEQ) and a Rotor (phase shifter). In the TX path, the IFFT transforms the DMT symbol generated in the frequency domain by the mapper into a time domain representation. The IFFT block is preceded by a Fine Tune Gain and a Rotor stage, allowing for a compensation of the possible frequency mismatch between the master clock frequency and the transmitter clock frequency (which may be locked to another reference). The FFT module is a slave DSP engine controlled by the transceiver controller. It works off line and communicates with the other blocks via buffers controlled by 4 the DSTU block. The DSP executes a program stored in a RAM area, a very flexible implementation open for future enhancements. MTC-20135 DPLL The Digital PLL module receives a metric for the phase error of the pilot tone. In general, the clock frequencies at the transmitter and receiver do not match exactly. The phase error is filtered and integrated by a low pass filter, yielding an estimation of the frequency offset. Various processes can use this estimate to deal with the frequency mismatch. In particular, small accumulated phase error can be compensated in the frequency domain by a rotation of the received code constellation (Rotor). Larger errors are compensated in the time domain by inserting or deleting clock cycles in the sample input sequence. Mapper/Demapper, Monitor, Trellis Coding, FEQ Update The Demapper converts the constellation points computed by the FFT to a block of bits. This essentially consists in identifying a point in a 2D QAM constellation plane. The Demapper supports trellis coded demodulation and provides a Viterbi maximum likelihood estimator. When the trellis is active, the Demapper receives an indication for the most likely constellation subset to be used. In the transmit direction, the Mapper performs the inverse operation, mapping a block of bits into one constellation point (in a complex x+jy representation) which is passed to the IFFT block. The Trellis Encoder generates redundant bits to improve the robustness of the transmission, using a 4-Dimensional Trellis Coded Modulation scheme. The Monitor computes error parameters for carriers specified in the Demapper process. Those parameters can be used for updates of adaptive filters coefficients, clock phase adjustments, error detection,etc. A series of values is constantly monitored, such as signal power, pilot phase deviations, symbol erasures generation, loss of frame,etc. 5 MTC-20135 Generic TC Layer Functions Indication bits AOC EOC SPLITTER Fast From Demapper F F PMD Descrambler Deframer RS Coding DeInterleaver To ATM TC I PMD Descrambler I Fig. 5: Generic TC Layer Functions These functions relate to byte oriented data streams. They are completely described in ANSI T1.413. Additions described in the Issue 2 of this specification are also supported. The data received from the demapper is split into two paths, one dedicated to an interleaved data flow, the other one for a non-interleaved data flow. These data flows are also referred to as slow and fast data flows. The interleaving/deinterleaving is used to increase the error correcting capability of block codes for error bursts. After deinterleaving (if applicable), the data flow enters a Reed-Solomon error correcting code decoder, able to correct a number of bytes containing bit errors. The decoder also uses the information of previous receiving stages that may have detected the errored bytes and have labelled them with an "erasure" indication. Each time the RS decoder detects and corrects errors in a RS codeword, an RS correction event is generated. The occurrence of such events can be signalled to the management layer. After leaving the RS decoder, the cor- rected byte stream is descrambled in the PMD (Physical Medium Dependent) descramblers. Two descramblers are used, for interleaved and non-interleaved data flows. These are defined in ANSI T1.413. After descrambling, the data flows enter the Deframer that extracts and processes bytes to support Physical layer related functions according to ANSI T1.413. The ADSL frames indeed contain physical layer-related information in addition to the data passed to the higher layers. In particular, the deframer extracts the EOC (Embedded Operations Channel), the AOC (ADSL Overhead Control) and the indicators bits and passes them to the appropriate processing unit (e.g. the transceiver controller). The deframer also performs a CRC check (Cyclic Redundancy Check ) on the received frame and generates events in case of error detection. Event counters can be read by management processes. 6 The outputs of the deframer are an interleaved and a fast data streams. These data streams can either carry ATM cells or another type of traffic. In the latter case, the ATM specific TC layer functional block, described hereafter, is bypassed and the data stream is directly presented at the input of the Interface module. MTC-20135 ATM Specific TC Layer Functions BER Fast From Generic TC Slow Cell Descrambler Synchronizer HEC Cell Descrambler Synchronizer HEC Cell filter To Interface Module Cell filter BER Fig. 6: ATM Specific TC Layer Functions The 2 bytes streams (fast and slow) are received from the byte-based processing unit. When ATM cells are transported, this block provides basic cell functions such as cell synchronization, cell payload descrambling, idle/unassigned cell filter, cell Header Error Correction (HEC) and detection. The cell processing happens according to ITU-T I.163 standard. Provision is also made for BER measurements at this ATM cell level. When non cell oriented byte streams are transported, the cell processing unit is not active. 7 MTC-20135 Interface Module Fast byte stream SLAP Fast ATM UTOPIA level 1 UTOPIA level 2 UTOPIA level 1 UTOPIA level 2 From ATM TC Slow ATM Slow byte stream SLAP Fig. 7: Interface Module The interface module collects cells (from the cell-based function module) or a byte stream (from the deframer). Cells are stored in FIFO's ( 424 bytes or 8 cells wide, transmit buffers have the same size), from which they are extracted by 2 interface submodules, one pro- viding an Utopia level 1 interface and the other an Utopia level 2 interface. Byte streams are dumped on the SLAP (Synchronous Link Access Protocol) interface. Only one type of interface can be enabled in a specific configuration. DMT Symbol Timing Unit (DSTU) The DSTU interfaces with various modules, like DSP Front-End, FFT/IFFT, Mapper/Demapper, RS , Monitor and Transceiver Controller. It consists of a real time and a scheduler modules. The real time unit generate a timebase for the DMT symbols (sample counter), superframes (symbol counter) and hyperframes (sync counter). The timebases can be modified by various control features. They are continuously fine-tuned by the DPLL module. The DSTU schedulers execute a program, controlled by program opcodes and a set of variables, the most important of which are real time counters.The transmit and receive sequencers are completely independent and run different programs. An independent set of variables is assigned to each of them. The sequencer programs can be updated in real time. 8 MTC-20135 Interfaces Analog Front-End Control Interface The Analog Front-End Interface is designed to be connected to the MTC20134 Analog Front-End component. Transmit Interface The 16 bit words are multiplexed on 4 AFTXD output signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 1 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. Refer to Figure 8. The MTC-20135 fetches the 16 bit word to be multiplexed on AFTXD from the Tx Digital Front-End module. Fig. 8: Timing Diagram Table 1: Transmitted Bits Assigned to Signal/Time Slot AFTXD[0] AFTXD [1] AFTXD[2] AFTXD[3] GP_OUT Cycle 0 b0 b1 b2 b3 t0 Cycle 1 b4 b5 b6 b7 t1 Cycle 2 b8 b9 b10 b11 t2 Cycle 3 b12 b13 b14 b15 t3 Receive Interface The 16 bit receive word is multiplexed on 4 AFRXD input signals. As a result 4 cycles are needed to transfer 1 word. Refer to Table 2 for the bit/pin allocation for the 4 cycles. The first of 4 cycles is identified by the CLWD signal. Refer to Figure 9. The CLWD must repeat after 4 MCLK cycles. Fig. 9: Receive Word Timing Diagram Table 2: Transmitted Bits Assigned to Signal/Time Slot AFRXD[0] AFRXD [1] AFRXD[2] AFRXD[3] GP_IN Cycle 0 b0 b1 b2 b3 t0 9 Cycle 1 b4 b5 b6 b7 t1 Cycle 2 b8 b9 b10 b11 t2 Cycle 3 b12 b13 b14 b15 t3 MTC-20135 Analog Front End Interface Timing Master Clock ( MCLK ) Table 3: MCLK, AC Electrical Characteristics Symbol F Tper Th Parameter Clock Frequency Clock Period Clock duty cycle Test Cond. Min Typ 35.328 28.3 40 Max 60 Unit MHz ns % Transmit Interface Fig. 10: Transmit Interface Table 4: AFTXD AFTXED CLWD, AC Electrical Characteristics Symbol Tv Tc Parameter Data valid time Data valid time Test Cond. Min 0 0 Typ Max 10 10 Unit ns ns Test Cond. Min 5 5 Typ Max Unit ns ns Receive Interface Fig. 11: Receive Interface Table 5: AFRXD, AC Electrical Characteristics Symbol Ts Th Parameter Data setup time Data hold time 10 MTC-20135 Controller Interface Interface Types Two interface types are supported for an external ADSL Transceiver Controller (ATC); a generic asynchronous interface and a specific i960 interface. The interface selection is made by the OBC_TYPE pin. ( 0b selects i960 type interface ) b)The CSB (input from an external decoder) and the WR_RDB (input from ATC) are asserted synchronous to PCLK. At this stage the MTC-20135 decides whether it is involved in the current bus cycle. If it is not selected ( by the signal the MTC-20135 returns to state 1. i960 Specific Interface Basic Operation c)The RDYB output is synchronous to PCLK. The signal is generated by the MTC-20135. It is used to extend the bus cycle. The i960 supports a synchronous bus interface protocol. Address and data bus are multiplexed. The ATC is bus master and the MTC-20135 is a slave. A bus cycle consists of an access cycle ( Ta ) wait cycles ( Tw ), data cycle (Td ), Recovery cycles (Tr). Let us have a look at the 3 basic states of a bus cycle : a)The bus cycle is initiated by the ATC. The ATC asserts the AD[15:2], BE1 and ALE signals. The MTC-20135 latches AD[15:2] on the falling edge of the ALE signal. The MTC-20135 computes the address by a concatenation of the signal on AD[15:2] and BE1 and a fixed 0b. Note: The RDYB output is continuously in tri-state, except for 2 cycles. Fig. 12: Read Cycle 11 MTC-20135 Note : The RDYB output is continuously in tri-state, except for 2 cycles. Fig. 13: Write Cycle Table 6: Pins & Functional Description AD[15:0] Name Type IO BE1 ALE WR_RDB PCLK CSB RDYB INTB I I I I I OZ O Function Multiplexed address-data bus,during address phase, AD[15:2] reflect address bits [15:2] reflects address bit [1] address latch enable write not read indication Processor clock chip select Bus cycle ready indication Interrupt ATC Interface Timing All timing parameters are specified at a load of 100 pF, all the electrical levels are CMOS compatible. Table 7: All Signals Symbol tr,tf Ci Co Parameter Rise and Fall time (10% - 90%) Input load Output load Min Typ Max 3 10 100 Unit ns pF pF Parameter PCLK clock frequency Min 8 Typ Max 35.328 Unit MHz Table 8: PCLK Symbol tf 12 MTC-20135 Table 9: Address with Respect to ALE Symbol tr,tf Talew Tavs Tavh Parameter Rise and Fall time (10-90%) ALE pulse width Address valid setup time Address valid hold time Min Typ Max 4 12 7 8 Unit ns ns ns ns Fig. 14: Address and ALE Timing Table 10: Data Input with Respect to the Clock Symbol Tdh Tds Parameter Data write hold time Data write setup time Min 3 10 Max Unit ns ns Min 3 3 Max 20 20 Unit ns ns Min 10 3 Max Unit ns ns Min 10 3 Max Unit ns ns Min 3 3 Max 19 19 Unit ns ns Table 11: Data Output with Respect to the Clock Symbol Tzd Tdz Parameter Data active delay from clock, Z to data Data inactive delay from clock, data to Z Table 12: WR_RDB Input Specification with Respect to PCLK Symbol Twrs Twrh Parameter setup WR_RDB to clock hold WR_RDB to clock Table 13: CSB Input Specification with Respect to PCLK Symbol Twrs Twrh Parameter setup CSB to clock hold CSB to clock Table 14: RDYB Output with Respect to PCLK Symbol Tzrd Trdz Parameter RDYB active delay from clock, Z to 0 RDYB inactive delay from clock, 0 to Z 13 MTC-20135 Generic Interface The generic interface allows for the connection of a series of processors with limited requirements for external interface logic. This interface targets a family of processors using a multiplexed address/data bus. Table 15: Pins & Functional Description Signal name AD[15:0] ALE RDB WR_B CSB RDYB INTB Type IO I I I I OZ O Function Multiplexed address-data bus, address latch enable read cycle indication write cycle indication chip select Bus cycle ready indication Interrupt PIN AD[15:0] ALE WR_RDB BE1 CSB RDYB INTB Dynamic Characteristics Table 16: All Signals Symbol tr,tf Ci Co Parameter Rise and Fall time (10% - 90%) Input load Output load Min Typ Max 3 10 100 Unit ns pF pF Min 12 10 10 0 Typ Max Unit ns ns ns ns ns Table 17: Timing Related to ALE Signal Symbol Talew Tavs Tavh Tale2cs Tale2Z Parameter ALE pulse width Address valid setup time Address valid hold time ALE to CSB ALE to high Z state of bus 50 Cycle Timing Table 18: Timing Parameters of the ATC Interface Symbol Tcs2rs Tcsre Tcs2wr Twr2d Trdy2wr Twvd Tdvh Twr2cs Tcs2wr Trdy2rd Twvd Trd2cs Tmclk Parameter CSB to RDYB asserted access time CSB to WRB WRB to data RDYB to WRB data set up time data hold time WRB to CSB CSB to WRB RDYB to RD data set up time RDB to CSB master clock timing. Min Typ Max 60 900 0 15 0 10 1/2 Tmclk -10 0 0 10 -10 Tmclk Unit ns ns ns ns ns ns ns ns ns ns ns ns All AC characteristics are measured in a circuit with a 100 pF capacitive load. Rise and fall times apply to all signals. 14 MTC-20135 Fig. 15: ATC Write Timing Diagram Fig. 16: ATC Read Timing Diagram 15 MTC-20135 Digital Interface Utopia Level 2 Interface The ATM forum takes the ATM layer chip as a reference. It defines the direction from ATM to physical layer as the Transmit direction. The direction from physical layer to ATM as the Receive direction is referred to as the receive direction. Figure 17 shows the interconnection between ATM and PHY layer devices, the optional signals are not supported and not shown. The UTOPIA interface transfers one byte in a single clock cycle, as a result cells are transferred in 53 clock cycles. Both transmit and receive interfaces are synchronized on clocks generated by the ATM layer chip, and no specific relationship between Receive and Transmit clock is assumed, they must be regarded as mutually asynchronous clocks. Flow control signals are available to match the bandwidth constraints of the physical layer and the ATM layer. The UTOPIA level2 supports point to multi point configurations by introducing an addressing capability and by making a distinction between polling and selecting a device : --the ATM chip polls a specific physical layer chip by putting its address on the address bus when the Enb line is asserted. The addressed physical layer answers the next cycle via a Clav line reflecting its status at that time. --the ATM chip selects a specific physical layer chip by putting its address on the address bus when the Enb line is deasserted and asserting the Enb line on the next cycle. The addressed physical layer chip will be the target or source of the next cell transfer. MTC-20135 Fig. 17: Signals at Utopia Level 2 Interface Reference Spec: Utopia Specification Level 2, Version 1.0, June 95. See www.atmforum.com 16 MTC-20135 UTOPIA Level 2 Signals The physical layer chip sends cell data towards the ATM layer chip. The ATM layer chip polls the status of the FIFO of the physical layer chip. Refer to Table 19 for a list of interface signals : Table 19: Signal Definitions for the Utopia Receive Path Name RxClav Meaning Receive Cell available notRxEnb Receive Enable (active low) RxClk Receive Byte Clock RxData Receive Data RxSOC RxAddr Receive Start Of Cell Receive Address The cell exchange proceeds like : a)The physical layer chip signals the availability of a cell by asserting RxClav when polled by the ATM chip. b)The ATM chips selects a physical layer chip, then starts the transfer by asserting notRxEnb. c)If the physical layer chip has data to send, it puts them on the RxData line the cycle after it sampled notRxEnb active. It also advances the offset in the cell. If the data transferred is the first byte of a cell, RxSOC is 1b at the time of the data transfer, 0b otherwise. d)The ATM chip accepts the data when they are available. If RxSOC was 1b during the transfer, it resets its internal offset pointer to the value 1, otherwise it advances the offset in the cell. Usage Signals to the ATM chip that the physical layer chip has a cell ready for transfer. Signals to the physical layer chip that the ATM layer chip will sample and accept data during next clock cycle. Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data from physical layer chip to ATM chip, byte wide Identifies the cell boundary on RxData Use to select the port that will be active or polled MTC-20135 Utopia Level 2 MPHY Operation Utopia level 2 MPHY operation can be done by various interface schemes. The MTC-20135 supports only the required mode, this mode is referred to as 'operation with 1 TxClav and 1 RxClav'. Remark Remains active for the entire cell transfer RxData and RxSOC could be tristate when notRxEnb is inactive (high). PHY Device Identification The MTC-20135 holds 2 PHY layer Utopia ports, one is dedicated to the fast data channel, the other one to the interleaved data channel. The associated PHY address is specified by the PHY_ADDR_x fields the Utopia PHY address register. Beware that an incorrect address configuration may lead to bus conflicts. Table 20: Signal Definitions for the Utopia Transmit Path Name TxClav notTxEnb TxClk TxData TxSOC TxAddr Meaning Transmit Cell available Transmit Enable (active low) Transmit Byte Clock Transmit Data Transmit Start Of Cell Transmit Address Usage Signals to the ATM chip that the physical layer chip is ready to accept a cell. Signals to the physical layer chip that TxData and TxSOC are valid. Gives the timing signal for the transfer, generated by ATM layer chip. ATM cell data from ATM chip to physical later chip, byte wide Identifies the cell boundary on TxData Use to select the port that will be active or polled 17 MTC-20135 Utopia Level 1 Data Flow Selection In this mode the MTC-20135 can only support one data flow ( either fast or interleaved ). The selection between fast or interleaved is under control of the Transceiver Controller. Reference Spec: Utopia Specification Level 1, Version 2.0, March 94. See www.atmforum.com Utopia Level 1 Configuration MTC-20135 Fig.18: Signals at UTOPIA Level 1 interface Utopia level 1 Handshake Protocol PHY->ATM The MTC-20135 supports a cell level handshake protocol only. The ATM layer indicates it wants to read data by asserting the notRxEnb signal. The PHY layer dumps 53 bytes ( 1 cell ) on the RxDATA bus, a cell start indication is available on the RxSOC signal. Refer to Figure 19. Fig.19a: Utopia Level 1 Functional Timing Diagram (PHY -> ATM) Fig.19b: Utopia Level 1 Functional Timing Diagram (ATM -> PHY) 18 MTC-20135 Utopia level 1 Reference Clock The Utopia reference clock ( notRxRef ) has a duty cycle of 50%. It is asynchronous to all other Utopia signals. Utopia level 1 Signal Multiplexing Table 21: Utopia level 1 Pinout Name signal RxData RxSOC notRxEnb RxClav RxClk Type O O I O I Pin U_RxData U_RxSOC U_RxENBB U_RxCLAV U_RxCLK UTOPIA Interface Timings Clock Signals Table 22: U_TxCLK, U_RxCLK, AC Electrical Characteristics Symbol F Tc Tj Trf L Parameter Clock Frequency Clock duty cycle Clock peak to peak jitter Clock rise/fall time Load Test Cond. Min 1.5 40 Typ Max 25 60 5 4 100 Unit MHz % % ns pF Min 10 Typ Max Unit ns Fig.20: Utopia Timing Diagram ATM to PHY Signals Table 23: U_TxData, U_TxSOC, U_TxADDR, AC Electrical Symbol T5 T6 L Parameter Input set up time to U_TxCLK Hold time time to U_TxCLK Load Test Cond. 1 ns 100 19 pF MTC-20135 Table 24: U_RxADDR AC Electrical Characteristics Symbol T5 T6 L Parameter Input set up time to U_RxCLK Hold time time to U_RxCLK Load Min 10 1 Typ Max 100 Unit ns ns pF PHY to ATM Signals U_TxCLAV Table 25: U_RxData, U_RxSOC, U_RxCLAV AC Electrical Characteristics Symbol T7 T8 T9 T10 T11 T12 L Parameter Input set up time to U_TxCLK Hold time time to U_TxCLK Signal going low impedance to U_RxCLK Signal going high impedance to U_RxCLK Signal going low impedance to U_RxCLK Signal going high impedance to U_RxCLK Load Min 10 1 10 0 1 1 Typ Max 100 Unit ns ns ns ns ns ns pF Table 26: U_RxADDR AC Electrical Characteristics Symbol T7 T8 T9 T10 T11 T12 L Parameter Input set up time to U_TxCLK Hold time time to U_TxCLK Signal going low impedance to U_RxCLK Signal going high impedance to U_RxCLK Signal going low impedance to U_RxCLK Signal going high impedance to U_RxCLK Load 20 Min 10 1 10 0 1 1 Typ Max 100 Unit ns ns ns ns ns ns pF MTC-20135 SLAP (Synchronous Link Access Protocol) Interface The SLAP ATM interface is a point to point bitstream interface. The MTC20135 is the bus master of the interface. The interface is synchronous, a common clock (INTERFACE_CLOCK) is used. The SLAP interface dumps the data of the fast and interleaved channels on 2 separate sub interfaces. The data flow from the SLAP interface must be enabled by the Transceiver Controller. A disabled cell interface does not dump data on its interface. Receive SLAP Interface The interface signals uses 2 signal types : ( refer to Figure 21) --SLR_DATA[1:0]: data pins, a byte is transferred in 4 cycles of 2 bits. The msb are transmitted first, odd bits are asserted on SLR_DATA[1]. --SLR_VAL: indicates the data transfer and the byte boundary --SLR_FRAME: indicates the start of a superframe Notice 2 SLAP interfaces are supported, one for the fast data flow, the other one for the interleaved data flow. The logical timing diagram is shown in Figure 22. Fig. 21: Receive Path, SLAP Interface Fig. 22: SLAP Interface Timing The implementation must guarantee that all active SLR_Valid signals must be separated by at least 8 clock cycles. Refer to Figure 22. The SLR_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the inter- 21 leaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow and guarantee that the frame MTC-20135 Transmit SLAP Interface The Transmit interface uses the following signals (refer to Figure 23) --SLT_REQ: byte request --SLT_FRAME: start of frame indication --SLT_DATA[1:0]: data pins, a byte is transferred 2 bits at the time in 4 successive clock cycles. MSB first, odd bits on SLT_DATA[1] The logical timing diagram is shown in Figure 24. The delay between Request and the associated data byte is defined as 8 cycles. Fig. 23: Interface Towards PHY Layer Fig. 24: Functional Interface Timing Diagram The SLT_FRAME signals are asserted when the first pair of bits of a frame are transferred. For the fast channel a frame is defined as a superframe timebase. For the interleaved channel the frame is defined by a timebase period of 4 superframes. Both timebases are synchronized to the data flow and guarantee that the frame indication is asserted when the first bits of the first DMT symbol are transferred. 22 MTC-20135 SLAP Interface Timings Fig. 25: SLAP Interface Timing Information Table 27: SLAP Interface, AC Electrical Characteristics Symbol Tper Th Tl Ts Thd Td Parameter Clock Period Clock High Clock Low Setup Hold Data delay Test Cond. refer to MCLK 20 pF load 23 Min 11 11 8 -2 0 Typ Max 17 17 3 Unit ns ns ns ns ns ns MTC-20135 JTAG TAP and Boundary Scan TAP Bus Signals The interface from the board to the onchip Test Access Port is the TAP bus, consisting of five signals: --the standard bus : TDI, TDO, TCK, TMS. --TRSTB : Test Reset, reset the TAP controller. TRSTB is an active low signal. TRSTB is explicitly required because TCK is not active in functional mode. To guarantee a correct operation of the component on the board, all flipflops that control the signals in the interface between the TAP controller and the device logic must support an asynchronous reset. Version 31 MS Bit Instructions The IEEE standard requires that INTEST, EXTEST, BYPASS and SAMPLE be implemented as a minimum. It is also mandatory to implement an IDCODE. The Alcatel Identification Code used in the IDCODE instruction is a 32 bit pattern. Part Number 28 27 Bit number Fig. 26: JTAG TAP Idcode Boundary Scan Data Register The scan chain uses 4 types of cells : a)input cells: able to sample and control the state of an external signal during BS tests. b)output cells: able to control the state of an external signal during BS tests. c)capture cell: able to sample the state of an external signal during BS tests. Its usage is restricted to paths where additional delay caused by an input cell is inacceptable. d)enable cell: provides a signal for direction control of bidirectional pins during BS tests. In boundary scan mode, the input signals are sampled at the rising edge of TCK, while the output signal changes at the falling edge. The component ensures correct operation of scan instructions related to any internal register up to 10 MHz (5 Mbit/s). 24 Manufacturer Identity 12 11 1 1 0 LS Bit MTC-20135 Table 28: Boundary Scan Chain Sequence Sequence Number 2 3 4 6 7 9 10 12 13 14 16 17 19 21 23 24 25 27 28 30 31 32 33 34 35 38 39 41 42 44 45 46 47 48 50 51 52 53 55 56 58 60 61 63 64 65 66 68 69 70 71 Mnemonic AD_0 AD_1 AD_2 AD_3 AD_4 AD_5 AD_6 AD_7 AD_8 AD_9 AD_10 AD_11 AD_12 PCLK AD_13 AD_14 AD_15 BE1 ALE CSB WR_RDB RDYB OBC_TYPE INTB RESETB U_RxData_0 U_RxData_1 U_RxData_2 U_RxData_3 U_RxData_4 U_RxData_5 VSS U_RxData_6 U_RxData_7 U_RxADDR_0 U_RxADDR_1 U_RxADDR_2 U_RxADDR_3 U_RxADDR_4 GP_IN_0 GP_IN_1 U_RxRefB U_TxRefB U_RxCLK U_RxSOC U_RxCLAV U_RxENBB U_TxCLK U_TxSOC U_TxCLAV U_TxENBB Pin BS Type B B B B B B B B B B B B B I B B B I C I I O I O I B B B B B B B B I I I I I I I O I C I O I C I O I 25 MTC-20135 74 75 77 78 79 80 82 83 84 85 87 88 89 90 92 93 94 96 97 98 99 100 101 103 104 105 106 107 110 111 112 113 114 116 118 119 120 121 123 124 125 126 128 129 130 132 133 135 136 138 139 140 142 143 U_TxData_7 U_TxData_6 U_TxData_5 U_TxData_4 U_TxData_3 U_TxData_2 U_TxData_1 U_TxData_0 U_TxADDR_4 U_TxADDR_3 U_TxADDR_2 U_TxADDR_1 U_TxADDR_0 SLR_FRAME_F SLR_FRAME_S SLR_DATA_S_1 SLR_DATA_S_0 SLR_DATA_S SLR_DATA_F_1 SLR_DATA_F_0 SLR_VAL_F INTERFACE_CLOCK SLT_FRAME_F SLT_DATA_F_1 SLT_DATA_F_0 SLT_DATA_S_1 SLT_DATA_S_0 SLT_REQ_F SLT_REQ_S SLT_FRAME_S TDI TDO TMS TCK TRSTB TESTSE GP_OUT PDOWN AFRXD_0 AFRXD_1 AFRXD_2 AFRXD_3 CLWD MCLK CTRLDATA AFTXED_0 AFTXED_0 AFTXED_0 AFTXED_0 IDDq AFTXD_0 AFTXD_1 AFTXD_0 AFTXD_1 I I I I I I I I I I I I I O O O O O O O O none O I I I I O O O none none none none none C O O I I I I I C O O O O O C - 26 MTC-20135 Reset Initialization The MTC-20135 supports two reset modes: --A 'hardware' reset is activated by the RESETB pin (active low). A hard reset occurs when a low input value is detected at the RESETB input. The low level must be applied for at least 1ms to guarantee a correct reset operation. All clocks and power supplies must be stable for 200ns prior to the rising edge of the RESETB signal. --'Soft' reset, activated by the controller write access to a soft reset configuration bit. The reset process takes less than 10000 MCLK clock cycles. Electrical Specifications Absolute Maximum Ratings Operation of the device beyond these conditions is not guaranteed. Sustained exposure to these limits will adversely effect device reliability. Table 1 Parameter Max Units DVDD, AVDD Vin, Voltage on any device pin 4.8 VSS-0.3 VDD+0.3 or 3.63 V (see note) V V, whichever is lower Storage temperature Temperature under bias Lead Temperature (soldering 10 sec) -65 to +150 -55 to +125 300 C C C Note: Exposure to voltages at or above this level for more than 10 hours accummulated over the device's operating life will adversely effect reliability. Note 2. All logic pins except NRESET, which is a Schmitt-trigger input with hysteresis. Operating Conditions Electrical characteristics are specified over the following operating conditions unless otherwise specified. Table 33: Operating Conditions Maximum Symbol VDD TA Ratings Parameter Supply voltage Ambient temperature 1m/s airflow Note - I version - C version 27 Min 3.0 -40 0 Typ 3.3 Max 3.6 +85 70 Unit V C C MTC-20135 Generic The values presented in the following table apply for all inputs and/or outputs unless specified otherwise. Specifically they are not influenced by the choice between CMOS or TTL levels. Table 29: IO Buffers Generic DC Characteristics DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions Min Typ Max IIN Input leakage current VIN = VSS, VDD -1 1 no pull up/pull down IOZ Tristate leakage current VIN = VSS, VDD, -1 1 no pull up/pull down IPU Pull up current VIN = VSS -25 -66 -125 IPD Pull down current VIN = VDD 25 66 125 RPU Pull up resistance VIN = VSS 50 RPD Pull down resistance VIN = VDD 50 Unit mA mA mA mA kOhm kOhm Table 30: IO Buffers Dynamic DC Characteristics DC Electrical Characteristics, important for transient but measured at (near) DC All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions Min Typ Max CIN Input capacitance @f = 1MHz 5 dI/dt Current derivative 8 mA driver, slew rate control 23.5 8 mA driver, no slew rate control 89 Ipeak Peak current 8 mA driver, slew rate control 85 8 mA driver, no slew rate control 100 COUT Output capacitance @f = 1MHz 7 (also bidirectional and tristate drivers) Unit pF mA/ns mA/ns mA mA pF Input/Output CMOS Generic Characteristics The values presented in the following table apply for all CMOS inputs and/or outputs unless specified otherwise. * The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are 2, 4 and 8 mA. Table 31: CMOS IO Buffers Generic Characteristics DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions Min Typ Max VIL Low level input voltage 0.2*VDD VIH High level input voltage 0.8*VDD VHY Schmitt trigger hysteresis slow edge < 1 V/ms, 0.8 only for SCHMITx VOL Low level output voltage IOUT = XmA* 0.4 VOH High level output voltage IOUT = -XmA* 0.85*VDD 28 Unit V V V V V MTC-20135 Input/Output TTL Generic Characteristics The values presented in the following table apply for all TTL inputs and/or outputs unless specified otherwise. Table 32: TTL IO buffers generic characteristics DC Electrical Characteristics All voltages are referenced to VSS, unless otherwise specified, positive current is towards the device Symbol Parameter Test Conditions Min Typ Max VIL Low level input voltage 0.8 VIH High level input voltage 2.0 VILHY Low level threshold, falling slow edge < 1 V/ms 0.9 1.35 VIHHY High level threshold, rising slow edge < 1 V/ms 1.3 1.9 VHY Schmitt trigger hysteresis slow edge < 1 V/ms 0.4 0.7 VOL Low level output voltage IOUT = XmA* 0.4 VOH High level output voltage IOUT = -XmA* 2.4 * The reference current is dependent on the exact buffer chosen and is a part of the buffer name. The available values are currently 2, 4 and 8 mA. Transient Energy Capabilities ESD ESD (Electrostatic Discharge) tests been performed for the Human Body Model (HBM) and for the Charged Device Model (CDM) The pins of the device are to be able to withstand minimum1500 V for the HBM and minimum 250 V for CDM. Latch-up The maximum sink or source current from any pin is limited to 100 mA to prevent latch-up. 29 Unit V V V V V V V MTC-20135 Pin Layout and Package The MTC-20135 is packaged in a Standard 144 pin PQFP Fig. 27: Pinout ( Topside View) 30 MTC-20135 Table 34: Pin summary Mnemonic Power supply VDD VSS ATC Interface ALE Type BS Type Signals Function VSS + 3.3 Volts power supply OV GROUND I PCLK I CSB I BE1 I WR_RDB I RDYB OZ INTB O AD IO OBC_TYPE I-PD Test Access Port Interface TDI I-PU TDO OZ TCK I-PD TMS I-PU TRSTB I-PD Analog Front End Interface AFRXD I AFTXD O AFTXED O CLWD I PDOWN O CTRLDATA O MCLK I ATM UTOPIA Interface U_RxData OZ U_TxData I U_RxADDR I U_TxADDR I U_RxCLAV O-Z U_TxCLAV O-Z U_RxENBB I-TTL U_TxENBB I-TTL U_TxSOC I-TTL U_RxSOC O-Z U_RxCLK I-TTL U_TxCLK I-TTL ATM SLAP Interface SLR_VAL_S O SLR_VAL_F O SLR_DATA_S O SLR_DATA_F O SLT_REQ_S O SLT_REQ_F O SLT_DATA_S I SLT_DATA_F I INTERFACE_CLOCK O C 1 I I I I O O B I 1 1 1 1 1 1 16 1 Used to latch the address of the internal register to be accessed Processor clock Chip selected to respond to bus cycle. Address[1] input Specifies the direction of the access cycle Controls the ATC bus cycle termination Requests ATC interrupt service Multiplexed address data bus Selects between I960 or generic interface 1 1 1 1 1 JTAG I/P JTAG O/P JTAG CLOCK JTAG IMODE SELECT JTAG RESET I O O I O O C 4 4 4 1 1 1 1 Receive data nibble Transmit data nibble Transmit echo nibble Start of word indication Power down analog front end Serial data transmit channel Master clock B I I I O O I I I O C C 8 8 5 5 1 1 1 1 1 1 1 1 Utopia RX data Utopia TX data Utopia RX address Utopia TX address Utopia Receive cell available Utopia Transmit cell available Utopia Receive enable Utopia Transmit enable Transmit interface Start of Cell indication Receive interface Start of Cell indication Receive interface Utopia clock Transmit interface Utopia clock 1 1 2 2 1 1 2 2 1 Data valid indicator interleaved Data valid indicator fast Data interleaved Data fast Byte request interleaved Byte request fast Data Fast Data Clock for Slap I/F 31 MTC-20135 SLR_FRAME_I_S SLT_FRAME_I_S SLR_FRAME_F SLT_FRAME_F Miscellaneous GP_IN GP_OUT RESETB TESTSE IDDq I I-PU I-PD I-TTL O OZ IO BS cell = = = = = = = = O O O O I-PD O I I I I O I none none 1 1 1 1 Frame indicator interleaved Start of Frame indicator interleaved Frame indicator fast Start of Frame indicator fast 2 1 I none none General purpose input General purpose output Hard reset Enables scan test mode Test pin, active high Input, CMOS levels Input with pull-up resistance, CMOS levels Input with pull-down resistance, CMOS levels Input TTL levels Push-pull output Push-pull output with high-impedance state input / Tri-state Push-pull output Boundary-Scan cell I = Input cell O = Output cell B = Bidirectional cell C = Capture cell 32 MTC-20135 Table 35: Pin List Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic VSS AD_0 AD_1 AD_2 VDD AD_3 AD_4 VSS AD_5 AD_6 VDD AD_7 AD_8 AD_9 VSS AD_10 AD_11 VDD AD_12 VSS PCLK VDD AD_13 AD_14 AD_15 VSS BE1 ALE 29 30 31 VDD CSB WR_RDB 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 RDYB OBC_TYPE INTB RESETB VSS VDD U_RxData_0 U_RxData_1 VSS U_RxData_2 U_RxData_3 VDD U_RxData_4 U_RxData_5 VSS U_RxData_6 U_RxData_7 VDD Type Supply Driver BS B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B B B VDD VDD BD8SCR BD8SCR B B B B VDD VDD BD8SCR BD8SCR B B B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B B B VDD VDD BD8SCR BD8SCR B B B VDD BD8SCR B I VDD IBUF I B B B VDD VDD VDD BD8SCR BD8SCR BD8SCR B B B I I VDD VDD IBUF IBUF I C I I VDD VDD IBUF IBUF I I OZ I-PD O I VDD VDD VDD VDD BT4CR IBUF IBUF IBUF O I O I OZ OZ VDD VDD BD8SRC BD8SRC B B OZ OZ VDD VDD BD8SRC BD8SRC B B OZ OZ VDD VDD BD8SRC BD8SRC B B OZ OZ VDD VDD BD8SRC BD8SRC B B 33 Description OV GROUND Micro processor interface Address / Data 1 Address / Data 2 + 3.3 Volts power supply Address / Data 3 Address / Data 4 OV GROUND Address / Data 5 Address / Data 6 + 3.3 Volts power supply Address / Data 7 Address / Data 8 Address / Data 9 OV GROUND Address / Data 10 Address / Data 11 + 3.3 Volts power supply Address / Data 12 OV GROUND Processor clock + 3.3 Volts power supply Address / Data 13 Address / Data 14 Address / Data 15 OV GROUND Address[1] input Used to latch the address of the internal register to be accessed + 3.3 Volts power supply Chip selected to respond to bus cycle. Specifies the direction of the access cycle Bus Cycle ready indication ATC Mode Selection Requests ATC interrupt service Hard reset OV GROUND + 3.3 Volts power supply UTOPIA RX Data 0 UTOPIA RX Data 1 OV GROUND UTOPIA RX Data 2 UTOPIA RX Data 3 + 3.3 Volts power supply UTOPIA RX Data 4 UTOPIA RX Data 5 OV GROUND UTOPIA RX Data 6 UTOPIA RX Data 7 + 3.3 Volts power supply MTC-20135 Pin 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Mnemonic U_RxADDR_0 U_RxADDR_1 U_RxADDR_2 U_RxADDR_3 VSS U_RxADDR_4 GP_IN_0 VDD GP_IN_1 VSS U_RxRefB U_TxRefB VDD U_RxCLK U_RxSOC U_RxCLAV U_RxENBB VSS U_TxCLK U_TxSOC U_TxCLAV U_TxENBB VDD VSS U_TxData_7 U_TxData_6 VDD U_TxData_5 U_TxData_4 U_TxData_3 U_TxData_2 VDD U_TxData_1 U_TxData_0 U_TxADDR_4 U_TxADDR_3 VDD U_TxADDR_2 U_TxADDR_1 U_TxADDR_0 SLR_FRAME_F VSS SLR_FRAME_S SLR_DATA_S_1 SLR_DATA_S_0 VDD SLR_VAL_S SLR_DATA_F_1 SLR_DATA_F_0 SLR_VAL_F INTERFACE_CLOCK SLT_FRAME_F VSS Type I I I I Supply VDD VDD VDD VDD Driver IBUF IBUF IBUF IBUF BS I I I I I I-PD VDD VDD IBUF IBUFDQ I I I-PD VDD IBUFDQ I O I VDD VDD IBUF BT4CR O I I O-Z O-Z I VDD VDD VDD VDD IBUF BD8SCR BD8SCR IBUF I I O-Z I VDD VDD VDD VDD IBUF IBUF BD8SCR IBUF I I VDD VDD IBUF IBUF I I I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I I I I O VDD VDD VDD VDD IBUF IBUF IBUF BT4CR I I I O O O VDD VDD VDD BT4CR BT4CR BT4CR O O O O O O VDD VDD VDD VDD VDD VDD BT4CR BT4CR BT4CR BT4CR BT4CR BT4CR 34 Description UTOPIA RX Address 0 UTOPIA RX Address 1 UTOPIA RX Address 2 UTOPIA RX Address 3 OV GROUND UTOPIA RX Address 4 General purpose input + 3.3 Volts power supply General purpose input 1 OV GROUND + 3.3 Volts power supply Receive interface Utopia clock Receive interface Start of Cell indication Receive cell available Receive enable + 3.3 volts power supply Transmit interface Utopia clock Transmit interface Start of Cell indication Transmit cell available UTOPIA TX Enable + 3.3 Volts power supply OV GROUND UTOPIA TX Data 7 UTOPIA TX Data 6 + 3.3 Volts power supply UTOPIA TX Data 5 UTOPIA TX Data 4 UTOPIA TX Data 3 UTOPIA TX Data 2 OV GROUND UTOPIA TX Data 1 UTOPIA TX Data 0 UTOPIA TX Addresss 4 UTOPIA TX Addresss 3 + 3.3 Volts power supply UTOPIA TX Addresss 2 UTOPIA TX Addresss 1 UTOPIA TX Addresss 0 Frame Identifier Fast OV GROUND Frame Identifier Interleaved Data Interleave 1 Data Interleave 0 + 3.3 Volts power supply Data Valid Indicator Interleaved Data Fast 1 Data Fast 0 Data Valid Indicator Fast Clock for SLAP I/F Start of Frame Indicator Fast OV GROUND MTC-20135 Pin 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Mnemonic SLT_DATA_F_1 SLT_DATA_F_0 SLT_DATA_S_1 SLT_DATA_S_0 SLT_REQ_F VDD VSS SLT_REQ_S SLT_FRAME_S TDI TDO TMS VDD TCK VSS TRSTB TESTSE GP_OUT PDOWN VDD AFRXD_0 AFRXD_1 AFRXD_2 AFRXD_3 VSS CLWD MCLK CTRLDATA VDD AFTXED_0 AFTXED_1 VSS AFTXED_2 AFTXED_3 VDD IDDq AFTXD_0 AFTXD_1 VSS AFTXD_2 AFTXD_3 VDD Type I I I I O Supply VDD VDD VDD VDD VDD Driver IBUFDQ IBUFDQ IBUFDQ IBUFDQ BT4CR BS O O I-PU OZ I-PU VDD VDD VDD VDD VDD BT4CR BT4CR IBUFUQ BT4CR IBUFUQ I-PD VDD IBUFDQ I-PD I O O VDD VDD VDD VDD IBUFDQ IBUF BD8SCR BT4CR none O O I I I I VDD VDD VDD VDD IBUF IBUF IBUF IBUF I I I I I I O VDD VDD VDD IBUF IBUF BT4CR I C O O O VDD VDD BT4CR BT4CR O O O O VDD VDD BT4CR BT4CR O O I O O VDD VDD VDD IBUF BT4CR BT4CR none O O O O VDD VDD BT4CR BT4CR O O Table 36: I/O Driver Function Driver BD4CR BD8SCR IBUF IBUFDQ IBUFUQ Function CMOS bidirectional, 4mA, slew rate control CMOS bidirectional, 8mA, slew rate control, Schmitt trigger CMOS input CMOS input, pull down, IDDq control CMOS input, pull up, IDDq control 35 Description Fast Data 1 Fast Data 0 Data 1 Data 0 Byte Request Fast + 3.3 Volts power supply OV GROUND Byte Request Interleaved Start of Frame Indication Interleaved JTAG I/P JTAG O/P JTAG Mode Select + 3.3 Volts power supply JTAG Clock OV GROUND JTAG Reset Enables scan test mode General purpose output Power down analog front end + 3.3 Volts power supply Receive data nibble Receive data nibble Receive data nibble Receive data nibble OV GROUND Start of word indication Master clock Serial data transmit channel + 3.3 Volts power supply Transmit echo nibble Transmit echo nibble OV GROUND Transmit echo nibble Transmit echo nibble + 3.3 Volts power supply Test pin, active high Transmit data nibble Transmit data nibble OV GROUND Transmit data nibble Transmit data nibble + 3.3 Volts power supply MTC-20135 1.238(31.45) 1.218(30.95) 1.106(28.10) 1.098(27.90) TYP.006(0.15) .041(1.03) .026(0.65) PIN 1 .016(0.40) .008(0.20) 1.106(28.10) 1.098(27.90) 1.238(31.45) 1.218(30.95) TYP.026(0.65) TYP 0 - 10 0 - 10 .141(3.59) .125(3.17) MAX .160(4.07) TYP.063(1.60) MIN .002(0.05) Drawing revision: 11 Date: 07-06-95 All dimensions are in inches and parenthetically in millimeters. Inches dimensions are approximated. 144 LEAD PQFP / DQFP DWG.NR.90-0040 General dimensions Fig.28:Package 144 Lead PQFP Alcatel Microelectronics acknowledges the trademarks of all companies referred to in this document. This document contains information on a new product. Alcatel Microelectronics reserves the right to make changes in specifications at any time and without notice. The information furnished by Alcatel Microelectronics in this document is believed to be accurate and reliable. However, no responsibility is assumed by Alcatel Microelectronics for its use, nor for any infringements of patents or other rights of third parties resulting from its use. No licence is granted under any patents or patent rights of Alcatel Microelectronics. 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