Hot-Swap Capability
Hot-Swap Inputs
Inserting circuit boards into a hot, or powered, backplane
may cause voltage transients on DE, DE/RE, RE, and
receiver inputs A and B that can lead to data errors. For
example, upon initial circuit board insertion, the processor
undergoes a power-up sequence. During this period, the
high-impedance state of the output drivers makes them
unable to drive the MAX3440E–MAX3444E enable inputs
to a defined logic level. Meanwhile, leakage currents of up
to 10µA from the high-impedance output, or capacitively
coupled noise from VCC or GND, could cause an input to
drift to an incorrect logic state. To prevent such a condi-
tion from occurring, the MAX3440E–MAX3443E feature
hot-swap input circuitry on DE, DE/RE, and RE to guard
against unwanted driver activation during hot-swap situ-
ations. The MAX3444E has hot-swap input circuitry only
on RE. When VCC rises, an internal pulldown (or pullup
for RE) circuit holds DE low for at least 10µs, and until the
current into DE exceeds 200µA. After the initial power-up
sequence, the pulldown circuit becomes transparent,
resetting the hot-swap tolerable input.
Hot-Swap Input Circuitry
At the driver-enable input (DE), there are two nMOS
devices, M1 and M2 (Figure 10). When VCC ramps from
zero, an internal 15µs timer turns on M2 and sets the SR
latch, which also turns on M1. Transistors M2, a 2mA cur-
rent sink, and M1, a 100µA current sink, pull DE to GND
through a 5.6kW resistor. M2 pulls DE to the disabled
state against an external parasitic capacitance up to
100pF that may drive DE high. After 15µs, the timer deac-
tivates M2 while M1 remains on, holding DE low against
three-state leakage currents that may drive DE high. M1
remains on until an external current source overcomes
the required input current. At this time, the SR latch resets
M1 and turns off. When M1 turns off, DE reverts to a stan-
dard, high-impedance CMOS input. Whenever VCC drops
below 1V, the input is reset.
A complementary circuit for RE uses two pMOS devices
to pull RE to VCC.
Applications Information
128 Transceivers on the Bus
The MAX3440E–MAX3444E transceivers 1/4-unit-load
receiver input impedance (48kW) allows up to 128 trans-
ceivers connected in parallel on one communication line.
Connect any combination of these devices, and/or other
RS-485 devices, for a maximum of 32-unit loads to the line.
Reduced EMI and Reections
The MAX3440E/MAX3442E/MAX3444E are slew-rate lim-
ited, minimizing EMI and reducing reflections caused by
improperly terminated cables. Figure 11 shows the driver
output waveform and its Fourier analysis of a 125kHz
signal transmitted by a MAX3443E. High-frequency har-
monic components with large amplitudes are evident.
Figure 12 shows the same signal displayed for a
MAX3442E transmitting under the same conditions.
Figure 12’s high-frequency harmonic components are
much lower in amplitude, compared with Figure 11’s, and
the potential for EMI is significantly reduced.
Figure 10. Simplified Structure of the Driver Enable Pin (DE)
VCC
TIMER
TIMER
DE
(HOT SWAP)
15µs
100µA
M1 M2
5.6kΩ
2mA
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MAX3440E–MAX3444E ±15kV ESD-Protected, ±60V Fault-Protected,
10Mbps, Fail-Safe RS-485/J1708 Transceivers