STEK 16K-BIT READ ONLY MEMORY MK34000(P/J/N)-3 FEATURES O 2K x 8 organization with static interface 0D 350ns max access time O Single +5V +10% power supply O 330mW max power dissipation O Contact programmed for fast turn-around DESCRIPTION The MK34000 is a new generation N-channel silicon gate MOS Read Only Memory circuit organized as 2048 words by 8 bits. As a state-of-the-art device, the MK34000 incor- porates advanced circuit techniques designed to provide maximum circuit density and reliability with highest possible performance, while maintaining low power dissipation and wide operating margins. The MK34000 requires a single +5 volt (+10% tolerance) power supply and has complete TTL compatibility at all inputs and outputs (a feature made possible by Mosteks lon- implantation technique). The three chip select inputs can be programmed for any desired combination of active highs or lows or even an optional DONT CARE" state. The convenient static operation of the MK34000 coupled with the programmable chip select inputs and three-state TTL O Three programmable chip selects O Inputs and three-state outputs TTL compatible O Outputs drive 2 TTL loads and 100pF 0 RAM/EPROM pin compatible O Pin compatible with Mosteks BYTEWYDE Memory Family compatible outputs results in extremely simple interface requirements. An outstanding feature of the MK34000 is the use of contact programming over gate mask programming. Since the contact mask is applied at a later processing stage, wafers can be partially processed and stored. When an order is received, a contact mask, which represents the desired bit pattern, is generated and applied to the wafers. Only a few processing steps are left to complete the part. Therefore, the use of contact programming reduces the turnaround time for a custom ROM. Any application requiring a high performance, high bit density ROM can be satisfied by this device. The MK34000 is ideally suited for 8-bit microprocessor systems such as those which utilize the Z8O or F8. The MK34000 also provides significant cost advantages over PROM. FUNCTIONAL DIAGRAM Og Ay Az O3 Aq Og, Og 07 = Yeo ~ GND A | cs 10-4 OUTPUT BUFFERS ECoDe dg} Ag ) 0 8 = YOECODER 1/16x8 47 & CHIP 5 SELECT Ag 5 PROG. 4, & | 2 Ag 9 t-8 TH A & | ii 3 c 8 | w 16,384 BIT cs1/CS1/NC* A2 5 CELL MATRIX CHIP t+ 36 SELECT , A, a INPUT ft CS2/CS2/NC [ x BUFFER Ao t | CS3/CS3/NC * PIN CONNECTIONS IY i Ag 1 ie 324. Vee Ag 20 [123 Ag As 34 322 A, 4 4 [i21 s3/s3 Nc* Ag 51] [320 S1/CS1 NC* Ag 6 119 Aag Ay 7q r118 cS2/Cs2 Nc* A 8c 1117 Qy % 90 16 Og Qo 100 15 Og % 174 14 Qy Vss_ 12 P13 Q3 *Programmable Chip Selects Iv1 ROMSABSOLUTE MAXIMUM RATINGS* Voltage on Any Terminal Relative to Vgg ...... eee cee eee eee cnet ene n tenn e nee een eee neeas ~0.5V to +7V Operating Temperature Ta (Ambient)........ 0.0. c cece eee ete eee e cent teen eee e eet e eet en tenes OC to +70C Storage Temperature - Ceramic (Ambient)......... 000 cc cee ee cee ener e eee e ene eee e epee eeeees -65C to +150C Storage Temperature - Plastic (Ambient) ......... 0.00 eee cece eee tree eee tee enn tee eaae -55C to +125C Power Dissipation 2.0... 0... cece ce ee nee eee eee E ORE E REE EE Eee eee EERE EE eee eee Eee 1 Watt *Stresses greater than these listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (Vcc = SV 10%; 0C < Ta = +70C) SYM PARAMETER MIN TYP MAX UNITS NOTES Vee Power Supply Voltage 45 5.0 5.5 Vv 6 VIL Input Logic O Voltage -0.5 08 Vv Vin Input Logic 1 Voltage 2.0 Vec Vv DC ELECTRICAL CHARACTERISTICS (Vcc = SV 10%; OC < Ta < +70C) SYM PARAMETER MIN MAX UNITS NOTES lec Voc Power Supply Current 60 mA 1 WL) Input Leakage Current 10 BA 2 lov) Output Leakage Current 10 pA 3 VoL Output Logic O Voltage 04 Vv @ lout = 3.3mA Vou Output Logic 1 Voltage. 24 Vcc Vv @ lout = -220 pA AC ELECTRICAL CHARACTERISTICS (Vcc = SV 10%; 0C < Ta < +70C) * SYM PARAMETER MIN MAX UNITS NOTES tacc Address to output delay time 350 ns 4 tes Chip select to output delay time ; 175 ns 4 tcp Chip deselect to output delay time 150 ns 4 CAPACITANCE SYM PARAMETER TYP MAX UNITS NOTES Cin Input Capacitance 6 8 pF 5 Cout Output Capacitance 10 15 pF 5 NOTES: 5. Capacitance measured with Boonton Meter or effective capacitance calculated from the equation: 1. All inputs 5.5V; Data Outputs open. C = At with current equal to a constant 20mA. 2. Vin = OV to 5.5V (Veg = 5V) av 3. Device unselected; VgytT = OV to 5.5V. 6. Aminimum 2ms time delay is required after the application of Vcc (+5) before 4. Measured with 2 TTL loads and 100pF, transition times = 20ns. proper device operation is achieved.TIMING DIAGRAM ADDRESS PROGRAMMABLE CHIP SELECTS DATA OUTPUT The chip setect inputs can be user programmed so that either the input is enabled by a Logic 0 voltage (Viv), a Logic 1 voltage (Vjj4), or the input is always enabled (regardless of the VIH Vib VALID x tacc tcs | tcD Vin VALID VIL Vou Vo. OPEN VALID \ oPEN - state of the input). See chart below for programming instructions. MOSTEK 34000 ROM PUNCHED CARD CODING FORMAT (1) FIRST CARD COLS 1-30 31-50 60-72 SECOND CARD 1-30 31-50 THIRD CARD 1-5 33 35 37 FOURTH CARD 1-9 15-28 35-57 INFORMATION FIELD Customer Customer Part Number Mostek Part Number (2) Engineer at Customer Site Direct Phone Number for Engineer Mostek Part Number (2) Chip SelectOne 1" = CSq or O" = CS4 or 2 = Don't Care Chip SelectTwo 1 = CS9 or 0 = CSo or 2 = Don't Care Chip Select Three 1 = CS3 or O" = CS3 or 2 = Don't Care Data Format (3) Logic - (Positive Logic or Negative Logic) Verification Code (4) DATA FORMAT 128 data cards (16 data words/card) with the following format: COLS INFORMATION FIELD 1-4 Four digit octal address of first output word on card 5-7 Three digit octal output word specified by address in column 1-4 8-52 Next fifteen output words, each word consists of three octal digits. NOTES: 1. Positive or negative logic formats are accepted as noted in the fourth card. 2. Assigned by Mostek; may be teft blank. 3. Mostek punched card coding format should be used. Punch Mostek starting in column one. 4. Punches as: (a} VERIFICATION HOLD - i.e. customer verification of the data as reproduced by Mostek is required prior to production of the ROM. To accomplish this Mostek supplies @ copy of its Customer Verification Data Sheet (CVDS) to the customer. (b) VERIFICATION PROCESS - i.e. the customer will receive a CVDS but production will begin prior to receipt of customer verification; (c} VERIFICATION NOT NEEDED -ie. the customer will not receive a CVDS and production will begin immediately.