© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 11
1Publication Order Number:
NLAS4599/D
NLAS4599
Low Voltage Single Supply
SPDT Analog Switch
The NLAS4599 is an advanced high speed CMOS single pole −
double throw analog switch fabricated with silicon gate CMOS
technology. It achieves high speed propagation delays and low ON
resistances while maintaining low power dissipation. This switch
controls analog and digital voltages that may vary across the full
power−supply range (from VCC to GND).
The device has been designed so the ON resistance (RON) is much
lower and more linear over input voltage than RON of typical CMOS
analog switches.
The channel select input is compatible with standard CMOS outputs.
The channel select input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
•Channel Select Input Over−Voltage Tolerant to 5.5 V
•Fast Switching and Propagation Speeds
•Break−Before−Make Circuitry
•Low Power Dissipation: ICC = 2 A (Max) at TA = 25°C
•Diode Protection Provided on Channel Select Input
•Improved Linearity and Lower ON Resistance over Input Voltage
•Latch−up Performance Exceeds 300 mA
•ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
•Chip Complexity: 38 FETs
•Pb−Free Packages are Available
U U
COM
CHANNEL SELECT 2 X 0
2 X 1 NO
U
NC
NO
SELECT 6
1
2
3
5
4
COM
NC
GND
V+
Figure 1. Pin Assignment
Figure 2. Logic Symbol
FUNCTION TABLE
Select ON Channel
L
H
NC
NO
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING
DIAGRAMS
TSOP−6
DT SUFFIX
CASE 318G
SC−88
DF SUFFIX
CASE 419B
A0 MG
G
1
6
A0 = Specific Device Code
M = Date Code
G= Pb−Free Package
(Note: Microdot may be in either location)
1
A0 MG
G
1
1
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See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
NLAS4599
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2
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC Positive DC Supply Voltage −0.5 to +7.0 V
VIS Analog Input Voltage (VNO or VCOM)−0.5 ≤ VIS ≤VCC )0.5 V
VIN Digital Select Input Voltage −0.5 ≤ VI ≤ + 7.0 V
IIK DC Current, Into or Out of Any Pin $50 mA
PDPower Dissipation in Still Air SC−88
TSOP−6
200
200
mW
TSTG Storage Temperature Range −65 to +150 °C
TLLead Temperature, 1mm from Case for 10 seconds 260 °C
TJJunction Temperature Under Bias 150 °C
VESD ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
2000
200
N/A
V
ILATCH−UP Latch−Up Performance Above VCC and Below GND at 125°C (Note 4) $300 mA
JA Thermal Resistance SC−88
TSOP−6
333
333
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
VCC DC Supply Voltage 2.0 5.5 V
VIN Digital Select Input Voltage GND 5.5 V
VIS Analog Input Voltage (NC, NO, COM) GND VCC V
TAOperating Temperature Range −55 +125 °C
tr, tfInput Rise or Fall Time,
SELECT VCC = 3.3 V + 0.3 V
VCC = 5.0 V + 0.5 V
0
0
100
20
ns/V
DEVICE JUNCTION TEMPERATURE VERSUS TIME
TO 0.1% BOND FAILURES
Junction
Temperature 5CTime, Hours Time, Years
80 1,032,200 117.8
90 419,300 47.9
100 178,700 20.4
110 79,600 9.4
120 37,000 4.2
130 17,800 2.0
140 8,900 1.0
1
1 10 100 1000
TIME, YEARS
NORMALIZED FAILURE RATE
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
TJ = 130°C
TJ = 110°C
TJ = 100°C
TJ = 90°C
TJ = 80°C
TJ = 120°C
NLAS4599
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3
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND)
Guaranteed Limit
Symbol Parameter Condition VCC −55 to 255C <855C <1255C Unit
VIH Minimum High−Level
Input Voltage, Select
Input
2.0
2.5
3.0
4.5
5.5
1.5
1.9
2.1
3.15
3.85
1.5
1.9
2.1
3.15
3.85
1.5
1.9
2.1
3.15
3.85
V
VIL Maximum Low−Level
Input Voltage, Select
Input
2.0
2.5
3.0
4.5
5.5
0.5
0.6
0.9
1.35
1.65
0.5
0.6
0.9
1.35
1.65
0.5
0.6
0.9
1.35
1.65
V
IIN Maximum Input Leakage
Current, Select Input
VIN = 5.5 V or GND 5.5 +0.1 +1.0 +1.0 A
IOFF Power Off Leakage
Current
VIN = 5.5 V or GND 0$10 $10 $10 A
ICC Maximum Quiescent
Supply Current
Select and VIS = VCC or GND 5.5 1.0 1.0 2.0 A
DC ELECTRICAL CHARACTERISTICS − Analog Section
Guaranteed Limit
Symbol Parameter Condition VCC −55 to 255C <855C <1255C Unit
RON Maximum “ON”
Resistance
(Figures 17 − 23)
VIN = VIL or VIH
VIS = GND to VCC
IINI < 10.0 mA
2.5
3.0
4.5
5.5
85
45
30
25
95
50
35
30
105
55
40
35
RFLAT
(ON)
ON Resistance Flatness
(Figures 17 − 23)
VIN = VIL or VIH
IINI < 10.0 mA
VIS = 1V, 2V, 3.5V
4.5 4 4 5
RON
(ON)
ON Resistance Match
Between Channels
VIN = VIL or VIH
IINI < 10.0 mA
VNO or VNC = 3.5 V
4.5 2 2 3
INC(OFF)
INO(OFF)
NO or NC Off Leakage
Current (Figure 9)
VIN = VIL or VIH
VNO or VNC = 1.0 VCOM 4.5 V
5.5 1 10 100 nA
ICOM(ON
)
COM ON Leakage
Current (Figure 9)
VIN = VIL or VIH
VNO 1.0 V or 4.5 V with VNC
floating or
VNO 1.0 V or 4.5 V with VNO
floating
VCOM = 1.0 V or 4.5 V
5.5 1 10 100 nA
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4
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
Symbol Parameter Test Conditions
Guaranteed Max Limit
Unit
VCC VIS −55 to 255C <855C <1255C
(V) (V) Min Typ* Max Min Max Min Max
tON Turn−On Time
(Figures 12 and 13)
RL = 300 CL = 35 pF
(Figures 5 and 6)
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
5
5
2
2
23
16
11
9
28
21
16
14
5
5
2
2
30
25
20
20
5
5
2
2
30
25
20
20
ns
tOFF Turn−Off Time
(Figures 12 and 13)
RL = 300 CL = 35 pF
(Figures 5 and 6)
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
7
5
4
3
12
10
9
8
1
1
1
1
15
15
12
12
1
1
1
1
15
15
12
12
ns
tBBM Minimum
Break−Before−Make
Time
VIS = 3.0 V (Figure 4)
RL = 300 CL = 35 pF
2.5
3.0
4.5
5.5
2.0
2.0
3.0
3.0
1
1
1
1
12
11
6
5
1
1
1
1
1
1
1
1
ns
*Typical Characteristics are at 25°C.
Typical @ 25, VCC = 5.0 V
CIN
CNO or CNC
CCOM
C(ON)
Maximum Input Capacitance, Select Input
Analog I/O (switch off)
Common I/O (switch off)
Feedthrough (switch on)
8
10
10
20
pF
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol Parameter Condition
VCC
(V)
Typical
Unit
25°C
BW Maximum On−Channel −3dB Bandwidth or
Minimum Frequency Response
(Figure 10)
VIN = 0 dBm
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
170
200
200
MHz
VONL Maximum Feedthrough On Loss VIN = 0 dBm @ 100 kHz to 50 MHz
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
−3
−3
−3
dB
VISO Off−Channel Isolation
(Figure 10)
f = 100 kHz; VIS = 1 V RMS
VIN centered between VCC and GND
(Figure 7)
3.0
4.5
5.5
−93
−93
−93
dB
QCharge Injection Select Input to
Common I/O
(Figure 15)
VIN = VCC to GND, FIS = 20 kHz
tr = tf = 3 ns
RIS = 0 , CL = 1000 pF
Q = CL * VOUT
(Figure 8)
3.0
5.5
1.5
3.0
pC
THD Total Harmonic Distortion
THD + Noise
(Figure 14)
FIS = 20 Hz to 100 kHz, RL = Rgen = 600 ,
CL = 50 pF
VIS = 5.0 VPP sine wave 5.5 0.1 %
NLAS4599
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5
Figure 4. tBBM (Time Break−Before−Make)
Output
DUT
300
35 pF
VCC
Switch Select Pin
90%
Output
Input
VCC
GND
90% of VOH
GND
Figure 5. tON/tOFF
50% 50%
90% 90%
tON tOFF
VOH
Output
Input
VCC
0 V
Figure 6. tON/tOFF
DUT
Open 35 pF
VCC
Input
50% 50%
10%
tON
tOFF
Output
Input
VCC
0 V
10%
300
0.1 F
tBMM
Output
VOUT
VOL
VOUT VOH
VOL
DUT
Open
VCC
Input
Output
300
35 pF
VOUT
0.1 F
NLAS4599
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6
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is
the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction.
VISO = Off Channel Isolation = 20 Log for VIN at 100 kHz
VONL = On Channel Loss = 20 Log for VIN at 100 kHz to 50 MHz
Bandwidth (BW) = the frequency 3 dB below VONL
Output
DUT
Input
50
50 Generator
Reference
Transmitted
Figure 7. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
50
ǒVOUT
VIN Ǔ
ǒVOUT
VIN Ǔ
Off On Off VOUT
VCC
GND
Output
VIN
CL
DUT
Figure 8. Charge Injection: (Q)
VIN
Open Output
−55 −20
LEAKAGE (nA)
Figure 9. Switch Leakage vs. Temperature
1
INO(OFF)
TEMPERATURE (°C)
0.01
25
0.001
0.1
70 85 125
ICOM(ON)
ICOM(OFF)
VCC = 5.0 V
10
100
NLAS4599
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7
1
0.1
0.01
3.0
10
30
20
30
FREQUENCY (MHz)
Figure 10. Bandwidth and Off−Channel
Isolation
Figure 11. Phase vs. Frequency
2.5 4.535
Figure 12. tON and tOFF vs. VCC at 255C
VCC (VOLTS)
Figure 13. tON and tOFF vs. Temp
Temperature (°C)
TIME (ns)
TIME (ns)
Figure 14. Total Harmonic Distortion
Plus Noise vs. Frequency
FREQUENCY (kHz)
Figure 15. Charge Injection vs. COM Voltage
VCOM (V)
THD + NOISE (%)
Q (pC)
101 100
0.01 0.1 100
−55 25 125−40
20
15
25
0
034215
tON
VCC = 3 V
VCC = 5 V
2.5
2.0
1.5
1.0
0.5
0
−0.5
VINpp = 5.0 V
VCC = 5.5 V
VINpp = 3.0 V
VCC = 3.6 V
10
5tOFF
tON (ns)
tOFF (ns)
1 10 200
0
VCC = 5.0 V
TA = 25°C
PHASE (Degree)
VCC = 4.5 V
3.5 4
30
20
15
25
0
10
5
85
0.01 1010.1
(dB)
−100
0
Off Isolation
FREQUENCY (MHz)
100 200
−80
−60
−40
−20
Bandwidth
(ON−RESPONSE)
VCC = 5.0 V
TA = 25°C
NLAS4599
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8
0
5
10
15
20
25
30
35
40
45
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
25°C
−55°C
85°C
125°C
85°C
−55°C
125°C
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5
25°C
−55°C
85°C
25°C
125°C
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0 2.01.0 3.0 4.0 5.0 6.0
Temperature (°C)
Figure 16. ICC vs. Temp, VCC = 3 V & 5 V
ICC (nA)
80
100
60
40
20
0
Figure 17. RON vs. VCC, Temp = 255C
VIS (VDC)
Figure 18. RON vs Temp, VCC = 2.0 V
RON ()
RON ()
Figure 19. RON vs. Temp, VCC = 2.5 V
VIS (VDC)
Figure 20. RON vs. Temp, VCC = 3.0 V
VIS (VDC)
RON ()
RON ()
−40 60 80200 100−20 120
VCC = 2.0 V
VCC = 2.5 V
VCC = 3.0 V VCC = 4.0 V
VCC = 5.5 V
VCC = 3.0 V
VCC = 5.0 V
10
1
0.1
100
0.01
0.001
0.0001
0.00001
Figure 21. RON vs. Temp, VCC = 4.5 V
VIS (VDC)
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
RON ()
VIS (VDC)
25°C
−55°C
125°C
85°C
NLAS4599
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9
Figure 22. RON vs. Temp, VCC = 5.0 V Figure 23. RON vs. Temp, VCC = 5.5 V
20
15
RON ()
10
25
VIS (VDC)
5
0
0.0 2.01.51.00.5 2.5 3.0 3.5 4.0 4.5 5.0
25°C
85°C
125°C
−55°C
20
15
RON ()
10
25
VIS (VDC)
5
0
0.0 2.01.51.00.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5
25°C
85°C
125°C
−55°C
ORDERING INFORMATION
Device
Device Nomenclature
Package Shipping†
Circuit
Indicator Technology
Device
Function Suffix
NLAS4599DFT2 NL AS DF T2 SC−88 3000 / Tape & Reel
NLAS4599DFT2G NL AS DF T2G SC−88
(Pb−Free)
3000 / Tape & Reel
NLAS4599DTT1 NL AS DT T1 TSOP−63000 / Tape & Reel
NLAS4599DTT1G NL AS DT T1G TSOP−6
(Pb−Free)
3000 / Tape & Reel
NLVAS4599DFT2 NL AS DF T2 SC−88 3000 / Tape & Reel
NLVAS4599DFT2G NL AS DF T2G SC−88
(Pb−Free)
3000 / Tape & Reel
NLVAS4599DTT1G NL AS DT T1G TSOP−6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NLAS4599
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10
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE W
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.
E0.2 (0.008) MM
123
D
e
A1
A
A3
C
L
654
−E−
b6 PL
DIM MIN NOM MAX
MILLIMETERS
A0.80 0.95 1.10
A1 0.00 0.05 0.10
A3
b0.10 0.21 0.30
C0.10 0.14 0.25
D1.80 2.00 2.20
0.031 0.037 0.043
0.000 0.002 0.004
0.004 0.008 0.012
0.004 0.005 0.010
0.070 0.078 0.086
MIN NOM MAX
INCHES
0.20 REF 0.008 REF
HE
HE
E1.15 1.25 1.35
e0.65 BSC
L0.10 0.20 0.30
2.00 2.10 2.20
0.045 0.049 0.053
0.026 BSC
0.004 0.008 0.012
0.078 0.082 0.086
ǒmm
inchesǓ
SCALE 20:1
0.65
0.025
0.65
0.025
0.50
0.0197
0.40
0.0157
1.9
0.0748
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SC−88/SC70−6/SOT−363
NLAS4599
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11
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE S
23
456
D
1
e
b
E
A1
A
0.05 (0.002)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
c
L
0.95
0.037
1.9
0.075
0.95
0.037
ǒmm
inchesǓ
SCALE 10:1
1.0
0.039
2.4
0.094
0.7
0.028
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
HE
DIM
A
MIN NOM MAX MIN
MILLIMETERS
0.90 1.00 1.10 0.035
INCHES
A1 0.01 0.06 0.10 0.001
b0.25 0.38 0.50 0.010
c0.10 0.18 0.26 0.004
D2.90 3.00 3.10 0.114
E1.30 1.50 1.70 0.051
e0.85 0.95 1.05 0.034
L0.20 0.40 0.60 0.008
0.039 0.043
0.002 0.004
0.014 0.020
0.007 0.010
0.118 0.122
0.059 0.067
0.037 0.041
0.016 0.024
NOM MAX
2.50 2.75 3.00 0.099 0.108 0.118
HE
− −
0°10°0°10°
q
q
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
NLAS4599/D
PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
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l
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