MICROCHIP 93LC56A/B 2K 2.5V Microwire Serial EEPROM FEATURES Single supply with operation down to 2.5V Low power GMOS technology - 1 mA active current (typical) - 1 pA standby current (maximum) 256 x 8 bit organization (93LC56A) 128 x 16 bit organization (S3LC56B) Self-timed ERASE and WRITE cycles (including auto-erase) Automatic ERAL before WRAL Power on/off data protection circuitry Industry standard 3-wire serial interface Device status signal during ERASE/WRITE cycles Sequential READ function 1,000,000 E/W cycles guaranteed Data retention > 200 years 8-pin PDIP/SOIC and 8-pin TSSOP packages Available for the following temperature ranges: ee ef @ @ @ BLOCK DIAGRAM MeMorY KlADDRESS ARRAY DECODER t AODRESS COUNTER OUTPUT | BUFFER | 2 4 DATA REGISTER DI CS LOGIC Voc CLOCK CLK GENERATOR Vss - Commercial (C): oc to +70C - Industrial (1): 40C to +85C DESCRIPTION The Microchip Technology Inc. 93LC56A/B are 2K-bit, low-voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC56A) or x16 bits (93LC56B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 938LC56A/B is available in standard 8-pin DIP, surface mount SOIC, and TSSOP packages. The 93LC56AX/BX are only offered in a 150-mil SOIC package. PACKAGE TYPE pIP soic soc TSSOP cs - cst am Ut 2 {Jee esctt' ogg) 8 vee NUL g ne ocikal2- & 7ENo cik(]z2 & 7[Nc 2 cq pies = SC LNG 8 ciKC_? QO 7 CONC Veo | a Vss DOcH4 5 5 vss Dl Us > SLING cs z 8[ "nc = csc = DO po |4 o 5(_]Vss o & poc|4 5[ vss 9 CLK | Dl Microwire is a registered trademark of National Semiconductor. 1997 Microchip Technology Inc. Preliminary DS21208A-page 1 MCHPS0007493LC56A/B 1.0 ELECTRICAL TABLE 1-1 PIN FUNCTION TABLE CHARACTERISTICS Name Function 1.1 Maximum Ratings* cs Chip Select 70V CLK Serial Data Clock All inputs and outputs w.rt. Vss . 0.6V to Veo +1.0V DI Serial Data Input Storage temperature ............... . -B5C to +150C DO Serial Data Output Ambient temp. with power applied................. -B5C to +125C Soldering temperature of leads (10 seconds) .............+300C Vss Ground ESD protection on all pins... cccccsecceesseecseneeeeeee 4kV NG No Connect Notice: Stresses above those listed under Maximum ratings may Vcc Power Supply cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri- ods may atfect device reliability. TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS All parameters apply over the specified | Commercial (C): Vcc #+2.5V10+6.0V Tamb= 0C to +70C operating ranges unless otherwise Industrial (I): VCC = +2.5V to +6.0V = Tamb = -40C to +85C noted Parameter Symbol Min. Max. Units Conditions j | Vint 2.0 Voc +1 Vv 2.7V < Vcc < 5.5V (Note 2) High level input voltage Vind 0.7 Voc Veo +1 v Voc <2.7V . Vitd 0.3 0.8 v Vcc > 2.7V (Note 2) Low level input voltage ViL2 -0.3 0.2 Vcc v Voc <2.7V Low level output voltage VoLt _ 04 v lot = 2.1 MA; Voc = 4.5V VoL2 _ 02 v IOL =100 pA; Veco = Vec Min. Vout 2.4 ~~ Vv OH = -400 HA; Vec = 4.5V High level output voltage . VouH2 Vec-0.2 _ Vv IOH = -100 HA; Vec = Vee Min. Input leakage current IL -10 10 pA VIN = VSS Output leakage current ILo -10 10 pA Vout = Vss re cmcou | | 7 | or [ymvousov More 42 Operating current | Word | 500 WA | Bout Mie: Voc 2 30V Icc write - 15 mA Standby current Iecs _ 1 pA CS = Vss Clock requency FouK = i Miz |Voo<asv Clock high time TCKH 250 _ ns Clock low time Tex 250 _ ns Chip select setup time Toss 50 _- ns Relative to CLK Chip select hold time TcsH 0 - ns Relative to CLK Chip select low time TCSL 250 - ns Data input setup time Tos 100 _ ns Relative to CLK Data input hold time TolH 100 - ns Relative to CLK Data output delay time TPD 400 ns Cl = 100 pF Data output disable time Tez _ 100 ns Cl = 100 pF (Note 2) Status valid time Tsv - 500 ns Cl = 100 pF Two _ 6 ms ERASE/WRITE mode Program cycle time TEC _ 6 ms ERAL mode TWu -> 15 ms WRAL mode Endurance | 1M - cycles 25C, Vcc = 5.0V, Block Mode (Note 3) Note 1: This parameter is tested at Tamb = 25C and Fcik = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consutt the Total Endurance Model which may be obtained on Microchip's BBS or website. DS21208A-page 2 Preliminary 1997 Microchip Technology Inc.93LC56A/B PIN DESCRIPTION Chip Select (CS 2.0 21 A high level selects the device; a low level deselects the device and forces it into standby mode. However, a pro- gramming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the pro- gramming cycle is completed. CS must be low for 250 ns minimum (TcsL} between consecutive instructions. If CS is low, the internal con- trol logic is held in a RESET status. Serial Clock (CLK) The Serial Clock is used to synchronize the communi- cation between a master device and the S3LC56A/B. Opcode, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. 2.2 CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. CLK is a Don't Care if CS is low (device deselected). lf CS is high, but START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for START condition). CLK cycles are not required during the self-timed WRITE ({i.e., auto ERASE/WRITE) cycle. After detection of a START condition the specified num- ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Tabie 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected. Data In (DI) Data In is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. 2.4 Data Out (DO) Data Out is used in the READ mode to output data syn- chronously with the CLK input (Tep after the positive edge of CLK). This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY sta- tus information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. tn this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. 2.3 TABLE 2-1 INSTRUCTION SET FOR 93LC56A . Instruction | SB | Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 an X A7 AB AS A4 AB AZ AT AD _ (RDY/BSY) 12 ERAL 1 00 1 0 xX X X X X X Xx _ (RDY/BSY) 12 EWDS 1 00 0 0 X X X X X X X _ HIGH-Z 12 EWEN 1 00 41314 *X X X X X X X _ HIGH-Z 12 READ 1 10 X A7 AB AS A4 AB AZ AL AD _ D7 - 00 20 WRITE 1 01 X A7 AB AS A4 ABD AZ Al AO) D7-DO (ROY/BSY) 20 WRAL 1 00 o 1X X X X X X XJ] D7-Do (RDY/BSY) 20 TABLE 2-2 INSTRUCTION SET FOR 93LC56B Instruction | SB | Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 1 X | AB] AS As] AB | AZ] AT] AO = (RDY/BSY) "1 ERAL 1 00 1 a0 %X% X xX X XxX xX (RDY/BSY) 1 EWDS 1 00 0 o xX X X X xX xX HIGH-Z 11 EWEN 1 00 1 1 X MWR X X XX X _ HIGH-Z 11 READ 1 10 X AG AS Ad AZ AZ Al AO _ Di5- DO 27 WRITE 1 01 X AB AS A4 AB A2 At AOD] DI5-DO]| (RDY/BSY) 27 WRAL 1 00 0 41 X X X XX XxX xX | DI5-DO} (RDY/BSY) 27 1997 Microchip Technology Inc. _ Preliminary DS21208A-page 393LC56A/B 3.0 FUNCTIONAL DESCRIPTION Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. 3.1 START Condition The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device oper- ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as GS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcode, address and data bits for any particular instruction is clocked in. After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new START condition is detected. FIGURE 3-1: SYNCHRONOUS DATA TIMING 3.2 DATA IN (DI) AND DATA OUT (DO [It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if AO is a logic-high level, it is possible for a bus conflict fo occur during the dummy zero that precedes the READ operation. Under such a condition, the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driv- ing AO. The higher the current sourcing capability of AO, the higher the voltage at the DO pin. 3.3 Data Protection During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions. The EWDS and EWEN commands give additional pro- tection against accidentally programming during normal operation. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed. cs VIH VIL VIH CLK VIL Vin Di VIL DO VoH (READ) yo. DO VOH (PROGRAM) VoL Note: AC Test Conditions: VIL = 0.4V, VIH - 2.4V. STATUS VALID DS21208A-page 4 Pratininary 1997 Microchip Technology Inc.93LC56A/B 3.4 ERASE 3.5 Erase All (ERAL) The ERASE instruction forces all data bits of the spec- The ERAL instruction will erase the entire memory ified address to the logical 1 state. CS is brought low array to the logical "1" state. The ERAL cycle is identical following the loading of the last address bit. This falling to the ERASE cycle except for the different opcode. The edge of the CS pin initiates the self-timed programming ERAL cycle is completely self-timed and commences at cycle. the falling edge of the CS. Clocking of the CLK pin is not The DO pin indicates the READY/BUSY status of the necessary after the device has entered the ERAL cycle. device if CS is brought high after a minimum of 250 ns The DO pin indicates the READY/BUSY status of the low (Tcst). DO at logical "0" indicates that program- device if CS is brought high after a minimum of 250 ns ming is still in progress. DO at logical 1 indicates that low (TCSL) and before the entire ERAL cycle is com- the register at the specified address has been erased plete. and the device is ready for another instruction. FIGURE 3-2: ERASE TIMING co 0ULUS KZ TU WU LLP? TL HIGH-Z po f Tost L me | ff CHECK STATUS ~ a je FIGURE 3-3: ERAL TIMING TCSL cs / X 7 CHECK STATUS TS LLL LLP bl 1 0 oO 1 \o ox HIGH-Z A A ~ Guaranteed at Vec = 4.5V to +6.0V. Tah Ls j soot] 1997 Microchip Technology Inc. PQvEnary DS21208A-page 593LC56A/B 3.6 ERASE/WRITE Disable and Enable (EWDS/EWEN) The 93LC56A/B powers up in the ERASE/WRITE Disable (EWDS) state. All programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruc- tion is executed or Vcc is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming opera- tions. Execution of a READ instruction is independent of both the EWDS and EWEN instructions. FIGURE 3-4: EWDSTIMING 3.7 READ The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the &-bit (93LC56A) or 16-bit (93LC568) output string. The output cata bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPp). Sequential read is possible when CS is held high. The memory data will automati- cally cycle to the next register and output sequentially. oc | O/ DI 1 Q 0 0 0 TUUUU UU UL UU Ue Tost a peng FIGURE 3-5: EWENTIMING DI FIGURE 3-6: READ TIMING cs / DO HIGH-Z DS21208A-page 6 oo a Preliminary 1997 Microchip Technology Inc.93LC56A/B 3.8 WRITE The WRITE instruction is followed by 8 bits (S3LG56A) or 16 bits (93LC56B) of data which are written into the specified address. After the last data bit is put on the DI pin, the falling edge of CS initiates the self-timed auto- erase and programming cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical "0" indicates that programming is still in progress. DO at logical 1 indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc- tion. FIGURE 3-7: WRITE TIMING 3.9 Write All (WRAL) The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and com- mences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TcSL). FIGURE 3-8: WRALTIMING sc DI 1 Q 9 QO 1 H-Z D0 HIG Guaranteed at Voc = 4.5V to 48.0V. 1997 Microchip Technology Inc. Ore Bral sock] 2] mingry DS21208A-page 793LC56A/B NOTES: DS21208A-page B Preliminary 1997 Microchip Technology Inc.93LC56A/B NOTES: ee 1997 Microchip Technology Inc. Preliminary DS21208A-page 993LC56A/B NOTES: = es DS21208A-page 10 Preliminary 1997 Microchip Technology Inc.93LC56A/B 93LC56A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 93LC56A/B ip yu Package: Temperature Range: Device: SN SM ST Blank = 93LC56A 93LCS5S6AT 93LC56AX 93LC56AXT 93LC56B 93LC56BT 93LC56BX 93LCS6BXT Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (208 mil Body), 8-lead TSSOP, 8-lead 0%C to +70%C -40% to +85C 2K Microwire Serial EEPROM (x8) 2K Microwire Serial EEPROM (x8) Tape and Reel 2K Microwire Serial EEPROM (x8) in alternate pinout (SN only) 2K Microwire Serial EEPROM (x8) in alternate pinout, Tape and Reel (SN only) 2K Microwire Serial EEPROM (x16} 2K Microwire Serial EEPROM (x16) Tape and Reel 2K Microwire Serial EEPROM (x16) in alternate pinout (SN only) 2K Microwire Serial EEPROM (x16) in alternate pinout, Tape and Reel (SN only) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). 1997 Microchip Technology Inc. ar EET = Braliminary DS21208A-page 11WORLDWIDE SALES & SERVICE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandier Bivd. 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EUROPE United Kingdom Arizona Microchip Technology Ltd. Unit 6, The Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire SL 5AJ Tel: 44-1628-851077 Fax: 44-1628-850259 France Arizona Microchip Technology SARL Zone industrielle de ta Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 0-81739 Michen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 italy Arizona Microchip Technology SRL Centro Direzionale Colleone Palazzo Taurus 1 V. Le Co#eoni 1 20041 Agrate Brianza Milan, Haly Tel: 39-39-6899939 Fax: 39-39-6699883 JAPAN Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shin Yokohama Kehoku-Ku, Yokohama Kanagawa 222 Japan Tel: 81-4-5471- 6166 Fax: 81-4-5471-6122 5/8/97 All rights reserved. @ 1997, Microchip Technology Incorporated, USA. 5/97 Information contained in this publication regarding device ions and the like is intended for suggestion only and may de Superseded by upd . No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or ather intefleciual property rights arising Irom such use or otherwse. Use of Microchip's products as critical componenis in lile support systems is not autnorizec except with express written approval by Microchip. No licenses are conveyed, implicitly or othenwise, under any intellectual property rights. The Mcrochio lago and name are registered trademarks ot Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21208A-page 12 Preliminary 1997 Microchip Technology Inc.