SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Eight High-Current Latches in a Single
Package
D
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
D
Full Parallel Access for Loading
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Ceramic Flat (W) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight latches of the ’HC373 are transparent
D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When LE is taken low, the Q outputs are latched
at the levels that were set up at the D inputs.
An output-enable (OE) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are off.
The SN54HC373 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HC373 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D V
8Q
4Q
GND
LE
SN54HC373 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HC373 ...J OR W PACKAGE
SN74HC373 . . . DB, DW, N, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
OE LE DQ
L H H H
LHL L
LLX Q
0
H X X Z
logic symbol†
1D
3
1D 4
2D 7
3D
EN
1
1Q
2
2Q
5
3Q
6
8
4D 13
5D 14
6D
4Q
9
5Q
12
6Q
15
OE
17
7D 18
8D
C1
11
LE
7Q
16
8Q
19
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
32
LE
1D
C1
1D 1Q
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 115°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
SN54HC373 SN74HC373
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0 0.5 0 0.5
VIL Low-level input voltage VCC = 4.5 V 0 1.35 0 1.35 V
VCC = 6 V 0 1.8 0 1.8
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V 0 1000 0 1000
ttInput transition (rise and fall) time VCC = 4.5 V 0 500 0 500 ns
VCC = 6 V 0 400 0 400
TAOperating free-air temperature –55 125 –40 85 °C
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 1.9 1.998 1.9 1.9
IOH = –20 µA4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6 V 5.9 5.999 5.9 5.9 V
IOH = –6 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –7.8 mA 6 V 5.48 5.8 5.2 5.34
2 V 0.002 0.1 0.1 0.1
IOL = 20 µA4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6 V 0.001 0.1 0.1 0.1 V
IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 7.8 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0 6 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA
Ci2 V to 6 V 3 10 10 10 pF
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
2 V 80 120 100
twPulse duration, LE high 4.5 V 16 24 20 ns
6 V 14 20 17
↓
2 V 50 75 63
tsu Setup time, data before LE
↓
4.5 V 10 15 13 ns
6 V 9 13 11
↓
2 V 20 26 24
thHold time, data after LE
↓
4.5 V 10 13 12 ns
6 V 10 13 12
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 58 150 225 190
D Q 4.5 V 15 30 45 38
td
6 V 13 26 38 32
ns
t
pd 2 V 73 175 265 220
ns
LE Any Q 4.5 V 18 35 53 44
6 V 15 30 45 38
2 V 65 150 225 190
ten OE Any Q 4.5 V 17 30 45 38 ns
6 V 14 26 38 32
2 V 50 150 225 190
tdis OE Any Q 4.5 V 15 30 45 38 ns
6 V 13 26 38 32
2 V 28 60 90 75
ttAny Q 4.5 V 8 12 18 15 ns
6 V 6 10 15 13
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO
VCC
TA = 25°C SN54HC373 SN74HC373
UNIT
PARAMETER
(INPUT) (OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
2 V 82 200 300 250
D Q 4.5 V 22 40 60 50
td
6 V 19 34 51 43
ns
t
pd 2 V 100 225 335 285
ns
LE Any Q 4.5 V 24 45 67 57
6 V 20 38 57 48
2 V 90 200 300 250
ten OE Any Q 4.5 V 23 40 60 50 ns
6 V 19 34 51 43
2 V 45 210 315 265
ttAny Q 4.5 V 17 42 63 53 ns
6 V 13 36 53 45
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per latch No load 100 pF
SN54HC373, SN74HC373
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS140B – DECEMBER 1982 – REVISED MAY 1997
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
50%
50%50% 10%10% 90% 90%
VCC
VCC
0 V
0 V
trtf
Reference
Input
Data
Input
50%
High-Level
Pulse 50% VCC
0 V
50% 50%
VCC
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50%
50%50% 10%10% 90% 90%
VCC
VOH
VOL
0 V
trtf
Input
In-Phase
Output
50%
tPLH tPHL
50% 50%
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
50%
10%
90%
VCC
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
W aveform 1
(See Note B)
50%
tPZL tPLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOH
≈0 V
50%
50%
tPZH
tPHZ
Output
W aveform 2
(See Note B)
≈VCC
Test
Point
From Output
Under Test
RL
VCC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF Open Open––
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
CL
(see Note A)
Figure 1. Load Circuit and Voltage Waveforms
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Copyright 1998, Texas Instruments Incorporated
