MF1282-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N08 / 60R08 Technical Manual S1C60N08 Technical Hardware/S1C60R08 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. (c) SEIKO EPSON CORPORATION 2001 All rights reserved. S1C60N08/S1C60R08 Technical Manual This publication consists of two manuals that explain the hardware specifications of the S1C60N08 and S1C60R08 (ROM emulator model for S1C60N08) CMOS 4-bit single chip microcomputers. I. S1C60N08 Technical Hardware This manual describes the functions, circuit configuration and control method of the S1C60N08. II. S1C60R08 Technical Hardware This manual describes the hardware specifications of the S1C60R08 except where the functions are the same as the S1C60N08. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08: for S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 Family processors Previous No. E0C6001 E0C6002 E0C6003 E0C6004 E0C6005 E0C6006 E0C6007 E0C6008 E0C6009 E0C6011 E0C6013 E0C6014 E0C60R08 New No. S1C60N01 S1C60N02 S1C60N03 S1C60N04 S1C60N05 S1C60N06 S1C60N07 S1C60N08 S1C60N09 S1C60N11 S1C60N13 S1C60140 S1C60R08 S1C62 Family processors Previous No. E0C621A E0C6215 E0C621C E0C6S27 E0C6S37 E0C623A E0C623E E0C6S32 E0C6233 E0C6235 E0C623B E0C6244 E0C624A E0C6S46 New No. S1C621A0 S1C62150 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N35 S1C6N3B0 S1C62440 S1C624A0 S1C6S460 Previous No. E0C6247 E0C6248 E0C6S48 E0C624C E0C6251 E0C6256 E0C6292 E0C6262 E0C6266 E0C6274 E0C6281 E0C6282 E0C62M2 E0C62T3 New No. S1C62470 S1C62480 S1C6S480 S1C624C0 S1C62N51 S1C62560 S1C62920 S1C62N62 S1C62660 S1C62740 S1C62N81 S1C62N82 S1C62M20 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 Family Previous No. ASM62 DEV6001 DEV6002 DEV6003 DEV6004 DEV6005 DEV6006 DEV6007 DEV6008 DEV6009 DEV6011 DEV60R08 DEV621A DEV621C DEV623B DEV6244 DEV624A DEV624C DEV6248 DEV6247 New No. S5U1C62000A S5U1C60N01D S5U1C60N02D S5U1C60N03D S5U1C60N04D S5U1C60N05D S5U1C60N06D S5U1C60N07D S5U1C60N08D S5U1C60N09D S5U1C60N11D S5U1C60R08D S5U1C621A0D S5U1C621C0D S5U1C623B0D S5U1C62440D S5U1C624A0D S5U1C624C0D S5U1C62480D S5U1C62470D Previous No. DEV6262 DEV6266 DEV6274 DEV6292 DEV62M2 DEV6233 DEV6235 DEV6251 DEV6256 DEV6281 DEV6282 DEV6S27 DEV6S32 DEV6S37 EVA6008 EVA6011 EVA621AR EVA621C EVA6237 EVA623A New No. S5U1C62620D S5U1C62660D S5U1C62740D S5U1C62920D S5U1C62M20D S5U1C62N33D S5U1C62N35D S5U1C62N51D S5U1C62560D S5U1C62N81D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N11E S5U1C621A0E2 S5U1C621C0E S5U1C62N37E S5U1C623A0E Previous No. EVA623B EVA623E EVA6247 EVA6248 EVA6251R EVA6256 EVA6262 EVA6266 EVA6274 EVA6281 EVA6282 EVA62M1 EVA62T3 EVA6S27 EVA6S32R ICE62R KIT6003 KIT6004 KIT6007 New No. S5U1C623B0E S5U1C623E0E S5U1C62470E S5U1C62480E S5U1C62N51E1 S5U1C62N56E S5U1C62620E S5U1C62660E S5U1C62740E S5U1C62N81E S5U1C62N82E S5U1C62M10E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C60N03K S5U1C60N04K S5U1C60N07K I. S1C60N08 Technical Hardware CONTENTS CONTENTS CHAPTER 1 OVERVIEW _______________________________________________ I-1 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER Configuration .............................................................................................. Features ....................................................................................................... Block Diagram ............................................................................................ Pin Layout Diagram ................................................................................... Pin Description ........................................................................................... S1C60N08 Option List ................................................................................ I-1 I-1 I-2 I-3 I-4 I-4 2 POWER SUPPLY AND INITIAL RESET ____________________________ I-7 2.1 2.2 Power Supply .............................................................................................. I-7 Initial Reset ................................................................................................. I-9 2.2.1 Power-on reset circuit ............................................................................... I-9 2.2.2 RESET terminal ......................................................................................... I-9 2.2.3 Simultaneous high input to input ports (K00-K03) ................................. I-9 2.2.4 Watchdog timer ......................................................................................... I-10 2.2.5 Internal register at initial reset ................................................................ I-10 2.3 CHAPTER 3 CPU, ROM, RAM _______________________________________ I-11 3.1 3.2 3.3 CHAPTER Test Terminal (TEST) ................................................................................. I-10 CPU ............................................................................................................ I-11 ROM ........................................................................................................... I-11 RAM ........................................................................................................... I-11 4 PERIPHERAL CIRCUITS AND OPERATION _________________________ I-12 4.1 4.2 Memory Map .............................................................................................. I-12 Resetting Watchdog Timer ......................................................................... I-16 4.2.1 Configuration of watchdog timer ............................................................. I-16 4.2.2 Mask option .............................................................................................. I-16 4.2.3 Control of watchdog timer ....................................................................... I-16 4.2.4 Programming note .................................................................................... I-16 4.3 Oscillation Circuit and Prescaler .............................................................. I-17 4.3.1 Configuration of oscillation circuit and prescaler .................................. I-17 4.3.2 OSC1 oscillation circuit ........................................................................... I-17 4.3.3 OSC3 oscillation circuit ........................................................................... I-18 4.3.4 Control of oscillation circuit and prescaler ............................................ I-19 4.3.5 Programming notes .................................................................................. I-20 4.4 Input Ports (K00-K03, K10, K20-K23) .................................................... I-21 4.4.1 Configuration of input ports .................................................................... I-21 4.4.2 Input comparison registers and interrupt function ................................. I-21 4.4.3 Mask option .............................................................................................. I-24 4.4.4 Control of input ports ............................................................................... I-24 4.4.5 Programming notes .................................................................................. I-26 4.5 Output Ports (R00-R03, R10-R13) ........................................................... I-27 4.5.1 Configuration of output ports .................................................................. I-27 4.5.2 Mask option .............................................................................................. I-27 4.5.3 Control of output ports ............................................................................. I-29 4.5.4 Programming note .................................................................................... I-30 S1C60N08 TECHNICAL HARDWARE EPSON I-i CONTENTS 4.6 I/O Ports (P00-P03, P10-P13) ................................................................. I-31 4.6.1 Configuration of I/O ports ....................................................................... I-31 4.6.2 I/O control register and I/O mode ........................................................... I-31 4.6.3 Mask option .............................................................................................. I-31 4.6.4 Control of I/O ports .................................................................................. I-32 4.6.5 Programming notes .................................................................................. I-33 4.7 Serial Interface (SIN, SOUT, SCLK) ......................................................... I-34 4.7.1 Configuration of serial interface ............................................................. I-34 4.7.2 Master mode and slave mode of serial interface ..................................... I-34 4.7.3 Data input/output and interrupt function ................................................ I-35 4.7.4 Mask option .............................................................................................. I-37 4.7.5 Control of serial interface ........................................................................ I-38 4.7.6 Programming notes .................................................................................. I-40 4.8 LCD Driver (COM0-COM3, SEG0-SEG47) ........................................... I-41 4.8.1 Configuration of LCD driver ................................................................... I-41 4.8.2 Cadence adjustment of oscillation frequency .......................................... I-46 4.8.3 Mask option (segment allocation) ............................................................ I-47 4.8.4 Control of LCD driver .............................................................................. I-48 4.8.5 Programming notes .................................................................................. I-49 4.9 Clock Timer ................................................................................................ I-50 4.9.1 Configuration of clock timer .................................................................... I-50 4.9.2 Interrupt function ..................................................................................... I-50 4.9.3 Control of clock timer .............................................................................. I-51 4.9.4 Programming notes .................................................................................. I-52 4.10 Stopwatch Timer ......................................................................................... I-53 4.10.1 Configuration of stopwatch timer .......................................................... I-53 4.10.2 Count-up pattern .................................................................................... I-53 4.10.3 Interrupt function ................................................................................... I-54 4.10.4 Control of stopwatch timer .................................................................... I-55 4.10.5 Programming notes ................................................................................ I-56 4.11 Sound Generator ........................................................................................ I-57 4.11.1 Configuration of sound generator ......................................................... I-57 4.11.2 Frequency setting ................................................................................... I-58 4.11.3 Digital envelope ..................................................................................... I-58 4.11.4 Mask option ............................................................................................ I-59 4.11.5 Control of sound generator .................................................................... I-60 4.11.6 Programming note .................................................................................. I-61 4.12 Event Counter ............................................................................................ I-62 4.12.1 Configuration of event counter .............................................................. I-62 4.12.2 Switching count mode ............................................................................ I-62 4.12.3 Mask option ............................................................................................ I-63 4.12.4 Control of event counter ......................................................................... I-64 4.12.5 Programming notes ................................................................................ I-65 4.13 Analog Comparator ................................................................................... I-66 4.13.1 Configuration of analog comparator ..................................................... I-66 4.13.2 Operation of analog comparator ........................................................... I-66 4.13.3 Control of analog comparator ............................................................... I-67 4.13.4 Programming notes ................................................................................ I-67 4.14 Battery Life Detection (BLD) Circuit ........................................................ I-68 4.14.1 Configuration of BLD circuit ................................................................. I-68 4.14.2 Programmable selection of evaluation voltage ..................................... I-68 4.14.3 Detection timing of BLD circuit ............................................................. I-69 4.14.4 Control of BLD circuit ........................................................................... I-70 4.14.5 Programming notes ................................................................................ I-71 I-ii EPSON S1C60N08 TECHNICAL HARDWARE CONTENTS 4.15 Heavy Load Protection Function and Sub-BLD Circuit ........................... I-72 4.15.1 Heavy load protection function .............................................................. I-72 4.15.2 Operation of sub-BLD circuit ................................................................ I-73 4.15.3 Control of heavy load protection function and sub-BLD circuit .......... I-74 4.15.4 Programming notes ................................................................................ I-76 4.16 Interrupt and HALT ................................................................................... I-77 4.16.1 Interrupt factors ..................................................................................... I-79 4.16.2 Specific masks and factor flags for interrupt ........................................ I-79 4.16.3 Interrupt vectors ..................................................................................... I-80 4.16.4 Control of interrupt and HALT .............................................................. I-81 4.16.5 Programming notes ................................................................................ I-82 CHAPTER 5 SUMMARY OF NOTES ______________________________________ I-83 5.1 5.2 5.3 Notes for Low Current Consumption ......................................................... I-83 Summary of Notes by Function .................................................................. I-84 Precautions on Mounting .......................................................................... I-89 CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM ___________________________ I-91 CHAPTER 7 ELECTRICAL CHARACTERISTICS _______________________________ I-93 7.1 7.2 7.3 7.4 7.5 CHAPTER I-93 I-93 I-94 I-95 I-98 8 PACKAGE _______________________________________________ I-99 8.1 8.2 CHAPTER Absolute Maximum Rating ......................................................................... Recommended Operating Conditions ........................................................ DC Characteristics .................................................................................... Analog Circuit Characteristics and Current Consumption ...................... Oscillation Characteristics ........................................................................ Plastic Package .......................................................................................... I-99 Ceramic Package for Test Samples ........................................................... I-100 9 PAD LAYOUT ____________________________________________ I-101 9.1 9.2 Diagram of Pad Layout ............................................................................. I-101 Pad Coordinates ........................................................................................ I-102 S1C60N08 TECHNICAL HARDWARE EPSON I-iii CHAPTER 1: OVERVIEW CHAPTER 1 OVERVIEW The S1C60N08 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200C, ROM (4,096 words x 12 bits), RAM (832 words x 4 bits), LCD driver, serial interface, event counter with dial input function, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. 1.1 Configuration The S1C60N08 Series is configured as follows, depending on supply voltage and oscillation circuits. Table 1.1.1 Model configuration Model Supply voltage Oscillation circuit Evaluation tool S1C60N08 S1C60A08 3.0 V 3.0 V OSC1 only OSC1 and OSC3 (Single clock) (Twin clock) S1C60R08 S1C60L08 1.5 V OSC1 only (Single clock) - 1.2 Features Table 1.2.1 Features Model OSC1 oscillation circuit OSC3 oscillation circuit Instruction set Instruction execution time (differs depending on instruction) (CLK: CPU operation frequency) ROM capacity RAM capacity Input ports Output ports I/O ports Serial interface LCD driver Time base counter Watchdog timer Event counter Sound generator Analog comparator Battery low detection circuit (BLD) External interrupt Internal interrupt Supply voltage Current CLK= 32.768 kHz consumption (when halted) (Typ. value) CLK= 32.768 kHz (when executed) CLK= 500 kHz (when executed) Form when shipped S1C60N08 TECHNICAL HARDWARE S1C60N08/S1C60R08 S1C60L08 S1C60A08/S1C60R08 Crystal oscillation circuit 32.768 kHz (Typ.)/38.400 kHz (Typ.) - CR or ceramic oscillation circuit (selected by mask option) 500 kHz (Typ.) 108 types 153 sec, 214 sec, 366 sec (CLK = 32.768 kHz) 130 sec, 182 sec, 313 sec (CLK = 38.400 kHz) - 10 sec, 14 sec, 24 sec (CLK = 500 kHz) 4,096 words x 12 bits 832 words x 4 bits 9 bits (pull-down resistor can be added by mask option) 8 bits (BZ, BZ, FOUT and SIOF outputs are available by mask option) 8 bits (pull-down resistor is added during input data read-out) 1 port (8-bit clock synchronous system) 48 segments x 4, 3, or 2 commons (selected by mask option) V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in) Two types (timer and stopwatch) Built-in (can be disabled by mask option) Two 8-bit inputs (dial input evaluation or independent) Programmable in 8 sounds (8 frequencies) Digital envelope built-in (can be disabled by mask option) Inverted input x 1, non-inverted input x 1 Dual system (programmable in 8 values and a fixed value) 2.4 V, 2.2-2.55 V 1.2 V, 1.05-1.4 V 2.4 V, 2.2-2.55 V Input interrupt: 3 systems Time base counter interrupt: 2 systems Serial interface interrupt: 1 system 3.0 V (1.8-3.5 V) 1.5 V (0.9-1.7 V) 3.0 V (2.2-3.5 V) 1.0 A 1.0 A 1.1 A 2.2 A 2.2 A 3.0 A - - 50 A QFP5-100pin, QFP15-100pin or chip EPSON I-1 CHAPTER 1: OVERVIEW 1.3 Block Diagram ROM System Reset Control 4,096 words x 12 bits RESET Core CPU S1C6200C OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Input Port 832 words x 4 bits COM0-3 SEG0-47 VDD VL1 VL2 VL3 CA CB VS1 VSS AMPP AMPM LCD Driver 48 SEG x 4 COM K00-K03, K10 K20-K23 TEST I/O Port P00-P03 P10-P13 Output Port R00-R03 R10-R13 Power Controller Sound Generator SVD Serial I/F Event Counter Timer Comparator Stopwatch SIN SOUT SCLK Fig. 1.3.1 Block diagram I-2 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW 1.4 Pin Layout Diagram QFP5-100pin 80 51 81 50 INDEX 31 100 1 30 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin name SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name No. Pin name SEG0 76 P10 AMPP 77 R03 AMPM 78 R02 K23 79 R01 K22 80 R00 K21 81 R12 K20 82 R11 K10 83 R10 K03 84 R13 K02 85 VSS K01 86 RESET K00 87 OSC4 SIN 88 OSC3 SOUT 89 VS1 N.C. 90 OSC2 SCLK 91 OSC1 P03 92 VDD P02 93 VL3 P01 94 VL2 P00 95 VL1 N.C. 96 CA N.C. 97 CB P13 98 N.C. P12 99 COM3 P11 100 COM2 N.C. = No connection No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin name SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 N.C. SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name No. Pin name AMPP 76 R02 AMPM 77 R01 K23 78 R00 K22 79 R12 K21 80 R11 K20 81 R10 K10 82 R13 K03 83 VSS K02 84 RESET K01 85 OSC4 K00 86 OSC3 SIN 87 VS1 SOUT 88 OSC2 N.C. 89 OSC1 SCLK 90 VDD N.C. 91 VL3 P03 92 VL2 P02 93 VL1 P01 94 CA P00 95 CB P13 96 N.C. P12 97 COM3 P11 98 COM2 P10 99 COM1 R03 100 COM0 N.C. = No connection QFP15-100pin 75 51 50 76 INDEX 26 100 1 25 Fig. 1.4.1 Pin layout S1C60N08 TECHNICAL HARDWARE EPSON I-3 CHAPTER 1: OVERVIEW 1.5 Pin Description Table 1.5.1 Pin description Pin No. Pin name QFP5-100 QFP15-100 92 90 VDD VSS VS1 VL1 VL2 VL3 CA, CB OSC1 OSC2 OSC3 OSC4 K00-K03 K10 K20-K23 P00-P03 P10-P13 R00-R03 R10 R13 R11 R12 SIN SOUT SCLK AMPP AMPM SEG0-47 COM0-3 RESET TEST 85 89 95 94 93 96, 97 91 90 88 87 62-59 58 57-54 70-67 76-73 80-77 83 84 82 81 63 64 66 52 53 51-28, 26-3 I/O Function 83 (I) (I) Power supply pin (+) Power supply pin (-) 87 93 92 - - - Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. -1.05 V or 1/2*VL2) LCD drive voltage output pin (2*VL1 or approx. -2.10 V) 91 94, 95 - - LCD drive voltage output pin (3*VL1 or 3/2*VL2) 89 88 86 I O Crystal oscillation input pin Crystal oscillation output pin I CR or ceramic oscillation input pin * (N.C. for S1C60N08 and S1C60L08) 85 O I I I I/O I/O O O O O O I O I/O I I O CR or ceramic oscillation output pin * (N.C. for S1C60N08 and S1C60L08) Input port pin Input port pin Input port pin I/O port pin I/O port pin Output port pin Output port pin or BZ output pin * 61-58 57 56-53 70-67 74-71 78-75 81 82 80 79 62 63 65 51 52 50-39, 37-26, 24-1 2, 1, 100, 99 100-97 86 84 27 25 O I I Boost capacitor connecting pin Output port pin or BZ output pin * Output port pin or SIOF output pin * Output port pin or FOUT output pin * Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin Analog comparator non-inverted input pin Analog comparator inverted input pin LCD segment output pin or DC output pin * LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *) Initial reset input pin Input pin for test Can be selected by mask option 1.6 S1C60N08 Option List Multiple specifications are available in each option item as indicated in the Option List. Select the specifications that meet the target system. Be sure to record the specifications for unused ports too, according to the instructions provided. 1. DEVICE TYPE * DEVICE TYPE ........................................... * CLOCK TYPE (for Evaluation board) ... 1. S1C60N08 (Normal Type) 2. S1C60L08 (Low Power Type) 3. S1C60A08 (Twin Clock Type) 1. 32 kHz 2. 38 kHz 2. OSC3 SYSTEM CLOCK (only for S1C60A08) 1. CR I-4 EPSON 2. Ceramic S1C60N08 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW 3. MULTIPLE KEY ENTRY RESET * COMBINATION .................................. * TIME AUTHORIZE ............................. 1. Not Use 2. Use K00, K01 3. Use K00, K01, K02 4. Use K00, K01, K02, K03 1. Use 2. Not Use 4. WATCHDOG TIMER 1. Use 2. Not Use 5. INPUT INTERRUPT NOISE REJECTOR * K00-K03 ................................................ 1. Use * K10 ......................................................... 1. Use * K20-K23 ................................................ 1. Use 2. Not Use 2. Not Use 2. Not Use 6. INPUT PORT PULL DOWN RESISTOR * K00 * K01 * K02 * K03 * K10 * K20 * K21 * K22 * K23 ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 7. OUTPUT PORT SPECIFICATION (R00-R03) * R00 .......................................................... * R01 .......................................................... * R02 .......................................................... * R03 .......................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 8. R10 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................... 1. DC Output 2. Pch-OpenDrain 2. Buzzer Output 9. R11 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................... 1. DC Output 2. Pch-OpenDrain 2. SIO Flag 10.R12 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary 2. Pch-OpenDrain * OUTPUT TYPE .................................... 1. DC Output 2. FOUT 32768 or 38400 [Hz] 3. FOUT 16384 or 19200 [Hz] 4. FOUT 8192 or 9600 [Hz] 5. FOUT 4096 or 4800 [Hz] 6. FOUT 2048 or 2400 [Hz] 7. FOUT 1024 or 1200 [Hz] 8. FOUT 512 or 600 [Hz] 9. FOUT 256 or 300 [Hz] S1C60N08 TECHNICAL HARDWARE EPSON I-5 CHAPTER 1: OVERVIEW 11.R13 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary 2. Pch-OpenDrain * OUTPUT TYPE .................................... 1. DC Output 2. Buzzer Inverted Output (R13 Control) 3. Buzzer Inverted Output (R10 Control) 12. I/O PORT SPECIFICATION * P00 .......................................................... * P01 .......................................................... * P02 .......................................................... * P03 .......................................................... * P10 .......................................................... * P11 .......................................................... * P12 .......................................................... * P13 .......................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 13. SIN PULL DOWN RESISTOR 1. With Resistor 2. Gate Direct 1. Complementary 2. Pch-OpenDrain * PULL DOWN RESISTOR ................... 1. With Resistor * OUTPUT SPECIFICATION ............... 1. Complementary * LOGIC ................................................... 1. Positive 2. Gate Direct 2. Pch-OpenDrain 2. Negative 14. SOUT SPECIFICATION 15. SCLK SPECIFICATION 16. SIO DATA PERMUTATION 1. MSB First 2. LSB First 17. EVENT COUNTER NOISE REJECTOR 1. 2048 or 2400 [Hz] 2. 256 or 300 [Hz] 18. LCD SPECIFICATION * BIAS SELECTION S1C60N08 .............................................. S1C60L08 .............................................. S1C60A08 .............................................. 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/2 Bias, Regulator Not Used, LCD 3 V 3. 1/3 Bias, Regulator Not Used, LCD 4.5 V 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V * DUTY SELECTION ............................. 1. 1/4 Duty 2. 1/3 Duty 3. 1/2 Duty 19. SEGMENT MEMORY ADDRESS 1. 0 Page (040-06F) 2. 2 Page (240-26F) I-6 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (1) supplied to VDD through VSS, the S1C60N08 Series generates the necessary internal voltage with the regulated voltage circuit (<VS1> for oscillators, <VL1 or VL2> for LCD) and the voltage booster/reducer circuit (<VL2 and VL3, or VL1 and VL3> for LCD). 1 Supply voltage: S1C60N08/60A08 .. 3 V, S1C60L08 .. 1.5 V Figure 2.1.1 shows the power supply configuration of the S1C60N08. Figure 2.1.2 shows the power supply configuration of the S1C60A08 and S1C60L08. The voltage <VS1> for the internal circuit that is generated by the internal system voltage regulator. The S1C60N08 generates <VL2> with the LCD system voltage regulator and <VL1, VL3> with the voltage booster/reducer. The S1C60A08 and the S1C60L08 generate <VL1> with the voltage regulator and <VL2, VL3> with the voltage booster/reducer. Notes: * External loads cannot be driven by the output voltage of the voltage regulator and voltage booster/reducer. * See Chapter 7, "Electrical Characteristics", for voltage values. Internal circuit VDD C5 VS1 Internal system voltage regurator VS1 C3 VL2 LCD system voltage regurator VL2 C2 C4 VL1 VL3 CA CB Oscillation circuit OSC1, 2 LCD driver COM0-3 SEG0-47 VL2 External power supply C1 VL1 LCD system voltage booster/reducer VL3 VSS Fig. 2.1.1 Power supply configuration of S1C60N08 Internal circuit VDD C5 VS1 Internal system voltage regurator VS1 C3 VL1 LCD system voltage regurator VL1 C2 VL2 C4 VL3 Oscillation circuit OSC1, 2 OSC3, 4 (S1C60A08) VL1 External power supply CA C1 VL2 LCD system voltage booster/reducer VL3 LCD driver COM0-3 SEG0-47 CB VSS Fig. 2.1.2 Power supply configuration of S1C60A08 and S1C60L08 S1C60N08 TECHNICAL HARDWARE EPSON I-7 CHAPTER 2: POWER SUPPLY AND INITIAL RESET The LCD system voltage regulator can be disabled by mask option. In this case, external elements can be minimized because the external capacitors for the LCD system voltage regulator are not necessary. However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used. Figure 2.1.3 shows the external element configuration when the LCD system voltage regulator is not used. 4.5 V LCD panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA CB VSS C5 C2 C4 C1 3.0 V Note: VL2 is shorded to VSS inside the IC 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA CB VSS 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA CB VSS C5 C2 C3 C1 3.0 V C5 C2 C1 3.0 V Note: VL3 is shorded to VSS inside the IC 4.5 V LCD panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA CB VSS 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA CB VSS C5 C3 C4 C1 1.5 V C5 C4 C1 1.5 V Note: VL1 is shorded to VSS inside the IC Fig. 2.1.3 External elements when LCD system voltage regulator is not used Note: If there is any segment pad that is set to be DC type, the internal LCD voltage regulator cannot be chosen in all models. Or, if the internal LCD voltage regulator is chosen in any model, the segment pad cannot be set to be DC type. Table 2.1.1 LCD voltage regulator and DC output from SEG terminals LCD system voltage regulator DC output from SEG terminals Use Not available Not use Available I-8 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C60N08 Series circuits, initial reset must be executed. There are four ways of doing this. (1) Initial reset by the power on reset circuit (2) External initial reset by the RESET terminal (3) External initial reset by simultaneous high input to terminals K00-K03 (4) Initial reset by the watchdog timer Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 OSC1 oscillation circuit OSC2 Watchdog timer Power-on reset circuit K00 VSS K01 Time authorize circuit K02 Noise rejector Initial reset K03 RESET VSS Mask option Fig. 2.2.1 Configuration of initial reset circuit 2.2.1 Power-on reset circuit The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts oscillating. Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The following two initial reset method are recommended to generate the initial reset signal. 2.2.2 RESET terminal Initial reset can be executed externally by setting the reset terminal to the high level. This high level must be maintained for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a noise rejector. When the reset terminal goes low the CPU begins to operate. 2.2.3 Simultaneous high input to input ports (K00-K03) Another way of executing initial reset externally is to input a high signal simultaneously to the input ports (K00-K03) selected with the mask option. The specified input port terminals must be kept high for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a noise rejector. Table 2.2.3.1 shows the combinations of input ports (K00-K03) that can be selected with the mask option. Table 2.2.3.1 Input port combination Selection Combination A Not used B C D K00K01 K00K01K02 K00K01K02K03 When, for instance, mask option D (K00*K01*K02*K03) is selected, initial reset is executed when the signals input to the four ports K00-K03 are all high at the same time. S1C60N08 TECHNICAL HARDWARE EPSON I-9 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Further, the time authorize circuit can be selected with the mask option. The time authorize circuit performs initial reset, when the input time of the simultaneous high input is authorized and found to be the same or more than the defined time (1 to 2 sec). If you use this function, make sure that the specified ports do not go high at the same time during ordinary operation. 2.2.4 Watchdog timer If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial reset signal. See Section 4.2, "Resetting Watchdog Timer", for details. 2.2.5 Internal register at initial reset Initial reset initializes the CPU as shown in the table below. Table 2.2.5.1 Initial values CPU Core Name Symbol Bit size Program counter step PCS 8 Program counter page PCP 4 New page pointer NPP 4 Stack pointer SP 8 Index register X X 10 Index register Y Y 10 Register pointer RP 4 General-purpose register A A 4 General-purpose register B B 4 Interrupt flag I 1 Decimal flag D 1 Zero flag Z 1 Carry flag C 1 Initial value 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Bit size Initial value RAM 4 Undefined Display memory 4 Undefined Other peripheral circuits 4 See Section 4.1, "Memory Map". Name 2.3 Test Terminal (TEST) This terminal is used when the IC load is being detected. During ordinary operation be certain to connect this terminal to VSS. I-10 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N08 Series employs the core CPU S1C6200C for the CPU, so that register configuration, instructions and so forth are virtually identical to those in other family processors using the S1C6200/ 6200A/6200B/6200C. Refer to the "S1C6200/6200A Core CPU Manual" for details about the core CPU. Note the following points with regard to the S1C60N08 Series: (1) The SLEEP operation is not assumed, so the SLP instruction cannot be used. (2) Because the ROM capacity is 4,096 words, bank bits are unnecessary and PCB and NBP are not used. (3) RAM is set up to four pages, so only the two low-order bits are valid for the page portion (XP, YP) of the index register that specifies addresses. (The two high-order bits are ignored.) 3.2 ROM The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps, 12 bits each. The program area is 16 pages (0-15), each of 256 steps (00H-FFH). After initial reset, the program start address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H-0FH. Bank 0 Step 00H Page 0 Step 01H Program start address Page 1 Interrupt vector area Page 2 Page 3 Step 0FH Step 10H Program area Page 15 Step FFH 12 bits Fig. 3.2.1 ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 832 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H-00FH is the memory area pointed by the register pointer (RP). S1C60N08 TECHNICAL HARDWARE EPSON I-11 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N08 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N08 Series has an address space of 865 words (913 words when display memory is laid out in Page 2), of which 48 words are allocated to display memory and 33 words, to I/O memory. Figure 4.1.1 shows the overall memory map for the S1C60N08 Series, and Tables 4.1.1(a)-(c), the memory maps for the peripheral circuits (I/O space). Address Low 0 1 2 3 4 5 6 7 8 9 A B C D E F Page High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 4 5 6 7 RAM (256 words x 4 bits) 0 8 R/W 9 A B C D E F 0 1 2 3 4 5 6 7 RAM (256 words x 4 bits) 1 8 R/W 9 A B C D E F Address Low 0 Page High 0 1 2 3 4 5 6 2 7 8 9 A B C D E F 0 1 2 3 4 5 6 3 7 8 9 A B C D E F 1 2 3 4 5 6 7 8 9 A B C D E F RAM (64 words x 4 bits) R/W Unused area I/O mamory (see Table 4.1.1) RAM (256 words x 4 bits) R/W Fig. 4.1.1 Memory map Address Low 0 Page High 4 5 0 or 2 6 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (48 words x 4 bits) Page 0: R/W, Page 2: W only Fig. 4.1.2 Display memory map Notes: * The display memory area can be selected from between Page 0 (040H-06FH) and Page 2 (240H-26FH) by mask option. When Page 0 (040H-06FH) is selected, the display memory is assigned in the RAM area. So read/write operation is allowed. When Page 2 (240H-26FH) is selected, the display memory is assigned as a write-only memory. * Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. I-12 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(a) I/O memory map (2D0H, 2E0H-2ECH) Address Register Comment Name Init 1 1 0 Unused 0 3 - 2 - - 0 0 0 LOF 0 3 - 2 Unused - - 2D0H 0 3 - 2 Unused - - R R/W LOF 1 Normal All off LCD all off control Clock timer data (2 Hz) TM3 0 TM3 TM2 TM1 TM0 Clock timer data (4 Hz) TM2 0 2E0H Clock timer data (8 Hz) TM1 0 R Clock timer data (16 Hz) TM0 0 SWL3 MSB 0 SWL3 SWL2 SWL1 SWL0 SWL2 0 2E1H Stopwatch timer 1/100 sec data (BCD) SWL1 0 R SWL0 LSB 0 SWH3 MSB 0 SWH3 SWH2 SWH1 SWH0 SWH2 0 2E2H Stopwatch timer 1/10 sec data (BCD) SWH1 0 R SWH0 LSB 0 K03 - 2 High Low K03 K02 K01 K00 - 2 High K02 Low 2E3H Input port data (K00-K03) - 2 High K01 Low R - 2 High K00 Low KCP03 0 KCP03 KCP02 KCP01 KCP00 KCP02 0 2E4H Input comparison register (K00-K03) KCP01 0 R/W KCP00 0 EIK03 0 Enable Mask EIK03 EIK02 EIK01 EIK00 EIK02 0 Enable Mask 2E5H Interrupt mask register (K00-K03) EIK01 0 Enable Mask R/W EIK00 0 Enable Mask HLMOD Heavy load Normal Heavy load protection mode register 0 HLMOD BLD0 EISWIT1 EISWIT0 Low Normal Sub-BLD evaluation data BLD0 0 2E6H Enable Mask Interrupt mask register (stopwatch 1 Hz) EISWIT1 0 R/W R R/W Enable Mask Interrupt mask register (stopwatch 10 Hz) EISWIT0 0 SCTRG3 Trigger - Serial I/F clock trigger - SCTRG EIK10 KCP10 K10 EIK10 Enable Mask Interrupt mask register (K10) 0 2E7H KCP10 Input comparison register (K10) 0 W R/W R Low Input port data (K10) K10 - 2 High CSDC 0 Static Dynamic LCD drive switch CSDC ETI2 ETI8 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No R03 0 High Low Output port (R03) R03 R02 R01 R00 R02 0 High Low Output port (R02) 2EBH R01 0 High Low Output port (R01) R/W R00 0 High Low Output port (R00) R13 0 High/On Low/Off Output port (R13)/BZ output control R11 R13 R12 R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control SIOF 2ECH R11 0 High Low Output port (R11, LAMP) R/W SIOF 0 Run Stop Output port (SIOF) R/W R/W R R10 0 High/On Low/Off Output port (R10)/BZ output control 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 S1C60N08 TECHNICAL HARDWARE EPSON I-13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(b) I/O memory map (2EDH-2FAH) Address Register D3 D2 D1 P03 P02 P01 2EDH R/W TMRST SWRUN SWRST 2EEH W R/W W WDRST WD2 WD1 2EFH W R SD3 SD2 SD1 2F0H R/W SD7 SD6 SD5 2F1H R/W SCS1 SCS0 SE2 2F2H R/W 0 0 IK2 2F3H R K23 K22 K21 2F4H R EIK23 EIK22 EIK21 2F5H R/W BZFQ2 BZFQ1 BZFQ0 2F6H R/W ENVON ENVRT AMPDT 2F7H R/W EV03 R EV02 EV01 2F8H R EV07 EV06 EV05 2F9H R EV13 EV12 EV11 2FAH R 1 Initial value at initial reset 2 Not set in the circuit I-14 Comment 1 0 Name Init 1 P03 - 2 High Low P00 - 2 High I/O port data (P00-P03) P02 Low - 2 High Output latch is reset at initial reset P01 Low - 2 High P00 Low TMRST3 Reset Reset Clock timer reset - IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop SWRST3 Reset Reset Stopwatch timer reset - R/W IOC0 0 Output Input I/O control register 0 (P00-P03) WDRST3 Reset Reset Watchdog timer reset - WD0 WD2 Timer data (watchdog timer) 1/4 Hz 0 WD1 Timer data (watchdog timer) 1/2 Hz 0 WD0 Timer data (watchdog timer) 1 Hz 0 SD3 x 5 SD0 x 5 SD2 Serial I/F data register (low-order 4 bits) x 5 SD1 x 5 SD0 SD7 x 5 SD4 x 5 SD6 Serial I/F data register (high-order 4 bits) x 5 SD5 x 5 SD4 [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 SE2 Serial I/F clock edge selection 0 EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 - 2 Unused - - ISIO 0 3 - 2 Unused - - IK2 4 0 Interrupt factor flag (K20-K23) Yes No ISIO 4 0 Interrupt factor flag (serial I/F) Yes No K23 - 2 High Low K20 - 2 High K22 Low Input port data (K20-K23) - 2 High K21 Low - 2 High K20 Low EIK23 0 Enable Mask EIK20 EIK22 0 Enable Mask Interrupt mask register (K20-K23) EIK21 0 Enable Mask EIK20 0 Enable Mask 1 2 3 [BZFQ2-0] 0 BZFQ2 0 Buzzer ENVRST Frequency fOSC1/8 fOSC1/10 fOSC1/12 fOSC1/14 BZFQ1 0 frequency 5 6 7 [BZFQ2-0] 4 BZFQ0 0 selection Frequency fOSC1/16 fOSC1/20 fOSC1/24 fOSC1/28 W ENVRST3 Reset Reset - Envelope reset ENVON Envelope On/Off 0 On Off AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register AMPDT 1 +>+ < - Analog comparator data R/W AMPON Analog comparator On/Off 0 On Off EV03 0 EV00 EV02 0 Event counter 0 (low-order 4 bits) EV01 0 EV00 0 EV07 0 EV04 EV06 0 Event counter 0 (high-order 4 bits) EV05 0 EV04 0 EV13 0 EV10 EV12 0 Event counter 1 (low-order 4 bits) EV11 0 EV10 0 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(c) I/O memory map (2FBH-2FFH) Address Register Comment Name Init 1 1 0 EV17 0 EV17 EV16 EV15 EV14 EV16 0 2FBH Event counter 1 (high-order 4 bits) EV15 0 R EV14 0 EVSEL 0 Separate Phase Event counter mode selection EVSEL ENRUN EV1RST EV0RST EVRUN 0 Run Stop Event counter Run/Stop 2FCH EV1RST3 Reset Reset Event counter 1 reset - R/W W EV0RST3 Reset Reset Event counter 0 reset - P13 - 2 High Low P13 P12 P11 P10 - 2 High I/O port data (P10-P13) P12 Low 2FDH - 2 High Output latch is reset at initial reset P11 Low R/W - 2 High P10 Low PRSM 0 38 kHz 32 kHz OSC1 prescaler selection PRSM CLKCHG OSCC IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch 2FEH OSCC OSC3 oscillation On/Off 0 On Off R/W IOC1 0 Output Input I/O control register (P10-P13) BLS 0 On Off BLD On/Off BLS BLC2 BLC1 BLC0 BLD1 0 Low Normal BLD evaluation data BLD1 Evaluation voltage setting register 2FFH BLC2 x 5 [BLC2-0] 0 1 2 3 4 5 6 7 W 5 BLC1 x R/W S1C60N08/60A08 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 (V) R S1C60L08 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 (V) x 5 BLC0 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 S1C60N08 TECHNICAL HARDWARE EPSON I-15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) 4.2 Resetting Watchdog Timer 4.2.1 Configuration of watchdog timer The S1C60N08 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 or 4 seconds, the initial reset signal is output automatically for the CPU. Figure 4.2.1.1 is the block diagram of the watchdog timer. Clock timer TM0-TM3 OSC1 demultiplier (256 Hz) 2 Hz Watchdog timer WD0-WD2 Initial reset signal Watchdog timer reset signal Fig. 4.2.1.1 Watchdog timer block diagram The watchdog timer, configured of a three-bit binary counter (WD0-WD2), generates the initial reset signal internally by overflow of the MSB. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the halt mode. If the halt status continues for 3 or 4 seconds, the initial reset signal restarts operation. 4.2.2 Mask option You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen, there is no need to reset the watchdog timer. 4.2.3 Control of watchdog timer Table 4.2.3.1 lists the watchdog timer's control bits and their addresses. Table 4.2.3.1 Control bits of watchdog timer Address Register D3 D2 D1 WDRST WD2 WD1 2EFH W 1 Initial value at initial reset 2 Not set in the circuit R Comment 1 0 Name Init 1 3 WDRST Watchdog timer reset Reset Reset - WD0 WD2 Timer data (watchdog timer) 1/4 Hz 0 WD1 Timer data (watchdog timer) 1/2 Hz 0 WD0 Timer data (watchdog timer) 1 Hz 0 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 WDRST: Watchdog timer reset (2EFH*D3) This is the bit for resetting the watchdog timer. When "1" is written : Watchdog timer is reset When "0" is written : No operation Read-out : Always "0" When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after this. When "0" is written to WDRST, no operation results. This bit is dedicated for writing, and is always "0" for read-out. 4.2.4 Programming note When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0-WD2) cannot be used for timer applications. I-16 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3 Oscillation Circuit and Prescaler 4.3.1 Configuration of oscillation circuit and prescaler The S1C60N08 and S1C60L08 have one oscillation circuit (OSC1), and the S1C60A08 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock the CPU and peripheral circuits. OSC3 is either a CR or ceramic oscillation circuit. When processing with the S1C60A08 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3. Figure 4.3.1.1 is the block diagram of this oscillation system. Prescaler selection signal OSC1 oscillation circuit Prescaler 2 Selector To peripheral circuits (256 Hz) Prescaler 1 To peripheral circuits Clock switch OSC3 oscillation circuit To CPU (and serial interface) CPU clock selection signal Oscillation circuit control signal Fig. 4.3.1.1 Oscillation system As Figure 4.3.1.1 indicates, two prescalers (demultiplier stage) are connected to the oscillation circuit. Prescaler 1 is for 32.768 kHz and prescaler 2 is for 38.4 kHz. These can be selected through the software to suit the crystal oscillator. This selection invokes the basic signal (256 Hz) for running the clock timer, stopwatch timer, and so forth. Also for S1C60A08, selection of either OSC1 or OSC3 for the CPU's operating clock can be made through the software. 4.3.2 OSC1 oscillation circuit The S1C60N08 Series has a built-in crystal oscillation circuit (OSC1 oscillation circuit). As an external element, the OSC1 oscillation circuit generates the operating clock for the CPU and peripheral circuits by connecting the crystal oscillator (Typ. 32.768 kHz) and trimmer capacitor (5-25 pF). Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit. VDD RFX CGX RDX OSC1 X'tal OSC2 To CPU and peripheral circuits CDX VDD S1C60N08 Series Fig. 4.3.2.1 OSC1 oscillation circuit As Figure 4.3.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) between terminals OSC1 and OSC2 to the trimmer capacitor (CGX) between terminals OSC1 and VDD. Also, the crystal oscillator can be connected to the 38.4 kHz oscillator in addition to the 32.768 kHz oscillator. S1C60N08 TECHNICAL HARDWARE EPSON I-17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3.3 OSC3 oscillation circuit In the S1C60N08 Series, the S1C60A08 has twin clock specification. The mask option enables selection of either the CR or ceramic oscillation circuit (OSC3 oscillation circuit) as the CPU's subclock source. Because the oscillation circuit itself is built-in, it provides the resistance as an external element when CR oscillation is selected, but when ceramic oscillation is selected both the ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit. CCR OSC3 RCR To CPU (and serial interface) OSC4 Oscillation circuit control signal S1C60A08 CR oscillation circuit Ceramic CDC OSC4 RDC OSC3 RFC VDD CGC To CPU (and serial interface) Oscillation circuit control signal S1C60A08 Ceramic oscillation circuit Fig. 4.3.3.1 OSC3 oscillation circuit As indicated in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor (RCR) between terminals OSC3 and OSC4 when CR oscillation is selected. When 82 k is used for RCR, the oscillation frequency is about 410 kHz. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Typ. 500 kHz) between terminals OSC3 and OSC4 to the two capacitors (CGC and CDC) located between terminals OSC3 and OSC4 and VDD. For both CGC and CDC, connect capacitors that are about 100 pF. To lower current consumption of the OSC3 oscillation circuit, oscillation can be stopped through the software. For the S1C60N08 and S1C60L08 (single clock specification), do not connect anything to terminals OSC3 and OSC4. I-18 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3.4 Control of oscillation circuit and prescaler Table 4.3.4.1 lists the control bits and their addresses for the oscillation circuit. Table 4.3.4.1 Control bits of oscillation circuit and prescaler Address Register D3 D2 D1 PRSM CLKCHG OSCC 2FEH R/W 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 PRSM 0 38 kHz 32 kHz OSC1 prescaler selection IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC OSC3 oscillation On/Off 0 On Off IOC1 0 Output Input I/O control register (P10-P13) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 OSCC: OSC3 oscillation control (2FEH*D1) Controls oscillation ON/OFF for the OSC3 oscillation circuit. (S1C60A08 only.) When "1" is written : The OSC3 oscillation ON When "0" is written : The OSC3 oscillation OFF Read-out : Valid When it is necessary to operate the CPU of the S1C60A08 at high speed, set OSCC to "1". At other times, set it to "0" to reduce current consumption. For S1C60N08 and S1C60L08, keep OSCC set to "0". At initial reset, OSCC is set to "0". CLKCHG: CPU clock switch (2FEH*D2) The CPU's operation clock is selected with this register. (S1C60A08 only.) When "1" is written : OSC3 clock is selected When "0" is written : OSC1 clock is selected Read-out : Valid When the S1C60A08's CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". This register cannot be controlled for S1C60N08 and S1C60L08, so that OSC1 is selected no matter what the set value. At initial reset, CLKCHG is set to "0". PRSM: OSC1 prescaler selection (2FEH*D3) Selects the prescaler for the crystal oscillator of the OSC1 oscillation circuit. When "1" is written : 38.4 kHz When "0" is written : 32.768 kHz Read-out : Valid Operation of the clock timer and stopwatch timer can be mode accurate by selecting this register. When the set value for this register does not suit the crystal oscillator used, the operation cycles of the previously mentioned peripheral circuitry is multiplied as shown below. fOSC1 = 32.768 kHz and PRSM = "1": T' 1.172T fOSC1 = 38.4 kHz and PRSM = "0": T' 0.853T At initial reset, PRSM is set to "0". S1C60N08 TECHNICAL HARDWARE EPSON I-19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3.5 Programming notes (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. (3) To operate the clock timer and stopwatch timer accurately, select the prescaler of the OSC1 to match the crystal oscillator used. I-20 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00-K03, K10, K20-K23) 4.4.1 Configuration of input ports The S1C60N08 Series has nine bits (4 bits x 2 + 1 bit) of general-purpose input ports. Each of the input port terminals (K00-K03, K10, K20-K23) provides internal pull-down resistor. Pull-down resistor can be selected for each bit with the mask option. Figure 4.4.1.1 shows the configuration of input port. VDD Data bus Interrupt request K Mask option Address VSS Fig. 4.4.1.1 Configuration of input port Selection of "With pull-down resistor" with the mask option suits input from the push switch, key matrix, and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing with other LSIs. Further, The input port terminal K02 and K03 are used as the input terminals for the event counter. (See Section 4.12, "Event Counter", for details.) 4.4.2 Input comparison registers and interrupt function All nine bits of the input ports (K00-K03, K10, K20-K23) provide the interrupt function for the five bits, K00-K03 and K10. The conditions for issuing an interrupt can be set by the software for the five bits, K00- K03 and K10. Further, whether to mask the interrupt function can be selected individually for all nine bits by the software. Figure 4.4.2.1 shows the configuration of K00-K03 and K10. Figure 4.4.2.3 shows the configuration of K20-K23. K Data bus Address Input comparison register (KCP) Address Interrupt mask register (EIK) One for each terminal series Noise rejector Interrupt factor flag (IK) Mask option (K00-K03, K10) Interrupt request Address Address Fig. 4.4.2.1 Input interrupt circuit configuration (K00-K03, K10) S1C60N08 TECHNICAL HARDWARE EPSON I-21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) The input interrupt timing for K00-K03 and K10 depends on the value set for the input comparison registers (KCP00-KCP03 and KCP10). Interrupt can be selected to occur at the rising or falling edge of the input. The interrupt mask registers (EIK00-EIK03, EIK10) enables the interrupt mask to be selected individually for K00-K03 and K10. However, whereas the interrupt function is enabled inside K00-K03, the interrupt occurs when the contents change from matching those of the input comparison register to non-matching contents. Interrupt for K10 can be generated by setting the same conditions individually. When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1". Figure 4.4.2.2 shows an example of an interrupt for K00-K03. Interrupt mask register EIK03 1 EIK02 1 EIK01 1 EIK00 0 Input comparison register KCP03 KCP02 KCP01 KCP00 1 0 1 0 With the above setting, the interrupt of K00-K03 is generated under the following condition: Input port (1) K03 1 K02 0 K01 1 K00 0 (2) K03 1 K02 0 K01 1 K00 1 (3) K03 0 K02 0 K01 1 K00 1 (4) K03 0 K02 1 K01 1 K00 1 (Initial value) Interrupt generation Because K00 interrupt is masked, interrupt will be generated when no matching occurs between the contents of the 3 bits K01-K03 and the 3 bits input comparison register KCP01-KCP03. Fig. 4.4.2.2 Example of interrupt of K00-K03 K00 is masked by the interrupt mask register (EIK00), so that an interrupt does not occur at (2). At (3), K03 changes to "0"; the data of the terminal that is interrupt enabled no longer matches the data of the input comparison register, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the input comparison register from matching to nonmatching. Hence, in (4), when the nonmatching status changes to another nonmatching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation. I-22 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K Noise rejector Data bus Address Interrupt mask register (EIK) Interrupt factor flag (IK2) Mask option (K20-K23) Address Interrupt request Address Fig. 4.4.2.3 Input interrupt circuit configuration (K20-K23) There is no input comparison register for K20-K23, and interrupt is fixed to occur at th rising edge of input. The interrupt mask can be selected for each of the four terminals with the interrupt mask register (EIK20-EIK23). When all the enabled terminals are "0", interrupt occurs when one or more of the ports changed to "1". When an interrupt occurs, the interrupt factor flag (IK2) is set to "1". Figure 4.4.2.4 shows an example of an interrupt being generated for K20-K23. Interrupt mask register EIK23 0 EIK22 1 EIK21 1 EIK20 1 With the above setting, the interrupt of K20-K23 is generated under the following condition: Input port (1) K23 0 K22 0 K21 0 K20 0 (2) K23 1 K22 0 K21 0 K20 0 (3) K23 1 K22 0 K21 1 K20 0 (4) K23 1 K22 0 K21 1 K20 1 (Initial value) Interrupt generation Because K23 interrupt is masked, interrupt will be generated when one or more terminals among the 3 bits K20-K22 become "1" from a state where all terminals were "0". Fig. 4.4.2.4 Example of interrupt of K20-K23 The mask register (EIK23) masks the interrupt of K23, so an interrupt does not occur at (2). At (3), K21 becomes "1", so that an interrupt occurs if the interrupt enabled terminals were all "0" and at least one terminal then changes to "1". At (4), the conditions for interrupt are not established, so an interrupt does not occur. Futher, terminals that have been masked for interrupt do not affect the conditions for interrupt generation. S1C60N08 TECHNICAL HARDWARE EPSON I-23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.3 Mask option The contents that can be selected with the input port mask option are as follows: (1) Internal pull-down resistor can be selected for each of the nine bits of the input ports (K00-K03, K10, K20-K23). When you have selected "Gate direct", take care that the floating status does not occur for the input. Select "With pull-down resistor" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejector for preventing interrupt occurring through noise. The mask option enables selection of whether to use the noise rejector for each separate terminal series. When "Use" is selected, a maximum delay of 1 msec occurs from the time interrupt condition is established until the interrupt factor flag (IK) is set to "1". 4.4.4 Control of input ports Table 4.4.4.1 lists the input ports control bits and their addresses. Table 4.4.4.1 Input port control bits Address Register D3 D2 D1 D0 K03 K02 K01 K00 2E3H R KCP03 KCP02 KCP01 KCP00 2E4H R/W EIK03 EIK02 EIK01 EIK00 2E5H R/W SCTRG EIK10 KCP10 K10 2E7H W IK1 R/W IK0 R SWIT1 SWIT0 IK2 ISIO K21 K20 EIK21 EIK20 2EAH R 0 0 2F3H R K23 K22 2F4H R EIK23 EIK22 2F5H R/W 1 Initial value at initial reset 2 Not set in the circuit I-24 Comment 1 0 Name Init 1 K03 - 2 High Low - 2 High K02 Low Input port data (K00-K03) - 2 High K01 Low - 2 High K00 Low KCP03 0 KCP02 0 Input comparison register (K00-K03) KCP01 0 KCP00 0 EIK03 0 Enable Mask EIK02 0 Enable Mask Interrupt mask register (K00-K03) EIK01 0 Enable Mask EIK00 0 Enable Mask SCTRG3 Trigger - Serial I/F clock trigger - EIK10 Enable Mask Interrupt mask register (K10) 0 KCP10 Input comparison register (K10) 0 Low Input port data (K10) K10 - 2 High IK1 4 0 Interrupt factor flag (K10) Yes No IK0 4 0 Interrupt factor flag (K00-K03) Yes No SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No 0 3 - 2 Unused - - 0 3 - 2 Unused - - IK2 4 0 Interrupt factor flag (K20-K23) Yes No ISIO 4 0 Interrupt factor flag (serial I/F) Yes No K23 - 2 High Low - 2 High K22 Low Input port data (K20-K23) - 2 High K21 Low - 2 High K20 Low EIK23 0 Enable Mask EIK22 0 Enable Mask Interrupt mask register (K20-K23) EIK21 0 Enable Mask EIK20 0 Enable Mask 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K00-K03, K10, K20-K23: Input port data (2E3H, 2E7H*D0, 2F4H) Input data of the input port terminals can be read out with these registers. When "1" is read out : High level When "0" is read out : Low level Writing : Invalid The read-out is "1" when the terminal voltage of the nine bits of the input ports (K00-K03, K10, K20-K23) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are dedicated for read-out, so writing cannot be done. KCP00-KCP03, KCP10: Input comparison registers (2E4H, 2E7H*D1) Interrupt conditions for terminals K00-K03 and K10 can be set with these registers. When "1" is written : Falling edge When "0" is written : Rising edge Read-out : Valid Of the nine bits of the input ports, the interrupt conditions can be set for the rising or falling edge of input for each of the five bits (K00-K03 and K10), through the input comparison registers (KCP00-KCP03 and KCP10). At initial reset, these registers are set to "0". EIK00-EIK03, EIK10, EIK20-EIK23: Interrupt mask registers (2E5H, 2E7H*D2, 2F5H) Masking the interrupt of the input port terminals can be selected with these registers. When "1" is written : Enable When "0" is written : Mask Read-out : Valid With these registers, masking of the input port bits can be selected for each of the nine bits. Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are all set to "0". IK0, IK1, IK2: Interrupt factor flags (2EAH*D2 and D3, 2F3H*D1) These flags indicate the occurrence of input interrupt. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid The interrupt factor flags IK0, IK1 and IK2 are associated with K00-K03, K10 and K20-K23, respectively. From the status of these flags, the software can decide whether an input interrupt has occurred. These flags are reset when the software reads them. Read-out can be done only in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". S1C60N08 TECHNICAL HARDWARE EPSON I-25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.5 Programming notes (1) When input ports are changed from high to low by pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 msec. (2) When "Use" is selected with the noise rejector mask option, a maximum delay of 1 msec occurs from time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be set after read-out, so that it will not be reset. (3) Input interrupt programing related precautions Port K input Active status Active status Input comparison register Falling edge interrupt Rising edge interrupt Mask register Factor flag set Not set Factor flag set When the content of the mask register is rewritten while the port K input is in the active status, the input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. Fig. 4.4.5.1 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 4.4.5.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 4.4.5.1. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the input comparison register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the input comparison register in the mask register = "0" status. (4) Read out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI status (interrupt flag = "1") will cause malfunction. (5) Write the interrupt mask register (EIK) only in the DI status (interrupt flag = "0"). Writing during EI status (interrupt flag = "1") will cause malfunction. I-26 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00-R03, R10-R13) 4.5.1 Configuration of output ports The S1C60N08 Series has eight bits (4 bits x 2) of general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Further, the mask option enables the output ports R10-R13 to be used as special output ports. Figure 4.5.1.1 shows the configuration of the output ports. Data bus VDD Register Rxx Complementary Pch open drain Address VSS Mask option Fig. 4.5.1.1 Configuration of output ports 4.5.2 Mask option The mask option enables the following output port selection. (1) Output specifications of output ports Output specifications for the output ports (R00-R03, R10-R13) enable selection of either complementary output or Pch open drain output for each of the eight bits. However, even when Pch open drain output is selected, voltage exceeding source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for the output ports R10-R13 as shown in Table 4.5.2.1. Figure 4.5.2.1 shows the structure of the output ports R10-R13. Table 4.5.2.1 Special output Output port Special output R10 R13 R11 R12 BZ output BZ output (selectable only when R10 is used as BZ output) SIOF output FOUT output S1C60N08 TECHNICAL HARDWARE EPSON I-27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZ R10 Register R10 R13 Data bus Register R13 SIOF R11 Register R11 FOUT R12 Register R12 Address 2ECH Mask option Fig. 4.5.2.1 Structure of output port R10-R13 BZ, BZ (R10, R13) BZ and BZ are the buzzer signal output for driving the piezoelectric buzzer. The buzzer signal is generated by demultiplicaion of fOSC1. Also, a digital envelope can be added to the buzzer signal. See Section 4.11, "Sound Generator", for details. Notes: * When the BZ and BZ output signals are turned ON or OFF, a hazard can result. * When DC output is set for the output port R10, the output port R13 cannot be set for BZ output. Figure 4.5.2.2 shows the output waveform for BZ and BZ. R00(R03) register "0" "1" "0" BZ output (R10 terminal) BZ output (R13 terminal) Fig. 4.5.2.2 Output waveform of BZ and BZ SIOF (R11) When the output port R11 is set for SIOF output, it outputs the signal indicating the running status (RUN/STOP) of the serial interface. See Section 4.7, "Serial Interface", for details. FOUT (R12) When the output port R12 is set for FOUT output, it outputs the clock of fOSC1 or the demultiplied fOSC1. The clock frequency is selectable with the mask options, from the frequencies listed in Table 4.5.2.2. Table 4.5.2.2 FOUT clock frequency Setting value fOSC1 / 1 fOSC1 / 2 fOSC1 / 4 fOSC1 / 8 fOSC1 / 16 fOSC1 / 32 fOSC1 / 64 fOSC1 / 128 Clock frequency (Hz) fOSC1 = 32.768 kHz fOSC1 = 38.400 kHz 32,768 38,400 16,384 19,200 8,192 9,600 4,096 4,800 2,048 2,400 1,024 1,200 512 600 256 300 Note: A hazard may occur when the FOUT signal is turned ON or OFF. I-28 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.3 Control of output ports Table 4.5.3.1 lists the output ports' control bits and their addresses. Table 4.5.3.1 Control bits of output ports Address Register D3 D2 D1 D0 R03 R02 R01 R00 2EBH R/W R11 R13 R12 2ECH SIOF R10 R/W R/W R R/W Name R03 R02 R01 R00 R13 R12 R11 SIOF R10 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Init 1 0 High Low Output port (R03) 0 High Low Output port (R02) 0 High Low Output port (R01) 0 High Low Output port (R00) 0 High/On Low/Off Output port (R13)/BZ output control 0 High/On Low/Off Output port (R12)/FOUT output control 0 High Low Output port (R11, LAMP) 0 Run Stop Output port (SIOF) 0 High/On Low/Off Output port (R10)/BZ output control 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read R00-R03, R10-R13 (when DC output): Output port data (2EBH, 2ECH) Sets the output data for the output ports. When "1" is written : High output When "0" is written : Low output Read-out : Valid The output port terminals output the data written in the corresponding registers (R00-R03, R10-R13) without changing it. When "1" is written in the register, the output port terminal goes high (VDD), and when "0" is written, the output port terminal goes low (VSS). At initial reset, all registers are set to "0". R10, R13 (when BZ and BZ output is selected): Buzzer output control (2ECH*D0 and D3) These bits control the output of the buzzer signals (BZ, BZ). When "1" is written : Buzzer signal is output When "0" is written : Low level (DC) is output Read-out : Valid BZ is output from terminal R13. With the mask option, selection can be made perform this output control by R13, or to perform output control simultaneously with BZ by R10. * When R13 controls BZ output BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to R10, and BZ output is controlled by writing data to R13. * When R10 controls BZ output BZ output and BZ output can be controlled simultaneously by writing data to R10 only. For this case, R13 can be used as a one-bit general register having both read and write functions, and data of this register exerts no affect on BZ output (output from the R13 pin). At initial reset, registers R10 and R13 are set to "0". R11 (when SIOF output is selected): Serial interface status (2ECH*D1) Indicates the running status of the serial interface. When "1" is read out : RUN When "0" is read out : STOP Writing : Valid See Section 4.7, "Serial Interface", for details of SIOF. This bit is exclusively for reading out, so data cannot be written to it. S1C60N08 TECHNICAL HARDWARE EPSON I-29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R12 (when FOUT is selected): FOUT output control (2ECH*D2) Controls the FOUT (clock) output. When "1" is written : Clock output When "0" is written : Low level (DC) output Read-out : Valid FOUT output can be controlled by writing data to R12. At initial reset, this register is set to "0". 4.5.4 Programming note When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes. I-30 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00-P03, P10-P13) 4.6.1 Configuration of I/O ports Data bus The S1C60N08 Series has eight bits (4 bits x 2) of general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O ports. The four bits of each of the I/O ports P00-P03 and P10-P13 can be set to either input mode or output mode. Modes can be set by writing data to the I/O control register. Input control Register P Address Address I/O control register VSS Fig. 4.6.1.1 Configuration of I/O port 4.6.2 I/O control register and I/O mode Input or output mode can be set for the four bits of I/O port P00-P03 and I/O port P10-P13 by writing data into the corresponding I/O control register IOC0 and IOC1. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, the input line is pulled down when input data is read. The output mode is set when "1" is written to the I/O control register. When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0". At initial reset, the I/O control registers are set to "0", and the I/O port enters the input mode. 4.6.3 Mask option The output specification during output mode (IOC = "1") of these I/O ports can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of each port. However, when Pch open drain output has been selected, voltage in excess of the power voltage must not be applied to the port. S1C60N08 TECHNICAL HARDWARE EPSON I-31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.4 Control of I/O ports Table 4.6.4.1 lists the I/O ports' control bits and their addresses. Table 4.6.4.1 I/O port control bits Address Register D3 D2 D1 P03 P02 P01 2EDH R/W TMRST SWRUN SWRST 2EEH W R/W W P13 P12 P11 2FDH R/W PRSM CLKCHG OSCC 2FEH R/W 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 P03 Low - 2 High P00 - 2 High I/O port data (P00-P03) P02 Low - 2 High Output latch is reset at initial reset P01 Low - 2 High P00 Low TMRST3 Reset Reset Clock timer reset - IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop SWRST3 Reset Reset Stopwatch timer reset - R/W IOC0 0 Output Input I/O control register 0 (P00-P03) P13 - 2 High Low P10 - 2 High I/O port data (P10-P13) P12 Low - 2 High Output latch is reset at initial reset P11 Low - 2 High P10 Low PRSM 0 38 kHz 32 kHz OSC1 prescaler selection IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC OSC3 oscillation On/Off 0 On Off IOC1 0 Output Input I/O control register (P10-P13) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 P00-P03, P10-P13: I/O port data (2EDH, 2FDH) I/O port data can be read and output data can be set through these ports. When writing data When "1" is written : High level When "0" is written : Low level When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can be written also in the input mode. When reading data out When "1" is read out : High level When "0" is read out : Low level The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port terminal can be read out; in the output mode the output voltage level can be read. When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal voltage is low (VSS) the data is "0". Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is pulled down. Notes: * When the I/O port is set to the output mode and a low-impedance load is connected to the port terminal, the data written to the register may differ from the data read out. * When the I/O port is set to the input mode and a low-level voltage (VSS) is input, erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. When the input data is being read out, the time that the input line is pulled down is equivalent to 1.5 cycles of the CPU system clock. However, the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be fulfilled, some measure must be devised such as arranging pull-down resistance externally, or performing multiple read-outs. I-32 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) IOC0, IOC1: I/O control registers (2EEH*D0, 2FEH*D0) The input and output modes of the I/O ports can be set with these registers. When "1" is written : Output mode When "0" is written : Input mode Read-out : Valid The input and output modes of the I/O ports are set in units of four bits. IOC0 sets the mode for P00-P03, and IOC1 sets the mode for P10-P13. Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and writing "0" induces the input mode. At initial reset, these two registers are set to "0", so the I/O ports are in the input mode. 4.6.5 Programming notes (1) When input data are changed from high to low by built-in pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 sec. (2) When the I/O port is set to the output mode and the data register has been read, the terminal data instead of the register data can be read out. Because of this, if a low-impedance load is connected and read-out performed, the value of the register and the read-out result may differ. S1C60N08 TECHNICAL HARDWARE EPSON I-33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7 Serial Interface (SIN, SOUT, SCLK) 4.7.1 Configuration of serial interface The S1C60N08 Series has a synchronous clock type 8 bits serial interface built-in. The configuration of the serial interface is shown in Figure 4.7.1.1. The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal. The synchronous clock for serial data input/output may be set by selecting by software any one of 3 types of master mode (internal clock mode: when the S1C60N08 Series is to be the master for serial input/output) and a type of slave mode (external clock mode: when the S1C60N08 Series is to be the slave for serial input/output). Also, when the serial interface is used at slave mode, SIOF signal which indicates whether or not the serial interface is available to transmit or receive can be output to output port R11 by mask option. SD0-SD7 Shift register (8 bits) SIN SCS0 Output latch SOUT SE2 SCS1 Serial clock counter Serial clock selector SCLK Serial clock generator Serial I/F interrupt control circuit System clock EISIO Serial I/F activating circuit SCTRG ISIO SIOF Fig. 4.7.1.1 Configuration of serial interface 4.7.2 Master mode and slave mode of serial interface The serial interface of the S1C60N08 Series has two types of operation mode: master mode and slave mode. In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates this internal clock at the SCLK terminal and controls the external (slave side) serial device. In the slave mode, the synchronous clock output from the external (master side) serial device is input from the SCLK terminal and uses it as the synchronous clock to the built-in shift register. The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address 2F2H*D2, D3). When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in Table 4.7.2.1. Table 4.7.2.1 Synchronous clock selection SCS1 0 0 1 1 SCS0 0 1 0 1 Mode Master mode Slave mode Synchronous clock CLK CLK/2 CLK/4 External clock CLK: CPU system clock At initial reset, the slave mode (external clock mode) is selected. Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as follows: * At master mode, after output of 8 clocks from the SCLK terminal, clock output is automatically suspended and SCLK terminal is fixed at low level. * At slave mode, after input of 8 clocks to the SCLK terminal, subsequent clock inputs are masked. I-34 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Note: When using the serial interface in the master mode, CPU system clock is used as the synchronous clock. Accordingly, when the serial interface is operating, system clock switching (fOSC1 fOSC3) should not be performed. A sample basic serial input/output portion connection is shown in Figure 4.7.2.1. SCLK External serial device CLK SOUT SOUT S1C60N08 SIN SOUT SOUT SIN SIN Input terminal SCLK External serial device CLK S1C60N08 SIN R11(SIOF) READY Master mode Input terminal Slave mode Fig. 4.7.2.1 Sample basic connection 4.7.3 Data input/output and interrupt function The serial interface can input/output data via the internal 8 bits shift register. The shift register operates by synchronizing with either the synchronous clock output from SCLK terminal (master mode), or the synchronous clock input to SCLK (slave mode). The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates interrupt. The serial data input/output procedure data is explained below: (1) Serial data output procedure and interrupt The serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to 4 bits registers SD0-SD3 (address 2F0H) and SD4-SD7 (address 2F1H) individually and writing "1" to SCTRG bit (address 2E7H*D3), it synchronizes with the synchronous clock and serial data is output at the SOUT terminal. The synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal. The serial output of the SOUT termina changes with the rising edge of the clock that is input or output from the SCLK terminal. The serial data to the built-in shift register is shifted with the rising edge of the SCLK signal when SE2 bit (address 2F2H*D1) is "1" and is shifted with the falling edge of the SCLK signal when SE2 bit (address 2F2H*D1) is "0". When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO (address 2F3H*D0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO (address 2F2H*D0). (2) Serial data input procedure and interrupt The serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN terminal, synchronizes with the synchronous clock, and is sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal. The serial data to the built-in shift register is read with the rising edge of the SCLK signal when SE2 bit is "1" and is read with the falling edge of the SCLK signal when SE2 bit is "0". Moreover, the shift register is sequentially shifted as the data is fetched. When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" after input of the 8 bits data. The data input in the shift register can be read from data registers SD0-SD7 by software. S1C60N08 TECHNICAL HARDWARE EPSON I-35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (3) Serial data input/output permutation The S1C60N08 Series allows the input/output permutation of serial data to be selected by mask option as to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB first and MSB first is provided in Figure 4.7.3.1. SIN Address [2F1H] SD7 SD6 SD5 SD4 Address [2F0H] SD3 SD2 SD1 SD0 Output latch SOUT Output latch SOUT In case of LSB first SIN Address [2F0H] SD0 SD1 SD2 SD3 Address [2F1H] SD4 SD5 SD6 SD7 In case of MSB first Fig. 4.7.3.1 Serial data input/output permutation (4) SIOF signal When the serial interface is used in the slave mode (external clock mode), SIOF is used to indicate whether the internal serial interface is available to transmit or receive data for the master side (external) serial device. SIOF signal is generated from output port R11 by mask option. SIOF signal becomes "1" (high) when the S1C60N08 serial interface becomes available to transmit or receive data; normally, it is at "0" (low). SIOF signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to "0" when eight synchronous clock has been counted. (5) Timing chart The serial interface timing chart is shown in Figure 4.7.3.2. SCTRG SCLK SIN 8-bit shift register SOUT ISIO SIOF (a) SE2 = "1" SCTRG SCLK SIN 8-bit shift register SOUT ISIO SIOF (b) SE2 = "0" Fig. 4.7.3.2 Serial interface timing chart I-36 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7.4 Mask option The serial interface may be selected for the following by mask option. (1) Whether or not the SIN terminal will use built-in pull down resistor may be selected. If the use of no pull down resistor is selected, take care that floating state does not occur at the SIN terminal. When the SIN terminal is not used, the use of pull down resistor should be selected. (2) Either complementary output or P channel (Pch) open drain as output specification for the SOUT terminal may be selected. However, even if Pch open drain has been selected, application of voltage exceeding power source voltage to the SOUT terminal will be prohibited. (3) Whether or not the SCLK terminal will use pull down resistor which is turned ON during input mode (external clock) may be selected. If the use of no pull down resistor is selected, take care that floating state does not occur at the SCLK terminal during input mode. Normally, the use of pull down resistor should be selected. (4) As output specification during output mode, either complementary output or P channel (Pch) open drain output may be selected for the SCLK terminal. (5) Positive or negative logic can be selected for the signal logic of the SCLK pin (SCLK or SCLK). However, keep in mind that only pull-down resistance can be set for the input mode (pull-up resistance is not built-in). (6) LSB first or MSB first as input/output permutation of serial data may be selected. (7) Output port R11 may be assigned as SIOF output terminal which will indicate whether the serial interface is available to transmit or receive signals. S1C60N08 TECHNICAL HARDWARE EPSON I-37 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7.5 Control of serial interface The control registers for the serial interface are explained below. Table 4.7.5.1 Control bits of serial interface Address Register D3 D2 D1 SCTRG IK10 KCP10 2E7H W R/W R11 R13 R12 SIOF 2ECH R/W R/W SD3 R SD2 SD1 2F0H R/W SD7 SD6 SD5 2F1H R/W SCS1 SCS0 SE2 2F2H R/W 0 0 IK2 2F3H R 1 Initial value at initial reset 2 Not set in the circuit Comment Name Init 1 1 0 SCTRG3 Trigger - Serial I/F clock trigger - K10 EIK0 Enable Mask Interrupt mask register (K10) 0 KCP10 Input comparison register (K10) 0 R Low Input port data (K10) K10 - 2 High R13 0 High/On Low/Off Output port (R13)/BZ output control R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control R11 0 High Low Output port (R11, LAMP) Output port (SIOF) SIOF Run Stop R/W R10 0 High/On Low/On Output port (R10)/BZ output control SD3 x 5 SD0 x 5 SD2 Serial I/F data register (low-order 4 bits) x 5 SD1 x 5 SD0 SD7 x 5 SD4 x 5 SD6 Serial I/F data register (high-order 4 bits) x 5 SD5 x 5 SD4 [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 SE2 Serial I/F clock edge selection 0 EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 - 2 Unused - - ISIO 0 3 - 2 Unused - - IK2 4 0 Interrupt factor flag (K20-K23) Yes No ISIO 4 0 Interrupt factor flag (serial I/F) Yes No 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 SD0-SD3, SD4-SD7: Serial interface data registers (2F0H, 2F1H) These registers are used for writing and reading serial data. During writing operation When "1" is written : High level When "0" is written : Low level Writes serial data will be output to SOUT terminal. From the SOUT terminal, the data converted to serial data as high (VDD) level bit for bits set at "1" and as low (VSS) level bit for bits set at "0". During reading operation When "1" is read out : High level When "0" is read out : Low level The serial data input from the SIN terminal can be read by this register. The data converted to parallel data, as high (VDD) level bit "1" and as low (VSS) level bit "0" input from SIN terminal. Perform data reading only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). At initial reset, these registers will be undefined. I-38 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SCS1, SCS0: Clock mode selection register (2F2H*D3, D2) Selects the synchronous clock for the serial interface (SCLK). Table 4.7.5.2 Synchronous clock selection SCS1 0 0 1 1 SCS0 0 1 0 1 Mode Master mode Slave mode Synchronous clock CLK CLK/2 CLK/4 External clock CLK: CPU system clock Synchronous clock (SCLK) is selected from among the above 4 types: 3 types of internal clock and external clock. At initial reset, external clock is selected. SE2: Clock edge selection register (2F2H*D1) Selects the timing for reading in the serial data input. When "1" is written : Rising edge of SCLK When "0" is written : Falling edge of SCLK Read-out : Valid Selects whether the fetching for the serial input data to registers (SD0-SD7) at the rising edge (at "1" writing) or falling edge (at "0" writing) of the SCLK signal. Pay attention if the synchtonous clock goes into reverse phase (SCLK SCLK) through the mask option. SCLK rising = SCLK falling, SCLK falling = SCLK rising When the internal clock is selected as the synchronous clock (SCLK), a hazard occurs in the synchronous clock (SCLK) when data is written to register SE2. The input data fetching timing may be selected but output timing for output data is fixed at SCLK rising edge. At initial reset, falling edge of SCLK (SE2 = "0") is selected. EISIO: Interrupt mask register (2F2H*D0) This is the interrupt mask register of the serial interface. When "1" is written : Enabled When "0" is written : Masked Read-out : Valid At initial reset, this register is set to "0" (mask). ISIO: Interrupt factor flag (2F3H*D0) This is the interrupt factor flag of the serial interface. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid From the status of this flag, the software can decide whether the serial interface interrupt. The interrupt factor flag is reset when it has been read out. Note, however, that even if the interrupt is masked, this flag will be set to "1" after the 8 bits data input/ output. Be sure that the interrupt factor flag reading is done with the interrupt in the DI status (interrupt flag = "0"). At initial reset, this flag is set to "0". S1C60N08 TECHNICAL HARDWARE EPSON I-39 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) SCTRG: Clock trigger (2E7H*D3) This is a trigger to start input/output of synchronous clock. When "1" is written : Trigger When "0" is written : No operation Read-out : Always "0" When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK) input/output is started. As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from perfoming trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. SIOF (R11): Serial interface status (2ECH*D1) Indicates the running status of the serial interface. When "1" is read out : RUN status When "0" is read out : STOP status Writing : Invalid The RUN status is indicated from immediatery after "1" is written to SCTRG bit through to the end of serial data input/output. 4.7.6 Programming notes (1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data of SE2 is to be changed. (2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial data is in the RUN status (during input or output), the data input or output will be suspended and the initial status resumed. Read-out during the EI status (interrupt flag = "1") causes malfunctioning. (3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fOSC1 fOSC3) while the serial interface is operating. (4) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (5) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. (6) Be sure that writing to the interrupt mask register is done only in the DI status (interrupt flag = "0"). Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause malfunction. I-40 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.8 LCD Driver (COM0-COM3, SEG0-SEG47) 4.8.1 Configuration of LCD driver The S1C60N08 Series has four common terminals and 48 (SEG0-SEG47) segment terminals, so that an LCD with a maximum of 192 (48 x 4) segments can be driven. The power for driving the LCD is generated by the internal circuit, so there is no need to supply power externally. The driving method is 1/4 duty (or 1/3, 1/2 duty is selectable by mask option) dynamic drive, adopting the four types of potential (1/3 bias), VDD, VL1, VL2 and VL3. Moreover, the 1/2 bias dynamic drive that uses three types of potential, VDD, VL1 = VL2 and VL3, can be selected by setting the mask option (drive duty can also be selected from 1/4, 1/3 or 1/2). 1/2 bias drive is effective when the LCD system voltage regulator is not used. The VL1 terminal and the VL2 terminal should be connected outside the IC. The frame frequency is 32 Hz for 1/4 duty and 1/2 duty, and 42.7 Hz for 1/3 duty (in the case of fOSC1 = 32.768 kHz). Figures 4.8.1.1 to 4.8.1.6 show the drive waveform for each duty and bias. Notes: * "fOSC1" indicates the oscillation frequency of the oscillation circuit. * If there is any segment pad that is set to be DC type, the internal LCD voltage regulator cannot be chosen in all models. Or, if the internal LCD voltage regulator is chosen in any model, the segment pad cannot be set to be DC type. Table 4.8.1.1 LCD voltage regulator and DC output from SEG terminals LCD system voltage regulator DC output from SEG terminals Use Not available Not use Available S1C60N08 TECHNICAL HARDWARE EPSON I-41 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD lighting status VDD VL1 VL2 VL3 COM0 COM0 COM1 COM2 COM3 COM1 COM2 SEG0-47 COM3 Off On VDD VL1 VL2 VL3 SEG0 -SEG47 Frame frequency Fig. 4.8.1.1 Drive waveform for 1/4 duty (1/3 bias) I-42 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) VDD VL1 VL2 VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-47 COM2 Off On COM3 VDD VL1 VL2 VL3 SEG0 -SEG47 Frame frequency Fig. 4.8.1.2 Drive waveform for 1/3 duty (1/3 bias) VDD VL1 VL2 VL3 COM0 COM1 LCD lighting status COM0 COM1 SEG0-47 COM2 COM3 VDD VL1 VL2 VL3 Off On SEG0 -SEG47 Frame frequency Fig. 4.8.1.3 Drive waveform for 1/2 duty (1/3 bias) S1C60N08 TECHNICAL HARDWARE EPSON I-43 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD lighting status -VDD -VL1, L2 -VL3 COM0 COM0 COM1 COM2 COM3 COM1 SEG0-47 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-47 Frame frequency Fig. 4.8.1.4 Drive waveform for 1/4 duty (1/2 bias) I-44 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 COM2 SEG0-47 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-47 Frame frequency Fig. 4.8.1.5 Drive waveform for 1/3 duty (1/2 bias) -VDD -VL1, L2 -VL3 COM0 COM1 LCD lighting status COM0 COM1 SEG0-47 COM2 Off On COM3 -VDD -VL1, L2 -VL3 SEG 0-47 Frame frequency Fig. 4.8.1.6 Drive waveform for 1/2 duty (1/2 bias) S1C60N08 TECHNICAL HARDWARE EPSON I-45 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.8.2 Cadence adjustment of oscillation frequency In the S1C60N08 Series, the LCD drive duty can be set to 1/1 duty by software. This function enables easy adjustment (cadence adjustment) of the oscillation frequency of the oscillation circuit. The procedure to set to 1/1 duty drive is as follows: Write "1" to the CSDC register at address 2E8H*D3. Write the same value to all registers corresponding to COMs 0 through 3 of the display memory. The frame frequency is 32 Hz (fOSC1/1,024, when fOSC1 = 32.768 kHz). Notes: * Even when l/3 or 1/2 duty is selected by the mask option, the display data corresponding to all COM are valid during 1/1 duty driving. Hence, for 1/1 duty drive, set the same value for all display memory corresponding to COMs 0 through 3. * For cadence adjustment, set the display data corresponding to COMs 0 through 3, so that all the LCD segments go on. Figures 4.8.2.1 and 4.8.2.2 show the 1/1 duty drive waveform in 1/3 bias and 1/2 bias driving. LCD lighting status -VDD -VL1 -VL2 -VL3 COM 0-3 COM0 COM1 COM2 COM3 Frame frequency SEG0-47 Off On -VDD -VL1 -VL2 -VL3 SEG 0-47 -VDD -VL1 -VL2 -VL3 Fig. 4.8.2.1 Drive waveform for 1/1 duty (1/3 bias) LCD lighting status -VDD -VL1, VL2 -VL3 COM 0-3 COM0 COM1 COM2 COM3 Frame frequency Off SEG0-47 On -VDD -VL1, VL2 -VL3 SEG 0-47 -VDD -VL1, VL2 -VL3 Fig. 4.8.2.2 Drive waveform for 1/1 duty (1/2 bias) I-46 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) 4.8.3 Mask option (segment allocation) (1) Segment allocation As shown in Figure 4.1.2, segment data of the S1C60N08 Series is decided depending on display data written to the display memory at address 040H-06FH (Page 0) or 240H-26FH (Page 2). * The mask option enables the display memory to be allocated entirely to either Page 0 or Page 2. * The address and bits of the display memory can be made to correspond to the segment terminals (SEG0-SEG47) in any form through the mask option. This makes design easy by increasing the degree of freedom with which the liquid crystal panel can be designed. Figure 4.8.3.1 shows an example of the relationship between the LCD segments (on the panel) and the display memory (when page 0 is selected) for the case of 1/3 duty. Address Common 0 Common 1 Common 2 9A, D0 9B, D1 9B, D0 (a) (f) (e) SEG11 9A, D1 9B, D2 9A, D3 (b) (g) (d) SEG12 9D, D1 9A, D2 9B, D3 (f') (c) (p) Data D3 D2 D1 D0 09AH d c b a 09BH p g f e 09CH d' c' b' a' 09DH p' g' f' e' SEG10 Display data memory allocation Pin address allocation a a' b f e g' c d SEG10 SEG11 Common 0 b' f' g c' e' p p' d' SEG12 Common 1 Common 2 Fig. 4.8.3.1 Segment allocation (2) Drive duty According to the mask option, either 1/4, 1/3 or 1/2 duty can be selected as the LCD drive duty. Table 4.8.3.1 shows the differences in the number of segments according to the selected duty. Table 4.8.3.1 Differences according to selected duty Duty COM used 1/4 COM0-COM3 1/3 COM0-COM2 1/2 COM0-COM1 S1C60N08 TECHNICAL HARDWARE Max. number of segments Frame frequency * 192 (48 x 4) fOSC1/1,024 (32 Hz) 144 (48 x 3) fOSC1/768 (42.7 Hz) 96 (48 x 2) fOSC1/1,024 (32 Hz) When fOSC1 = 32 kHz EPSON I-47 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) (3) Output specification * The segment terminals (SEG0-SEG47) are selected by mask option in pairs for either segment signal output or DC output (VDD and VSS binary output). When DC output is selected, the data corresponding to COM0 of each segment terminal is output. * When DC output is selected, either complementary output or Pch open drain output can be selected for each terminal by mask option. Note: The terminal pairs are the combination of SEG (2n) and SEG (2n + 1) (where n is an integer from 0 to 23). (4) Drive bias For the drive bias of the S1C60N08 or the S1C60L08, either 1/3 bias or 1/2 bias can be selected by the mask option. When using the LCD system voltage regulator, it is fixed at 1/3 bias. 4.8.4 Control of LCD driver Table 4.8.4.1 shows the LCD driver's control bits and their addresses. Figure 4.8.4.1 shows the display memory map. Table 4.8.4.1 Control bits of LCD driver Address Register D3 D2 D1 D0 0 0 0 LOF 2D0H R CSDC R/W ETI2 ETI8 ETI32 2E8H R/W Name 0 3 0 3 0 3 LOF CSDC ETI2 ETI8 ETI32 1 Initial value at initial reset 2 Not set in the circuit Address Low 0 Page High 4 5 0 or 2 6 1 Comment Init 1 1 0 Unused - 2 - - - 2 Unused - - - 2 Unused - - 1 Normal All off LCD all off control 0 Static Dynamic LCD drive switch 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 0 Enable Mask Interrupt mask register (clock timer 8 Hz) 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read 2 3 4 5 6 7 8 9 A B C D E F Display memory (48 words x 4 bits) Page 0: R/W, Page 2: W only Fig. 4.8.4.1 Display memory map LOF: LCD all Off control (2D0H*D0) Controls the LCD display. When "1" is written : LCD displayed When "0" is written : LCD is all off Read-out : Valid By writing "0" to the LOF register, all the LCD dots goes off, and when "1" is written, it returns to normal display. Writing "0" outputs an off waveform to the SEG terminals, and does not affect the content of the display memory. After an initial reset, LOF is set to "1". CSDC: LCD drive switch (2E8H*D3) The LCD drive format can be selected with this switch. When "1" is written : Static drive When "0" is written : Dynamic drive Read-out : Valid At initial reset, dynamic drive (CSDC = "0") is selected. I-48 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Display memory (040H-06FH or 240H-26FH) The LCD segments are lit or turned off depending on this data. When "1" is written : Lit When "0" is written : Not lit Read-out : Valid for Page 0 Undefined Page 2 By writing data into the display memory allocated to the LCD segment (on the panel), the segment can be lit or put out. At initial reset, the contents of the display memory are undefined. 4.8.5 Programming notes (1) When Page 0 is selected for the display memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the display memory by executing initial processing. (2) When Page 2 is selected for the display memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). S1C60N08 TECHNICAL HARDWARE EPSON I-49 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.9 Clock Timer 4.9.1 Configuration of clock timer The S1C60N08 Series has a built-in clock timer as the source oscillator for prescaler. The clock timer is configured of a seven-bit binary counter that serves as the input clock, a 256 Hz signal output by the prescaler. Data of the four high-order bits (16 Hz-2 Hz) can be read out by the software. Figure 4.9.1.1 is the block diagram for the clock timer. Data bus OSC1 oscillation circuit Clock Timer Prescaler 2 256 Hz Selector 128 Hz-32 Hz 16 Hz-2 Hz Prescaler 1 Watchdog timer 32 Hz, 8 Hz, 2 Hz Prescaler selection signal Interrupt control Clock timer reset signal Interrupt request Fig. 4.9.1.1 Clock timer block diagram Ordinarily, this clock timer is used for all types of timing functions such as clocks. The input clock of the clock timer is output through the prescaler, so the prescaler mode must be set correctly to suit the crystal oscillator to be used (32.768 kHz or 38.4 kHz). For how to set the prescaler, see Section 4.3, "Oscillation Circuit and Prescaler". 4.9.2 Interrupt function The clock timer can cause interrupts at the falling edge of 32 Hz, 8 Hz and 2 Hz signals. Software can set whether to mask any of these frequencies. Figure 4.9.2.1 is the timing chart of the clock timer. Address Register Frequency 2E0H D0 16 Hz D1 8 Hz D2 4 Hz D3 2 Hz Clock timer timing chart 32 Hz interrupt request 8 Hz interrupt request 2 Hz interrupt request Fig. 4.9.2.1 Clock timer timing chart As shown in Figure 4.9.2.1, interrupt is generated at the falling edge of the frequencies (32 Hz, 8 Hz , 2 Hz). At this time, the corresponding interrupt factor flag (TI32, TI8, TI2) is set to "1". Selection of whether to mask the separate interrupts can be made with the interrupt mask registers (ETI32, ETI8, ETI2). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. I-50 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) 4.9.3 Control of clock timer Table 4.9.3.1 shows the clock timer control bits and their addresses. Table 4.9.3.1 Control bits of clock timer Address Register Comment 1 0 Name Init 1 TM3 Clock timer data (2 Hz) 0 TM3 TM2 TM1 TM0 TM2 Clock timer data (4 Hz) 0 2E0H TM1 Clock timer data (8 Hz) 0 R TM0 Clock timer data (16 Hz) 0 CSDC 0 Static Dynamic LCD drive switch CSDC ETI2 ETI8 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No TMRST3 Reset Reset Clock timer reset - TMRST SWRUN SWRST IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop 2EEH SWRST3 Reset Reset Stopwatch timer reset - W R/W W R/W IOC0 0 Output Input I/O control register 0 (P00-P03) 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 TM0-TM3: Timer data (2E0H) The 16 Hz-2 Hz timer data of the clock timer can be read out with this register. These four bits are readout only, and writing operations are invalid. At initial reset, the timer data is initialized to "0H". ETI32, ETI8, ETI2: Interrupt mask registers (2E8H*D0-D2) These registers are used to select whether to mask the clock timer interrupt. When "1" is written : Enabled When "0" is written : Masked Read-out : Valid The interrupt mask registers (ETI32, ETI8, ETI2) are used to select whether to mask the interrupt to the separate frequencies (32 Hz, 8 Hz, 2 Hz). Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are all set to "0". TI32, TI8, TI2: Interrupt factor flags (2E9H*D0-D2) These flags indicate the status of the clock timer interrupt. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid The interrupt factor flags (TI32, TI8, TI2) correspond to the clock timer interrupts of the respective frequencies (32 Hz, 8 Hz, 2 Hz). The software can judge from these flags whether there is a clock timer interrupt. However, even if the interrupt is masked, the flags are set to "1" at the falling edge of the signal. These flags can be reset through being read out by the software. Also, the flags can be read out only in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". S1C60N08 TECHNICAL HARDWARE EPSON I-51 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) TMRST: Clock timer reset (2EEH*D3) This bit resets the clock timer. When "1" is written : Clock timer reset When "0" is written : No operation Read-out : Always "0" The clock timer is reset by writing "1" to TMRST. The clock timer starts immediately after this. No operation results when "0" is written to TMRST. This bit is write-only, and so is always "0" at read-out. 4.9.4 Programming notes (1) The prescaler mode must be set correctly to suit the crystal oscillator to be used. (2) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) as necessary at reset. (3) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer may be counted up at timer reset. (4) Read-out the interrupt factor flag (TI) only during the DI status (interrupt flag = "0"). Read-out during EI status (interrupt flag = "1") will cause malfunction. I-52 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.10 Stopwatch Timer 4.10.1 Configuration of stopwatch timer The S1C60N08 Series incorporates a 1/100 sec and 1/10 sec stopwatch timer. The stopwatch timer is configured of a two-stage, four-bit BCD counter serving as the input clock of an approximately 100 Hz signal (signal obtained by approximately demultiplying the 256 Hz signal output by the prescaler). Data can be read out four bits at a time by the software. Figure 4.10.1.1 is the block diagram of the stopwatch timer. Data bus OSC1 oscillation circuit Prescaler 2 256 Hz Selector Stopwatch Timer 10 Hz SWL counter SWH counter Prescaler 1 10 Hz, 1 Hz Prescaler selection signal Interrupt control Stopwatch timer reset signal Stopwatch timer RUN/STOP signal Interrupt request Fig. 4.10.1.1 Stopwatch timer block diagram The stopwatch timer can be used as a separate timer from the clock timer. In particular, digital watch stopwatch functions can be realized easily with software. The input clock of the stopwatch timer is output through the prescaler, so the prescaler mode must be set correctly to suit the crystal oscillator to be used (32.768 kHz or 38.4 kHz). For how to set the prescaler, see Section 4.3, "Oscillation Circuit and Prescaler". 4.10.2 Count-up pattern The stopwatch timer is configured of four-bit BCD counters SWL and SWH. The counter SWL, at the stage preceding the stopwatch timer, has an approximated 100 Hz signal for the input clock. It counts up every 1/100 sec, and generates an approximated 10 Hz signal. The counter SWH has an approximated 10 Hz signal generated by the counter SWL for the input clock. It count-up every 1/ 10 sec, and generated 1 Hz signal. Figure 4.10.2.1 shows the count-up pattern of the stopwatch timer. SWH count-up pattern SWH count value 0 Count time (sec) 1 26 256 SWL count-up pattern 1 SWL count value Count time (sec) SWL count-up pattern 2 SWL count value Count time (sec) 2 3 4 5 6 7 8 9 0 26 25 25 26 26 25 25 26 26 256 256 256 256 256 256 256 256 256 26 x 6 + 25 x 4 = 1 (sec) 256 256 0 1 3 256 0 2 3 4 5 6 7 8 9 0 2 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 25 256 (sec) 1 2 3 4 5 6 7 8 9 0 3 3 3 2 3 2 3 2 3 2 256 256 256 256 256 256 256 256 256 256 26 (sec) 256 1 Hz signal generation Approximate 10 Hz signal generation Approximate 10 Hz signal generation Fig. 4.10.2.1 Count-up pattern of stopwatch timer S1C60N08 TECHNICAL HARDWARE EPSON I-53 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWL generates an approximated 10 Hz signal from the basic 256 Hz signal. The count-up intervals are 2/ 256 sec and 3/256 sec, so that finally two patterns are generated: 25/256 sec and 26/256 sec intervals. Consequently, these patterns do not amount to an accurate 1/100 sec. SWH counts the approximated 10 Hz signals generated by the 25/256 sec and 26/256 sec intervals in the ratio of 4:6, to generate a 1 Hz signal. The count-up intervals are 25/256 sec and 26/256 sec, which do not amount to an accurate 1/10 sec. 4.10.3 Interrupt function The 10 Hz (approximate 10 Hz) and 1 Hz interrupts can be generated through the overflow of stopwatch timers SWL and SWH respectively. Also, software can set whether to separately mask the frequencies described earlier. Figure 4.10.3.1 is the timing chart for the stopwatch timer. Address Register 2E1H D0 1/100 sec (BCD) D1 Stopwatch timer (SWL) timing chart D2 D3 10 Hz interrupt request Address Register 2E2H D0 1/10 sec (BCD) D1 Stopwatch timer (SWH) timing chart D2 D3 1 Hz interrupt request Fig. 4.10.3.1 Stopwatch timer timing chart As shown in Figure 4.10.3.1, the interrupts are generated by the overflow of their respective counters ("9" changing to "0"). Also, at this time the corresponding interrupt factor flags (SWIT0, SWIT1) are set to "1". The respective interrupts can be masked separately through the interrupt mask registers (EISWIT0, EISWIT1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. I-54 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) 4.10.4 Control of stopwatch timer Table 4.10.4.1 list the stopwatch timer control bits and their addresses. Table 4.10.4.1 Control bits of stopwatch timer Address Register Comment 1 0 Name Init 1 SWL3 MSB 0 SWL3 SWL2 SWL1 SWL0 SWL2 0 2E1H Stopwatch timer 1/100 sec data (BCD) SWL1 0 R SWL0 LSB 0 SWH3 MSB 0 SWH3 SWH2 SWH1 SWH0 SWH2 0 2E2H Stopwatch timer 1/10 sec data (BCD) SWH1 0 R SWH0 LSB 0 HLMOD Heavy load Normal Heavy load protection mode register 0 HLMOD BLD0 EISWIT1 EISWIT0 Low Normal Sub-BLD evaluation data BLD0 0 2E6H Enable Mask Interrupt mask register (stopwatch 1 Hz) EISWIT1 0 R/W R R/W Enable Mask Interrupt mask register (stopwatch 10 Hz) EISWIT0 0 IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No TMRST3 Reset Reset Clock timer reset - TMRST SWRUN SWRST IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop 2EEH SWRST3 Reset Reset Stopwatch timer reset - W R/W W R/W IOC0 0 Output Input I/O control register 0 (P00-P03) 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 SWL0-SWL3: Stopwatch timer 1/100 sec (2E1H) Data (BCD) of the 1/100 sec column of the stopwatch timer can be read out. These four bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0H". SWH0-SWH3: Stopwatch timer 1/10 sec (2E2H) Data (BCD) of the 1/10 sec column of the stopwatch timer can be read out. These four bits are read-only, and cannot be used for writing operations. At initial reset, the timer data is set to "0H". EISWIT0, EISWIT1: Interrupt mask registers (2E6H*D0 and D1) These registers are used to select whether to mask the stopwatch timer interrupt. When "1" is written : Enabled When "0" is written : Masked Read-out : Valid The interrupt mask registers (EISWIT0, EISWIT1) are used to separately select whether to mask the 10 Hz and 1 Hz interrupts. At initial reset, these registers are both set to "0". S1C60N08 TECHNICAL HARDWARE EPSON I-55 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer) SWIT0, SWIT1: Interrupt factor flags (2EAH*D0 and D1) These flags indicate the status of the stopwatch timer interrupt. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid The interrupt factor flags (SWIT0, SWIT1) correspond to the 10 Hz and 1 Hz interrupts respectively. With these flags, the software can judge whether a stopwatch timer interrupt has occurred. However, regardless of the interrupt mask register setting, these flags are set to "1" by the counter overflow. These flags are reset when read out by the software. Also, read-out is only possible in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". SWRST: Stopwatch timer reset (2EEH*D1) This bit resets the stopwatch timer. When "1" is written : Stopwatch timer reset When "0" is written : No operation Read-out : Always "0" The stopwatch timer is reset when "1" is written to SWRST. When the stopwatch timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. This bit is write-only, and is always "0" at read-out. SWRUN: Stopwatch timer RUN/STOP (2EEH*D2) This bit controls RUN/STOP of the stopwatch timer. When "1" is written : RUN When "0" is written : STOP Read-out : Valid The stopwatch timer enters the RUN status when "1" is written to SWRUN, and the STOP status when "0" is written. In the STOP status, the timer data is maintained until the next RUN status or resets timer. Also, when the STOP status changes to the RUN status, the data that was maintained can be used for resuming the count. When the timer data is read out in the RUN status, correct read-out may be impossible because of the carry from the low-order bit (SWL) to the high-order bit (SWH). This occurs when read-out has extended over the SWL and SWH bits when the carry occurs. To prevent this, perform read out after entering the STOP status, and then return to the RUN status. Also, the duration of the STOP status must be within 976 sec (256 Hz 1/4 cycle). At initial reset, this register is set to "0". 4.10.5 Programming notes (1) The prescaler mode must be set correctly so that the stopwatch timer suits the crystal oscillator to be used. (2) If timer data is read out in the RUN status, the timer must be made into the STOP status, and after data is read out the RUN status can be restored. If data is read out when a carry occurs, the data cannot be read correctly. Also, the processing above must be performed within the STOP interval of 976 sec (256 Hz 1/4 cycle). (3) Read-out of the interrupt factor flag (SWIT) must be done only in the DI status (interrupt flag = "0"). Read-out during EI status (interrupt flag = "1") will cause malfunction. I-56 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.11 Sound Generator 4.11.1 Configuration of sound generator The S1C60N08 Series outputs buzzer signals (BZ, BZ) to drive the piezoelectric buzzer. The frequency of the buzzer signal is software-selectable from eight kinds of demultiplied fOSC1. Further, a digital envelope can be added to the buzzer signal through duty ratio control. Figure 4.11.1.1 shows the sound generator configuration. Figure 4.11.1.2 shows the sound generator timing chart. [ENVRST] [ENVRT] Envelope generation circuit 256 Hz [BZFQ0-BZFQ2] Programmable dividing circuit fOSC1 [ ] : Register Envelope addition circuit [ENVON] [R10] Output port [R13] R10 (BZ) R13 (BZ) Fig. 4.11.1.1 Configuration of sound generator SR BZFQ0-2 ENVON ENVRT R10(register) R13(register) BZ(R10 terminal) BZ(R13 terminal register R10 control) BZ(R13 terminal register R13 control) Fig. 4.11.1.2 Timing chart of sound generator S1C60N08 TECHNICAL HARDWARE EPSON I-57 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.11.2 Frequency setting The frequencies of the buzzer signals (BZ, BZ) are set by writing data to registers BZFQ0-BZFQ2. Table 4.11.2.1 lists the register setting values and the frequencies that can be set. Table 4.11.2.1 Setting of frequencies of buzzer signals BZFQ Buzzer frequency (Hz) 2 1 0 Demultiplier ratio When fOSC1 = 32 kHz When fOSC1 = 38.4 kHz 0 0 0 fOSC1/8 4,096.0 4,800.0 0 0 1 fOSC1/10 3,276.8 3,840.0 0 1 0 fOSC1/12 2,730.7 3,200.0 0 1 1 fOSC1/14 2,340.6 2,742.9 1 0 0 fOSC1/16 2,048.0 2,400.0 1 0 1 fOSC1/20 1,638.4 1,920.0 1 1 0 fOSC1/24 1,365.3 1,600.0 1 1 1 fOSC1/28 1,170.3 1,371.4 Note: A hazard may be observed in the output waveform of the BZ and BZ signals when data of the buzzer frequency selection registers (BZFQ0-BZFQ2) changes. 4.11.3 Digital envelope A duty ratio control data envelope (with duty ratio change in eight stages) can be added to the buzzer signal (BZ, BZ). The duty ratio is the ratio of the pulse width compared with the pulse cycle. The BZ output is TH/ (TH+TL) when the high level output is TH and the low level output is TL. The BZ output (BZ inverted output) is TL/ (TH+TL). Also, care must be taken because the duty ratio differs depending on the buzzer frequency. The envelope is added by writing "1" to register ENVON. If "0" is written the duty ratio is fixed to the maximum. Also, if the envelope is added, the duty ratio is reverted to the maximum by writing "1" in register ENVRST, and the duty ratio also becomes the maximum at the start of the buzzer signal output. The decay time of the envelope (time for the duty ratio to change) can be selected with the register ENVRT. This time is 62.5 msec (16 Hz) when "0" is written, and 125 msec (8 Hz) when "1" is written. However, a maximum difference of 4 msec is taken from envelope-ON until the first change. Table 4.11.3.1 lists the duty rates and buzzer frequencies. Figure 4.11.3.1 shows the digital envelope timing chart. Table 4.11.3.1 Duty rates and buzzer frequencies BZFQ 2 1 0 Duty rate Level 1 (max.) Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 (min.) (register) I-58 0 1 0 0 0 0 8/16 7/16 6/16 5/16 4/16 3/16 2/16 1/16 0 1 0 0 1 1 8/20 7/20 6/20 5/20 4/20 3/20 2/20 1/20 EPSON 0 1 1 1 0 0 12/24 11/24 10/24 9/24 8/24 7/24 6/24 5/24 0 1 1 1 1 1 12/28 11/28 10/28 9/28 8/28 7/28 6/28 5/28 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) No change of duty level SR BZFQ0-2 ENON ENVRST ENVRT R10 (register) BZ signal duty ratio Level 1 (MAX) 2 3 4 5 6 7 8 (MIN) t01 t02 t03 t04 t05 t06 t07 t01 +0 62.5 -4 t01 = msec t02-07 = 62.5 msec t11 t12 t13 t14 t15 t16 t17 +0 125 -4 t11 = msec t12-17 = 125 msec Fig. 4.11.3.1 Digital envelope timing chart 4.11.4 Mask option (1) Selection can be made whether to output the BZ signal from the R10 terminal. (2) Selection can be made whether to output the BZ signal from the R13 terminal. However, if the BZ signal is not output the BZ signal cannot be output. (3) Selection can be made to perform the BZ signal output control through the R10 register or the R13 register. See Section 4.5, "Output Ports" for details of the above mask option. S1C60N08 TECHNICAL HARDWARE EPSON I-59 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) 4.11.5 Control of sound generator Table 4.11.5.1 lists the sound generator's control bits and their addresses. Table 4.11.5.1 Control bits of sound generator Address Register Comment Name Init 1 1 0 R13 0 High/On Low/Off Output port (R13)/BZ output control R11 R13 R12 R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control SIOF 2ECH R11 0 High Low Output port (R11, LAMP) R/W SIOF 0 Run Stop Output port (SIOF) R/W R/W R R10 0 High/On Low/On Output port (R10)/BZ output control [BZFQ2-0] 0 1 2 3 BZFQ2 0 Buzzer BZFQ2 BZFQ1 BZFQ0 ENVRST Frequency fOSC1/8 fOSC1/10 fOSC1/12 fOSC1/14 BZFQ1 0 frequency 5 6 7 [BZFQ2-0] 4 2F6H BZFQ0 0 selection Frequency fOSC1/16 fOSC1/20 fOSC1/24 fOSC1/28 R/W W ENVRST3 Reset Reset - Envelope reset ENVON Envelope On/Off 0 On Off ENVON ENVRT AMPDT AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register 2F7H AMPDT 1 +>+ < - Analog comparator data R/W R R/W AMPON Analog comparator On/Off 0 On Off 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 BZFQ0-BZFQ2: Buzzer frequency selection register (2F6H*D1-D3) This is used to select the frequency of the buzzer signal. Table 4.11.5.2 Buzzer frequency BZFQ2 0 0 0 0 1 1 1 1 BZFQ1 0 0 1 1 0 0 1 1 BZFQ0 Buzzer frequency (Hz) 0 fOSC1/8 1 fOSC1/10 0 fOSC1/12 1 fOSC1/14 0 fOSC1/16 1 fOSC1/20 0 fOSC1/24 1 fOSC1/28 Buzzer frequency is selected from the above eight types that have been divided by fOSC1 (oscillation frequency of the OSC1 oscillation circuit). At initial reset, fOSC1/8 (Hz) is selected. ENVRST: Envelope reset (2F6H*D0) This is the reset input to make the duty ratio of the buzzer signal the maximum. When "1" is written : Reset input When "0" is written : No operation Read-out : Always "0" When the envelope is added to the buzzer signal, the duty ratio is made maximum through this reset input. When the envelope is not added or when the buzzer signal is not output, the reset input is invalid. ENVON: Envelope ON/OFF (2F7H*D3) This controls adding the envelope to the buzzer signal. When "1" is written : Envelope added (ON) When "0" is written : No envelope (OFF) Read-out : Valid The envelope is the digital envelope based on duty ratio control. When there is no envelope, the duty ratio is fixed to the maximum. At initial reset, no envelope (OFF) is selected. I-60 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Sound Generator) ENVRT: Envelope decay time (2F7H*D2) This input selects the decay time of the envelope added to the buzzer signal. When "1" is written : 1.0 sec (125 msec x 7 = 875 msec) When "0" is written : 0.5 sec (62.5 msec x 7 = 437.5 msec) Read-out : Valid The decay time of the digital envelope is decided by the time taken for the duty ratio to change. When "1" is written to ENVRT the time is 125 msec (8 Hz) units, and when "0" is written it is 62.5 msec (16 Hz) units. At initial reset, 0.5 sec (437.5 msec) is selected. R10, R13 (at BZ, BZ output selection): Special output port data (2ECH*D0, D3) These control output of the buzzer signals (BZ, BZ). When "1" is written : Buzzer signal output When "0" is written : Low level (DC) output Read-out : Valid * BZ output under R13 control BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to register R10. BZ output is controlled by writing data to register R13. * BZ output under R10 control By writing data to register R10 only, BZ output and BZ output can be controlled simultaneously. In this case, register R13 can be used as a read/write one-bit general register. This register does not affect BZ output (output to pin R13). At initial reset, R10 and R13 are set to "0". 4.11.6 Programming note A hazard may be observed in the output waveform of the BZ and BZ signals when data of the output registers (R10, R13) and the buzzer frequency selection registers (BZFQ0-BZFQ2) changes. S1C60N08 TECHNICAL HARDWARE EPSON I-61 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) 4.12 Event Counter 4.12.1 Configuration of event counter The S1C60N08 Series has an event counter that counts the clock signals input from outside. The event counter is configured of a pair of eight-bit binary counters (UP counters). The clock pulses are input through terminals K02 and K03 of the input port. The clock signals input from the terminals are input to the event counter via the noise rejector. The event counter detects the phases of the two clock signals. Software selection provides for two modes, the phase detection mode in which one of the counters can be chosen to input the clock signal, and the separate mode in which each clock signal is input to different counters. Figure 4.12.1.1 shows the configuration of the event counter. K02 Input port Interrupt request K03 Noise rejector Event counter 0 [EV00-EV07] [EV0RST] Phase detection circuit [EVRUN] [EVSEL] Event counter 1 [EV10-EV17] Noise rejector [EV1RST] [ ] : Register Fig. 4.12.1.1 Configuration of event counter 4.12.2 Switching count mode The event counter detects the phases of the two clock signals. Software selection provides for two modes, the phase detection mode in which one of the counters can be chosen to input the clock signal, and the separate mode in which each clock signal is input to different counters. Selection can be made by writing data to the EVSEL register. When "0" is written the phase detection mode is enabled, and when "1" is written the separate mode is enabled. In the phase detection mode, the clock signals having different phases must be input simultaneously to terminals K02 and K03. When the input from terminal K02 is fast the clock signal is input to event counter 1, and when the input from terminal K03 is fast the clock signal is input to event counter 0. In the separate mode, input from terminal K02 is made to event counter 0, and input from terminal K03 is made to event counter 1. Figure 4.12.2.1 is the timing chart for the event counter. I-62 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) Terminal K02 input TP T H TP TL TP T H TP TL Noise TN Terminal K03 input EVRUN TON TOFF STOP RUN When EVSEL="0" (phase detection mode) Input to event counter 0 Input to event counter 1 When EVSEL="1" (separate mode) Input to event counter 0 Input to event counter 1 Defined time TON 1.5 Tch TOFF 1.5 Tch TN < 0.5 Tch Tch = 1/fch: fch, the clock frequency for thenoise rejector, can be selected as fOSC1/16 or fOSC1/128 with the mask option Fig. 4.12.2.1 Event counter timing chart TP 1.5 Tch TH 1.5 Tch TL 1.5 Tch 4.12.3 Mask option The clock frequency of the noise rejector can be selected as fOSC1/16 or fOSC1/128. Table 4.12.3.1 lists the defined time depending on the frequency selected. Table 4.12.3.1 Defined time depending on frequency selected fOSC1 = 32.768 kHz fOSC1/16 fOSC1/128 TN 0.24 1.95 TON 0.74 5.86 TOFF 0.74 5.86 TP 0.74 5.86 TH 0.74 5.86 TL 0.74 5.86 : Max value TN Others : Min value Selection S1C60N08 TECHNICAL HARDWARE EPSON fOSC1 = 38.400 kHz fOSC1/16 fOSC1/128 0.20 1.66 0.63 5.00 0.63 5.00 0.63 5.00 0.63 5.00 0.63 5.00 (Unit: msec) I-63 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) 4.12.4 Control of event counter Table 4.12.4.1 shows the event counter control bits and their addresses. Table 4.12.4.1 Control bits of event counter Address Register Comment 1 0 Name Init 1 EV03 0 EV03 EV02 EV01 EV00 EV02 0 2F8H Event counter 0 (low-order 4 bits) EV01 0 R EV00 0 EV07 0 EV07 EV06 EV05 EV04 EV06 0 2F9H Event counter 0 (high-order 4 bits) EV05 0 R EV04 0 EV13 0 EV13 EV12 EV11 EV10 EV12 0 2FAH Event counter 1 (low-order 4 bits) EV11 0 R EV10 0 EV17 0 EV17 EV16 EV15 EV14 EV16 0 2FBH Event counter 1 (high-order 4 bits) EV15 0 R EV14 0 EVSEL 0 Separate Phase Event counter mode selection EVSEL ENRUN EV1RST EV0RST EVRUN 0 Run Stop Event counter Run/Stop 2FCH EV1RST3 Reset Reset Event counter 1 reset - R/W W EV0RST3 Reset Reset Event counter 0 reset - 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 EV00-EV03: Event counter 0 low-order data (2F8H) The four low-order data bits of event counter 0 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 0 is set to "00H". EV04-EV07: Event counter 0 high-order data (2F9H) The four high-order data bits of event counter 0 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 0 is set to "00H". EV10-EV13: Event counter 1 low-order data (2FAH) The four low-order data bits of event counter 1 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 1 is set to "00H". EV14-EV17: Event counter 1 high-order data (2FBH) The four high-order data bits of event counter 1 are read out. These four bits are read-only, and cannot be used for writing. At initial reset, event counter 1 is set to "00H". EV0RST: Event counter 0 reset (2FCH*D0) This is the register for resetting event counter 0. When "1" is written : Event counter 0 reset When "0" is written : No operation Read-out : Always "0" When "1" is written, event counter 0 is reset and the data becomes "00H". When "0" is written, no operation is executed. This is a write-only bit, and is always "0" at read-out. I-64 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) EV1RST: Event counter 1 reset (2FCH*D1) This is the register for resetting event counter 1. When "1" is written : Event counter 1 reset When "0" is written : No operation Read-out : Always "0" When "1" is written, event counter 1 is reset and the data becomes "00H". When "0" is written, no operation is executed. This is a write-only bit, and is always "0" at read-out. EVRUN: Event counter RUN/STOP (2FCH*D2) This register controls the event counter RUN/STOP status. When "1" is written : RUN When "0" is written : STOP Read-out : Valid When "1" is written, the event counter enters the RUN status and starts receiving the clock signal input. When "0" is written, the event counter enters the STOP status and the clock signal input is ignored. (However, input to the input port is valid.) At initial reset, this register is set to "0". EVSEL: Event counter mode (2FCH*D3) This register control the count mode of the event counter. When "1" is written : Separate When "0" is written : Phase detection Read-out : Valid When "0" is written, the phases of the two clock signals are detected, and the phase detection mode is selected, in which one of the counters is chosen to input the clock signal. When "1" is written, the separate mode is selected, in which each clock signal is input to different counters. At initial reset, this register is set to "0". 4.12.5 Programming notes (1) After the event counter has written data to the EVRUN register, it operates or stops in synchronization with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the above timing when input signals (input to K02 and K03) are being received. (2) To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result. S1C60N08 TECHNICAL HARDWARE EPSON I-65 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator) 4.13 Analog Comparator 4.13.1 Configuration of analog comparator The S1C60N08 Series incorporates an MOS input analog comparator. This analog comparator, which has two differential input terminals (inverted input terminal AMPM, non-inverted input terminal AMPP), can be used for general purposes. Figure 4.13.1.1 shows the configuration of the analog comparator. VDD + AMPM - AMPDT Data bus AMPP Input control Power source AMPON control Address VSS Fig. 4.13.1.1 Configuration of analog comparator 4.13.2 Operation of analog comparator The analog comparator is ON when the AMPON register is "1", and compares the input levels of the AMPP and AMPM terminals. The result of the comparison is read from the AMPDT register. It is "1" when AMPP (+) > AMPM (-) and "0" when AMPP (+) < AMPM (-). After the analog comparator goes ON it takes a maximum of 3 msec until the output stabilizes. I-66 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator) 4.13.3 Control of analog comparator Table 4.13.3.1 lists the analog comparator control bits and their addresses. Table 4.13.3.1 Control bits of analog comparator Address Register Comment 1 0 Name Init 1 ENVON Envelope On/Off 0 On Off ENVON ENVRT AMPDT AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register 2F7H AMPDT 1 +>+ < - Analog comparator data R/W R R/W AMPON Analog comparator On/Off 0 On Off 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 AMPON: Analog comparator ON/OFF (2F7H*D0) Switches the analog comparator ON and OFF. When "1" is written : The analog comparator goes ON When "0" is written : The analog comparator goes OFF Read-out : Valid The analog comparator goes ON when "1" is written to AMPON, and OFF when "0" is written. At initial reset, AMPON is set to "0". AMPDT: Analog comparator data (2F7H*D1) Reads out the output from the analog comparator. When "1" is read out : AMPP (+) > AMPM (-) When "0" is read out : AMPP (+) < AMPM (-) Writing : Invalid AMPDT is "0" when the input level of the inverted input terminal (AMPM) is greater than the input level of the noninverted input terminal (AMPP); and "1" when smaller. At initial reset, AMPDT is set to "1". 4.13.4 Programming notes (1) To reduce current consumption, set the analog comparator to OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 msec for the operation of the analog comparator to stabilize before reading the output data of the analog comparator from AMPDT. S1C60N08 TECHNICAL HARDWARE EPSON I-67 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit) 4.14 Battery Life Detection (BLD) Circuit 4.14.1 Configuration of BLD circuit The S1C60N08 Series has a built-in battery life detection (BLD) circuit, so that the software can find when the source voltage lowers. The configuration of the BLD circuit is shown in Figure 4.14.1.1. Also provides a heavy load protection function and an associated sub-BLD circuit. See Section 4.15, "Heavy Load Protection Function and Sub-BLD Circuit". Turning the BLD operation ON/OFF is controlled through the software (HLMOD, BLS). Moreover, when a drop in source voltage (BLD0 = "1") is detected by the sub-BLD circuit, BLD operation is periodically performed by the hardware until the source voltage is recovered (BLD0 = "0"). Because the power current consumption of the IC increases when the BLD operation is turned ON, set the BLD operation to OFF unless otherwise necessary. VDD Address 2E6H BLD sampling control HLMOD Address 2FFH Data bus BLD circuit BLS VSS BLD1 Detection output BLC2 Evaluation voltage setting circuit BLC1 BLC0 Fig. 4.14.1.1 Configuration of BLD circuit 4.14.2 Programmable selection of evaluation voltage In the S1C60N08 Series, the evaluation voltage for judging the battery life can be switched by programming. Consequently, the optimum evaluation voltage can be set for the battery used. One of eight evaluation voltages can be selected with the software. Table 4.14.2.1 lists the evaluation voltages for the models in the S1C60N08 Series. Table 4.14.2.1 Evaluation voltages for BLD circuit Register setting BLC2 BLC1 BLC0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Evaluation voltage (V) S1C60L08 S1C60N08 S1C60A08 1.05 2.20 2.20 1.10 2.25 2.25 1.15 2.30 2.30 1.20 2.35 2.35 1.25 2.40 2.40 1.30 2.45 2.45 1.35 2.50 2.50 1.40 2.55 2.55 See the electrical characteristics for the evaluation voltage accuracy. I-68 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit) 4.14.3 Detection timing of BLD circuit This section explains the timing for when the BLD circuit writes the result of the source voltage detection to the BLD latch. Turning the BLD operation ON/OFF is controlled through the software (HLMOD, BLS). Moreover, when a drop in source voltage (BLD0 = "1") is detected by the sub-BLD circuit, BLD operation is periodically performed by the hardware until the source voltage is recovered (BLD0 = "0"). The result of the source voltage detection is written to the BLD latch by the BLD circuit, and this data can be read out by the software to find the status of the source voltage. There are three status, explained below, for the detection timing of the BLD circuit. (1) Sampling with HLMOD set to "1" When HLMOD is set to "1" and BLD sampling executed, the detection results can be written to the BLD latch in the following two timings. Immediately after the time for one instruction cycle has ended immediately after HLMOD = "1" Immediately after sampling in the 2 Hz cycle output by the clock timer while HLMOD = "1" Consequently, the BLD latch data is loaded immediately after HLMOD has been set to "1", and at the same time the new detection result is written in 2 Hz cycles. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 sec. When the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in above may be invalid or incorrect. (When performing BLD detection using the timing in , be sure that the CPU system clock is fOSC1.) (2) Sampling with BLS set to "1" When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 sec. Hence, to obtain the BLD detection result, follow the programming sequence below. 0. 1. 2. 3. 4. 5. Set HLMOD to "1" (only when the CPU system clock is fOSC3 in the S1C60A08) Set BLS to "1" Maintain at 100 sec minimum Set BLS to "0" Read out BLD Set HLMOD to "0" (only when the CPU system clock is fOSC3 in the S1C60A08) However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N08, S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 sec for the BLS = "1" with the software. (3) Sampling by hardware when sub-BLD latch is set to "1" When BLD0 (sub-BLD latch) is set to "1", the detection results can be written to the BLD0 (sub-BLD latch) and BLD1 (BLD latch) in the following two timings (same as that sampling with HLMOD set to "1"). Immediately after the time for one instruction cycle has ended immediately after BLD0 = "1" Immediately after sampling in the 2 Hz cycle output by the clock timer while BLD0 = "1" Consequently, the BLD0 (sub-BLD latch) and BLD1 (BLD latch) data are loaded immediately after BLD0 (sub-BLD latch) has been set to "1", and at the same time the new detection result is written in 2 Hz cycles. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 sec. When the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in above may be invalid or incorrect. S1C60N08 TECHNICAL HARDWARE EPSON I-69 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit) 4.14.4 Control of BLD circuit Table 4.14.4.1 shows the BLD circuit's control bits and their addresses. Table 4.14.4.1 Control bits of BLD circuit Address Register Comment 1 0 Name Init 1 HLMOD Heavy load Normal Heavy load protection mode register 0 HLMOD BLD0 EISWIT1 EISWIT0 BLD0 Low Normal Sub-BLD evaluation data 0 2E6H EISWIT1 Enable Mask Interrupt mask register (stopwatch 1 Hz) 0 R/W R R/W EISWIT0 Enable Mask Interrupt mask register (stopwatch 10 Hz) 0 BLS On Off BLD On/Off 0 BLS BLC2 BLC1 BLC0 BLD1 Low Normal BLD evaluation data 0 BLD1 Evaluation voltage setting register 2FFH x 5 BLC2 [BLC2-0] 0 1 2 3 4 5 6 7 W x 5 BLC1 R/W S1C60N08/60A08 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 (V) R S1C60L08 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 (V) x 5 BLC0 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 HLMOD: Heavy load protection mode (2E6H*D3) Sets the IC in heavy load protection mode. When "1" is written : Heavy load protection mode is set When "0" is written : Heavy load protection mode is released Read-out : Valid When HLMOD is set to "1", the IC operating status enters the heavy load protection mode and at the same time the battery life detection of the BLD circuit is controlled (ON/OFF). For details about the heavy load protection mode, see Section 4.15, "Heavy Load Protection Function and Sub-BLD Circuit". When HLMOD is set to "1", sampling control is executed for the BLD circuit ON time. There are two types of sampling time, as follows: (1) The time of one instruction cycle immediately after HLMOD = "1" (2) Sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1" The BLD circuit must be made ON with at least 100 sec for the BLD circuit to respond. Hence, when the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in (1) above may be invalid or incorrect. When performing BLD detection using the timing in (1), be sure that the CPU system clock is fOSC1. When BLD sampling is done with HLMOD set to "1", the results are written to the BLD latch in the timing as follows: (1) As soon as the time has elapsed for one instruction cycle immediately following HLMOD = "1" (2) Immediately on completion of sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1" Consequently, the BLD latch data is written immediately after HLMOD is set to "1", and at the same time the new detection result is written in 2 Hz cycles. I-70 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (BLD Circuit) BLS/BLD1: BLD detection/BLD data (2FFH*D3) Controls the BLD operation. When "0" is written : When "1" is written : When "0" is read out : When "1" is read out : BLD detection OFF BLD detection ON Source voltage (VDD-VSS) is higher than BLD set value Source voltage (VDD-VSS) is lower than BLD set value Note that the function of this bit when written is different to when read out. When this bit is written to, ON/OFF of the BLD detection operation is controlled; when this bit is read out, the result of the BLD detection (contents of BLD latch) is obtained. Appreciable current is consumed during operation of BLD detection, so keep BLD detection OFF except when necessary. When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 sec. Hence, to obtain the BLD detection result, follow the programming sequence below. 0. 1. 2. 3. 4. 5. Set HLMOD to "1" (only when the CPU system clock is fOSC3 in the S1C60A08) Set BLS to "1" Maintain at 100 sec minimum Set BLS to "0" Read out BLD Set HLMOD to "0" (only when the CPU system clock is fOSC3 in the S1C60A08) However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N08, S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 sec for the BLS = "1" with the software. 4.14.5 Programming notes (1) It takes 100 sec from the time the BLD circuit goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: When the CPU system clock is fOSC1 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 1 instruction has passed. 2. When detection is done at BLS After writing "1" on BLS, write "0" after at least 100 sec has lapsed (possible with the next instruction) and then read the BLD. When the CPU system clock is fOSC3 (in case of S1C60A08 only) 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 0.6 second has passed. (HLMOD holds "1" for at least 0.6 second) 2. When detection is done at BLS Before writing "1" on BLS, write "1" on HLMOD first; after at least 100 sec has lapsed after writing "1" on BLS, write "0" on BLS and then read the BLD. (2) BLS resides in the same bit at the same address as BLD1, and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be used for BLS control. S1C60N08 TECHNICAL HARDWARE EPSON I-71 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit) 4.15 Heavy Load Protection Function and Sub-BLD Circuit This section explains the heavy load protection and sub-BLD circuit. 4.15.1 Heavy load protection function Note that the heavy load protection function on the S1C60L08 is different from the S1C60N08/60A08. (1) In case of S1C60L08 The S1C60L08 has the heavy load protection function for when the battery load becomes heavy and the source voltage drops, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. In this mode, operation with a lower voltage than normal is possible. The normal mode changes to the heavy load protection mode in the following two cases: When the software changes the mode to the heavy load protection mode (HLMOD = "1") When source voltage drop (BLD0 = "1") in the sub-BLD circuit is detected, the mode will automatically shift to the heavy load protection mode until the source voltage is recovered (BLD0 = "0") The sub-BLD circuit, a BLD circuit dedicated to 2.4 V/1.2 V detection, operates in synchronize with the BLD circuit. It is the S1C60L08's battery life detection circuit controlling the heavy load protection function so that operation is assured even when the source voltage drops. Based on the workings of the sub-BLD circuit and the heavy load protection function, the S1C60L08 realizes operation at 0.9 V source voltage. See the electrical characteristics for the precisions of voltage detection by this sub-BLD circuit. Figure 4.15.1.1 shows the configuration of the heavy load protection function and the sub-BLD circuit. Voltage regulator Sub-BLD circuit VS1 VL2 Vss Address 2E6H HLMOD BLD0 Vss BLS Data bus Sub-BLD sampling control BLD1 Fig. 4.15.1.1 Configuration of sub-BLD circuit In the heavy load protection mode, the internally regulated voltage is generated by the liquid crystal driver source output VL2 so as to operate the internal circuit. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. I-72 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit) (2) In case of S1C60N08/60A08 The S1C60N08/60A08 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights. The state where the heavy load protection function is in effect is called the heavy load protection mode. Compared with the normal operation mode, this mode can reduce the output voltage variation of the constant voltage/booster voltage circuit of the LCD system. The normal mode changes to the heavy load protection mode in the following case: * When the software changes the mode to the heavy load protection mode (HLMOD = "1") The heavy load protection mode switches the constant voltage circuit of the LCD system to the highstability mode from the low current consumption mode. Consequently, more current is consumed in the heavy load protection mode than in the normal mode. Unless it is necessary, be careful not to set the heavy load protection mode with the software. 4.15.2 Operation of sub-BLD circuit Software control of the sub-BLD circuit is virtually the same as for the BLD circuit, except that the evaluation voltage cannot be set by programming. Just as for the BLD circuit, HLMOD or BLS control the detection timing of the sub-BLD circuit and the timing for writing the detection data to the sub-BLD latch. However, for the S1C60L08, even if the subBLD circuit detects a drop in source voltage (1.2 V or below) and invokes the heavy load protection mode, this will be the same as when the software invokes the heavy load protection mode, in that the BLD circuit and sub-BLD circuit will be sampled in timing synchronized to the 2 Hz output from the prescaler. If the sub-BLD circuit detects a voltage drop and enters the heavy load protection mode, it will return to the normal mode once the source voltage recovers and the BLD circuit judges that the source voltage is 1.2 V or more. For the S1C60N08/60A08, when the sub-BLD circuit detects a drop in source voltage (2.4 V or below) and the detection data is written to the sub-BLD latch, the BLD circuit and sub-BLD circuit will be sampled in timing synchronized to the 2 Hz output from the prescaler. Once the source voltage recovers and the BLD circuit judges that the source voltage is 2.4 V or more, the BLD circuit and sub-BLD circuit won't be sampled in timing synchronized to the 2 Hz output from the prescaler. S1C60N08 TECHNICAL HARDWARE EPSON I-73 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit) 4.15.3 Control of heavy load protection function and sub-BLD circuit Table 4.15.3.1 shows the control bits and their addresses for the heavy load protection function and subBLD circuit. Table 4.15.3.1 Control bits of heavy load protection function and sub-BLD circuit Address Register Comment Name Init 1 1 0 Heavy load Normal Heavy load protection mode register HLMOD 0 HLMOD BLD0 EISWIT1 EISWIT0 Low Normal Sub-BLD evaluation data BLD0 0 2E6H Enable Mask Interrupt mask register (stopwatch 1 Hz) EISWIT1 0 R/W R R/W Enable Mask Interrupt mask register (stopwatch 10 Hz) EISWIT0 0 BLS 0 On Off BLD On/Off BLS BLC2 BLC1 BLC0 BLD1 0 Low Normal BLD evaluation data BLD1 Evaluation voltage setting register 2FFH BLC2 x 5 [BLC2-0] 0 1 2 3 4 5 6 7 W 5 BLC1 x R/W S1C60N08/60A08 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 (V) R S1C60L08 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 (V) x 5 BLC0 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 HLMOD: Heavy load protection mode (2E6H*D3) Sets the IC in heavy load protection mode. When "1" is written : Heavy load protection mode is set When "0" is written : Heavy load protection mode is released Read-out : Valid When HLMOD is set to "1", the IC operating status enters the heavy load protection mode and at the same time the battery life detection of the BLD circuit is controlled (ON/OFF). When HLMOD is set to "1", sampling control is executed for the BLD circuit ON time. There are two types of sampling time, as follows: (1) The time of one instruction cycle immediately after HLMOD = "1" (2) Sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1" The BLD circuit must be made ON with at least 100 sec for the BLD circuit to respond. Hence, when the CPU system clock is fOSC3 in the S1C60A08, the detection result at the timing in (1) above may be invalid or incorrect. When performing BLD detection using the timing in (1), be sure that the CPU system clock is fOSC1. When BLD sampling is done with HLMOD set to "1", the results are written to the BLD latch in the timing as follows: (1) As soon as the time has elapsed for one instruction cycle immediately following HLMOD = "1" (2) Immediately on completion of sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1" Consequently, the BLD latch data is written immediately after HLMOD is set to "1", and at the same time the new detection result is written in 2 Hz cycles. BLD0: Sub-BLD data (2E6H*D2) The voltage detection data in the heavy load protection mode is read out. When "0" is read out : High source voltage upward from about 2.4 V (S1C60N08/60A08)/1.2 V (S1C60L08) When "1" is read out : Low source voltage from about 2.4 V (S1C60N08/60A08)/1.2 V (S1C60L08) or under Writing : Invalid When BLD0 is "1" the CPU enters the heavy load protection mode. In the heavy load protection mode, the detection operation of the BLD circuit and sub-BLD circuit is sampled in 2 Hz cycles, and the respective detection results are written to the BLD latch and sub-BLD latch. I-74 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit) BLS/BLD1: BLD detection/BLD data (2FFH*D3) Controls the BLD operation. When "0" is written : When "1" is written : When "0" is read out : When "1" is read out : BLD detection OFF BLD detection ON Source voltage (VDD-VSS) is higher than BLD set value Source voltage (VDD-VSS) is lower than BLD set value Note that the function of this bit when written is different to when read out. When this bit is written to, ON/OFF of the BLD detection operation is controlled; when this bit is read out, the result of the BLD detection (contents of BLD latch) is obtained. Appreciable current is consumed during operation of BLD detection, so keep BLD detection OFF except when necessary. When BLS is set to "1", BLD detection is executed. As soon as BLS is reset to "0" the detection result is loaded to the BLD latch. To obtain a stable BLD detection result, the BLD circuit must be set to ON with at least 100 sec. Hence, to obtain the BLD detection result, follow the programming sequence below. 0. 1. 2. 3. 4. 5. Set HLMOD to "1" (only when the CPU system clock is fOSC3 in the S1C60A08) Set BLS to "1" Maintain at 100 sec minimum Set BLS to "0" Read out BLD Set HLMOD to "0" (only when the CPU system clock is fOSC3 in the S1C60A08) However, when a crystal oscillation clock (fOSC1) is selected for the CPU system clock in the S1C60N08, S1C60L08, and S1C60A08, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 sec for the BLS = "1" with the software. S1C60N08 TECHNICAL HARDWARE EPSON I-75 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Heavy Load Protection Function and Sub-BLD Circuit) 4.15.4 Programming notes (1) It takes 100 sec from the time the BLD circuit goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: When the CPU system clock is fOSC1 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 1 instruction has passed. 2. When detection is done at BLS After writing "1" on BLS, write "0" after at least 100 sec has lapsed (possible with the next instruction) and then read the BLD. When the CPU system clock is fOSC3 (in case of S1C60A08 only) 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 0.6 second has passed. (HLMOD holds "1" for at least 0.6 second) 2. When detection is done at BLS Before writing "1" on BLS, write "1" on HLMOD first; after at least 100 sec has lapsed after writing "1" on BLS, write "0" on BLS and then read the BLD. (2) BLS resides in the same bit at the same address as BLD1, and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be used for BLS control. (3) Select one of the following software processing to return to the normal mode after a heavy load has been driven in the heavy load protection mode in the S1C60L08. After heavy load drive is completed, return to the normal mode after at least one second has elapsed. After heavy load drive is completed, switch BLS ON and OFF (at least 100 sec is necessary for the ON status) and then return to the normal mode. The S1C60N08/60A08 returns to the normal mode after driving a heavy load without special software processing. (4) If the BLS is set to ON while the heavy load protection mode is in effect, keep the ON time within 10 msec. I-76 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16 Interrupt and HALT The S1C60N08 Series provides the following interrupt settings, each of which is maskable. External interrupt: Internal interrupt: Input interrupt (three) Timer interrupt (three) Stopwatch interrupt (two) Serial interface interrupt (one) To authorize interrupt, the interrupt flag must be set to "1" (EI) and the necessary related interrupt mask registers must be set to "1" (enable). When an interrupt occurs the interrupt flag is automatically reset to "0" (DI), and interrupts after that are inhibited. When a HALT instruction is input the CPU operating clock stops, and the CPU enters the HALT status. The CPU is reactivated from the HALT status when an interrupt request occurs. If reactivation is not caused by an interrupt request, initial reset by the watchdog timer causes reactivates the CPU (when the watchdog timer is enabled). Figure 4.16.1 shows the configuration of the interrupt circuit. Interrupt vector map Table 4.16.1 Interrupt vector map Page 1 Step 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Interrupt vector Initial reset Serial interface interrupt Input port interrupt Serial interface + Input port interrupt Clock timer interrupt Serial interface + Clock timer interrupt Input port + Clock timer interrupt Serial interface + Input port + Clock timer interrupt Stopwatch timer interrupt Serial interface + Stopwatch timer interrupt Input port + Stopwatch timer interrupt Serial interface + Input port + Stopwatch timer interrupt Clock timer + Stopwatch timer interrupt Serial interface + Clock timer + Stopwatch timer interrupt Input port + Clock timer + Stopwatch timer interrupt All interrupts The interrupt service routine start address should be written to each interrupt vector address. S1C60N08 TECHNICAL HARDWARE EPSON I-77 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) SWIT1 EISWIT1 SWIT0 EISWIT0 Interrupt vector TI2 ETI2 (MSB) TI8 Program counter (four low-order bits) ETI8 TI32 ETI32 (LSB) K00 KCP00 EIK00 INT (interrupt request) K01 KCP01 Interrupt flag EIK01 IK0 K02 KCP02 EIK02 K03 KCP03 EIK03 K10 KCP10 IK1 EIK10 Interrupt factor flag K20 EIK20 K21 Interrupt mask register EIK21 K22 IK2 Input comparison register EIK22 K23 EIK23 ISIO EISIO Fig. 4.16.1 Configuration of interrupt circuit I-78 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16.1 Interrupt factors Table 4.16.1.1 shows the factors for generating interrupt requests. The interrupt flags are set to "1" depending on the corresponding interrupt factors. The CPU operation is interrupted when any of the conditions below set an interrupt factor flag to "1". * The corresponding mask register is "1" (enabled) * The interrupt flag is "1" (EI) The interrupt factor flag is a read-only register, but can be reset to "0" when the register data is read out. At initial reset, the interrupt factor flags are reset to "0". Note: Read the interrupt factor flags only in the DI status (interrupt flag = "0"). A malfunction could result from read-out during the EI status (interrupt flag = "1"). Table 4.16.1.1 Interrupt factors Interrupt factor Clock timer 2 Hz falling edge Clock timer 8 Hz falling edge Clock timer 32 Hz falling edge Stopwatch timer 1 Hz falling edge Stopwatch timer 10 Hz falling edge Serial interface When 8-bit data input/output has completed Input (K00-K03) port rising/falling edge Input (K10) port rising/falling edge Input (K20-K23) port rising edge Interrupt factor flag TI2 (2E9H*D2) TI8 (2E9H*D1) TI32 (2E9H*D0) SWIT1 (2EAH*D1) SWIT0 (2EAH*D0) ISIO (2F3H*D0) IK0 IK1 IK2 (2EAH*D2) (2EAH*D3) (2F3H*D1) 4.16.2 Specific masks and factor flags for interrupt The interrupt factor flags can be masked by the corresponding interrupt mask registers. The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them. At initial reset, the interrupt mask register is set to "0". Table 4.16.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags. Table 4.16.2.1 Interrupt mask registers and interrupt factor flags Interrupt mask register ETI2 (2E8H*D2) ETI8 (2E8H*D1) ETI32 (2E8H*D0) EISWIT1 (2E6H*D1) EISWIT0 (2E6H*D0) EISIO (2F2H*D0) EIK03* (2E5H*D3) EIK02* (2E5H*D2) EIK01* (2E5H*D1) EIK00* (2E5H*D0) EIK10* (2E7H*D2) EIK23* (2F5H*D3) EIK22* (2F5H*D2) EIK21* (2F5H*D1) EIK20* (2F5H*D0) Interrupt factor flag TI2 (2E9H*D2) TI8 (2E9H*D1) TI32 (2E9H*D0) SWIT1 (2EAH*D1) SWIT0 (2EAH*D0) ISIO (2F3H*D0) IK0 (2EAH*D2) IK1 IK2 (2EAH*D3) (2F3H*D1) There is an interrupt mask register for each pin of the input ports. S1C60N08 TECHNICAL HARDWARE EPSON I-79 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16.3 Interrupt vectors When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is terminated, the interrupt processing is executed in the following order. The address data (value of program counter) of the program to be executed next is saved in the stack area (RAM). The interrupt request causes the value of the interrupt vector (page 1, 01H-0FH) to be set in the program counter. The program at the specified address is executed (execution of interrupt processing routine by software). Table 4.16.3.1 shows the correspondence of interrupt requests and interrupt vectors. Note: The processing in and above take 12 cycles of the CPU system clock. Table 4.16.3.1 Interrupt request and interrupt vectors PC Value Interrupt request PCS3 1 Stopwatch timer interrupt 0 PCS2 1 Clock timer interrupt 0 PCS1 1 Input port interrupt 0 PCS0 1 Serial interface interrupt 0 Enabled Masked Enabled Masked Enabled Masked Enabled Masked The four low-order bits of the program counter are indirectly addressed through the interrupt request. I-80 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.16.4 Control of interrupt and HALT Table 4.16.4.1 shows the interrupt control bits and their addresses. Table 4.16.4.1 Interrupt control bits Address Register Comment Name Init 1 1 0 KCP03 0 KCP03 KCP02 KCP01 KCP00 KCP02 0 2E4H Input comparison register (K00-K03) KCP01 0 R/W KCP00 0 EIK03 0 Enable Mask EIK03 EIK02 EIK01 EIK00 EIK02 0 Enable Mask 2E5H Interrupt mask register (K00-K03) EIK01 0 Enable Mask R/W EIK00 0 Enable Mask HLMOD Heavy load Normal Heavy load protection mode register 0 HLMOD BLD0 EISWIT1 EISWIT0 Low Normal Sub-BLD evaluation data BLD0 0 2E6H Enable Mask Interrupt mask register (stopwatch 1 Hz) EISWIT1 0 R/W R R/W Enable Mask Interrupt mask register (stopwatch 10 Hz) EISWIT0 0 SCTRG3 Trigger - Serial I/F clock trigger - SCTRG EIK10 KCP10 K10 EIK10 Enable Mask Interrupt mask register (K10) 0 2E7H KCP10 Input comparison register (K10) 0 W R/W R Low Input port data (K10) K10 - 2 High CSDC 0 Static Dynamic LCD drive switch CSDC ETI2 ETI8 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 SCS1 SCS0 SE2 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 2F2H SE2 Serial I/F clock edge selection 0 R/W EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 - 2 Unused - - 0 0 IK2 ISIO 0 3 - 2 Unused - - 2F3H IK2 4 0 Interrupt factor flag (K20-K23) Yes No R ISIO 4 0 Interrupt factor flag (serial I/F) Yes No EIK23 0 Enable Mask EIK23 EIK22 EIK21 EIK20 EIK22 0 Enable Mask 2F5H Interrupt mask register (K20-K23) EIK21 0 Enable Mask R/W EIK20 0 Enable Mask 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 S1C60N08 TECHNICAL HARDWARE EPSON I-81 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) ETI32, ETI8, ETI2: Interrupt mask registers (2E8H*D0-D2) TI32, TI8, TI2: Interrupt factor flags (2E9H*D0-D2) See Section 4.9, "Clock Timer". EISWIT0, EISWIT1: Interrupt mask registers (2E6H*D0-D1) SWIT0, SWIT1: Interrupt factor flags (2EAH*D0-D1) See Section 4.10, "Stopwatch Timer". EISIO: Interrupt mask register (2F2H*D0) ISIO: Interrupt factor flag (2F3H*D0) See Section 4.7, "Serial Interface". KCP00-KCP03: Input comparison registers (2E4H) EIK00-EIK03: Interrupt mask registers (2E5H) IK0: Interrupt factor flag (2EAH*D2) See Section 4.4, "Input Ports". KCP10: Input comparison register (2E7H*D1) EIK10: Interrupt mask register (2E7H*D2) IK1: Interrupt factor flag (2EAH*D3) See Section 4.4, "Input Ports". EIK20-EIK23: Interrupt mask registers (2F5H) IK2: Interrupt factor flag (2F3H*D1) See Section 4.4, "Input Ports". 4.16.5 Programming notes (1) When the interrupt mask register (EIK) is set to "0", the interrupt factor flag (IK) of the input port cannot be set even though the terminal status of the input port has changed. (2) The interrupt factor flags of the clock timer, stopwatch timer and serial interface (TI, SWIT, ISIO) are set when the timing condition is established, even if the interrupt mask registers (ETI, EISWIT, EISIO) are set to "0". (3) Read out the interrupt factor flags only in the DI status (interrupt flag = "0"). If read-out is performed in the EI status (interrupt flag = "1") a malfunction will result. (4) Writing to the interrupt mask register only in the DI status (interrupt flag = "0"). Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause mulfunction. I-82 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES CHAPTER 5 SUMMARY OF NOTES 5.1 Notes for Low Current Consumption The S1C60N08 Series contains control registers for each of the circuits so that current consumption can be lowered. These control registers lower the current consumption through programs that operate the circuits at the minimum levels. The following text explains the circuits that can control operation and their control registers. Refer to these when putting programs together. Table 5.1.1 Circuits and control register Circuit (and item) Control register Order of consumed current CPU CPU operating frequency (S1C60A08) Heavy load protection mode BLD circuit Analog comparator HALT instruction CLKCHG, OSCC HLMOD HLMOD, BLS AMPON See Electrical Characteristics (Chapter 7) See Electrical Characteristics (Chapter 7) See Electrical Characteristics (Chapter 7) Several tens A Several tens A Below are the circuit statuses at initial reset. CPU: CPU operating frequency: Operating status Low speed side (CLKCHG = "0"), OSC3 oscillation circuit stop status (OSCC = "0") Heavy load protection mode: Normal operating mode (HLMOD = "0") BLD circuit: OFF status (HLMOD = "0", BLS = "0") Analog comparator: OFF status (AMPON = "0") Also, be careful about panel selection because the current consumption can differ by the order of several A on account of the LCD panel characteristics. S1C60N08 TECHNICAL HARDWARE EPSON I-83 CHAPTER 5: SUMMARY OF NOTES 5.2 Summary of Notes by Function Here, the cautionary notes are summed up by function category. Keep these notes well in mind when programming. Memory Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. Watchdog timer When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0-WD2) cannot be used for timer applications. Oscillation circuit and prescaler (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. (3) To operate the clock timer and stopwatch timer accurately, select the prescaler of the OSC1 to match the crystal oscillator used. Input port (1) When input ports are changed from high to low by pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 msec. (2) When "Use" is selected with the noise rejector mask option, a maximum delay of 1 msec occurs from time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be set after read-out, so that it will not be reset. (3) Input interrupt programing related precautions Port K input Active status Active status Input comparison register Falling edge interrupt Rising edge interrupt Mask register Factor flag set Not set Factor flag set When the content of the mask register is rewritten while the port K input is in the active status, the input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. Fig. 5.2.1 Input interrupt timing I-84 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 5.2.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 5.2.1. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the input comparison register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the input comparison register in the mask register = "0" status. Output port When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes. I/O port (1) When input data are changed from high to low by built-in pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 sec. (2) When the I/O port is set to the output mode and the data register has been read, the terminal data instead of the register data can be read out. Because of this, if a low-impedance load is connected and read-out performed, the value of the register and the read-out result may differ. Serial interface (1) If the bit data of SE2 changes while SCLK is in the master mode, a hazard will be output to the SCLK pin. If this poses a problem for the system, be sure to set the SCLK to the external clock if the bit data of SE2 is to be changed. (2) Be sure that read-out of the interrupt factor flag (ISIO) is done only when the serial port is in the STOP status (SIOF = "0") and the DI status (interrupt flag = "0"). If read-out is performed while the serial data is in the RUN status (during input or output), the data input or output will be suspended and the initial status resumed. Read-out during the EI status (interrupt flag = "1") causes malfunctioning. (3) When using the serial interface in the master mode, the synchronous clock uses the CPU system clock. Accordingly, do not change the system clock (fOSC1 fOSC3) while the serial interface is operating. (4) Perform data writing/reading to data registers SD0-SD7 only while the serial interface is halted (i.e., the synchronous clock is neither being input or output). (5) As a trigger condition, it is required that data writing or reading on data registers SD0-SD7 be performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writing/reading on data registers SD0-SD7.) Supply trigger only once every time the serial interface is placed in the RUN state. Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the trigger. S1C60N08 TECHNICAL HARDWARE EPSON I-85 CHAPTER 5: SUMMARY OF NOTES LCD driver (1) When Page 0 is selected for the display memory, the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the display memory by executing initial processing. (2) When Page 2 is selected for the display memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). Clock timer (1) The prescaler mode must be set correctly to suit the crystal oscillator to be used. (2) When the clock timer has been reset, the interrupt factor flag (TI) may sometimes be set to "1". Consequently, perform flag read-out (reset the flag) as necessary at reset. (3) The input clock of the watchdog timer is the 2 Hz signal of the clock timer, so that the watchdog timer may be counted up at timer reset. Stopwatch timer (1) The prescaler mode must be set correctly so that the stopwatch timer suits the crystal oscillator to be used. (2) If timer data is read out in the RUN status, the timer must be made into the STOP status, and after data is read out the RUN status can be restored. If data is read out when a carry occurs, the data cannot be read correctly. Also, the processing above must be performed within the STOP interval of 976 sec (256 Hz 1/4 cycle). Sound generator A hazard may be observed in the output waveform of the BZ and BZ signals when data of the output registers (R10, R13) and the buzzer frequency selection registers (BZFQ0-BZFQ2) changes. Event counter (1) After the event counter has written data to the EVRUN register, it operates or stops in synchronization with the falling edge of the noise rejector clock or stops. Hence, attention must be paid to the above timing when input signals (input to K02 and K03) are being received. (2) To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result. Analog comparator (1) To reduce current consumption, set the analog comparator to OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 msec for the operation of the analog comparator to stabilize before reading the output data of the analog comparator from AMPDT. Battery life detection (BLD) circuit (1) It takes 100 sec from the time the BLD circuit goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: When the CPU system clock is fOSC1 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 1 instruction has passed. 2. When detection is done at BLS After writing "1" on BLS, write "0" after at least 100 sec has lapsed (possible with the next instruction) and then read the BLD. I-86 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES When the CPU system clock is fOSC3 (in case of S1C60A08 only) 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 0.6 second has passed. (HLMOD holds "1" for at least 0.6 second) 2. When detection is done at BLS Before writing "1" on BLS, write "1" on HLMOD first; after at least 100 sec has lapsed after writing "1" on BLS, write "0" on BLS and then read the BLD. (2) BLS resides in the same bit at the same address as BLD1, and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be used for BLS control. Heavy load protection function and sub-BLD circuit (1) It takes 100 sec from the time the BLD circuit goes ON until a stable result is obtained. For this reason, keep the following software notes in mind: When the CPU system clock is fOSC1 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 1 instruction has passed. 2. When detection is done at BLS After writing "1" on BLS, write "0" after at least 100 sec has lapsed (possible with the next instruction) and then read the BLD. When the CPU system clock is fOSC3 (in case of S1C60A08 only) 1. When detection is done at HLMOD After writing "1" on HLMOD, read the BLD after 0.6 second has passed. (HLMOD holds "1" for at least 0.6 second) 2. When detection is done at BLS Before writing "1" on BLS, write "1" on HLMOD first; after at least 100 sec has lapsed after writing "1" on BLS, write "0" on BLS and then read the BLD. (2) BLS resides in the same bit at the same address as BLD1, and one or the other is selected by write or read operation. This means that arithmetic operations (AND, OR, ADD, SUB and so forth) cannot be used for BLS control. (3) Select one of the following software processing to return to the normal mode after a heavy load has been driven in the heavy load protection mode in the S1C60L08. After heavy load drive is completed, return to the normal mode after at least one second has elapsed. After heavy load drive is completed, switch BLS ON and OFF (at least 100 sec is necessary for the ON status) and then return to the normal mode. The S1C60N08/60A08 returns to the normal mode after driving a heavy load without special software processing. (4) If the BLS is set to ON while the heavy load protection mode is in effect, keep the ON time within 10 msec. S1C60N08 TECHNICAL HARDWARE EPSON I-87 CHAPTER 5: SUMMARY OF NOTES Interrupt and HALT (1) When the interrupt mask register (EIK) is set to "0", the interrupt factor flag (IK) of the input port cannot be set even though the terminal status of the input port has changed. (2) The interrupt factor flags of the clock timer, stopwatch timer and serial interface (TI, SWIT, ISIO) are set when the timing condition is established, even if the interrupt mask registers (ETI, EISWIT, EISIO) are set to "0". (3) Read out the interrupt factor flags only in the DI status (interrupt flag = "0"). If read-out is performed in the EI status (interrupt flag = "1") a malfunction will result. (4) Writing to the interrupt mask register only in the DI status (interrupt flag = "0"). Writing to the interrupt mask register while in the EI status (interrupt flag = "1") may cause mulfunction. I-88 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 5: SUMMARY OF NOTES 5.3 Precautions on Mounting <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when using a crystal oscillator, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC1, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VDD pattern as large as possible at circumscription of the OSC1/OSC3 and OSC2/OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VDD pattern for any purpose other than the oscillation system. Sample VDD pattern OSC2 OSC1 VDD In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1/OSC3 and VSS, please keep enough distance between OSC1/OSC3 and VSS or other signals on the board pattern. <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-down resistor is added to the RESET terminal by mask option, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VS1, VL1, VL2, VL3 terminals, such as a capacitor, should be connected in the shortest line. S1C60N08 TECHNICAL HARDWARE EPSON I-89 CHAPTER 5: SUMMARY OF NOTES <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern OSC2 OSC1 VDD Large current signal line High-speed signal line <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. I-90 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM S1C60N08 and S1C60L08 I/O CA VL1 VL3 VDD P00 : P03 P10 : P13 X'tal S1C60N08 S1C60L08 OSC2 (back of the chip) is VDD.] OSC3 N.C. OSC4 N.C. 3.0 V (S1C60N08) or 1.5 V (S1C60L08) R10 (BZ) X'tal Crystal oscillator Trimmer capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Protection resistor Protection resistor + TEST CP VSS Piezo 32.768 kHz or 38.400 kHz, CI = 35 k 5-25 pF 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 3.3 F 100 100 R13 (BZ) R13 (BZ) R11 (LAMP) R12 (FOUT) RESET Lamp CGX C1 C2 C3 C4 C5 CP RA1 RA2 C5 VS1 AMPM AMPP R00 : R03 CGX OSC1 SIN SOUT SCLK O Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. Please refer to pages I-7 and I-8. VL2 [The potential of the substrate SIO C1 CB R10 (BZ) I COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA1 RA2 Piezo When the piezoelectric buzzer is driven directly Note: The above table is simply an example, and is not guaranteed to work. S1C60N08 TECHNICAL HARDWARE EPSON I-91 CHAPTER 6: BASIC EXTERNAL WIRING DIAGRAM S1C60A08 P00 : P03 P10 : P13 I/O VL2 VL3 VDD CGX X'tal S1C60A08 OSC2 [The potential of the substrate VS1 (back of the chip) is VDD.] C5 CGC OSC3 OSC4 R10 (BZ) R13 (BZ) R11 (LAMP) Lamp 3.0 V CR CDC 1 2 + TEST CP VSS Piezo 1 Ceramic oscillation 2 CR oscillation 32.768 kHz or 38.400 kHz, CI = 35 k 5-25 pF Trimmer capacitor 500 kHz Ceramic oscillator 100 pF Gate capacitor 100 pF Drain capacitor Resistor for CR oscillation 82 k 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 3.3 F Capacitor 100 Protection resistor 100 Protection resistor R13 (BZ) X'tal Crystal oscillator CGX CR CGC CDC RCR C1 C2 C3 C4 C5 CP RA1 RA2 RCR RESET R12 (FOUT) R00 : R03 Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. Please refer to pages I-7 and I-8. OSC1 AMPM AMPP O C1 CA VL1 SIN SOUT SCLK SIO CB R10 (BZ) I COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA2 RA1 Piezo When the piezoelectric buzzer is driven directly Note: The above table is simply an example, and is not guaranteed to work. I-92 EPSON S1C60N08 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS CHAPTER 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Rating S1C60N08 and S1C60A08 (VDD=0V) Item Rated value Unit Symbol Supply voltage -5.0 to 0.5 V VSS Input voltage (1) VI VSS-0.3 to 0.5 V Input voltage (2) VIOSC VS1-0.3 to 0.5 V Permissible total output current 1 IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation 2 PD 250 mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). 2 In case of plastic package. S1C60L08 (VDD=0V) Item Rated value Unit Symbol Supply voltage -2.0 to 0.5 V VSS Input voltage (1) VI VSS-0.3 to 0.5 V Input voltage (2) VIOSC VS1-0.3 to 0.5 V Permissible total output current 1 IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation 2 PD 250 mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). 2 In case of plastic package. 7.2 Recommended Operating Conditions S1C60N08 Item Supply voltage Oscillation frequency Symbol VSS fOSC1 Condition VDD=0V Either one is selected Min. -3.5 - - (Ta=-20 to 70C) Typ. Max. Unit -3.0 -1.8 V 32.768 - kHz 38.400 - kHz Min. -1.7 -1.7 -1.7 - - (Ta=-20 to 70C) Max. Unit Typ. -1.1 V -1.5 -0.9 2 V -1.5 V -1.5 -1.2 kHz 32.768 - kHz 38.400 - Min. -3.5 - - 50 (Ta=-20 to 70C) Typ. Max. Unit -3.0 -2.2 V 32.768 - kHz 38.400 - kHz 500 600 kHz S1C60L08 Item Supply voltage Symbol VSS Oscillation frequency fOSC1 Condition VDD=0V VDD=0V, with software control 1 VDD=0V, when analog comparator is used Either one is selected 1 When switching to heavy load protection mode. (See Section 4.15 for details.) 2 The possibility of LCD panel display differs depending on the characteristics of the LCD panel. S1C60A08 Item Supply voltage Oscillation frequency (1) Symbol VSS fOSC1 VDD=0V Either one is selected Oscillation frequency (2) fOSC3 duty 505% S1C60N08 TECHNICAL HARDWARE Condition EPSON I-93 CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.3 DC Characteristics S1C60N08 and S1C60A08 Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Item Condition Min. Symbol High level input voltage (1) VIH1 K00-03, K10, K20-23, P00-03 0.2*VSS P10-13, SIN High level input voltage (2) VIH2 0.1*VSS SCLK, RESET, TEST Low level input voltage (1) K00-03, K10, K20-23, P00-03 VIL1 VSS P10-13, SIN VIL2 VSS Low level input voltage (2) SCLK, RESET, TEST High level input current (1) IIH1 VIH1=0V K00-03, K10, K20-23, P00-03 0 No pull-down P10-13, SIN, SCLK, AMPP AMPM IIH2 K00-03, K10, K20-23, SIN High level input current (2) VIH2=0V 4 With pull-down SCLK VIH3=0V High level input current (3) 25 IIH3 P00-03, P10-13, RESET, TEST With pull-down Low level input current -0.5 IIL K00-03, K10, K20-23, P00-03 VIL=VSS P10-13, SIN, SCLK, AMPP AMPM, RESET, TEST High level output current (1) IOH1 VOH1=0.1*VSS R10, R11, R13 High level output current (2) IOH2 R00-03, R12, P00-03, P10-13 VOH2=0.1*VSS SOUT, SCLK Low level output current (1) IOL1 6.0 VOL1=0.9*VSS R10, R11, R13 Low level output current (2) IOL2 3.0 VOL2=0.9*VSS R00-03, R12, P00-03, P10-13 SOUT, SCLK Common output current VOH3=-0.05V IOH3 COM0-3 3 IOL3 VOL3=VL3+0.05V Segment output current VOH4=-0.05V IOH4 SEG0-47 (during LCD output) 3 IOL4 VOL4=VL3+0.05V Segment output current VOH5=0.1*VSS IOH5 SEG0-47 (during DC output) 200 VOL5=0.9*VSS IOL5 Typ. Max. 0 Unit V 0 0.8*VSS V V 0.9*VSS 0.5 V A 16 A 100 A 0 A -1.8 -0.9 mA mA mA mA -3 -3 -200 A A A A A A S1C60L08 Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25C, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Item Condition Min. Symbol High level input voltage (1) VIH1 K00-03, K10, K20-23, P00-03 0.2*VSS P10-13, SIN High level input voltage (2) VIH2 SCLK, RESET, TEST 0.1*VSS Low level input voltage (1) VIL1 VSS K00-03, K10, K20-23, P00-03 P10-13, SIN Low level input voltage (2) VIL2 VSS SCLK, RESET, TEST High level input current (1) IIH1 VIH1=0V K00-03, K10, K20-23, P00-03 0 No pull-down P10-13, SIN, SCLK, AMPP AMPM High level input current (2) IIH2 K00-03, K10, K20-23, SIN VIH2=0V 2 With pull-down SCLK High level input current (3) IIH3 VIH3=0V P00-03, P10-13, RESET, TEST 12 With pull-down Low level input current VIL=VSS -0.5 IIL K00-03, K10, K20-23, P00-03 P10-13, SIN, SCLK, AMPP AMPM, RESET, TEST High level output current (1) IOH1 R10, R11, R13 VOH1=0.1*VSS High level output current (2) IOH2 VOH2=0.1*VSS R00-03, R12, P00-03, P10-13 SOUT, SCLK Low level output current (1) IOL1 1400 VOL1=0.9*VSS R10, R11, R13 Low level output current (2) IOL2 700 VOL2=0.9*VSS R00-03, R12, P00-03, P10-13 SOUT, SCLK Common output current IOH3 VOH3=-0.05V COM0-3 3 IOL3 VOL3=VL3+0.05V Segment output current VOH4=-0.05V IOH4 SEG0-47 (during LCD output) 3 IOL4 VOL4=VL3+0.05V Segment output current VOH5=0.1*VSS IOH5 SEG0-47 (during DC output) 100 IOL5 VOL5=0.9*VSS I-94 EPSON Typ. Max. 0 Unit V 0 0.8*VSS V V 0.9*VSS 0.5 V A 10 A 60 A 0 A -300 -150 A A A A -3 -3 -100 A A A A A A S1C60N08 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.4 Analog Circuit Characteristics and Current Consumption S1C60N08 (Normal operating mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Min. Typ. Condition Item Symbol 1/2*VL2 Connect 1 M load resistor between VDD and VL1 LCD drive voltage VL1 (without panel load) - 0.1 -2.10 Connect 1 M load resistor between VDD and VL2 -2.30 VL2 (without panel load) VL3 3/2*VL2 Connect 1 M load resistor between VDD and VL3 (without panel load) - 0.1 -2.20 VB0 BLC="0" -2.35 BLD voltage 1 -2.25 VB1 BLC="1" -2.40 -2.30 VB2 BLC="2" -2.45 -2.35 VB3 BLC="3" -2.50 -2.40 VB4 BLC="4" -2.55 -2.45 VB5 BLC="5" -2.60 -2.50 VB6 BLC="6" -2.65 -2.55 VB7 BLC="7" -2.70 BLD circuit response time tB -2.40 VBS Sub-BLD voltage -2.55 Sub-BLD circuit response time tBS Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 input voltage VIM Inverted input (AMPM) VOF Analog comparator offset voltage Analog comparator tAMP VIP=-1.5V response time VIM=VIP15mV During HALT Without IOP Current consumption 1.0 panel load During operation 2 2.2 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Max. Unit 1/2*VL2 V x0.9 -1.90 V 3/2*VL2 V x0.9 -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 V 100 sec -2.25 V 100 sec VDD-0.9 V 10 mV 3 msec 2.0 4.0 A A S1C60N08 (Heavy load protection mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Min. Typ. Condition Item Symbol 1/2*VL2 Connect 1 M load resistor between VDD and VL1 LCD drive voltage VL1 (without panel load) - 0.1 -2.10 VL2 Connect 1 M load resistor between VDD and VL2 -2.30 (without panel load) VL3 Connect 1 M load resistor between VDD and VL3 3/2*VL2 (without panel load) - 0.1 -2.20 VB0 BLC="0" -2.35 BLD voltage 1 -2.25 VB1 BLC="1" -2.40 -2.30 VB2 BLC="2" -2.45 -2.35 VB3 BLC="3" -2.50 -2.40 VB4 BLC="4" -2.55 -2.45 VB5 BLC="5" -2.60 -2.50 VB6 BLC="6" -2.65 -2.55 VB7 BLC="7" -2.70 BLD circuit response time tB -2.40 VBS Sub-BLD voltage -2.55 Sub-BLD circuit response time tBS Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 input voltage VIM Inverted input (AMPM) VOF Analog comparator offset voltage Analog comparator tAMP VIP=-1.5V response time VIM=VIP15mV During HALT Without IOP Current consumption 10 panel load During operation 2 12 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. S1C60N08 TECHNICAL HARDWARE EPSON Max. Unit 1/2*VL2 V x0.9 V -1.90 3/2*VL2 V x0.9 -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 V 100 sec -2.25 V 100 sec VDD-0.9 V 10 mV 3 msec 20 25 A A I-95 CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C60L08 (Normal operating mode) Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Min. Typ. Condition Item Symbol -1.15 -1.05 Connect 1 M load resistor between VDD and VL1 LCD drive voltage VL1 (without panel load) 2*VL1 Connect 1 M load resistor between VDD and VL2 VL2 - 0.1 (without panel load) 3*VL1 VL3 Connect 1 M load resistor between VDD and VL3 (without panel load) - 0.1 -1.05 VB0 BLC="0" -1.15 BLD voltage 1 -1.10 VB1 BLC="1" -1.20 -1.15 VB2 BLC="2" -1.25 -1.20 VB3 BLC="3" -1.30 -1.25 VB4 BLC="4" -1.35 -1.30 VB5 BLC="5" -1.40 -1.35 VB6 BLC="6" -1.45 -1.40 VB7 BLC="7" -1.50 BLD circuit response time tB -1.20 VBS Sub-BLD voltage -1.30 Sub-BLD circuit response time tBS Analog comparator VIP Non-inverted input (AMPP) VSS+0.3 input voltage VIM Inverted input (AMPM) VOF Analog comparator offset voltage tAMP VIP=-1.1V Analog comparator VIM=VIP30mV response time During HALT Without IOP Current consumption 1.0 panel load During operation 2 2.2 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Max. -0.95 Unit V 2*VL1 V x0.9 3*VL1 V x0.9 -0.95 V -1.00 V -1.05 V -1.10 V -1.15 V -1.20 V -1.25 V -1.30 V 100 sec -1.10 V 100 sec VDD-0.9 V 20 mV 3 msec 2.0 4.0 A A Max. -0.95 Unit V S1C60L08 (Heavy load protection mode) Unless otherwise specified: VDD=0V, VSS=-1.5V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Item Min. Typ. Condition Symbol LCD drive voltage -1.15 -1.05 Connect 1 M load resistor between VDD and VL1 VL1 (without panel load) 2*VL1 VL2 Connect 1 M load resistor between VDD and VL2 - 0.1 (without panel load) 3*VL1 VL3 Connect 1 M load resistor between VDD and VL3 - 0.1 (without panel load) BLD voltage 1 -1.05 -1.15 VB0 BLC="0" -1.10 -1.20 VB1 BLC="1" -1.15 VB2 -1.25 BLC="2" -1.20 VB3 -1.30 BLC="3" -1.25 -1.35 VB4 BLC="4" -1.30 VB5 -1.40 BLC="5" -1.35 VB6 -1.45 BLC="6" -1.40 VB7 -1.50 BLC="7" BLD circuit response time tB -1.20 VBS Sub-BLD voltage -1.30 Sub-BLD circuit response time tBS Analog comparator VIP VSS+0.3 Non-inverted input (AMPP) input voltage VIM Inverted input (AMPM) VOF Analog comparator offset voltage Analog comparator tAMP VIP=-1.1V response time VIM=VIP30mV During HALT Without IOP Current consumption 6.5 panel load During operation 2 8.5 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. I-96 EPSON 2*VL1 V x0.85 3*VL1 V x0.85 -0.95 V -1.00 V -1.05 V -1.10 V -1.15 V -1.20 V -1.25 V -1.30 V 100 sec -1.10 V 100 sec VDD-0.9 V 20 mV 3 msec 10 15 A A S1C60N08 TECHNICAL HARDWARE CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C60A08 (Normal operating mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Min. Typ. Item Symbol Condition -1.15 -1.05 LCD drive voltage Connect 1 M load resistor between VDD and VL1 VL1 (without panel load) Connect 1 M load resistor between VDD and VL2 2*VL1 VL2 - 0.1 (without panel load) 3*VL1 VL3 Connect 1 M load resistor between VDD and VL3 - 0.1 (without panel load) -2.35 -2.20 BLD voltage 1 VB0 BLC="0" -2.40 -2.25 VB1 BLC="1" -2.30 -2.45 VB2 BLC="2" -2.35 VB3 -2.50 BLC="3" -2.55 -2.40 BLC="4" VB4 -2.60 -2.45 VB5 BLC="5" -2.50 -2.65 VB6 BLC="6" VB7 -2.55 -2.70 BLC="7" BLD circuit response time tB -2.40 VBS -2.55 Sub-BLD voltage Sub-BLD circuit response time tBS Analog comparator VIP VSS+0.3 Non-inverted input (AMPP) input voltage VIM Inverted input (AMPM) Analog comparator VOF offset voltage Analog comparator tAMP VIP=-1.5V response time VIM=VIP15mV Current consumption 1.1 IOP During HALT Without 3.0 During operation 2 panel load 50 During operation at 500kHz 2 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Max. -0.95 Unit V 2*VL1 V x0.9 3*VL1 V x0.9 -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 V 100 sec -2.25 V 100 sec VDD-0.9 V 10 mV 3 msec 2.0 5.0 70 A A A Max. -0.95 Unit V S1C60A08 (Heavy load protection mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Item Min. Typ. Symbol Condition LCD drive voltage -1.15 -1.05 VL1 Connect 1 M load resistor between VDD and VL1 (without panel load) Connect 1 M load resistor between VDD and VL2 VL2 2*VL1 (without panel load) - 0.1 VL3 Connect 1 M load resistor between VDD and VL3 3*VL1 (without panel load) - 0.1 VB0 BLC="0" -2.35 BLD voltage 1 -2.20 BLC="1" -2.40 VB1 -2.25 VB2 BLC="2" -2.45 -2.30 BLC="3" -2.50 VB3 -2.35 VB4 BLC="4" -2.55 -2.40 BLC="5" VB5 -2.60 -2.45 BLC="6" -2.65 -2.50 VB6 BLC="7" VB7 -2.70 -2.55 BLD circuit response time tB -2.55 VBS -2.40 Sub-BLD voltage Sub-BLD circuit response time tBS Non-inverted input (AMPP) VSS+0.3 Analog comparator VIP Inverted input (AMPM) input voltage VIM Analog comparator VOF offset voltage Analog comparator tAMP VIP=-1.5V VIM=VIP15mV response time Current consumption IOP 6.5 During HALT Without 8.5 During operation 2 panel load 55 During operation at 500kHz 2 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. S1C60N08 TECHNICAL HARDWARE EPSON 2*VL1 V x0.9 3*VL1 V x0.9 -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 V 100 sec -2.25 V 100 sec VDD-0.9 V 10 mV 3 msec 10 15 75 A A A I-97 CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. S1C60N08 (OSC1 crystal oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Item Condition Symbol Oscillation start voltage tsta5sec (VSS) Vsta Oscillation stop voltage tstp10sec (VSS) Vstp Built-in capacitance (drain) CD Including the parasitic capacitance inside the chip Frequency/voltage deviation f/V VSS=-1.8 to -3.5V Frequency/IC deviation f/IC Frequency adjustment range f/CG CG=5 to 25pF (VSS) Harmonic oscillation start voltage Vhho Between OSC1 and VDD Permitted leak resistance Rleak Min. -1.8 -1.8 Typ. Max. 20 -10 35 5 10 45 -3.5 200 Unit V V pF ppm ppm ppm V M S1C60L08 (OSC1 crystal oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-1.5V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Symbol Condition Item Vsta tsta5sec (VSS) Oscillation start voltage Vstp tstp10sec (VSS) Oscillation stop voltage Including the parasitic capacitance inside the chip Built-in capacitance (drain) CD Frequency/voltage deviation f/V VSS=-1.1 (-0.9)1 to -1.7V f/IC Frequency/IC deviation Frequency adjustment range f/CG CG=5 to 25pF (VSS) Harmonic oscillation start voltage Vhho Permitted leak resistance Rleak Between OSC1 and VDD 1 Parentheses indicate value for operation in heavy load protection mode. Min. -1.1 -1.1 (-0.9)1 Typ. Max. 20 -10 35 5 10 45 -1.7 200 Unit V V pF ppm ppm ppm V M S1C60A08 (OSC1 crystal oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: Q13MC146, CG=25pF, CD=built-in, Ta=25C Item Condition Symbol Oscillation start voltage tsta5sec (VSS) Vsta Oscillation stop voltage tstp10sec (VSS) Vstp Built-in capacitance (drain) CD Including the parasitic capacitance inside the chip Frequency/voltage deviation f/V VSS=-2.2 to -3.5V Frequency/IC deviation f/IC Frequency adjustment range f/CG CG=5 to 25pF (VSS) Harmonic oscillation start voltage Vhho Permitted leak resistance Rleak Between OSC1 and VDD Min. -2.2 -2.2 Typ. Max. 20 -10 35 5 10 45 -3.5 200 Unit V V pF ppm ppm ppm V M S1C60A08 (OSC3 CR oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, RCR=82k, Ta=25C Item Symbol Oscillation frequency dispersion fOSC3 Oscillation start voltage Vsta (VSS) Oscillation start time tsta VSS=-2.2 to -3.5V Oscillation stop voltage Vstp (VSS) Condition Min. -30 -2.2 Typ. 480kHz Max. 30 3 -2.2 Unit % V msec V S1C60A08 (OSC3 ceramic oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, Ceramic oscillator: 500kHz, CGC=CDC=100pF, Ta=25C Item Symbol Condition Oscillation start voltage Vsta (VSS) Oscillation start time VSS=-2.2 to -3.5V tsta Oscillation stop voltage Vstp (VSS) I-98 EPSON Min. -2.2 Typ. Max. 5 -2.2 Unit V msec V S1C60N08 TECHNICAL HARDWARE CHAPTER 8: PACKAGE CHAPTER 8 PACKAGE 8.1 Plastic Package QFP5-100pin (Unit: mm) 25.60.4 200.1 80 51 81 INDEX 31 100 1 30 0.30.1 0.26 2.70.1 0.65 3.4max 19.60.4 140.1 50 0.150.05 0 12 1.5 2.8 QFP15-100pin (Unit: mm) 160.4 140.1 75 51 140.1 160.4 50 76 INDEX 26 100 1.40.1 25 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7max 1 1 S1C60N08 TECHNICAL HARDWARE EPSON I-99 CHAPTER 8: PACKAGE 8.2 Ceramic Package for Test Samples QFP5-100pin (Unit: mm) 26.80.3 20.00.18 80 51 20.90.3 50 14.00.14 81 INDEX 100 31 1 0.35 30 0.2 0.15 2.79max 0.65 0.80.2 QFP15-100pin (Unit: mm) 17.00 0.30 12.00Typ. 100 76 75 25 51 13.97 0.15 1 26 50 0.50Typ. GLASS I-100 0.20 0.38 0.08 0.95 0.08 0.76 0.13 2.54Max. 0.50 EPSON CERAMIC 0.82 0.30 S1C60N08 TECHNICAL HARDWARE CHAPTER 9: PAD LAYOUT CHAPTER 9 PAD LAYOUT 9.1 Diagram of Pad Layout 20 15 10 5 1 95 25 90 30 Y (0, 0) 35 3.73 mm 85 X 80 40 Die No. 75 45 50 55 60 65 70 3.74 mm Chip thickness: 400m Pad opening: 95m S1C60N08 TECHNICAL HARDWARE EPSON I-101 CHAPTER 9: PAD LAYOUT 9.2 Pad Coordinates (Unit: m) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I-102 Pad name AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT SCLK P03 P02 P01 P00 P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 R10 R13 VSS RESET X 1,294 1,164 1,034 904 774 644 514 384 254 124 -7 -137 -267 -397 -527 -657 -787 -917 -1,048 -1,178 -1,308 -1,438 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 Y 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,699 1,686 1,556 1,426 1,296 1,166 1,036 812 682 457 327 No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pad name OSC4 OSC3 VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB COM3 COM2 COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 X -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,704 -1,415 -1,285 -1,155 -1,025 -895 -765 -635 -505 -375 -245 -115 15 145 275 405 535 665 EPSON Y 176 46 -84 -214 -344 -503 -633 -763 -893 -1,022 -1,153 -1,283 -1,413 -1,543 -1,673 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Pad name SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X 795 925 1,055 1,185 1,315 1,445 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 1,704 Y -1,699 -1,699 -1,699 -1,699 -1,699 -1,699 -1,621 -1,465 -1,310 -1,180 -1,050 -920 -790 -660 -530 -400 -270 -140 -10 120 250 380 510 640 770 900 1,030 1,160 1,290 1,420 1,550 1,680 S1C60N08 TECHNICAL HARDWARE II. S1C60R08 Technical Hardware CONTENTS PREFACE This manual describes the hardware specification of the S1C60R08. The S1C60R08 is a ROM emulator MCU for the S1C60N08. The mask ROM in the S1C60R08 has been changed to a programmable RAM that is programmed by the Serial EEPROM connected in outside through the serial I/F circuit. Almost all other circuits are compatible with the S1C60N08, therefore this manual explains only the parts related to the programmable RAM and other differences from the S1C60N08. Furthermore, an exclusive Serial EEPROM should be used for programmable RAM programming. Refer to the following manuals in addition to this manual. For the functions and control of the peripheral circuit: "S1C60N08 Technical Hardware" CONTENTS CHAPTER 1 OVERVIEW ______________________________________________ II-1 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER 2 ROM EMULATOR/ROM EMULATOR PROGRAMMER ________________ II-7 2.1 2.2 2.3 CHAPTER Configuration .............................................................................................. II-1 Features ....................................................................................................... II-1 Block Diagram ............................................................................................ II-2 Pin Layout Diagram ................................................................................... II-3 Pin Description ........................................................................................... II-4 S1C60R08 Option List ................................................................................ II-4 Configuration of ROM Emulator ................................................................ II-7 Configuration of ROM Emulator Programmer .......................................... II-8 Operation .................................................................................................... II-8 3 SUMMARY OF NOTES ______________________________________ II-9 3.1 3.2 3.3 3.4 Target Type for S1C60N08 Series ............................................................... II-9 Mask/Segment Option ................................................................................. II-9 Serial EEPROM .......................................................................................... II-9 Precautions on Mounting ........................................................................... II-9 CHAPTER 4 MEMORY MAP ___________________________________________ II-11 CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM ___________________________ II-15 CHAPTER 6 ELECTRICAL CHARACTERISTICS _______________________________ II-17 6.1 6.2 6.3 6.4 6.5 CHAPTER 7 PACKAGE _______________________________________________ II-22 7.1 7.2 CHAPTER Absolute Maximum Rating ......................................................................... II-17 Recommended Operating Conditions ........................................................ II-17 DC Characteristics .................................................................................... II-18 Analog Circuit Characteristics and Current Consumption ...................... II-19 Oscillation Characteristics ........................................................................ II-21 Plastic Package .......................................................................................... II-22 Ceramic Package for Test Samples ............................................................ II-23 8 PAD LAYOUT ____________________________________________ II-24 8.1 8.2 Diagram of Pad Layout .............................................................................. II-24 Pad Coordinates ......................................................................................... II-25 S1C60R08 TECHNICAL HARDWARE EPSON II-i CHAPTER 1: OVERVIEW CHAPTER 1 OVERVIEW The S1C60R08 is a microcomputer with a CMOS 4-bit core CPU S1C6200C as main component, and a built-in programmable RAM (ROM emulator). The S1C60R08 has almost the same functions as the S1C60N08. The mask ROM in the S1C60N08 has been changed to a ROM emulator that allows the user to rewrite programs using a Serial EEPROM. 1.1 Configuration The S1C60R08 is a ROM emulator model of the S1C60N08 and the S1C60A08. Table 1.1.1 lists the difference between these target models. Table 1.1.1 Model configuration Model Target Supply voltage Oscillation circuit S1C60R08 S1C60N08 S1C60A08 3.0 V 3.0 V OSC1 only OSC1 and OSC3 (Single clock) (Twin clock) Note: The S1C60R08 cannot be use as the S1C60L08. 1.2 Features Table 1.2.1 Features Model Target OSC1 oscillation circuit OSC3 oscillation circuit Instruction set Instruction execution time (differs depending on instruction) (CLK: CPU operation frequency) ROM emulator capacity Serial EEPROM interface RAM capacity Input ports Output ports I/O ports Serial interface LCD driver Time base counter Watchdog timer Event counter Sound generator Analog comparator Battery low detection circuit (BLD) External interrupt Internal interrupt Supply voltage Current CLK= 32.768 kHz consumption (when halted) (Typ. value) CLK= 32.768 kHz (when executed) CLK= 500 kHz (when executed) Form when shipped S1C60R08 TECHNICAL HARDWARE S1C60R08 S1C60N08 S1C60A08 Crystal oscillation circuit 32.768 kHz (Typ.)/38.400 kHz (Typ.) - CR or ceramic oscillation circuit (selected by mask option) 500 kHz (Typ.) 108 types 153 sec, 214 sec, 366 sec (CLK = 32.768 kHz) 130 sec, 182 sec, 313 sec (CLK = 38.400 kHz) - 10 sec, 14 sec, 24 sec (CLK = 500 kHz) 4,096 words x 12 bits Built-in (Microchip 24AA65 two wire bus protocol interface 832 words x 4 bits 9 bits (pull-down resistor can be added by mask option) 8 bits 8 bits 1 port (8-bit clock synchronous system) 48 segments x 4, 3, or 2 commons (selected by mask option) V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in) Two types (timer and stopwatch) Built-in (can be disabled by mask option) Two 8-bit inputs (dial input evaluation or independent) Programmable in 8 sounds (8 frequencies) Digital envelope built-in (can be disabled by mask option) Inverted input x 1, non-inverted input x 1 Dual system (programmable in 8 values and a fixed value) 2.4 V, 2.2-2.55 V Input interrupt: 3 systems Time base counter interrupt: 2 systems Serial interface interrupt: 1 system 3.0 V (1.8-3.5 V) 3.0 V (2.2-3.5 V) 1.0 A 1.1 A 6.5 A 7.5 A - 115 A QFP5-100pin, QFP15-100pin or chip EPSON II-1 CHAPTER 1: OVERVIEW 1.3 Block Diagram SDA SCL Serial EEPROM Interface Error Detecting Circuit System Reset Control ROM Emulator 4,096 words x 12 bits ERROUT OTPRST RESET Core CPU S1C6200C OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Input Port 832 words x 4 bits COM0-3 SEG0-47 VDD VL1 VL2 VL3 CA CB VS1 VSS AMPP AMPM LCD Driver 48 SEG x 4 COM K00-K03, K10 K20-K23 TEST I/O Port P00-P03 P10-P13 Output Port R00-R03 R10-R13 Power Controller Sound Generator SVD Serial I/F Event Counter Timer Comparator Stopwatch SIN SOUT SCLK Fig. 1.3.1 Block diagram II-2 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW 1.4 Pin Layout Diagram QFP5-100pin 80 51 81 50 INDEX 31 100 1 30 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin name SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name SEG0 AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin name P10 R03 R02 R01 R00 R12 R11 R10 R13 VSS RESET OSC4 OSC3 VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin name SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 AMPP No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin name R02 R01 R00 R12 R11 R10 R13 VSS RESET OSC4 OSC3 VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 COM1 COM0 QFP15-100pin 75 51 50 76 INDEX 26 100 1 25 Fig. 1.4.1 Pin layout S1C60R08 TECHNICAL HARDWARE EPSON II-3 CHAPTER 1: OVERVIEW 1.5 Pin Description Table 1.5.1 Pin description Pin name Pin No. I/O Function QFP5-100 QFP15-100 92 85 90 83 (I) Power supply pin (+) VSS (I) Power supply pin (-) VS1 89 87 VL1 95 94 93 92 - - Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. -1.05 V or 1/2*VL2) 93 96, 97 91 94, 95 91 89 I 90 88 87 88 86 85 O I 62-59 58 60-57 56 O I I 57-54 70-67 76-73 55-52 68-65 74-71 I I/O I/O 80-77 83 82 78-75 81 80 O O R13 SIN SOUT 81 84 63 64 79 82 61 62 SCLK AMPP AMPM 66 52 53 64 50 51 O O I O I/O SEG0-47 COM0-3 RESET TEST 51-28, 26-3 2, 1, 100, 99 86 27 49-26, 24-1 100-97 84 25 SCL SDA ERROUT OTPRST 71 72 98 65 69 70 96 63 VDD VL2 VL3 CA, CB OSC1 OSC2 OSC3 OSC4 K00-K03 K10 K20-K23 P00-P03 P10-P13 R00-R03 R10 R11 R12 - LCD drive voltage output pin (2*VL1 or approx. -2.10 V) - - LCD drive voltage output pin (3*VL1 or 3/2*VL2) Boost capacitor connecting pin Crystal oscillation input pin O I I O O I I O I/O O I Crystal oscillation output pin CR or ceramic oscillation input pin * (N.C. for S1C60N08) CR or ceramic oscillation output pin * (N.C. for S1C60N08) Input port pin Input port pin Input port pin I/O port pin I/O port pin Output port pin Output port pin or BZ output pin * Output port pin or SIOF output pin * Output port pin or FOUT output pin * Output port pin or BZ output pin * Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin Analog comparator non-inverted input pin Analog comparator inverted input pin LCD segment output pin or DC output pin * LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *) Initial reset input pin Input pin for test Serial EEPROM clock output pin Serial EEPROM data input/output pin Errout detecting singnal output for download program Cold reset pin for re-start download program from EEPROM Can be selected by mask option 1.6 S1C60R08 Option List Multiple specifications are available in each option item as indicated in the Option List. Refer to the "S1C60N08 Technical Hardware". 1. DEVICE TYPE * DEVICE TYPE ........................................... 1. S1C60N08 (Normal Type) 2. S1C60A08 (Twin Clock Type) * CLOCK TYPE (for Evaluation board) ... 1. 32 kHz 2. 38 kHz 2. OSC3 SYSTEM CLOCK (only for S1C60A08) 1. CR II-4 EPSON 2. Ceramic S1C60R08 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW 3. MULTIPLE KEY ENTRY RESET * COMBINATION .................................. * TIME AUTHORIZE ............................. 1. Not Use 2. Use K00, K01 3. Use K00, K01, K02 4. Use K00, K01, K02, K03 1. Use 2. Not Use 4. WATCHDOG TIMER 1. Use 2. Not Use 5. INPUT INTERRUPT NOISE REJECTOR * K00-K03 ................................................ 1. Use * K10 ......................................................... 1. Use * K20-K23 ................................................ 1. Use 2. Not Use 2. Not Use 2. Not Use 6. INPUT PORT PULL DOWN RESISTOR * K00 * K01 * K02 * K03 * K10 * K20 * K21 * K22 * K23 ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... ......................................................... 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 7. OUTPUT PORT SPECIFICATION (R00-R03) * R00 .......................................................... * R01 .......................................................... * R02 .......................................................... * R03 .......................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 8. R10 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................... 1. DC Output 2. Pch-OpenDrain 2. Buzzer Output 9. R11 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary * OUTPUT TYPE .................................... 1. DC Output 2. Pch-OpenDrain 2. SIO Flag 10.R12 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary 2. Pch-OpenDrain * OUTPUT TYPE .................................... 1. DC Output 2. FOUT 32768 or 38400 [Hz] 3. FOUT 16384 or 19200 [Hz] 4. FOUT 8192 or 9600 [Hz] 5. FOUT 4096 or 4800 [Hz] 6. FOUT 2048 or 2400 [Hz] 7. FOUT 1024 or 1200 [Hz] 8. FOUT 512 or 600 [Hz] 9. FOUT 256 or 300 [Hz] S1C60R08 TECHNICAL HARDWARE EPSON II-5 CHAPTER 1: OVERVIEW 11.R13 SPECIFICATION * OUTPUT SPECIFICATION ............... 1. Complementary 2. Pch-OpenDrain * OUTPUT TYPE .................................... 1. DC Output 2. Buzzer Inverted Output (R13 Control) 3. Buzzer Inverted Output (R10 Control) 12. I/O PORT SPECIFICATION * P00 .......................................................... * P01 .......................................................... * P02 .......................................................... * P03 .......................................................... * P10 .......................................................... * P11 .......................................................... * P12 .......................................................... * P13 .......................................................... 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 13. SIN PULL DOWN RESISTOR 1. With Resistor 2. Gate Direct 1. Complementary 2. Pch-OpenDrain * PULL DOWN RESISTOR ................... 1. With Resistor * OUTPUT SPECIFICATION ............... 1. Complementary * LOGIC ................................................... 1. Positive 2. Gate Direct 2. Pch-OpenDrain 2. Negative 14. SOUT SPECIFICATION 15. SCLK SPECIFICATION 16. SIO DATA PERMUTATION 1. MSB First 2. LSB First 17. EVENT COUNTER NOISE REJECTOR 1. 2048 or 2400 [Hz] 2. 256 or 300 [Hz] 18. LCD SPECIFICATION * BIAS SELECTION S1C60N08 .............................................. S1C60A08 .............................................. 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V * DUTY SELECTION ............................. 1. 1/4 Duty 2. 1/3 Duty 3. 1/2 Duty 19. SEGMENT MEMORY ADDRESS 1. 0 Page (040-06F) 2. 2 Page (240-26F) II-6 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 2: ROM EMULATOR/ROM EMULATOR PROGRAMMER CHAPTER 2 ROM EMULATOR/ ROM EMULATOR PROGRAMMER The S1C60R08 has a built-in ROM emulator, which is constructed by RAM, to emulate mask ROM. The ROM emulator is programmed from outside through the serial interface (programmer) circuit and then its data is read by the CPU. This chapter explain the ROM emulator and the Programmer circuit. 2.1 Configuration of ROM Emulator The built-in ROM emulator is the same structure with the mask ROM built-in S1C60N08. And used for loading the user-program. That has a capacity of 4,096 steps x 12 bits. The program area consists of 16 (015) pages x 256 (00H-FFH) steps. After initial reset, the program beginning address is set to bank 0, page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H-0FH. Bank 0 Step 00H Program start address Page 0 Page 1 Step 01H Page 2 Page 3 Interrupt vector area Step 0FH Step 10H Page 15 Step FFH 12 bits Fig. 2.1.1 ROM emulator configuration The ROM emulator data is downloaded from an external Serial EEPROM through the Programmer circuit. After power on or a HIGH pulse is input to the OTPRST pin, the ROM emulator data is initialized and downloading will be started. S1C60R08 TECHNICAL HARDWARE EPSON II-7 CHAPTER 2: ROM EMULATOR/ROM EMULATOR PROGRAMMER 2.2 Configuration of ROM Emulator Programmer The ROM emulator data is written through the Programmer. The Programmer supports data transmit/ receive communication with Serial EEPROM, interface data error check and system reset signal generation. S1C60R08 OSC1 RESET VDD System reset CPU and peripheral circuit A1 A0 SDA SCL ERROUT ROM Emulator 4,096 x 12 bits A2 Serial EEPROM OTPRST EEPROM Interface Circuit Configuration flag CPU Error Detect Circuit VSS Fig. 2.2.1 ROM emulator Terminals The Programmer uses the following input/output terminals. SCL: Serial EEPROM control clock output terminal SDA: Serial EEPROM data transmit/receive terminal ERROUT: Data check result output terminal OTPRST: Data re-loading start input terminal 2.3 Operation The S1C60R08 has two operation modes, * Programming mode: Load the data from the Serial EEPROM * Normal mode: Work as if the mask ROM type The following describes how to operate the S1C60R08. 1) Make an application software. 2) Convert the software to the Serial EEPROM format with winedg in the S1C60R08 package. 3) Write the program which is converted to the Serial EEPROM format to the Serial EEPROM. 4) Set up the S1C60R08, the Serial EEPROM and the other peripheral components on the user target application. (The example is described in "CHAPTER 5 BASIC EXTERNAL CONNECTION DIAGRAM".) 5) The application power on. 6) The S1C60R08 enters to the Programming mode, and starts data loading from the Serial EEPROM to the built-in ROM emulator automatically. In the loading, internal circuit is kept as system reset condition except the Programmer. And data error checking is done at the same time. 7) If the data error happens, the ERROUT pin goes HIGH level and data loading is terminated. 8) If the data has loaded without any error, the S1C60R08 enters to the Normal mode automatically. Then the CPU read the ROM emulator data as the instruction and start to run as if the mask ROM type. 9) If you want to re-load the data, input a HIGH pulse to the OTPRST pin. Then the S1C60R08 enters to Programming mode and starts re-loading. II-8 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 3: SUMMARY OF NOTES CHAPTER 3 SUMMARY OF NOTES 3.1 Target Type for S1C60N08 Series The S1C60N08 has 3 types (S1C60N08, S1C60A08 and S1C60L08). In these models, the S1C60R08 supports the following 2 types as the ROM emulator model. S1C60N08 VDD = 3.0 V (Typ.), OSC1 S1C60A08 VDD = 3.0 V (Typ.), OSC1/OSC3 Refer the "S1C60N08 Technical Hardware". 3.2 Mask/Segment Option The S1C60R08 can load ROM emulator data. But cannot load the mask option and segment option. Therefore customer must make the function option data and segment option data by the S1C60R08 development tool at first. Then send the data to SEIKO EPSON and order the mask. SEIKO EPSON makes the S1C60R08 with a customized option according to this request. 3.3 Serial EEPROM The external Serial EEPROM is necessary for programming the ROM emulator data, and this component is recommended. Recommended component: AK6010A/12A (AKM) M24C64/32 (SGS-THOMSON) BR24C64 (ROHM) 24AA64 (Microchip) Note: Use larger EEPROM than program memory size. 3.4 Precautions on Mounting <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when using a crystal oscillator, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: (1) Components which are connected to the OSC1, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VDD pattern as large as possible at circumscription of the OSC1/OSC3 and OSC2/OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VDD pattern for any purpose other than the oscillation system. In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1/OSC3 and VSS, please keep enough distance between OSC1/OSC3 and VSS or other signals on the board pattern. S1C60R08 TECHNICAL HARDWARE EPSON Sample VDD pattern OSC2 OSC1 VDD II-9 CHAPTER 3: SUMMARY OF NOTES <Reset Circuit> The power-on reset signal which is input to the RESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-down resistor is added to the RESET terminal by mask option, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the RESET terminal in the shortest line. <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: (1) The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example VDD VDD VSS VSS (3) Components which are connected to the VS1, VL1, VL2, VL3 terminals, such as a capacitor, should be connected in the shortest line. <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern OSC2 OSC1 VDD Large current signal line High-speed signal line <Precautions for Visible Radiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. II-10 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 4: MEMORY MAP CHAPTER 4 MEMORY MAP The data memory of the S1C60R08 Series has an address space of 865 words (913 words when display memory is laid out in Page 2), of which 48 words are allocated to display memory and 33 words, to I/O memory. Figure 4.1 shows the overall memory map for the S1C60R08 Series, and Tables 4.1(a)-(c), the memory maps for the peripheral circuits (I/O space). Address Low 0 1 2 3 4 5 6 7 8 9 A B C D E F Page High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 4 5 6 7 RAM (256 words x 4 bits) 0 8 R/W 9 A B C D E F 0 1 2 3 4 5 6 7 RAM (256 words x 4 bits) 1 8 R/W 9 A B C D E F Address Low 0 Page High 0 1 2 3 4 5 6 2 7 8 9 A B C D E F 0 1 2 3 4 5 6 3 7 8 9 A B C D E F 1 2 3 4 5 6 7 8 9 A B C D E F RAM (64 words x 4 bits) R/W Unused area I/O mamory (see Table 4.1) RAM (256 words x 4 bits) R/W Fig. 4.1 Memory map Address Low 0 Page High 4 5 0 or 2 6 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (48 words x 4 bits) Page 0: R/W, Page 2: W only Fig. 4.2 Display memory map Notes: * The display memory area can be selected from between Page 0 (040H-06FH) and Page 2 (240H-26FH) by mask option. When Page 0 (040H-06FH) is selected, the display memory is assigned in the RAM area. So read/write operation is allowed. When Page 2 (240H-26FH) is selected, the display memory is assigned as a write-only memory. * Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. S1C60R08 TECHNICAL HARDWARE EPSON II-11 CHAPTER 4: MEMORY MAP Table 4.1(a) I/O memory map (2D0H, 2E0H-2ECH) Address Register Comment Name Init 1 1 0 Unused 0 3 - 2 - - 0 0 0 LOF 0 3 - 2 Unused - - 2D0H 0 3 - 2 Unused - - R R/W LOF 1 Normal All off LCD all off control Clock timer data (2 Hz) TM3 0 TM3 TM2 TM1 TM0 Clock timer data (4 Hz) TM2 0 2E0H Clock timer data (8 Hz) TM1 0 R Clock timer data (16 Hz) TM0 0 SWL3 MSB 0 SWL3 SWL2 SWL1 SWL0 SWL2 0 2E1H Stopwatch timer 1/100 sec data (BCD) SWL1 0 R SWL0 LSB 0 SWH3 MSB 0 SWH3 SWH2 SWH1 SWH0 SWH2 0 2E2H Stopwatch timer 1/10 sec data (BCD) SWH1 0 R SWH0 LSB 0 K03 - 2 High Low K03 K02 K01 K00 - 2 High K02 Low 2E3H Input port data (K00-K03) - 2 High K01 Low R - 2 High K00 Low KCP03 0 KCP03 KCP02 KCP01 KCP00 KCP02 0 2E4H Input comparison register (K00-K03) KCP01 0 R/W KCP00 0 EIK03 0 Enable Mask EIK03 EIK02 EIK01 EIK00 EIK02 0 Enable Mask 2E5H Interrupt mask register (K00-K03) EIK01 0 Enable Mask R/W EIK00 0 Enable Mask HLMOD Heavy load Normal Heavy load protection mode register 0 HLMOD BLD0 EISWIT1 EISWIT0 Low Normal Sub-BLD evaluation data BLD0 0 2E6H Enable Mask Interrupt mask register (stopwatch 1 Hz) EISWIT1 0 R/W R R/W Enable Mask Interrupt mask register (stopwatch 10 Hz) EISWIT0 0 SCTRG3 Trigger - Serial I/F clock trigger - SCTRG EIK10 KCP10 K10 EIK10 Enable Mask Interrupt mask register (K10) 0 2E7H KCP10 Input comparison register (K10) 0 W R/W R Low Input port data (K10) K10 - 2 High CSDC 0 Static Dynamic LCD drive switch CSDC ETI2 ETI8 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 - 2 Unused - - 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00-K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No R03 0 High Low Output port (R03) R03 R02 R01 R00 R02 0 High Low Output port (R02) 2EBH R01 0 High Low Output port (R01) R/W R00 0 High Low Output port (R00) R13 0 High/On Low/Off Output port (R13)/BZ output control R11 R13 R12 R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control SIOF 2ECH R11 0 High Low Output port (R11, LAMP) R/W SIOF 0 Run Stop Output port (SIOF) R/W R/W R R10 0 High/On Low/Off Output port (R10)/BZ output control 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read II-12 D3 D2 D1 D0 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 4: MEMORY MAP Table 4.1(b) I/O memory map (2EDH-2FAH) Address Register D3 D2 D1 P03 P02 P01 2EDH R/W TMRST SWRUN SWRST 2EEH W R/W W WDRST WD2 WD1 2EFH W R SD3 SD2 SD1 2F0H R/W SD7 SD6 SD5 2F1H R/W SCS1 SCS0 SE2 2F2H R/W 0 0 IK2 2F3H R K23 K22 K21 2F4H R EIK23 EIK22 EIK21 2F5H R/W BZFQ2 BZFQ1 BZFQ0 2F6H R/W ENVON ENVRT AMPDT 2F7H R/W EV03 R EV02 EV01 2F8H R EV07 EV06 EV05 2F9H R EV13 EV12 EV11 2FAH R 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 P03 - 2 High Low P00 - 2 High I/O port data (P00-P03) P02 Low - 2 High Output latch is reset at initial reset P01 Low - 2 High P00 Low TMRST3 Reset Reset Clock timer reset - IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop SWRST3 Reset Reset Stopwatch timer reset - R/W IOC0 0 Output Input I/O control register 0 (P00-P03) WDRST3 Reset Reset Watchdog timer reset - WD0 WD2 Timer data (watchdog timer) 1/4 Hz 0 WD1 Timer data (watchdog timer) 1/2 Hz 0 WD0 Timer data (watchdog timer) 1 Hz 0 SD3 x 5 SD0 x 5 SD2 Serial I/F data register (low-order 4 bits) x 5 SD1 x 5 SD0 SD7 x 5 SD4 x 5 SD6 Serial I/F data register (high-order 4 bits) x 5 SD5 x 5 SD4 [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 SE2 Serial I/F clock edge selection 0 EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 - 2 Unused - - ISIO 0 3 - 2 Unused - - IK2 4 0 Interrupt factor flag (K20-K23) Yes No ISIO 4 0 Interrupt factor flag (serial I/F) Yes No K23 - 2 High Low K20 - 2 High K22 Low Input port data (K20-K23) - 2 High K21 Low - 2 High K20 Low EIK23 0 Enable Mask EIK20 EIK22 0 Enable Mask Interrupt mask register (K20-K23) EIK21 0 Enable Mask EIK20 0 Enable Mask 1 2 3 [BZFQ2-0] 0 BZFQ2 0 Buzzer ENVRST Frequency fOSC1/8 fOSC1/10 fOSC1/12 fOSC1/14 BZFQ1 0 frequency 5 6 7 [BZFQ2-0] 4 BZFQ0 0 selection Frequency fOSC1/16 fOSC1/20 fOSC1/24 fOSC1/28 W ENVRST3 Reset Reset - Envelope reset ENVON Envelope On/Off 0 On Off AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register AMPDT 1 +>+ < - Analog comparator data R/W AMPON Analog comparator On/Off 0 On Off EV03 0 EV00 EV02 0 Event counter 0 (low-order 4 bits) EV01 0 EV00 0 EV07 0 EV04 EV06 0 Event counter 0 (high-order 4 bits) EV05 0 EV04 0 EV13 0 EV10 EV12 0 Event counter 1 (low-order 4 bits) EV11 0 EV10 0 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 S1C60R08 TECHNICAL HARDWARE EPSON II-13 CHAPTER 4: MEMORY MAP Table 4.1(c) I/O memory map (2FBH-2FFH) Address Register Comment Name Init 1 1 0 EV17 0 EV17 EV16 EV15 EV14 EV16 0 2FBH Event counter 1 (high-order 4 bits) EV15 0 R EV14 0 EVSEL 0 Separate Phase Event counter mode selection EVSEL ENRUN EV1RST EV0RST EVRUN 0 Run Stop Event counter Run/Stop 2FCH EV1RST3 Reset Reset Event counter 1 reset - R/W W EV0RST3 Reset Reset Event counter 0 reset - P13 - 2 High Low P13 P12 P11 P10 - 2 High I/O port data (P10-P13) P12 Low 2FDH - 2 High Output latch is reset at initial reset P11 Low R/W - 2 High P10 Low PRSM 0 38 kHz 32 kHz OSC1 prescaler selection PRSM CLKCHG OSCC IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch 2FEH OSCC OSC3 oscillation On/Off 0 On Off R/W IOC1 0 Output Input I/O control register (P10-P13) BLS 0 On Off BLD On/Off BLS BLC2 BLC1 BLC0 BLD1 0 Low Normal BLD evaluation data BLD1 Evaluation voltage setting register 2FFH BLC2 x 5 [BLC2-0] 0 1 2 3 4 5 6 7 W 5 BLC1 x R/W S1C60N08/60A08 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 (V) R S1C60L08 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 (V) x 5 BLC0 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read II-14 D3 D2 D1 D0 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM CHAPTER 5 BASIC EXTERNAL WIRING DIAGRAM Target for S1C60N08 VL1 VDD P00 : P03 P10 : P13 X'tal S1C60R08 OSC2 [The potential of the substrate (back of the chip) is VDD.] OSC4 N.C. 3.0 V R10 (BZ) R13 (BZ) ERROUT SDA + TEST CP VSS Piezo NC SCL SDA Crystal oscillator 32.768 kHz or 38.400 kHz Trimmer capacitor 5-25 pF Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 3.3 F Protection resistor 100 Protection resistor 100 Serial EEPROM : See "3.3 Serial EEPROM" (page II-9) R10 (BZ) X'tal CGX C1 C2 C3 C4 C5 CP RA1 RA2 IC1 N.C. R13 (BZ) VSS OSC3 RESET SCL A2 C5 VS1 VCC IC1 A1 CGX OSC1 Lamp A0 Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. Please refer to pages I-7 and I-8. VL3 SIN SOUT SCLK OTPRST AMPM AMPP SIO CA R11 (LAMP) I/O C1 CB VL2 R12 (FOUT) I COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA1 RA2 Piezo When the piezoelectric buzzer is driven directly Note: The above table is simply an example, and is not guaranteed to work. S1C60R08 TECHNICAL HARDWARE EPSON II-15 CHAPTER 5: BASIC EXTERNAL WIRING DIAGRAM Target for S1C60A08 VL3 VDD OSC2 [The potential of the substrate (back of the chip) is VDD.] CGC RCR 3.0 V CR CDC 1 2 R10 (BZ) R13 (BZ) R12 (FOUT) ERROUT RESET + TEST CP VSS Piezo 1 Ceramic oscillation 2 CR oscillation SDA X'tal CGX CR CGC CDC RCR C1 C2 C3 C4 C5 CP RA1 RA2 IC1 Crystal oscillator 32.768 kHz or 38.400 kHz Trimmer capacitor 5-25 pF Ceramic oscillator 500 kHz Gate capacitor 100 pF Drain capacitor 100 pF Resistor for CR oscillation 82 k Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 0.1 F Capacitor 3.3 F Protection resistor 100 Protection resistor 100 Serial EEPROM : See "3.3 Serial EEPROM" (page II-9) R10 (BZ) VSS NC SCL R13 (BZ) A2 C5 OSC3 OSC4 SDA SCL VS1 VCC IC1 A1 CGX X'tal S1C60R08 Lamp A0 Capacitors (C2-C4) are connected. Connection depending on power supply and LCD panel specification. Please refer to pages I-7 and I-8. OSC1 SIN SOUT SCLK OTPRST AMPM AMPP SIO C1 CA VL1 P00 : P03 P10 : P13 I/O CB VL2 R11 (LAMP) I COM3 K00 : K03 K10 K20 : K23 SEG47 COM0 SEG0 LCD panel RA1 RA2 Piezo When the piezoelectric buzzer is driven directly Note: The above table is simply an example, and is not guaranteed to work. II-16 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS CHAPTER 6 ELECTRICAL CHARACTERISTICS 6.1 Absolute Maximum Rating Target for S1C60N08 and S1C60A08 (VDD=0V) Item Rated value Unit Symbol Supply voltage -5.0 to 0.5 V VSS Input voltage (1) VI VSS-0.3 to 0.5 V Input voltage (2) VIOSC VS1-0.3 to 0.5 V Permissible total output current 1 IVSS 10 mA Operating temperature Topr -20 to 70 C Storage temperature Tstg -65 to 150 C Soldering temperature / time Tsol 260C, 10sec (lead section) - Permissible dissipation 2 PD 250 mW 1 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pin (or is drawn in). 2 In case of plastic package. 6.2 Recommended Operating Conditions Target for S1C60N08 Item Supply voltage Oscillation frequency Symbol VSS fOSC1 Condition VDD=0V Either one is selected Min. -3.5 - - (Ta=-20 to 70C) Typ. Max. Unit -3.0 -1.8 V 32.768 - kHz 38.400 - kHz Min. -3.5 - - 50 (Ta=-20 to 70C) Typ. Max. Unit -3.0 -2.2 V 32.768 - kHz 38.400 - kHz 500 600 kHz Target for S1C60A08 Item Supply voltage Oscillation frequency (1) Symbol VSS fOSC1 VDD=0V Either one is selected Oscillation frequency (2) fOSC3 duty 505% S1C60R08 TECHNICAL HARDWARE Condition EPSON II-17 CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.3 DC Characteristics Target for S1C60N08 and S1C60A08 Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Condition Min. Item Symbol K00-03, K10, K20-23, P00-03 0.2*VSS High level input voltage (1) VIH1 P10-13, SIN, SDA SCLK, RESET, TEST, OTPRST 0.1*VSS High level input voltage (2) VIH2 K00-03, K10, K20-23, P00-03 Low level input voltage (1) VIL1 VSS P10-13, SIN, SDA SCLK, RESET, TEST, OTPRST VIL2 VSS Low level input voltage (2) IIH1 VIH1=0V K00-03, K10, K20-23, P00-03 0 High level input current (1) No pull-down P10-13, SIN, SCLK, AMPP AMPM, SDA IIH2 K00-03, K10, K20-23, SIN VIH2=0V 4 High level input current (2) With pull-down SCLK VIH3=0V IIH3 P00-03, P10-13, RESET, TEST 25 High level input current (3) With pull-down OTPRST IIL K00-03, K10, K20-23, P00-03 VIL=VSS -0.5 Low level input current P10-13, SIN, SCLK, AMPP AMPM, RESET, TEST, OTPRST SDA R10, R11, R13 VOH1=0.1*VSS High level output current (1) IOH1 VOH2=0.1*VSS R00-03, R12, P00-03, P10-13 High level output current (2) IOH2 SOUT, SCLK, SDA, ERROUT SCL R10, R11, R13 VOL1=0.9*VSS 6.0 Low level output current (1) IOL1 VOL2=0.9*VSS R00-03, R12, P00-03, P10-13 3.0 Low level output current (2) IOL2 SOUT, SCLK, SDA, ERROUT SCL IOH3 COM0-3 VOH3=-0.05V Common output current IOL3 VOL3=VL3+0.05V 3 VOH4=-0.05V IOH4 SEG0-47 Segment output current IOL4 VOL4=VL3+0.05V 3 (during LCD output) VOH5=0.1*VSS IOH5 SEG0-47 Segment output current IOL5 VOL5=0.9*VSS 200 (during DC output) II-18 EPSON Typ. Max. 0 Unit V 0 0.8*VSS V V 0.9*VSS V 0.5 A 16 A 100 A 0 A -1.8 -0.9 mA mA mA mA -3 -3 -200 A A A A A A S1C60R08 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.4 Analog Circuit Characteristics and Current Consumption Target for S1C60N08 (Normal operating mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Item Symbol Min. Typ. Condition LCD drive voltage VL1 1/2*VL2 Connect 1 M load resistor between VDD and VL1 - 0.1 (without panel load) VL2 -2.30 Connect 1 M load resistor between VDD and VL2 -2.10 (without panel load) 3/2*VL2 VL3 Connect 1 M load resistor between VDD and VL3 (without panel load) - 0.1 BLD voltage 1 BLC="0" -2.35 VB0 -2.20 BLC="1" VB1 -2.40 -2.25 BLC="2" VB2 -2.45 -2.30 BLC="3" -2.50 VB3 -2.35 BLC="4" -2.55 VB4 -2.40 BLC="5" -2.60 VB5 -2.45 BLC="6" -2.65 VB6 -2.50 BLC="7" -2.70 VB7 -2.55 BLD circuit response time tB -2.55 Sub-BLD voltage VBS -2.40 Sub-BLD circuit response time tBS Non-inverted input (AMPP) VSS+0.3 Analog comparator VIP Inverted input (AMPM) input voltage VIM Analog comparator VOF offset voltage Analog comparator tAMP VIP=-1.5V response time VIM=VIP15mV Current consumption 1.0 IOP During HALT Without 6.5 During operation 2 panel load 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Max. Unit 1/2*VL2 V x0.9 V -1.90 3/2*VL2 V x0.9 V -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 100 sec V -2.25 100 sec VDD-0.9 V 10 mV 3 msec 2.0 9.0 A A Target for S1C60N08 (Heavy load protection mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Item Symbol Min. Typ. Condition LCD drive voltage VL1 1/2*VL2 Connect 1 M load resistor between VDD and VL1 (without panel load) - 0.1 Connect 1 M load resistor between VDD and VL2 VL2 -2.30 -2.10 (without panel load) Connect 1 M load resistor between VDD and VL3 VL3 3/2*VL2 (without panel load) - 0.1 BLD voltage 1 BLC="0" -2.35 VB0 -2.20 BLC="1" -2.40 VB1 -2.25 BLC="2" VB2 -2.45 -2.30 BLC="3" -2.50 VB3 -2.35 BLC="4" -2.55 VB4 -2.40 BLC="5" -2.60 VB5 -2.45 BLC="6" -2.65 VB6 -2.50 BLC="7" -2.70 VB7 -2.55 BLD circuit response time tB -2.55 Sub-BLD voltage VBS -2.40 Sub-BLD circuit response time tBS Non-inverted input (AMPP) VSS+0.3 Analog comparator VIP Inverted input (AMPM) input voltage VIM Analog comparator VOF offset voltage Analog comparator tAMP VIP=-1.5V response time VIM=VIP15mV Current consumption 6.5 IOP During HALT Without 11.5 During operation 2 panel load 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. S1C60R08 TECHNICAL HARDWARE EPSON Max. Unit 1/2*VL2 V x0.9 V -1.90 3/2*VL2 V x0.9 V -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 100 sec V -2.25 100 sec VDD-0.9 V 10 mV 3 msec 10 20 A A II-19 CHAPTER 6: ELECTRICAL CHARACTERISTICS Target for S1C60A08 (Normal operating mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Item Symbol Min. Typ. Condition LCD drive voltage VL1 -1.15 -1.05 Connect 1 M load resistor between VDD and VL1 (without panel load) Connect 1 M load resistor between VDD and VL2 VL2 2*VL1 (without panel load) - 0.1 Connect 1 M load resistor between VDD and VL3 3*VL1 VL3 (without panel load) - 0.1 BLD voltage 1 BLC="0" -2.35 VB0 -2.20 BLC="1" -2.40 VB1 -2.25 BLC="2" -2.45 VB2 -2.30 BLC="3" -2.50 VB3 -2.35 BLC="4" -2.55 VB4 -2.40 BLC="5" -2.60 VB5 -2.45 BLC="6" -2.65 VB6 -2.50 BLC="7" -2.70 VB7 -2.55 BLD circuit response time tB -2.55 Sub-BLD voltage VBS -2.40 Sub-BLD circuit response time tBS Non-inverted input (AMPP) VSS+0.3 Analog comparator VIP Inverted input (AMPM) input voltage VIM Analog comparator VOF offset voltage Analog comparator tAMP VIP=-1.5V response time VIM=VIP15mV Current consumption 1.1 During HALT Without IOP 7.5 During operation 2 panel load 115 During operation at 500kHz 2 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit, sub-BLD circuit and analog comparator are in the OFF status. Max. -0.95 Unit V 2*VL1 V x0.9 V 3*VL1 x0.9 V -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 100 sec V -2.25 100 sec VDD-0.9 V 10 mV 3 msec 2.0 10 150 A A A Max. -0.95 Unit V Target for S1C60A08 (Heavy load protection mode) Unless otherwise specified: VDD=0V, VSS=-3.0V, fOSC1=32.768kHz, Ta=25C, CG=25pF, VS1/VL1-VL3 are internal voltage, C1-C5=0.1F Condition Min. Typ. Item Symbol Connect 1 M load resistor between VDD and VL1 -1.15 -1.05 LCD drive voltage VL1 (without panel load) 2*VL1 VL2 Connect 1 M load resistor between VDD and VL2 - 0.1 (without panel load) VL3 3*VL1 Connect 1 M load resistor between VDD and VL3 - 0.1 (without panel load) -2.20 VB0 -2.35 BLC="0" BLD voltage 1 -2.25 VB1 -2.40 BLC="1" -2.30 VB2 -2.45 BLC="2" -2.35 VB3 -2.50 BLC="3" -2.40 VB4 -2.55 BLC="4" -2.45 VB5 -2.60 BLC="5" -2.50 VB6 -2.65 BLC="6" -2.55 VB7 -2.70 BLC="7" BLD circuit response time tB -2.40 VBS Sub-BLD voltage -2.55 Sub-BLD circuit response time tBS Analog comparator VIP VSS+0.3 Non-inverted input (AMPP) VIM input voltage Inverted input (AMPM) VOF Analog comparator offset voltage tAMP VIP=-1.5V Analog comparator VIM=VIP15mV response time IOP During HALT Without Current consumption 6.5 panel load During operation 2 12.5 During operation at 500kHz 2 120 1 The relationships among VB0-VB7 are VB0>VB1>VB2>...VB5>VB6>VB7. 2 The BLD circuit and sub-BLD circuit are in the ON status (HLMOD="1", BLS="0"). The analog comparator is in the OFF status. II-20 EPSON 2*VL1 V x0.9 3*VL1 V x0.9 -2.05 V -2.10 V -2.15 V -2.20 V -2.25 V -2.30 V -2.35 V -2.40 V 100 sec -2.25 V 100 sec VDD-0.9 V 10 mV 3 msec 10 20 160 A A A S1C60R08 TECHNICAL HARDWARE CHAPTER 6: ELECTRICAL CHARACTERISTICS 6.5 Oscillation Characteristics The oscillation characteristics change depending on the conditions (components used, board pattern, etc.). Use the following characteristics as reference values. Target for S1C60N08 (OSC1 crystal oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: C-002R (CI=35k), CG=25pF, CD=built-in, Ta=25C Item Symbol Condition tsta5sec (VSS) Oscillation start voltage Vsta Oscillation stop voltage Vstp tstp10sec (VSS) Including the parasitic capacitance inside the chip Built-in capacitance (drain) CD Frequency/voltage deviation f/V VSS=-1.8 to -3.5V Frequency/IC deviation f/IC Frequency adjustment range f/CG CG=5 to 25pF (VSS) Harmonic oscillation start voltage Vhho Between OSC1 and VDD Permitted leak resistance Rleak Min. -1.8 -1.8 Typ. Max. 20 -10 35 5 10 45 -3.5 200 Unit V V pF ppm ppm ppm V M Target for S1C60A08 (OSC1 crystal oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, Crystal: C-002R (CI=35k), CG=25pF, CD=built-in, Ta=25C Item Condition Symbol Oscillation start voltage tsta5sec (VSS) Vsta Oscillation stop voltage tstp10sec (VSS) Vstp Built-in capacitance (drain) Including the parasitic capacitance inside the chip CD Frequency/voltage deviation f/V VSS=-2.2 to -3.5V Frequency/IC deviation f/IC Frequency adjustment range f/CG CG=5 to 25pF (VSS) Harmonic oscillation start voltage Vhho Between OSC1 and VDD Permitted leak resistance Rleak Min. -2.2 -2.2 Typ. Max. 20 -10 35 5 10 45 -3.5 200 Unit V V pF ppm ppm ppm V M Target for S1C60A08 (OSC3 CR oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, RCR=82k, Ta=25C Item Symbol Oscillation frequency dispersion fOSC3 (VSS) Oscillation start voltage Vsta Oscillation start time VSS=-2.2 to -3.5V tsta Oscillation stop voltage Vstp (VSS) Condition Min. -30 -2.2 Typ. 480kHz Max. 30 3 -2.2 Unit % V msec V Target for S1C60A08 (OSC3 ceramic oscillation circuit) Unless otherwise specified: VDD=0V, VSS=-3.0V, Ceramic oscillator: 500kHz, CGC=CDC=100pF, Ta=25C Item Symbol Condition Oscillation start voltage Vsta (VSS) Oscillation start time tsta VSS=-2.2 to -3.5V Oscillation stop voltage Vstp (VSS) S1C60R08 TECHNICAL HARDWARE EPSON Min. -2.2 Typ. Max. 5 -2.2 Unit V msec V II-21 CHAPTER 7: PACKAGE CHAPTER 7 PACKAGE 7.1 Plastic Package QFP5-100pin (Unit: mm) 25.60.4 200.1 80 51 81 140.1 INDEX 31 100 1 30 0.30.1 0.26 2.70.1 0.65 3.4max 19.60.4 50 0.150.05 0 12 1.5 2.8 QFP15-100pin (Unit: mm) 160.4 140.1 75 51 140.1 160.4 50 76 INDEX 26 100 1.40.1 25 0.5 +0.1 0.18 -0.05 +0.05 0.125 -0.025 0 10 0.50.2 0.1 1.7max 1 1 Note: The dimentions are subject to change without notice. II-22 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 7: PACKAGE 7.2 Ceramic Package for Test Samples QFP5-100pin (Unit: mm) 26.80.3 20.00.18 80 51 20.90.3 50 14.00.14 81 INDEX 100 31 1 0.35 30 0.2 0.15 2.79max 0.65 0.80.2 QFP15-100pin (Unit: mm) 17.00 0.30 12.00Typ. 100 76 75 25 51 13.97 0.15 1 26 50 0.20 0.50Typ. 0.38 0.08 0.95 0.08 0.76 0.13 2.54Max. 0.50 GLASS CERAMIC 0.82 0.30 Note: The dimentions are subject to change without notice. S1C60R08 TECHNICAL HARDWARE EPSON II-23 CHAPTER 8: PAD LAYOUT CHAPTER 8 PAD LAYOUT 8.1 Diagram of Pad Layout Die No. 25 15 20 10 1 5 100 30 95 35 Y (0, 0) 7.00 mm 90 X 85 40 45 80 50 55 60 65 70 75 8.35 mm Chip thickness: 400 m Pad opening: 95 m II-24 EPSON S1C60R08 TECHNICAL HARDWARE CHAPTER 8: PAD LAYOUT 8.2 Pad Coordinates (Unit: m) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad name AMPP AMPM K23 K22 K21 K20 K10 K03 K02 K01 K00 SIN SOUT OTPRST SCLK P03 P02 P01 P00 SCL SDA P13 P12 P11 P10 R03 R02 R01 R00 R12 R11 R10 R13 VSS X 2,893 2,638 2,382 2,127 1,871 1,616 1,360 1,105 849 594 339 83 -85 -260 -438 -683 -863 -1,064 -1,275 -1,566 -1,821 -2,126 -2,405 -2,685 -2,978 -3,686 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 S1C60R08 TECHNICAL HARDWARE Y 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,330 3,090 2,787 2,657 2,527 2,288 2,064 1,599 1,470 No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pad name REST OSC4 OSC3 VS1 OSC2 OSC1 VDD VL3 VL2 VL1 CA CB ERROUT COM3 COM2 COM1 COM0 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 X -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -4,005 -3,420 -3,116 -2,811 -2,507 -2,203 -1,899 -1,595 -1,290 -986 -682 -378 -74 230 534 838 1,142 1,446 EPSON Y 1,340 733 517 300 -576 -793 -958 -1,174 -1,391 -1,607 -1,824 -2,040 -2,241 -2,429 -2,645 -2,862 -3,088 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad name SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 TEST SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 X 1,751 2,055 2,359 2,663 2,967 3,272 3,661 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 4,005 Y -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,330 -3,049 -2,590 -2,355 -2,119 -1,883 -1,647 -1,411 -1,175 -939 -703 -467 -231 4 240 476 712 948 1,184 1,420 1,656 1,892 2,128 2,364 2,600 2,836 II-25 International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. - HEADQUARTERS - 28F, Beijing Silver Tower 2# North RD DongSanHuan ChaoYang District, Beijing, CHINA Phone: 64106655 Fax: 64107319 1960 E. Grand Avenue EI Segundo, CA 90245, U.S.A. Phone: +1-310-955-5300 Fax: +1-310-955-5400 SHANGHAI BRANCH 4F, Bldg., 27, No. 69, Gui Jing Road Caohejing, Shanghai, CHINA Phone: 21-6485-5552 Fax: 21-6485-0775 - SALES OFFICES West 150 River Oaks Parkway San Jose, CA 95134, U.S.A. Phone: +1-408-922-0200 Fax: +1-408-922-0238 Central 101 Virginia Street, Suite 290 Crystal Lake, IL 60014, U.S.A. Phone: +1-815-455-7630 Fax: +1-815-455-7633 Northeast 301 Edgewater Place, Suite 120 Wakefield, MA 01880, U.S.A. Phone: +1-781-246-3600 Fax: +1-781-246-5443 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 Fax: 02-2712-9164 Telex: 24444 EPSONTB HSINCHU OFFICE Southeast 3010 Royal Blvd. South, Suite 170 Alpharetta, GA 30005, U.S.A. Phone: +1-877-EEA-0020 Fax: +1-770-777-2637 13F-3, No. 295, Kuang-Fu Road, Sec. 2 HsinChu 300 Phone: 03-573-9900 Fax: 03-573-9169 EPSON SINGAPORE PTE., LTD. No. 1 Temasek Avenue, #36-00 Millenia Tower, SINGAPORE 039192 Phone: +65-337-7911 Fax: +65-334-2716 EUROPE EPSON EUROPE ELECTRONICS GmbH SEIKO EPSON CORPORATION KOREA OFFICE - HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110 SALES OFFICE Altstadtstrasse 176 51379 Leverkusen, GERMANY Phone: +49-(0)2171-5045-0 Fax: +49-(0)2171-5045-10 UK BRANCH OFFICE Unit 2.4, Doncastle House, Doncastle Road Bracknell, Berkshire RG12 8PE, ENGLAND Phone: +44-(0)1344-381700 Fax: +44-(0)1344-381701 50F, KLI 63 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: 02-784-6027 Fax: 02-767-3677 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing & Engineering Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5816 Fax: +81-(0)42-587-5624 ED International Marketing Department Europe & U.S.A. FRENCH BRANCH OFFICE 1 Avenue de l' Atlantique, LP 915 Les Conquerants Z.A. de Courtaboeuf 2, F-91976 Les Ulis Cedex, FRANCE Phone: +33-(0)1-64862350 Fax: +33-(0)1-64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Prima Sant Cugat Avda. Alcalde Barrils num. 64-68 E-08190 Sant Cugat del Valles, SPAIN Phone: +34-93-544-2490 Fax: +34-93-544-2491 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5812 Fax: +81-(0)42-587-5564 ED International Marketing Department Asia 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-(0)42-587-5814 Fax: +81-(0)42-587-5110 S1C60N08 / 60R08 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue June, 2000 Printed March, 2001 in Japan M A