eZ80L925148MODG eZ80L92 Module Product Specification PS031802-0514 PRELIMINARY Copyright (c)2014 Zilog(R), Inc. All rights reserved. www.zilog.com eZ80L925148MODG Product Specification ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer (c)2014 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. eZ80, eZ80Acclaim!, and eZ80AcclaimPlus! are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. PS031802-0514 PRELIMINARY eZ80L925148MODG Product Specification iii Revision History Each instance in this document's revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the following table. Revision Level Description Page May 2014 02 Updated Figure 8 schematic diagram to correct PD4 resistor from pull-up to pull-down. 20 Oct 2013 01 Original Zilog issue. All Date PS031802-0514 PRELIMINARY Revision History eZ80L925148MODG eZ80L92 Module Product Specification iv Table of Contents Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi The eZ80L92 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 eZ80L92 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . . . . . . 12 EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 EMAC Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Mounting the Module onto the eZ80(R) Development Platform . . . . . . . . . . . . . . . . 16 ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PS031802-0514 PRELIMINARY Table of Contents eZ80L925148MODG eZ80L92 Module Product Specification v List of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. eZ80L92 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3 eZ80L92 Module Peripheral Bus Connector Pin Configuration . . . . . . . . . . 4 eZ80L92 Module I/O Connector Pin Configuration . . . . . . . . . . . . . . . . . . . 7 Dimension Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Mounting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 eZ80L92 Module Schematic Diagram, #1 of 4: EMAC and Ethernet Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 9. eZ80L92 Module Schematic Diagram, #2 of 4: Memory . . . . . . . . . . . . . . 21 Figure 10. eZ80L92 Module Schematic Diagram, #3 of 4: eZ80L92 Device . . . . . . . 22 Figure 11. eZ80L92 Module Schematic Diagram, #4 of 4: Interfaces . . . . . . . . . . . . . 23 PS031802-0514 PRELIMINARY List of Figures eZ80L925148MODG eZ80L92 Module Product Specification vi List of Tables Table 1. Table 2. Table 3. Table 4. Table 5. PS031802-0514 eZ80L92 Module Peripheral Bus Connector Pin Identification . . . . . . . . . . . 5 eZ80L92 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . . . . 8 Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip Frequency to Wait State Cycle Time Calculation . . . . . . . . . . . . . . . . 13 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PRELIMINARY List of Tables eZ80L925148MODG eZ80L92 Module Product Specification 1 The eZ80L92 Module The eZ80L92 Module is a compact, high-performance Ethernet module specially designed for the rapid development and deployment of embedded systems requiring control and Internet/Intranet connectivity. This low-cost, expandable module is powered by Zilog's power-efficient, high-speed, optimized pipeline architecture eZ80L92 device (eZ80L925048MOD), a member of Zilog's eZ80(R) microprocessor family. The eZ80L92 microprocessor is a high-speed single-cycle instruction-fetch microprocessor, which can operate with a clock speed of 48 MHz. It can operate in Z80-compatible addressing mode (64 KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80L92 Module makes it suitable for a variety of applications, including industrial control, IrDA connectivity, communication, security, automation, point-of-sale terminals, and embedded networking applications. Module Features * * * * * * * * eZ80L92 MPU default factory operating clock frequency at 48 MHz * * * * * Low-cost connection to carrier board via two 2x25pin (2.54mm) headers PS031802-0514 10 Base-T Ethernet Media Access Controller+ PHI with on-board RJ45 connector 512 KB zero-wait-state on-board SRAM 8 MB on-board NOR Flash ROM (90-100 ns) GoldCap backup for Real-Time Clock I/O connector provides 24 general-purpose 5 V-tolerant I/O pinouts On-board connector provides I2C 2-wire SDA/SCL interface On-board connector provides I/O bus for external peripheral connections (IRQ, CS, 24 address, 8 data) Horizontal or vertical mounting onto the eZ80(R) Development Platform Small footprint 64 x 64mm; height is 24 mm 3.3 V power supply Standard operating temperature range: 0C to +70C PRELIMINARY The eZ80L92 Module eZ80L925148MODG eZ80L92 Module Product Specification 2 eZ80L92 Processor Features * * Single-cycle instruction fetch, high-performance, pipelined eZ80(R) CPU core * * * * * * Two UARTs with independent baud rate generators * * Fixed-priority vectored interrupts (both internal and external) and interrupt controller * * * * * * * Six 16-bit Counter/Timers with prescalers and direct input/output drive Low power features including Sleep Mode, Halt Mode, and selective peripheral powerdown control SPI with independent clock rate generator I2C with independent clock rate generator Infrared Data Association (IrDA)-compliant infrared encoder/decoder New DMA-like eZ80(R) instructions for efficient block data transfer Glueless external memory interface with 4 chip selects, individual wait state generators, and an external WAIT input pin: supports Intel- and Motorola-style buses Real-time clock with on-chip 32KHz oscillator, selectable 50/60Hz input, and separate VDD pin for battery backup Watch-Dog Timer 24 bits of general-purpose I/O JTAG and ZDI debug interfaces 100-pin LQFP package 3.0-3.6 V supply voltage with 5V tolerant inputs Standard operating temperature range: 0C to +70C Note: All signals with an overline are active Low. For example, B/W, for which WORD is active Low, and B/W, for which BYTE is active Low. Block Diagram Figure 1 illustrates a block diagram of the eZ80L92 Module. PS031802-0514 PRELIMINARY eZ80L92 Processor Features eZ80L925148MODG eZ80L92 Module Product Specification 3 Gold Cap 32 KHz XTAL PD PC PB Real-Time Clock eZ80 CPU UART Watch-Dog Timer UART 24-Bit GPIO 50-Pin Connector XTAL/Osc. SPI 6 Timer Power-On Reset ZDI/JTAG I2C/SPI RJ45 Bus Controller 10 BaseT Controller w/ Magnetics 50-Pin Connector 8 MB Flash/ROM 128/512 KB SRAM Figure 1. eZ80L92 Module Functional Block Diagram PS031802-0514 PRELIMINARY eZ80L92 Processor Features eZ80L925148MODG eZ80L92 Module Product Specification 4 Pin Description Peripheral Bus Connector Figure 2 illustrates the pin layout of the 50-pin I/O Connector, located at position JP1 on the eZ80L92 Module. Table 6 describes the pins and their functions. JP1 A6 1 A10 3 GND_EXT 5 A8 7 A13 9 A15 11 A18 13 A19 15 A2 17 A11 19 A4 21 A5 23 DIS_ETH 25 A21 27 A22 29 CS0 31 CS2 33 D1 35 D3 37 D5 39 D7 41 MREQ 43 GND_EXT 45 WR BUSACK47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 A0 A3 V3.3_EXT A7 A9 A14 A1 6 GND_EXT A1 A12 A20 A17 DIS_FLASH V3.3_EXT A23 CS1 D0 D2 D4 GND_EXT D6 IOREQ RD INSTRD BUSREQ HEADER 25X2 IDC50 Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration PS031802-0514 PRELIMINARY Pin Description eZ80L925148MODG eZ80L92 Module Product Specification 5 Table 6. eZ80L92 Module Peripheral Bus Connector Pin Identification* Pull Up/Down* Pin # Symbol Signal Direction Comments 1 A6 Bidirectional 2 A0 Bidirectional 3 A10 Bidirectional 4 A3 Bidirectional 5 GND VSS/Ground (0 V). 6 VDD 3.3 V Supply Input Pin. 7 A8 Bidirectional 8 A7 Bidirectional 9 A13 Bidirectional 10 A9 Bidirectional 11 A15 Bidirectional 12 A14 Bidirectional 13 A18 Bidirectional 14 A16 Bidirectional 15 A19 Bidirectional 16 GND 17 A2 Bidirectional 18 A1 Bidirectional 19 A11 Bidirectional 20 A12 Bidirectional 21 A4 Bidirectional 22 A20 Bidirectional 23 A5 Bidirectional 24 A17 Bidirectional 25 DIS_Eth VSS/Ground (0 V). PU 10 K3/4 Input A Low disables on-module EMAC from responding to CS3 on a per-cycle basis. CS3 can be used on the eZ80(R) Development Platform; CMOS Input 3.3 V (5 V tolerant) Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the eZ80(R) CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS031802-0514 PRELIMINARY Peripheral Bus Connector eZ80L925148MODG eZ80L92 Module Product Specification 6 Table 6. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued) Pin # Symbol Pull Up/Down* Signal Direction Comments 26 DIS_Flash PU 10 K3/4 Input 27 A21 28 VDD 29 A22 Bidirectional 30 A23 Bidirectional 31 CS0 Output 32 CS1 Output 33 CS2 Output 34 D0 PU 4k73/4 Bidirectional 35 D1 PU 4k73/4 Bidirectional 36 D2 PU 4k73/4 Bidirectional 37 D3 PU 4k73/4 Bidirectional 38 D4 PU 4k73/4 Bidirectional 39 D5 PU 4k73/4 Bidirectional 40 GND 41 D7 42 D6 Bidirectional 43 MREQ Bidirectional 44 IORQ Bidirectional 45 GND 46 RD Bidirectional 47 WR Bidirectional 48 INSTRD Output 49 BUSACK PU 10K3/4 Output 50 BUSREQ PU 10K3/4 Input A Low disables on-module Flash memory from responding to CS0 on a per-cycle basis. CS0 can be used on the eZ80(R) Development Platform for external memory purposes; CMOS Input 3.3 V (5 V tolerant). Bidirectional 3.3 V supply input pin. VSS/Ground (0 V). PU 4k73/4 Bidirectional VSS/Ground (0 V). Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the eZ80(R) CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS031802-0514 PRELIMINARY Peripheral Bus Connector eZ80L925148MODG eZ80L92 Module Product Specification 7 I/O Connector Figure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position JP2 of the eZ80L92 Module. Table 7 describes the pins and their functions. JP2 PB7 PB5 PB3 PB1 GND_EXT PC6 PC4 PC2 PC0 PD6 PD5 PD3 PD1 TDO GND_EXT TCK RTC_VDD IICSCL IICSDA FLASHWE CS3 RESET V3.3_EXT HALT_SLP V3.3_EXT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 GND_EXT PD4 PD2 PD0 TDI TRIGOUT TMS EZ80CLK GND_EXT DIS_IRDA WAIT GND_EXT NMI HEADER 25X2 IDC50 Figure 3. eZ80L92 Module I/O Connector Pin Configuration PS031802-0514 PRELIMINARY I/O Connector eZ80L925148MODG eZ80L92 Module Product Specification 8 Table 7. eZ80L92 Module I/O Connector Pin Identification* Pull Up/Down Signal Direction Pin # Symbol Comments 1 PB7 Bidirectional 2 PB6 Bidirectional 3 PB5 Bidirectional 4 PB4 Bidirectional 5 PB3 Bidirectional 6 PB2 Bidirectional 7 PB1 Bidirectional 8 PB0 Bidirectional 9 GND 10 PC7 Bidirectional 11 PC6 Bidirectional 12 PC5 Bidirectional 13 PC4 Bidirectional 14 PC3 Bidirectional 15 PC2 Bidirectional 16 PC1 Bidirectional 17 PC0 Bidirectional 18 PD7 Bidirectional 19 PD6 Bidirectional 20 GND 21 PD5 22 PD4 23 PD3 Bidirectional 24 PD2 Bidirectional 25 PD1 Bidirectional 26 PD0 Bidirectional 27 TDO Output JTAG data output pin. 28 TDI/ZDA Input JTAG data input pin. 29 GND VSS/Ground (0 V). VSS/Ground (0 V). Bidirectional PD 4k7 PU 10 K3/4 Bidirectional VSS/Ground (0 V). Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS031802-0514 PRELIMINARY I/O Connector eZ80L925148MODG eZ80L92 Module Product Specification 9 Table 7. eZ80L92 Module I/O Connector Pin Identification* (Continued) Pin # Symbol 30 TRIGOUT 31 TCK/ZCL 32 TMS 33 RTC_VDD 34 EZ80CLK 35 SCL 36 GND 37 SDA 38 GND 39 FlashWE 40 GND 41 CS3 42 DIS_IRDA 43 Pull Up/Down Signal Direction Comments Output Active High trigger event indicator. PU 10 K3/4 Input JTAG clock. High on reset enables ZDI mode; Low on reset enables OCI debug. PU 10 K3/4 Input JTAG Test Mode Select. RTC supply from GoldCap (or external battery). PU 4k7 Output 48 MHz synchronous CPU clock. Bidirectional I2C Bus Clock. VSS/Ground (0 V). PU 4k7 Bidirectional I2C Bus Data. VSS/Ground (0 V). PU 10 K3/4 Input Low enables Write to on-board Flash memory. If this pin is unconnected, the Flash memory is write-protected. VSS/Ground (0 V). Output Used on module for CS8900 EMAC. PU 10 K3/4 Input Low disables on-board IRDA transceiver to use PD0/ PD1 UART pins externally. RESET PU 2k2 Bidirectional Reset output from Module or push-button reset. 44 WAIT PU 2k2 Input Driving the WAIT pin Low forces the eZ80(R) CPU to provide additional clock cycles for an external peripheral or external memory to complete its Read or Write operation. 45 VDD 3.3 V supply input pin. Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS031802-0514 PRELIMINARY I/O Connector eZ80L925148MODG eZ80L92 Module Product Specification 10 Table 7. eZ80L92 Module I/O Connector Pin Identification* (Continued) Pin # Symbol 46 GND 47 HALT_SLP 48 NMI 49 VDD 50 Reserved Pull Up/Down Signal Direction Comments VSS/Ground (0 V). Output, Active A Low on this pin indicates that the eZ80(R) CPU Low enters either Halt or Sleep modes because of execution of either a HALT or SLP instruction. PU 10 K3/4 Schmitt Trigger Input, Active Low The NMI input is a higher priority input than the maskable interrupts. It is always recognized at the end of an instruction, regardless of the state of the interrupt enable control bits. This input includes a Schmitt trigger to allow RC rise times. This external NMI signal is combined with an internal NMI signal generated from the WDT block before being connected to the NMI input of the eZ80(R) CPU. 3.3 V supply input pin. NC Reserved; No Connection. Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0-D7 and A0-A23 should be below 10 pF to satisfy timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register. All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted. PS031802-0514 PRELIMINARY I/O Connector eZ80L925148MODG eZ80L92 Module Product Specification 11 On-Board Component Description Logic-Level I/Os The I/O connector features 24 general-purpose 3.3 V CMOS I/O pins that can be used as outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the General-Purpose I/O pins support dual mode functions (SPI, Timer I/O, UARTs and bit I/O with edge- or level-triggered interrupt functions on each pin). For more information on eZ80L92 dual modes, please refer to the eZ80L92 Product Specification (PS0130). On-Board Battery Backup An on-board 0.1 F capacitor (GoldCap) is used to bridge power outages of 2-4 hours if the power supply to the module is disconnected. The capacitor is charged to 3.1 V during normal operation and is discharged through the on-chip Real Time Clock. The VRTC pin is available on the I/O connector of the module to connect external components to a power supply or to a larger GoldCap. Caution: Do not connect a Lithium Battery to the GoldCap capacitor, because on-board charging circuitry for the capacitor can destroy the lithium battery. Ethernet Media Access Controller The eZ80L92 Module contains a CS8900A EMAC (MAC, PHI, and RAM) which is attached to the data/address bus of the processor. This chip is connected to the processor's CS3 Chip Select, A0-A3, D0-D7, RD, WR, and PD4 pins for interrupt purposes. The connection of the PD6 and PD7 pins for LANACT (i.e., wake-up from sleep) and Sleep is optional and resistor-selectable onboard; see the Ethernet Connectors section that follows to learn more. Ethernet LEDs Two LEDs are embedded in the RJ45 connector. When facing the connector, the GREEN LED is located on the left side, and the YELLOW LED is located on the right. The GREEN LED is active when the module transmits or receives a frame, or when it detects a collision. The YELLOW LED is active when the module receives a valid 10 Base-T link pulse; it is, essentially an indicator of an established link. PS031802-0514 PRELIMINARY On-Board Component Description eZ80L925148MODG eZ80L92 Module Product Specification 12 Ethernet Connectors The eZ80L92 Module is equipped with an RJ45 connector that features integrated magnetics (transformer, common mode chokes, and LEDs). The remaining pins on the on-board RJ45 connector are not connected. Node assignments for the RJ45 Ethernet connector are shown in Table 8. Table 8. Ethernet Connector Pin Assignments Pin Function 1 TX+ 2 TX- 3 RX+ 6 RX- Node assignment, in contrast to hub assignment, means that a straight-through cable (equivalent pin numbers on both sides of the cable are connected to each other) is used to attach the board to an Ethernet hub or switch. To connect the eZ80L92 Module directly to another node (e.g., a personal computer), a crossover cable must be used. The EMAC can be additionally protected by placing a U2 ESD protection array on the module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1 (ST Microelectronics) devices. GPIO Pins for Enabling LAN Activity, Sleep, Interrupt GPIO input bit PD4 serves as an active High interrupt input for the EMAC's INTRQ0 output. GPIO output bit PD7 can be used to enter the EMAC into Sleep Mode. When pulling Sleep (PD7) Low after enabling HWStandbyE and HWSleepE modes, the chip draws lower current, because only the receiver is operating. A zero-Ohm resistor at position R6 on the eZ80L92 Module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector. If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is connected to GPIO input PD6 and can be used in interrupt edge-detection mode to wake up and reinitialize the Ethernet chip. A zero-Ohm resistor at position R3 on the module is required for this function. In this case, the PD6 pin is not available for GPIO on the I/O connector. PS031802-0514 PRELIMINARY Ethernet Media Access Controller eZ80L925148MODG eZ80L92 Module Product Specification 13 EMAC Ports Chip Select CS3 is used for selecting the EMAC via I/O decoding. The I/O base address is user-selectable. The EMAC is connected as an 8- or 16-bit device with 8-word-wide I/O registers: EMAC Wait States The CS8900A EMAC should be operated in Intel bus mode so that the setup and hold times for the I/O access are met. For 48 MHz operation, first set CS3_BMC (I/O address 0xF3h) to 84h (Intel bus mode with four system clock cycles per bus cycle) and then CS3_CTL (I/O Address 0xB3) to 18h (0 wait states for I/O). For a 20.8 ns CPU Clock cycle time, the Read and Write access time is: 2 x 4 x 20.8 ns-16 ns (for capacitive and chip delays) = 150 ns Memory The eZ80L92 Module offers SRAM and Flash memories and the wait states that support memory operations, as described in this section. Wait States To ensure that valid data is read from or written to slower memories, a number of wait states must be inserted into the memory or I/O access operations by the processor. The number of wait states that are required should be added by programming the chip select control registers. To calculate the minimum number of wait states required, refer to Table 9. Table 9. Chip Frequency to Wait State Cycle Time Calculation MHz Cycle Time 12 83.3 ns 20 50.0 ns 24 41.7 ns 36 27.8 ns 40 25.0 ns 48 20.8 ns Static RAM The eZ80L92 Module features 512 KB of fast SRAM. Access speed is typically 12 ns or faster, allowing zero-wait-state operation at 48 MHz. With the CPU at 48 MHz, on-board PS031802-0514 PRELIMINARY Memory eZ80L925148MODG eZ80L92 Module Product Specification 14 SRAM can be accessed with zero wait states in eZ80 mode. CS1_CTL (chip select CS1) can be set to 08h (no wait states). Flash Memory The Flash Boot Loader, application code, and user configuration data are held permanently in NOR Flash memory. A typical application requires eight times more ROM for code than RAM. As an example, for 128 KB on-board SRAM, 1 MB of ROM is required. The eZ80L92 Module allows NOR Flash memories between 4 megabits (512 KB) and 64 megabits (8 MB) to be used. The chips are housed in wide TSOP40 cases. Flash ROM access times are 55-150 ns; typically 90 ns. NOR Flash should be operated in Intel bus mode to satisfy setup and hold times and to prevent bus contention with a Write cycle that could possibly follow. For proper CPU operation at 48 MHz, first set the bus mode control register CS0_BMC (I/O address 0xF0h) to 82h, then set the Chip Select Control register CS0_CTL (I/O address 0xAAh) to 08h. These settings select Intel Bus Mode with two system clocks per bus cycle and zero wait states. Reset Generator The on-board Reset Generator Chip performs reliable Power-On Reset. The chip generates a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V. This reset pulse ensures that the board always starts in a defined condition. The RESET pin on the I/ O connector reflects the status of the RESET line. It is a bidirectional pin for resetting external peripheral components or for resetting the eZ80L92 Module with a low-impedance output (e.g. a 100-Ohm pushbutton). Serial Interface Ports The processor contains two 16550-style UARTs with programmable baud rate generators. UART0 is typically used for console I/O and initial boot code upload or to connect remote peripherals that can be controlled and monitored via Ethernet. UART0 is connected to GPIO PD[0:3] on the I/O connector. There are no RS232-level shifters on the eZ80L92 Module. Note: Do not connect an RS-232 interface without level shifters. UART1 can be used for modem attachment or as a communications port to a host computer, where the embedded Ethernet module emulates an AT-style modem for internet access. UART1 does not offer on-board RS232-level shifters. PS031802-0514 PRELIMINARY Reset Generator eZ80L925148MODG eZ80L92 Module Product Specification 15 Physical Dimensions The size of the eZ80L92 Module PCB is 64 x 64mm. With an RJ45 Ethernet connector, the overall height is 25 mm, as shown in Figure 4. 63.5 mm 16 mm LAN 13.7 mm 8.3 mm max. 1 1 2.54 mm 16.3 mm Top View I/O Connector Bus Connector RJ45 64 mm 55.88 mm Figure 4. Dimension Drawing Figure 5 illustrates a top view of the eZ80L92 Module. PS031802-0514 PRELIMINARY Physical Dimensions eZ80L925148MODG eZ80L92 Module Product Specification 16 Figure 5. Top View Mounting the Module onto the eZ80(R) Development Platform The eZ80L92 Module can be mounted in several positions. Depending on volume and area restrictions, it can be mounted horizontally or vertically with or without components between the connectors on the eZ80(R) Development Platform. See Figure 6 for examples. PS031802-0514 PRELIMINARY Mounting the Module onto the eZ80(R) eZ80L925148MODG eZ80L92 Module Product Specification 17 Low Profile Mounting RJ45 (rear) 63.5 mm 1 64 mm 1 15.3 mm E-NET Module Bus H = 4.5 mm 1.7 mm I/O 8.3 mm Carrier Board Figure 6. Mounting Examples ESD/EMI Protection Caution: The eZ80L92 Module is a component that is intended to be part of a system design for end-user devices. Therefore, the user must exercise caution to use ESD protection on the I/O pins. The EMAC can be additionally protected by placing an ESD protection array on the eZ80L92 Module at position U9. Either use ESDA25B1 from ST Microelectronics or LCDA15C-6 from Semtech. A mounting hole on the board can be used for grounding the shield of the Ethernet RJ45 jack to prevent surge or ESD currents from flowing through the digital circuitry. The RJ45 Ethernet Connector on the eZ80L92 Module contains a transformer and common mode chokes for EMI suppression. Caution: CMOS I/Os are ESD-sensitive and must be handled with care. Handling of the module should be performed in ESD-safe environments (for example with a wrist-wrap attached). When developing applications, the user must provide for proper ESD protection on external, user-accessible I/Os (e.g. suppressor arrays for the I/Os). The components are mounted on a multilayer PCB to provide a stable ground plane for onboard components. The module features several GND pins next to pins with higher switching frequency for short ground returns. If unused, the clock output can be separated PS031802-0514 PRELIMINARY ESD/EMI Protection eZ80L925148MODG eZ80L92 Module Product Specification 18 from the module header by removing a series resistor on the module. Removing the series resistor further reduces electromagnetic emissions. Absolute Maximum Ratings Stresses greater than those listed in Table 10 can cause permanent damage to the device. These ratings are stress ratings only. Operation of the device at any condition outside those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For improved reliability, unused inputs should be tied to one of the supply voltages (VDD or VSS). Table 10. Absolute Maximum Ratings Parameter Min Max Units 0 +70 C Storage temperature -45 +85 C Operating Humidity (RH @ 50C) 25% 90% - 3.3 Standard operating temperature Operating Voltage (5%) V Power Supply The eZ80L92 Module requires a regulated external 3.3 VDC/0.5A power supply. You may use a Low Dropout Regulator (LDO) to get 3.3 V from 5 V or use the following switcher circuit to generate 3.3 V from unregulated 10-28V power supply. Power connections follow these conventional descriptions: Connection Circuit Device Power VCC VDD Ground GND VSS Figure 7 offers two typical power supply examples. PS031802-0514 PRELIMINARY Power Supply eZ80L925148MODG eZ80L92 Module Product Specification 19 Switcher 10-28V 3.3V To Module U1 LM2575S-ADJ 10-28V 1 V IN VIN G N D C2 C1 1000uF 100n 3 FB OVOUT N / O F F 4 2 VDD 3.3V L1 330uH/1A R1 5k6 1% D1 1A/30V R2 3k3 1% 5 GND C3 470uF/6.3V Low ESR GND LDO 5V 3.3V 4-6V U1 LM3940 VCC VI G N D VDD 3.3V VO C3 Low ESR 470uF/6.3V C1 100n GND GND Figure 7. Power Supply Examples PS031802-0514 PRELIMINARY Power Supply eZ80L925148MODG eZ80L92 Module Product Specification Schematic Diagrams Figures 8 through 11 diagram the layout of the eZ80L92 Module. VCC_3v3 VCC_3v3 VCC_3v3 CS8900A 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GND GND R4 4.7K PD4 ETHIRQ A[3:0] LANLED LINKLED/HC0 XTAL2 XTAL1 AVSS AVDD AVSS RES RXDRXD+ AVDD AVSS TXDTXD+ AVSS AVDD DODO+ CICI+ DIDI+ BSTATUS/HC1 SLEEP TEST 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A0 A1 A2 A3 SD9 SD8 MEMW MEMR INTRQ2 INTRQ1 INTRQ0 IOCS16 MEMCS16 INTRQ3 SHBE SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 REFRESH SA12 SA13 SA14 SA15 SA16 DVSS DVDD DVSS SA17 SA18 SA19 IOR IOW AEN (TCK) IOCHRDY SD0 SD1 SD2 SD3 DVDD DVSS SD4 SD5 SD6 SD7 RESET 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SD10 SD11 DVSS DVDD SD12 SD13 SD14 SD15 CSOUT DMACK0 DMARQ0 DMACK1 DMARQ1 DMACK2 DMARQ2 DVSS DVDD DVSS CHIPSEL EEDATAIN EEDATAOUT (TDO) EESK EECS ELCS AVSS R4 is located directly on the JP2 R3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 LANLED LINKLED PD6 Y1 U2 0 ohm 20MHZ RXD+ 1 8 TD+ RXD- 2 7 TD- 3 6 R5 4.99K RXDRXD+ TXDTXD+ 4 5 LCDA..C-6 R6 -SLEEP PD7 0 ohm U1 R7 8.2 TXD+ TD+ C1 8.2 -ETHRD -ETHWR R9 D4 D5 D6 D7 D0 D1 D2 D3 TXD- R8 P1 1 2 560pF TD- 3 6 RXD+ 0 ohm 4 5 R10 100 ohm WAIT- C2 D[7:0] 0.1uF RXD- C3 7 8 0.1uF R1 220 ohm 9 10 VCC_3v3 LANLED LEFT VCC_3v3 C23 C24 C25 C26 C27 C28 0.1F 0.1F 0.1F 0.1F 0.1F R2 220 ohm NC16 NC15 16 15 RD+ RDCTD CRD NC7 NC8 AN1 CT1 AN2 CT2 SHIELD2 SHIELD1 14 13 R11 C29 LINKLED 0.1F 11 12 TD+ TD- RIGHT 0.1F HFJ11-1041ERL-L11 C4 1 MEG 0.001F/2000V Figure 8. eZ80L92 Module Schematic Diagram, #1 of 4: EMAC and Ethernet Connections PS031802-0514 20 eZ80L925148MODG eZ80L92 Module Product Specification U9 A[23:0] 3 4 5 6 7 16 17 18 19 20 26 27 28 29 30 38 39 40 41 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D[7:0] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 D0 D1 D2 D3 D4 D5 D6 D7 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 VCC1 VCC2 37 15 8 RDWR- RDWRCS1- OE WE CE GND1 GND2 9 10 13 14 31 32 35 36 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 1 2 21 22 23 24 25 42 43 44 VCC_3v3 D0 D1 D2 D3 D4 D5 D6 D7 VCC_3v3 11 33 12 34 C21 C22 0.1uF 0.1uF RN1 10 9 8 7 6 5 4 3 2 1 4.7K CY7C1049DV33 U5 FLASH_CSRDWR- F1 G1 A4 10K B4 F6 B3 R25 E2 H2 E3 H3 H4 E4 H5 E5 F2 G2 F3 G3 F4 G5 F5 G6 D0 D1 D2 D3 D4 D5 D6 D7 VCC_3v3 A0 RD- RY/BY 1 3 A3 G4 GND1 GND2 C19 C20 0.1uF 0.1uF H1 H6 14 7 11 1A GND 2A FLASH_CS- 13 1Y VCC 2Y 6 5 4 VCC_3v3 FLASH_WP- 7 1 2 3 FLASH_WE- SN74ALVC32 U7D 12 R27 U6 DIS_FLASH- -ETHWR FLASH_WPVCC_3v3 10K -ETHWR 5 VCC_3v3 CS0- U7B 6 WR- VCC_3v3 R26 SN74ALVC32 4 S29GL064N 10K -ETHRD VCC_3v3 CS3- CE OE WE RST BYTE WP -ETHRD 2 VCC_3v3 VCC U7A 14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15/A-1 SN74ALVC32 VCC_3v3 14 VCC_3v3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 7 E1 D1 C1 A1 B1 D2 C2 A2 B5 A5 C5 D5 B6 A6 C6 D6 E6 B2 C3 D4 D3 C4 14 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 U7C 9 8 74LVC2GU04 10 7 GND SN74ALVC32 Figure 9. eZ80L92 Module Schematic Diagram, #2 of 4: Memory PS031802-0514 21 eZ80L925148MODG eZ80L92 Module Product Specification U8 D[7:0] VCC_3v3 R15 R16 R12 R13 R14 R17 10K 10K 10K 10K 10K 10K D0 D1 D2 D3 D4 D5 D6 D7 35 36 37 38 39 40 41 42 50 WAIT- 53 BUSREQ- 52 NMITMS TCK TDI RESET- ZCL ZDA 62 63 65 SYS_RST- 51 A[23:0] D0 D1 D2 D3 D4 D5 D6 D7 WAIT BUSREQ NMI TMS TCK TDI RESET eZ80L92 R18 4.75K VCC_3v3 C5 86 0.1uF 85 XOUT XIN Y2 VCC_3v3 R19 4.7K 48.000MHZ R22 MAX6328 2 RESET 3 100K C6 VCC GND 1 L1 3.3UH C7 12pF 7 18 33 43 56 67 87 96 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 12pF 8 19 34 44 57 61 84 97 U3 C8 220pF VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VCC_3v3 2 1 RB751V BATT+ 100 ohm 1 0.1F, Super Cap BT1 2 RB751V GND 60 59 58 1 D3 2 RTC_VDD IORQ MREQ RD WR BUSACK CS0 CS1 CS2 CS3 SCL SDA PB7/MOSI PB6/MISO PB5/T5_OUT PB4/T4_OUT PB3/SCK PB2/SS PB1/T1_IN PB0/T0_IN PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 PC2/RTS1 PC1/RXD1 PC0/TXD1 R23 D2 VCC_3v3 VCC_3v3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 Y3 C9 32.768KHZ C10 GND 18pF 18pF RTC_VDD RTC_XOUT RTC_XIN PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0 PD1/RXD0/IR_RXD PD0/TXD0/IR_TXD HALT_SLP PHI INSTRD TDO TRIGOUT 1 2 3 4 5 6 9 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 28 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 45 46 47 48 54 29 30 31 32 IORQMREQRDWRBUSACKCS0CS1CS2CS3- VCC_3v3 R20 4.99K 99 98 95 94 93 92 91 90 89 88 IICSCL IICSDA PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 83 82 81 80 79 78 77 76 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 75 74 73 72 71 70 69 68 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 55 100 49 66 64 R21 4.99K PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 R24 33.2 Place resistor near CPU HALT_SLPEZ80CLK INSTRDTDO TRGOUT VCC_3v3 C11 C12 C13 C14 C15 C16 C17 C18 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Figure 10. eZ80L92 Module Schematic Diagram, #3 of 4: eZ80L92 Device PS031802-0514 22 eZ80L925148MODG eZ80L92 Module Product Specification A[23:0] D[7:0] A[23:0] D[7:0] JP2 JP1 A6 A10 A8 A13 A15 A18 A19 A2 A11 A4 A5 CS0CS2- MREQWRBUSACK- A21 A22 CS0CS2D1 D3 D5 D7 MREQGND WRBUSACK- 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 PB7 PB5 PB3 PB1 A0 A3 VCC_3v3 A7 A9 A14 A16 A1 A12 A20 A17 DIS_FLASHA23 CS1D0 D2 D4 DIS_FLASHCS1- GND D6 IOREQRDINSTRDBUSREQ- PC6 PC4 PC2 PC0 PD6 PD5 PD3 PD1 TDO IORQRDINSTRDBUSREQ- TCK RTC_VDD IICSCL IICSDA FLASH_WECS3RESETHALT_SLP- PB7 PB5 PB3 PB1 PC6 PC4 PC2 PC0 PD6 PD5 PD3 PD1 TD0 GND TCK RTC_VDD IICSCL IICSDA FLASH_WECS3RESETHALT_SLPVCC_3v3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 PD4 PD2 PD0 TDI TRIGOUT TMS EZ80CLK PB6 PB4 PB2 PB0 PC7 PC5 PC3 PC1 PD7 PD4 PD2 PD0 TDI TRGOUT TMS EZ80CLK GND WAITNMI- WAITNMI- 2x25/PIN 2x25/PIN GND GND VCC_3v3 VCC_3v3 Figure 11. eZ80L92 Module Schematic Diagram, #4 of 4: Interfaces PS031802-0514 23 eZ80L925148MODG eZ80L92 Module Product Specification 24 Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog's Technical Support page at http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base or consider participating in the Zilog Forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com. PS031802-0514 PRELIMINARY Customer Support Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ZiLOG: EZ80L925148MODG