eZ80L925148MODG
Copyright ©2014 Zilog®, Inc. All rights reserved.
www.zilog.com
eZ80L92 Module
Product Specification
PS031802-0514
PRELIMINARY
PS031802-0514 PRELIMINARY
eZ80L925148MODG
Product Specification
ii
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal compon ent is a ny comp onent in a life su pport dev ice or s ystem wh ose failu re to pe rform can be reason -
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2014 Zilog, Inc. All rights reserved. Information in this publication co ncerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION , DEV I CES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
eZ80, eZ80Acclaim!, and eZ80AcclaimPlus! are trademarks or registered trademarks of Zilog, Inc. All
other product or service names are the property of their respective owners.
Warning:
PS031802-0514 PRELIMINARY Revision History
eZ80L925148MODG
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edi-
tion. For more details, refer to the corresponding page(s) or appropriate links furnished in
the following table.
Date Revision
Level Description Page
May
2014 02 Updated Figure 8 schematic diagram to correct PD4 resistor from pull-up to
pull-down. 20
Oct
2013 01 Original Zilog issue. All
PS031802-0514 PRELIMINARY Table of Contents
eZ80L925148MODG
eZ80L92 Module Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vi
The eZ80L92 Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
eZ80L92 Processor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Peripheral Bus Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
I/O Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Onboard Component Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic-Level I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Onboard Battery Backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ethernet Media Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ethernet LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ethernet Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt . . . . . . . . . . . . . . . . . . 12
EMAC Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EMAC Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Interface Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mounting the Module onto the eZ80® Development Platform . . . . . . . . . . . . . . . . 16
ESD/EMI Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PS031802-0514 PRELIMINARY List of Figures
eZ80L925148MODG
eZ80L92 Module Product Specification
v
List of Figures
Figure 1. eZ80L92 Module Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration . . . . . . . . . . 4
Figure 3. eZ80L92 Module I/O Connector Pin Configuration . . . . . . . . . . . . . . . . . . . 7
Figure 4. Dimension Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Mounting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Power Supply Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. eZ80L92 Module Schematic Diagram, #1 of 4: EMAC and Ethernet
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. eZ80L92 Module Schematic Diagram , #2 of 4: Memory . . . . . . . . . . . . . . 21
Figure 10. eZ80L92 Module Schematic Diagram, #3 of 4: eZ80L92 Device . . . . . . . 22
Figure 11. eZ80L92 Module Schematic Diagram, #4 of 4: Interfaces . . . . . . . . . . . . . 23
PS031802-0514 PRELIMINARY List of Tables
eZ80L925148MODG
eZ80L92 Module Product Specification
vi
List of Tables
Table 1. eZ80L92 Module Peripheral Bus Connector Pin Identification. . . . . . . . . . . 5
Table 2. eZ80L92 Module I/O Connector Pin Identification . . . . . . . . . . . . . . . . . . . . 8
Table 3. Ethernet Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Chip Frequency to Wait State Cycle Time Calculation . . . . . . . . . . . . . . . . 13
Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PS031802-0514 PRELIMINARY The eZ80L92 Module
eZ80L925148MODG
eZ80L92 Module Product Specification
1
The eZ80L92 Module
The eZ80L92 Module is a compact, high-performance Ethernet m odule specially designed
for the rapid development and deployment of embedded systems requiring control and
Internet/Intranet connectivity.
This low-cost, expandable module is powered by Zilog’s power-efficient, high-speed,
optimized pipeline architecture eZ80L92 device (eZ80L925048MOD), a member of
Zilog’s eZ80® mic roprocessor family.
The eZ80L92 microprocessor is a high-speed single-cycle instruction-fetch microproces-
sor, which can operate with a clock speed of 48 MHz. It can operate in Z80-compatible
addressing mode (64 KB) or full 24-bit addressing mode (16 MB).
The rich peripheral set of the eZ80L92 Module makes it suitable for a variety of applica-
tions, including industrial control, IrDA connectivity, communication, security, automa-
tion, point-of-sale terminals, and embedded networking applications.
Module Features
•
eZ80L92 MPU default factory operating clock frequency at 48 MHz
•
10 Base-T Ethernet Media Access Controller+ PHI with on-board RJ45 connector
•
512 KB zero-wait-state on-board SRAM
•
8 MB on-board NOR Flash ROM (90–100 ns)
•
GoldCap backup for Real-Time Clock
•
I/O connector provides 24 general-purpose 5 V-tolerant I/O pinouts
•
On-board connector provides I2C 2-wire SDA/SCL interface
•
On-board connector provi des I/O bus for external peripheral connections (IRQ, CS, 24
address, 8 data)
•
Low-cost connection to carrier board via two 2x25pin (2.54mm) headers
•
Horizontal or vertical mounting onto the eZ80® Development Platform
•
Small footprint 64 x 64mm; height is 24 mm
•
3.3 V power supply
•
Standard operating temperature range: 0ºC to +70ºC
PS031802-0514 PRELIMINARY eZ80L92 Processor Features
eZ80L925148MODG
eZ80L92 Module Product Specification
2
eZ80L92 Processor Features
•
Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core
•
Low power features including Sleep Mode, Halt Mode, and selective peripheral power-
down control
•
Two UARTs with independent baud rate generators
•
SPI with independent clock rate generator
•
I2C with independent clock rate generator
•
Infrared Data Association (IrDA)-compliant infrared encoder/decoder
•
New DMA-l ike eZ80® instructions for efficient block data transfer
•
Glueless external memory interface with 4 chip selects, individual wait state genera-
tors, and an external WAIT input pin: supports Intel- and Motorola-style buses
•
Fixed-priority vectored interrupts (both internal and external) and interrupt controller
•
Real-time clock with on-chip 32KHz oscillator , selectable 50/60Hz input, and separate
VDD pin for battery backup
•
Six 16-bit Counter/Timers with prescalers and direct input/output drive
•
Watch-Dog Timer
•
24 bits of general-purpose I/O
•
JTAG and ZDI debug interfaces
•
100-pin LQFP package
•
3.0–3.6 V supply voltage with 5V tolerant inputs
•
Standard operating temperature range: 0ºC to +70ºC
All signals with an overline are active Low. For exampl e, B/W, for which WORD is active
Low, and B/W, for which BYTE is active Low.
Block Diagram
Figure 1 illustrates a block diagram of the eZ80L92 Module.
Note:
PS031802-0514 PRELIMINARY eZ80L92 Processor Features
eZ80L925148MODG
eZ80L92 Module Product Specification
3
Figure 1. eZ80L92 Module Functional Block Diagram
Gold Cap 32 KHz XTAL
XTAL/Osc.
eZ80 CPUReal-Time Clock
Bus Controller
PD
PC
PB
Watch-Dog
Timer
I C/SPI
Power-On
Reset
ZDI/JTAG
UART
SPI
6 Timer
128/512 KB
SRAM
8 MB
Flash/ROM
50-Pin Connector
UART
50-Pin Connector
24-Bit GPIO
10 BaseT
Controller
w/ Magnetics
RJ45
2
PS031802-0514 PRELIMINARY Pin Description
eZ80L925148MODG
eZ80L92 Module Product Specification
4
Pin Description
Peripheral Bus Connector
Figure 2 illustrates the pin layout of the 50-pin I/O Connector, located at position JP1 on
the eZ80L92 Module. Table 6 describes the pins and their functions.
Figure 2. eZ80L92 Module Peripheral Bus Connector Pin Configuration
A0
A2
A4
A6
A8
A10
CS2
D3
A17
A5
V3.3_EXT
GND_EXT
A7
A22
A1
A18 A1 6
GND_EXT
RD
D5
GND_EXT
A9
A23
CS1
A13
A11
D0
A19
D6
BUSACK
V3.3_EXT
CS0
INSTRD
A15
D1
A14
A3
D4
D7
IOREQ
A21
GND_EXT
MREQ
A12
A20
DIS_FLASH
BUSREQ
WR
D2
DIS_ETH
JP1
HEADER 25X2
IDC50
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
PS031802-0514 PRELIMINARY Peripheral Bus Connector
eZ80L925148MODG
eZ80L92 Module Product Specification
5
Table 6. eZ80L92 Module Peripheral Bus Connector Pin Identification*
Pin # Symbol Pull
Up/Down* Signal Direction Comments
1 A6 Bidirectional
2 A0 Bidirectional
3 A10 Bidirectional
4 A3 Bidirectional
5GND V
SS
/Ground (0 V).
6V
DD
3.3 V Supply Input Pin.
7 A8 Bidirectional
8 A7 Bidirectional
9 A13 Bidirectional
10 A9 Bidirectional
11 A15 Bidirectional
12 A14 Bidirectional
13 A18 Bidirectional
14 A16 Bidirectional
15 A19 Bidirectional
16 GND V
SS
/Ground (0 V).
17 A2 Bidirectional
18 A1 Bidirectional
19 A11 Bidirectional
20 A12 Bidirectional
21 A4 Bidirectional
22 A20 Bidirectional
23 A5 Bidirectional
24 A17 Bidirectional
25 DIS_Eth PU 10 K¾ Input A Low disables on-module EMAC from
responding to CS3 on a per-cycle basis. CS3
can be used on th e eZ 8 0® Development
Platform; CMOS Input 3.3 V (5 V tolerant)
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requi re m en ts for the eZ80® CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS031802-0514 PRELIMINARY Peripheral Bus Connector
eZ80L925148MODG
eZ80L92 Module Product Specification
6
26 DIS_Flash PU 10 K¾ Input A Low disables on-module Flash memory
from responding to CS0 on a per-cycle basis.
CS0 can be used on the eZ80® Developmen t
Platform for external memory purposes;
CMOS Input 3.3 V (5 V tolerant).
27 A21 Bidirectional
28 V
DD
3.3 V supply input pin.
29 A22 Bidirectional
30 A23 Bidirectional
31 CS0 Output
32 CS1 Output
33 CS2 Output
34 D0 PU 4k7¾ Bidirectional
35 D1 PU 4k7¾ Bidirectional
36 D2 PU 4k7¾ Bidirectional
37 D3 PU 4k7¾ Bidirectional
38 D4 PU 4k7¾ Bidirectional
39 D5 PU 4k7¾ Bidirectional
40 GND V
SS
/Ground (0 V).
41 D7 PU 4k7¾ Bidirectional
42 D6 Bidirectional
43 MREQ Bidirectional
44 IORQ Bidirectional
45 GND V
SS
/Ground (0 V).
46 RD Bidirectional
47 WR Bidirectional
48 INSTRD Output
49 BUSACK PU 10K¾ Output
50 BUSREQ PU 10K¾ Input
Table 6. eZ80L92 Module Peripheral Bus Connector Pin Identification* (Continued)
Pin # Symbol Pull
Up/Down* Signal Direction Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requi re m en ts for the eZ80® CPU.
All unused inputs should be pulled to either VDD or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated via software in the eZ80L92 Peripheral Power-Down
Register.
All inputs are CMOS level 3.3 V (5 V tolerant), except where otherwise noted.
PS031802-0514 PRELIMINARY I/O Connector
eZ80L925148MODG
eZ80L92 Module Product Specification
7
I/O Connector
Figure 3 illustrates the pin layout of the 50-pin I/O Connector, located at position JP2 of
the eZ80L92 Module. Table 7 describes the pins and their functions.
Figure 3. eZ80L92 Module I/O Connector Pin Configuration
PB1
PB3
PB5
PB7
PC1
PC3
PC5
PC7
GND_EXT
PD1
PD3
PD5
PD7
DIS_IRDA
CS3
EZ80CLK
V3.3_EXT
FLASHWE
NMI
WAIT
GND_EXT
PB0
PB2
PB4
PB6
GND_EXT
PC2
PC4
RTC_VDD
PD0
PD2
PD4
PD6
GND_EXT
IICSCL
IICSDA
TDITDO
TRIGOUT
TCK TMS
RESET
GND_EXT
HALT_SLP
V3.3_EXT
PC6
PC0
JP2
HEADER 25X2
IDC50
12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
PS031802-0514 PRELIMINARY I/O Connector
eZ80L925148MODG
eZ80L92 Module Product Specification
8
Table 7. eZ80L92 Module I/O Connector Pin Identification*
Pin # Symbol Pull
Up/Down Signal
Direction Comments
1 PB7 Bidirectional
2 PB6 Bidirectional
3 PB5 Bidirectional
4 PB4 Bidirectional
5 PB3 Bidirectional
6 PB2 Bidirectional
7 PB1 Bidirectional
8 PB0 Bidirectional
9GND V
SS
/Ground (0 V).
10 PC7 Bidirectional
11 PC6 Bidirectional
12 PC5 Bidirectional
13 PC4 Bidirectional
14 PC3 Bidirectional
15 PC2 Bidirectional
16 PC1 Bidirectional
17 PC0 Bidirectional
18 PD7 Bidirectional
19 PD6 Bidirectional
20 GND V
SS
/Ground (0 V).
21 PD5 Bidirectional
22 PD4 PD 4k7 Bidirectional
23 PD3 Bidirectional
24 PD2 Bidirectional
25 PD1 Bidirectional
26 PD0 Bidirectional
27 TDO Output JTAG data output pin.
28 TDI/ZDA PU 10 K¾ Input JTAG data input pin.
29 GND V
SS
/Ground (0 V).
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their
inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK
output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register . All inputs are CMOS
level 3.3 V (5 V tolerant), except where otherwise noted.
PS031802-0514 PRELIMINARY I/O Connector
eZ80L925148MODG
eZ80L92 Module Product Specification
9
30 TRIGOUT Output Active High trigger event indicator.
31 TCK/ZCL PU 10 K¾ Input JTAG clock. High on reset enables ZDI mode; L ow on
reset enables OCI debug.
32 TMS PU 10 K¾ Input JTAG Test Mode Select.
33 RTC_V
DD
RTC supply from GoldCap (or external batte ry).
34 EZ80CLK Output 48 MHz synchr on ous CPU clo ck.
35 SCL PU 4k7 Bidirectional I
2
C Bus Clock.
36 GND V
SS
/Ground (0 V).
37 SDA PU 4k7 Bidirectional I
2
C Bus Data.
38 GND V
SS
/Ground (0 V).
39 FlashWE PU 10 K¾ Input Low enables W rite to on-board Flash memory. If this
pin is unconnected, the Flash memory is write-pro-
tected.
40 GND V
SS
/Ground (0 V).
41 CS3 Output Used on module for CS8900 EMAC.
42 DIS_IRDA PU 10 K¾ Input Low disables on-board IRDA transceiver to use PD0/
PD1 UART pins externally.
43 RESET PU 2k2 Bidirectional Reset output fro m Mo d ule or pu sh -b ut to n re se t.
44 WAIT PU 2k2 Input Driving the WAIT pin Low forces the eZ80® CPU to
provide additional clock cycles for an external periph-
eral or external memory to complete its Read or W rite
operation.
45 V
DD
3.3 V supply input pin.
Table 7. eZ80L92 Module I/O Connector Pin Identification* (Continued)
Pin # Symbol Pull
Up/Down Signal
Direction Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their
inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK
output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register . All inputs are CMOS
level 3.3 V (5 V tolerant), except where otherwise noted.
PS031802-0514 PRELIMINARY I/O Connector
eZ80L925148MODG
eZ80L92 Module Product Specification
10
46 GND V
SS
/Ground (0 V).
47 HALT_SLP Output, Active
Low A Low on this pin indicates that the eZ 8 0® CPU
enters either Halt or Sleep modes because of execu-
tion of either a HALT or SLP instruction.
48 NMI PU 10 K¾ Schmitt Trig-
ger Input,
Active Low
The NMI input is a higher prior ity input than the mask-
able interrupts. It is always recognized at the end of
an instruction , re ga rdle ss of th e state of the int er ru p t
enable control bits. This input includes a Schmitt trig-
ger to allow RC rise times. This external NMI signal is
combined with an internal NMI signal generated from
the WDT block before being connected to the NMI
input of the eZ80® CPU.
49 V
DD
3.3 V supply input pin.
50 Reserved NC Reserved; No Connection.
Table 7. eZ80L92 Module I/O Connector Pin Identification* (Continued)
Pin # Symbol Pull
Up/Down Signal
Direction Comments
Notes: *External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF to satisfy
timing requirements for the CPU. All unused inputs should be pulled to either VDD or GND, depending on their
inactive levels, to reduce power consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK
output can be deactivated via software in the eZ80F91 Peripheral Power-Down Register . All inputs are CMOS
level 3.3 V (5 V tolerant), except where otherwise noted.
PS031802-0514 PRELIMINARY On-Board Component Description
eZ80L925148MODG
eZ80L92 Module Product Specification
11
On-Board Component Description
Logic-Level I/Os
The I/O connector features 24 general-purpose 3.3 V CMOS I/O pins that can be used as
outputs or inputs interfacing to external logic. All I/Os are 5 V tolerant. Some of the Gen-
eral-Purpose I/O pins support dual mode functions (SPI, Timer I/O, UARTs and bit I/O
with edge- or level-triggered interrupt functions on each pin). For more information on
eZ80L92 dual modes, please refer to the eZ80L92 Product Specification (PS0130).
On-Board Battery Backup
An on-board 0.1 F capacitor (GoldCap) is used to bridge power outages of 2–4 hour s if the
power supply to the module is disconnected. The capacitor is charged to 3.1 V during nor-
mal operation and is discharged through the on-chip Real Time Clock. The V
RTC
pin is
available on the I/O connector of the module to connect external components to a power
supply or to a larger GoldCap.
Do not connect a Lithium Battery to the GoldCap capacitor , because on-board charging
circuitry for the capacitor can destroy the lithium battery.
Ethernet Media Access Controller
The eZ80L92 Module contains a CS8900A EMAC (MAC, PHI, and RAM) which is
attached to the data/address bus of the processor. This chip is connected to the processor’s
CS3 Chip Select, A0–A3, D0–D7, RD, WR, and PD4 pins for interrupt purposes. The con-
nection of the PD6 and PD7 pins for LANACT (i.e., wake-up from sleep) and Sleep is
optional and resistor-selectable onboard; see the Ethernet Connectors section that follows
to learn more.
Ethernet LEDs
Two LEDs are embedded in the RJ45 connector. When facing the connector, the GREEN
LED is located on the left side, and the YELLOW LED is located on the right. The
GREEN LED is active when the module transmits or receives a frame, or when it detects a
collision. The YELLOW LED is active when the module receives a valid 10 Base-T link
pulse; it is, essentially an indicator of an established link.
Caution:
PS031802-0514 PRELIMINARY Ethernet Media Access Controller
eZ80L925148MODG
eZ80L92 Module Product Specification
12
Ethernet Connectors
The eZ80L92 Modu le is equipped wi th an RJ45 connector that features integrated magnet-
ics (transformer, common mode chokes, and LEDs). The remaining pins on the on-board
RJ45 connector are not connected.
Node assignments for the RJ45 Ethernet connector are shown in Table 8.
Node assignment, in contrast to hub assignment, means that a straight-through cable
(equivalent pin numbers on both sides of the cable are connected to each other) is used to
attach the board to an Ethernet hub or swit ch . To connect the eZ80L92 Modu le dire ctl y to
another node (e.g., a personal co mputer), a crossover cable must be used.
The EMAC can be additionally protected by placing a U2 ESD protection array on the
module. This array can be either of the LCDA15C-6 (Semtech) or ESDA25B1 (ST Micro-
electronics) devices.
GPIO Pins for Enabling LAN Activity, Sleep, Interrupt
GPIO input bit PD4 serves as an active High interrupt input for the EMAC’s INTRQ0 out-
put.
GPIO output bit PD7 can be used to enter the EMAC into Sleep Mode. When pulling
Sleep (PD7) Low after enabling HWStandbyE and HWSleepE modes, the chip draws
lower current, because only the receiver is operating. A zero-Ohm resistor at position R6
on the eZ80L92 Module is required for this function. In this case, the PD6 pin is not avail-
able for GPIO on the I/O connecto r.
If LAN activity is detected, the LANACT signal is pulled Low. The LANACT is con-
nected to GPIO input PD6 and can be used in interrupt edge-detection mode to wake up
and reinitialize the Ethernet chip. A zero-Ohm resistor at position R3 on the module is
required for this function. In this case, the PD6 pin is not available for GPIO on the I/O
connector.
Table 8. Ethernet Connector Pin Assignments
Pin Function
1 TX+
2 TX–
3 RX+
6 RX–
PS031802-0514 PRELIMINARY Memory
eZ80L925148MODG
eZ80L92 Module Product Specification
13
EMAC Ports
Chip Select CS3 is used for selecting the EM AC via I/O decoding. The I/O base address is
user-selectable. The EMAC is connected as an 8- or 16-bit device with 8-word-wide I/O
registers:
EMAC Wait States
The CS8900A EMAC should be operated in Intel bus mode so that the setup and hold
times for the I/O access are met. For 48 MHz operation, first set CS3_BMC (I/O address
0xF3h) to 84h (Intel bus mode with four system clock cycles per bus cycle) and then
CS3_CTL (I/O Address 0xB3) to 18h (0 wait states for I/O). For a 20.8 ns CPU Clock
cycle time, the Read and
Write
access time is:
2 x 4 x 20.8 ns–16 ns (for capacitive and chip delays) = 150 ns
Memory
The eZ80L92 Module offers SRAM and Flash memories and the wait states that support
memory operations, as described in this section.
Wait States
To ensure that valid data is read from or written to slower memories, a number of wait
states must be inserted into the memory or I/O access operations by the processor. The
number of wait states that are required should be added by programming the chip select
control registers. To calculate the minimum number of wait states required, refer to
Table 9.
Static RAM
The eZ80L92 Module features 512 KB of fast SRAM. Access speed is typically 12 ns or
faster, allowing zero-wait-state operation at 48 MHz. With the CPU at 48 MHz, on-board
Table 9. Chip Frequency to Wait State Cycle Time Calculation
MHz Cycle Time
12 83.3 ns
20 50.0 ns
24 41.7 ns
36 27.8 ns
40 25.0 ns
48 20.8 ns
PS031802-0514 PRELIMINARY Reset Generator
eZ80L925148MODG
eZ80L92 Module Product Specification
14
SRAM can be accessed with zero wait states in eZ80 mode. CS1_CTL (chip select CS1)
can be set to 08h (no wait states).
Flash Memory
The Flash Boot Loader, application code, and user configuration data are held perma-
nently in NOR Flash memory. A typical application requires eight times more ROM for
code than RAM. As an example, for 128 KB on-board SRAM, 1 MB of ROM is required.
The eZ80L92 Module allows NOR Flash memories between 4 megabits (512 KB) and 64
megabits (8 MB) to be used. The chips are housed in wide TSOP40 cases. Flash ROM
access times are 55–150 ns; typically 90 ns.
NOR Flash should be operated in Intel bus mode to satisfy setup and hold times and to
prevent bus contention with a
Write
cycle that could possibly follow. For proper CPU
operation at 48 MHz, first set the bus mode control register CS0_BMC (I/O address
0xF0h) to 82h, then set the Chip Select Control register CS0_CTL (I/O address 0xAAh) to
08h. These settings select Intel Bus Mode with two system clocks per bus cycle and zero
wait states.
Reset Generator
The on-board Reset Generator Chip performs reliable Power -On Reset. The chip generates
a reset pulse with a duration of 200 ms if the power supply drops below 2.93 V. This reset
pulse ensures that the board always starts in a defined condition. The RESET pin on the I/
O connector reflects the status of the RESET line. It is a bidirectional pin for resetting
external peripheral components or for resetting the eZ80L92 Module with a low-imped-
ance output (e.g. a 100-Ohm pushbutton).
Serial Interface Ports
The processor contains two 16550-sty le UARTs with programmable baud rate generators.
UART0 is typically used for console I/O and initial boot code upload or to connect remote
peripherals that can be controlled and monitored via Ethernet. UART0 is connected to
GPIO PD[0:3] on the I/O connector. There are no RS232-level shifters on the eZ80L92
Module.
Do not connect an RS-232 interface without level shifters.
UART1 can be used for modem attachment or as a communications port to a host com-
puter, where the embedded Ethernet module emulates an AT-style modem for internet
access. UART1 does not offer on-board RS232-level shifters.
Note:
PS031802-0514 PRELIMINARY Physical Dimensions
eZ80L925148MODG
eZ80L92 Module Product Specification
15
Physical Dimensions
The size of the eZ80L 92 Module PCB is 64 x 64mm. With an RJ45 Ethernet connector , the
overall height is 25 mm, as shown in Figure 4.
Figure 5 illustrates a top view of the eZ80L92 Module.
Figure 4. Dimension Drawing
max.
8.3 mm
2.54 mm
1
13.7 mm LAN
1
RJ45
Top View
Bus Connector
I/O Connector
16.3 mm
16 mm
64 mm
63.5 mm
55.88 mm
PS031802-0514 PRELIMINARY Mounting the Module onto the eZ80®
eZ80L925148MODG
eZ80L92 Module Product Specification
16
Mounting the Module onto the eZ80® Development
Platform
The eZ80L92 Module can be mounted in several positions. Depending on volume and
area restrictions, it can be mounted horizontally or vertically with or without components
between the connectors on the eZ80® Development Platform. See Figure 6 for examples.
Figure 5. Top View
PS031802-0514 PRELIMINARY ESD/EMI Protection
eZ80L925148MODG
eZ80L92 Module Product Specification
17
ESD/EMI Protection
The eZ80L92 Module is a component that is intended to be part of a system design for
end-user devices. Therefore, the user must exercise caution to use ESD protection on the
I/O pins.
The EMAC can be additionally protected by placing an ESD protection array on the
eZ80L92 Module at position U9. Either use ESDA25B1 from ST Microelectronics or
LCDA15C-6 from Semtech. A moun ting hole on the board can be used for grounding the
shield of the Ethernet RJ45 jack to prevent surge or ESD currents from flowing through
the digital circuitry.
The RJ45 Ethernet Connector on the eZ80L92 Module contains a transformer and com-
mon mode chokes for EMI suppression.
CMOS I/Os are ESD-sensitive and must be handled with care. Handling of the module
should be performed in ESD-safe environments (for example with a wrist-wrap at-
tached). When developing applications, the user must provide for proper ESD protection
on external, user-accessible I/Os (e.g. suppressor arrays for the I/Os).
The components are mounted on a multilayer PCB to provide a stable ground plane for on-
board components. The modu le features several GND pins next to pins with higher
switching frequency for short ground returns. If unused, the clock output can be separated
Figure 6. Mounting Examples
Low Profile Mounting
64 mm 1
E-NET Module
RJ45
(rear) 1
8.3 mm
I/O
Carrier Board
H = 4.5 mm 1.7 mm
Bus
15.3 mm
63.5 mm
Caution:
Caution:
PS031802-0514 PRELIMINARY Power Supply
eZ80L925148MODG
eZ80L92 Module Product Specification
18
from the module header by removing a series resistor on the module. Removing the series
resistor further reduces electromagnetic emissions.
Absolute Maximum Ratings
Stresses greater than those listed in Table 10 can cause permanent damage to the device.
These ratings are stress ratings only . Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
For improved reliability, unused inputs should be tied to one of the supply voltages (VDD
or VSS).
Power Supply
The eZ80L92 Module requires a regulated external 3. 3 VDC/0.5A power supply. You may
use a Low Dropout Regulator (LDO) to get 3.3 V from 5 V or use the following switcher
circuit to generate 3.3 V from unregulated 10-28V power supply.
Power connections follow these conventional descriptions:
Figure 7 offers two typical power supply examples.
Table 10. Absolute Maximum Ratings
Parameter Min Max Units
Standard operat ing t em p er at ur e 0 +70 ºC
Storage temperature –45 +85 ºC
Operating Humidity (RH @ 50ºC) 25% 90%
Operating Voltage (±5%) – 3.3 V
Connection Circuit Device
Power V
CC
V
DD
Ground GND V
SS
PS031802-0514 PRELIMINARY Power Supply
eZ80L925148MODG
eZ80L92 Module Product Specification
19
Figure 7. Power Supply Examples
PS031802-0514 20
eZ80L925148MODG
eZ80L92 Module Product Specification
Schematic Diagrams
Figures 8 through 11 diagram the layout of the eZ80L92 Module.
Figure 8. eZ80L92 Module Schematic Diagram, #1 of 4: EMAC and Ethernet Connections
LEFT
RIGHT
R4 is located directly on the JP2
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
LANLED
LINKLED
RXD-
RXD+
TXD-
TXD+
-SLEEP
ETHIRQ
TD+
TD-
TXD+
TXD-
RXD+
RXD+
RXD-
TD+
TD-
RXD-
VCC_3v3
GND
LANLED
LINKLED
VCC_3v3
VCC_3v3
VCC_3v3
D[7:0]
-ETHWR
-ETHRD
A[3:0]
WAIT-
PD4
PD6
PD7
VCC_3v3
GND
R10
100 ohm
P1
HFJ11-1041ERL-L11
TD+
1
TD-
2
RD+
3
CTD
4
CRD
5
RD-
6
NC8
8
SHIELD2 14
SHIELD1 13
NC15 15
NC16 16
NC7
7
AN1
9
CT1
10
AN2
11
CT2
12
R5
4.99K
CS8900A
U1
SD4
71
SD5
72
SD6
73
SD7
74
SD0
65
SD1
66
SD2
67
SD3
68
SA17
58
SA18
59
SA19
60
SA13
51
SA14
52
SA15
53
SA16
54
SA0
37
AVSS 1
SA1
38
ELCS 2
SA2
39
EECS 3
SA3
40
EESK 4
SA4
41
EEDATAOUT (TDO) 5
SA5
42
EEDATAIN 6
SA6
43
CHIPSEL 7
SA7
44
DVSS 8
SA8
45
DVDD 9
SA9
46
DVSS 10
SA10
47
DMARQ2 11
SA11
48
DMACK2 12
REFRESH
49
DMARQ1 13
SA12
50
DMACK1 14
DMARQ0 15
DMACK0 16
CSOUT 17
SD15 18
SD14 19
SD13 20
SD12 21
DVDD 22
DVSS 23
SD11 24
SD10 25
SD9
26
SD8
27
MEMW
28
MEMR
29
INTRQ2
30
INTRQ1
31
INTRQ0
32
IOCS16
33
MEMCS16
34
INTRQ3
35
SHBE
36
DVSS
55
DVDD
56
DVSS
57
IOR
61
IOW
62
AEN (TCK)
63
IOCHRDY
64
DVDD
69
DVSS
70
RESET
75
TEST 76
SLEEP 77
BSTATUS/HC1 78
DI+ 79
DI- 80
CI+ 81
CI- 82
DO+ 83
DO- 84
AVDD 85
AVSS 86
TXD+ 87
TXD- 88
AVSS 89
AVDD 90
RXD+ 91
RXD- 92
RES 93
AVSS 94
AVDD 95
AVSS 96
XTAL1 97
XTAL2 98
LINKLED/HC0 99
LANLED 100
R4
4.7K
U2
LCDA..C-6
1
2
3
4 5
6
7
8
C29
0.1μF
C2
0.1uF
C28
0.1μF
C27
0.1μF
R2 220 ohm
C3
0.1uF
Y1
20MHZ
C26
0.1μF
R1 220 ohm
C25
0.1μF
R11
1 MEG
C24
0.1μF
C23
0.1μF
R8
8.2
R7 8.2
R6
0 ohm
R3
0 ohm
C4
0.001μF/2000V
R9 0 ohm
C1
560pF
PS031802-0514 21
eZ80L925148MODG
eZ80L92 Module Product Specification
Figure 9. eZ80L92 Module Schematic Diagram, #2 of 4: Memory
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
A6
A5
A9
A0
A4
A15
A7
A12
A2
A11
A14
A16
A10
A8
A13
A1
A3
A17
A18
A0
A6
A5
A9
A4
A15
A7
A12
A2
A11
A14
A16
A10
A8
A13
A1
A3
A17
A18
A19
A20
A21
A22
FLASH_CS-
FLASH_WP-
RD-
WR-
FLASH_CS-
D0
D1
D2
D3
D4
D5
D6
D7
D2
D1
D0
D4
D3
D7
D6
D5
-ETHRD
-ETHWR
WR-
RD-
FLASH_WP-
WR-
RD-
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
A[23:0]
DIS_FLASH-
CS0-
FLASH_WE-
D[7:0]
CS3-
-ETHRD
-ETHWR
VCC_3v3
GND
RD-
WR-
CS1-
R2610K
RN1
4.7K
2
3
4
5
6
7
8
9
1
10
C20
0.1uF
U7B
SN74ALVC32
4
5
6
147
R2510K
R2710K
U7A
SN74ALVC32
1
2
3
147
C21
0.1uF
U6
74LVC2GU04
1A
1
GND
2
2A
32Y 4
VCC 5
1Y 6
U9
CY7C1049DV33
GND1 12
D0 9
D1 10
D2 13
D3 14
A16
39 A15
38
A11
27
A8
19
A13
29 A12
28
A10
26
A0
3
A1
4
A2
5
A3
6
A4
7
A5
16
A6
17
A7
18
A9
20
A14
30
GND2 34
D4 31
D5 32
D6 35
D7 36
OE
37
WE
15
CE
8
VCC1 11
VCC2 33
A17
40
A18
41
NC1 1
NC2 2
NC3 21
NC4 22
NC5 23
NC6 24
NC7 25
NC9 43
NC10 44
NC8 42
U7C
SN74ALVC32
9
10
8
147
C22
0.1uF
U7D
SN74ALVC32
12
13
11
147
C19
0.1uF
U5
S29GL064N
A0
E1
A1
D1
A2
C1
A3
A1
A4
B1
A5
D2
A6
C2
A7
A2
A8
B5
A9
A5
A10
C5
A11
D5
A12
B6
A13
A6
A14
C6
A15
D6
A16
E6
A17
B2
A18
C3
A19
D4
CE
F1
OE
G1
WE
A4
DQ0 E2
DQ1 H2
DQ2 E3
DQ3 H3
DQ4 H4
DQ5 E4
DQ6 H5
DQ7 E5
DQ8 F2
DQ9 G2
DQ10 F3
DQ11 G3
DQ12 F4
DQ13 G5
DQ14 F5
DQ15/A-1 G6
RST
B4
BYTE
F6
GND2 H6
GND1 H1
WP
B3
A20
D3
A21
C4
VCC G4
RY/BY A3
PS031802-0514 22
eZ80L925148MODG
eZ80L92 Module Product Specification
Figure 10. eZ80L92 Module Schematic Diagram, #3 of 4: eZ80L92 Device
Place resistor near CPU
A6
A5
A9
A0
A4
PD6
A15
A7
A12
A2
A11
A14
A16
A10
A8
A13
A1
A3
A17
ZCL
SYS_RST-
A18
PC0
PC1
PD0
PD1
PC3
PC2
PC4
PD2
PD3
PD4
ZDA
D0
D1
D2
D3
D4
D5
D6
D7
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PD7
A19
A20
A21
A22
A23
BATT+
PD5
GND
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
VCC_3v3
A[23:0]
RD-
WR-
CS1-
CS2-
CS0-
TMS
TCK
TDI
WAIT-
BUSREQ-
NMI-
RESET-
BUSACK-
CS3-
IICSCL
IICSDA
MREQ-
IORQ-
D[7:0]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PD0
HALT_SLP-
EZ80CLK
INSTRD-
TDO
TRGOUT
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VCC_3v3
GND
RTC_VDD
R15
10K
R19
4.7K
C5
0.1uF
R23
100 ohm
C18
0.1uF
R16
10K
R17
10K
C6
12pF
R20
4.99K
U8
eZ80L92
A0 1
A1 2
A2 3
A3 4
A4 5
A5 6
A6 9
A7 10
A8 11
A9 12
A10 13
A11 14
A12 15
A13 16
A14 17
A15 20
A16 21
A17 22
A18 23
A19 24
A20 25
A21 26
A22 27
A23 28
D0
35
D1
36
D2
37
D3
38
D4
39
D5
40
D6
41
D7
42
BUSREQ
53
TMS
62
TCK
63
TDI
65
NMI
52
RESET
51
IORQ 45
MREQ 46
RD 47
WR 48
CS0 29
CS1 30
CS2 31
CS3 32
SCL 99
SDA 98
XOUT
86
XIN
85
VDD1
7
VDD2
18
VDD3
33
VDD4
43
VDD6
67
VDD7
87
VDD8
96
VSS1
8
VSS2
19
VSS3
34
VSS4
44
VSS5
57
VSS6
61
VSS7
84
VSS8
97
PB7/MOSI 95
PB6/MISO 94
PB5/T5_OUT 93
PB4/T4_OUT 92
PB3/SCK 91
PB2/SS 90
PB1/T1_IN 89
PB0/T0_IN 88
PC7/RI1 83
PC6/DCD1 82
PC5/DSR1 81
PC4/DTR1 80
PC3/CTS1 79
PC2/RTS1 78
PC1/RXD1 77
PC0/TXD1 76
PD7/RI0 75
PD6/DCD0 74
PD5/DSR0 73
PD4/DTR0 72
PD3/CTS0 71
PD2/RTS0 70
PD1/RXD0/IR_RXD 69
PD0/TXD0/IR_TXD 68
HALT_SLP 55
PHI 100
TDO 66
TRIGOUT 64
BUSACK 54
INSTRD 49
RTC_VDD
60
RTC_XOUT
59
RTC_XIN
58
VDD5
56
WAIT
50
R12
10K
R22
100K
C11
0.1uF
R13
10K
D3
RB751V
2 1
Y3
32.768KHZ
C12
0.1uF
L1
3.3UH
C13
0.1uF
R18
4.75K
C8
220pF
R21
4.99K
C10
18pF
C14
0.1uF
Y2
48.000MHZ
C15
0.1uF
R24 33.2
R14
10K
U3
MAX6328
GND 1
RESET 2
VCC
3
C16
0.1uF
D2
RB751V
2 1
C7
12pF
C9
18pF
BT1
0.1F, Super Cap
12
C17
0.1uF
PS031802-0514 23
eZ80L925148MODG
eZ80L92 Module Product Specification
Figure 11. eZ80L92 Module Schematic Diagram, #4 of 4: Interfaces
A0
A6
A10
GND
A13
A8
A18
A15
A2
A11
A4
A19
A21
A22
A5
D3
D1
CS2-
CS0-
MREQ-
D5
D7
WR-
BUSACK-
GND
A3
A9
A7
A16
A14
A17
A1
A12
A20
D2
A23
CS1-
D0
D4
DIS_FLASH-
PB7
PB3
PB5
PB1
PC6
PC2
PC4
PC0
PD6
PD3
PD5
TCK
IICSCL
RTC_VDD
IICSDA
FLASH_WE-
RESET-
CS3-
WAIT-
NMI-
TDI
TMS
TRIGOUT
EZ80CLK
PC5
PC1
PC3
PD7
PB4
PB0
PB2
PC7
PB6
PD0
PD4
PD2
BUSREQ-
IOREQ-
RD-
INSTRD-
D6
TD0
HALT_SLP-
PD1
GND
GND
GND
A[23:0]
D[7:0]
GND
VCC_3v3
VCC_3v3
VCC_3v3
A[23:0]
PB0
PB2
PB4
PB6
PB1
PB3
PB5
PB7
PC0
PC2
PC4
PC6
PD1
PD3
PD5
PD6
IICSDA
IICSCL
RTC_VDD
TCK
HALT_SLP-
RESET-
CS3-
FLASH_WE-
TDO
PC1
PC5
PC3
PC7
PD0
PD2
PD7
PD4
TDI
TMS
EZ80CLK
TRGOUT
WAIT-
NMI-
D[7:0]
DIS_FLASH-
CS1-
IORQ-
RD-
INSTRD-
BUSREQ-
CS0-
CS2-
MREQ-
WR-
BUSACK-
VCC_3v3
GND
JP2
2x25/PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49 50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
JP1
2x25/PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49 50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
PS031802-0514 PRELIMINARY Customer Support
eZ80L925148MODG
eZ80L92 Module Product Specification
24
Customer Support
To share comments, get your technical questions answered, o r report issues you may b e
experiencing with our products, please visit Zilog’s Technical Support page at
http://support.zilog.com.
To learn more about this product, find additional documentation, or to discover other fac-
ets about Zilog product offerings, please visit the Zilog Knowledge Base or consider p ar-
ticipating in the Zilog Forum.
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EZ80L925148MODG