Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 0 1Publication Order Number:
BCX71J/D
BCX71J
General Purpose Transistor
PNP Silicon
•Moisture Sensitivity Level: 1
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector-Emitter Voltage VCEO –45 Vdc
Collector-Base Voltage VCBO –45 Vdc
Emitter-Base Voltage VEBO –5.0 Vdc
Collector Current – Continuous IC–100 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation (Note 1.)
TA = 25°C
Derate above 25°C
PD350
2.8
mW
mW/°C
Storage Temperature Tstg 150 °C
Thermal Resistance –
Junction-to-Ambient (Note 1.) RθJA 357 °C/W
1. Package mounted on 99.5% alumina 10 X 8 X 0.6 mm. SOT–23
CASE 318
STYLE 6
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BJ = Specific Device Marking
M = Date Code
BJ M
MARKING DIAGRAM
1
3
2
Device Package Shipping
ORDERING INFORMATION
BCX71JLT1 SOT–23 3000/Tape & Reel
COLLECTOR
3
1
BASE
2
EMITTER
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2
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage
(IC = 2.0 mAdc, IB = 0) V(BR)CEO –45 – Vdc
Collector–Base Breakdown Voltage
(IE = 1.0 µAdc, IE = 0) V(BR)EBO –5.0 – Vdc
Collector Cutoff Current
(VCE = 32 Vdc)
(VCE = 32 Vdc, TA = 150°C)
ICES –
––20
–20 nAdc
µAdc
ON CHARACTERISTICS
DC Current Gain
(IC = 10 Adc, VCE = 5.0 Vdc)
(IC = 2.0 mAdc, VCE = 5.0 Vdc)
(IC = 50 mAdc, VCE = 1.0 Vdc)
(IC = 2.0 mAdc, VCE = 5.0 Vdc, f = 1.0 kHz)
hFE 40
250
100
250
–
460
–
500
–
Collector–Emitter Saturation Voltage
(IC = 10 mAdc, IB = 0.25 mAdc)
(IC = 50 mAdc, IB = 1.25 mAdc)
VCE(sat) –
––0.25
–0.55
Vdc
Base–Emitter Saturation Voltage
(IC = 1.0 mAdc, VCE = 5.0 Vdc)
(IC = 10 mAdc, VCE = 5.0 Vdc)
VBE(sat) –0.6
–0.68 –0.85
–1.05
Vdc
Base–Emitter On Voltage
(IC = 2.0 mAdc, VCE = 5.0 Vdc) VBE(on) –0.6 –0.75 Vdc
Output Capacitance
(VCE = 10 Vdc, IC = 0, f = 1.0 MHz) Cobo – 6.0 pF
Noise Figure
(IC = 0.2 mAdc, VCE = 5.0 Vdc, RS = 2.0 k, f = 1.0 kHz, BW = 200 Hz) NF – 6.0 dB
SWITCHING CHARACTERISTICS
Turn–On Time
(IC = 10 mAdc, IB1 = 1.0 mAdc) ton – 150 ns
Turn–Off Time
(IB2 = 1.0 mAdc, VBB = 3.6 Vdc, R1 = R2 = 5.0 k, RL = 990 )toff – 800 ns
TYPICAL NOISE CHARACTERISTICS
(VCE = –5.0 Vdc, TA = 25°C)
Figure 1. Noise Voltage
f, FREQUENCY (Hz)
5.0
7.0
10
3.0
Figure 2. Noise Current
f, FREQUENCY (Hz)
1.0
10 20 50 100 200 500 1.0k 2.0k 5.0k 10k
1.0
7.0
5.0
3.0
2.0
1.0
0.7
0.5
0.3
0.1
BANDWIDTH = 1.0 Hz
RS ≈ 0
IC = 10 µA
100 µA
en, NOISE VOLTAGE (nV)
In, NOISE CURRENT (pA)
30 µA
BANDWIDTH = 1.0 Hz
RS ≈∞
IC = 1.0 mA
300 µA
100 µA
30 µA
10 µA
10 20 50 100 200 500 1.0k 2.0k 5.0k 10k
2.0 1.0 mA
0.2
300 µA
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NOISE FIGURE CONTOURS
(VCE = –5.0 Vdc, TA = 25°C)
500k
100
200
500
1.0k
10k
5.0k
20k
50k
100k
200k
2.0k
1.0M
500k
100
200
500
1.0k
10k
5.0k
20k
50k
100k
200k
2.0k
1.0M
Figure 3. Narrow Band, 100 Hz
IC, COLLECTOR CURRENT (µA)
Figure 4. Narrow Band, 1.0 kHz
IC, COLLECTOR CURRENT (µA)
10
0.5 dB
BANDWIDTH = 1.0 Hz
RS, SOURCE RESISTANCE (OHMS)
RS, SOURCE RESISTANCE (OHMS)
Figure 5. Wideband
IC, COLLECTOR CURRENT (µA)
10
10 Hz to 15.7 kHz
RS, SOURCE RESISTANCE (OHMS)
Noise Figure is Defined as:
NF 20 log10en24KTRSIn2RS2
4KTRS12
= Noise Voltage of the Transistor referred to the input. (Figure 3)
= Noise Current of the T ransistor referred to the input. (Figure 4)
= Boltzman’s Constant (1.38 x 10–23 j/°K)
= Temperature of the Source Resistance (°K)
= Source Resistance (Ohms)
en
In
K
T
RS
1.0 dB
2.0 dB
3.0 dB
20 30 50 70 100 200 300 500 700 1.0k 10 20 30 50 70 100 200 300 500 700 1.0k
500k
100
200
500
1.0k
10k
5.0k
20k
50k
100k
200k
2.0k
1.0M
20 30 50 70 100 200 300 500 700 1.0k
BANDWIDTH = 1.0 Hz
5.0 dB
0.5 dB
1.0 dB
2.0 dB
3.0 dB
5.0 dB
0.5 dB
1.0 dB
2.0 dB
3.0 dB
5.0 dB
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TYPICAL STATIC CHARACTERISTICS
Figure 6. DC Current Gain
IC, COLLECTOR CURRENT (mA)
400
0.003
h , DC CURRENT GAIN
FE
TJ = 125°C
-55°C
25°C
VCE = 1.0 V
VCE = 10 V
Figure 7. Collector Saturation Region
IC, COLLECTOR CURRENT (mA)
1.4
Figure 8. Collector Characteristics
IC, COLLECTOR CURRENT (mA)
V, VOLTAGE (VOLTS)
1.0 2.0 5.0 10 20 50
1.6
100
TJ = 25°C
VBE(sat) @ IC/IB = 10
VCE(sat) @ IC/IB = 10
VBE(on) @ VCE = 1.0 V
*VC for VCE(sat)
VB for VBE
0.1 0.2 0.5
MPS390
6
Figure 9. “On” Voltages
IB, BASE CURRENT (mA)
0.4
0.6
0.8
1.0
0.2
0
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
0.002
TA = 25°C
MPS3906
IC = 1.0 mA 10 mA 100 mA
Figure 10. Temperature Coefficients
50 mA
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
40
60
80
100
20
0
0
IC, COLLECTOR CURRENT (mA)
TA = 25°C
PULSE WIDTH = 300 µs
DUTY CYCLE ≤ 2.0%
IB = 400 µA
350 µA
300 µA250 µA
200 µA
*APPLIES for IC/IB ≤ hFE/2
25°C to 125°C
-55°C to 25°C
25°C to 125°C
-55°C to 25°C
40
60
0.005 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 70 100
0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 5.0 10 15 20 25 30 35 40
1.2
1.0
0.8
0.6
0.4
0.2
02.4
0.8
0
1.6
0.8
1.0 2.0 5.0 10 20 50 100
0.1 0.2 0.5
200
100
80
V, TEMPERATURE COEFFICIENTS (mV/ C)°θ
150 µA
100 µA
50 µA
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TYPICAL DYNAMIC CHARACTERISTICS
C, CAPACITANCE (pF)
Figure 11. Turn–On Time
IC, COLLECTOR CURRENT (mA)
500
Figure 12. Turn–Off Time
IC, COLLECTOR CURRENT (mA)
2.0 5.0 10 20 30 50
1000
Figure 13. Current–Gain — Bandwidth Product
IC, COLLECTOR CURRENT (mA)
Figure 14. Capacitance
VR, REVERSE VOLTAGE (VOLTS)
Figure 15. Input Impedance
IC, COLLECTOR CURRENT (mA)
Figure 16. Output Admittance
IC, COLLECTOR CURRENT (mA)
3.01.0
500
0.5
10
t, TIME (ns)
t, TIME (ns)
f, CURRENT-GAIN  BANDWIDTH PRODUCT (MHz)
T
h , OUTPUT ADMITTANCE ( mhos)
oe
hie, INPUT IMPEDANCE (k )Ω
5.0
7.0
10
20
30
50
70
100
300
7.0 70 100
VCC = 3.0 V
IC/IB = 10
TJ = 25°C
td @ VBE(off) = 0.5 V
tr
10
20
30
50
70
100
200
300
500
700
-2.0-1.0
VCC = -3.0 V
IC/IB = 10
IB1 = IB2
TJ = 25°C
ts
tf
50
70
100
200
300
0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50
TJ = 25°C
VCE = 20 V
5.0 V
1.0
2.0
3.0
5.0
7.0
0.1 0.2 0.5 1.0 2.0 5.0 10 20 500.05
Cib
Cob
2.0 5.0 10 20 50
1.0
0.2
100
0.3
0.5
0.7
1.0
2.0
3.0
5.0
7.0
10
20
0.1 0.2 0.5
MPS3905
hfe ≈ 100
@ IC = -1.0 mA
VCE = -10 Vdc
f = 1.0 kHz
TA = 25°C
2.0 5.0 10 20 50
1.0
2.0
100
3.0
5.0
7.0
10
20
30
50
70
100
200
0.1 0.2 0.5
VCE = 10 Vdc
f = 1.0 kHz
TA = 25°C
200
-3.0 -5.0 -7.0 -20-10 -30 -50 -70 -100
TJ = 25°C
MPS3906
hfe ≈ 200
@ IC = -1.0 mA
MPS3905
hfe ≈ 100
@ IC = 1.0 mA
MPS3906
hfe ≈ 200
@ IC = 1.0 mA
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Figure 17. Thermal Response
t, TIME (ms)
1.0
0.01
r(t) TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.01
0.02
0.03
0.05
0.07
0.1
0.2
0.3
0.5
0.7
0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 500 1.0k 2.0k 5.0k 10k 20k 50k 100k
D = 0.5
0.2
0.1
0.05
0.02
0.01 SINGLE PULSE
DUTY CYCLE, D = t1/t2
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1 (SEE AN-569)
ZθJA(t) = r(t) •RθJA
TJ(pk) - TA = P(pk) ZθJA(t)
t1
t2
P(pk)
FIGURE 19
Figure 18. Active–Region Safe Operating Area
TJ, JUNCTION TEMPERATURE (°C)
104
-40
IC, COLLECTOR CURRENT (nA)
Figure 19. Typical Collector Leakage Current
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
400
2.0
IC, COLLECTOR CURRENT (mA)
DESIGN NOTE: USE OF THERMAL RESPONSE DATA
A train of periodical power pulses can be represented by the model
as shown in Figure 19. Using the model and the device thermal
response the normalized effective transient thermal resistance of
Figure 17 was calculated for various duty cycles.
To find ZθJA(t), multiply the value obtained from Figure 17 by the
steady state value RθJA.
Example:
The MPS3905 is dissipating 2.0 watts peak under the following
conditions: t1 = 1.0 ms, t2 = 5.0 ms (D = 0.2)
Using Figure 17 at a pulse width of 1.0 ms and D = 0.2, the reading of
r(t) is 0.22.
The peak rise in junction temperature is therefore
∆T = r(t) x P(pk) x RθJA = 0.22 x 2.0 x 200 = 88°C.
For more information, see AN–569.
The safe operating area curves indicate IC–VCE limits of the
transistor that must be observed for reliable operation. Collector load
lines for specific circuits must fall below the limits indicated by the
applicable curve.
The data of Figure 18 is based upon TJ(pk) = 150°C; TC or TA is
variable depending upon conditions. Pulse curves are valid for duty
cycles to 10% provided TJ(pk) ≤ 150°C. TJ(pk) may be calculated from
the data in Figure 17. At high case or ambient temperatures, thermal
limitations will reduce the power than can be handled to values less
than the limitations imposed by second breakdown.
10-2
10-1
100
101
102
103
-20 0 +20 +40 +60 +80 +100 +120 +140 +160
VCC = 30 V
ICEO
ICBO
AND
ICEX @ VBE(off) = 3.0 V
TA = 25°C
CURRENT LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
1.0 ms 10 µs
TC = 25°C1.0 s
dc
dc
4.0
6.0
10
20
40
60
100
200
4.0 6.0 8.0 10 20 40
TJ = 150°C
100 µs
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INFORMATION FOR USING THE SOT-23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT-23 POWER DISSIPATION
The power dissipation of the SOT-23 is a function of the
drain pad size. This can vary from the minimum pad size
for soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient; and the operating
temperature, TA. Using the values provided on the data
sheet, PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W assumes the use of the recommended
footprint on a glass epoxy printed circuit board to achieve a
power dissipation of 225 milliwatts. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad. Using a board material such
as Thermal Clad, the power dissipation can be doubled
using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference should be a maximum of 10°C.
•The soldering temperature and time should not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient should be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied
during cooling
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass
or stainless steel with a typical thickness of 0.008 inches.
The stencil opening size for the surface mounted package
should be the same as the pad size on the printed circuit
board, i.e., a 1:1 registration.
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 20 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
STEP 1
PREHEAT
ZONE 1
RAMP"
STEP 2
VENT
SOAK"
STEP 3
HEATING
ZONES 2 & 5
RAMP"
STEP 4
HEATING
ZONES 3 & 6
SOAK"
STEP 5
HEATING
ZONES 4 & 7
SPIKE"
STEP 6
VENT
STEP 7
COOLING
200°C
150°C
100°C
50°C
TIME (3 TO 7 MINUTES TOTAL) TMAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205° TO 219°C
PEAK AT
SOLDER JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
100°C
150°C
160°C
140°C
Figure 20. Typical Solder Heating Profile
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
170°C
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PACKAGE DIMENSIONS
SOT–23
TO–236AB
CASE 318–08
ISSUE AF
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
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Notes
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Notes
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