A product Line of Diodes Incorporated PI6C49S1510A High Performance Differential Fanout Buffer Features Description II10 differential outputs with 2 banks The PI6C49S1510A is a high performance fanout buffer devicewhich supports up to 1.5GHz frequency. It also integrates a unique feature with user configurable output signaling standards on per bank basis which provide great flexibilities to users. The device also uses Pericom's proprietary input detection technique to make sure illegal input conditions will be detected and reflected by output states. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. IIUser configurable output signaling standard for each bank: LVDS or LVPECL or HCSL IILVCMOS reference output up to 200MHz IIUp to 1.5GHz output frequency for differential outputs IIUltra low additive phase jitter: < 0.02 ps (typ) (differential 156.25MHz, 12KHz to 20MHz integration range); < 0.01 ps (typ) (differential 156.25MHz, 10kHz to 1MHz integration range) Applications IISelectable reference inputs support either single-ended IINetworking systems including switches and Routers or differential or Xtal IIHigh frequency backplane based computing and telecom IILow skew between outputs within banks (<40ps) platforms IILow delay from input to output (Tpd typ. < 0.9ns) IISeparate Input output supply voltage for level shifting II2.5V / 3.3V power supply IIIndustrial temperature support IITQFN-48 package Ref_Out IN_SEL[1:0] Sync_OE Sync Iref GND Iref OPMODEB_1 IN1- 34 QB1+ QA1- 4 33 QB1- VDDO 5 32 VDDO QA2+ 6 31 QB2+ QA2- 7 30 QB2- VDDO 8 29 VDDO QA3+ 9 28 QB3+ QA3- 10 27 QB3- QA4+ 11 26 QB4+ QA4- 12 25 QB4- GND X2 X1 VDD OPMODEA_0 GND 1 IN1+ 3 13 14 15 16 17 18 PI6C49S1510A Document Number DS40482 Rev 2-2 VDD GND Ref_Out QBO- QA1+ 19 20 21 22 23 24 www.diodes.com GND IN1+ IN1- 35 OPMODEB_0 5 QBO+ 2 IN_SEL_1 QB[0:4] 36 QAO- IN0- IN0+ IN0- 1 IN0+ OPMODEB[1:0] 42 41 40 39 38 37 QAO+ IN_SEL_0 5 OSC VDDO 48 47 46 45 44 43 QA[0:4] X1 X2 Sync_OE GND OPMODEA[1:0] OPMODEA_1 Pin Configuration (48-TQFN) Block Diagram January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Pin Description Pin # 1,2 3,4 5,8,29,32,45 6,7 9,10 11,12 Pin Name QA0+ QA0QA1+ QA1- Type Output Bank A differential output pair 0. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank A differential output pair 1. Pin selectable LVPECL/LVDS/HCSL interface levels. Power Power supply pins for IO Output Bank A differential output pair 2. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank A differential output pair 3. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank A differential output pair 4. Pin selectable LVPECL/LVDS/HCSL interface levels. Power Power supply ground VDDO QA2+ QA2QA3+ QA3QA4+ QA4- Description 13,18,24,37,43,48 GND 14,47 OPMODEA 15,42 VDD Power Power supply pins 16 X1 Input XTAL input, can also be used as single ended input pin 17 X2 Output 19,22 IN_SEL Input Pulldown 20 IN0+ Input Pulldown Reference input 0 21 IN0- Input Pull-up/ Inverted reference input 0, internal bias to VDD/2 Pulldown 23,39 OPMODEB Input Pulldown 26,25 28,27 31,30 34,33 QB4+ QB4QB3+ QB3QB2+ QB2QB1+ QB1- PI6C49S1510A Document Number DS40482 Rev 2-2 Input Pulldown Output mode select for Bank A. See Table 2 for functions, LVCMOS/ LVTTL interface levels XTAL output. If X1 is used as a single ended input pin, X2 is to be left open Input clock sele ct. See Table 1 for function. LVCMOS/LVTTL interface levels. Output mode select for Bank B. See Table 2for functions, LVCMOS/ LVTTL interface levels Output Bank B differential output pair 4. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank B differential output pair 3. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank B differential output pair 2. Pin selectable LVPECL/LVDS/HCSL interface levels. Output Bank B differential output pair 1. Pin selectable LVPECL/LVDS/HCSL interface levels. 2 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Pinout Description Cont. Pin # 36,35 Pin Name QB0+ QB0- Type Description Output Bank B differential output pair 0. Pin selectable LVPECL/LVDS/HCSL interface levels. A fixed precision resistor (475ohm) from this pin to ground provides a reference current for HCSL mode. If LVPECL or LVDS mode chosen, pin can be left open 38 Iref Output 40 IN1- Input Pull-up/ Inverted reference input, internal bias to VDD/2 Pulldown 41 IN1+ Input Pulldown Reference input 1 44 Ref_Out Output 46 Sync_OE Input Reference output, CMOS Pulldown Synchronous output enable for Ref_Out, see Table 3 for functions Function Table Table 1: Input select function IN_SEL [1] IN_SEL [0] Function 0 0 IN0 is the selected reference input 0 1 IN1 is the selected reference input 1 X XTAL is the selected input Table 2: Output Mode select function OPMODEA/B [1] OPMODEA/B [0] Output Bank A / Bank B Mode 0 0 LVPECL 0 1 LVDS 1 0 HCSL 1 1 Hi-Z Table 3: Reference output enable function Sync_OE Ref_Out 0 Hi-Z 1 Output enabled Table 4: Illegal input level function Input illegal status Output status Input open Logic Low Input both high Logic Low Input both low Logic Low PI6C49S1510A Document Number DS40482 Rev 2-2 3 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Note: Storage temperature....................................................-55 to +150C Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Supply Voltage to Ground Potential (VDD, VDDO).... -0.5 to +4.6V Inputs (Referenced to GND).............................. -0.5 to VDD+0.5V Clock Output (Referenced to GND)................. -0.5 to VDD+0.5V Latch up...................................................................................200mA ESD Protection (Input)................................... 2000 V min (HBM) Junction Temperature .................................................. 125 C max Power Supply Characteristics and Operating Conditions Symbol Parameter VDD Core Supply Voltage VDDO Output Supply Voltage IDD Core Power Supply Current IDDO Test Condition Output Power Supply Current Min. Typ. Max. Units 2.375 3.465 V 2.375 3.465 V 90 120 All LVPECL outputs unloaded 150 190 All LVDS outputs loaded 110 130 All HCSL outputs unloaded 80 120 mA TA Ambient Operating Temperature1 -40 85 C TB PCB Operating Temperature -40 105 C 1 Note 1: Either TA or TB used as operating condition DC Electrical Specifications - Differential Inputs Symbol Parameter Test Condition IIH Input High current Input = VDD IIL Input Low current Input = GND CIN Input capacitance VIH Input high voltage VIL Input low voltage -0.3 VID Input Differential Amplitude PK-PK 0.15 VDD -0.85 V VCM Common model input voltage GND + 0.5 VDD -0.85 V ISOMUX MUX isolation PI6C49S1510A Document Number DS40482 Rev 2-2 Min. Typ. Max. Units 150 uA -150 uA 3 PF V VDD+0.3 V -89 4 www.diodes.com dBc January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A DC Electrical Specifications - LVCMOS Inputs Symbol Parameter Conditions Min. Typ. Max. Units IIH Input High current Input = VDD 150 uA IIL Input Low current Input = GND -150 VIH Input high voltage VDD =3.3V 2.0 VDD+0.3 V VIL Input low voltage VDD =3.3V -0.3 0.8 V VIH Input high voltage VDD =2.5V 1.7 VDD+0.3 V VIL Input low voltage VDD =2.5V -0.3 0.7 V Max. Units uA DC Electrical Specifications- LVPECL Outputs Parameter Description Conditions Min. Typ. VOH Output High voltage VDDO -1.4 VDDO -0.9 V VOL Output Low voltage VDDO -2.2 VDDO -1.7 V Max. Units DC Electrical Specifications- LVDS Outputs Parameter Description Conditions Min. Typ. VOH Output High voltage 1.43 V VOL Output Low voltage 1.0 V Vocm Output commode voltage 1.25 V DVocm Change in Vocm between completely output states Ro Output impedance 85 50 mV 140 W Max. Units DC Electrical Specifications - HCSL Outputs Parameter Description VOH Output High voltage 520 900 mV VOL Output Low voltage -150 150 mV PI6C49S1510A Document Number DS40482 Rev 2-2 Conditions 5 Min. Typ. www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A DC Electrical Specifications - LVCMOS Output Parameter Description VOH Output High voltage VOL Output Low voltage VOH Output High voltage VOL Output Low voltage R IUT Output Impedance Conditions Min. Typ. Max. Units VDDO =3.3V +/-5%, IOH = 8mA 2.3 V VDDO =2.5V +/- 5%, IOH = 8mA 1.5 V VDDO =3.3V +/-5%, IOL = -8mA 0.5 V VDDO =2.5V +/- 5%, IOL = -8mA 0.4 V VDDO =3.3V +/-5%, IOH = 24mA 2.1 V VDDO =2.5V +/- 5%, IOH = 16mA 1.5 V VDDO =3.3V +/-5%, IOL = -24mA 1 V VDDO =2.5V +/- 5%, IOL = -16mA VDDO = 3.3V 5% 0.8 V 17 VDDO = 2.5V 5% 22 AC Electrical Specifications - Differential Outputs Parameter Description FOUT Clock output frequency Tr Tf TODC Output rise time Output fall time Output duty cycle Conditions Min. 1500 HCSL 250 LVPECL 120 150 300 LVDS 120 150 300 HCSL 300 LVPECL 120 150 300 LVDS 120 150 300 HCSL 300 700 Frequency<650MHz, VID 400mV LVPECL, HCSL (<250MHz) 48 52 LVDS 47 53 Frequency<1GHz, LVPECL 45 55 VID 400mV LVDS 45 55 LVDS 40 60 LVPECL 40 60 LVPECL outputs @ <1GHz 500 1100 LVPECL outputs @ >1GHz 400 1000 LVDS outputs @ <1GHz 250 600 LVDS outputs @ >1GHz 250 550 From 20% to 80% From 80% to 20% VID 400mV Frequency<1.5GHz, VID 400mV Output swing Single-ended PI6C49S1510A Document Number DS40482 Rev 2-2 Max. LVPECL, LVDS Frequency<1.5GHz, VPP Typ. 6 Units MHz ps 700 www.diodes.com ps % mV January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A AC Electrical Specifications - Differential Outputs Cont. Parameter Description Tj Buffer additive jitter RMS VCROSS Conditions Min. Typ. Max. Units 156.25MHz, 12kHz to 20MHz 0.02 ps 156.25MHz, 10kHz to 1MHz 0.01 ps Absolute crossing voltage HCSL 460 mV DVCROSS Total variation of crossing voltage HCSL TSK Output Skew 10 outputs devices, outputs in same tank, with same load, at DUT. 15 TPD Propagation Delay LVPECL, LVDS @ 3.3V, 100MHz 570 ps HCSL @ 3.3V, 100MHz 900 ps TOD Valid to HiZ 80 ns TOE HiZ to valid 80 ns TP2P Skew Part to Part Skew1 120 ps 80 140 mV 40 ps AC Electrical Specifications - CMOS Parameter Description FOUT Ref_Out frequency Tj Buffer additive jitter RMS tr/ tf Conditions Min. XTAL input 10 Typ. Reference input Max. Units 50 MHz 200 MHz XTAL input 0.3 ps Reference input 0.03 ps Rise time, Fall time CL = 10pF 1.5 ns TODC Output duty cycle CL = 10pF tPD Propagation delay 3.3V, 25MHz tS Setup time tSOD Clock edge to output disable Ref_Out 2 4 cycles tSOE Clock edge to output enable Ref_Out 2 4 cycles 45 55 2200 % ps 300 ps Notes: 1. This parameter is guaranteed by design PI6C49S1510A Document Number DS40482 Rev 2-2 7 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Crystal Characteristics Parameter Min. Max. Units 50 MHz Equivalent Series Resistance (ESR) 70 Shunt Capacitance 7 pF 18 pF 500 W Mode of Oscillation Frequency Range Load Capacitance Typ. Fundamental 10 10 Drive Level Recommended Crystals Pericom recommends: a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf b) FY2500091, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm http://www.pericom.com/pdf/datasheets/se/FL.pdf PI6C49S1510A Document Number DS40482 Rev 2-2 8 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Propagation Delay Output Skew Output Skew TSK Propagation Delay TPD VOH IN+/IN- IN+/IN- tPD tPD TPLHx VOH CLKn VOH VOL TSK TSK QA/QB VOL TPHLx VOH VOL tR CLKn+1 tF VOL TPLHy TPHLy TSK = TPLHy - TPLHx or TSK = TPHLy - TPHLx TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1 Part to Part Skew Part-to-Part Skew VOH IN+/IN- TPLH1 TPHL1 Part1 CLK VOL VOH VOL TSK TSK Part2 CLK VOH VOL TPLH2 TPHL2 TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1 PI6C49S1510A Document Number DS40482 Rev 2-2 9 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A LVPECL/ LVDS Output Swing vs. Frequency LVDS VPP vs Frequency 600 800 500 VPP (mV) VPP (mV) LVPECL VPP vs Frequency 1000 600 400 200 400 300 200 100 0 0 25 100 125 312.5 625 1000 1500 25 Frequency (MHz) 2.5V LVPECL 100 125 312.5 625 1000 1500 Frequency (MHz) 3.3V LVPECL 2.5V LVDS 3.3V LVDS Propagation Delay vs Temperature Propagation Delay (ps) Propagation Delay vs Temperature 1800 1600 1400 1200 1000 800 600 400 200 0 -40 25 85 Temperature (C) LVPECL LVDS HCSL CMOS 1.5GHz LVPECL/ LVDS Waveform 2.5V LVPECL Waveform 3.3V LVPECL Waveform 2.5V LVDS Waveform 3.3V LVDS Waveform PI6C49S1510A Document Number DS40482 Rev 2-2 10 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Phase Noise and Additive Jitter Output phase noise (Dark Blue) vs Input Phase noise (light blue) Additive jitter is calculated at 156.25MHz~27fs RMS (12kHz to 20MHz). Additive jitter = (Output jitter2 - Input jitter2) Total phase jitter with 25MHz XTAL ~ 264fs RMS (12kHz ~20MHz) Configuration Test Load Board Termination for LVPECL/ LVDS Outputs LVPECL/ LVDS Buffer VDDQx Z o = 50 L = 0 ~ 10 in. 100 Z o = 50 150* 150* *Remove for LVDS PI6C49S1510A Document Number DS40482 Rev 2-2 11 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Configuration Test Load Board Termination for HCSL Outputs Rs 33 5% DUT Clock TLA Rs 33 5% Clock# TLB 475 1% Rp 49.9 1% Rp 49.9 1% 2pF 5% 2pF 5% Configuration Test Load Board Termination for LVCMOS Outputs 3.3V 5% VDD VDDO 10pF GND PI6C49S1510A Document Number DS40482 Rev 2-2 12 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Application Information Wiring the differential input to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609. VDD R1 Single Ended Clock Input 1K CLK /CLK C1 0.1 R2 1K Figure 1. Single-ended input to Differential input device Power Supply Filtering Techniques As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias, and 0.1F an 1F bypass capacitors should be used for each pin. VDD VDD 0.1F 1F VDDO VDDO 0.1F PI6C49S1510A Document Number DS40482 Rev 2-2 13 1F www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Single Ended Input, AC couple Driving X1 with a Single Ended Input CMOS Clock Rs 0.1F 0.1F 50 X1 CMOS Clock Input 50 Rs 0.1F 0.1F 50 50 X2 Differential Clock Input 0.1F Single Ended Input, DC couple Single Ended Input, DC couple VDD CMOS Clock 100 Rs VDD 100 Rs CMOS Clock 50 50 Differential Clock Input Differential Clock Input 0.1F 0.1F LVPECL, DC Couple, Thevenin Equivalent LVPECL, AC Couple, Thevenin Equivalent VDDO VDDO QAn+/ QBn+ LVPECL Driver QAn-/ QBn- RPU 0.1F RT 100 Differential VDDO RPD 0.1F RPU QAn+/ QBn+ LVPECL Driver Clock Input 100 Differential VDDO RPD LVPECL Receiver RPU RPU QAn-/ QBn- RT RPD VDDO RT VDDO RPU RPD RPU RPD 3.3V 120 82 3.3V 160 120 82 2.5V PI6C49S1510A Document Number DS40482 Rev 2-2 91 RPD 2.5V 250 62.5 250 62.5 14 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A LVDS DC Couple LVDS AC Couple at Load 0.1F QAn+/ QBn+ QAn+/ QBn+ LVDS Driver 100 Differential 100 LVDS Receiver k LVDS Driver QAn-/ QBn- 100 Differential Vbias 100 k QAn-/ QBn- LVDS AC Couple with Internal Termination 0.1F Single Ended LVPECL, DC Couple VDDO - 2V QAn+/ QBn+ 0.1F 50 QAn+/ QBn+ 50 LVDS Driver 100 Differential LVPECL Driver Vbias 50 QAn-/ QBn- 50 0.1F QAn-/ QBn- Single Ended LVPECL, DC Couple, Thevenin Equivalent VDDO - 2V 50 Single Ended LVPECL, AC Couple, Thevenin Equivalent VDDO QAn+/ QBn+ RPU QAn+/ QBn+ LVPECL Driver 50 VDDO LVPECL Driver RPD VDDO RPU RPD RPU 3.3V 120 82 QAn-/ QBn- 2.5V 250 62.5 QAn-/ QBn- 0.1F Load 50 RT 50 0.1F VDDO RT 3.3V 160 RT 50 2.5V 91 RPD PI6C49S1510A Document Number DS40482 Rev 2-2 15 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A LVPECL/ LVDS AC and DC input Clock IC Crystal Input Guide *Remove for LVDS Clock IC 0.1uF (For AC Couple Only) Rf C_in Driver C_out XTL_IN 150* Input XTL_OUT Cb Crystal (CL) C1 PI6C49S1510A Document Number DS40482 Rev 2-2 100 Differential 100 IN+ 150* Cb IN0.1uF (For AC Couple Only) C2 16 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Clock IC Crystal loading cap. design guide CL =crystal spec. loading cap. Clock IC C_in/out = (3~5pF) of IC pin cap. Rf Cb = PCB trace (2~4pF) C_in C_out XTL_IN C1,C2 = load cap. of design XTL_OUT Cb Crystal (CL) C1 Rd = 50 to 100ohm drive level limit Cb C2 Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm Example1: Select CL=18 pF crystal, C1=C2=2*(18pF) - (4pF+5pF)=27pF, check datasheet too Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do fine tune of C1, C2 for more accurate ppm if necessary Thermal Information Symbol Description JA Junction-to-ambient thermal resistance JC Junction-to-case thermal resistance Condition 23.65 C/W Still air 9.10 C/W Part Marking ZD Package PI6C49S 1510AZDIE YYWWXX PI6C49S1510A Document Number DS40482 Rev 2-2 YY : Year WW : Workweek 1st X : Assembly Site Code 2nd X : Wafer Site Code 17 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A Packaging Mechanical: 48-TQFN (ZD) 16-0151 For latest package info. please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/ Ordering Information Ordering Code PI6C49S1510AZDIEX Package Code Package Type ZD Operating Temperature 48-Contact, Very Thin Quad Flat No-Lead (TQFN) -40 C to 85 C Notes: 1. EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. All applicable RoHS exemptions applied. 2. See http://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated's definitions of Halogen- and Antimony-free, "Green" and Lead-free. Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/ 3. E = Pb-free and Green 4. X suffix = Tape/Reel PI6C49S1510A Document Number DS40482 Rev 2-2 18 www.diodes.com January 2018 (c) Diodes Incorporated A product Line of Diodes Incorporated PI6C49S1510A IMPORTANT NOTICE DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION). 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Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems. Copyright (c) 2016, Diodes Incorporated www.diodes.com PI6C49S1510A Document Number DS40482 Rev 2-2 19 www.diodes.com January 2018 (c) Diodes Incorporated