PI6C49S1510AZDIEX - DIODES INC - Datasheet.Directory

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

Features

 10 dierential outputs with 2 banks

 User congurable output signaling standard for each bank:

LVDS or LVPECL or HCSL

 LVCMOS reference output up to 200MHz

 Up to 1.5GHz output frequency for dierential outputs

 Ultra low additive phase jitter: < 0.02 ps (typ) (dierential

156.25MHz, 12KHz to 20MHz integration range); < 0.01 ps

(typ) (dierential 156.25MHz, 10kHz to 1MHz integration

range)

 Selectable reference inputs support either single-ended

or dierential or Xtal

 Low skew between outputs within banks (<40ps)

 Low delay from input to output (Tpd typ. < 0.9ns)

 Separate Input output supply voltage for level shiing

 2.5V / 3.3V power supply

 Industrial temperature support

 TQFN-48 package

Block Diagram Pin Configuration (48-TQFN)

Description

e PI6C49S1510A is a high performance fanout buer device-

which supports up to 1.5GHz frequency. It also integrates a

unique feature with user congurable output signaling standards

on per bank basis which provide great exibilities to users. e

device also uses Pericom's proprietary input detection technique

to make sure illegal input conditions will be detected and re-

ected by output states. is device is ideal for systems that need

to distribute low jitter clock signals to multiple destinations.

Applications

 Networking systems including switches and Routers

 High frequency backplane based computing and telecom

platforms

QBO+

QBO-

QB1+

QB1-

VDDO

QB2+

QB2-

VDDO

QB3+

QB3-

QB4+

QB4-

GND

OPMODEA_0

VDD

GND

IN_SEL_0

IN0+

IN0-

IN_SEL_1

OPMODEB_0

GND

OPMODEA_1

Sync_OE

VDDO

Ref_Out

GND

VDD

IN1+

IN1-

OPMODEB_1

Iref

GND

QAO+

QAO-

QA1+

QA1-

VDDO

QA2+

QA2-

VDDO

QA3+

QA3-

QA4+

QA4-

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

OSC

QA[0:4]

QB[0:4]

Ref_Out

OPMODEA[1:0]

OPMODEB[1:0]

IN_SEL[1:0]

Sync_OE

Iref

IN1-

IN1+

IN0+

IN0-

Sync

A product Line of

Diodes Incorporated

PI6C49S1510A

High Performance Differential Fanout Buffer

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Pin # Pin Name Type Description

1,2 QA0+

QA0- Output Bank A dierential output pair 0. Pin selectable LVPECL/LVDS/HCSL

interface levels.

3,4 QA1+ Output Bank A dierential output pair 1. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QA1-

5,8,29,32,45 VDDO Power Power supply pins for IO

6,7 QA2+ Output Bank A dierential output pair 2. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QA2-

9,10 QA3+ Output Bank A dierential output pair 3. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QA3-

11,12 QA4+ Output Bank A dierential output pair 4. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QA4-

13,18,24,37,43,48 GND Power Power supply ground

14,47 OPMODEA Input Pulldown Output mode select for Bank A. See Table 2 for functions, LVCMOS/

LVTTL interface levels

15,42 VDD Power Power supply pins

16 X1 Input XTAL input, can also be used as single ended input pin

17 X2 Output XTAL output. If X1 is used as a single ended input pin, X2 is to be le

open

19,22 IN_SEL Input Pulldown Input clock sele ct. See Table 1 for function. LVCMOS/LVTTL interface

levels.

20 IN0+ Input Pulldown Reference input 0

21 IN0- Input Pull-up/

Pulldown Inverted reference input 0, internal bias to VDD/2

23,39 OPMODEB Input Pulldown Output mode select for Bank B. See Table 2for functions, LVCMOS/

LVTTL interface levels

26,25 QB4+ Output Bank B dierential output pair 4. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QB4-

28,27 QB3+ Output Bank B dierential output pair 3. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QB3-

31,30 QB2+ Output Bank B dierential output pair 2. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QB2-

34,33 QB1+ Output Bank B dierential output pair 1. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QB1-

Pin Description

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Pin # Pin Name Type Description

36,35 QB0+ Output Bank B dierential output pair 0. Pin selectable LVPECL/LVDS/HCSL

interface levels.

QB0-

38 Iref Output

A xed precision resistor (475ohm) from this pin to ground provides a

reference current for HCSL mode. If LVPECL or LVDS mode chosen,

pin can be le open

40 IN1- Input Pull-up/

Pulldown Inverted reference input, internal bias to VDD/2

41 IN1+ Input Pulldown Reference input 1

44 Ref_Out Output Reference output, CMOS

46 Sync_OE Input Pulldown Synchronous output enable for Ref_Out, see Table 3 for functions

Function Table

Pinout Description Cont.

Table 1: Input select function

IN_SEL [1] IN_SEL [0] Function

0 0 IN0 is the selected reference input

0 1 IN1 is the selected reference input

1 X XTAL is the selected input

Table 2: Output Mode select function

OPMODEA/B [1] OPMODEA/B [0] Output Bank A / Bank B Mode

0 0 LVPECL

0 1 LVDS

1 0 HCSL

1 1 Hi-Z

Table 3: Reference output enable function

Sync_OE Ref_Out

0Hi-Z

1Output enabled

Table 4: Illegal input level function

Input illegal status Output status

Input open Logic Low

Input both high Logic Low

Input both low Logic Low

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

DC Electrical Specifications - Differential Inputs

Symbol Parameter Test Condition Min. Ty p. Max. Units

IIH Input High current Input = VDD 150 uA

IIL Input Low current Input = GND -150 uA

CIN Input capacitance 3PF

VIH Input high voltage VDD+0.3 V

VIL Input low voltage -0.3 V

VID Input Dierential Amplitude

PK-PK 0.15 VDD-0.85 V

VCM Common model input voltage GND + 0.5 VDD-0.85 V

ISOMUX MUX isolation -89 dBc

Power Supply Characteristics and Operating Conditions

Symbol Parameter Test Condition Min. Ty p. Max. Units

VDD Core Supply Voltage 2.375 3.465 V

VDDO Output Supply Voltage 2.375 3.465 V

IDD Core Power Supply Current 90 120

IDDO Output Power Supply Current

All LVPECL outputs unloaded 150 190

All LVDS outputs loaded 110 130

All HCSL outputs unloaded 80 120

TAAmbient Operating Temperature1-40 85 °C

TBPCB Operating Temperature1-40 105 °C

Note 1: Either TA or TB used as operating condition

Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)

Note:

Stresses greater than those listed under MAXIMUM

RATINGS may cause permanent damage to the device. is

is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in

the operational sections of this specication is not implied.

Exposure to absolute maximum rating conditions for ex-

tended periods may aect reliability.

Storage temperature ...................................................-55 to +150ºC

Supply Voltage to Ground Potential (VDD, VDDO) ... -0.5 to +4.6V

Inputs (Referenced to GND) ............................. -0.5 to VDD+0.5V

Clock Output (Referenced to GND)................. -0.5 to VDD+0.5V

Latch up ..................................................................................200mA

ESD Protection (Input) ..................................2000 V min (HBM)

Junction Temperature ................................................. 125 °C max

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

DC Electrical Specifications- LVPECL Outputs

Parameter Description Conditions Min. Typ. Max. Units

VOH Output High voltage VDDO-1.4 VDDO-0.9 V

VOL Output Low voltage VDDO-2.2 VDDO-1.7 V

DC Electrical Specifications - LVCMOS Inputs

Symbol Parameter Conditions Min. Ty p. Max. Units

IIH Input High current Input = VDD 150 uA

IIL Input Low current Input = GND -150 uA

VIH Input high voltage VDD=3.3V 2.0 VDD+0.3 V

VIL Input low voltage VDD=3.3V -0.3 0.8 V

VIH Input high voltage VDD=2.5V 1.7 VDD+0.3 V

VIL Input low voltage VDD=2.5V -0.3 0.7 V

Parameter Description Conditions Min. Typ. Max. Units

VOH Output High voltage 1.43 V

VOL Output Low voltage 1.0 V

Vocm Output commode voltage 1.25 V

DVocm Change in Vocm between com-

pletely output states 50 mV

Ro Output impedance 85 140 W

DC Electrical Specifications- LVDS Outputs

Parameter Description Conditions Min. Typ. Max. Units

VOH Output High voltage 520 900 mV

VOL Output Low voltage -150 150 mV

DC Electrical Specifications – HCSL Outputs

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Parameter Description Conditions Min. Typ. Max. Units

VOH Output High voltage VDDO=3.3V +/-5%, IOH = 8mA 2.3 V

VDDO=2.5V +/- 5%, IOH = 8mA 1.5 V

VOL Output Low voltage VDDO=3.3V +/-5%, IOL = -8mA 0.5 V

VDDO=2.5V +/- 5%, IOL = -8mA 0.4 V

VOH Output High voltage VDDO=3.3V +/-5%, IOH = 24mA 2.1 V

VDDO=2.5V +/- 5%, IOH = 16mA 1.5 V

VOL Output Low voltage VDDO=3.3V +/-5%, IOL = -24mA 1 V

VDDO=2.5V +/- 5%, IOL = -16mA 0.8 V

RIUT Output Impedance

DDO

= 3.3V ± 5%

DDO

= 2.5V ± 5%

AC Electrical Specifications – Differential Outputs

Parameter Description Conditions Min. Typ. Max. Units

FOUT Clock output frequency LVPECL, LVDS 1500 MHz

HCSL 250

TrOutput rise time From 20% to 80%

LVPECL 120 150 300

psLVDS 120 150 300

HCSL 300 700

TfOutput fall time From 80% to 20%

LVPECL 120 150 300

psLVDS 120 150 300

HCSL 300 700

TODC Output duty cycle

Frequency<650MHz,

VID ≥ 400mV

LVPECL,

HCSL

(<250MHz)

48 52

LVDS 47 53

Frequency<1GHz,

≥ 400mV

LVPECL 45 55

LVDS 45 55

Frequency<1.5GHz,

≥ 400mV LVDS 40 60

Frequency<1.5GHz, VID

≥ 400mV LVPECL 40 60

VPP Output swing Single-ended

LVPECL outputs @ <1GHz 500 1100

LVPECL outputs @ >1GHz 400 1000

LVDS outputs @ <1GHz 250 600

LVDS outputs @ >1GHz 250 550

DC Electrical Specifications – LVCMOS Output

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Parameter Description Conditions Min. Typ. Max. Units

TjBuer additive jitter RMS 156.25MHz, 12kHz to 20MHz 0.02 ps

156.25MHz, 10kHz to 1MHz 0.01 ps

VCROSS Absolute crossing voltage HCSL 460 mV

DVCROSS Total variation of crossing

voltage HCSL 140 mV

TSK Output Skew

10 outputs devices, out-

puts in same tank, with

same load, at DUT.

15 40 ps

TPD Propagation Delay LVPECL, LVDS @ 3.3V, 100MHz 570 ps

HCSL @ 3.3V, 100MHz 900 ps

TOD Valid to HiZ 80 ns

TOE HiZ to valid 80 ns

TP2P Skew Part to Part Skew180 120 ps

Parameter Description Conditions Min. Typ. Max. Units

FOUT Ref_Out frequency XTAL input 10 50 MHz

Reference input 200 MHz

TjBuer additive jitter RMS XTAL input 0.3 ps

Reference input 0.03 ps

tr/ tfRise time, Fall time CL = 10pF 1.5 ns

TODC Output duty cycle CL = 10pF 45 55 %

tPD Propagation delay 3.3V, 25MHz 2200 ps

tSSetup time 300 ps

tSOD Clock edge to output disable Ref_Out 2 4 cycles

tSOE Clock edge to output enable Ref_Out 2 4 cycles

AC Electrical Specifications – CMOS

Notes:

1. is parameter is guaranteed by design

AC Electrical Specifications – Differential Outputs Cont.

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Crystal Characteristics

Parameter Min. Typ. Max. Units

Mode of Oscillation Fundamental

Frequency Range 10 50 MHz

Equivalent Series Resistance (ESR) 70 Ω

Shunt Capacitance 7 pF

Load Capacitance 10 18 pF

Drive Level 500 µW

Recommended Crystals

Pericom recommends:

a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm

http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf

b) FY2500091, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm

http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf

c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm

http://www.pericom.com/pdf/datasheets/se/FL.pdf

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

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PI6C49S1510A

Output Skew

IN+/IN- T

PLHx

CLKn

Output Skew T

CLKn+1

PLHy

PHLy

PHLx

PLHy

PLHx

PHLy

PHLx

Propagation Delay

IN+/IN- tPD

QA/QB

Propagation Delay T

tPD

VOH

VOL

TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1

Part to Part Skew

IN+/IN- T

PLH1

Part1 CLK

Part-to-Part Skew

Part2 CLK

PLH2

PHL2

PHL1

PLH2

PLH1

PHL2

PHL1

PI6C49S1510A

Document Number DS40482 Rev 2-2

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A product Line of

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PI6C49S1510A

200

400

600

800

1000

1200

1400

1600

1800

-40 25 85

Propagation Delay (ps)

Temperature (°C)

Propagation Delay vs Temperature

LVPECL LVDS HCSL CMOS

LVPECL/ LVDS Output Swing vs. Frequency

1.5GHz LVPECL/ LVDS Waveform

2.5V LVPECL Waveform

2.5V LVDS Waveform

3.3V LVPECL Waveform

3.3V LVDS Waveform

200

400

600

800

1000

25 100 125 312.5 625 1000 1500

VPP (mV)

Frequency (MHz)

LVPECL VPP vs Frequency

2.5V LVPECL 3.3V LVPECL

100

200

300

400

500

600

25 100 125 312.5 625 1000 1500

VPP (mV)

Frequency (MHz)

LVDS VPP vs Frequency

2.5V LVDS 3.3V LVDS

Propagation Delay vs Temperature

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Phase Noise and Additive Jitter

Output phase noise (Dark Blue) vs Input Phase noise (light blue)

Additive jitter is calculated at 156.25MHz~27fs RMS (12kHz to 20MHz). Additive jitter = √(Output jitter2 - Input jitter2)

Configuration Test Load Board Termination for LVPECL/ LVDS Outputs

100Ω

Z = 50Ω

150Ω*

LVPECL/ LVDS Buffer

DDQx

L = 0 ~ 10 in.

*Remove for LVDS

Total phase jitter with 25MHz XTAL ~ 264fs RMS (12kHz ~20MHz)

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Configuration Test Load Board Termination for HCSL Outputs

33Ω

49.9Ω

475Ω

49.9Ω

2pF

Clock#

Clock

TLA

TLB

DUT

3.3V ±5%

VDD

VDDO

10pF

GND

Configuration Test Load Board Termination for LVCMOS Outputs

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

Diodes Incorporated

PI6C49S1510A

Application Information

Wiring the differential input to accept single ended levels

Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is gener-

ated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and

R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is

only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.

Figure 1. Single-ended input to Differential input device

Single Ended

Clock Input

VDD

0.1µ

CLK

/CLK

Power Supply Filtering Techniques

As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. All power pins should be individually connected to the power supply plane through vias, and 0.1μF

an 1μF bypass capacitors should be used for each pin.

0.1µF

0.1µF 1µF

DDO

1µF

DDO

PI6C49S1510A

Document Number DS40482 Rev 2-2

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A product Line of

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PI6C49S1510A

CMOS

Clock 50Ω

0.1µF

50Ω

Input

0.1µF

CMOS

Clock 50Ω

0.1µF

100Ω

Differential

Clock

Input

VDD

100Ω

LVPECL

Driver

RPD

QAn+/ QBn+

Clock

Input

VDDO

RPU

100Ω Differential

VDDO

RPU

RPD

QAn-/ QBn-

RPU RPDVDDO

3.3V

2.5V

120Ω

250Ω

82Ω

62.5Ω

0.1µF

160Ω

91Ω

CMOS

Clock 50Ω

0.1µF 0.1µF

0.1µF

50Ω

Differential

Clock

Input

LVPECL

Driver 100Ω Differential RPD

QAn+/ QBn+

LVPECL

Receiver

VDDO

RPU

VDDO

RPU

RPD

QAn-/ QBn-

RPU RPDVDDO

3.3V

2.5V

120Ω

250Ω

82Ω

62.5Ω

Driving X1 with a Single Ended Input Single Ended Input, AC couple

Single Ended Input, DC couple

LVPECL, AC Couple, Thevenin Equivalent LVPECL, DC Couple, Thevenin Equivalent

CMOS

Clock 50Ω

0.1µF

Differential

Clock

Input

Single Ended Input, DC couple

PI6C49S1510A

Document Number DS40482 Rev 2-2

www.diodes.com January 2018

A product Line of

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PI6C49S1510A

LVDS

Driver

100Ω Differential 100Ω LVDS

Receiver

QAn+/ QBn+

QAn-/ QBn-

LVDS

Driver 100Ω Differential

QAn+/ QBn+

QAn-/ QBn-

0.1µF

Vbias

50Ω

LVPECL

Driver

50Ω

QAn+/ QBn+

VDDO

QAn-/ QBn-

RPU RPDVDDO

3.3V

2.5V

120Ω

250Ω

82Ω

62.5Ω

VDDO

RPD

RPU

RPD

LVDS

Driver 100Ω Differential 100Ω

QAn+/ QBn+

QAn-/ QBn-

0.1µF

Vbias

kΩ

LVPECL

Driver

50Ω

QAn+/ QBn+

VDDO - 2V

50Ω

QAn-/ QBn- 50Ω

VDDO - 2V

LVPECL

Driver

50Ω

QAn+/ QBn+

QAn-/ QBn-

RTVDDO

3.3V

2.5V

160Ω

91Ω

50Ω

0.1µF

Load

LVDS DC Couple LVDS AC Couple at Load

LVDS AC Couple with Internal Termination Single Ended LVPECL, DC Couple

Single Ended LVPECL, DC Couple, Thevenin

Equivalent

Single Ended LVPECL, AC Couple, Thevenin

Equivalent

PI6C49S1510A

Document Number DS40482 Rev 2-2

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A product Line of

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PI6C49S1510A

Clock IC Crystal Input Guide

XTL_IN

C1 C2

Clock IC

XTL_OUT

Crystal (CL)

C_outC_in

Driver 100Ω Differential 100Ω Input

IN+

IN-

150Ω*

150Ω* 0.1uF

(For AC Couple Only)

0.1uF

(For AC Couple Only)

*Remove for LVDS

LVPECL/ LVDS AC and DC input

PI6C49S1510A

Document Number DS40482 Rev 2-2

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A product Line of

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PI6C49S1510A

Thermal Information

Symbol Description Condition

ΘJA Junction-to-ambient thermal resistance Still air 23.65 °C/W

ΘJC Junction-to-case thermal resistance 9.10 °C/W

Clock IC Crystal loading cap. design guide

XTL_IN

C1 C2

Clock IC

XTL_OUT

Crystal (CL)

C_outC_in

CL =crystal spec. loading cap.

C_in/out = (3~5pF) of IC pin cap.

Cb = PCB trace (2~4pF)

C1,C2 = load cap. of design

Rd = 50 to 100ohm drive level limit

Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm

Example1: Select CL=18 pF crystal, C1=C2=2*(18pF) – (4pF+5pF)=27pF, check datasheet too

Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do ne tune of C1, C2 for more accurate

ppm if necessary

PI6C49S

1510AZDIE

YYWWXX

YY : Year

WW : Workweek

1st X : Assembly Site Code

2nd X : Wafer Site Code

Part Marking

ZD Package

PI6C49S1510A

Document Number DS40482 Rev 2-2

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PI6C49S1510A

Packaging Mechanical: 48-TQFN (ZD)

Ordering Information

16-0151

Ordering Code Package Code Package Type Operating Temperature

PI6C49S1510AZDIEX ZD 48-Contact, Very in Quad Flat No-Lead (TQFN) -40 °C to 85 °C

Notes:

1. EU Directive 2002/95/EC (RoHS), 2011/65/EU (RoHS 2) & 2015/863/EU (RoHS 3) compliant. All applicable RoHS exemptions applied.

2. See http://www.diodes.com/quality/lead-free/ for more information about Diodes Incorporated’s denitions of Halogen- and Antimony-free, “Green” and Lead-free.

Thermal characteristics can be found on the company web site at www.diodes.com/design/support/packaging/

3. E = Pb-free and Green

4. X sufx = Tape/Reel

For latest package info.

please check: http://www.diodes.com/design/support/packaging/pericom-packaging/packaging-mechanicals-and-thermal-characteristics/

PI6C49S1510A

Document Number DS40482 Rev 2-2

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A product Line of

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PI6C49S1510A

IMPORTANT NOTICE

DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT

LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER

THE LAWS OF ANY JURISDICTION).

Diodes Incorporated and its subsidiaries reserve the right to make modications, enhancements, improvements, corrections or other changes without further no-

tice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or

any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer

or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all

the companies whose products are represented on Diodes Incorporated website, harmless against all damages.

Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.

Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes

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This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the nal and determi-

native format released by Diodes Incorporated.

LIFE SUPPORT

Diodes Incorporated products are specically not authorized for use as critical components in life support devices or systems without the express written approval

of the Chief Executive Ofcer of Diodes Incorporated. As used herein:

A. Life support devices or systems are devices or systems which:

1. are intended to implant into the body, or

2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably

expected to result in signicant injury to the user.

B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or to affect its safety or effectiveness.

Customers represent that they have all necessary expertise in the safety and regulatory ramications of their life support devices or systems, and acknowledge

and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated

products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by

Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes

Incorporated products in such safety-critical, life support devices or systems.