FN3973 Rev 6.00 Page 1 of 14
July 2004
FN3973
Rev 6.00
July 2004
HI5714
8-Bit, 40/60/75/80 MSPS A/D Converter
DATASHEET
The HI5714 is a high precision, monolithic, 8-bit, Analog-to-
Digital Converter fabricated in Intersil’ advanced HBC10
BiCMOS process.
The HI5714 is optimized for a wide range of applications such as
ultrasound imaging, mass storage, instrumentation, and video
digitizing, where accuracy and low power consumption are
essential. The HI5714 is offered in 40 MSPS, 60 MSPS, and 75
MSPS sample rates.
The HI5714 delivers 0.4 LSB differential nonlinearity while
consuming only 325mW power (Typical) at 75 MSPS. The
digital inputs and outputs are TTL compatible, as well as
allowing for a low-level sine wave clock input.
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . .40/60/75/80 MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325mW
• 7.65 ENOB at 4.43MHz
• Overflow/Underflow Three-State TTL Output
• Operates with Low Level AC Clock
• Very Low Analog Input Capacitance
• No Buffer Amplifier Required
• No Sample and Hold Required
• TTL Compatible I/O
• Pin-Compatible to Philips TDA8714
• Pb-free Available
Applications
• Video Digitizing
• QAM Demodulator
• Digital Cable Setup Box
• Tape Drive/Mass Storage
• Medical Ultrasound Imaging
• Communication Systems
Pinout
HI5714 (SOIC)
TOP VIEW
Ordering Information
PART
NUMBER
TEMP.
RANGE
(°C) PACKAGE
SAMPLING
FREQUENCY
(MHz)
PKG.
DWG. #
HI5714/4CB 0 to 70 24 Ld SOIC 40 M24.3
HI5714/4CBZ
(Note)
0 to 70 24 Ld SOIC
(Pb-free)
40 M24.3
HI5714/7CB-T 0 to 70 24 Ld SOIC
Tape & Reel
75 M24.3
HI5714/7CBZ-T
(Note)
0 to 70 24 Ld SOIC
Tape & Reel
(Pb-free)
75 M24.3
HI5714EVAL 25 Evaluation Board
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
1
2
3
4
5
6
7
8
9
10
11
12
D1
D0
NC
VRB
NC
AGND
VCCA
VIN
VRT
NC
O/UF
D7
16
17
18
19
20
21
22
23
24
15
14
13
D2
OE
VCCO2
OGND
VCCO1
DGND
D4
D5
D6
D3
VCCD
CLK
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
HI5714
FN3973 Rev 6.00 Page 2 of 14
July 2004
Functional Block Diagram
Typical Application Schematic
NOTES:
1. Pin 5 should be connected to AGND and pins 3 and 10 to DGND to reduce noise coupling into the device.
2. Analog and Digital supplies should be separated and decoupled to reduce digital noise coupling into the analog supply.
ANALOG TO DIGITAL
CONVERTER LATCHES TTL OUTPUTS
TTL OUTPUT
OVERFLOW/UNDERFLOW
LATCH
CLOCK DRIVER
VCCA CLK VCCD OE
VRT
VRB
OGND
AGND DGND
VCCO1
VCCO2
O/UF
VIN
1
2
4
6
7
8
9
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D7
D6
D5
D4
D3
D2
D1
D0
12
13
14
15
23
24
1
2
VRB
HI5714
VRT
CLK
DGND
NC
NC
AGND
VCCA
VCCD
D7
D6
D5
D4
D3
D2
D1
D0
as close to part as possible.
1nF and 0.1F CAPS are placed
CLOCK
VIN
NC
VIN
OGND
VCCO
VCCO
+5VA
O/UF
BNC
DGND AGND
OE
11
19
21
18
20
3
17
10
16
9
4
8
7
5
6
22
3.6V
1.3V
+5VA
+5VD
1nF 0.1F
1nF 0.1F
0.1
0.1
-
+
-
+
-
+
HI5714
FN3973 Rev 6.00 Page 3 of 14
July 2004
Absolute Maximum Ratings TA=25
oCThermal Information
VCCA, VCCD, VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
VCCA - VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
VCCO - VCCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
VCCA - VCCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
VIN, VCLK, VRT, VRB, OE . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
IOUT, Digital Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Input Current, All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OGND to VCCO
Operating Conditions
Temperature Range
HI5714/XCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Resistance (Typical, Note 1) JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VCCA = VCCD = VCCO = +5V; VRB = 1.3V; VRT = 3.6V; TA = 25oC, Unless Otherwise Specified
PARAMETER TEST CONDITION MIN TYP MAX UNITS
CLOCK (Referenced to DGND) (Note 2)
Logic Input Voltage Low, VIL 0-0.8V
Logic Input Voltage High, VIH 2.0 - VCCD V
Logic Input Current Low, IIL VCLK = 0.4V -400 - - A
Logic Input Current High, IIH VCLK = 2.7V - - 300 A
Input Impedance, ZIN fCLK = 75MHz (Note 9) - 2 - k
Input Capacitance, CIN fCLK = 75MHz (Note 9) - 4.5 - pF
OE (Referenced to DGND)
Logic Input Voltage Low, VIL 0-0.8V
Logic Input Voltage High, VIH 2.0 - VCCD V
Logic Input Current Low, IIL VIL = 0.4V -400 - - A
Logic Input Current High, IIH VIH = 2.7V - - 20 A
VIN (Referenced to AGND)
Input Current Low, IIL VIN = 1.2V - 0 - A
Input Current High, IIH VIN = 3.5V - 100 180 A
Input Impedance, ZIN fIN = 4.43MHz - 10 - k
Input Capacitance, CIN fIN = 4.43MHz - 14 - pF
REFERENCE INPUT
Bottom Reference Range, VRB 1.2 1.3 1.6 V
Top Reference Range, VRT 3.5 3.6 3.9 V
Reference Range, VREF (VRT - VRB) 1.9 2.3 2.7 V
Reference Current, IREF -10-mA
Reference Ladder Resistance, RLAD - 240 -
RLADTC -0.24-/oC
Bottom Offset Voltage, VOB (Note 5) - 255 - mV
VOBTC (Note 5) - 136 - V/oC
Top Offset Voltage, VOT (Note 5) - -300 - mV
VOTTC (Note 5) - 480 - V/oC
HI5714
FN3973 Rev 6.00 Page 4 of 14
July 2004
DIGITAL OUTPUTS (D0 to D7 and O/UF Referenced to OGND)
Logic Output Voltage Low, VOL IO = 1mA 0 - 0.4 V
Logic Output Voltage High, VOH IO = -0.4mA 2.7 - VCCO V
Output Leakage Current, ID0.4V < VOUT < VCCO -20 - +20 A
SWITCHING CHARACTERISTICS (Notes 4, 5) See Figure 1
Sample Rate, fCLK
HI5714/7 75 - - MHz
HI5714/4 40 - - MHz
Clock Pulse Width High, tCPH 6--ns
Clock Pulse Width Low, tCPL 6--ns
ANALOG SIGNAL PROCESSING (fCLK = 40MHz)
Differential Gain, DG (Notes 6, 9) - 1.0 - %
Differential Phase, DP (Notes 6, 9) - 0.05 - degree
HARMONICS (fCLK = 75MHz)
Second Harmonic, H2 fIN = 4.43MHz - -63 - dB
Third Harmonic, H3 fIN = 4.43MHz - -65 - dB
Total Harmonic Distortion, THD fIN = 4.43MHz - -59 - dB
Spurious Free Dynamic Range, SFDR fIN = 4.43MHz - 62 - dB
Analog Input Bandwidth (-3dB) - 18 - MHz
TRANSFER FUNCTION
Differential Linearity Error, DNL (Note 7) - 0.4 - LSB
Integral Linearity Error, INL (Note 7) - 0.75 - LSB
EFFECTIVE NUMBER OF BITS
ENOB
HI5714/4 (fCLK = 40MHz) fIN = 4.43MHz - 7.65 - Bits
fIN = 7.5MHz - 7.5 - Bits
HI5714/7 (fCLK = 75MHz) fIN = 4.43MHz - 7.4 - Bits
fIN = 7.5MHz - 7.15 - Bits
fIN = 10MHz - 6.8 - Bits
Bit Error Rate, BER (Note 8) - 10-11 -Times/
Sample
TIMING (fCLK = 75MHz) See Figures 1, 2
Sampling Delay, tSD --2ns
Output Hold Time, tHD 5--ns
Output Delay Time, tD HI5714/4/7 - 10 13 ns
Output Enable Delay, tPZH Enable to High - 14.6 - ns
Output Enable Delay, tPZL Enable to Low - 17.8 - ns
Output Disable Delay, tPHZ Disable from High - 5.3 - ns
Output Disable Delay, tPLZ Disable from Low - 6.7 - ns
Aperture Jitter, tAJ -50-ps
Electrical Specifications VCCA = VCCD = VCCO = +5V; VRB = 1.3V; VRT = 3.6V; TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
HI5714
FN3973 Rev 6.00 Page 5 of 14
July 2004
POWER SUPPLY CHARACTERISTICS
Analog Power Supply Range, VCCA 4.75 5.0 5.25 V
Digital Power Supply Range, VCCD 4.75 5.0 5.25 V
Output Power Supply Range, VCCO 4.75 5.0 5.25 V
Total Supply Current -6575mA
Supply Current, ICCA -30-mA
Supply Current, ICCD -26-mA
Supply Current, ICCO -9-mA
Power Dissipation - 325 375 mW
NOTES:
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
3. The supply voltages VCCA and VCCD may have any value between -0.3V and +6V as long as the difference VCCA - VCCD lies between
-0.3V and +0.3V.
4. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock not be less than 1ns.
5. Analog input voltages producing code 00 up to and including FF. VOB (Bottom Offset Voltage) is the difference between the analog input which
produces data equal to 00 and the Bottom Reference Voltage (VRB). VOBTC (Bottom Offset Voltage Temperature Coefficient) is the variation
of VOB with temperature. VOT (Top Offset Voltage) is the difference between the Top Reference Voltage (VRT) and the analog input which
produces data output equal to FF. VOTTC (Top Offset Voltage Temperature Coefficient) is the variation of VOT with temperature.
6. Input is standard 5 step video test signal. A 12-bit R reconstruct DAC and VM700 are used for measurement.
7. Full scale sinewave, fIN = 4.43MHz.
8. fCLK = 75MHz, fIN = 4.43MHz, VIN = 8 LSB at code 128, 50% Clock duty cycle.
9. Parameter is guaranteed by design, not production tested.
Electrical Specifications VCCA = VCCD = VCCO = +5V; VRB = 1.3V; VRT = 3.6V; TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
HI5714
FN3973 Rev 6.00 Page 6 of 14
July 2004
Timing Waveforms
FIGURE 1. INPUT-TO-OUTPUT TIMING
FIGURE 2. THREE-STATE TIMING CIRCUIT
ANALOG
INPUT
CLOCK
INPUT
DATA (D0-D7)
OUTPUTS tD
tDS
tHD
2.4V
1.4V
0.4V
1.4V
tCPL
tCPH
SAMPLE N SAMPLE N + 1
SAMPLE N + 2
DN - 2 DN - 1DN + 1
DN
OE
DIGITAL
OUTPUT
DIGITAL
OUTPUT
tPZL
tPZH
tPLZ
tPHZ
1.4V 1.4V
0V
0V
VOH
VOL
0.3V
0.3V
3.5V
INPUT
4V
HI5714
FN3973 Rev 6.00 Page 7 of 14
July 2004
Typical Performance Curves
FIGURE 3. TOTAL ICC vs TEMPERATURE FIGURE 4. INTEGRAL LINEARITY ERROR vs TEMPERATURE
FIGURE 5. DIFFERENTIAL LINEARITY ERROR vs
TEMPERATURE
FIGURE 6. REFERENCE RESISTANCE vs TEMPERATURE
FIGURE 7. VOT vs TEMPERATURE FIGURE 8. VOB vs TEMPERATURE
70
60
50
40
30
20
10
0
-40-30-20-10 0 1020304050607080
TEMPERATURE (oC)
mA
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-40-30-20-100 1020304050607080
TEMPERATURE (oC)
LSB
90
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1.0
-40-30-20-100 1020304050607080
TEMPERATURE (oC)
LSB
-0.2
-0.1
0
90
270
260
250
240
230
220
210
200
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (oC)
OHMS
280
-230
-240
-250
-260
-270
-280
-290
-320
-40-30-20-100 1020304050607080
TEMPERATURE (oC)
mV
-220
-300
-310
250
240
230
210
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (oC)
mV
260
220
HI5714
FN3973 Rev 6.00 Page 8 of 14
July 2004
Pin Descriptions
PIN NUMBER SYMBOL DESCRIPTION
1, 2, 12-15,
23, 24
D0 to D7 Digital Outputs, D0 (LSB) to D7 (MSB).
4V
RB Bottom Reference Voltage Input. Range: 1.2V to 1.6V.
6 AGND Analog Ground.
7V
CCA Analog +5V.
8V
IN Analog Input.
9V
RT Top Reference Voltage Input. Range: 3.5V to 3.9V.
11 O/UF Underflow/Overflow Digital Output. Goes high if the analog input goes above or below the
reference (VRB, VRT) minus the offset.
16 CLK Clock Input.
17 DGND Digital GND.
18 VCCD Digital +5V.
19, 21 VCCO1, VCCO2 Digital +5V for Digital Output Stage.
20 OGND Digital Ground for Digital Output Stage.
22 OE Output Enable
High: Digital outputs are three-stated.
Low: Digital outputs are active.
TABLE 1. A/D CODE TABLE
CODE
DESCRIPTION
(NOTE 1)
INPUT VOLTAGE
VRT = 3.6V
VRB = 1.3V O/UF
BINARY OUTPUT CODE
D7 D6 D5 D4 D3 D2 D1 D0
Underflow <1.555V 1 0 0 0 0 0 0 0 0
0 1.555V 0 0 0 0 0 0 0 0 0
1 - 0 --------
- - 0 --------
- - 0 --------
254 - 0 11111110
255 3.300V 0 1 1 1 1 1 1 1 1
Overflow >3.300V 1 1 1 1 1 1 1 1 1
NOTE:
10. The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage, including the typical
reference offset voltages.
TABLE 2. MODE SELECTION
OE D7 to D0 O/UF
1 High Impedance High Impedance
0 Active: Binary Active
HI5714
FN3973 Rev 6.00 Page 9 of 14
July 2004
Detailed Description
Theory of Operation
The HI5714 design utilizes a folding and interpolating
architecture. This architecture reduces the number of
comparators, reference taps, and latches, thereby reducing
power requirements, die size and cost.
A folding A/D converter operates basically like a 2 step
subranging converter by using 2 lower resolution converters
to do a course and subranged fine conversion. A more
complete description is given in the application note “Using
the HI5714 Evaluation Module” (AN9517).
Reference Input, VRT and VRB
The HI5714 requires an external reference to be connected
to pins 4 and 9, VRB and VRT.
It is recommended that adequate high frequency decoupling
be provided at the reference input pin in order to minimize
overall converter noise. A 0.1F and a 1nF capacitor as
close as possible to the reference pins work well.
VRT must be kept within the range of 3.5V to 3.9V and VRB
within 1.2V to 1.6V. If the reference voltages go outside their
respective ranges, the input folding amplifiers may saturate
giving erroneous digital data. The range for (VRT - VRB) is
1.9V to 2.7V, which defines the analog input range.
Digital Control and Clock Requirements
The HI5714 provides a standard high-speed interface to
external TTL logic families.
The outputs can be three-stated by setting the OE input (pin
22) high.
The clock input operates at standard TTL levels as well as a
low level sine wave around the threshold level. The HI5714
can operate with clock frequencies from DC to 75MHz. The
clock duty cycle should be 50% 10% to ensure rated
performance. Duty cycle variation, within the specified
range, has little effect on performance. Due to the clock
speed it is important to remember that clock jitter will affect
the quality of the digital output data.
The clock can be stopped at any time and restarted at a later
time. Once restarted the digital data will be valid at the
second rising edge of the clock plus the data delay time.
Digital Outputs and O/UF Output
The digital outputs are standard TTL type outputs. The
HI5714 can drive 1 to 3 TTL inputs depending on the input
current requirements.
Should the analog input exceed the top or bottom reference
the over/underflow output (pin 11) will go high. Should the
analog input exceed the top reference voltage, VRT, the
digital outputs will remain at all 1s until the analog input goes
below VRT. Also, should the analog input go below the
bottom reference voltage, VRB, the digital outputs will
remain at all 0s until the analog input goes above VRT.
Analog Input
The analog input will accept a voltage within the reference
voltage levels, VRB and VRT, minus some offset. The offset
is specified in the Electrical Specifications table.
The analog input is relatively high impedance (10k) but
should be driven from a low impedance source. The input
capacitance is low (14pF) and there is little kickback from the
input, so a series resistance is not necessary but it may help
to prevent the driving amplifier from oscillating.
The input bandwidth is typically 18MHz. Exceeding 18MHz
will result in sparkle at the digital outputs. The bandwidth
remains constant at clock rates up to 75MHz.
Supply and Ground Considerations
In order to keep digital noise out of the analog signal path,
the HI5714 has separate analog and digital supply and
ground pins. The part should be mounted on a board that
provides separate low impedance connections for the
analog and digital supplies and grounds.
The analog and digital grounds should be tied together at
one point near the HI5714. The grounds can be connected
directly, through an inductor (ferrite bead), or a low valued
resistor. DGND and AGND can be tied together. To help
minimize noise, tie pin 5 (NC) to AGND and pins 3 (NC) and
10 (NC) to DGND.
For best performance, the supplies to the HI5714 should be
driven by clean, linear regulated supplies. The board should
also have good high frequency leaded decoupling capacitors
mounted as close as possible to the converter. Capacitor
leads must be kept as short as possible (less than 1/2 inch
total length). A 0.1F and a 1nF capacitor as close as
possible to the pin works well. Chip capacitors will provide
better high frequency decoupling but leaded capacitors
appear to be adequate.
If the part is to be powered by a single supply, then the
analog supply pins should be isolated by ferrite beads from
the digital supply pins. This should help minimize noise on
the analog power pins.
Refer to Application Note AN9214, “Using Intersil High
Speed A/D Converters”, for additional considerations when
using high speed converters.
Increased Accuracy
Further calibration of the ADC can be done to increase
absolute level accuracy. First, a precision voltage equal to
the ideal VIN-FS + 0.5 LSB is applied at VIN. Adjust VRB
until the 0 to 1 transition occurs on the digital output. Next, a
voltage equal to the ideal VIN+FS - 1.5 LSB is applied at VIN.
VRT is then adjusted until the 254 to 255 transition occurs on
the digital output.
HI5714
FN3973 Rev 6.00 Page 10 of 14
July 2004
Applications
Figures 9 and 10 show two possible circuit configurations,
AC coupled with a DC restore circuit and DC coupled with a
DC offset amplifier.
Due to the high clock rate, FCT (TTL/CMOS) or FAST (TTL)
glue logic should be used. FCT logic will tend to have large
overshoots if not loaded. Long traces (>2 or 3 inches) should
be terminated to maintain signal integrity.
FIGURE 9. TYPICAL AC COUPLED INPUT WITH DC RESTORE
FIGURE 10. TYPICAL DC COUPLED INPUT
12
13
14
15
23
24
1
2
VRB
HI5714
VRT
CLK
DGND
NC
NC
AGND
VCCA
VCCD
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK
VIN
NC
VIN
OGND
VCCO
VCCO
+5VA
O/UF
OE
11
19
21
18
20
3
17
10
16
9
4
8
7
5
6
22
3.6V
1.3V
+5VA
+5VD
10 0.1
10 0.1
0.1
0.1
SAMPLE
PULSE
DC RESTORE
-
+
-
+
12
13
14
15
23
24
1
2
VRB
HI5714
VRT
CLK
DGND
NC
NC
AGND
VCCA
VCCD
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK
VIN
NC
VIN
OGND
VCCO
VCCO
+5VA
O/UF
OE
11
19
21
18
20
3
17
10
16
9
4
8
7
5
6
22
3.6V
1.3V
+5VA
+5VD
10 0.1
10 0.1
0.1
0.1
+5VA
OFFSET
-
+
-
+
-
+
HI5714
FN3973 Rev 6.00 Page 11 of 14
July 2004
Timing Definitions
Aperture Delay: Aperture delay is the time delay between
the external sample command (the rising edge of the clock)
and the time at which the signal is actually sampled. This
delay is due to internal clock path propagation delays.
Aperture Jitter: This is the RMS variation in the aperture
delay due to variation of internal clock path delays.
Data Latency
After the analog sample is taken, the data on the bus is
output at the next rising edge of the clock. This is due to the
output latch of the converter. This delay is specified as the
data latency. After the data latency time, the data
representing each succeeding sample is output at the
following clock pulse. The digital data lags the analog input
by 1 cycle.
Static Performance Definitions
Offset Error and Full-Scale Error use a measured value of
the external voltage reference to determine the ideal plus
and minus full-scale values. The results are all displayed in
LSBs.
Bottom Offset Voltage (VOB)
The first code transition should occur at a level 0.5 LSB
above the negative full-scale. Bottom offset voltage is
defined as the deviation of the actual code transition from
this point.
Top Offset Voltage (VOT)
The last code transition should occur for a analog input that
is 1.5 LSBs below positive full-scale. Top Offset Voltage is
defined as the deviation of the actual code transition from
this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB. The converter is guaranteed to have no
missing codes.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
FIGURE 11. 8-BIT VIDEO COMPONENTS
A/D D/A
DSP/P
REFERENCE
ICL8069
AMP AMP
HA5020 (Single)
HA5022 (Dual)
HA5024 (Quad)
HA5013 (Triple)
HFA1105 (Single)
HFA1205 (Dual)
HFA1405 (Quad)
HI5714 (8-Bit) HSP9501
HSP48410
HSP48908
HSP48901
HSP48212
HSP43881
HSP43168
HI1171 (8-Bit)
CA3338 (8-Bit)
HI5721 (10-Bit)
HA5020 (Single)
HA2842 (Single)
HFA1115 (Single)
HFA1212 (Dual)
HFA1412 (Quad)
CMOS Logic Available in FCT
HSP9501: Programmable Data Buffer
HSP48410: Histogrammer/accumulating Buffer, 10-Bit Pixel Resolution, 4K x 4K Frame Size
HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit
HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit
HSP48212: Video Mixer
HSP43881: Digital Filter, 30MHz, 1-D and 2-D Fir Filters
HSP43168: Dual Fir Filter, 10-Bit, 33/45MHz
HI3050 (10-Bit)
HI5714
FN3973 Rev 6.00 Page 12 of 14
July 2004
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5714. A low
distortion sine wave is applied to the input, it is sampled, and
the output is stored in RAM. The data is then transformed
into the frequency domain with a 2048 point FFT and
analyzed to evaluate the dynamic performance of the A/D.
The sine wave input to the part is 0.5dB down from full scale
for these tests. The distortion numbers are quoted in dBc
(decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to full scale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency excluding
DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
ENOB = (SINAD - 1.76) / 6.02
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the 2nd and 3rd
harmonic component respectively to the RMS value of the
measured input signal.
Full Power Input Bandwidth
Full power bandwidth is the frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has a peak-to-peak amplitude equal to
the difference between the top reference voltage input and
the bottom reference voltage input. The bandwidth given is
measured at the specified sampling frequency.
HI5714
FN3973 Rev 6.00 Page 13 of 14
July 2004
Die Characteristics
DIE DIMENSIONS:
134 mils x 134 mils x 19 mils 1 mil
METALLIZATION:
Type: AlSiCu
Thickness: M1 - 8kÅ, M2 - 17kÅ
SUBSTRATE POTENTIAL (POWERED UP):
GND (0.0V)
PASSIVATION:
Type: Sandwich Passivation* Undoped Silicon Glass
(USG) + Nitride
Thickness: USG - 8kÅ, Nitride - 4.2kÅ
Total 12.2kÅ + 2kÅ
WORST CASE CURRENT DENSITY:
1.6 x 104 A/cm2
TRANSISTOR COUNT:
3714
DIE ATTACH:
Silver Filled Epoxy
Metallization Mask Layout
HI5714
DO D1 D2 D3 OE
O/UF D7 D6 D5 D4
VRB
AGND
VCCA
VRT
VIN
VCC02
OGND
VCC01
DGND
VCCD
CLK
FN3973 Rev 6.00 Page 14 of 14
July 2004
HI5714
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2003-2004. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
0o8o0o8o-
Rev. 0 12/93
