Precision
Instrumentation Amplifier
AD524
Rev. F
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
Low noise: 0.3 μV p-p at 0.1 Hz to 10 Hz
Low nonlinearity: 0.003% (G = 1)
High CMRR: 120 dB (G = 1000)
Low offset voltage: 50 μV
Low offset voltage drift: 0.5 μV/°C
Gain bandwidth product: 25 MHz
Pin programmable gains of 1, 10, 100, 1000
Input protection, power-on/power-off
No external components required
Internally compensated
MIL-STD-883B and chips available
16-lead ceramic DIP and SOIC packages and 20-terminal
leadless chip carrier available
Available in tape and reel in accordance with EIA-481A
standard
Standard military drawing also available
FUNCTIONAL BLOCK DIAGRAM
AD524
20kΩ
– INPUT
G = 10
+ INPUT
G = 100
G = 1000
4.44kΩ
404Ω
40Ω
PROTECTION
20kΩ
20kΩ20kΩ
20kΩ20kΩ
SENSE
REFERENCE
PROTECTION
RG
1
RG
2
1
13
12
11
16
3
2
V
b
OUTPUT
00500-001
Figure 1.
GENERAL DESCRIPTION
The AD524 is a precision monolithic instrumentation amplifier
designed for data acquisition applications requiring high accu-
racy under worst-case operating conditions. An outstanding
combination of high linearity, high common-mode rejection,
low offset voltage drift, and low noise makes the AD524 suitable
for use in many data acquisition systems.
The AD524 has an output offset voltage drift of less than
25 μV/°C, input offset voltage drift of less than 0.5 μV/°C, CMR
above 90 dB at unity gain (120 dB at G = 1000), and maximum
nonlinearity of 0.003% at G = 1. In addition to the outstanding
dc specifications, the AD524 also has a 25 kHz bandwidth
(G = 1000). To make it suitable for high speed data acquisition
systems, the AD524 has an output slew rate of 5 V/μs and settles
in 15 μs to 0.01% for gains of 1 to 100.
As a complete amplifier, the AD524 does not require any exter-
nal components for fixed gains of 1, 10, 100 and 1000. For other
gain settings between 1 and 1000, only a single resistor is required.
The AD524 input is fully protected for both power-on and
power-off fault conditions.
The AD524 IC instrumentation amplifier is available in four
different versions of accuracy and operating temperature range.
The economical A grade, the low drift B grade, and lower drift,
higher linearity C grade are specified from −25°C to +85°C.
The S grade guarantees performance to specification over the
extended temperature range −55°C to +125°C. The AD524 is
available in a 16-lead ceramic DIP, 16-lead SBDIP, 16-lead SOIC
wide packages, and 20-terminal leadless chip carrier.
PRODUCT HIGHLIGHTS
1. The AD524 has guaranteed low offset voltage, offset
voltage drift, and low noise for precision high gain
applications.
2. The AD524 is functionally complete with pin program-
mable gains of 1, 10, 100, and 1000, and single resistor
programmable for any gain.
3. Input and output offset nulling terminals are provided for
very high precision applications and to minimize offset
voltage changes in gain ranging applications.
4. The AD524 is input protected for both power-on and
power-off fault conditions.
5. The AD524 offers superior dynamic performance with a
gain bandwidth product of 25 MHz, full power response of
75 kHz and a settling time of 15 μs to 0.01% of a 20 V step
(G = 100).
AD524
Rev. F | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 8
Connection Diagrams .................................................................. 8
ESD Caution .................................................................................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits ................................................................................. 14
Theory of Operation ...................................................................... 15
Input Protection .......................................................................... 15
Input Offset and Output Offset ................................................ 15
Gain .............................................................................................. 16
Input Bias Currents .................................................................... 17
Common-Mode Rejection ........................................................ 17
Grounding ................................................................................... 18
Sense Terminal ............................................................................ 18
Reference Terminal .................................................................... 18
Programmable Gain ................................................................... 20
Autozero Circuits ....................................................................... 20
Error Budget Analysis ................................................................ 21
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 25
REVISION HISTORY
11/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to General Description .................................................... 1
Changes to Figure 1 .......................................................................... 1
Changes to Figure 3 and Figure 4 Captions .................................. 8
Changes to Error Budget Analysis Section ................................. 21
Changes to Ordering Guide .......................................................... 25
4/99—Rev. D to Rev. E
AD524
Rev. F | Page 3 of 28
SPECIFICATIONS
@ VS = ±15 V, RL = 2 kΩ and TA = +25°C, unless otherwise noted.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical
test. Results from those tests are used to calculate outgoing quality levels.
Table 1.
AD524A AD524B
Parameter Min Typ Max Min Typ Max Unit
GAIN
Gain Equation (External Resistor Gain Programming)
%201
000,40 ±
⎥
⎦
⎤
⎢
⎣
⎡+
G
R %201
000,40 ±
⎥
⎦
⎤
⎢
⎣
⎡+
G
R
Gain Range (Pin Programmable) 1 to 1000 1 to 1000
Gain Error1
G = 1 ±0.05 ±0.03 %
G = 10 ±0.25 ±0.15 %
G = 100 ±0.5 ±0.35 %
G = 1000 ±2.0 ±1.0 %
Nonlinearity
G = 1 ±0.01 ±0.005 %
G = 10, G = 100 ±0.01 ±0.005 %
G = 1000 ±0.01 ±0.01 %
Gain vs. Temperature
G = 1 5 5 ppm/°C
G = 10 15 10 ppm/°C
G = 100 35 25 ppm/°C
G = 1000 100 50 ppm/°C
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage 250 100 μV
vs. Temperature 2 0.75 μV/°C
Output Offset Voltage 5 3 mV
vs. Temperature 100 50 μV
Offset Referred to the Input vs. Supply
G = 1 70 75 dB
G = 10 85 95 dB
G = 100 95 105 dB
G = 1000 100 110 dB
INPUT CURRENT
Input Bias Current ±50 ±25 nA
vs. Temperature ±100 ±100 pA/°C
Input Offset Current ±35 ±15 nA
vs. Temperature ±100 ±100 pA/°C
AD524
Rev. F | Page 4 of 28
AD524A AD524B
Parameter Min Typ Max Min Typ Max Unit
INPUT
Input Impedance
Differential Resistance 109 109 Ω
Differential Capacitance 10 10 pF
Common-Mode Resistance 109 109 Ω
Common-Mode Capacitance 10 10 pF
Input Voltage Range
Maximum Differential Input Linear (VDL)2
±10 ±10 V
Maximum Common-Mode Linear (VCM)2
⎟
⎠
⎞
⎜
⎝
⎛×− D
V
2
G
V12 ⎟
⎠
⎞
⎜
⎝
⎛×− D
V
2
G
V12 V
Common-Mode Rejection DC to 60 Hz with 1 kΩ Source Imbalance V
G = 1 70 75 dB
G = 10 90 95 dB
G = 100 100 105 dB
G = 1000 110 115 dB
OUTPUT RATING
VOUT, RL = 2 kΩ ±10 ±10 V
DYNAMIC RESPONSE
Small Signal – 3 dB
G = 1 1 1 MHz
G = 10 400 400 kHz
G = 100 150 150 kHz
G = 1000 25 25 kHz
Slew Rate 5.0 5.0 V/μs
Settling Time to 0.01%, 20 V Step
G = 1 to 100 15 15 μs
G = 1000 75 75 μs
NOISE
Voltage Noise, 1 kHz
RTI 7 7 nV/√Hz
RTO 90 90 nV√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 15 15 μV p-p
G = 10 2 2 μV p-p
G = 100, 1000 0.3 0.3 μV p-p
Current Noise
0.1 Hz to 10 Hz 60 60 pA p-p
SENSE INPUT
RIN 20 20 kΩ ± 20%
IIN 15 15 μA
Voltage Range ±10 ±10 V
Gain to Output 1 1 %
REFERENCE INPUT
RIN 40 40 kΩ ± 20%
IIN 15 15 μA
Voltage Range ±10 ±10 V
Gain to Output 1 1 %
AD524
Rev. F | Page 5 of 28
AD524A AD524B
Parameter Min Typ Max Min Typ Max Unit
TEMPERATURE RANGE
Specified Performance –25 +85 –25 +85 °C
Storage –65 +150 –65 +150 °C
POWER SUPPLY
Power Supply Range ±6 ±15 ±18 ±6
±15 ±18 V
Quiescent Current 3.5 5.0 3.5
5.0 mA
1 Does not include effects of external resistor, RG.
2 VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
VDL at the maximum = 10 V/G.
VD = actual differential input voltage.
Example: G = 10, VD = 0.50.
VCM = 12 V − (10/2 × 0.50 V) = 9.5 V.
@ VS = ±15 V, RL = 2 kΩ and TA = +25°C, unless otherwise noted.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical
test. Results from those tests are used to calculate outgoing quality levels.
Table 2.
AD524C AD524S
Parameter Min Typ Max Min Typ Max Unit
GAIN
Gain Equation (External Resistor Gain Programming)
%201
000,40 ±
⎥
⎦
⎤
⎢
⎣
⎡+
G
R %201
000,40 ±
⎥
⎦
⎤
⎢
⎣
⎡+
G
R
Gain Range (Pin Programmable) 1 to 1000 1 to 1000
Gain Error1
G = 1 ±0.02 ±0.05 %
G = 10 ±0.1 ±0.25 %
G = 100 ±0.25 ±0.5 %
G = 1000 ±0.5 ±2.0 %
Nonlinearity
G = 1 ±0.003 ±0.01 %
G = 10, G = 100 ±0.003 ±0.01 %
G = 1000 ±0.01 ±0.01 %
Gain vs. Temperature
G = 1 5 5 ppm/°C
G = 10 10 10 ppm/°C
G = 100 25 25 ppm/°C
G = 1000 50 50 ppm/°C
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage 50 100 μV
vs. Temperature 0.5 2.0 μV/°C
Output Offset Voltage 2.0 3.0 mV
vs. Temperature 25 50 μV
Offset Referred to the Input vs. Supply
G = 1 80 75 dB
G = 10 100 95 dB
G = 100 110 105 dB
G = 1000 115 110 dB
AD524
Rev. F | Page 6 of 28
AD524C AD524S
Parameter Min Typ Max Min Typ Max Unit
INPUT CURRENT
Input Bias Current ±15 ±50 nA
vs. Temperature ±100 ±100 pA/°C
Input Offset Current ±10 ±35 nA
vs. Temperature ±100 ±100 pA/°C
INPUT
Input Impedance
Differential Resistance 109 109 Ω
Differential Capacitance 10 10 pF
Common-Mode Resistance 109 109 Ω
Common-Mode Capacitance 10 10 pF
Input Voltage Range
Maximum Differential Input Linear (VDL)2
±10 ±10 V
Maximum Common-Mode Linear (VCM)2
⎟
⎠
⎞
⎜
⎝
⎛×− D
V
2
G
V12 ⎟
⎠
⎞
⎜
⎝
⎛×− D
V
2
G
V12 V
Common-Mode Rejection DC to 60 Hz with 1 kΩ Source Imbalance V
G = 1 80 70 dB
G = 10 100 90 dB
G = 100 110 100 dB
G = 1000 120 110 dB
OUTPUT RATING
VOUT, RL = 2 kΩ ±10 ±10 V
DYNAMIC RESPONSE
Small Signal – 3 dB
G = 1 1 1 MHz
G = 10 400 400 kHz
G = 100 150 150 kHz
G = 1000 25 25 kHz
Slew Rate 5.0 5.0 V/μs
Settling Time to 0.01%, 20 V Step
G = 1 to 100 15 15 μs
G = 1000 75 75 μs
NOISE
Voltage Noise, 1 kHz
RTI 7 7 nV/√Hz
RTO 90 90 nV√Hz
RTI, 0.1 Hz to 10 Hz
G = 1 15 15 μV p-p
G = 10 2 2 μV p-p
G = 100, 1000 0.3 0.3 μV p-p
Current Noise
0.1 Hz to 10 Hz 60 60 pA p-p
SENSE INPUT
RIN 20 20 kΩ ± 20%
IIN 15 15 μA
Voltage Range ±10 ±10 V
Gain to Output 1 1 %
AD524
Rev. F | Page 7 of 28
AD524C AD524S
Parameter Min Typ Max Min Typ Max Unit
REFERENCE INPUT
RIN 40 40 kΩ ± 20%
IIN 15 15 μA
Voltage Range 10 10 V
Gain to Output 1 1 %
TEMPERATURE RANGE
Specified Performance –25 +85 –55 +85 °C
Storage –65 +150 –65 +150 °C
POWER SUPPLY
Power Supply Range ±6 ±15 ±18 ±6
±15 ±18 V
Quiescent Current 3.5 5.0 3.5
5.0 mA
1 Does not include effects of external resistor RG.
2 VOL is the maximum differential input voltage at G = 1 for specified nonlinearity.
VDL at the maximum = 10 V/G.
VD = actual differential input voltage.
Example: G = 10, VD = 0.50.
VCM = 12 V − (10/2 × 0.50 V) = 9.5 V.
AD524
Rev. F | Page 8 of 28
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation 450 mW
Input Voltage1
(Either Input Simultaneously) |VIN| + |VS| <36 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range
(R) –65°C to +125°C
(D, E) –65°C to +150°C
Operating Temperature Range
AD524A/AD524B/AD524C –25°C to +85°C
AD524S –55°C to +125°C
Lead Temperature (Soldering, 60 sec) +300°C
1 Maximum input voltage specification refers to maximum voltage to which
either input terminal may be raised with or without device power applied.
For example, with ±18 volt supplies maximum, VIN is ±18 V; with zero supply
voltage maximum, VIN is ±36 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
RG116
–INPUT
1
+INPUT
2
RG2
3
4
INPUT
NULL
5
INPUT
NULL
6
REFERENCE
9
OUTPUT
8 +VS
7 –VS
SENSE
10
G = 1000
11
G = 100
12
G = 10
13
OUTPUT
NULL
14
O
UTPUT
NULL
15
0.170 (4.33)
0.103
(2.61)
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR
THE D-16 AND RW-16 16-LEAD CERAMIC PACKAGES.
00500-002
Figure 2. Metallization Photograph
Contact factory for latest dimensions;
Dimensions shown in inches and (mm)
CONNECTION DIAGRAMS
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
– INPUT
+ INPUT
INPUT NULL
INPUT NULL
REFERENCE
OUTPUT NULL
OUTPUT NULL
G = 10
G = 100
G = 1000
SENSE
OUTPUT
AD524
RG
2
RG
1
–V
S
–V
S
+V
S
+V
S
SHORT TO
RG
2
FOR
DESIRED
GAIN
415
514 OUTPUT
OFFSET NULL
INPUT
OFFSET NULL
TOP VIEW
(Not to Scale)
0
0500-003
Figure 3. Ceramic (D) and
SOIC (RW-16 and D-16) Packages
SHORT T
O
RG
2
FOR
DESIRED
GAIN
4
RG
2
5
INPUT NULL
6
NC
7
INPUT NULL
8
REFERENCE
18
OUTPUT NULL
17
G = 10
16
NC
15
G = 100
14
G = 1000
19
RG
1
20
OUTPUT
NULL
1
NC
2
–INPUT
3
+INPUT
13
SENSE
12
OUTPUT
11
NC
10
+V
S
9
–V
S
NC = NO CONNECT
AD524
TOP VIEW
(Not to Scale)
+V
S
–V
S
INPUT
OFFSET NULL
OUTPUT
OFFSET NULL
719
518
00500-004
Figure 4. Leadless Chip Carrier (E)
ESD CAUTION
AD524
Rev. F | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
5
00 5 10 15 20
SUPPLY VOLTAGE (±V)
INPUT VOLTAGE (±V)
+25°C
00500-005
Figure 5. Input Voltage Range vs. Supply Voltage, G = 1
20
15
10
5
00 5 10 15 20
SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE SWING (±V)
00500-006
Figure 6. Output Voltage Swing vs. Supply Voltage
30
20
10
0
10 100 1k 10k
LOAD RESISTANCE (Ω)
OUTPUT VOLTAGE SWING (V p-p)
00500-007
Figure 7. Output Voltage Swing vs. Load Resistance
8
6
4
2
00 5 10 15 20
SUPPLY VOLTAGE (±V)
QUIESCENT CURRENT (mA)
00500-008
Figure 8. Quiescent Current vs. Supply Voltage
16
12
8
4
14
10
6
2
00 5 10 15 20
SUPPLY VOLTAGE (±V)
INPUT BIAS CURRENT (±nA)
00500-009
Figure 9. Input Bias Current vs. Supply Voltage
40
20
0
–20
30
10
–10
–30
–40 –75 –25 25 75 125
TEMPERATURE (°C)
INPUT BIAS CURRENT (nA)
00500-010
Figure 10. Input Bias Current vs. Temperature
AD524
Rev. F | Page 10 of 28
16
12
8
4
14
10
6
2
00 5 10 15 20
INPUT VOLTAGE (±V)
INPUT BIAS CURRENT (±nA)
00500-011
Figure 11. Input Bias Current vs. Input Voltage
1
3
5
0
2
4
6
02461357
WARM-UP TIME (Minutes)
ΔV
OS
FROM FINAL VALUE (µV)
8
00500-012
Figure 12. Offset Voltage, RTI, Turn-On Drift
100
1
1000
10
0 100 10k 1M10 1k 100k 10M
FREQUENCY (Hz)
GAIN (V/V)
00500-013
Figure 13. Gain vs. Frequency
–120
–80
–
140
–100
–40
0
–60
–20
0 100 10k 1M10 1k 100k 10M
FREQUENCY (Hz)
CMRR (dB)
G = 1000
G = 100
G = 10
G = 1
00500-014
Figure 14. CMRR vs. Frequency, RTI, Zero to 1000 Source Imbalance
30
20
10
0
1k 10k 100k 1M
FREQUENCY (Hz)
FULL POWER RESPONSE (V p-p)
G = 1, 10, 100
00500-015
BANDWIDTH LIMITED
G = 1000 G = 100 G = 10
Figure 15. Large Signal Frequency Response
10
6
8
4
2
01 10 100 1000
GAIN (V/V)
SLEW RATE (V/µs)
G = 1000
00500-016
Figure 16. Slew Rate vs. Gain
AD524
Rev. F | Page 11 of 28
120
80
140
160
100
40
0
60
20
100 10k10 1k 100k
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO (dB)
G = 1000
G = 10
G = 1
G = 100
+V
S
= 15V DC +
1V p-p SINEWAVE
00500-017
Figure 17. Positive PSRR vs. Frequency
120
80
140
160
100
40
0
60
20
100 10k10 1k 100k
FREQUENCY (Hz)
POWER SUPPLY REJECTION RATIO (dB)
G = 100
G = 10
G = 1
G = 1000
–V
S
= –15V DC +
1V p-p SINEWAVE
00500-018
Figure 18. Negative PSRR vs. Frequency
1000
0.1
1 100k
FREQUENCY (Hz)
VOLT NSD (nV/ Hz)
10 100 1k 10k
1
10
100
G = 1000
G = 100, 1000
G = 10
G = 1
00500-019
Figure 19. RTI Noise Spectral Density vs. Gain
100k
0 10k
FREQUENCY (Hz)
CURRENT NOISE SPECTRAL DENSITY (fA/ Hz)
1 10 100 1k
100
1k
10k
00500-020
Figure 20. Input Current Noise vs. Frequency
0.1Hz TO 10Hz
VERTICAL SCALE; 1 DIVISION = 5µV
5mV 1s
00500-021
Figure 21. Low Frequency Noise, G = 1 (System Gain = 1000)
0.1Hz TO 10Hz
VERTICAL SCALE; 1 DIVISION = 0.1µV
10mV 1s
00500-022
Figure 22. Low Frequency Noise, G = 1000 (System Gain = 100,000)
AD524
Rev. F | Page 12 of 28
–12 TO +12
+4 TO –4
+8 TO –8
+12 TO –12
–8 TO +8
–4 TO +4
1% 0.1% 0.01%
1% 0.1% 0.01%
OUTPUT
STEP (V)
SETTLING TIME (µs)
0 5 10 15 20
00500-023
Figure 23. Settling Time, Gain = 1
10V 10µs1mV
00500-024
Figure 24. Large Signal Pulse Response and Settling Time, Gain =1
–12 TO +12
+4 TO –4
+8 TO –8
+12 TO –12
–8 TO +8
–4 TO +4
0.01%
0.01%
OUTPUT
STEP (V)
0.1%
1%
1% 0.1%
SETTLING TIME (µs)
0 5 10 15 20
00500-025
Figure 25. Settling Time, Gain = 10
1mV 10V 10µs
0
0500-026
Figure 26. Large Signal Pulse Response and Settling Time, Gain = 10
–
12 TO +12
+4 TO –4
+8 TO –8
+12 TO –12
–8 TO +8
–4 TO +4
OUTPUT
STEP (V)
1%
1% 0.01%
0.01%
0.1%
0.1%
SETTLING TIME (µs)
0 5 10 15 20
00500-027
Figure 27. Settling Time, Gain = 100
1mV 10V 10µs
0
0500-028
Figure 28. Large Signal Pulse Response and Settling Time, Gain = 100
AD524
Rev. F | Page 13 of 28
–12 TO +12
+4 TO –4
+8 TO –8
+12 TO –12
–8 TO +8
–4 TO +4
OUTPUT
STEP (V)
1% 0.01%
1% 0.01%
0.1%
0.1%
0 102030405060708
SETTLING TIME (µs)
00500-029
0
Figure 29. Settling Time, Gain = 1000
5mV 10V 20µs
0
0500-030
Figure 30. Large Signal Pulse Response and Settling Time, Gain = 1000
AD524
Rev. F | Page 14 of 28
TEST CIRCUITS
AD524
G = 10
G = 100
G = 1000
10kΩ
0.01%
1kΩ
10T
10kΩ
0.1%
V
OUT
+V
S
–
+
INPUT
20V p-p
11kΩ
0.1%
1kΩ
0.1%
100Ω
0.1%
–V
S
RG
1
RG
2
100kΩ
0.1%
1
16
13
12 9
11
10
6
3
8
7
2
00500-031
Figure 31. Settling Time Test Circuit
–IN
C4C3
+IN
REFERENCE
SENSE
A3
4.44kΩ
404Ω
40Ω
G = 100
G = 1000
Q2, Q4
Q1, Q3
+VS
I1
50µA
I2
50µA
A1 A2 R52
20kΩ
R55
20kΩ
VO
CH1
I4
50µA
–VS
I3
50µA
VB
R53
20kΩ
R54
20kΩ
CH2, CH3,
CH4
RG2
RG1
CH1
CH2,
CH3, CH4
R57
20kΩR56
20kΩ
++
00500-032
Figure 32. Simplified Circuit of Amplifier; Gain Is Defined as
((R56 + R57)/(RG)) +1; For a Gain of 1, RG Is an Open Circuit
AD524
Rev. F | Page 15 of 28
THEORY OF OPERATION
The AD524 is a monolithic instrumentation amplifier based
on the classic 3-op amp circuit. The advantage of monolithic
construction is the closely matched components that enhance
the performance of the input preamplifier. The preamplifier
section develops the programmed gain by the use of feedback
concepts. The programmed gain is developed by varying the
value of RG (smaller values increase the gain) while the feedback
forces the collector currents (Q1, Q2, Q3, and Q4) to be constant,
which impresses the input voltage across RG.
As RG is reduced to increase the programmed gain, the
transconductance of the input preamplifier increases to the
transconductance of the input transistors. This has three
important advantages. First, this approach allows the circuit
to achieve a very high open-loop gain of 3 × 108 at a programmed
gain of 1000, thus reducing gain-related errors to a negligible
30 ppm. Second, the gain bandwidth product, which is deter-
mined by C3 or C4 and the input transconductance, reaches
25 MHz. Third, the input voltage noise reduces to a value
determined by the collector current of the input transistors
for an RTI noise of 7 nV/√Hz at G = 1000.
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instru-
mentation amplifiers are often subjected to input overloads,
that is, voltage levels in excess of the full scale for the selected
gain range. At low gains (10 or less), the gain resistor acts as a
current limiting element in series with the inputs. At high gains,
the lower value of RG does not adequately protect the inputs
from excessive currents. Standard practice is to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) requires
over 7k of resistance, which adds 10 nV√Hz of noise. To
provide both input protection and low noise, a special series
protection FET is used.
A unique FET design was used to provide a bidirectional
current limit, thereby protecting against both positive and
negative overloads. Under nonoverload conditions, three
channels (CH2, CH3, CH4) act as a resistance (≈1 kΩ) in series
with the input as before. During an overload in the positive
direction, a fourth channel, CH1, acts as a small resistance
(≈3 kΩ) in series with the gate, which draws only the leakage
current, and the FET limits IDSS. When the FET enhances under
a negative overload, the gate current must go through the small
FET formed by CH1 and when this FET goes into saturation,
the gate current is limited and the main FET goes into controlled
enhancement. The bidirectional limiting holds the maximum
input current to 3 mA over the 36 V range.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may
be adjusted to zero, shifts in offset voltage due to temperature
variations causes errors. Intelligent systems can often correct
this factor with an autozero cycle, but there are many small-
signal high-gain applications that do not have this capability.
+Vs
RG2
AD712
1/2
9.09kΩ
1kΩ
100Ω
16.2kΩ
1/2
16.2kΩ
1.62MΩ1.82kΩ
10
100
1000
G = 1, 10, 100
G = 1000
AD524
+
V
S
–
+
–VS
1
16
13
12 9
11
10
6
3
8
7
2
1µF
1µF
–VS
1µF
3
2
8
15
64
7
0
0500-033
+
–
+
–
Figure 33. Noise Test Circuit
AD524
Rev. F | Page 16 of 28
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is the component
of offset that is directly proportional to gain, that is, input offset
as measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, output
offset drift is dominant, at high gains, input offset drift dominates.
Therefore, the output offset voltage drift is normally specified as
drift at G = 1 (where input effects are insignificant), whereas
input offset voltage drift is given by drift specification at a high
gain (where output offset effects are negligible). All input
related numbers are referred to the input (RTI) that is the effect
on the output is G times larger. Voltage offset vs. power supply
is also specified at one or more gain settings and is also RTI.
By separating these errors, one can evaluate the total error
independent of the gain setting used. In a given gain configura-
tion, both errors can be combined to give a total error referred
to the input (RTI) or output (RTO) by the following formulas:
Total error RTI = input error + (output error/gain)
Total error RTO = (gain × input error) + output error
As an illustration, a typical AD524 might have a +250 µV
output offset and a −50 µV input offset. In a unity gain
configuration, the total output offset would be 200 µV or
the sum of the two. At a gain of 100, the output offset would
be −4.75 mV or: +250 µV + 100(−50 µV) = −4.75 mV.
The AD524 provides for both input and output offset adjustment.
This simplifies very high precision applications and minimizes
offset voltage changes in switched gain applications. In such
applications, the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
GAIN
The AD524 has internal high accuracy pretrimmed resistors
for pin programmable gains of 1, 10, 100, and 1000. One of the
preset gains can be selected by pin strapping the appropriate
gain terminal and RG2 together (for G = 1, RG2 is not connected).
AD524
G = 10
G = 100
G = 1000
+INPUT
–
INPUT
V
OUT
OUTPUT
SIGNAL
COMMON
–V
S
INPUT
OFFSET
NULL
+V
S
10kΩ
RG
1
RG
2
1
16
13
12
11
3
2
8
4
5
10
9
6
7
00500-034
Figure 34. Operating Connections for G = 100
The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between
Pin 3 and Pin 16 (see Figure 35), which programs the gain
according to the following formula:
1
k40
−=
Ω
=G
RG
For best results, RG should be a precision resistor with a low
temperature coefficient. An external RG affects both gain
accuracy and gain drift due to the mismatch between it and
the internal thin-film resistors. Gain accuracy is determined
by the tolerance of the external RG and the absolute accuracy
of the internal resistors (±20%). Gain drift is determined by the
mismatch of the temperature coefficient of RG and the tempera-
ture coefficient of the internal resistors (−50 ppm/°C typical).
40,000
2.105
G = + 1 = 20 ±20%
AD524
REFERENCE
1kΩ
+INPUT
–INPUT
2.105kΩ
1.5kΩ
V
OUT
+
V
S
–V
S
RG
1
RG
2
1
16 8
7
69
10
13
12
11
3
2
00500-035
Figure 35. Operating Connections for G = 20
The second method uses the internal resistors in parallel with
an external resistor (see Figure 36). This technique minimizes
the gain adjustment range and reduces the effects of tempera-
ture coefficient sensitivity.
G =
G = 10
AD524
REFERENCE
+INPUT
–INPUT
4kΩ
*R|
G = 10
= 4444.44Ω
*R|
G = 100
= 404.04Ω
*R|
G = 1000
= 40.04Ω
*NOMINAL (±20%)
V
OUT
40,000
4000||4444.44 + 1 = 20 ±17%
+
V
S
–V
S
RG
1
RG
2
1
16
13
12
11
3
2
8
7
10
69
00500-036
Figure 36. Operating Connections for G = 20, Low Gain
Temperature Coefficient Technique
AD524
Rev. F | Page 17 of 28
The AD524 can also be configured to provide gain in the output
stage. Figure 37 shows an H pad attenuator connected
to the reference and sense lines of the AD524. R1, R2, and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 precisely sets the gain
without affecting CMRR. CMRR is determined by the match
of R1 and R3.
G = 100
G = 1000
G =
G = 10
AD524
+INPUT
–INPUT
+V
S
–V
S
(R1 + R2 + R3)||R
L
≥ 2kΩ
V
OU
T
R
L
R1
2.26kΩ
R2
5kΩ
R3
2.26kΩ
(R2||40kΩ) + R1 + R3
(R2||40kΩ)
RG
1
RG
2
1
16
13
12
11
3
2
8
7
10
69
00500-037
Figure 37. Gain of 2000
Table 4. Output Gain Resistor Values
Output Gain R2 R1, R3 Nominal Gain
2 5 kΩ 2.26 kΩ 2.02
5 1.05 kΩ 2.05 kΩ 5.01
10 1 kΩ 4.42 kΩ 10.1
INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the
input transistors of a dc amplifier. Bias currents are an
additional source of input error and must be considered in
a total error budget. The bias currents, when multiplied by
the source resistance, appear as an offset voltage. What is of
concern in calculating bias current errors is the change in bias
current with respect to signal voltage and temperature. Input
offset current is the difference between the two input bias
currents. The effect of offset current is an input offset voltage
whose magnitude is the offset current times the source
impedance imbalance.
AD524
LOAD
+
–
TO POWER
SUPPLY
GROUND
+V
S
–V
S
2
3
11
12
13
16
1
8
7
10
6
9
00500-038
Figure 38. Indirect Ground Returns for Bias Currents—Transformer Coupled
AD524
LOAD
+
–
+V
S
–V
S
TO POWER
SUPPLY
GROUND
28
7
10
6
9
3
11
12
13
16
1
00500-039
Figure 39. Indirect Ground Returns for Bias Currents—Thermocouple
AD524
LOAD
+
V
S
–V
S
TO POWER
SUPPLY
GROUND
2
8
7
10
6
9
3
11
12
13
16
1
+
–
00500-040
Figure 40. Indirect Ground Returns for Bias Currents–AC-Coupled
Although instrumentation amplifiers have differential inputs,
there must be a return path for the bias currents. If this is not
provided, those currents charge stray capacitances, causing the
output to drift uncontrollably or to saturate. Therefore, when
amplifying floating input sources such as transformers and
thermocouples, as well as ac-coupled sources, there must still
be a dc path from each input to ground.
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance. Common-mode
rejection ratio (CMRR) is a ratio expression whereas common-
mode rejection (CMR) is the logarithm of that ratio. For
example, a CMRR of 10,000 corresponds to a CMR of 80 dB.
In an instrumentation amplifier, ac common-mode rejection is
only as good as the differential phase shift. Degradation of ac
common-mode rejection is caused by unequal drops across
differing track resistances and a differential phase shift due
to varied stray capacitances or cable capacitances. In many
applications, shielded cables are used to minimize noise. This
technique can create common-mode rejection errors unless the
shield is properly driven. Figure 41 and Figure 42 show active
data guards that are configured to improve ac common-mode
rejection by bootstrapping the capacitances of the input cabling,
thus minimizing differential phase shift.
REFERENCE
AD524
100Ω
AD711
G = 100
+INPUT
–INPUT
V
OUT
+
V
S
–V
S
+
–
RG
2
1
12
3
2
8
10
9
6
7
00500-041
Figure 41. Shield Driver, G ≥ 100
REFERENCE
AD524
100Ω
AD712
+INPUT
–INPUT
100Ω
V
OUT
+V
S
–V
S
RG
1
RG
2
–V
S
–
+
1
16
12
3
2
7
6
9
10
8
00500-042
Figure 42. Differential Shield Driver
AD524
Rev. F | Page 18 of 28
GROUNDING
Many data acquisition components have two or more ground
pins that are not connected together within the device. These
grounds must be tied together at one point, usually at the system
power-supply ground. Ideally, a single solid ground would be
desirable. However, because current flows through the ground
wires and etch stripes of the circuit cards, and because these
paths have resistance and inductance, hundreds of millivolts can
be generated between the system ground point and the data
acquisition components. Separate ground returns should be
provided to minimize the current flow in the path from the
sensitive points to the system ground point. In this way, supply
currents and logic-gate return currents are not summed into the
same return path as analog signals where they would cause
measurement errors.
Because the output voltage is developed with respect to the
potential on the reference terminal, an instrumentation
amplifier can solve many grounding problems.
DIGITAL P.S.
+5V
C–15V
ANALOG P.S.
AD574A
C+15V
6
AD524 AD583
SAMPLE
AND HOLD
DIG
COM
DIGITAL
DATA
OUTPUT
SIGNAL
GROUND
ANALOG
GROUND*
OUTPUT
REFERENCE
*IF INDEPENDENT; OTHERWISE, RETURN AMPLIFIER REFERENCE
TO MECCA AT ANALOG P.S. COMMON.
1µF1µF 1µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
2
1
8
7
10
9
7 9 11 15 1
00500-043
Figure 43. Basic Grounding Practice
SENSE TERMINAL
The sense terminal is the feedback point for the instrument
amplifier’s output amplifier. Normally, it is connected to the
instrument amplifier output. If heavy load currents are to be
drawn through long leads, voltage drops due to current flowing
through lead resistance can cause errors. The sense terminal can
be wired to the instrument amplifier at the load, thus putting
the IxR drops inside the loop and virtually eliminating this
error source.
V–
V
+
X1
AD524
(REF)
(SENSE)
OUTPUT
CURRENT
BOOSTER
R
L
V
IN
+
V
IN
–
2
3
12
17
6
9
10
8
00500-044
Figure 44. AD524 Instrumentation Amplifier with Output Current Booster
Typically, IC instrumentation amplifiers are rated for a full
±10 volt output swing into 2 kΩ. In some applications, however,
the need exists to drive more current into heavier loads.
Figure 44 shows how a high current booster may be connected
inside the loop of an instrumentation amplifier to provide the
required current boost without significantly degrading overall
performance. Nonlinearities and offset and gain inaccuracies of
the buffer are minimized by the loop gain of the AD524 output
amplifier. Offset drift of the buffer is similarly reduced.
REFERENCE TERMINAL
The reference terminal can be used to offset the output by up to
±10 V. This is useful when the load is floating or does not share
a ground with the rest of the system. It also provides a direct
means of injecting a precise offset. It must be remembered that
the total output swing is ±10 V to be shared between signal and
reference offset.
When the AD524 is of the 3-amplifier configuration it
is necessary that nearly zero impedance be presented to the
reference terminal.
Any significant resistance from the reference terminal to
ground increases the gain of the noninverting signal path,
thereby upsetting the common-mode rejection of the AD524.
In the AD524, a reference source resistance unbalances the CMR
trim by the ratio of 20 kΩ/RREF. For example, if the reference
source impedance is 1 Ω, CMR is reduced to 86 dB (20 kΩ/1 Ω
= 86 dB). An operational amplifier can be used to provide that
low impedance reference point, as shown in Figure 45. The
input offset voltage characteristics of that amplifier adds directly
to the output offset voltage performance of the instrumentation
amplifier.
AD524
Rev. F | Page 19 of 28
AD524
REF
SENSE
LOAD
AD711
+INPUT
–INPUT
R1
R1 ===
(
1 +
R1
)
40,000
A2
+
–
V
X
I
L
R
G
I
L
V
X
V
IN
2
3
13
1
10
9
6
00500-046
AD524
REF
SENSE
LOAD
AD711
V
OFFSET
–V
S
+V
S
V
IN
+
V
IN
–
28
10
9
6
7
3
12
1
0
0500-045
Figure 45. Use of Reference Terminal to Provide Output Offset
Figure 46. Voltage-to-Current Converter
An instrumentation amplifier can be turned into a voltage-
to-current converter by taking advantage of the sense and
reference terminals, as shown in Figure 46.
By establishing a reference at the low side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain, and the value of that resistor. Because only a small
current is demanded at the input of the buffer amplifier (A2)
the forced current, IL, largely flows through the load. Offset and
drift specifications of A2 must be added to the output offset and
drift specifications of the AD524.
Y0
Y2
Y1
+5V
C1 C2
A
B
+5V
–IN
+IN
OUT K1 K2 K3D1 D2 D3
NC
GAIN TABLE
ABGAIN
0
0
1
1
0
1
0
1
10
1000
100
1
NC = NO CONNECT
1
2
3
4
5
6
7
8
20kΩ
20kΩ
20kΩ404Ω
4.44kΩ
20kΩ
20kΩ20kΩ40Ω
PROTECTION
PROTECTION
16
15
14
13
12
11
10
9
INPUT
OFFSET
TRIM
ANALOG
COMMON
–VS
+VS
K1 – K3 =
THERMOSEN DM2C
4.5V COIL
D1 – D3 = IN4148
INPUTS
GAIN
RANGE
A1
AD524
LOGIC
COMMON
10µF
7407N
BUFFER
DRIVER
74LS138
DECODER
G = 1000
K3
G = 100
K2
G = 10
K1
OUTPUT
OFFSET
TRIM
RELAY
SHIELDS
R1
10kΩ
+VS
R2
10kΩ
1µF
35V
116
15
14
13
2
3
4
5
6
7
116
2
3
4
5
6
7
00500-047
Figure 47. Three-Decade Gain Programmable Amplifier
AD524
Rev. F | Page 20 of 28
PROGRAMMABLE GAIN
Figure 47 shows the AD524 being used as a software program-
mable gain amplifier. Gain switching can be accomplished with
mechanical switches such as DIP switches or reed relays. It should
be noted that the on resistance of the switch in series with the
internal gain resistor becomes part of the gain equation and has
an effect on gain accuracy.
The AD524 can also be connected for gain in the output stage.
Figure 48 shows an AD711 used as an active attenuator in the
output amplifier’s feedback loop. The active attenuation presents
very low impedance to the feedback resistors, therefore
minimizing the common-mode rejection ratio degradation.
TO –V
AD524
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
20kΩ
20kΩ
20kΩ404Ω
4.44kΩ
20kΩ
20kΩ20kΩ40Ω
PROTECTION
PROTECTION
–IN
+IN
(+INPUT)
(–INPUT)
10kΩ
10pF
20kΩ
AD711
AD7590
GND
39.2kΩ
28.7kΩ
316kΩ
1kΩ
1kΩ
1kΩ
A4A3A2 WR
–VS
+
VS
1µF
35V
INPUT
OFFSET
NULL
+VS
OUTPUT
OFFSET
NULL
R2
10kΩ
VOUT
+VS
–VS
VDD
VSS VDD
15
13
11
9
2
14
12
10
34567
18
16
00500-048
+
–
+–
Figure 48. Programmable Output Gain
2
1
10
6
AD524
DAC A
DB0
256:1
20kΩ
G = 10
G = 100
G = 1000
4.44kΩ
404Ω
40Ω
PROTECTION
20kΩ
20kΩ20kΩ
20kΩ20kΩ
DAC B
DB7
AD7528
9
16
11
12
PROTECTION
3
13
RG
1
RG
2
V
b
+INPUT
(–INPUT)
–INPUT
(+INPUT)
V
OUT
CS
WR
1/2
AD712
1/2
AD712
DATA
INPUTS
DAC A/DAC B
+V
S
4
14
7
15
16
6
18
5
17 3
2
1
19
20
00500-049
Figure 49. Programmable Output Gain Using a DAC
Another method for developing the switching scheme is to
use a DAC. The AD7528 dual DAC, which acts essentially as
a pair of switched resistive attenuators having high analog
linearity and symmetrical bipolar transmission, is ideal in this
application. The multiplying DAC’s advantage is that it can
handle inputs of either polarity or zero without affecting the
programmed gain. The circuit shown uses an AD7528 to set
the gain (DAC A) and to perform a fine adjustment (DAC B).
AUTOZERO CIRCUITS
In many applications, it is necessary to provide very accurate
data in high gain configurations. At room temperature, the
offset effects can be nulled by the use of offset trim potenti-
ometers. Over the operating temperature range, however,
offset nulling becomes a problem. The circuit of Figure 50
shows a CMOS DAC operating in bipolar mode and connected
to the reference terminal to provide software controllable offset
adjustments.
AD524
Rev. F | Page 21 of 28
WR
CS
+INPUT
G = 10
–INPUT
G = 100
G = 1000
AD7524
OUT2
39kΩ
AD589
MSB
LSB
C1
GND
OUT1
AD524
+V
S
RG
1
RG
2
+
–
–
+
–
+
–V
S
V
REF
+V
S
+V
S
R5
20kΩ
R3
20kΩ
R4
10kΩ
–V
S
R6
5kΩ
1/2
AD712
1/2
AD712
DATA
INPUTS
–V
S
2
8
7
10
6
9
16
13
12
11
3
1
7
6
54
1
8
2
3
3
13
12
11
4
15 14 16
1
2
00500-050
AD524C
G = 100
10kΩ
+10V
350Ω350Ω
350Ω350Ω
14-BIT
ADC
0V TO 2V
F.S.
+VS
–VS
RG1
RG2
+
–
2
8
4
5
10
9
6
7
16
13
12
11
3
1
00500-052
Figure 52. Typical Bridge Application
ERROR BUDGET ANALYSIS
To illustrate how instrumentation amplifier specifications are
applied, review a typical case where an AD524 is required to
amplify the output of an unbalanced transducer. Figure 52
shows a differential transducer, unbalanced by 100 Ω, supplying
a 0 mV to 20 mV signal to an AD524C. The output of the IA
feeds a 14-bit ADC with a 0 V to 2 V input voltage range. The
operating temperature range is −25°C to +85°C. Therefore, the
largest change in temperature, ∆T, within the operating range is
from ambient to +85°C (85°C − 25°C = 60°C).
Figure 50. Software Controllable Offset
In many applications, complex software algorithms for autozero
applications are not available. For those applications, Figure 51
provides a hardware solution.
AD524
14
15 16
13
GND
CH
1kΩ
ZERO PULSE
AD7510KD
AD711
A1 A2 A3 A4
V
DD
V
SS
200µs
910
1112
–V
S
V
OUT
0.1µF LOW
LEAKAGE
+V
S
RG
1
RG
2
2
8
7
10
6
9
16
13
12
11
3
1
8
1
2
–
+
–
+
00500-051
In many applications, differential linearity and resolution are of
prime importance in cases where the absolute value of a variable is
less important than changes in value. In these applications, only
the irreducible errors (45 ppm = 0.004%) are significant. Further-
more, if a system has an intelligent processor monitoring the
analog-to-digital output, the addition of an autogain/autozero
cycle removes all reducible errors and may eliminate the require-
ment for initial calibration. This also reduces errors to 0.004%.
Figure 51. Autozero Circuit
AD524
Rev. F | Page 22 of 28
Table 5. Error Budget Analysis
Error Source
AD524C
Specifications Calculation
Effect on
Absolute
Accuracy
at TA = 25°C
Effect on
Absolute
Accuracy
at TA = 85°C
Effect
on
Resolution
Gain Error ±0.25% ±0.25% = 2500 ppm 2500 ppm 2500 ppm –
Gain Instability 25 ppm (25 ppm/°C)(60°C) = 1500 ppm – 1500 ppm –
Gain Nonlinearity ±0.003% ±0.003% = 30 ppm – – 30 ppm
Input Offset Voltage ±50 μV, RTI ±50 μV/20 mV = ±2500 ppm 2500 ppm 2500 ppm –
Input Offset Voltage Drift ±0.5 μV/°C
–
(±0.5 μV/°C)(60°C) = 30 μV
30 μV/20 mV = 1500 ppm
– 1500 ppm –
Output Offset Voltage1
±2.0 mV ±2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm –
Output Offset Voltage Drift1
±25 μV/°C (±25 μV/°C)(60°C)= 1500 μV
1500 μV/20 mV = 750 ppm
– 750 ppm –
Bias Current-Source
Imbalance Error
±15 nA (±15 nA)(100 Ω ) = 1.5 μV
1.5 μV/20 mV = 75 ppm
75 ppm 75 ppm –
Bias Current-Source
Imbalance Drift
±100 pA/°C (±100 pA/°C)(100 Ω )(60°C) = 0.6 μV
0.6 μV/20 mV = 30 ppm
– 30 ppm –
Offset Current-Source
Imbalance Error
±10 nA (±10 nA)(100 Ω ) = 1 μV
1 μV/20 mV = 50 ppm
50 ppm 50 ppm –
Offset Current-Source
Imbalance Drift
±100 pA/°C (100 pA/°C)(100 Ω )(60°C) = 0.6 μV
0.6 μV/20 mV = 30 ppm
– 30 ppm –
Offset Current-Source
Resistance-Error
±10 nA (10 nA)(175 Ω ) = 3.5 μV
3.5 μV/20 mV = 87.5 ppm
87.5 ppm 87.5 ppm –
Offset Current-Source
Resistance-Drift
±100 pA/°C (100 pA/°C)(175 Ω )(60°C) = 1 μV
1 μV/20 mV = 50 ppm
– 50 ppm –
Common Mode Rejection 5 V DC 115 dB 115 dB = 1.8 ppm × 5 V = 8.8 μV
8.8 μV/20 mV = 444 ppm
444 ppm 444 ppm –
Noise, RTI (0.1 Hz to 10 Hz) 0.3 μV p-p 0.3 μV p-p/20 mV = 15 ppm – – 15 ppm
Total Error 6656.5 ppm 10516.5 ppm 45 ppm
1 Output offset voltage and output offset voltage drift are given as RTI figures.
AD524
Rev. F | Page 23 of 28
Figure 53 shows a simple application in which the variation
of the cold-junction voltage of a Type J thermocouple-iron ±
constantan is compensated for by a voltage developed in series
by the temperature-sensitive output current of an AD590
semiconductor temperature sensor.
AD524
IRON
CONSTANTAN
AD590
CU 52.3Ω
8.66kΩ
1kΩ
E
O
2.5V
AD580
7.5V
G = 100
– 2.5V
1 + 52.3Ω
R
TYPE
J
K
E
T
S, R
R
A
NOMINAL
VALUE
REFERENCE
JUNCTION
+15°C < T
A
< +35°C
52.3Ω
41.2Ω
61.4Ω
40.2Ω
5.76Ω
+V
S
I
A
T
A
V
A
+V
S
+
–
–V
S
OUTPUT
AMPLIFIER
OR METER
R
T
NOMINAL VALUE
9135Ω
R
A
E
O
= V
T
– V
A
+ 52.3ΩI
A
+ 2.5V
MEASURING
JUNCTION
= V
T
~
V
T
0
0500-053
Figure 53. Cold-Junction Compensation
The circuit is calibrated by adjusting RT for proper output
voltage with the measuring junction at a known reference
temperature and the circuit near 25°C. If resistors with low
temperature coefficients are used, compensation accuracy is
to within ±0.5°C, for temperatures between +15°C and +35°C.
Other thermocouple types may be accommodated with the
standard resistance values shown in Table 5. For other ranges
of ambient temperature, the equation in Figure 53 may be
solved for the optimum values of RT and RA.
The microprocessor controlled data acquisition system shown
in Figure 54 includes both autozero and autogain capability. By
dedicating two of the differential inputs, one to ground and one
to the A/D reference, the proper program calibration cycles can
eliminate both initial accuracy errors and accuracy errors over
temperature. The autozero cycle, in this application, converts a
number that appears to be ground and then writes that same
number (8-bit) to the AD7524, which eliminates the zero error.
Because its output has an inverted scale, the autogain cycle
converts the A/D reference and compares it with full scale. A
multiplicative correction factor is then computed and applied
to subsequent readings.
For a comprehensive study of instrumentation amplifier
design and applications, refer to the Designer’s Guide to
Instrumentation Amplifiers (3rd Edition), available free from
Analog Devices, Inc.
AD524
AD7524
AD574A
AD583
AGND
20kΩ
10kΩ
5kΩ
AD7507
CONTROL
DECODE
LATCH
ADDRESS BUS
A0, A2,
EN, A1
V
IN
V
REF
MICRO-
PROCESSOR
+
–
RG
2
RG
1
–V
REF
20kΩ
1/2
AD712
1/2
AD712
–
+
–
+
2
10
6
9
16
13
12
11
3
1
0
0500-054
Figure 54. Microprocessor Controlled Data Acquisition System
AD524
Rev. F | Page 24 of 28
OUTLINE DIMENSIONS
16
18
9
0.310 (7.87)
0.220 (5.59)
PIN 1
0.080 (2.03) MAX
0.005 (0.13) MIN
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18) 0.070 (1.78)
0.030 (0.76)
0.100
(2.54)
BSC
0.150
(3.81)
MIN
0.840 (21.34) MAX
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 16-Lead Side-Brazed Ceramic Dual In-Line [SBDIP]
(D-16)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1
20 4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
022106-A
Figure 56. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013- AA
032707-B
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
Figure 57. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
AD524
Rev. F | Page 25 of 28
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD524AD −40°C to +85°C 16-Lead SBDIP D-16
AD524ADZ1−40°C to +85°C 16-Lead SBDIP D-16
AD524AE −40°C to +85°C 20-Terminal LCC E-20
AD524AR-16 −40°C to +85°C 16-Lead SOIC_W RW-16
AD524AR-16-REEL −40°C to +85°C 16-Lead SOIC_W, 13" Tape and Reel RW-16
AD524AR-16-REEL7 −40°C to +85°C 16-Lead SOIC_W, 7" Tape and Reel RW-16
AD524ARZ-161
−40°C to +85°C 16-Lead SOIC_W RW-16
AD524ARZ-16-REEL71
−40°C to +85°C 16-Lead SOIC_W, 7”Tape and Reel RW-16
AD524BD −40°C to +85°C 16-Lead SBDIP D-16
AD524BDZ1
−40°C to +85°C 16-Lead SBDIP D-16
AD524BE −40°C to +85°C 20-Terminal LCC E-20
AD524CD −40°C to +85°C 16-Lead SBDIP D-16
AD524CDZ1
−40°C to +85°C 16-Lead SBDIP D-16
AD524SD −55°C to +125°C 16-Lead SBDIP D-16
AD524SD/883B −55°C to +125°C 16-Lead SBDIP D-16
5962-8853901EA2 −55°C to +125°C 16-Lead SBDIP D-16
AD524SE/883B −55°C to +125°C 20-Terminal LCC E-20
AD524SCHIPS −55°C to +125°C Die
1 Z = RoHS Compliant Part.
2 Refer to the official DESC drawing for tested specifications.
AD524
Rev. F | Page 26 of 28
NOTES
AD524
Rev. F | Page 27 of 28
NOTES
AD524
Rev. F | Page 28 of 28
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00500-0-11/07(F)
