 
  
FEATURES APPLICATIONS
DESCRIPTION
Successive ApproximationRegisterandControlLogic
Clock
BUSY
Comparator
BYTE
CS
R/C
CDAC
Buffer
REF
CAP
±10VInput
5kΩ
2k
Ω
9.8kΩ
Internal
+2.5VRef
4kΩ
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
•Industrial Process Control•105dB SFDR at 250-kHz Sample Rate
•Data Acquisition Systems•Standard ±10-V Input Range
•Digital Signal Processing• ± 1.5 LSB Max INL
•Medical Equipment• ± 1 LSB Max DNL, 16-Bits No Missing Codes
•Instrumentation• ± 2 mV Max Bipolar Zero Error With ±0.4PPM/ °C Drift• ± 0.1% FSR Max Full-Scale Error With ±2
The ADS8505 is a complete 16-bit sampling A/DPPM/ °C Drift
converter using state-of-the-art CMOS structures. It•Single 5-V Supply Operation
contains a complete 16-bit, capacitor-based, SAR•Pin-Compatible With ADS7805 (Low Speed)
A/D with S/H, reference, clock, interface forand 12-Bit ADS8504/7804
microprocessor use, and 3-state output drivers.•Uses Internal or External Reference
The ADS8505 is specified at a 250-kHz sampling•Full Parallel Data Output rate over the full temperature range. Precisionresistors provide an industry standard ±10-V input•70-mW Typ Power Dissipation at 250 KSPS
range, while the innovative design allows operation•28-Pin SSOP and SOIC Packages
from a single +5-V supply, with power dissipationunder 100 mW.
The ADS8505 is available in 28-pin SOIC and 28-pinSSOP packages, both fully specified for operationover the industrial –40 °C to 85 °C temperature range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
ELECTRICAL CHARACTERISTICS
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
(1)
MINIMUM
NO MINIMUM SPECIFICATIONRELATIVE PACKAGE PACKAGE ORDERING TRANSPORTPRODUCT MISSING SINAD TEMPERATUREACCURACY LEAD DESIGNATOR NUMBER MEDIA, QTYCODE (dB) RANGE(LSB)
ADS8505IBDW Tube, 20SO-28 DW
ADS8505IBDWR Tape and Reel, 1000ADS8505IB ±1.5 16 86 –40 °C to 85 °C
ADS8505IBDB Tube, 50SSOP-28 DB
ADS8505IBDBR Tape and Reel, 2000
ADS8505IDW Tube, 20SO-28 DW
ADS8505IDWR Tape and Reel, 1000ADS8505I ±4 15 83 –40 °C to 85 °C
ADS8505IDB Tube, 50SSOP-28 DB
ADS8505IDBR Tape and Reel, 2000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
over operating free-air temperature range (unless otherwise noted)
(2)
UNIT
V
IN
±25VAnalog inputs REF +V
ANA
+ 0.3 V to AGND2 – 0.3 VCAP Indefinite short to AGND2, momentary short to V
ANA
DGND, AGND1, AGND2 ±0.3 VV
ANA
6 VGround voltage differences
V
DIG
to V
ANA
0.3 VV
DIG
6 VDigital inputs –0.3 V to +V
DIG
+ 0.3 VMaximum junction temperature 165 °CInternal power dissipation 825 mWLead temperature (soldering, 10s) 300 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
T
A
= –40 °C to 85 °C, f
s
= 250 kHz, V
DIG
= V
ANA
= 5 V, using internal reference (unless otherwise noted)
ADS8505I ADS8505IBPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
Resolution 16 16 Bits
ANALOG INPUT
Voltage range ±10 ±10 V
Impedance 11.5 11.5 k Ω
Capacitance 50 50 pF
THROUGHPUT SPEED
Conversion cycle Acquire and convert 4 4 µs
Throughput rate 250 250 kHz
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ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)T
A
= –40 °C to 85 °C, f
s
= 250 kHz, V
DIG
= V
ANA
= 5 V, using internal reference (unless otherwise noted)
ADS8505I ADS8505IBPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
DC ACCURACY
INL Integral linearity error –4 4 –1.5 1.5 LSB
(1)
DNL Differentiall linearity error –2 2 –1 1 LSB
(1)
No missing codes 15 16 Bits
Transition noise
(2)
0.77 0.77 LSB
Full-scale error
(3) (4)
Int. ref. –0.5 0.5 –0.25 0.25 %FSR
Full-scale error drift Int. ref. ±7±7 ppm/ °C
Full-scale error
(3) (4)
Ext. 2.5-V ref. –0.25 0.25 –0.1 ±0.01 0.1 %FSR
Full-scale error drift Ext. 2.5-V ref. ±2±2 ppm/ °C
Bipolar zero error
(3)
–5 5 –2 2 mV
Bipolar zero error drift ±0.4 ±0.4 ppm/ °C
Power supply sensitivity –8 8 –8 8+4.75 V < V
D
< +5.25 V LSB(V
DIG
= V
ANA
= V
D
)
AC ACCURACY
SFDR Spurious free dynamic range f
I
= 20 kHz 92 98 96 105 dB
(5)
THD Total harmonic distortion f
I
= 20 kHz –98 –92 –103 –96 dB
f
I
= 20 kHz 83 88 86 88 dBSINAD Signal-to-(noise + distortion)
–60-dB Input 30 32 dB
SNR Signal-to-noise ratio f
I
= 20 kHz 83 88 86 88 dB
Full-power bandwidth
(6)
500 500 kHz
SAMPLING DYNAMICS
Aperture delay 5 5 ns
Transient response FS Step 2 2 µs
Overvoltage recovery
(7)
150 150 ns
REFERENCE
Internal reference voltage 2.48 2.5 2.52 2.48 2.5 2.52 V
Internal reference source current (must
1 1 µAuse external buffer)
Internal reference drift 8 8 ppm/ °C
External reference voltage range for
2.3 2.5 2.7 2.3 2.5 2.7 Vspecified linearity
External reference current drain Ext. 2.5-V ref. 100 100 µA
DIGITAL INPUTS
Logic levels
V
IL
Low-level input voltage –0.3 0.8 –0.3 0.8 V
V
IH
High-level input voltage 2.0 V
DIG
+0.3 V 2.0 V
DIG
+0.3 V V
I
IL
Low-level input current ±10 ±10 µA
I
IH
High-level input current ±10 ±10 µA
DIGITAL OUTPUTS
Data format (parallel 16-bits)
Data coding (binary 2's complement)
V
OL
Low-level output voltage I
SINK
= 1.6 mA 0.4 0.4 V
V
OH
High-level output voltage I
SOURCE
= 500 mA 4 4 V
Hi-Z state,Leakage current ±5±5µAV
OUT
= 0 V to V
DIG
Output capacitance Hi-Z state 15 15 pF
(1) LSB means least significant bit. For the 16-bit, ±10-V input ADS8505, one LSB is 305 µV.(2) Typical rms noise at worst case transitions and temperatures.(3) As measured with fixed resistors shown in Figure 27 . Adjustable to zero with external potentiometer.(4) Full-scale error is the worst case of –full-scale or +full-scale deviation from ideal first and last code transitions, divided by the transitionvoltage (not divided by the full-scale range) and includes the effect of offset error.(5) All specifications in dB are referred to a full-scale ±10-V input.(6) Full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB, or 10 bits ofaccuracy.
(7) Recovers to specified performance after 2 x FS input overvoltage.
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DEVICE INFORMATION
VDIG
VANA
BUSY
CS
R/C
BYTE
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
VIN
AGND1
REF
CAP
AGND2
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)T
A
= –40 °C to 85 °C, f
s
= 250 kHz, V
DIG
= V
ANA
= 5 V, using internal reference (unless otherwise noted)
ADS8505I ADS8505IBPARAMETER TEST CONDITIONS UNITMIN TYP MAX MIN TYP MAX
DIGITAL TIMING
Bus access timing 83 83 ns
Bus relinquish timing 83 83 ns
POWER SUPPLIES
V
DIG
Digital input voltage 4.75 5 5.25 4.75 5 5.25 V
V
ANA
Analog input voltage 4.75 5 5.25 4.75 5 5.25 VMust be ≤V
ANAI
DIG
Digital input current 2 5 2 5 mA
I
ANA
Analog input current 12 15 12 15 mA
Power dissipation f
S
= 250 kHz 70 100 70 100 mW
TEMPERATURE RANGE
Specified performance –40 85 –40 85 °C
Derated performance
(8)
–55 125 –55 125 °C
Storage –65 150 –65 150 °C
THERMAL RESISTANCE ( Θ
JA
)
SSOP 62 62 °C/W
SO 46 46 °C/W
(8) The internal reference may not be started correctly beyond the industrial temperature range (–40 °C to 85 °C), therefore use of anexternal reference is recommended.
DB OR DW PACKAGE
(TOP VIEW)
4
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ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
DEVICE INFORMATION (continued)Terminal Functions
TERMINAL
DIGITAL
DESCRIPTIONI/ONAME DB/DW NO.
AGND1 2 Analog ground. Used internally as ground reference point.AGND2 5 Analog ground.BUSY 26 O At the start of a conversion, BUSY goes low and stays low until the conversion iscompleted and the digital outputs have been updated.BYTE 23 I Selects 8 most significant bits (low) or 8 least significant bits (high).CAP 4 Reference buffer capacitor. 2.2- µF Tantalum capacitor to ground.CS 25 I Internally ORed with R/ C. If R/ C is low, a falling edge on CS initiates a new conversion.DGND 14 Digital ground.D15 (MSB) 6 O Data bit 15. Most significant bit (MSB) of conversion results. Hi-Z state when CS ishigh, or when R/ C is low.D14 7 O Data bit 14. Hi-Z state when CS is high, or when R/ C is low.D13 8 O Data bit 13. Hi-Z state when CS is high, or when R/ C is low.D12 9 O Data bit 12. Hi-Z state when CS is high, or when R/ C is low.D11 10 O Data bit 11. Hi-Z state when CS is high, or when R/ C is low.D10 11 O Data bit 10. Hi-Z state when CS is high, or when R/ C is low.D9 12 O Data bit 9. Hi-Z state when CS is high, or when R/ C is low.D8 13 O Data bit 8. Hi-Z state when CS is high, or when R/ C is low.D7 15 O Data bit 7. Hi-Z state when CS is high, or when R/ C is low.D6 16 O Data bit 6. Hi-Z state when CS is high, or when R/ C is low.D5 17 O Data bit 5. Hi-Z state when CS is high, or when R/ C is low.D4 18 O Data bit 4. Hi-Z state when CS is high, or when R/ C is low.D3 19 O Data bit 3. Hi-Z state when CS is high, or when R/ C is low.D2 20 O Data bit 2. Hi-Z state when CS is high, or when R/ C is low.D1 21 O Data bit 1. Hi-Z state when CS is high, or when R/ C is low.D0 (LSB) 22 O Data bit 0. Least significant bit (LSB) of conversion results. Hi-Z state when CS is high,or when R/ C is low.R/ C 24 I With CS low and BUSY high, a falling edge on R/ C initiates a new conversion. With CSlow, a rising edge on R/ C enables the parallel output.REF 3 Reference input/output. 2.2- µF Tantalum capacitor to ground.V
ANA
27 Analog supply input. Nominally +5 V. Decouple to ground with 0.1- µF ceramic and10- µF tantalum capacitors.V
DIG
28 Digital supply input. Nominally +5 V. Connect directly to pin 27. Must be ≤V
ANA
.V
IN
1 Analog input. See Figure 28 .
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TYPICAL CHARACTERISTICS
-105
-100
-95
-90
-85
-80
-75
-40 -20 0 20 40 60 80
T -Free-AirTemperature- C
Aº
THD-TotalHarmonicDistortion-dB
f =250KSPS
f =20kHz
s
i
80
85
90
95
100
105
110
-40 -20 0 20 40 60 80
T -Free-AirTemperature- C
Aº
SFDR-SpuriousFreeDynamicRange-dB
f =250KSPS,
f =20kHz
s
i
70
75
80
85
90
95
100
-40 -20 0 20 40 60 80
T -Free-AirTemperature- C
Aº
SNR-Signal-to-NoiseRatio-dB
f =250KSPS
f =20kHz
s
i
70
75
80
85
90
95
100
-40 -20 0 20 40 60 80
T -Free-AirTemperature- C
Aº
SINAD-Signal-to-NoiseandDistortion-dB
f =250KSPS
f =20kHz
s
I
60
65
70
75
80
85
90
95
100
105
1 10 100 125
f -InputFrequency-kHz
i
SINAD-Signal-to-NoiseandDistortion-dB
2.490
2.492
2.494
2.496
2.498
2.500
2.502
2.504
2.506
2.508
2.510
−40 −20 0 20 40 60 80
Internal Reference Voltage − V
TA − Free-Air Temperature − 5C
60
70
80
90
100
110
120
1 10 100 125
f -InputFrequency-kHz
i
THD-TotalHarmonicDistortion-dB
75
85
95
105
115
1 10 100 125
f -InputFrequency-kHz
i
SFDR-SpuriousFreeDynamicRange-dB
80
90
110
100
120
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION SIGNAL-TO-NOISE RATIOvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 1. Figure 2. Figure 3.
SIGNAL-TO-NOISE SIGNAL-TO-NOISEAND DISTORTION SIGNAL-TO-NOISE RATIO AND DISTORTIONvs vs vsFREE-AIR TEMPERATURE INPUT FREQUENCY INPUT FREQUENCY
Figure 4. Figure 5. Figure 6.
SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION INTERNAL REFERENCE VOLTAGEvs vs vsINPUT FREQUENCY INPUT FREQUENCY FREE-AIR TEMPERATURE
Figure 7. Figure 8. Figure 9.
6
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−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
−40 −20 0 20 40 60 80
Negative Full−Scale Error − %FSR
TA − Free-Air Temperature − 5C
Internal Reference
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
−40 −20 0 20 40 60 80
Negative Full−Scale Error − %FSR
TA − Free-Air Temperature − 5C
External Reference
−5
−4
−3
−2
−1
0
1
2
3
4
5
−40 −20 0 20 40 60 80
BPZ − Bipolar Zero Scale Error − mV
TA − Free-Air Temperature − 5C
−0.25
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
0.25
−40 −20 0 20 40 60 80
Positive Full−Scale Error − %FSR
TA − Free-Air Temperature − 5C
Internal Reference
−0.2
−0.15
−0.1
−0.05
0
0.05
0.1
0.15
0.2
−40 −20 0 20 40 60 80
Positive Full−Scale Error − %FSR
TA − Free-Air Temperature − 5C
External Reference
10
11
12
13
14
15
16
17
18
19
20
-40 -20 0 20 40 60 80
T -Free-AirTemperature- C
Aº
I-SupplyCurrent-mA
DD
1151
2221
4028
1713
76 2
0
500
1000
1500
2000
2500
3000
3500
4000
4500
−3 −2 −1 0 1 2 3
8192
Conversions
of a DC Input
Hits
Code
50
60
70
80
90
100
110
0 1 2 3 4 5 6 7 8 9 10
ESR-Resistance- W
Performance
| THD|
SINAD
2.2 FCapacitoron
CAP Pin(pin4)
m
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)
BIPOLAR ZERO SCALE ERROR NEGATIVE FULL-SCALE ERROR NEGATIVE FULL-SCALE ERRORvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 10. Figure 11. Figure 12.
POSITIVE FULL-SCALE ERROR POSITIVE FULL-SCALE ERROR SUPPLY CURRENTvs vs vsFREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 13. Figure 14. Figure 15.
PERFORMANCE
vsHISTOGRAM CAP PIN CAPACITOR ESR
Figure 16. Figure 17.
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-1.5
-1
-0.5
0
0.5
1
1.5
016384 32768 49152 65536
Code
INL -LSBs
-1
-0.5
0
0.5
1
016384 32768 49152 65536
Code
DNL -LSBs
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
0 25 50 75 100 125
f-Frequency-kHz
Amplitude-dB
8192Points
fs=250KSPS
fi=20KHz,0dB
SINAD=87.7dB
THD=-103.9dB
BASIC OPERATION
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
TYPICAL CHARACTERISTICS (continued)INTEGRAL NONLINEARITY
Figure 18.
DIFFERENTIAL NONLINEARITY
Figure 19.
FFT (20-kHz Input)
Figure 20.
Figure 21 shows a basic circuit to operate the ADS8505 with a full parallel data output. Taking R/ C (pin 24) lowfor a minimum of 40 ns (1.75 µs max) initiates a conversion. BUSY (pin 26) goes low and stays low until theconversion is completed and the output registers are updated. Data is output in binary 2's complement formatwith the MSB on pin 6. BUSY going high can be used to latch the data.
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STARTING A CONVERSION
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
BASIC OPERATION (continued)The ADS8505 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convertcommands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistorscompensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to theCALIBRATION section).
The combination of CS (pin 25) and R/ C (pin 24) low for a minimum of 40 ns immediately puts the sample/holdof the ADS8505 in the hold state and starts conversion n. BUSY (pin 26) goes low and stays low untilconversion nis completed and the internal output register has been updated. All new convert commands duringBUSY low will abort the conversion in progress and reset the ADC (see Figure 26 ).
The ADS8505 begins tracking the input signal at the end of the conversion. Allowing 4 µs between convertcommands assures accurate acquisition of a new signal. Refer to Table 1 for a summary of CS, R/ C, and BUSYstates and Figure 23 through Figure 25 for the timing diagrams.
CS and R/ C are internally ORed and level triggered. There is not a requirement which input goes low first wheninitiating a conversion. If, however, it is critical that CS or R/ C initiates conversion n, be sure the less criticalinput is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/ C to control the read and convert modes. Theparallel output becomes active whenever R/ C goes high. Refer to the READING DATA section.
Table 1. Control Line Functions for Read and Convert
CS R/ C BUSY OPERATION
1 X X None. Databus is in Hi-Z state.↓0 1 Initiates conversion n. Databus remains in Hi-Z state.0↓1 Initiates conversion n. Databus enters Hi-Z state.0 1 ↑Conversion ncompleted. Valid data from conversion non the databus.↓1 1 Enables databus with valid data from conversion n.↓1 0 Enables databus with valid data from conversion n-1
(1)
. Conversion nin progress.0↑0 Enables databus with valid data from conversion n-1
(1)
. Conversion nin progress.0 0 ↑Data is invalid. CS and/or R/ C must be high when BUSY goes high.X↓0 Conversion nis halted. Causes ADC to reset.
(2)
(1) See Figure 23 and Figure 24 for constraints on data valid from conversion n-1.(2) See Figure 26 for details on ADC reset.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS8505
+5V
++
+
+Convert Pulse
40 ns Min
200 Ω
2.2 µF
2.2 µF
0.1 µF10 µF
33.2 kΩ
B15 (MSB)
B14
B13
B12
B11
B10
B9
B8
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
READING DATA
PARALLEL OUTPUT (After a Conversion)
PARALLEL OUTPUT (During a Conversion)
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Figure 21. Basic Operation
The ADS8505 outputs full or byte-reading parallel data in binary 2's complement data output format. The paralleloutput is active when R/ C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/ C 3-statesthe parallel output. Valid conversion data can be read in a full parallel, 16-bit word or two 8-bit bytes on pins6-13 and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer toTable 2 for ideal output codes and Figure 22 for bit locations relative to the state of BYTE.
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT BINARY 2'S COMPLEMENTDESCRIPTION ANALOG INPUT
BINARY CODE HEX CODE
Full-scale range ±10 VLeast significant bit (LSB) 305 µVFull scale (10 V-1 LSB) 9.999695 V 0111 1111 1111 1111 7FFFMidscale 0 V 0000 0000 0000 0000 0000One LSB below midscale -305 µV 1111 1111 1111 1111 FFFF–Full scale -10 V 1000 0000 0000 0000 8000
After conversion nis completed and the output registers have been updated, BUSY (pin 26) goes high. Validdata from conversion nis available on D15-D0 (pins 6-13 and 15-22). BUSY going high can be used to latch thedata. Refer to Table 3 ,Figure 23 ,Figure 24 , and Figure 25 for timing specifications.
After conversion nhas been initiated, valid data from conversion n-1 can be read and is valid up to t
2
(2.2 µstyp) after the start of conversion n. Do not attempt to read data from t
2
(2.2 µs typ) after the start of conversion nuntil BUSY (pin 26) goes high; this may result in reading invalid data. Refer to Table 3 ,Figure 23 ,Figure 24 , andFigure 25 for timing specifications.
Note: For the best possible performance, data should not be read during a conversion. The switching noise ofthe asynchronous data transfer can cause digital feedthrough degrading converter performance.
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Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 15 (MSB)
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS8505
BYTE LOW
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15 (MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
6
7
8
9
10
11
12
13
14
23
22
21
20
19
18
17
16
15
ADS8505
BYTE HIGH +5 V
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
The number of control lines can be reduced by tying CS low while using the falling edge of R/ C to initiateconversions and the rising edge of R/ C to activate the output mode of the converter. See Figure 23 .
Table 3. Conversion Timing
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
w1
Pulse duration, convert 40 1750 nst
a
Access time, data valid after R/ C low 2.2 3.2 µst
pd
Propagation delay time, BUSY from R/ C low 15 25 nst
w2
Pulse duration, BUSY low 2.2 µst
d1
Delay time, BUSY after end of conversion 5 nst
d2
Delay time, aperture 5 nst
conv
Conversion time 2.2 µst
acq
Acquisition time 1.8 µst
dis
Disable time, bus 10 30 83 nst
d3
Delay time, BUSY after data valid 35 50 nst
v
Valid time, previous data remains valid after R/ C low 1.5 2 µst
conv
+ t
acq
Throughput time 4 µst
su
Setup time, R/ C to CS 10 nst
c
Cycle time between conversions 4 µst
en
Enable time, bus 10 30 83 nst
d4
Delay time, BYTE 5 10 30 ns
Figure 22. Bit Locations Relative to State of BYTE (Pin 23)
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BUSY
R/C
MODE Acquire ConvertConvert
DATA BUS Previous
Data Valid Hi−Z Data ValidHi−Z Previous
Data Valid Not Valid
Acquire
Data Valid
tw1
tc
ta1 tw2
tpd
td2 td1
tconv tacq
tdis tv
td3
Hi−Z State
BUSY
R/C
DATA BUS
MODE Acquire
Data Valid Hi−Z State
Convert Acquire
CS
tsu tsu tsu tsu
tw1
tpd tw2
td2
tconv
ten tdis
Hi−Z High Byte Low Byte Hi−Z
Hi−Z Low Byte High Byte Hi−Z
Pins 6 − 13
Pins 15 − 22
BYTE
CS
R/C
tsu tsu
ten td4 tdis
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Figure 23. Conversion Timing with Outputs Enabled after Conversion ( CS Tied Low)
Figure 24. Using CS to Control Conversion and Read Timing
Figure 25. Using CS and BYTE to Control Data Bus
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R/C
BUSY
4.75V
VANA
0nsMIN
tpd
tw1
tpd
tw1
tc
DATA BUS Hi-Z NotValid Hi-Z NotValid DataValid
td3
Unknown
VDIG
ADC RESET
INPUT RANGES
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Figure 26. ADC Reset
The ADC reset function of the ADS8505 can be used to terminate the current conversion cycle. Bringing R/ C lowfor at least 40 ns while BUSY is low will initiate the ADC reset. To initiate a new conversion, R/ C must return tothe high state and remain high long enough to acquire a new sample (see Table 3 , t
c
) before going low to initiatethe next conversion sequence. In applications that do not monitor the BUSY signal, it is recommended that theADC reset function be implemented as part of a system initialization sequence.
The ADS8505 offers a standard ±10-V input range. Figure 28 shows the necessary circuit connections for theADS8505 with and without hardware trim. Offset and full-scale error specifications are tested and specified withthe fixed resistors shown in Figure 28 (b). Full-scale error includes offset and gain errors measured at both +FSand –FS. Adjustments for offset and gain are described in the CALIBRATION section of this data sheet.
Offset and gain are adjusted internally to allow external trimming with a single supply. The external resistorscompensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to theCALIBRATION section).
The nominal input impedance of 11.5 k Ωresults from the combination of the internal resistor network shown onthe front page of the product data sheet and the external resistors. The input resistor divider network providesinherent overvoltage protection assured to at least ±25 V. The 1% resistors used for the external circuitry do notcompromise the accuracy or drift of the converter. They have little influence relative to the internal resistors, andtighter tolerances are not required.
The input signal must be referenced to AGND1. This minimizes the ground loop problem typical to analogdesigns. The analog signal should be driven by a low impedance source. A typical driving circuit using anOPA627 or OPA132 is shown in Figure 27 .
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OPA627
GND
GND
GND
GND
Pin1
Pin7
−
Pin2
+
Pin3 Pin4
Pin 6
−15V
+15 V
Vin
2.2 mF
100 nF
2 kW
22 pF
2 kW
22 pF
200 W
33.2 kW
2.2 mF
2.2 mF
100 nF
2.2 mF
VIN
AGND1
REF
CAP
ADS8505
OPA132
or
AGND2
DGND
GND
GND
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Figure 27. Typical Driving Circuit ( ±10 V, No Trim)
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APPLICATION INFORMATION
CALIBRATION
Hardware Calibration
Software Calibration
No Calibration
1
2
3
4
5AGND2
CAP
REF
AGND1
VIN
+
+5 V +
Gain
Offset
1
2
3
4
5AGND2
CAP
REF
AGND1
VIN
+
+
±10 V 200 Ω
33.2 kΩ
50 kΩ
50 kΩ
2.2 µF
2.2 µF
2.2 µF
2.2 µF
200 Ω
33.2 kΩ
±10 V
(a) ±10 V With Hardware Trim (b) ±10 V Without Hardware Trim
Note: Use 1% metal film resistors.
576 kΩ
REFERENCE
REF
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
The ADS8505 can be trimmed in hardware or software. The offset should be trimmed before the gain since theoffset directly affects the gain. To achieve optimum performance, several iterations may be required.
To calibrate the offset and gain of the ADS8505, install the proper resistors and potentiometers as shown inFigure 28 (a).
To calibrate the offset and gain of the ADS8505 in software, no external resistors are required. See the NoCalibration section for details on the effects of the external resistors.
See Figure 28 (b) for circuit connections. The external resistors shown in Figure 28 (b) may not be necessary insome applications. These resistors provide compensation for an internal adjustment of the offset and gain whichallows calibration with a single supply.
Figure 28. Circuit Diagram With and Without External Resistors
The ADS8505 can operate with its internal 2.5-V reference or an external reference. By applying an externalreference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internallywith the output on CAP (pin 4).
The internal reference has an 8 ppm/ °C drift (typical) and accounts for approximately 20% of the full-scale error(FSE = ±0.5%).
REF (pin 3) is an input for an external reference or the output for the internal 2.5-V reference. A 2.2- µF capacitorshould be connected as close to the REF pin as possible. The capacitor and the output resistance of REF createa low-pass filter to bandlimit noise on the reference. Using a smaller value capacitor introduces more noise tothe reference degrading the SNR and SINAD. The REF pin should not be used to drive external ac or dc loads.
The range for the external reference is 2.3 V to 2.7 V and determines the actual LSB size. Increasing thereference voltage increases the full-scale range and the LSB size of the converter which can improve the SNR.
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CAP
LAYOUT
POWER
GROUNDING
SIGNAL CONDITIONING
INTERMEDIATE LATCHES
ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
APPLICATION INFORMATION (continued)
CAP (pin 4) is the output of the internal reference buffer. A 2.2- µF capacitor can be placed between the CAP pinand ground. Because the internal reference buffer is internally compensated, the external capacitor is notnecessary for compensation of the reference buffer. This relaxes the performance requirements of the capacitorand makes the performance of the ADC less sensitive to the capacitor.
The output of the buffer is capable of driving up to 2 mA of current to a dc load. A dc load requiring more than 2mA of current from the CAP pin begins to degrade the linearity of the ADS8505. Using an external buffer allowsthe internal reference to be used for larger dc loads and ac loads. Do not attempt to directly drive an ac loadwith the output voltage on CAP. This causes performance degradation of the converter.
For optimum performance, tie the analog and digital power pins to the same +5-V power supply and tie theanalog and digital grounds together. As noted in the electrical specifications, the ADS8505 uses 90% of itspower for the analog circuitry. The ADS8505 should be considered as an analog component.
The +5-V power for the A/D should be separate from the +5 V used for the system's digital logic. ConnectingV
DIG
(pin 28) directly to a digital supply can reduce converter performance due to switching noise from the digitallogic. For best performance, the +5-V supply can be produced from whatever analog supply is used for the restof the analog signal conditioning. If +12-V or +15-V supplies are present, a simple +5-V regulator can be used.Although it is not suggested, if the digital supply must be used to power the converter, be sure to properly filterthe supply. Either using a filtered digital supply or a regulated analog supply, both V
DIG
and V
ANA
should be tiedto the same +5-V source.
Three ground pins are present on the ADS8505. DGND is the digital supply ground. AGND2 is the analogsupply ground. AGND1 is the ground which all analog signals internal to the A/D are referenced. AGND1 is moresusceptible to current induced voltage drops and must have the path of least resistance back to the powersupply.
All the ground pins of the A/D should be tied to the analog ground plane, separated from the system's digitallogic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to thesystem ground as near to the power supplies as possible. This helps to prevent dynamic digital ground currentsfrom modulating the analog ground through a common impedance to power ground.
The FET switches used for the sample/hold on many CMOS A/D converters release a significant amount ofcharge injection which can cause the driving op-amp to oscillate. The FET switch on the ADS8505, compared tothe FET switches on other CMOS A/D converters, releases 5% to 10% of the charge. There is also a resistivefront end which attenuates any charge which is released. The end result is a minimal requirement for theanti-alias filter on the front end. Any op-amp sufficient for the signal in an application is sufficient to drive theADS8505.
The resistive front end of the ADS8505 also provides an assured ±25-V overvoltage protection. In most cases,this eliminates the need for external input protection circuitry.
The ADS8505 does have 3-state outputs for the parallel port, but intermediate latches should be used if the busis to be active during conversions. If the bus is not active during conversion, the 3-state outputs can be used toisolate the A/D from other peripherals on the same bus. The 3-state outputs can also be used when the A/D isthe only peripheral on the data bus.
16
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ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Intermediate latches are beneficial on any monolithic A/D converter. The ADS8505 has an internal LSB size of38 µV. Transients from fast switching signals on the parallel port, even when the A/D is 3-stated, can be coupledthrough the substrate to the analog circuitry causing degradation of converter performance.
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ADS8505
SLAS180B – SEPTEMBER 2005 – REVISED JUNE 2007
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September, 2005) to A Revision ............................................................................................. Page
•Added SFDR value ............................................................................................................................................................... 1•Changed 3.0 to 1.5 Max INL ................................................................................................................................................. 1•Changed 3.0 to 1.5 Minimum Relative Accuracy .................................................................................................................. 2•Changed REF and CAP - reversed ...................................................................................................................................... 2•Changed INL, SFDR, THD, SNR values .............................................................................................................................. 2•Changed SFDR-TA, THD-TA, SINAD-TA, SNR-fi, SINAD-fi SFDR-fi, THD-fi, IDD-TA, CAP ESR, INL, DNL, andFFT curves ............................................................................................................................................................................ 6•Changed CAP description................................................................................................................................................... 16
Changes from A Revision (October, 2006) to B Revision ............................................................................................. Page
•Deleted text from basic operation description ...................................................................................................................... 8•Changed text in starting a conversion description ................................................................................................................ 9•Changed operation descriptions and R/ C in table ................................................................................................................ 9•Added SAR Reset timing .................................................................................................................................................... 13•Added ADC RESET section ............................................................................................................................................... 13
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS8505IBDB ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IBDBG4 ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IBDBR ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IBDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IBDW ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IBDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IBDWR ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IBDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDB ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDBG4 ACTIVE SSOP DB 28 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDBR ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDW ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDWG4 ACTIVE SOIC DW 28 20 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDWR ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8505IDWRG4 ACTIVE SOIC DW 28 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 26-May-2007
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 26-May-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS8505IBDBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
ADS8505IBDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
ADS8505IDBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1
ADS8505IDWR SOIC DW 28 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS8505IBDBR SSOP DB 28 2000 367.0 367.0 38.0
ADS8505IBDWR SOIC DW 28 1000 367.0 367.0 55.0
ADS8505IDBR SSOP DB 28 2000 367.0 367.0 38.0
ADS8505IDWR SOIC DW 28 1000 367.0 367.0 55.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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