100351QIX - Fairchild Semiconductor

July 1988

Revised August 2000

100351 Low Power Hex D-Type Flip-Flop

100351

Low Power Hex D-Type Flip-Flop

General Description

The 100351 contains six D-type edge-triggered, master/

slave flip-fl ops with true and compl ement out puts , a pair of

common Clock inputs (C Pa and C Pb) and com mon M aster

Reset (MR) input. Data enters a master when both CPa

and CPb are LOW and transfers to the slave when CPa and

CPb (or both) go HIGH. The MR input overrides all other

inputs and makes the Q outputs LOW. All inputs have

50 kΩ pull-down resistors.

Features

■40% power reduction of the 100151

■2000V ESD protection

■Pin/function compatible with 100151

■Voltage compensated operating range:

−4.2V to −5.7V

■Available to industrial grade temperature range

Ordering Code:

Devises also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering code.

Logic Symbol

Pin Descriptions

Connection Diagrams

24-Pin DIP/SOIC

28-Pin PL CC

Order Number Package Number Package Description

100351SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

100351PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

100351QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

100351QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Industrial Temperature Range (−40°C to +85°C)

Pin Names Description

D0–D5Data Inputs

CPa, CP bCommon Clock Inputs

MR Asynchronous Master Reset Input

Q0–Q5Data Outputs

Q0–Q5Complementary Data Outputs

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100351

Tr uth Tables

(Each Flip-flop)

Synchronous Operation

H = HIGH Voltage Le ve l

L = LOW Voltage Level

X = Don’t Care

t = Time before CP positive transition

t+1 = Time afte r CP p os i tive transi ti on



= LOW-to-HIGH transition

Asynchr on ous Op er ati on

Logic Diagram

Inputs Outputs

DnCPaCPbMR Qn(t+1)



LL L



LL H



n(t)



HL Q

n(t)

XL LL Q

n(t)

Inputs Outputs

DnCPaCPbMR Qn(t+1)

XXXH L

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100351

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: The “A bsolute Maximum Ratings” are those value s beyond whic h

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the absolute maximum rating.

The “R ecomm ended Ope rating Co ndition s” table will define the condit ions

for actu al device operation.

Note 2: ESD testing conforms to MIL-STD-883, Method 3015.

Commercial Version

DC Electrical Characteristics (N ote 3)

VEE = −4.2V to −5.7V, VCC = VCCA = GND, TC = 0°C to +85°C

Note 3: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are ch o-

sen to guarante e operation under “worst case” conditions.

DIP AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Storage Temperature (TSTG)−65°C to +150°C

Maximum Junction Temperature (TJ)+150°C

VEE Pin Potential to Ground Pin −7.0V to +0.5V

Input Voltage (DC) VEE to +0.5V

Output Current (DC Output HIGH) −50 mA

ESD (Note 2) ≥2000V

Case Temperature (TC)

Commercial 0°C to +85°C

Industrial −40°C to +85°C

Supply Voltage (VEE)−5.7V to −4.2V

Symbol Parameter Min Typ Max Units Conditions

VOH Output HIGH Voltage −1025 −955 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1705 −1620 or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1035 mV VIN = VIH (Min) Loadi ng with

VOLC Output LOW Voltage −1610 or VIL (Max) 50Ω to −2.0V

VIH Input HIGH V olta ge −1165 −870 mV Guaranteed HIGH Signal for All Inputs

VIL Input LOW V olta ge −1830 −1475 mV Guaranteed LOW Signal for All Inputs

IIL Input LOW Current 0.50 µAV

IN = VIL (Min)

IIH Input HIGH Current MR 350

D0–D5240 µAV

IN = VIH (Max)

CPa, CPb350

IEE Power Supply Current −129 −62 mA Inputs OPEN

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Toggle Frequency 375 375 375 MHz Figures 2, 3

tPLH Propagation Delay 0.80 2.00 0.80 2.0 0.90 2.10 ns Figures 1, 3

tPHL CPa, CPb to Output

tPLH Propagation Delay 1.10 2.30 1.10 2.30 1.20 2.40 ns Figures 1, 4

tPHL MR to Output

tTLH Transition Time 0.35 1.20 0.35 1.20 0.35 1.20 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D0–D50.40 0 .40 0.40 ns Figure 5

MR (Release Time) 1.60 1.60 1.60 Figure 4

tHHold Time 0.80 0.80 0.80 ns Figure 5

D0–D5

tPW(H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4

CPa, CPb, MR

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100351

Commercial Version (Continued)

SOIC and PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Note 4: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same pack-

aged d evice . The sp ecificatio ns appl y to an y output s swit ching in th e sam e direc tion eithe r HIGH- to-LOW (tOSHL), or LOW-to-H IGH (tOSLH), or in opp osite

direc ti ons both H L and LH (tOST). Parameters tOST and tPS guaranteed by design.

Symbol Parameter TC = 0°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Toggle Frequency 375 375 375 MHz Figures 2, 3

tPLH Propagation Delay 0.80 1.80 0.80 1.80 0.90 1.90 ns Figures 1, 3

tPHL CPa, CPb to Output

tPLH Propagation Delay 1.10 2.10 1.10 2.10 1.20 2.20 ns Figures 1, 4

tPHL MR to Output

tTLH Transition Time 0.45 1.70 0.45 1.60 0.45 1.70 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D0–D50.30 0.30 0.30 ns Figure 5

MR (Release Time) 1.50 1.50 1.50 Figure 4

tHHold Time 0.80 0.80 0.80 ns Figure 5

D0–D5

tPW(H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4

CPa, CPb, MR

tOSHL Maximum Skew Common Edge PLCC only

Output-to-Output Variation 220 220 220 ps (Note 4)

Clock to Output Path

tOSLH Maximum Skew Common Edge PLCC only

Output-to-Output Variation 210 210 210 ps (Note 4)

Clock to Output Path

tOST Maximum Skew Opposite Edge PLCC only

Output-to-Output Variation 240 240 240 ps (Note 4)

Clock to Output Path

tPS Maximum Skew PLCC only

Pin (Signal) Transition Variation 230 230 230 ps (Note 4)

Clock to Output Path

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100351

Industri a l Version

PLCC DC Electrical Characteristics

VEE=−4.2V to −5.7V, VCC=VCCA= GND, TC= 0°C to +85°C (Note 5)

Note 5: The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional

noise immunity an d gu ardband ing c an be achi eved by d ecre asin g the al l owable syste m operating ranges. Conditi ons fo r t estin g shown i n the tables are cho-

sen to guarante e operation under “worst case” conditions.

PLCC AC Electrical Characteristics

VEE = −4.2V to −5.7V, VCC = VCCA = GND

Symbol Parameter TC = −40°CT

C = 0° to +85°CUnits Conditions

Min Max Min Max

VOH Output HIGH Voltage −1085 −870 −1025 −870 mV VIN =VIH (Max) Loading with

VOL Output LOW Voltage −1830 −1575 −1830 −1620 or VIL (Min) 50Ω to −2.0V

VOHC Output HIGH Voltage −1095 −1035 mV VIN = VIH (Min) Loading with

VOLC Output LOW Voltage −1565 −1610 or VIL (Max) 50Ω to −2.0V

VIH Input HIGH Voltage −1170 −870 −1165 −870 mV Guaranteed HIGH Signal

for All Inputs

VIL Input LOW Voltage −1830 −1480 −1830 −1475 mV Guaranteed LOW Signal

for All Inputs

IIL Input LOW Current 0.50 0.50 µAV

IN = VIL (Min)

IIH Input HIGH Current MR 350 350

D0–D5240 240 µAV

IN = VIH (Max)

CPa, CPb350 350

IEE Power Supply Current −129 −62 −129 −62 mA Inputs OPEN

Symbol Parameter TC = −40°CT

C = +25°CT

C = +85°CUnits Conditions

Min Max Min Max Min Max

fMAX Toggle Frequency 375 375 375 MHz Figures 2, 3

tPLH Propagation Delay 0.80 1.80 0.80 1.80 0.90 1.90 ns Figures 1, 3

tPHL CPa, CPb to Output

tPLH Propagation Delay 1.10 2.10 1.10 2.10 1.20 2.20 ns Figures 1, 4

tPHL MR to Output

tTLH Transition Time 0.45 1.70 0.45 1.60 0.45 1.70 ns Figures 1, 3

tTHL 20% to 80%, 80% to 20%

tSSetup Time

D0–D50.60 0.30 0.30 ns Figure 5

MR (Release Time) 2.20 1.50 1.50 Figure 4

tHHold Time 0.60 0.90 0.90 ns Figure 5

D0–D5

tPW(H) Pulse Width HIGH 2.00 2.00 2.00 ns Figures 3, 4

CPa, CPb, MR

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100351

Test Circuitry

Notes:

VCC, VCCA = +2V, V EE = −2.5V

L1 and L2 = equa l length 50Ω impedance lines

RT = 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to VCC and VEE

All unus ed out put s are loade d w it h 50Ω to G ND

CL = Fixture and stray capacita nc e ≤ 3 pF

FIGURE 1. AC Test Circuit

Notes:

VCC, VCCA = +2V, V EE = −2.5V

L1 and L2 = equal length 50Ω impe dance lines

RT = 50Ω terminator internal to scope

Decoupling 0.1 µF from GND to VCC and VEE

All unus ed out put s are loade d w it h 50Ω to G ND

CL = Jig and str ay capacitance ≤ 3 pF

FIGURE 2. Toggle Frequency Test Circuit

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Switching Waveforms

FIGURE 3. Propagation Delay (Clock) and Transition Times

FIGURE 4. Propagation Delay (Reset)

Notes:

tS is the mini m um t im e before th e t ransition of the cloc k th at inf ormatio n m ust be present at t he data input.

tH is the mini m um t im e after the t ransition of the cloc k th at inf ormatio n m us t remain unc hanged at th e data input .

FIGURE 5. Setu p and Hold Time

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100351

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

Package Number M24B

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide

Package Number N24E

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100351 Low Power Hex D-Type Flip-Flop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square

Package Number V28A

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.