DATA SHEET MOS INTEGRATED CIRCUIT PD780204, 780205, 780206, 780208 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The PD780204, 780205, 780206, and 780208 microcontrollers are the products of PD780208 subseries in 78K/0 series, and incorporate many hardware peripherals such as an FIPTM controller/driver, 8-bit resolution A/D converter, timer, serial interface, and interrupt controller. In addition to these standard mask ROM models, one-time PROM models that can operate in the same voltage range, EPROM models PD78P0208, and various development tools are available. The functions of these microcontrollers are described in detail in the following User's Manual. Be sure to read this manual when you design a system using any of these microcontrollers. PD780208 Subseries User's Manual: U11302E 78K/0 Series User's Manual - Instruction: IEU-1372 FEATURES * High-capacity ROM and RAM Item Program Memory Data Memory Package Product Name (ROM) Internal high-speed RAM Buffer RAM PD780204 32 K bytes 1024 bytes 64 bytes PD780205 40 K bytes PD780206 48 K bytes PD780208 60 K bytes FIP display RAM Internal expansion RAM 80 bytes Not provided 100-pin plastic QFP (14 x 20 mm) 1024 bytes * Wide range of instruction execution time - from high-speed (0.4 s) to ultra low-speed (122 s) * I/O ports: 74 * FIP controller/driver: total display outputs: 53 * * * * 8-bit resolution A/D converter: 8 channels Serial interface: 2 channels Timer: 5 channels Power supply voltage: VDD = 2.7 to 5.5 V APPLICATIONS Minicomponent stereo, cassette deck, tuner, CD player, VCR. ORDERING INFORMATION Part Number Package PD780204GF-xxx-3BA PD780205GF-xxx-3BA PD780206GF-xxx-3BA PD780208GF-xxx-3BA 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Remark "xxx" indicates ROM code number. The information in this document is subject to change without notice. Document No. U10436EJ2V0DS00 (2nd edition) Date Published February 1997 N Printed in Japan The mark shows major revised point. (c) 1994 PD780204, 780205, 780206, 780208 78K/0 SERIES PRODUCT DEVELOPMENT The following shows the 78K/0 Series products development. Subseries name are shown inside frames. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin PD78075B PD78075BY PD78078 PD78078Y PD78070A PD78070AY PD780018Note PD780018YNote PD780058 PD780058YNote PD78058F PD78058FY PD78054 PD78054Y PD780034 PD780034Y PD780024 PD780024Y PD78014H PD78018F PD78018FY PD78014 PD78014Y PD780001 PD78002 PD78002Y PD78083 EMI-noise reduced version of the PD78078 A timer was added to the PD78054 and external interface was enhanced ROM-less version of the PD78078 Serial I/O of the PD78078 was enhanched and the function is limited Serial I/O of the PD78054 was enhanced and EMI-noise was reduced EMI-noise reduced version of the PD78054 UART and D/A converter were added to the PD78014 and I/O was enchanced A/D converter of the PD780024 was enchanced Serial I/O of the PD78018F was added and EMI-noise was reduced EMI-noise reduced version of PD78018F Low-voltage (1.8 V) operation version of the PD78014, with larger selection of ROM and RAM capacities An A/D converter and 16-bit timer were added to the PD78002 An A/D converter was added to the PD78002 Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) Inverter control 64-pin 64-pin 78K/0 Series A/D converter of the PD780924 was enhanced PD780964 PD780924 On-chip inverter control circuit and UART. EMI-noise was reduced. FIP drive 100-pin 100-pin 80-pin 80-pin The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53 The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48 N-ch open drain was added to the PD78044F, Display output total: 34 PD780208 PD780228 PD78044H PD78044F Basic subseries for driving FIP, Display output total: 34 LCD drive 100-pin 100-pin 100-pin PD780308 PD780308Y The SIO of the PD78064 was enhanced and ROM, RAM capacity increased PD78064B PD78064 PD78064Y EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, On-chip UART IEBusTM supported 80-pin PD78098 An IEBus controller was added to the PD78054 LV 64-pin Note 2 Under planning PD78P0914 On-chip PWM output, LV digital code decoder, and Hsync counter PD780204, 780205, 780206, 780208 The following lists the main functional differences between subseries products. Function Subseries Name Control ROM Timer 8-bit 10-bit 8-bit Serial Capacity 8-bit 16-bit Watch WDT A/D A/D D/A Interface 4ch 8ch - 2ch PD78075B 32 K - 40K PD78078 48 K - 60K PD78070A - PD780018 48 K - 60K PD780058 24 K - 60 K PD78058F 48 K - 60 K PD78054 16 K - 60 K PD780034 8 K - 32 K 1ch 1ch 1ch 2ch - 8 ch PD78014 8 K - 32 K PD780001 8K PD78002 8 K - 16 K 2.7 V 88 2ch 3ch (time division UART: 1ch) 68 1.8 V 3ch (UART: 1ch) 69 2.7 V 8ch - 3ch (UART: 1ch, time 51 1.8 V division 3-wire: 1ch) - - - 1ch 1ch - 53 - 8ch 33 1.8 V - 2c (UART: 2ch) 47 2.7 V - 2 ch 74 2.7 V 1ch 72 4.5 V 68 2.7 V 57 1.8 V PD780964 PD780924 FIP PD780208 32 K - 60 K 2 ch 1 ch 1 ch drive PD780228 48 K - 60 K 3ch - - PD78044H 32 K - 48 K 2ch 1ch 1ch PD78044F 16 K - 40 K PD780308 48 K - 60 K PD78064B 32 K PD78064 16 K - 32 K IEBus supported PD78098 32 K - 60 K 2 ch 1 ch 1 ch 1 ch 8 ch - 2 ch LV PD78P0914 32 K 6 ch - - 1 ch 8 ch - - Note - 1ch 1 ch - 1ch (UART: 1ch) control 3ch 39 53 Inverter Note 61 2.7 V PD78083 8 K - 32 K 1.8 V 2ch (time division 3-wire: 1ch) 2ch 8 K - 60 K 88 - PD78014H PD78018F VDD MIN. External Value Expansion 2.0 V PD780024 LCD drive 3ch (UART : 1ch) I/O - 8ch 8ch - 8 ch - - - 2ch 2 ch 1 ch 1 ch 1 ch 8 ch - - 3 ch (time division UART: 1ch) 2 ch (UART : 1 ch) - 2.0 V 3 ch (UART : 1 ch) 69 2.7 V 2 ch 54 4.5 V 10-bit timer: 1 channel 3 PD780204, 780205, 780206, 780208 FUNCTIONAL OUTLINE Product Name Item Internal memory ROM PD780204 PD780205 PD780206 PD780208 32 K bytes 40 K bytes 48 K bytes 60 K bytes High-speed RAM 1024 bytes Buffer RAM 64 bytes FIP display RAM 80 bytes Expansion RAM Not provided 1024 bytes General-purpose registers 8 bits x 32 registers (8 bits x 8 registers x 4 banks) Instruction cycle Variable instruction execution time w/main system clock 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 5.0 MHz) w/subsystem clock 122 s (at 32.768 kHz) Instruction set * Multiplecation/division (8 bits x 8 bits, 16 bits / 8 bits) * Bit operation (set, reset, test, Boolean algebra) I/O ports (including those Total : 74 lines multiplexed with FIP pins) * CMOS input : * CMOS I/O : 27 lines * N-ch open-drain I/O : * P-ch open-drain I/O : 24 lines * P-ch open-drain output : 16 lines FIP controller/driver A/D converter Total : 53 lines * Segment : 9 to 40 lines * Digit : 2 to 16 lines 2 lines 5 lines * 8-bit resolution x 8 channels * Supply voltage : AVDD = 4.0 to 5.5 V Serial interface * 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel * 3-wire serial I/O mode (w/automatic transfer/receive function of up to 64 bytes): 1 channel Timer * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watch timer : 1 channel * Watchdog timer : 1 channel Timer output 3 lines (one for 14-bit PWM output) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz (main system clock: at 5.0 MHz) 32.768 kHz (subsystem clock: at 32.768 kHz) Buzzer output 4 1.2 kHz, 2.4 kHz, 4.9 kHz : (main system clock: at 5.0 MHz) PD780204, 780205, 780206, 780208 Product Name PD780204 Item Vectored interrupt sources Maskable Internal: 9, external: 4 Non-maskable Internal: 1 Software 1 PD780205 Test input Internal: 1 line Supply voltage VDD = 2.7 to 5.5 V Package 100-pin plastic QFP (14 x 20 mm) PD780206 PD780208 5 PD780204, 780205, 780206, 780208 CONTENTS 1. PIN CONFIGURATION (Top View) ............................................................................................... 7 2. BLOCK DIAGRAM .......................................................................................................................... 9 3. PIN FUNCTIONS ............................................................................................................................. 10 3.1 PORT PINS ............................................................................................................................................. 10 3.2 PINS OTHER THAN PORT PINS .......................................................................................................... 12 3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ................................................................. 14 4. MEMORY SPACE............................................................................................................................ 17 5. PERIPHERAL HARDWARE FUNCTIONS ..................................................................................... 18 5.1 PORTS .................................................................................................................................................... 18 5.2 CLOCK GENERATOR CIRCUIT ........................................................................................................... 19 5.3 TIMER/EVENT COUNTER ..................................................................................................................... 19 5.4 CLOCK OUTPUT CONTROL CIRCUIT .................................................................................................. 22 5.5 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................................ 22 5.6 A/D CONVERTER .................................................................................................................................. 23 5.7 SERIAL INTERFACE ............................................................................................................................. 23 5.8 FIP CONTROLLER/DRIVER .................................................................................................................. 25 INTERRUPT FUNCTION AND TEST FUNCTION ....................................................................... 27 6.1 INTERRUPT FUNCTION ........................................................................................................................ 27 6.2 TEST FUNCTION ................................................................................................................................... 30 7. STANDBY FUNCTION .................................................................................................................... 31 8. RESET FUNCTION .......................................................................................................................... 31 9. INSTRUCTION SET ......................................................................................................................... 32 10. ELECTRICAL SPECIFICATIONS ................................................................................................... 35 11. CHARACTERISTIC CURVE (REFERENCE VALUE) ................................................................... 58 12. PACKAGE DRAWING ..................................................................................................................... 68 13. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 69 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 70 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 72 6. 6 PD780204, 780205, 780206, 780208 PIN CONFIGURATION (Top View) 100-Pin Plastic QFP (14 x 20 mm) PD780204GF - xxx - 3BA PD780205GF - xxx - 3BA PD780206GF - xxx - 3BA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD P37 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 RESET X2 X1 IC XT2 P04/XT1 VDD P27/SCK0 P26/SO0/SB1 P25/SI0/SB0 P24/BUSY P23/STB P22/SCK1 P21/SO1 P20/SI1 AVSS P17/ANI7 P16/ANI6 P15/ANI5 P14/ANI4 P13/ANI3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 P80/FIP13 P81/FIP14 P82/FIP15 P83/FIP16 P84/FIP17 P85/FIP18 P86/FIP19 PD780208GF - xxx - 3BA P87/FIP20 VLOAD P90/FIP21 P91/FIP22 P92/FIP23 P93/FIP24 P94/FIP25 P95/FIP26 P96/FIP27 P97/FIP28 P100/FIP29 P101/FIP30 P102/FIP31 P103/FIP32 P104/FIP33 P105/FIP34 P106/FIP35 P107/FIP36 P110/FIP37 P111/FIP38 P112/FIP39 P113/FIP40 P114/FIP41 P115/FIP42 P116/FIP43 P117/FIP44 P120/FIP45 P121/FIP46 P122/FIP47 P123/FIP48 P12/ANI2 P11/ANI1 P10/ANI0 AVDD AVREF P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0/TI0 VSS P74 P73 P72 P71 P70 VDD P127/FIP52 P126/FIP51 P125/FIP50 P124/FIP49 1. Cautions 1. Connect the IC (Internally Connected) pins directly to the VSS. 2. Connect the AVDD pin to the VDD pin. 3. Connect the AVSS pin to the VSS pin. 7 PD780204, 780205, 780206, 780208 8 P00-P04 : Port0 SCK0, SCK1 : Serial Clock P10-P17 : Port1 PCL : Programmable Clock P20-P27 : Port2 BUZ : Buzzer Clock P30-P37 : Port3 STB : Strobe P70-P74 : Port7 BUSY : Busy P80-P87 : Port8 FIP0-FIP52 : Fluorescent Indicator Panel P90-P97 : Port9 VLOAD : Negative Power Supply P100-P107 : Port10 X1, X2 : Crystal (Main System Clock) P110-P117 : Port11 XT1, XT2 : Crystal (Subsystem Clock) P120-P127 : Port12 RESET : Reset INTP0-INTP3 : Interrupt from Peripherals ANI0-ANI7 : Analog Input TI0-TI2 : Timer Input AVDD : Analog Power Supply TO0-TO2 : Timer Output AVSS : Analog Ground SB0, SB1 : Serial Bus AVREF : Analog Reference Voltage SI0, SI1 : Serial Input VDD : Power Supply SO0, SO1 : Serial Output VSS : Ground IC : Internally Connected PD780204, 780205, 780206, 780208 2. BLOCK DIAGRAM TO0/P30 TI0/INTP0/P00 16-bit TIMER/ EVENT COUNTER PORT 0 P00 P01 - P03 P04 PORT 1 P10 - P17 TO1/P31 TI1/P33 8-bit TIMER/ EVENT COUNTER 1 PORT 2 P20 - P27 TO2/P32 TI2/P34 8-bit TIMER/ EVENT COUNTER 2 PORT 3 P30 - P37 WATCHDOG TIMER PORT 7 P70 - P74 WATCH TIMER PORT 8 P80 - P87 PORT 9 P90 - P97 PORT 10 P100 - P107 PORT 11 P110 - P117 PORT 12 P120 - P127 FIP CONTROLLER/ DRIVER FIP0 - FIP52 SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 SERIAL INTERFACE 0 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SERIAL INTERFACE 1 ANI0/P10 ANI7/P17 AVDD AVSS AVREF A/D CONVERTER 78K/0 CPU CORE ROM RAM VLOAD INTP0/TI0/P00 INTP3/P03 BUZ/P36 INTERRUPT CONTROL BUZZER OUTPUT VDD PCL/P35 VSS IC SYSTEM CONTROL CLOCK OUTPUT CONTROL RESET X1 X2 XT1/P04 XT2 Remark The capacities of the internal ROM and RAM differ depending on the product. 9 PD780204, 780205, 780206, 780208 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name I/O P00 Input Function Input only I/O Port 0 bit units. When used as an input port pin, 5-bit I/O port an on-chip pull-up resistor can be used P03 P04Note 1 Sharde by: Input INTP0/TI0 Can be specified for input or output in 1- P01 P02 On Reset INTP1 Input INTP3 through software. Input only Input INTP2 Input XT1 Input ANI0-ANI7 Port 1 P10-P17 I/O 8-bit I/O port Can be specified for input or output in 1-bit units. When used as an input port pin, an on-chip pull-up resistor can be used through software. Note 2 P20 SI1 P21 SO1 P22 P23 Port 2 SCK1 8-bit I/O port I/O Can be specified for input or output in 1-bit units. P24 When used as an input port pin, an on-chip pull-up resistor can be P25 used through software. STB Input BUSY SI0/SB0 P26 SO0/SB1 P27 SCK0 P30 TO0 P31 Port 3 TO1 8-bit I/O port P32 TO2 Can be specified for input or output in 1-bit units. P33 P34 I/O Can directly drive LEDs. When used as an input port pin, an on-chip pull-up resistor can be TI1 Input TI2 used through software. P35 P36 P37 Notes A pull-down resistor can be connected in 1-bit units by mask PCL option. BUZ -- 1. When the P04/XT1 pins is used as an input port pin, bit 6 (FRC) of the porcessor clock control register (PCC) must be set to 1. (At this time, do not use the feedback resistor of the subsystem clock oscillator circuit.) 2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be sure to place the port 1 in the input mode. In this case, the on-chip pull-up resistors are automaticaly unused. 10 PD780204, 780205, 780206, 780208 3.1 PORT PINS (2/2) Pin Name I/O Function On Reset Shared by: Input -- Output FIP13-FIP20 Output FIP21-FIP28 Input FIP29-FIP36 Input FIP37-FIP44 Input FIP45-FIP52 Port 7 5-bit N-ch open-drain I/O port P70-P74 I/O Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-up resistor can be connected in 1-bit units by mask option. Port 8 8-bit P-ch open-drain high-voltage output port P80-P87 Output Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Port 9 8-bit P-ch open-drain high-voltage output port P90-P97 Output Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Port 10 8-bit P-ch open-drain high-voltage output port P100-P107 I/O Can be specified for input or output in bit units. Can directly drive LEDs. A pull-down resistor can be connected in 1-bit units by mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Port 11 8-bit P-ch open-drain high-voltage I/O port P110-P117 I/O Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pull-down resistor can be conneced in 1-bit units by mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). Port12 8-bit P-ch open-drain high-voltage I/O port. P120-P127 I/O Can be specified for input or output in 1-bit units. Can directly drive LEDs. A pul-down resistor can be connected in 1-bit units by mask option (whether VLOAD or VSS is connected can be specified in 4-bit units). 11 PD780204, 780205, 780206, 780208 3.2 PINS OTHER THAN PORT PINS (1/2) Pin Name Function I/O INTP0 On Reset P00/TI0 Input INTP2 Valid edge (rising, falling, or both rising and falling edges) can be specified. External interrupt request input INTP3 Falling edge-active external interrupt input Input Serial data input lines of serial interface Input INTP1 Input Shared by: P01 P02 SI0 P03 P25/SB0 Input SI1 P20 SO0 P26/SB1 Output Serial data output lines of serial interface Input SO1 P21 SB0 P25/SI0 I/O Serial data I/O lines of serial interface Input SB1 P26/SO0 SCK0 P27 I/O Serial clock I/O lines of serial interface Input SCK1 P22 STB Output Automatic transfer/receive strobe output line of serial interface Input P23 BUSY Input Automatic transfer/receive busy input line of serial interface Input P24 TI0 TI1 External count clock input to 16-bit timer (TM0) Input External count clock input to 8-bit timer (TM1) P00/INTP0 Input P33 TI2 External count clock input to 8-bit timer (TM2) P34 TO0 16-bit timer (TM0) output (multiplexed with 14-bit PWM output) P30 TO1 Output TO2 8-bit timer (TM1) output Input 8-bit timer (TM2) output P31 P32 PCL Output Clock output (for trimming main system clock and subsystem clock) Input P35 BUZ Output Buzzer output Input P36 FIP0-FIP12 Output High-voltage, high-current output for FIP controller/driver display output A pull down register can be connected by mask option. Output - FIP13-FIP20 Output FIP21-FIP28 FIP29-FIP36 P90-P97 Output High-voltage, high-current output for FIP controller/driver display output FIP37-FIP44 P100-P107 Input FIP45-FIP52 VLOAD 12 P80-P87 P110-P117 P120-P127 - Connects pull-down resistor to FIP controller/driver - - PD780204, 780205, 780206, 780208 3.2 PINS OTHER THAN PORT PINS (2/2) Pin Name I/O Function On Reset Shared by: ANI0-ANI7 Input A/D converter analog input lines Input P10-P17 AVREF Input A/D converter reference voltage input line -- -- AVDD -- Analog power supply to A/D converter. Connected to VDD pin. -- -- AVSS -- A/D converter ground line. Connected to VSS pin. -- -- RESET Input System reset input -- -- X1 Input -- -- -- -- Input P04 -- -- Connect crystal for main system clock oscillation. X2 -- XT1 Input Connect crystal for subsystem clock oscillation. XT2 -- VDD -- Positive power supply -- -- VSS -- Ground potential -- -- IC -- Internal connection. Connected directly to VSS pin. -- -- 13 PD780204, 780205, 780206, 780208 3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 3-1. Table 3-1. I/O Circuit Type I/O Circuit Type I/O 2 Input 8-A I/O P04/XT1 16 Input P10/ANI0-P17/ANI7 11 P20/SI1 8-A P21/SO1 5-A P22/SCK1 8-A P23/STB 5-A P24/BUSY 8-A Pin Name P00/INTP0/TI0 Recommended Connections When Unused Connect to VSS P01/INTP1 P02/INTP2 Independently connect to Vss through resistor P03/INTP3 Connect to VDD or VSS P25/SI0/SB0 P26/SO0/SB1 10-A I/O P27/SCK0 Independently connect to VDD or VSS through resistor P30/TO0 P31/TO1 5-C P32/TO2 P33/TI1 8-B P34/TI2 P35/PCL P36/BUZ 5-C P37 P70-P74 13-B FIP0-FIP12 14-A Output 15-C I/O Independently connect to VDD or VSS through resistor RESET 2 Input -- XT2 16 P80/FIP13-P87/FIP20 Open P90/FIP21-P97/FIP28 P100/FIP29-P107/FIP36 P110/FIP37-P117/FIP44 P120/FIP45-P127/FIP52 Open AVREF Connect to VSS AVDD Connect to VDD -- AVSS -- Connect to VSS VLOAD IC 14 Connect directly to VSS PD780204, 780205, 780206, 780208 Figure 3-1. Pin I/O Circuits (1/2) Type 2 Type 8-A VDD pullup enable P-ch V DD IN data P-ch IN/OUT output disable N-ch Schmitt trigger input with hysteresis characteristics Type 5-A Type 8-B V DD pullup enable pullup enable P-ch V DD data V DD P-ch V DD P-ch data P-ch IN/OUT output disable N-ch IN/OUT output disable N-ch (Mask Option) input enable Type 5-C Type 10-A V DD pullup enable P-ch V DD pullup enable P-ch V DD data V DD P-ch IN/OUT output disable data P-ch IN/OUT N-ch (Mask Option) open drain output disable N-ch input enable 15 PD780204, 780205, 780206, 780208 Figure 3-1. Pin I/O Circuits (2/2) Type 15-C V DD Type 11 pullup enable V DD P-ch V DD P-ch P-ch V DD data IN/OUT data P-ch IN/OUT output disable N-ch N-ch P-ch Comparator + RD - N-ch N-ch V REF (Threshold voltage) (Mask Option) input enable Type 13-B Type 16 V DD (Mask Option) feedback cut-off P-ch IN/OUT data output disable N-ch V DD RD P-ch XT1 Medium-voltage input buffer Type 14-A V DD P-ch V DD P-ch OUT data N-ch (Mask Option) V LOAD (Mask Option) 16 (Mask Option) XT2 V LOAD PD780204, 780205, 780206, 780208 4. MEMORY SPACE Figure 4-1 shows the memory maps for PD780204, 780205, 780206, and 780208. Figure 4-1. Memory Map FFFFH FF00H FEFFH FEE0H FEDFH Special function register (SFR) 256 x 8 bits FA2FH Inhibited F800H F7FFH General-purpose register 32 x 8 bits F400H F3FFH Internal high-speed RAM 1024 x 8 bits Inhibited nnnnH+1 FB00H FAFFH Data memory space nnnnH Program area Buffer RAM 64 x 8 bits 1000H 0FFFH FAC0H FABFH FA80H FA7FH FA30H FA2FH CALLF entry area Inhibited 0800H 07FFH FIP display RAM 80 x 8 bits Program area 0080H 007FH Inhibited CALLT entry area nnnnH+1 nnnnH Program memory space Internal expansion RAM 1024 x 8 bits Note 1 Internal ROM 0040H 003FH Note 2 Vector table area 0000H 0000H Notes 1. PD780206 and 780208 only. 2. The internal ROM capacities vary depending on the product. (Refer to the table below.) Product Name Internal ROM Last Address nnnnH PD780204 7FFFH PD780205 9FFFH PD780206 BFFFH PD780208 EFFFH 17 PD780204, 780205, 780206, 780208 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS I/O ports are classified into the following 5 kinds: * CMOS input (P00, P04) :2 * CMOS input/output (P01 - P03, ports 1-3) : 27 * N-ch open-drain input/output (port 7) :5 * P-ch open-drain output (ports 8, 9) : 16 * P-ch open-drain input/output (ports 10 - 12) : 24 Total : 74 Table 5-1. Port Function Name Pin Name P00, P04 Input port P01-P03 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Port 1 P10-P17 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Port 2 P20-P27 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Port 3 P30-P37 I/O port. Can be specified for input or output in 1-bit units. When used as input port, internal pull-up resistor can be connected through software. Pull-down resistor can be connected in 1-bit units by mask option. Can directly drive LED. Port 7 P70-P74 N-ch open-drain I/O port. Can be specified for input or output in 1-bit units. Pull-up resistor can be connected in 1-bit units by mask option. Can directly drive LED. Port 8 P80-P87 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LEDs. Port 9 P90-P97 P-ch open-drain high-voltage output port. Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LEDs. Port 10 P100-P107 P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LEDs. Port 11 P110-P117 P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LEDs. Port 12 P120-P127 P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units. Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD or VSS can be specified in 4-bit units). Can directly drive LEDs. Port 0 18 Function PD780204, 780205, 780206, 780208 5.2 CLOCK GENERATOR CIRCUIT The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock. The instruction time can be changed. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (with main system clock: 5.0 MHz) * 122 s (with subsystem clock: 32.768 kHz) Figure 5-1. Clock Generator Circuit Block Diagram XT2 f XT Clock output circuit Selector Subsystem clock generator circuit XT1/P04 Noise detector circuit Selector fX 8 Watch timer fX 16 Pre-scaler X2 Pre-scaler fX fX 2 fX 22 fX 23 2 Clock to hardware peripherals f XT 2 fX 24 Selector Main system clock generator circuit X1 1 STOP Standby control circuit CPU clock (fCPU) To INTP0 sampling clock 5.3 TIMER/EVENT COUNTER Five channels of timer/event counters are provided. * 16-bit timer/event counter : 1 channel * 8-bit timer/event counter : 2 channels * Watch timer : 1 channel * Watchdog timer : 1 channel Function Group Table 5-2. Timer/Event Counter Groups and Configurations 16-bit Timer/ Event Counter 8-bit Timer/ Event Counter Watch Timer Watchdog Timer Interval timer 1 channel 2 channels 1 channel 1 channel External event counter 1 channel 2 channels - - Timer output 1 output 2 outputs - - PWM output 1 output - - - 1 input - - - 1 output 2 outputs - - Interrupt Request 1 2 1 1 Test input - - 1 input - Pulse width measurement Square wave output 19 PD780204, 780205, 780206, 780208 Figure 5-2. 16-Bit Timer/Event Counter Block Diagram Internal bus 16-bit compare register (CR00) INTTM0 PWM pulse output control circuit Coincidence fX Selector f X/2 f X/22 f X/23 TI0/INTP0/P00 Output control circuit TO0/P30 16-bit timer register(TM0) Edge detector circuit Selector Cleared INTP0 16-bit capture register (CR01) Internal bus Figure 5-3. 8-Bit Timer/Event Counter Block Diagram Internal bus 8-bit compare register (CR10) 8-bit compare register (CR20) Coincidence Coincidence Selector INTTM1 Output control circuit TO2/P32 f X/212 8-bit timer register 1 (TM1) TI1/P33 f X/2 2 -fX/210 f X/212 Selector Cleared Selector f X/22 -fX/210 Selector INTTM2 8-bit timer register 2 (TM2) Cleared Selector TI2/P34 Output control circuit Internal bus 20 TO1/P31 PD780204, 780205, 780206, 780208 Selector f X/2 f XT fW Pre-scaler fW 25 fW 26 fW 27 fW 28 5-bit counter INTWT fW 213 fW 29 Selector fW 24 fW 214 Selector 8 Selector Figure 5-4. Watch Timer Block Diagram INTTM3 f WDT Pre-selector f WDT 2 f WDT 22 f WDT 23 f WDT 24 f WDT 25 f WDT 26 f WDT 28 8-bit counter Control circuit fX 23 Selector fX 24 Selector Figure 5-5. Watchdog Timer Block Diagram INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request 21 PD780204, 780205, 780206, 780208 5.4 CLOCK OUTPUT CONTROL CIRCUIT Clocks of the following frequencies can be output to the clock : * 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz) * 32.768 kHz (with subsystem clock: 32.768 kHz) Figure 5-6. Clock Output Control Circuit Block Diagram f X /2 3 f X /2 4 Selector f X /2 5 f X /2 6 f X /2 7 Output control circuit Sync circuit PCL/P35 8 f X /2 f XT 5.5 BUZZER OUTPUT CONTROL CIRCUIT Clocks of the following frequencies can be output to the buzzer: * 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz) f X /2 10 22 f X /2 11 f X /2 12 Selector Figure 5-7. Buzzer Output Control Circuit Block Diagram Output control circuit BUZ/P36 PD780204, 780205, 780206, 780208 5.6 A/D CONVERTER An 8-bit resolution 8-channel A/D converter is provided. This A/D converter can be started in the following two modes: * Hardware start * Software start Figure 5-8. A/D Converter Block Diagram Series resistor string AVDD ANI0/P10 AVREF ANI2/P12 ANI4/P14 Voltage comparator Selector ANI3/P13 Tap selector Sample & hold circuit ANI1/P11 ANI5/P15 ANI6/P16 AVSS Successive approximation registor (SAR) ANI7/P17 INTP3/P03 Falling edge detector circuit Control circuit INTAD INTP3 A/D conversion result register (ADCR) Internal bus 5.7 SERIAL INTERFACE Two channels of clocked serial interfaces are provided. * Serial interface channel 0 * Serial interface channel 1 Table 5-3. Serial Interface Groups and Functions Function Serial Interface Channel 0 Serial Interface Channel 1 3-line serial I/O mode (MSB/LSB first selectable) (MSB/LSB first selectable) SBI (serial bus interface) mode (MSB first) - 2-line serial I/O mode (MSB first) - 3-line serial I/O mode w/automatic transfer/reception - (MSB/LSB first selectable) function 23 PD780204, 780205, 780206, 780208 Figure 5-9. Serial Interface Channel 0 Block Diagram Internal bus Selector SI0/SB0/P25 Selector SO0/SB1/P26 Serial I/O shift register 0 (SIO0) Output latch Busy/acknowledge output circuit Bus release/ command/acknowledge detector circuit SCK0/P27 Interrupt request signal generator circuit Serial clock control circuit INTCSI0 f X/22 -fX/29 Selector Serial clock counter TO2 Figure 5-10. Serial Interface Channel 1 Block Diagram Internal bus Automatic data transfer/ reception address pointer (ADTP) Automatic data transfer/reception interval specification register (ADTI) Buffer RAM Coincidence Serial I/O shift register 1 (SIO1) SI1/P20 SO1/P21 5-bit counter BUSY/P24 SCK1/P22 Handshake control circuit Serial clock counter Serial clock control circuit 24 Interrupt request signal generator circuit Selector STB/P23 INTCSI1 f X/22 -f X/29 TO2 PD780204, 780205, 780206, 780208 5.8 FIP CONTROLLER/DRIVER An FIP controller/driver having the following features is provided: (a) Automatic output of segment signals (DMA operation) and digit signals by automatically reading display data (b) Display mode register 0-2 (DSPM0-DSPM2) that can control an FIP of 9 to 40 segments and 2 to 16 digits (c) The output timing of the digit signal can be freely set by selecting the display mode 2 by using the display mode register 0 (DSPM0). (d) Port pins not used for FIP display can be used as output port or I/O port pins (however, FIP0-FIP12 are display output pins). (e) Display mode register 1 (DSPM1) can adjust luminance in eight steps. (f) Hardware suitable for key scan application using segment pins (g) High-voltage output buffer (FIP driver) that can directly drive an FIP (h) Display output pins can be connected to a pull-down resistor by mask option. Figure 5-11. Selecting Display Modes Selecting number of digits 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 9 10 11 12 13 Selecting number of segments 14 15 16 17 18 19 20 36 37 38 39 40 Caution If the total number of digits and segments exceeds 53, the specified number of digits takes precedence. 25 PD780204, 780205, 780206, 780208 Figure 5-12. FIP Controller/Driver Block Diagram Internal bus Write mask control circuit Display data memory Digit signal generation circuit Display data selector Display data latch Port output latch High-voltage buffer FIP0 26 FIP13/P80 FIP52/P127 PD780204, 780205, 780206, 780208 6. INTERRUPT FUNCTION AND TEST FUNCTION 6.1 INTERRUPT FUNCTION The following three types, 15 sources of interrupt functions are available: * Non-maskable : 1 * Maskable : 13 * Software : 1 Table 6-1. Interrupt Sources Interrupt Source Interrupt Type Default PriorityNote 1 Name Nonmaskable -- INTWDT 0 INTWDT 1 INTP0 2 INTP1 Trigger Software Vector Table Address Internal 0004H Overflow of watchdog timer (when watchdog timer mode 1 is selected) Basic Configuration TypeNote 2 (A) Overflow of watchdog timer (when interval timer mode is selected) (B) 0006H (C) 0008H Pin input edge detection Maskable Internal/ External External 3 INTP2 000AH 4 INTP3 000CH 5 INTCSI0 End of transfer by serial interface channel 0 000EH 6 INTCSI1 End of transfer by serial interface channel 1 0010H 7 INTTM3 Reference time interval signal from watch timer 0012H 8 INTTM0 Coincidence signal generation of 16-bit timer/event counter 9 INTTM1 Coincidence signal generation of 8-bit timer/event counter 1 0016H 10 INTTM2 Coincidence signal generation of 8-bit timer/event counter 2 0018H 11 INTAD End of conversion by A/D converter 001AH 12 INTKS Key scan timing from FIP controller/ driver 001CH -- BRK Execution of BRK instruction 003EH Internal 0014H (D) (B) (E) Notes 1. The default priority is assumed when two or more maskable interrupts are generated at the same time, and 0 is the highest and 12 is the lowest. 2. Basic configuration types (A)-(E) respectively correspond to (A) to (E) in Figure 6-1. 27 PD780204, 780205, 780206, 780208 Figure 6-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal bus Interrupt request Priority control circuit Vector table address generator circuit Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE PR ISP Vector table address generator circuit Priority control circuit IF Standby release signal (C) External maskable interrupt (INTP0) Internal bus Sampling clock select register (SCS) Interrupt request Sampling clock External interrupt mode register (INTM0) Edge detector circuit MK IF IE PR Priority control circuit ISP Vector table address generator circuit Standby release signal 28 PD780204, 780205, 780206, 780208 Figure 6-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (except INTP0) Internal bus External interrupt mode register (INTM0) Edge detector circuit Interrupt request MK IE PR Priority control circuit IF ISP Vector table address generator circuit Standby release signal (E) Software interrupt Internal bus Interrupt request IF Priority control circuit Vector table address generator circuit : Interrupt request flag IE : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 29 PD780204, 780205, 780206, 780208 6.2 TEST FUNCTION The following trigger is available for test function. Test Input Source Internal/ Name Trigger External INTWT Overflow of watch timer Internal Figure 6-2. Basic Configuration of Test Function Internal bus MK Test input source (INTWT) IF : Test request flag MK : Test mask flag 30 IF Standby release signal PD780204, 780205, 780206, 780208 7. STANDBY FUNCTION The standby function is to reduce the current dissipation of the system and can be effected in the following two modes: * HALT mode: In this mode, the operating clock of the CPU is stopped. By using this mode in combination with the normal operation mode, the system can be operated intermittently, so that the average current dissipation can be reduced. * STOP mode: Oscillation of the main system clock is stopped. All the operations on the main system clock are stopped, and therefore, the current dissipation of the system can be minimized with only the subsystem clock oscillating. Figure 7-1. Standby Function Main system clock operation STOP instruction Interrupt request STOP mode (Oscillation of main system clock stopped) Note CSS=1 CSS=0 Subsystem clock operationNote HALT instruction Interrupt request HALT instruction Interrupt request HALT mode (Clock supply to CPU stopped. Oscillation continues) HALT modeNote (Clock supply to CPU stopped. Oscillation continues) By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on the subsystem clock, stop the main system clock by setting the MCC. The STOP instruction cannot be used. Caution To select the main system clock again after the main system clock has been stopped once while the subsystem clock is in use, make sure through the program that the oscillation stabilization time elapses, and then that the main system clock is selected. 8. RESET FUNCTION The system can be reset in the following two modes: * External reset by RESET pin * Internal reset by watchdog timer that detects hang up 31 PD780204, 780205, 780206, 780208 9. INSTRUCTION SET (1) 8-bit instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand #byte A rNote sfr saddr MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW [DE] [HL] [HL + byte] [HL + B] [HL + C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP First Operand A ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV MOV XCH 1 None ROR ROL RORC ROLC MOV ADD ADDC SUB SUBC AND OR XOR CMP B,C INC DEC DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV !addr16 PSW MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP $addr16 DBNZ INC DEC MOV MOV MOV [DE] MOV [HL] MOV [HL + byte] [HL + B] [HL + C] MOV PUSH POP ROR4 ROL4 X MULU C DIVUW Note Except for r=A 32 PD780204, 780205, 780206, 780208 (2) 16-bit instruction MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rpNote sfrp saddrp !addr16 SP None First Operand AX ADDW SUBW CMPW rp MOVW sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW XCHW MOVW MOVW MOVW MOVW Note INCW DECW PUSH POP MOVW MOVW SP MOVW MOVW Note Only when rp=BC, DE, HL (3) Bit manipulation instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 First Operand CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 33 PD780204, 780205, 780206, 780208 (4) Call/Branch instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 CALL BR CALLF CALLT First Operand Basic operation BR Compound operation (5) BR BC BNC BZ BNZ BT BF BTCLR DBNZ Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 34 PD780204, 780205, 780206, 780208 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 C) Parameter Supply voltage Symbol Conditions Rating VDD -0.3 to +7.0 V VLOAD VDD -45 to VDD +0.3 V AVDD -0.3 to VDD +0.3 V AVREF -0.3 to VDD +0.3 V AVSS -0.3 to +0.3 V Input voltage Output voltage Analog input voltage VI1 P00 to P04, P10 to P17 (except analog input pin), P20 to P27, P30 to P37, X1, X2, XT2, RESET -0.3 to VDD +0.3 V VI2 P70 to P74 -0.3 to +16 Note 1 V VI3 P100 to P107, P110 to P117, P120 to P127 P-ch open drain VDD -45 to VDD +0.3 V VO1 P01 to P03, P10 to P17, P20 to P27, P30 to P37 -0.3 to VDD +0.3 V VO2 P70 to P74 -0.3 to +16 Note 1 V VOD P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, FIP0 to FIP12 VDD -45 to VDD +0.3 V VAN ANI0 to ANI7 AVSS -0.3 to AVREF +0.3 V 1 pin of P01 to P03, P10 to P17, P20 to P27, P30 to P37 -10 mA Total for P01 to P03, P10 to P17, P20 to P27, P30 to P37 -30 mA 1 pin of P80 to P87, P90 to P97, P100 to P107, P110 to P117, -30 mA -240 mA N-ch open drain Analog input pins P120 to P127, FIP0 to FIP12 High-level output current IOH Total for P80 to P87, FIP0 to FIP12 Peak value RMS Total for P90 to P97, P100 to P107, Peak value P110 to 117, P120 to P127 RMS 1 pin of P01 to P03, P10 to P17, P20 to Peak value P27, P30 to P37, P70 to P74 RMS Low-level output current IOL Total for P70 to P74 P10 to17, P20 to 27, P30 to P37 PT Note 3 Operating ambient temperature Storage temperature Caution Note 2 -100 Note 2 -60 mA mA mA 30 mA 15 Note 2 mA 100 mA Note 2 mA Peak value 50 mA RMS Note 2 mA 60 20 800 mW 600 mW TA -40 to +85 C Tstg -65 to +150 C dissipation TA = -40 to +60 C -120 Peak value RMS Total for P01 to P03, Total power Unit Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, dual-function pin characteristics are the same as port pin characteristics. Notes 1. With the mask option, the range of the internal pull-up resistor pin is 0.3 to VDD +0.3. 2. The RMS should be calculated as follows: [RMS] = [Peak value] x Duty 35 PD780204, 780205, 780206, 780208 Total power dissipation PT [mW] Notes 3. Total power dissipation differs depending on the temperature (see the following figure). 800 600 400 200 -40 0 +40 +80 Temperature [C] How to calculate total power dissipation The following three power dissipation are available for the PD780204, 780205, 780206, and 780208. The sum of the three power dissipation should be less than the total power dissipation PT (80 % or less of ratings is recommended). <1> CPU power dissipation: calculate VDD (MAX.) x IDD1 (MAX.). <2> Output pin power dissipation: Normal output and display output are available. Power dissipation when maximum current flows into each output. <3> Pull-down resistor power dissipation: Power dissipation by pull-down resistor incorporated in display output pin by mask option. The following is how to calculate total power dissipation for the example in the next page. Example Assume the following conditions: VDD = 5 V 10 %, 5.0 MHz oscillator Supply current (IDD) = 21.6 mA Display output: 11 grids x 10 segments (Cut width = 1/16) Maximum current at the grid pin is 15 mA. Maximum current at the segment pin is 3 mA. At the key scan timing, display output pin is OFF. Display output voltage: grid VOD = VDD - 2 V (voltage drop of 2 V) segments VOD = VDD - 0.4 V (voltage drop of 0.4 V) Fluorescent display control voltage (VLOAD) = -35 V Mask option pull-down resistor = 25 k 36 PD780204, 780205, 780206, 780208 By placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out. <1> CPU power dissipation: 5.5 V x 21.6 mA = 118.8 mW <2> Output pin power dissipation: (VDD - VOD) x Grid =2Vx Segment (VDD - VOD) x Total current value of each grid x Digit width (1 - Cut width) The number of grids + 1 15 mA x 11 Grids 1 x (1 - ) = 25.8 mW 11 Grids + 1 16 Total segment current value of illuminated dots The number of grids +1 = 0.4 V x 3 mA x 31 Dots = 3.1 mW 11 Grids + 1 <3> Pull-down resistor power dissipation: (VOD - VLOAD)2 Grid = Segment = Pull-down resistor value (5.5 V - 2 V - (-35 V))2 25 k The number of grids x Digit width The number of grids + 1 11 Grids 1 x x (1 - ) = 50.9 mW 11 Grids + 1 16 x The number of illuminated dots (VOD - VLOAD)2 x Pull-down resistor value The number of grids + 1 (5.5 V - 0.4 V - (-35 V))2 31 dots x = 166.1 mW 25 k 11 Grids + 1 Total power dissipation = <1> + <2> + <3> = 118.8 + 25.8 + 3.1 + 50.9 + 166.1 = 364.7 mW In this example, the total power dissipation do not exceed the rating of the total power dissipation, so there is no problem in power dissipation. However, when the total power dissipation exceeds the rating of the total power dissipation, it is necessary to lower the power dissipation. To reduce power dissipation, reduce the number of pull-down resistor. 37 38 Figure 10-1 Display Example of 10 segments-11 digits Display Data Memory FA7AH FA79H FA6AH FA69H a b c d e f g h i T10 FA75H FA74H FA73H FA65H FA64H FA63H FA72H FA71H FA70H FA62H FA61H FA60H 0 0 0 0 0 1 0 0 1 0 0 Bit 7 0 1 1 0 1 0 0 1 1 0 0 Bit 6 0 1 1 0 1 1 0 1 1 0 1 Bit 5 0 0 0 0 0 1 0 0 1 1 0 Bit 4 0 0 0 0 0 0 0 0 0 1 1 Bit 3 0 0 0 0 1 1 0 0 0 0 1 Bit 2 0 0 0 0 1 1 0 0 1 1 1 Bit 1 0 0 0 0 0 0 1 0 0 0 0 Bit 0 1 0 1 0 0 0 0 0 0 0 0 Bit 7 0 0 0 1 0 0 0 0 0 0 0 Bit 6 T9 T8 T7 SUN MON T6 T5 T4 T3 T2 T1 TUE WED THU FRI SAT 4 5 6 7 T0 j i 0 a f g b j* AMi PMj j* 1 2 3 e d c 8 9 10 h FA7 x H FA6 x H PD780204, 780205, 780206, 780208 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 FA78H FA77H FA76H FA68H FA67H FA66H PD780204, 780205, 780206, 780208 MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) Resonator Recommended Circuit IC Parameter Conditions Oscillator frequency X1 X2 MIN. TYP. MAX. Unit 1 (fX)Note 1 5 MHz 4 ms 5 MHz Ceramic resonator C1 C2 Oscillator stabilization timeNote 2 IC X1 X2 Crystal resonator C1 C2 Oscillator frequency (fX)Note 1 Oscillator stabilization timeNote 2 1 VDD = 4.5 to 5.5 V 4.19 10 ms 30 X1 X2 X1 input frequency (fX)Note 1 1 5 MHz X1 input high-/low-level width (tXH/t XL) 85 500 ns External clock PD74HCU04 Notes 1. Only the oscillator characteristics are shown. See AC CHARACTERISTICS for instruction execution times. 2. This is the time required for oscillation to stabilize after reset, or STOP mode release. Cautions 1. When the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance, etc. * The wiring should be kept as short as possible. * No other signal lines should be crossed. * Keep away from lines carrying a high fluctuating current. * The oscillator capacitor grounding point should always be at the same potential as VSS. * Do not connect to a ground pattern carrying a high current. * A signal should not be taken from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 39 PD780204, 780205, 780206, 780208 SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) Resonator Recommended Circuit XT1 XT2 IC R Parameter Conditions Oscillator frequency MIN. TYP. MAX. Unit 32 (fXT)Note 1 32.768 35 1.2 2 kHz Crystal resonator C3 C4 Oscillator stabilization VDD = 4.5 to 5.5 V s timeNote 2 XT1 XT2 10 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high-/low-level width (tXTH/tXTL) 5 15 s External clock Notes 1. Only the oscillator characteristics are shown. See AC CHARACTERISTICS for instruction execution times. 2. This is the time required for oscillation to stabilize after VDD reaches MIN. in the range of oscillation voltage. Cautions 1. When the subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance, etc. * * * * * * The wiring should be kept as short as possible. No other signal lines should be crossed. Keep away from lines carrying a high fluctuating current. The oscillator capacitor grounding point should always be at the same potential as VSS. Do not connect to a ground pattern carrying a high current. A signal should not be taken from the oscillator. 2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. 40 PD780204, 780205, 780206, 780208 RECOMMENDED OSCILLATOR CONSTANT (1) PD780204, 780205 Main System Clock: Ceramic Resonator (TA = -40 to +85 C) Manufacturer Product Name Frequency Circuit Constant Oscillator Voltage Range (MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V) Remark Murata Mfg. Co., Ltd. CSB1000J 1.0 100 100 3.00 5.50 Toyama CSA2.00MG040 2.0 100 100 2.80 5.50 CST2.00MG040 2.0 -- -- 2.80 5.50 CSA4.00MG 4.0 30 30 2.70 5.50 CST4.00MGW 4.0 -- -- 2.70 5.50 CSA5.00MG 5.0 30 30 2.90 5.50 CST5.00MGW 5.0 -- -- 2.90 5.50 CCR1000K2 1.0 150 150 2.70 5.50 FCR4.00MC5 4.0 -- -- 2.70 5.50 Built-in capacitor CCR4.00MC3 4.0 -- -- 2.70 5.50 Built-in capacitor FCR5.00MC5 5.0 -- -- 2.80 5.50 Built-in capacitor CCR5.00MC3 5.0 -- -- 2.70 5.50 Built-in capacitor Matsushita Electronics EFOEC5004A4 5.0 -- -- 2.70 5.50 Built-in capacitor Components Co., Ltd. EFOEN5004A4 5.0 33 33 2.70 5.50 EFOS5004B5 5.0 -- -- 2.70 5.50 TDK Corp. Built-in capacitor Built-in capacitor Built-in capacitor Built-in capacitor Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 41 PD780204, 780205, 780206, 780208 (2) PD780206, 780208 Main System Clock: Ceramic Resonator (TA = -40 to +85 C) Manufacturer Product Name Frequency Circuit Constant Oscillator Voltage Range (MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V) Remark Murata Mfg. Co., Ltd. CSB1000J 1.0 100 100 2.80 5.50 Toyama CSA2.00MG040 2.0 100 100 2.70 5.50 CST2.00MG040 2.0 -- -- 2.70 5.50 CSA4.00MG 4.0 30 30 2.70 5.50 CST4.00MGW 4.0 -- -- 2.70 5.50 CSA5.00MG 5.0 30 30 2.70 5.50 CST5.00MGW 5.0 -- -- 2.70 5.50 CCR1000K2 1.0 220 220 2.70 5.50 CCR2.0MC33 2.0 -- -- 2.70 5.50 Built-in capacitor CCR4.0MC3 4.0 -- -- 2.70 5.50 Built-in capacitor FCR4.0MC5 4.0 -- -- 2.70 5.50 Built-in capacitor CCR4.19MC3 4.19 -- -- 2.70 5.50 Built-in capacitor FCR4.19MC5 4.19 -- -- 2.70 5.50 Built-in capacitor CCR5.0MC3 5.0 -- -- 2.70 5.50 Built-in capacitor FCR5.0MC5 5.0 -- -- 2.70 5.50 Built-in capacitor Matsushita Electronics EFOEC2004A5 2.0 33 33 2.70 5.50 Components Co., Ltd. EFOEC4004A4 4.0 33 33 2.85 5.50 EFOEC4194A4 4.19 33 33 2.70 5.50 EFOEC5004A4 5.0 33 33 2.70 5.50 TDK Corp. Built-in capacitor Built-in capacitor Built-in capacitor Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 42 PD780204, 780205, 780206, 780208 CAPACITANCE (TA = 25 C, V DD = VSS = 0 V) Parameter Symbol Input capacitance CIN Output capacitance COUT Input/output capacitance CIO Conditions MIN. TYP. MAX. Unit f = 1 MHz Unmeasured pins returned to 0 V 15 pF f = 1 MHz Unmeasured pins returned to 0 V 35 pF f = 1 MHz Unmeasured pins returned to 0 V P01 to P03, P10 to P17, P20 to P27, P30 to P37 15 pF P70 to P74 20 pF P100 to P107, P110 to P117, P120 to P127 35 pF Remark Unless otherwise specified, the characteristics of the shared pin are the same as the characteristics of the port pin. POWER SUPPLY VOLTAGE (TA = -40 to +85 C) Parameter MAX. Unit 2.7Note 2 5.5 V Display controller/driver 4.5 5.5 V PWM mode of 16-bit time/event counter (TM0) 4.5 5.5 V A/D converter 4.0 5.5 V Other hardware 2.7 5.5 V CPUNote 1 Conditions MIN. TYP. Notes 1. Except for system clock oscillator, display controller/driver, and PWM. 2. Operating power supply voltage range differs depending on the cycle time. See AC CHARACTERISTICS. 43 PD780204, 780205, 780206, 780208 DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) Parameter High-level input voltage Symbol Conditions MIN. VIH1 P21, P23 VIH2 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET VIH3 P70 to P74 VIH4 X1, X2 VIH5 XT1/P04, XT2 VIH6 P10 to P17, P30 to P32, N-ch open-drain VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V P35 to P37 VIH7 P100 to P107, P110 to P117, VDD = 4.5 to 5.5 V P120 to P127 Low-level input voltage High-level output voltage Low-level output voltage TYP. MAX. Unit 0.7 VDD VDD V 0.8 VDD VDD V 0.7 VDD 15 V VDD - 0.5 VDD V 0.8 VDD VDD V 0.9 VDD VDD V 0.65 VDD VDD V 0.7 VDD VDD V 0.7 VDD VDD V VDD - 0.5 VDD V VIL1 P21, P23 0 0.3 VDD V VIL2 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET 0 0.2 VDD V VIL3 P70 to P74 0 0.3 VDD V 0 0.2 VDD V VDD = 4.5 to 5.5 V VIL4 X1, X2 VIL5 XT1/P04, XT2 VIL6 P10 to P17, P30 to P32, P35 to P37 VIL7 P100 to P107, P110 to P117, P120 to P127 VOH VOL1 VOL2 VOL3 VDD = 4.5 to 5.5 V 0 0.4 V 0 0.2 VDD V 0 0.1 VDD V 0 0.3 VDD V VDD - 40 0.3 VDD V P01 to P03, P10 to P17, P20 to P27, P30 to P37, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, FIP0 to FIP12 VDD = 4.5 to 5.5 V, IOH = -1 mA VDD - 1.0 V IOH = -100 A VDD - 0.5 V P30 to P37, P70 to P74 VDD = 4.5 to 5.5 V IOL = 15 mA P01 to P03, P10 to P17, P20 to P27 VDD = 4.5 to 5.5 V IOL = 1.6 mA SB0, SB1, SCK0 VDD = 4.5 to 5.5 V With open-drain and pull-up (R = 1 k) IOL = 400 A 0.4 2.0 V 0.4 V 0.2 VDD V 0.5 V Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin. 44 PD780204, 780205, 780206, 780208 DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) Parameter High-level input leakage current Symbol ILIH1 Conditions VIN = VDD ILIH2 MIN. TYP. MAX. Unit P00 to P03, P10 to P17, P20 to P27, P30 to P37, P70 to P74, RESET 3 A X1, X2, XT1/P04, XT2 20 A 80 A 3Note 1 A 3Note 2 A P00 to P03, P10 to P17, P20 to P27, P30 to P37, RESET -3 A X1, X2, XT1/P04 XT2 -20 A -3Note 3 A ILIH3 VIN = 15 V P70 to P74 ILIH4 P100 to P107, P110 to P117, VDD = 4.5 to 5.5 V P120 to P127 VIN = VDD Low-level input leakage current ILIL1 VIN = 0 V ILIL2 ILIL3 P70 to P74 ILIL4 P100 to P107, P110 to P117, P120 to P127 -10 A ILOH1 VOUT = VDD P01 to P03, P10 to P17, P20 to P27, P30 to P37, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, FIP0 to FIP12 3 A ILOH2 VOUT = 15 V P70 to P74, N-ch open-drain 80 A ILOL1 VOUT = 0 V P01 to P03, P10 to P17, P20 to P27, P30 to P37, P70 to P74 -3 A ILOL2 VOUT = VLOAD = VDD - 40 V P80 to P87, P90 to P97, P100 to 107, P110 to P117, P120 to P127, FIP0 to FIP12 -10 A Display output current IOD VDD = 4.5 to 5.5 V, VOD = VDD - 2 V -15 -18 Mask option pull-up resistor R1 VIN = 0 V, P70 to P74 20 40 90 k Software R2 VIN = 0 V, 15 40 90 k 500 k High-level output leakage current Note 4 Low-level output leakage current Note 4 pull-up resistor P01 to P03, P10 to P17, VDD = 4.5 to 5.5 V 20 mA P20 to P27, P30 to P37 Notes 1. For P110 to P117 and P120 to P127 without on-chip pull-down resistor (specifiable by mask option), a highlevel input leak current of 50 A (MAX.) flows only during the 1.5 clocks after an instruction has been executed to read out ports 11, 12 (P11, P12) or port mode registers 11, 12 (PM11, PM12). Outside the period of 1.5 clocks following executing a read-out instruction, the current is 3 A (MAX.). 2. For P110 to P117 and P120 to P127 without on-chip pull-down resistor (specifiable by mask option), a highlevel input leak current of 30 A (MAX.) flows only during the 1.5 clocks after an instruction has been executed to read out P11, P12, PM11, and PM12. Outside the period of 1.5 clocks following executing a read-out instruction, the current is 3 A (MAX.). 3. For P70 to P74 without on-chip pull-up resistor (specifiable by mask option), a low-level input leak current of -200 A (MAX.) flows only during the 1.5 clocks after an instruction has been executed to read out port 7 (P7) or port mode register 7 (PM7). Outside the period of 1.5 clocks following executing a read-out instruction, the current is -3 A (MAX.). 4. This current excludes the current which flows in the on-chip pull-up/pull-down resistor. Remark Unless otherwise specified, the characteritics of a shared pin are the same as those of a port pin. 45 PD780204, 780205, 780206, 780208 DC CHARACTERISTICS (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) Parameter Mask option pull-down resistor Symbol R3 R4 Power supply Note 1 current IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Conditions P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127 MIN. TYP. MAX. Unit VOD - VLOAD = 40 V 25 70 135 k VOD - VSS = 5 V 20 55 100 k 40 P30 to P37, VIN = VDD 5.0 MHz crystal oscillation operating mode 80 150 K VDD = 5.0 V 10 %Note 2 7.2 21.6 mA VDD = 3.0 V 10 %Note 3 0.9 2.7 mA VDD = 5.0 V 10 % 1.6 4.8 mA VDD = 3.0 V 10 % 650 1950 A VDD = 5.0 V 10 % 60 120 A VDD = 3.0 V 10 % 32 64 A VDD = 5.0 V 10 % 25 55 A VDD = 3.0 V 10 % 5 15 A VDD = 5.0 V 10 % 1 30 A VDD = 3.0 V 10 % 0.5 10 A XT1 = 0 V in STOP mode when VDD = 5.0 V 10 % not connecting to feedback resistor VDD = 3.0 V 10 % 0.1 30 A 0.05 10 A 5.0 MHz crystal oscillation HALT mode 32.768 kHz crystal oscillation operating modeNote 4 32.768 kHz crystal oscillation HALT modeNote 4 XT1 = 0 V in STOP mode when connecting to feedback resistor Notes 1. This current excludes the AVREF current, port current, and current which flows in the on-chip pull-down resistor (mask option). 2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H) 3. When operating at low-speed mode (when the PCC is set to 04H) 4. When main system clock stopped. 46 PD780204, 780205, 780206, 780208 AC CHARACTERISTICS (1) Basic Operation (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) Parameter Cycle time (minimum instruction execution time) Symbol TCY Conditions Operated with main MIN. VDD = 4.5 to 5.5 V system clock Operated with subsystem clock TI1, TI2 input frequency fTI TI1, TI2 input high, low-level width fTIH MAX. Unit 0.4 32 s 0.8 32 s 125 s 0 2 MHz 0 138 kHz 40Note 1 VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V TYP. 122 250 ns fTIL 3.6 s 8/fsamNote 2 s 10 s 10 s Interrupt input high, low-level width fINTH INTP0 fINTL INTP1 to INTP3 RESET low-level width tRSL Notes 1. Value when external clock input is used as subsystem clock. When crystal is used, the value becomes 114 s. 2. Selection of fsam = fx/2N+1, fx/64, fx/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of sampling clock select register (SCS). TCY vs. VDD (with main system clock operated) 60 30 Operation guarantee range Cycle time TCY [ s] 10 2.0 1.0 0.5 0.4 0 1 2 3 4 5 6 Power supply voltage VDD [V] 47 PD780204, 780205, 780206, 780208 (2) Serial Interface (TA = -40 to +85 C, VDD = 2.7 to 5.5 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0: Internal clock output) Parameter SCK0 cycle time Symbol tKCY1 SCK0 high, low-level width tKH1 tKL1 SI0 setup time (to SCK0) tSIK1 SI0 hold time (from SCK0) tKSI1 SCK0 SO0 output delay time tKSO1 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 MIN. TYP. MAX. Unit 800 ns 1600 ns tKCY1/2 - 50 ns tKCY1/2 - 100 ns 100 ns 150 ns 400 ns C = 100 pFNote 300 ns MAX. Unit Note C is a load capacitance of the SCK0 or SO0 output line. (ii) 3-wire serial I/O mode (SCK0: External clock input) Parameter SCK0 cycle time Symbol tKCY2 SCK0 high, low-level width tKH2 tKL2 SI0 setup time (to SCK0) tSIK2 SI0 hold time (from SCK0) tKSI2 SCK0 SO0 output delay time tKSO2 SCK0 rise, fall time tR2 tF2 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V C = 100 pFNote Note C is a load capacitance of the SO0 output line. 48 MIN. TYP. 800 ns 1600 ns tKCY2/2 - 50 ns tKCY2/2 - 100 ns 100 ns 150 ns 400 ns 300 ns 160 ns PD780204, 780205, 780206, 780208 (iii) SBI mode (SCK0: Internal clock output) Parameter SCK0 cycle time SCK0 high, low-level width Symbol tKCY3 tKH3 Conditions MIN. VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL3 VDD = 4.5 to 5.5 V TYP. MAX. Unit 800 ns 3200 ns tKCY3/2 - 50 ns tKCY3/2 - 150 ns 100 ns 300 ns tKCY3/2 ns SB0, SB1 setup time (to SCK0) tSIK3 SB0, SB1 hold time (from SCK0) tKSI3 SCK0 SB0, SB1 output delay time tKSO3 SCK0SB0, SB1 tKSB tKCY3 ns SB0, SB1SCK0 tSBK tKCY3 ns SB0, SB1 high-level tSBH tKCY3 ns tSBL tKCY3 ns R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V 0 250 ns 0 1000 ns width SB0, SB1 low-level width Note R is a load resistance and C is a load capacitance of the SCK0, SB0, or SB1 output line. (iv) SBI mode (SCK0: External clock input) Parameter SCK0 cycle time Symbol tKCY4 SCK0 high, low-level width tKH4 tKL4 SB0, SB1 setup time tSIK4 Conditions MIN. VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V (to SCK0) SB0, SB1 hold time tKSI4 TYP. MAX. Unit 800 ns 3200 ns 400 ns 1600 ns 100 ns 300 ns tKCY4/2 ns (from SCK0) R = 1 k, C = 100 pFNote SCK0 SB0, SB1 output delay time tKSO4 VDD = 4.5 to 5.5 V 0 250 ns 0 1000 ns SCK0SB0, SB1 tKSB tKCY4 ns SB0, SB1SCK0 tSBK tKCY4 ns SB0, SB1 high-level width tSBH tKCY4 ns SB0, SB1 low-level width tSBL tKCY4 ns SCK0 rise, fall time tR4 tF4 160 ns Note R is a load resistance and C is a load capacitance of the SB0 or SB1 output line. 49 PD780204, 780205, 780206, 780208 (v) 2-wire serial I/O mode (SCK0: Internal clock output) Parameter Symbol SCK0 cycle time tKCY5 SCK0 high-level width tKH5 SCK0 low-level width tKL5 SB0, SB1 setup time Conditions R = 1 k, C = 100 MIN. pFNote VDD = 4.5 to 5.5 V tSIK5 VDD = 4.5 to 5.5 V (to SCK0) TYP. MAX. Unit 1600 ns tKCY5/2 - 160 ns tKCY5/2 - 50 ns tKCY5/2 - 100 ns 300 ns 350 ns ns SB0, SB1 hold time (from SCK0) tKSI5 600 SCK0SB0, SB1 output delay time tKSO5 0 300 ns MAX. Unit Note R is a load resistance and C is a load capacitance of the SCK0, SB0, or SB1 output line. (vi) 2-wire serial I/O mode (SCK0: External clock input) Parameter Symbol Conditions MIN. TYP. SCK0 cycle time tKCY6 1600 ns SCK0 high-level width tKH6 650 ns SCK0 low-level width tKL6 800 ns SB0, SB1 setup time tSIK6 100 ns tKSI6 tKCY6/2 ns (to SCK0) SB0, SB1 hold time (from SCK0) SCK0SB0, SB1 output delay time tKSO6 SCK0 rise, fall time tR6 tF6 R = 1 k, C = 100 pFNote VDD = 4.5 to 5.5 V 0 300 ns 0 500 ns 160 ns Note R is a load resistance and C is a load capacitance of the SB0 or SB1 output line. 50 PD780204, 780205, 780206, 780208 (b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1: Internal clock output) Parameter SCK1 cycle time SCK1 high, low-level width SI1 setup time (to SCK1) SI1 hold time (from SCK1) SCK1 SO1 output delay time Symbol tKCY7 tKH7 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKL7 tSIK7 VDD = 4.5 to 5.5 V tKSI7 tKSO7 C = 100 MIN. TYP. MAX. Unit 800 ns 1600 ns tKCY7/2 - 50 ns tKCY7/2 - 100 ns 100 ns 150 ns 400 ns pFNote 300 ns MAX. Unit Note C is a load capacitance of the SCK1 or SO1 output line. (ii) 3-wire serial I/O mode (SCK1: External clock input) Parameter SCK1 cycle time Symbol tKCY8 SCK1 high, low-level width tKL8 SI1 setup time (to SCK1) tSIK8 SI1 hold time (from SCK1) tKH8 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKSI8 SCK1 SO1 output delay time tKSO8 SCK1 rise, fall time tR8 tF8 C = 100 pFNote MIN. TYP. 800 ns 1600 ns tKCY8/2-50 ns tKCY8/2-100 ns 100 ns 150 ns 400 ns 300 ns 160 ns Note C is a load capacitance of the SO1 output line. 51 PD780204, 780205, 780206, 780208 (iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1: Internal clock output) Parameter SCK1 cycle time Symbol tKCY9 SCK1 high, low-level width tKL9 SI1 setup time (to SCK1) tSIK9 SI1 hold time (from SCK1) tKH9 Conditions VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V VDD = 4.5 to 5.5 V tKSI9 SCK1 SO1 output delay time tKSO9 SCK1 STB tSBD Strobe signal high-level width C = 100 MIN. TYP. MAX. Unit 800 ns 1600 ns tKCY9/2 - 50 ns tKCY9/2 - 100 ns 100 ns 150 ns 400 ns pFNote 300 ns tKCY9/2 - 100 tKCY9/2 + 100 ns tSBW tKCY9 - 30 tKCY9 + 30 ns Busy signal setup time (to busy signal detection timing) tBYS 100 ns Busy signal hold time (from busy signal tBYH 100 ns 150 ns VDD = 4.5 to 5.5 V detection timing Busy inactibe SCK1 tSPS 2tKCY9 ns Note C is a load capacitance of the SCK1 or SO1 output line. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1: External clock input) Parameter SCK1 cycle time Symbol TYP. MAX. Unit ns 1600 ns 400 ns tKL10 800 ns SI1 setup time (to SCK1) tSIK10 100 ns SI1 hold time (from SCK1) tKSI10 400 ns SCK1 SO1 output delay time tKSO10 SCK1 rise, fall time tR10 tF10 tKH10 VDD = 4.5 to 5.5 V MIN. 800 SCK1 high, low-level width tKCY10 Conditions VDD = 4.5 to 5.5 V C = 100 pFNote Note C is a load capacitance of the SO1 output line. 52 300 ns 160 ns PD780204, 780205, 780206, 780208 AC TIMING TEST POINT (EXCLUDING X1, XT1 INPUT) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD CLOCK TIMING 1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.) X1 Input 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 Input TI TIMING 1/fTI tTIL tTIH TI0 - TI2 53 PD780204, 780205, 780206, 780208 SERIAL TRANSFER TIMING 3-wire serial I/O mode: IDD vs V DD (fx = 5.0 MHz, fxx = MHz tKCY1.2, 7, 8 tKL1.2, 7, 8 tKH1.2, 7, 8 tR2, 8 tF2, 8 SCK0, SCK1 tSIK1.2, 7, 8 tKSI1.2, 7, 8 SI0, SI1 Input Data tKSO1.2, 7, 8 SO0, SO1 Output Data SBI mode (bus release signal transfer): tKCY3.4 tKL3.4 tKH3.4 tR4 tF4 SCK0 tKSB tSBL tSBH tSBK tSIK3.4 SB0, SB1 tKSO3.4 SBI mode (command signal transfer): tKCY3.4 tKL3.4 tKH3.4 SCK0 tKSB tSBK tSIK3.4 SB0, SB1 tKSO3.4 54 tKSI3.4 tKSI3.4 PD780204, 780205, 780206, 780208 2-wire serial I/O mode: tKCY5, 6 tKL5, 6 tR6 tKH5, 6 tF6 SCK0 tSIK5, 6 tKSO5, 6 tKSI5, 6 SB0, SB1 3-wire serial I/O mode with automatic transmit/receive function: SO1 D2 SI1 D1 D2 D0 D1 D7 D0 D7 tKSI9, 10 tSIK9, 10 tKH9, 10 tKSO9, 10 tF10 SCK1 tR10 tKL9, 10 tKCY9, 10 tSBD tSBW STB 3-wire serial I/O mode with automatic transmit/receive function (Busy processing): SCK1 7 8 Note 9 Note Note 10 tBYS 10+n tBYH 1 tSPS BUSY (Active high) Note Though it does not become low level actually, here it is described as it does due to the timing rule. 55 PD780204, 780205, 780206, 780208 A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V) Parameter Symbol Conditions Resolution Total error MIN. TYP. MAX. Unit 8 8 8 bit 0.6 % 200 s Note 1 Conversion time Sampling time Note 2 Note 3 tCONV 1 MHz fX 5.0 MHz 19.1 s tSAMP 12/fX Analog input voltage VIAN AVSS AVREF V Reference voltage AVREF 4.0 AVDD V AVREF resistor RAVREF 4 14 k Notes 1. Quantization error (1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value. 2. Set the A/D conversion time to 19.1 s or more. 3. Sampling time depends on the conversion time. DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C) Parameter Symbol Data retention supply voltage VDDDR Data retention supply current IDDDR Conditions MIN. TYP. 1.8 VDDDR = 2.0 V Subsystem clock stopped, 0.1 MAX. Unit 5.5 V 10 A Feedback resistor not connected Release signal set time tSREL Oscillation stabilization wait time tWAIT Note s 0 Release by RESET 217/fX ms Release by interrupt Note ms Selection of 212/fX, 214/fX to 217/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register (OSTS). Data retention timing (STOP mode release by RESET) Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT 56 PD780204, 780205, 780206, 780208 Data retention timing (standby release signal: STOP mode release by interrupt signal) HALT mode STOP mode Operating mode Data retention mode VDD tSREL VDDDR STOP instruction execution Standby release signal (interrupt request) tWAIT Interrupt input timing tINTL tINTH INTP0 - INTP2 tINTL INTP3 RESET input timing tRSL RESET 57 PD780204, 780205, 780206, 780208 11. CHARACTERISTIC CURVE (REFERENCE VALUE) (1) PD780204, 780205 IDD vs. VDD (Main system clock: 5.0 MHz) (TA = 25 C) 10.0 PCC = 00H 5.0 PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H, HALT (X1 oscillates, XT1 oscillates) 1.0 fX = 5.0 MHz fXT = 32.768 kHz Supply current IDD [mA] 0.5 0.1 PCC = B0H 0.05 HALT (X1 stops, XT1 oscillates) STOP (X1 stops, XT1 oscillates) 0.01 0.005 0.001 0 2 3 4 5 Supply voltage VDD [V] 58 6 7 8 9 PD780204, 780205, 780206, 780208 IDD vs. fX (VDD = 5 V, TA = 25 C) 11 10 9 8 Supply current IDD [mA] 7 6 PCC = 00H 5 4 PCC = 01H 3 PCC = 02H 2 PCC = 03H PCC = 04H 1 0 0 1 2 3 4 5 6 Clock oscillation frequency fX [MHz] 59 PD780204, 780205, 780206, 780208 VOL vs. IOL (Port 1) (TA = 25 C) 30 VDD = 5 V V DD = 4 V Low-level output current IOL [mA] VDD = 6 V VDD = 3 V 20 10 0 0 0.5 1.0 1.5 Low-level output voltage VOL [V] VOL vs. IOL (Ports 0, 2, 3) (TA = 25 C) 30 VDD = 5 V V DD = 4 V Low-level output current IOL [mA] VDD = 6 V VDD = 3 V 20 10 0 0 0.5 1.0 Low-level output voltage VOL [V] 60 1.5 PD780204, 780205, 780206, 780208 VOL vs. IOL (Port 7) (TA = 25 C) VDD = 5 V V DD = 4 V 30 VDD = 6 V Low-level output current IOL [mA] VDD = 3 V 20 10 0 0 0.5 1.0 1.5 Low-level output voltage VOL [V] 61 PD780204, 780205, 780206, 780208 VDD - VOH vs. IOH (Port 0 - Port 3) High-level output current IOH [mA] (TA = 25 C) -10 VDD = 5 V VDD = 4 V VDD = 6 V VDD = 3 V -5 0 0 0.5 1.0 1.5 High-level output voltage VDD - VOH [V] VDD - VOH vs. IOH (Port 8 - Port 12) (TA = 25 C) VDD = 5 V -30 High-level output current IOH [mA] VDD = 6 V VDD = 4 V -20 VDD = 3 V -10 0 0 1.0 2.0 High-level output voltage VDD - VOH [V] 62 3.0 PD780204, 780205, 780206, 780208 (2) PD780206, 780208 IDD vs. VDD (Main system clock: 5.0 MHz) (TA = 25 C) 10.0 PCC = 00H 5.0 PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H, HALT (X1 oscillates, XT1 oscillates) 1.0 fX = 5.0 MHz fXT = 32.768 kHz Supply current IDD [mA] 0.5 0.1 PCC = B0H 0.05 0.01 0.005 0.001 0 2 3 4 5 6 7 8 9 Supply voltage VDD [V] 63 PD780204, 780205, 780206, 780208 IDD vs. fX (VDD = 5 V, TA = 25 C) 11 10 9 8 Supply current IDD [mA] 7 6 PCC = 00H 5 4 PCC = 01H 3 PCC = 02H 2 PCC = 03H PCC = 04H 1 0 0 1 2 3 4 Clock oscillation frequency fX [MHz] 64 5 6 PD780204, 780205, 780206, 780208 VOL vs. IOL (Port 1) (TA = 25 C) 30 VDD = 5 VV DD = 4 V Low-level output current IOL [mA] VDD = 6 V VDD = 3 V 20 10 0 0 0.5 1.0 1.5 Low-level output voltage VOL [V] VOL vs. IOL (Ports 0, 2, 3) (TA = 25 C) 30 VDD = 5 V VDD = 4 V Low-level output current IOL [mA] VDD = 6 V VDD = 3 V 20 10 0 0 0.5 1.0 1.5 Low-level output voltage VOL [V] 65 PD780204, 780205, 780206, 780208 VOL vs. IOL (Port 7) (TA = 25 C) VDD = 5 V VDD = 4 V Low-level output current IOL [mA] 30 VDD = 6 V VDD = 3 V 20 10 0 0 0.5 1.0 Low-level output voltage VOL [V] 66 1.5 PD780204, 780205, 780206, 780208 VDD - VOH vs. IOH (Port 0 - Port 3) High-level output current IOH [mA] (TA = 25 C) -10 VDD = 5 V VDD = 4 V VDD = 6 V VDD = 3 V -5 0 0 0.5 1.0 1.5 High-level output voltage VDD - VOH [V] VDD - VOH vs. IOH (Port 8 - Port 12) (TA = 25 C) High-level output current IOH [mA] -30 VDD = 5 V VDD = 4 V VDD = 6 V VDD = 3 V -20 -10 0 0 1.0 2.0 3.0 High-level output voltage VDD - VOH [V] 67 PD780204, 780205, 780206, 780208 12. PACKAGE DRAWING 100 PIN PLASTIC QFP (14 x 20) A B Q F G H I M 55 31 30 S 100 1 detail of lead end D 51 50 C 80 81 J M P K N L P100GF-65-3BA1-2 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 23.6 0.4 0.929 0.016 B 20.0 0.2 0.795+0.009 -0.008 C 14.0 0.2 0.551+0.009 -0.008 D 17.6 0.4 0.693 0.016 F 0.8 0.031 G 0.6 0.024 H 0.30 0.10 0.012+0.004 -0.005 I 0.15 0.006 J 0.65 (T.P.) 0.026 (T.P.) K 1.8 0.2 0.071+0.008 -0.009 L 0.8 0.2 0.031+0.009 -0.008 M 0.15+0.10 -0.05 0.006+0.004 -0.003 N 0.10 0.004 P 2.7 0.106 Q 0.1 0.1 0.004 0.004 S 3.0 MAX. 0.119 MAX. Remark The dimensions and materials of the ES model are the same as the mass-produced model. 68 PD780204, 780205, 780206, 780208 13. RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD780204, 780205, 780206, and 780208. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. Table 13-1. Soldering Conditions for Surface-Mount Type PD780204GF-xxx-3BA: PD780205GF-xxx-3BA: PD780206GF-xxx-3BA: PD780208GF-xxx-3BA: Soldering Method 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic QFP (14 x 20 mm) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Thrice max. IR35-00-3 VPS Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Thrice max. VP15-00-3 Wave soldering Solder bath temperature: 260 C max. Duration: 10 sec. max. Number of times: Once Preliminary heat temperature: 120 C max. (Package surface temperature) WS60-00-1 Partial heating Pin temperature: 300 C max., Duration: 3 sec. max. (per device side) -- Caution Using more than one soldering method should be avoided (except in the case of partial heating). 69 PD780204, 780205, 780206, 780208 APPENDIX A. DEVELOPMENT TOOLS The following tools are available for development of systems using the PD780204, 780205, 780206, and 780208: Language Processing Software RA78K/0Note 1, 2, 3, 4 Assembler package common to 78K/0 series Note 1, 2, 3, 4 C compiler package common to 78K/0 series CC78K/0 DF780208Note 1, 2, 3, 4 CC78K/0-L Device file for PD780208 subseries Note 1, 2, 3, 4 C compiler library source file common to 78K/0 series PROM Writing Tools PG-1500 PROM programmer PA-78P0208GF Programmer adapter connectd to PG-1500 PA-78P0208KL-T PG-1500 ControllerNote 1, 2 Control program for PG-1500 Debugging Tools IE-78000-R In-circuit emulator common to 78K/0 series IE-78000-R-A In-circuit emulator common to 78K/0 series (for integrated debugger) IE-78000-R-BK Break board common to 78K/0 series IE-780208-R-EM Emulation board for evaluating PD780208 subseries EP-78064GF-R Emulation probe common to PD78064 subseries EV-9200GF-100 Socket mounted to target system created for 100-pin plastic QFP (GF-3BA type) Note 5, 6, 7 SM78K0 System simulator common to 78K/0 series Note 4, 5, 6, 7 ID78K0 Integrated debugger for IE-78000-R-A Note 1, 2 SD78K/0 Screen debugger for IE-78000-R Note 1, 2, 4, 5, 6, 7 Device file for PD780208 subseries DF780208 Real-time OS Note 1, 2, 3, 4 Real-time OS for 78K/0 series Note 1, 2, 3, 4 OS for 78K/0 series RX78K/0 MX78K0 TM Notes 1. PC-9800 series (MS-DOS ) based TM 2. IBM PC/AT and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 series 300 TM TM 4. HP9000 series 700 TM (HP-UX ) based TM (HP-UX) based, SPARCstation TM (Sun OS ) based, EWS4800 series (EWS-UX/V) based TM 5. PC-9800 series (MS-DOS + Windows ) based 6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF780208. 70 PD780204, 780205, 780206, 780208 Fuzzy Inference Development Support System FE9000Note 1/FE9200Note 3 Fuzzy knowledge data creation tool FT9080Note 1/FT9085Note 2 Translator FI78K0Note 1, 2 Fuzzy inference module FD78K0Note 1, 2 Fuzzy inference debugger Notes 1. PC-9800 series (MS-DOS) based 2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based 3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based Remark Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development tools. 71 PD780204, 780205, 780206, 780208 APPENDIX B. RELATED DOCUMENTS Documents Related to Devices Document No. Document Name Japanese English PD780208 subseries user's manual U11302J U11302E PD780204, 780205, 780206, 780208 data sheet U10436J This document PD78P0208 data sheet U11295J U11295E PD780208 subseries special function register list U10997J -- 78K/0 series user's manual - instruction IEU-849 IEU-1372 78K/0 series instruction list U10903J -- 78K/0 series instruction set U10904J -- 78K/0 series application note - Basic (II) U10121J U10121E Caution The documents listed above are subject to change without notice. Be sure to use the latest documents for designing your system. 72 PD780204, 780205, 780206, 780208 Development Tool Documents (User's Manual) Document No. Document Name Japanese English Operation EEU-809 EEU-1399 Language EEU-815 EEU-1404 Operation U11802J U11802E Assembly language U11801J U11801E Structured assembly language U11789J U11789E EEU-817 EEU-1402 Operation EEU-656 EEU-1280 Language EEU-655 EEU-1284 Operation U11517J U11517E Language U11518J U11518E EEU-777 -- EEA-618 EEA-1208 PG-1500 PROM programmer EEU-651 EEU-1335 PG-1500 controller PC-9800 series (MS-DOS) base EEU-704 EEU-1291 PG-1500 controller IBM PC series (PC DOS) base EEU-5008 U10540E IE-78000-R EEU-810 U11376E IE-78000-R-A U10057J U10057E IE-78000-R-BK EEU-867 EEU-1427 IE-780208-R-EM EEU-977 EEU-1501 EP-78064 EEU-934 EEU-1469 RA78K series assembler package RA78K0 assembler package RA78K series structured assembler preprocessor CC78K series C compiler CC78K0 C compiler CC78K series library source file CC78K/0 C compiler application note Programming know-how SM78K0 system simulator Reference U10181J U10181E SM78K series system simulator External parts user-open interface specification U10092J U10092E SD78K/0 screen debugger PC-9800 series (MS-DOS) base Introduction EEU-852 U10539E Reference U10952J -- EEU-5024 EEU-1414 Reference U11279J U11279E ID78K0 integrated debugger EWS based Reference U11151J -- ID78K0 integrated debugger PC based Reference U11539J U11539E ID78K0 integrated debugger Windows based Guide U11649J U11649E SD78K/0 screen debugger IBM PC/AT (PC DOS) base Caution Introduction The documents listed above are subject to change without notice. Be sure to use the latest documents for designing your system. 73 PD780204, 780205, 780206, 780208 Documents Related to Embedded Software (User's Manual) Document No. Document Name Japanese English Fundamental U11537J -- Installation U11536J -- Technical U11538J -- EEU-5010 -- Fuzzy knowledge data creation tool EEU-829 EEU-1438 78K/0, 78K/II, 87AD series fuzzy inference development suppport system translator EEU-862 EEU-1444 78K/0 series fuzzy inference development support system - fuzzy inference module EEU-858 EEU-1441 78K/0 series fuzzy inference development support system - fuzzy inference debugger EEU-921 EEU-1458 78K/0 series real-time OS 78K/0 series OS MX78K0 Fundamental Other Related Documents Document No. Document Name Japanese IC package manual English C10943X Semiconductor device mounting technology manual C10535J C10535E Quality grade on NEC semiconductor devices C11531J C11531E NEC semiconductor device reliability/quality control system C10983J C10983E Static electricity discharge (ESD) test MEM-539 -- Semiconductor device quality guarantee guide C11893J MEI-1202 Product guide related to microcomputer - other manufacturers U11416J -- Caution The documents listed above are subject to change without notice. Be sure to use the latest documents for designing your system. 74 PD780204, 780205, 780206, 780208 [MEMO] 75 PD780204, 780205, 780206, 780208 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 76 PD780204, 780205, 780206, 780208 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 77 PD780204, 780205,780206, 780208 The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. FIP and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation. HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 78