©
1994
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD780204, 780205, 780206, 780208
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
µ
PD780204, 780205, 780206, and 780208 microcontrollers are the products of
µ
PD780208 subseries in
78K/0 series, and incorporate many hardware peripherals such as an FIPTM controller/driver, 8-bit resolution A/D
converter, timer, serial interface, and interrupt controller.
In addition to these standard mask ROM models, one-time PROM models that can operate in the same voltage range,
EPROM models
µ
PD78P0208, and various development tools are available.
The functions of these microcontrollers are described in detail in the following User’s Manual. Be sure to
read this manual when you design a system using any of these microcontrollers.
µ
PD780208 Subseries User’s Manual: U11302E
78K/0 Series User’s Manual - Instruction: IEU-1372
FEATURES
• High-capacity ROM and RAM
Item Program Memory Data Memory Package
Product Name
(ROM)
Internal high-speed RAM Buffer RAM FIP display RAM Internal expansion RAM
µ
PD780204 32 K bytes 1024 bytes 64 bytes 80 bytes Not provided
100-pin plastic QFP
µ
PD780205 40 K bytes (14 × 20 mm)
µ
PD780206 48 K bytes 1024 bytes
µ
PD780208 60 K bytes
• Wide range of instruction execution time • 8-bit resolution A/D converter: 8 channels
- from high-speed (0.4
µ
s) to ultra low-speed (122
µ
s) • Serial interface: 2 channels
• I/O ports: 74 • Timer: 5 channels
• FIP controller/driver: total display outputs: 53 • Power supply voltage: VDD = 2.7 to 5.5 V
APPLICATIONS
Minicomponent stereo, cassette deck, tuner, CD player, VCR.
ORDERING INFORMATION
Part Number Package
µ
PD780204GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µ
PD780205GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µ
PD780206GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
µ
PD780208GF-×××-3BA 100-pin plastic QFP (14 × 20 mm)
Remark “×××” indicates ROM code number.
Document No. U10436EJ2V0DS00 (2nd edition)
Date Published February 1997 N
Printed in Japan
The information in this document is subject to change without notice.
The mark shows major revised point.
µ
PD780204, 780205, 780206, 780208
2
78K/0 SERIES PRODUCT DEVELOPMENT
The following shows the 78K/0 Series products development. Subseries name are shown inside frames.
Control
FIP drive
100-pin
LCD drive
IEBus
TM
supported
42/44-pin
64-pin
64-pin
64-pin
80-pin
100-pin
80-pin
80-pin
100-pin
100-pin
80-pin
78K/0
Series
Basic subseries for driving FIP, Display output total: 34
Basic subseries for driving LCDs, On-chip UART
Y subseries products are compatible with I
2
C bus.
Products under
development
Products in
mass production
80-pin
100-pin
PD78054
µ
PD78014
µ
PD780001
µ
PD78002
µ
PD78054Y
µ
PD78014Y
µ
PD78002Y
µ
PD78083
µ
PD780208
µ
PD78044H
µ
PD78044F
µ
PD78064B
µ
PD78064
µ
PD78098
µ
PD78064Y
µ
An IEBus controller was added to the PD78054
µ
EMI-noise reduced version of the PD78078
µ
The I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53
µ
EMI-noise reduced version of the PD78064
µ
PD78058F
µ
PD78058FY
µ
PD780058Y
Note
µ
PD780058
µ
PD78070A
µ
PD78070AY
µ
PD78078
µ
PD78078Y
µ
80-pin
PD780308
µ
PD780308Y
µ
The SIO of the PD78064 was enhanced and ROM, RAM capacity increased
µ 
100-pin
LV
64-pin On-chip PWM output, LV digital code decoder, and Hsync counter
PD78P0914
µ
PD78075BY
µ
PD78075B
µ
100-pin
PD780018Y
Note
µ
PD780018
Note
µ
100-pin
PD780024Y
µ
PD780024
µ
64-pin PD780034Y
µ
PD780034
µ
64-pin
64-pin PD78014H
µ
64-pin PD78018F
µ
PD78018FY
µ
A timer was added to the PD78054 and external interface was enhanced
µ
ROM-less version of the PD78078
µ
EMI-noise reduced version of the PD78054
µ
UART and D/A converter were added to the PD78014 and I/O was enchanced
µ
A/D converter of the PD780024 was enchanced
µ
Serial I/O of the PD78018F was added and EMI-noise was reduced
µ
Serial I/O of the PD78054 was enhanced and EMI-noise was reduced
µ
EMI-noise reduced version of PD78018F
µ
Serial I/O of the PD78078 was enhanched and the function is limited
µ
Low-voltage (1.8 V) operation version of the PD78014, with larger 
selection of ROM and RAM capacities
µ
An A/D converter and 16-bit timer were added to the PD78002
µ
An A/D converter was added to the PD78002
µ
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
PD780924
µ
64-pin PD780964
µ
64-pin
Inverter control
PD780228
µ
100-pin
On-chip inverter control circuit and UART. EMI-noise was reduced.
A/D converter of the PD780924 was enhanced
µ 
The I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48
µ
N-ch open drain was added to the PD78044F, Display output total: 34
µ 
Note Under planning
3
µ
PD780204, 780205, 780206, 780208
The following lists the main functional differences between subseries products.
Function ROM Timer 8-bit 10-bit 8-bit Serial I/O VDD MIN. External
Subseries Name Capacity 8-bit 16-bit Watch WDT A/D A/D D/A Interface Value
Expansion
Control
µ
PD78075B 32 K - 40K 4ch 1ch 1ch 1ch 8ch – 2ch 3ch (UART : 1ch) 88 1.8 V
µ
PD78078 48 K - 60K
µ
PD78070A – 61 2.7 V
µ
PD780018 48 K - 60K – 2ch (time division 88
3-wire: 1ch)
µ
PD780058 24 K - 60 K 2ch 2ch 3ch (time division 68 1.8 V
UART: 1ch)
µ
PD78058F 48 K - 60 K 3ch (UART: 1ch) 69 2.7 V
µ
PD78054 16 K - 60 K 2.0 V
µ
PD780034 8 K - 32 K – 8ch – 3ch (UART: 1ch, time 51 1.8 V
µ
PD780024 8 ch – division 3-wire: 1ch)
µ
PD78014H 2ch 53
µ
PD78018F 8 K - 60 K
µ
PD78014 8 K - 32 K 2.7 V
µ
PD780001 8 K – – 1ch 39 –
µ
PD78002 8 K - 16 K 1ch – 53
µ
PD78083 – 8ch 1ch (UART: 1ch) 33 1.8 V –
Inverter
µ
PD780964 8 K - 32 K 3ch Note – 1ch – 8ch – 2c (UART: 2ch) 47 2.7 V
control
µ
PD780924 8ch –
FIP
µ
PD780208 32 K - 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – – 2 ch 74 2.7 V –
drive
µ
PD780228 48 K - 60 K 3ch – – 1ch 72 4.5 V
µ
PD78044H 32 K - 48 K 2ch 1ch 1ch 68 2.7 V
µ
PD78044F 16 K - 40 K 2ch
LCD
µ
PD780308 48 K - 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – – 3 ch (time division 57 1.8 V –
drive UART: 1ch)
µ
PD78064B 32 K 2 ch (UART : 1 ch) 2.0 V
µ
PD78064 16 K - 32 K
IEBus
µ
PD78098 32 K - 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART : 1 ch) 69 2.7 V
supported
LV
µ
PD78P0914 32 K 6 ch – – 1 ch 8 ch – – 2 ch 54 4.5 V
Note 10-bit timer: 1 channel
µ
PD780204, 780205, 780206, 780208
4
ROM
High-speed RAM
Buffer RAM
FIP display RAM
Expansion RAM
FUNCTIONAL OUTLINE
Internal
memory
Product Name
µ
PD780204
µ
PD780205
µ
PD780206
µ
PD780208
32 K bytes 40 K bytes 48 K bytes 60 K bytes
1024 bytes
64 bytes
80 bytes
Not provided 1024 bytes
General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Variable instruction execution time
w/main system 0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s (at 5.0 MHz)
clock
w/subsystem 122
µ
s (at 32.768 kHz)
clock
Instruction set • Multiplecation/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit operation (set, reset, test, Boolean algebra)
I/O ports (including those Total : 74 lines
multiplexed with FIP pins) • CMOS input : 2 lines
• CMOS I/O : 27 lines
• N-ch open-drain I/O : 5 lines
• P-ch open-drain I/O : 24 lines
• P-ch open-drain output : 16 lines
FIP controller/driver Total : 53 lines
• Segment : 9 to 40 lines
• Digit : 2 to 16 lines
A/D converter • 8-bit resolution × 8 channels
• Supply voltage : AVDD = 4.0 to 5.5 V
Serial interface • 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel
•
3-wire serial I/O mode (w/automatic transfer/receive function of up to 64 bytes)
:
1 channel
Timer • 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
Timer output 3 lines (one for 14-bit PWM output)
Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(main system clock: at 5.0 MHz)
32.768 kHz (subsystem clock: at 32.768 kHz)
Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz : (main system clock: at 5.0 MHz)
Instruction
cycle
Item
5
µ
PD780204, 780205, 780206, 780208
µ
PD780204
µ
PD780205
µ
PD780206
µ
PD780208
Product Name
Maskable Internal: 9, external: 4
Non-maskable Internal: 1
Software 1
Test input Internal: 1 line
Supply voltage VDD = 2.7 to 5.5 V
Package 100-pin plastic QFP (14 × 20 mm)
Item
Vectored
interrupt
sources
µ
PD780204, 780205, 780206, 780208
6
CONTENTS
1. PIN CONFIGURATION (Top View) ............................................................................................... 7
2. BLOCK DIAGRAM .......................................................................................................................... 9
3. PIN FUNCTIONS ............................................................................................................................. 10
3.1 PORT PINS............................................................................................................................................. 10
3.2 PINS OTHER THAN PORT PINS .......................................................................................................... 12
3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ................................................................. 14
4. MEMORY SPACE............................................................................................................................ 17
5. PERIPHERAL HARDWARE FUNCTIONS..................................................................................... 18
5.1 PORTS.................................................................................................................................................... 18
5.2 CLOCK GENERATOR CIRCUIT ........................................................................................................... 19
5.3 TIMER/EVENT COUNTER ..................................................................................................................... 19
5.4 CLOCK OUTPUT CONTROL CIRCUIT.................................................................................................. 22
5.5 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................................ 22
5.6 A/D CONVERTER .................................................................................................................................. 23
5.7 SERIAL INTERFACE ............................................................................................................................. 23
5.8 FIP CONTROLLER/DRIVER.................................................................................................................. 25
6. INTERRUPT FUNCTION AND TEST FUNCTION ....................................................................... 27
6.1 INTERRUPT FUNCTION........................................................................................................................ 27
6.2 TEST FUNCTION ................................................................................................................................... 30
7. STANDBY FUNCTION .................................................................................................................... 31
8. RESET FUNCTION.......................................................................................................................... 31
9. INSTRUCTION SET......................................................................................................................... 32
10. ELECTRICAL SPECIFICATIONS ................................................................................................... 35
11. CHARACTERISTIC CURVE (REFERENCE VALUE)................................................................... 58
12. PACKAGE DRAWING..................................................................................................................... 68
13. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 69
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 70
APPENDIX B. RELATED DOCUMENTS............................................................................................ 72
7
µ
PD780204, 780205, 780206, 780208
1. PIN CONFIGURATION (Top View)
100-Pin Plastic QFP (14 × 20 mm)
µ
PD780204GF - ××× - 3BA
µ
PD780205GF - ××× - 3BA
µ
PD780206GF - ××× - 3BA
µ
PD780208GF - ××× - 3BA
FIP0
FIP1
FIP2
FIP3
FIP4
FIP5
FIP6
FIP7
FIP8
FIP9
FIP10
FIP11
FIP12
P80/FIP13
P81/FIP14
P82/FIP15
P83/FIP16
P84/FIP17
P85/FIP18
P86/FIP19
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P87/FIP20
V
LOAD
P90/FIP21
P91/FIP22
P92/FIP23
P93/FIP24
P94/FIP25
P95/FIP26
P96/FIP27
P97/FIP28
P100/FIP29
P101/FIP30
P102/FIP31
P103/FIP32
P104/FIP33
P105/FIP34
P106/FIP35
P107/FIP36
P110/FIP37
P111/FIP38
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61 P112/FIP39
P113/FIP40
P114/FIP41
P115/FIP42
P116/FIP43
P117/FIP44
P120/FIP45
P121/FIP46
60
59
58
57
56
55
54
53 P122/FIP47
P123/FIP48
52
51
V
DD
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
RESET
X2
X1
IC
XT2
P04/XT1
V
DD
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P23/STB
P22/SCK1
P21/SO1
P20/SI1
AV
SS
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P12/ANI2
P11/ANI1
P10/ANI0
AV
DD
AV
REF
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0/TI0
V
SS
P74
P73
P72
P71
P70
V
DD
P127/FIP52
P126/FIP51
P125/FIP50
P124/FIP49
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Cautions 1. Connect the IC (Internally Connected) pins directly to the VSS.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
µ
PD780204, 780205, 780206, 780208
8
P00-P04 : Port0 SCK0, SCK1 : Serial Clock
P10-P17 : Port1 PCL : Programmable Clock
P20-P27 : Port2 BUZ : Buzzer Clock
P30-P37 : Port3 STB : Strobe
P70-P74 : Port7 BUSY : Busy
P80-P87 : Port8 FIP0-FIP52 : Fluorescent Indicator Panel
P90-P97 : Port9 VLOAD : Negative Power Supply
P100-P107 : Port10 X1, X2 : Crystal (Main System Clock)
P110-P117 : Port11 XT1, XT2 : Crystal (Subsystem Clock)
P120-P127 : Port12 RESET : Reset
INTP0-INTP3 : Interrupt from Peripherals ANI0-ANI7 : Analog Input
TI0-TI2 : Timer Input AVDD : Analog Power Supply
TO0-TO2 : Timer Output AVSS : Analog Ground
SB0, SB1 : Serial Bus AVREF : Analog Reference Voltage
SI0, SI1 : Serial Input VDD : Power Supply
SO0, SO1 : Serial Output VSS : Ground
IC : Internally Connected
9
µ
PD780204, 780205, 780206, 780208
2. BLOCK DIAGRAM
PORT 0 P01 - P03
PORT 1 P10 - P17
PORT 2 P20 - P27
PORT 3 P30 - P37
PORT 7 P70 - P74
PORT 8 P80 - P87
PORT 9 P90 - P97
PORT 10 P100 - P107
PORT 11 P110 - P117
PORT 12 P120 - P127
FIP
CONTROLLER/
DRIVER FIP0 - FIP52
78K/0
CPU 
CORE ROM
RAM
8-bit TIMER/
EVENT COUNTER 1
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
16-bit TIMER/
EVENT COUNTER
V
LOAD
SYSTEM
CONTROL
RESET
X1
X2
XT1/P04
XT2
WATCH TIMER
SERIAL 
INTERFACE 0
SERIAL
INTERFACE 1
A/D CONVERTER
INTERRUPT
CONTROL
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
V
DD
V
SS
IC
P00
P04
TO0/P30
TI0/INTP0/P00
TO1/P31
TI1/P33
TO2/P32
TI2/P34
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
ANI0/P10 -
ANI7/P17
INTP0/TI0/P00 -
INTP3/P03
AV
DD
AV
SS
AV
REF
BUZ/P36
PCL/P35
Remark The capacities of the internal ROM and RAM differ depending on the product.
µ
PD780204, 780205, 780206, 780208
10
Sharde by:
INTP0/TI0
INTP1
INTP2
INTP3
XT1
ANI0-ANI7
SI1
SO1
SCK1
STB
BUSY
SI0/SB0
SO0/SB1
SCK0
TO0
TO1
TO2
TI1
TI2
PCL
BUZ
—
I/O
I/O
Port 2
8-bit I/O port
Can be specified for input or output in 1-bit units.
When used as an input port pin, an on-chip pull-up resistor can be
used through software.
Port 0
5-bit I/O port
On Reset
Input
Input
Input
Input
Input
Input
Input only
Can be specified for input or output in 1-
bit units. When used as an input port pin,
an on-chip pull-up resistor can be used
through software.
Input only
Port 1
8-bit I/O port
Can be specified for input or output in 1-bit units.
When used as an input port pin, an on-chip pull-up resistor can be
used through software.Note 2
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
I/O
Input
I/O
Input
I/O
Function
Notes 1. When the P04/XT1 pins is used as an input port pin, bit 6 (FRC) of the porcessor clock control register (PCC)
must be set to 1. (At this time, do not use the feedback resistor of the subsystem clock oscillator circuit.)
2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be sure
to place the port 1 in the input mode. In this case, the on-chip pull-up resistors are automaticaly unused.
Port 3
8-bit I/O port
Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
When used as an input port pin, an on-chip pull-up resistor can be
used through software.
A pull-down resistor can be connected in 1-bit units by mask
option.
Pin Name
P00
P01
P02
P03
P04Note 1
P10-P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
11
µ
PD780204, 780205, 780206, 780208
3.1 PORT PINS (2/2)
Pin Name I/O Function
Port 7
5-bit N-ch open-drain I/O port
P70-P74 I/O Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
A pull-up resistor can be connected in 1-bit units by mask option.
Port 8
8-bit P-ch open-drain high-voltage output port
P80-P87 Output Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by mask
option (whether VLOAD or VSS is connected can be specified in
4-bit units).
Port 9
8-bit P-ch open-drain high-voltage output port
P90-P97 Output Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by mask
option (whether VLOAD or VSS is connected can be specified in 4-bit
units).
Port 10
8-bit P-ch open-drain high-voltage output port
P100-P107 I/O Can be specified for input or output in bit units.
Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by mask option
(whether VLOAD or VSS is connected can be specified in 4-bit units).
Port 11
8-bit P-ch open-drain high-voltage I/O port
P110-P117 I/O Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
A pull-down resistor can be conneced in 1-bit units by mask option
(whether VLOAD or VSS is connected can be specified in 4-bit units).
Port12
8-bit P-ch open-drain high-voltage I/O port.
P120-P127 I/O Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
A pul-down resistor can be connected in 1-bit units by mask option
(whether VLOAD or VSS is connected can be specified in 4-bit units).
On Reset Shared by:
Input —
Output FIP13-FIP20
Output FIP21-FIP28
Input FIP29-FIP36
Input FIP37-FIP44
Input FIP45-FIP52
µ
PD780204, 780205, 780206, 780208
12
3.2 PINS OTHER THAN PORT PINS (1/2)
Pin Name
INTP0
INTP1
INTP2
INTP3
SI0
SI1
SO0
SO1
SB0
SB1
SCK0
SCK1
STB
BUSY
TI0
TI1
TI2
TO0
TO1
TO2
PCL
BUZ
FIP0-FIP12
FIP13-FIP20
FIP21-FIP28
FIP29-FIP36
FIP37-FIP44
FIP45-FIP52
VLOAD
I/O
Input
Input
Output
I/O
I/O
Output
Input
Input
Output
Output
Output
Output
Output
–
Function
Valid edge (rising, falling, or both rising and falling edges) can be
specified.
External interrupt request input
Falling edge-active external interrupt input
Serial data input lines of serial interface
Serial data output lines of serial interface
Serial data I/O lines of serial interface
Serial clock I/O lines of serial interface
Automatic transfer/receive strobe output line of serial interface
Automatic transfer/receive busy input line of serial interface
External count clock input to 16-bit timer (TM0)
External count clock input to 8-bit timer (TM1)
External count clock input to 8-bit timer (TM2)
16-bit timer (TM0) output (multiplexed with 14-bit PWM output)
8-bit timer (TM1) output
8-bit timer (TM2) output
Clock output (for trimming main system clock and subsystem
clock)
Buzzer output
High-voltage, high-current output for FIP controller/driver display
output
A pull down register can be connected by mask option.
High-voltage, high-current output for FIP controller/driver display
output
Connects pull-down resistor to FIP controller/driver
On Reset
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
–
Shared by:
P00/TI0
P01
P02
P03
P25/SB0
P20
P26/SB1
P21
P25/SI0
P26/SO0
P27
P22
P23
P24
P00/INTP0
P33
P34
P30
P31
P32
P35
P36
–
P80-P87
P90-P97
P100-P107
P110-P117
P120-P127
–
13
µ
PD780204, 780205, 780206, 780208
3.2 PINS OTHER THAN PORT PINS (2/2)
Pin Name I/O Function On Reset Shared by:
ANI0-ANI7 Input A/D converter analog input lines Input P10-P17
AVREF Input A/D converter reference voltage input line — —
AVDD — Analog power supply to A/D converter. Connected to VDD pin. — —
AVSS — A/D converter ground line. Connected to VSS pin. — —
RESET Input System reset input — —
X1 Input ——
X2 — ——
XT1 Input Input P04
XT2 — ——
VDD — Positive power supply — —
VSS — Ground potential — —
IC — Internal connection. Connected directly to VSS pin. — —
Connect crystal for main system clock oscillation.
Connect crystal for subsystem clock oscillation.
µ
PD780204, 780205, 780206, 780208
14
3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins.
For the configuration of the I/O circuit of each type, refer to Figure 3-1.
Table 3-1. I/O Circuit Type
Pin Name
P00/INTP0/TI0
P01/INTP1
P02/INTP2
P03/INTP3
P04/XT1
P10/ANI0-P17/ANI7
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
P70-P74
FIP0-FIP12
P80/FIP13-P87/FIP20
P90/FIP21-P97/FIP28
P100/FIP29-P107/FIP36
P110/FIP37-P117/FIP44
P120/FIP45-P127/FIP52
RESET
XT2
AVREF
AVDD
AVSS
VLOAD
IC
I/O Circuit Type
2
8-A
16
11
8-A
5-A
8-A
5-A
8-A
10-A
5-C
8-B
5-C
13-B
14-A
15-C
2
16
—
I/O
Input
I/O
Input
I/O
Output
I/O
Input
—
Recommended Connections When Unused
Connect to VSS
Independently connect to Vss through resistor
Connect to VDD or VSS
Independently connect to VDD or VSS through resistor
Open
Independently connect to VDD or VSS through resistor
—
Open
Connect to VSS
Connect to VDD
Connect to VSS
Connect directly to VSS
15
µ
PD780204, 780205, 780206, 780208
Figure 3-1. Pin I/O Circuits (1/2)
Type 5-C
Type 2 Type 8-A
Type 5-A Type 8-B
IN
Schmitt trigger input with hysteresis characteristics
V
DD
V
DD
pullup
enable
data
output
disable
P-ch
IN/OUT
N-ch
P-ch
V
DD
V
DD
pullup
enable
data
output
disable
P-ch
N-ch
IN/OUT
(Mask
Option)
P-ch
Type 10-A
P-ch
N-ch
V
DD
pullup
enable
data
IN/OUT
open drain
output disable
V
DD
P-ch
V
DD
V
DD
P-ch
P-ch
N-ch
IN/OUT
pullup
enable
data
output
disable
input
enable
V
DD
P-ch
N-ch
P-ch
V
DD
IN/OUT
(Mask
Option)
pullup
enable
data
output
disable
input
enable
µ
PD780204, 780205, 780206, 780208
16
Type 11
Type 14-A
Type 15-C
Type 13-B
V
DD
IN/OUT
(Threshold voltage)
V
REF
pullup
enable
data
output
disable
V
DD
P-ch
P-ch
N-ch
P-ch
N-ch
input enable
V
DD
+
–
IN/OUT
Comparator
N-ch
(Mask
Option)
data
output disable
Medium-voltage input buffer
V
DD
P-ch P-ch
N-ch
data OUT
(Mask
Option)
(Mask
Option)
V
DD
V
LOAD
V
DD
V
DD
data
N-ch
P-ch P-ch
IN/OUT
V
LOAD
(Mask
Option)
(Mask
Option)
Type 16
P-ch
feedback
cut-off
XT1 XT2
V
DD
P-ch
RD
V
P-ch
RD
RD N-ch
Figure 3-1. Pin I/O Circuits (2/2)
µ
PD780204, 780205, 780206, 780208
17
4. MEMORY SPACE
Figure 4-1 shows the memory maps for
µ
PD780204, 780205, 780206, and 780208.
Figure 4-1. Memory Map
Notes 1.
µ
PD780206 and 780208 only.
2. The internal ROM capacities vary depending on the product. (Refer to the table below.)
Product Name Internal ROM Last Address
nnnnH
µ
PD780204 7FFFH
µ
PD780205 9FFFH
µ
PD780206 BFFFH
µ
PD780208 EFFFH
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FAC0H
FABFH
FA30H
FA2FH
0000H
nnnnH
1000H
0FFFH
0800H
07FFH
0080H
007FH
0040H
003FH
0000H
Special function
register (SFR)
256 × 8 bits
General-purpose
register
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
Buffer RAM
64 × 8 bits
FIP display RAM
80 × 8 bits
Internal ROM
Note 2
CALLF entry area
Program area
CALLT entry area
Inhibited
Program area
Vector table area
Data
memory
space
Program
memory
space
FB00H
FAFFH
FA80H
FA7FH
nnnnH+1
nnnnH
Inhibited
Internal expansion
RAM
1024 × 8 bits
Inhibited
Inhibited
nnnnH+1
F800H
F7FFH
F400H
F3FFH
FA2FH 












Note 1
µ
PD780204, 780205, 780206, 780208
18
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
I/O ports are classified into the following 5 kinds:
• CMOS input (P00, P04) : 2
• CMOS input/output (P01 - P03, ports 1-3) : 27
• N-ch open-drain input/output (port 7) : 5
• P-ch open-drain output (ports 8, 9) : 16
• P-ch open-drain input/output (ports 10 - 12) : 24
Total : 74
Table 5-1. Port Function
Name Pin Name Function
Input port
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units.
When used as input port, internal pull-up resistor can be connected through software.
Pull-down resistor can be connected in 1-bit units by mask option.
Can directly drive LED.
N-ch open-drain I/O port. Can be specified for input or output in 1-bit units.
Pull-up resistor can be connected in 1-bit units by mask option.
Can directly drive LED.
P-ch open-drain high-voltage output port.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units). Can directly drive LEDs.
P-ch open-drain high-voltage output port.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units). Can directly drive LEDs.
P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units). Can directly drive LEDs.
P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units). Can directly drive LEDs.
P-ch open-drain high-voltage I/O port. Can be specified for input or output in 1-bit units.
Pull-down resistor can be connected in 1-bit units by mask option (connection to VLOAD
or VSS can be specified in 4-bit units). Can directly drive LEDs.
P00, P04
P01-P03
P10-P17
P20-P27
P30-P37
P70-P74
P80-P87
P90-P97
P100-P107
P110-P117
P120-P127
Port 0
Port 1
Port 2
Port 3
Port 7
Port 8
Port 9
Port 10
Port 11
Port 12
µ
PD780204, 780205, 780206, 780208
19
5.2 CLOCK GENERATOR CIRCUIT
The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock.
The instruction time can be changed.
• 0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s/6.4
µ
s (with main system clock: 5.0 MHz)
• 122
µ
s (with subsystem clock: 32.768 kHz)
Figure 5-1. Clock Generator Circuit Block Diagram
Table 5-2. Timer/Event Counter Groups and Configurations
16-bit Timer/ 8-bit Timer/ Watch Watchdog
Event Counter Event Counter Timer Timer
Interval timer 1 channel 2 channels 1 channel 1 channel
External event counter 1 channel 2 channels – –
Timer output 1 output 2 outputs – –
PWM output 1 output – – –
Pulse width measurement 1 input – – –
Square wave output 1 output 2 outputs – –
Interrupt Request 1 2 1 1
Test input – – 1 input –
Subsystem
clock generator
circuit
Main system
clock generator
circuit
Selector
Noise detector
circuit
Pre-scaler
Selector
Selector
Pre-scaler
To INTP0
sampling clock
Standby
control
circuit CPU clock (f
CPU
)
Clock to
hardware peripherals
Watch timer
Clock output circuit
f
XT
f
X
f
XT
XT1/P04
XT2
X1
X2
f
X
8
f
X
16
f
X
2f
X
2
2
f
X
2
3
f
X
2
4
STOP
12
2
5.3 TIMER/EVENT COUNTER
Five channels of timer/event counters are provided.
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer : 1 channel
• Watchdog timer : 1 channel
Group
Function
µ
PD780204, 780205, 780206, 780208
20
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal bus
16-bit compare
register (CR00)
16-bit timer register(TM0)
16-bit capture register (CR01)
Internal bus
PWM
pulse
output
control
circuit
Selector
Output control 
circuit
Edge
detector
circuit
Coincidence
Selector
Cleared
TI0/INTP0/P00
f
X
/2
3
f
X
/2
2
f
X
/2
INTP0
TO0/P30
INTTM0
f
X
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
8-bit timer
register 2 (TM2)
Internal bus
Internal bus
8-bit compare
register (CR10) 8-bit compare
register (CR20)
8-bit timer
register 1 (TM1)
Output
control
circuit
Output
control
circuit
Coincidence
Coincidence
SelectorSelector
Selector
Selector
Selector
Cleared
TO1/P31
INTTM2
TO2/P32
INTTM1
f
X
/2
12
f
X
/2 -f
X
/2
10
f
X
/2 -f
X
/2
10
f
X
/2
12
TI1/P33 Cleared
TI2/P34
2
2
µ
PD780204, 780205, 780206, 780208
21
Figure 5-4. Watch Timer Block Diagram
Figure 5-5. Watchdog Timer Block Diagram
Pre-scaler
5-bit counter
Selector Selector
Selector
Selector
fX/28
fXT
fW
fW
29
fW
28
fW
27
fW
26
fW
25
fW
24
fW
213
fW
214
INTWT
INTTM3
Pre-selector
Selector
RESET
Selector
Control circuit
8-bit
counter
INTWDT
maskable
interrupt
request
INTWDT
non-maskable
interrupt
request
f
X
2
4
f
X
2f
WDT
2
f
WDT
f
WDT
2
2
f
WDT
2
3
f
WDT
2
4
f
WDT
2
5
f
WDT
2
6
f
WDT
2
8
3
µ
PD780204, 780205, 780206, 780208
22
5.4 CLOCK OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the clock :
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz)
• 32.768 kHz (with subsystem clock: 32.768 kHz)
Figure 5-6. Clock Output Control Circuit Block Diagram
5.5 BUZZER OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the buzzer:
• 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
XT
Selector
PCL/P35
Sync circuit Output control circuit
f
X
/2
10
f
X
/2
11
f
X
/2
12
Selector
BUZ/P36
Output control circuit
µ
PD780204, 780205, 780206, 780208
23
5.6 A/D CONVERTER
An 8-bit resolution 8-channel A/D converter is provided.
This A/D converter can be started in the following two modes:
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
5.7 SERIAL INTERFACE
Two channels of clocked serial interfaces are provided.
• Serial interface channel 0
• Serial interface channel 1
Table 5-3. Serial Interface Groups and Functions
Function Serial Interface Channel 0 Serial Interface Channel 1
3-line serial I/O mode (MSB/LSB first selectable) (MSB/LSB first selectable)
SBI (serial bus interface) mode (MSB first) –
2-line serial I/O mode (MSB first) –
3-line serial I/O mode
w/automatic transfer/reception – (MSB/LSB first selectable)
function
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
INTP3/P03 INTAD
INTP3
AV
SS
AV
REF
AV
DD
Sample & hold circuit
Voltage comparator
Successive approximation
registor (SAR)
Series resistor string
Falling edge
detector 
circuit
Control
circuit
A/D conversion result
register (ADCR)
Internal bus
Tap selector
Selector
µ
PD780204, 780205, 780206, 780208
24
Figure 5-9. Serial Interface Channel 0 Block Diagram
Figure 5-10. Serial Interface Channel 1 Block Diagram
Internal bus
Buffer RAM
Serial I/O shift register 1 (SIO1)
Automatic data
transfer/reception
interval specification
register (ADTI)
5-bit counter
SO1/P21
SI1/P20
Selector
Interrupt request
signal generator
circuit INTCSI1
f
X
/2
2
-f
X
/2
9
TO2
Serial clock counter
Serial clock
control circuit
SCK1/P22
Automatic data transfer/
reception address
pointer (ADTP)
STB/P23
BUSY/P24
Coincidence
Handshake
control
circuit
Internal bus
Serial I/O shift
Bus release/
command/acknowledge
detector circuit
Serial clock counter
Serial clock
control circuit
Interrupt request
signal generator
circuit
Busy/acknowledge
output circuit
Selector Selector
Selector
Output
latch
INTCSI0
f
X
/2
2
-f
X
/2
9
TO2
register 0 (SIO0)
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
µ
PD780204, 780205, 780206, 780208
25
5.8 FIP CONTROLLER/DRIVER
An FIP controller/driver having the following features is provided:
(a) Automatic output of segment signals (DMA operation) and digit signals by automatically reading display data
(b) Display mode register 0-2 (DSPM0-DSPM2) that can control an FIP of 9 to 40 segments and 2 to 16 digits
(c) The output timing of the digit signal can be freely set by selecting the display mode 2 by using the display mode
register 0 (DSPM0).
(d) Port pins not used for FIP display can be used as output port or I/O port pins (however, FIP0-FIP12 are display
output pins).
(e) Display mode register 1 (DSPM1) can adjust luminance in eight steps.
(f) Hardware suitable for key scan application using segment pins
(g) High-voltage output buffer (FIP driver) that can directly drive an FIP
(h) Display output pins can be connected to a pull-down resistor by mask option.
Figure 5-11. Selecting Display Modes
2345678910 11 12 13 14 15 16
9
10
11
12
13
14
15
16
17
18
19
20
36
37
00
Selecting number of digits
Selecting number of segments
38
39
40
Caution If the total number of digits and segments exceeds 53, the specified number of digits takes
precedence.
µ
PD780204, 780205, 780206, 780208
26
Figure 5-12. FIP Controller/Driver Block Diagram
Internal bus
Display data memory
Display data selector
FIP52/P127
Display data latch
Write mask control circuit
Digit signal generation circuit
Port output latch
FIP13/P80FIP0
High-voltage buffer
µ
PD780204, 780205, 780206, 780208
27
Interrupt Source
Default
PriorityNote 1
—
0
1
2
3
4
5
6
7
8
9
10
11
12
—
Name
INTWDT
INTWDT
INTP0
INTP1
INTP2
INTP3
INTCSI0
INTCSI1
INTTM3
INTTM0
INTTM1
INTTM2
INTAD
INTKS
BRK
Internal/
External
Internal
External
Internal
Trigger
Overflow of watchdog timer (when
watchdog timer mode 1 is selected)
Overflow of watchdog timer (when
interval timer mode is selected)
Pin input edge detection
End of transfer by serial interface
channel 0
End of transfer by serial interface
channel 1
Reference time interval signal from
watch timer
Coincidence signal generation of
16-bit timer/event counter
Coincidence signal generation of
8-bit timer/event counter 1
Coincidence signal generation of
8-bit timer/event counter 2
End of conversion by A/D converter
Key scan timing from FIP controller/
driver
Execution of BRK instruction
6. INTERRUPT FUNCTION AND TEST FUNCTION
6.1 INTERRUPT FUNCTION
The following three types, 15 sources of interrupt functions are available:
• Non-maskable : 1
• Maskable : 13
• Software : 1
Table 6-1. Interrupt Sources
Interrupt
Type
Non-
maskable
Maskable
Software
Notes 1. The default priority is assumed when two or more maskable interrupts are generated at the same time, and
0 is the highest and 12 is the lowest.
2. Basic configuration types (A)-(E) respectively correspond to (A) to (E) in Figure 6-1.
Vector
Table
Address
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
003EH
Basic Configura-
tion Type
Note 2
(A)
(B)
(C)
(D)
(B)
(E)
µ
PD780204, 780205, 780206, 780208
28
Figure 6-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Interrupt
request Priority
control circuit Vector table 
address
generator circuit
Standby
release signal
(B) Internal maskable interrupt
Internal bus
Interrupt
request
Priority
control circuit Vector table 
address
generator circuit
Standby
release signal
MK IE PR ISP
IF
(C) External maskable interrupt (INTP0)
Internal bus
MK IE PR ISP
IF
Interrupt
request
Standby
release signal
Priority
control circuit Vector table 
address
generator circuit
Sampling clock 
select register 
(SCS)
External interrupt
mode register
(INTM0)
Sampling
clock Edge 
detector
circuit
µ
PD780204, 780205, 780206, 780208
29
Figure 6-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal bus
MK IE PR ISP
IF
Interrupt
request
Standby
release signal
Priority
control circuit Vector table 
address
generator circuit
External interrupt
mode register
(INTM0)
Edge 
detector
circuit
(E) Software interrupt
Internal bus
Priority
control circuit Vector table 
address
generator circuit
Interrupt
request
IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
µ
PD780204, 780205, 780206, 780208
30
6.2 TEST FUNCTION
The following trigger is available for test function.
Test Input Source Internal/
Name Trigger External
INTWT Overflow of watch timer Internal
Figure 6-2. Basic Configuration of Test Function
Internal bus
MK
IF
Test input source
(INTWT) Standby
release signal
IF : Test request flag
MK : Test mask flag
µ
PD780204, 780205, 780206, 780208
31
7. STANDBY FUNCTION
The standby function is to reduce the current dissipation of the system and can be effected in the following two modes:
• HALT mode: In this mode, the operating clock of the CPU is stopped. By using this mode in combination with
the normal operation mode, the system can be operated intermittently, so that the average current
dissipation can be reduced.
• STOP mode: Oscillation of the main system clock is stopped. All the operations on the main system clock are
stopped, and therefore, the current dissipation of the system can be minimized with only the
subsystem clock oscillating.
Figure 7-1. Standby Function
STOP mode
(Oscillation of main system
clock stopped)
Main system
clock operation Subsystem
clock operation
Note
HALT mode
(Clock supply to CPU stopped.
Oscillation continues)
HALT mode
Note
(Clock supply to CPU stopped.
Oscillation continues)
STOP
instruction
Interrupt 
request Interrupt 
request
CSS=0
CSS=1
HALT instruction
Interrupt 
request
HALT instruction
Note By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on the
subsystem clock, stop the main system clock by setting the MCC. The STOP instruction cannot be used.
Caution To select the main system clock again after the main system clock has been stopped once while the
subsystem clock is in use, make sure through the program that the oscillation stabilization time
elapses, and then that the main system clock is selected.
8. RESET FUNCTION
The system can be reset in the following two modes:
• External reset by RESET pin
• Internal reset by watchdog timer that detects hang up
32
µ
PD780204, 780205, 780206, 780208
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
Operand
[HL + byte]
#byte A rNote sfr saddr !addr16 PSW [DE] [HL] [HL + B]
$addr16
1 None
First [HL + C]
Operand
A ADD MOV MOV MOV MOV MOV MOV MOV MOV ROR
ADDC XCH XCH XCH XCH XCH XCH XCH ROL
SUB ADD ADD ADD ADD ADD RORC
SUBC ADDC ADDC ADDC ADDC ADDC ROLC
AND SUB SUB SUB SUB SUB
OR SUBC SUBC SUBC SUBC SUBC
XOR AND AND AND AND AND
CMP OR OR OR OR OR
XOR XOR XOR XOR XOR
CMP CMP CMP CMP CMP
r MOV MOV INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B,C DBNZ
sfr MOV MOV
saddr MOV MOV DBNZ INC
ADD DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV ROR4
ROL4
[HL + byte] MOV
[HL + B]
[HL + C]
XMULU
C DIVUW
Note Except for r=A
33
µ
PD780204, 780205, 780206, 780208
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second
Operand #word AX rpNote sfrp saddrp !addr16 SP None
First
Operand
AX ADDW MOVW MOVW MOVW MOVW MOVW
SUBW XCHW
CMPW
rp MOVW Note INCW
MOVW DECW
PUSH
POP
sfrp MOVW MOVW
saddrp MOVW MOVW
!addr16 MOVW
SP MOVW MOVW
Note Only when rp=BC, DE, HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second
Operand
A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None
First
Operand
A.bit MOV1 BT SET1
BF CLR1
BTCLR
sfr.bit MOV1 BT SET1
BF CLR1
BTCLR
saddr.bit MOV1 BT SET1
BF CLR1
BTCLR
PSW.bit MOV1 BT SET1
BF CLR1
BTCLR
[HL].bit MOV1 BT SET1
BF CLR1
BTCLR
CY MOV1 MOV1 MOV1 MOV1 MOV1 SET1
AND1 AND1 AND1 AND1 AND1 CLR1
OR1 OR1 OR1 OR1 OR1 NOT1
XOR1 XOR1 XOR1 XOR1 XOR1
34
µ
PD780204, 780205, 780206, 780208
(4) Call/Branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second
Operand AX !addr16 !addr11 [addr5] $addr16
First
Operand
Basic operation BR CALL CALLF CALLT BR
BR BC
BNC
BZ
BNZ
Compound BT
operation BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
35
µ
PD780204, 780205, 780206, 780208
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Supply voltage
Input voltage
–0.3 to VDD +0.3 V
VI1
1 pin of P01 to P03, P10 to P17, P20 to
P27, P30 to P37, P70 to P74
Total for P90 to P97, P100 to P107,
P110 to 117, P120 to P127
High-level
output current
Parameter Symbol Conditions Rating Unit
VDD –0.3 to +7.0 V
VLOAD VDD –45 to VDD +0.3 V
AVDD –0.3 to VDD +0.3 V
AVREF –0.3 to VDD +0.3 V
AVSS –0.3 to +0.3 V
P00 to P04, P10 to P17 (except analog input pin),
P20 to P27, P30 to P37, X1, X2, XT2, RESET
VI2 P70 to P74 N-ch open drain –0.3 to +16 Note 1 V
VI3
P100 to P107, P110 to P117, P120 to P127
P-ch open drain VDD –45 to VDD +0.3 V
Output voltage VO1 P01 to P03, P10 to P17, P20 to P27, P30 to P37 –0.3 to VDD +0.3 V
VO2 P70 to P74 –0.3 to +16 Note 1 V
VOD P80 to P87, P90 to P97, P100 to P107, P110 to P117, VDD –45 to VDD +0.3 V
P120 to P127, FIP0 to FIP12
Analog input voltage VAN
ANI0 to ANI7 Analog input pins AVSS –0.3 to AVREF +0.3 V
1 pin of P01 to P03, P10 to P17, P20 to P27, P30 to P37
–10 mA
Total for P01 to P03, P10 to P17, P20 to P27, P30 to P37
–30 mA
1 pin of P80 to P87, P90 to P97, P100 to P107, P110 to P117, –30 mA
P120 to P127, FIP0 to FIP12
Total for P80 to P87, FIP0 to FIP12 Peak value –240 mA
RMS –120 Note 2 mA
Peak value –100 mA
RMS –60 Note 2 mA
Peak value 30 mA
RMS 15 Note 2 mA
Total for P70 to P74 Peak value 100 mA
RMS 60 Note 2 mA
Total for P01 to P03, Peak value 50 mA
P10 to17, P20 to 27, P30 to P37 RMS 20 Note 2 mA
Total power PT Note 3 TA = –40 to +60 ˚C 800 mW
dissipation 600 mW
TA–40 to +85 °C
Storage temperature
Tstg –65 to +150 °C
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,
or even momentarily. In other words, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used under
conditions which ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, dual-function pin characteristics are the same as port pin characteristics.
Notes 1. With the mask option, the range of the internal pull-up resistor pin is 0.3 to VDD +0.3.
2. The RMS should be calculated as follows: [RMS] = [Peak value] × √Duty
Operating ambient
temperature
Low-level
output current
I
OH
IOL
36
µ
PD780204, 780205, 780206, 780208
Notes 3. Total power dissipation differs depending on the temperature (see the following figure).
+80+400–40
800
600
400
200
Temperature [˚C]
Total power dissipation P
T
[mW]
How to calculate total power dissipation
The following three power dissipation are available for the
µ
PD780204, 780205, 780206, and 780208. The sum of
the three power dissipation should be less than the total power dissipation PT (80 % or less of ratings is recommended).
<1> CPU power dissipation: calculate VDD (MAX.) × IDD1 (MAX.).
<2> Output pin power dissipation: Normal output and display output are available. Power dissipation when maximum
current flows into each output.
<3> Pull-down resistor power dissipation: Power dissipation by pull-down resistor incorporated in display output pin
by mask option.
The following is how to calculate total power dissipation for the example in the next page.
Example Assume the following conditions:
VDD = 5 V ± 10 %, 5.0 MHz oscillator
Supply current (IDD) = 21.6 mA
Display output: 11 grids × 10 segments (Cut width = 1/16)
Maximum current at the grid pin is 15 mA.
Maximum current at the segment pin is 3 mA.
At the key scan timing, display output pin is OFF.
Display output voltage: grid VOD = VDD – 2 V (voltage drop of 2 V)
segments VOD = VDD – 0.4 V (voltage drop of 0.4 V)
Fluorescent display control voltage (VLOAD) = –35 V
Mask option pull-down resistor = 25 kΩ
37
µ
PD780204, 780205, 780206, 780208
By placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out.
<1> CPU power dissipation: 5.5 V × 21.6 mA = 118.8 mW
<2> Output pin power dissipation:
Grid (VDD – VOD) × Total current value of each grid × Digit width (1 – Cut width)
The number of grids + 1
= 2 V × 15 mA × 11 Grids × (1 – 1 ) = 25.8 mW
11 Grids + 1 16
Segment (VDD – VOD) × Total segment current value of illuminated dots
The number of grids +1
= 0.4 V × 3 mA × 31 Dots = 3.1 mW
11 Grids + 1
<3> Pull-down resistor power dissipation:
Grid (VOD – VLOAD)2 × The number of grids × Digit width
Pull-down resistor value The number of grids + 1
= (5.5 V – 2 V – (–35 V))2 × 11 Grids × (1 – 1 ) = 50.9 mW
25 kΩ 11 Grids + 1 16
Segment (VOD – VLOAD)2 × The number of illuminated dots
Pull-down resistor value The number of grids + 1
= (5.5 V – 0.4 V – (–35 V))2 × 31 dots = 166.1 mW
25 kΩ 11 Grids + 1
Total power dissipation = <1> + <2> + <3> = 118.8 + 25.8 + 3.1 + 50.9 + 166.1 = 364.7 mW
In this example, the total power dissipation do not exceed the rating of the total power dissipation, so there
is no problem in power dissipation.
However, when the total power dissipation exceeds the rating of the total power dissipation, it is necessary
to lower the power dissipation. To reduce power dissipation, reduce the number of pull-down resistor.
38
µ
PD780204, 780205, 780206, 780208
Figure 10-1 Display Example of 10 segments-11 digits
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
0
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
1
1
1
0
0
0
FA7AH
FA6AH FA79H
FA69H FA78H
FA68H FA77H
FA67H FA76H
FA66H FA75H
FA65H FA74H
FA64H FA73H
FA63H FA72H
FA62H FA71H
FA61H FA70H
FA60H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
FA7 × H
FA6 × H
S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0
SUN
1
MON
2
TUE
3
WED
4
THU
5
FRI
6
SAT
7 8 9 10
AMi
PMj
0
i
e
f
d
g
c
b
a
j·
j·
a b c d e f g h i j
Display Data Memory
h
39
µ
PD780204, 780205, 780206, 780208
MAIN SYSTEM CLOCK OSCILLATION CIRCUIT CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillator frequency
(fX)Note 1
Oscillator stabilization
timeNote 2
Oscillator frequency
(fX)Note 1
Oscillator stabilization VDD = 4.5 to 5.5 V 10
timeNote 2
30
X1 input frequency
(fX)Note 1
X1 input high-/low-level
width (tXH/tXL)
Notes 1. Only the oscillator characteristics are shown. See AC CHARACTERISTICS for instruction execution times.
2. This is the time required for oscillation to stabilize after reset, or STOP mode release.
Cautions 1. When the main system clock oscillator is used, the following should be noted concerning wiring
in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance,
etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed.
• Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VSS.
• Do not connect to a ground pattern carrying a high current.
• A signal should not be taken from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization time has been secured by the program before switching back
to the main system clock.
15
MHz
4ms
1
4.19 5
MHz
ms
15
MHz
85 500 ns
X1 X2
PD74HCU04
µ
X1IC X2
C2
C1
Crystal resonator
External clock
Ceramic resonator
X1 X2IC
C1 C2
40
µ
PD780204, 780205, 780206, 780208
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
XT1 XT2
XT1 ICXT2
C4
R
C3
External clock
Crystal resonator
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Oscillator frequency
(fXT)Note 1
Oscillator stabilization
timeNote 2
XT1 input frequency
(fXT)Note 1
XT1 input high-/low-level
width (tXTH/tXTL)
32.768
32
kHz
35
VDD = 4.5 to 5.5 V
10 s
32 100
kHz
515
µ
s
1.2 2
Notes 1. Only the oscillator characteristics are shown. See AC CHARACTERISTICS for instruction execution times.
2. This is the time required for oscillation to stabilize after VDD reaches MIN. in the range of oscillation voltage.
Cautions 1. When the subsystem clock oscillator is used, the following should be noted concerning wiring
in the area in the figure enclosed by a broken line to prevent the influence of wiring capacitance,
etc.
• The wiring should be kept as short as possible.
• No other signal lines should be crossed.
• Keep away from lines carrying a high fluctuating current.
• The oscillator capacitor grounding point should always be at the same potential as VSS.
• Do not connect to a ground pattern carrying a high current.
• A signal should not be taken from the oscillator.
2. The subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption
current, and is more prone to misoperation due to noise than the main system clock oscillator.
Particular care is therefore required with the wiring method when the subsystem clock is used.
41
µ
PD780204, 780205, 780206, 780208
RECOMMENDED OSCILLATOR CONSTANT
(1)
µ
PD780204, 780205
Main System Clock: Ceramic Resonator (TA = –40 to +85 ˚C)
Manufacturer Product Name Frequency Circuit Constant
Oscillator Voltage Range
Remark
(MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V)
Murata Mfg. Co., Ltd. CSB1000J 1.0 100 100 3.00 5.50
Toyama CSA2.00MG040 2.0 100 100 2.80 5.50
CST2.00MG040 2.0 — — 2.80 5.50 Built-in capacitor
CSA4.00MG 4.0 30 30 2.70 5.50
CST4.00MGW 4.0 — — 2.70 5.50 Built-in capacitor
CSA5.00MG 5.0 30 30 2.90 5.50
CST5.00MGW 5.0 — — 2.90 5.50 Built-in capacitor
TDK Corp. CCR1000K2 1.0 150 150 2.70 5.50
FCR4.00MC5 4.0 — — 2.70 5.50 Built-in capacitor
CCR4.00MC3 4.0 — — 2.70 5.50 Built-in capacitor
FCR5.00MC5 5.0 — — 2.80 5.50 Built-in capacitor
CCR5.00MC3 5.0 — — 2.70 5.50 Built-in capacitor
Matsushita Electronics EFOEC5004A4 5.0 — — 2.70 5.50 Built-in capacitor
Components Co., Ltd. EFOEN5004A4 5.0 33 33 2.70 5.50
EFOS5004B5 5.0 — — 2.70 5.50 Built-in capacitor
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation.
However, they do not guarantee accuracy of the oscillation frequency. If the application circuit
requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the
application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being
used.
42
µ
PD780204, 780205, 780206, 780208
(2)
µ
PD780206, 780208
Main System Clock: Ceramic Resonator (TA = –40 to +85 ˚C)
Manufacturer Product Name Frequency Circuit Constant
Oscillator Voltage Range
Remark
(MHz) C1 (pF) C2 (pF) MIN. (V) MAX. (V)
Murata Mfg. Co., Ltd. CSB1000J 1.0 100 100 2.80 5.50
Toyama CSA2.00MG040 2.0 100 100 2.70 5.50
CST2.00MG040 2.0 — — 2.70 5.50 Built-in capacitor
CSA4.00MG 4.0 30 30 2.70 5.50
CST4.00MGW 4.0 — — 2.70 5.50 Built-in capacitor
CSA5.00MG 5.0 30 30 2.70 5.50
CST5.00MGW 5.0 — — 2.70 5.50 Built-in capacitor
TDK Corp. CCR1000K2 1.0 220 220 2.70 5.50
CCR2.0MC33 2.0 — — 2.70 5.50 Built-in capacitor
CCR4.0MC3 4.0 — — 2.70 5.50 Built-in capacitor
FCR4.0MC5 4.0 — — 2.70 5.50 Built-in capacitor
CCR4.19MC3 4.19 — — 2.70 5.50 Built-in capacitor
FCR4.19MC5 4.19 — — 2.70 5.50 Built-in capacitor
CCR5.0MC3 5.0 — — 2.70 5.50 Built-in capacitor
FCR5.0MC5 5.0 — — 2.70 5.50 Built-in capacitor
Matsushita Electronics EFOEC2004A5 2.0 33 33 2.70 5.50
Components Co., Ltd. EFOEC4004A4 4.0 33 33 2.85 5.50
EFOEC4194A4 4.19 33 33 2.70 5.50
EFOEC5004A4 5.0 33 33 2.70 5.50
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation.
However, they do not guarantee accuracy of the oscillation frequency. If the application circuit
requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the
application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being
used.
43
µ
PD780204, 780205, 780206, 780208
CAPACITANCE (TA = 25 ˚C, VDD = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input capacitance CIN f = 1 MHz Unmeasured pins returned to 0 V 15 pF
Output COUT f = 1 MHz Unmeasured pins returned to 0 V 35 pF
capacitance
Input/output CIO f = 1 MHz
P01 to P03, P10 to P17,
15 pF
capacitance Unmeasured pins returned
P20 to P27, P30 to P37
to 0 V P70 to P74 20 pF
P100 to P107, P110 to
35 pF
P117, P120 to P127
Remark Unless otherwise specified, the characteristics of the shared pin are the same as the characteristics of the
port pin.
POWER SUPPLY VOLTAGE (TA = –40 to +85 ˚C)
Parameter Conditions MIN. TYP. MAX. Unit
CPUNote 1 2.7Note 2 5.5 V
Display controller/driver 4.5 5.5 V
PWM mode of 16-bit 4.5 5.5 V
time/event counter (TM0)
A/D converter 4.0 5.5 V
Other hardware 2.7 5.5 V
Notes 1. Except for system clock oscillator, display controller/driver, and PWM.
2. Operating power supply voltage range differs depending on the cycle time. See AC CHARACTERISTICS.
44
µ
PD780204, 780205, 780206, 780208
DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 2.7 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-level VIH1 P21, P23 0.7 VDD VDD V
input voltage VIH2 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET 0.8 VDD VDD V
VIH3 P70 to P74 N-ch open-drain 0.7 VDD 15 V
VIH4 X1, X2 VDD – 0.5 VDD V
VIH5 XT1/P04, XT2 VDD = 4.5 to 5.5 V 0.8 VDD VDD V
0.9 VDD VDD V
VIH6 P10 to P17, P30 to P32, VDD = 4.5 to 5.5 V 0.65 VDD VDD V
P35 to P37 0.7 VDD VDD V
VIH7 P100 to P107, P110 to P117, VDD = 4.5 to 5.5 V 0.7 VDD VDD V
P120 to P127 VDD – 0.5 VDD V
Low-level VIL1 P21, P23 0 0.3 VDD V
input voltage VIL2 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET 0 0.2 VDD V
VIL3 P70 to P74 VDD = 4.5 to 5.5 V 0 0.3 VDD V
0 0.2 VDD V
VIL4 X1, X2 0 0.4 V
VIL5 XT1/P04, XT2 VDD = 4.5 to 5.5 V 0 0.2 VDD V
0 0.1 VDD V
VIL6 P10 to P17, P30 to P32, P35 to P37 0 0.3 VDD V
VIL7 P100 to P107, P110 to P117, P120 to P127
VDD – 40
0.3 VDD V
High-level VOH VDD = 4.5 to 5.5 V,
VDD – 1.0
V
output voltage IOH = –1 mA
IOH = –100
µ
A
VDD – 0.5
V
Low-level VOL1 P30 to P37, P70 to P74 VDD = 4.5 to 5.5 V 0.4 2.0 V
output voltage IOL = 15 mA
P01 to P03, P10 to P17, VDD = 4.5 to 5.5 V 0.4 V
P20 to P27 IOL = 1.6 mA
VOL2 SB0, SB1, SCK0 VDD = 4.5 to 5.5 V 0.2 VDD V
With open-drain and
pull-up (R = 1 kΩ)
VOL3 IOL = 400
µ
A 0.5 V
Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
P01 to P03, P10 to P17, P20 to
P27, P30 to P37, P80 to P87, P90
to P97, P100 to P107, P110 to
P117, P120 to P127, FIP0 to FIP12
45
µ
PD780204, 780205, 780206, 780208
DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 2.7 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-level ILIH1 VIN = VDD
P00 to P03, P10 to P17,
3
µ
A
input leakage
P20 to P27, P30 to P37,
current P70 to P74, RESET
ILIH2 X1, X2, XT1/P04, XT2 20
µ
A
ILIH3 VIN = 15 V P70 to P74 80
µ
A
ILIH4 P100 to P107, P110 to P117, VDD = 4.5 to 5.5 V 3Note 1
µ
A
P120 to P127 VIN = VDD 3Note 2
µ
A
Low-level input ILIL1 VIN = 0 V
P00 to P03, P10 to P17, P20
–3
µ
A
leakage
to P27, P30 to P37, RESET
current ILIL2 X1, X2, XT1/P04 XT2 –20
µ
A
ILIL3 P70 to P74 –3Note 3
µ
A
ILIL4 P100 to P107, P110 to –10
µ
A
P117, P120 to P127
High-level output ILOH1 VOUT = VDD
P01 to P03, P10 to P17,
3
µ
A
leakage
P20 to P27, P30 to P37,
current Note 4
P80 to P87, P90 to P97,
P100 to P107, P110 to
P117, P120 to P127,
FIP0 to FIP12
ILOH2 VOUT = 15 V
P70 to P74, N-ch open-drain
80
µ
A
Low-level output ILOL1 VOUT = 0 V
P01 to P03, P10 to P17,
–3
µ
A
leakage
P20 to P27, P30 to P37,
current Note 4 P70 to P74
ILOL2 VOUT = VLOAD = VDD – 40 V
P80 to P87, P90 to P97,
–10
µ
A
P100 to 107, P110 to
P117,
P120 to P127,
FIP0 to FIP12
Display output IOD VDD = 4.5 to 5.5 V, VOD = VDD – 2 V –15 –18 mA
current
Mask option R1VIN = 0 V, P70 to P74 20 40 90 kΩ
pull-up resistor
Software R2VIN = 0 V
,
VDD = 4.5 to 5.5 V 15 40 90 kΩ
pull-up resistor P01 to P03, P10 to P17, 20 500 kΩ
P20 to P27, P30 to P37
Notes 1. For P110 to P117 and P120 to P127 without on-chip pull-down resistor (specifiable by mask option), a high-
level input leak current of 50
µ
A (MAX.) flows only during the 1.5 clocks after an instruction has been executed
to read out ports 11, 12 (P11, P12) or port mode registers 11, 12 (PM11, PM12). Outside the period of 1.5
clocks following executing a read-out instruction, the current is 3
µ
A (MAX.).
2. For P110 to P117 and P120 to P127 without on-chip pull-down resistor (specifiable by mask option), a high-
level input leak current of 30
µ
A (MAX.) flows only during the 1.5 clocks after an instruction has been executed
to read out P11, P12, PM11, and PM12. Outside the period of 1.5 clocks following executing a read-out
instruction, the current is 3
µ
A (MAX.).
3. For P70 to P74 without on-chip pull-up resistor (specifiable by mask option), a low-level input leak current
of –200
µ
A (MAX.) flows only during the 1.5 clocks after an instruction has been executed to read out port
7 (P7) or port mode register 7 (PM7). Outside the period of 1.5 clocks following executing a read-out
instruction, the current is –3
µ
A (MAX.).
4. This current excludes the current which flows in the on-chip pull-up/pull-down resistor.
Remark Unless otherwise specified, the characteritics of a shared pin are the same as those of a port pin.
46
µ
PD780204, 780205, 780206, 780208
DC CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 2.7 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Mask option R3VOD – VLOAD = 40 V 25 70 135 kΩ
pull-down resistor
VOD – VSS = 5 V 20 55 100 kΩ
R4P30 to P37, VIN = VDD 40 80 150 KΩ
Power supply IDD1 5.0 MHz crystal oscillation
VDD = 5.0 V ± 10 %
Note 2
7.2 21.6 mA
current Note 1 operating mode
VDD = 3.0 V ± 10 %
Note 3
0.9 2.7 mA
IDD2 5.0 MHz crystal oscillation V DD = 5.0 V ± 10 % 1.6 4.8 mA
HALT mode VDD = 3.0 V ± 10 % 650 1950
µ
A
IDD3 32.768 kHz crystal oscillation VDD = 5.0 V ± 10 % 60 120
µ
A
operating mode
Note 4
VDD = 3.0 V ± 10 % 32 64
µ
A
IDD4 32.768 kHz crystal oscillation VDD = 5.0 V ± 10 % 25 55
µ
A
HALT mode
Note 4
VDD = 3.0 V ± 10 % 5 15
µ
A
IDD5
XT1 = 0 V in STOP mode when
VDD = 5.0 V ± 10 % 1 30
µ
A
connecting to feedback resistor
VDD = 3.0 V ± 10 % 0.5 10
µ
A
IDD6
XT1 = 0 V in STOP mode when
VDD = 5.0 V ± 10 % 0.1 30
µ
A
not connecting to feedback resistor
VDD = 3.0 V ± 10 % 0.05 10
µ
A
Notes 1. This current excludes the AVREF current, port current, and current which flows in the on-chip pull-down
resistor (mask option).
2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H)
3. When operating at low-speed mode (when the PCC is set to 04H)
4. When main system clock stopped.
P80 to P87, P90 to P97,
P100 to P107, P110 to P117,
P120 to P127
47
µ
PD780204, 780205, 780206, 780208
AC CHARACTERISTICS
(1) Basic Operation (TA = –40 to +85 ˚C, VDD = 2.7 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Cycle time (minimum TCY Operated with main VDD = 4.5 to 5.5 V 0.4 32
µ
s
instruction execution system clock 0.8 32
µ
s
time) Operated with subsystem clock 40Note 1 122 125
µ
s
TI1, TI2 input fTI VDD = 4.5 to 5.5 V 0 2 MHz
frequency 0 138 kHz
TI1, TI2 input high, fTIH VDD = 4.5 to 5.5 V 250 ns
low-level width fTIL 3.6
µ
s
Interrupt input high, fINTH INTP0
8/fsam
Note 2
µ
s
low-level width fINTL INTP1 to INTP3 10
µ
s
RESET low-level width tRSL 10
µ
s
Notes 1. Value when external clock input is used as subsystem clock. When crystal is used, the value becomes 114
µ
s.
2. Selection of fsam = fx/2N+1, fx/64, fx/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of sampling
clock select register (SCS).
6531
60
30
10
2.0
Power supply voltage V
DD
[V]
Cycle time T
CY
[ s]
42
1.0
0.5
0.4
T
CY
vs. V
DD
(with main system clock operated)
Operation guarantee
range
0
µ
48
µ
PD780204, 780205, 780206, 780208
(2) Serial Interface (TA = –40 to +85 ˚C, VDD = 2.7 to 5.5 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0: Internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY1 VDD = 4.5 to 5.5 V 800 ns
1600 ns
SCK0 high, low-level tKH1 VDD = 4.5 to 5.5 V
tKCY1/2 – 50
ns
width tKL1
tKCY1/2 – 100
ns
SI0 setup time (to SCK0↑)
tSIK1 VDD = 4.5 to 5.5 100 ns
150 ns
SI0 hold time (from SCK0↑)
tKSI1 400 ns
SCK0↓→ SO0 tKSO1 C = 100 pFNote 300 ns
output delay time
Note C is a load capacitance of the SCK0 or SO0 output line.
(ii) 3-wire serial I/O mode (SCK0: External clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY2 VDD = 4.5 to 5.5 V 800 ns
1600 ns
SCK0 high, low-level tKH2 VDD = 4.5 to 5.5 V
tKCY2/2 – 50
ns
width tKL2
tKCY2/2 – 100
ns
SI0 setup time (to SCK0↑)
tSIK2 VDD = 4.5 to 5.5 V 100 ns
150 ns
SI0 hold time (from SCK0↑)
tKSI2 400 ns
SCK0↓→ SO0 tKSO2 C = 100 pFNote 300 ns
output delay time
SCK0 rise, fall time tR2 160 ns
tF2
Note C is a load capacitance of the SO0 output line.
49
µ
PD780204, 780205, 780206, 780208
(iii) SBI mode (SCK0: Internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY3 VDD = 4.5 to 5.5 V 800 ns
3200 ns
SCK0 high, low-level tKH3 VDD = 4.5 to 5.5 V
tKCY3/2 – 50
ns
width tKL3
tKCY3/2 – 150
ns
SB0, SB1 setup time tSIK3 VDD = 4.5 to 5.5 V 100 ns
(to SCK0↑) 300 ns
SB0, SB1 hold time tKSI3 tKCY3/2 ns
(from SCK0↑)
SCK0↓→ SB0, SB1 tKSO3 R = 1 kΩ, C = 100 pFNote VDD = 4.5 to 5.5 V 0 250 ns
output delay time 0 1000 ns
SCK0↑→SB0, SB1↓tKSB tKCY3 ns
SB0, SB1↓→SCK0↓tSBK tKCY3 ns
SB0, SB1 high-level tSBH tKCY3 ns
width
SB0, SB1 low-level tSBL tKCY3 ns
width
Note R is a load resistance and C is a load capacitance of the SCK0, SB0, or SB1 output line.
(iv) SBI mode (SCK0: External clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY4 VDD = 4.5 to 5.5 V 800 ns
3200 ns
SCK0 high, low-level tKH4 VDD = 4.5 to 5.5 V 400 ns
width tKL4 1600 ns
SB0, SB1 setup time tSIK4 VDD = 4.5 to 5.5 V 100 ns
(to SCK0↑) 300 ns
SB0, SB1 hold time tKSI4 tKCY4/2 ns
(from SCK0↑)
SCK0↓→ SB0, SB1 tKSO4 R = 1 kΩ, C = 100 pFNote VDD = 4.5 to 5.5 V 0 250 ns
output delay time 0 1000 ns
SCK0↑→SB0, SB1↓tKSB tKCY4 ns
SB0, SB1↓→SCK0↓tSBK tKCY4 ns
SB0, SB1 high-level tSBH tKCY4 ns
width
SB0, SB1 low-level tSBL tKCY4 ns
width
SCK0 rise, fall time tR4 160 ns
tF4
Note R is a load resistance and C is a load capacitance of the SB0 or SB1 output line.
50
µ
PD780204, 780205, 780206, 780208
(v) 2-wire serial I/O mode (SCK0: Internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY5 R = 1 kΩ, C = 100 pFNote 1600 ns
SCK0 high-level width tKH5
tKCY5/2 – 160
ns
SCK0 low-level width tKL5 VDD = 4.5 to 5.5 V
tKCY5/2 – 50
ns
tKCY5/2 – 100
ns
SB0, SB1 setup time tSIK5 VDD = 4.5 to 5.5 V 300 ns
(to SCK0↑) 350 ns
SB0, SB1 hold time tKSI5 600 ns
(from SCK0↑)
SCK0↓→SB0, SB1 tKSO5 0 300 ns
output delay time
Note R is a load resistance and C is a load capacitance of the SCK0, SB0, or SB1 output line.
(vi) 2-wire serial I/O mode (SCK0: External clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK0 cycle time tKCY6 1600 ns
SCK0 high-level width tKH6 650 ns
SCK0 low-level width tKL6 800 ns
SB0, SB1 setup time tSIK6 100 ns
(to SCK0↑)
SB0, SB1 hold time tKSI6 tKCY6/2 ns
(from SCK0↑)
SCK0↓→SB0, SB1 tKSO6 R = 1 kΩ, C = 100 pFNote VDD = 4.5 to 5.5 V 0 300 ns
output delay time 0 500 ns
SCK0 rise, tR6 160 ns
fall time tF6
Note R is a load resistance and C is a load capacitance of the SB0 or SB1 output line.
51
µ
PD780204, 780205, 780206, 780208
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1: Internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK1 cycle time tKCY7 VDD = 4.5 to 5.5 V 800 ns
1600 ns
SCK1 high, low-level tKH7 VDD = 4.5 to 5.5 V
tKCY7/2 – 50
ns
width tKL7
tKCY7/2 – 100
ns
SI1 setup time (to SCK1↑)
tSIK7 VDD = 4.5 to 5.5 V 100 ns
150 ns
SI1 hold time (from SCK1↑)
tKSI7 400 ns
SCK1↓→ SO1 tKSO7 C = 100 pFNote 300 ns
output delay time
Note C is a load capacitance of the SCK1 or SO1 output line.
(ii) 3-wire serial I/O mode (SCK1: External clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK1 cycle time tKCY8 VDD = 4.5 to 5.5 V 800 ns
1600 ns
SCK1 high, low-level tKH8 VDD = 4.5 to 5.5 V
tKCY8/2–50
ns
width tKL8
tKCY8/2–100
ns
SI1 setup time (to SCK1↑)
tSIK8 VDD = 4.5 to 5.5 V 100 ns
150 ns
SI1 hold time (from SCK1↑)
tKSI8 400 ns
SCK1↓→ SO1 tKSO8 C = 100 pFNote 300 ns
output delay time
SCK1 rise, fall time tR8 160 ns
tF8
Note C is a load capacitance of the SO1 output line.
52
µ
PD780204, 780205, 780206, 780208
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1: Internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK1 cycle time tKCY9 VDD = 4.5 to 5.5 V 800 ns
1600 ns
SCK1 high, low-level tKH9 VDD = 4.5 to 5.5 V
tKCY9/2 – 50
ns
width tKL9
tKCY9/2 – 100
ns
SI1 setup time (to SCK1↑)tSIK9 VDD = 4.5 to 5.5 V 100 ns
150 ns
SI1 hold time (from SCK1↑)tKSI9 400 ns
SCK1↓ → SO1 output tKSO9 C = 100 pFNote 300 ns
delay time
SCK1↓ → STB↑tSBD
tKCY9/2 – 100 t KCY9/2 + 100
ns
Strobe signal tSBW
tKCY9 – 30 tKCY9 + 30
ns
high-level width
Busy signal setup time tBYS 100 ns
(to busy signal
detection timing)
Busy signal hold time tBYH VDD = 4.5 to 5.5 V 100 ns
(from busy signal
detection timing 150 ns
Busy inactibe → SCK1↓tSPS 2tKCY9 ns
Note C is a load capacitance of the SCK1 or SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1: External clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK1 cycle time tKCY10 VDD = 4.5 to 5.5 V 800 ns
1600 ns
SCK1 high, low-level tKH10 VDD = 4.5 to 5.5 V 400 ns
width tKL10 800 ns
SI1 setup time (to SCK1↑)tSIK10 100 ns
SI1 hold time (from SCK1↑)tKSI10 400 ns
SCK1↓ → SO1 output tKSO10 C = 100 pFNote 300 ns
delay time
SCK1 rise, fall time tR10 160 ns
tF10
Note C is a load capacitance of the SO1 output line.
53
µ
PD780204, 780205, 780206, 780208
TI0 - TI2
1/f
TI
t
TIL
t
TIH
X1 Input
1/f
X
t
XL
t
XH
V
IH4
(MIN.)
XT1 Input
1/f
XT
t
XTL
t
XTH
V
IL4
(MAX.)
V
IH5
(MIN.)
V
IL5
(MAX.)
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Test Points
CLOCK TIMING
TI TIMING
AC TIMING TEST POINT (EXCLUDING X1, XT1 INPUT)
54
µ
PD780204, 780205, 780206, 780208
t
SIK3.4
t
KCY3.4
t
KL3.4
t
KH3.4
SCK0
t
SBL
t
SBH
t
KSB
t
SBK
t
KSI3.4
t
KSO3.4
SB0, SB1
t
R4
t
F4
SCK0, SCK1
SI0, SI1
SO0, SO1
Input Data
Output Data
t
R2, 8
t
F2, 8
t
SIK1.2, 7, 8
t
KL1.2, 7, 8
t
KCY1.2, 7, 8
t
KH1.2, 7, 8
t
KSI1.2, 7, 8
t
KSO1.2,
7, 8
IDD vs VDD (fx = 5.0 MHz, fxx = MHz
SERIAL TRANSFER TIMING
3-wire serial I/O mode:
SBI mode (bus release signal transfer):
SBI mode (command signal transfer):
t
SIK3.4
t
KCY3.4
SCK0
t
KSB
t
SBK
t
KSI3.4
t
KSO3.4
SB0, SB1
t
KH3.4
t
KL3.4
55
µ
PD780204, 780205, 780206, 780208
2-wire serial I/O mode:
t
KSO5, 6
SCK0
SB0, SB1
t
KCY5, 6
t
KL5, 6
t
KH5, 6
t
R6
t
F6
t
KSI5, 6
t
SIK5, 6
3-wire serial I/O mode with automatic transmit/receive function:
STB
SCK1
SI1
SO1
D2 D1 D0
D2 D1 D0
D7
D7
t
SIK9, 10
t
KSI9, 10
t
KSO9, 10
t
KH9, 10
t
F10
t
R10
t
KL9, 10
t
KCY9, 10
t
SBD
t
SBW
3-wire serial I/O mode with automatic transmit/receive function (Busy processing):
t
BYH
t
SPS
t
BYS
789
Note
10
Note
10+n
Note
1SCK1
BUSY
(Active high)
Note Though it does not become low level actually, here it is described as it does due to the timing rule.
56
µ
PD780204, 780205, 780206, 780208
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 ˚C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 888bit
Total error Note 1 0.6 %
Conversion time Note 2 tCONV 1 MHz ≤ fX ≤ 5.0 MHz 19.1 200
µ
s
Sampling time Note 3 tSAMP 12/fX
µ
s
Analog input voltage VIAN AVSS AVREF V
Reference voltage AVREF 4.0 AVDD V
AVREF resistor RAVREF 414 kΩ
Notes 1. Quantization error (±1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale value.
2. Set the A/D conversion time to 19.1
µ
s or more.
3. Sampling time depends on the conversion time.
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40 to +85 ˚C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.8 5.5 V
Data retention supply current IDDDR VDDDR = 2.0 V 0.1 10
µ
A
Subsystem clock stopped,
Feedback resistor not connected
Release signal set time tSREL 0
µ
s
Oscillation stabilization tWAIT Release by RESET 217/fXms
wait time Release by interrupt Note ms
Note Selection of 212/fX, 214/fX to 217/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time
select register (OSTS).
Data retention timing (STOP mode release by RESET)
Data retention mode
RESET
V
DD
STOP mode
STOP instruction execution
V
DDDR
Operating mode
Internal reset operation
HALT mode
t
SREL
t
WAIT
57
µ
PD780204, 780205, 780206, 780208
Data retention timing (standby release signal: STOP mode release by interrupt signal)
Data retention mode
V
DD
STOP mode
STOP instruction execution
V
DDDR
Operating mode
HALT mode
t
SREL
t
WAIT
Standby release signal
(interrupt request)
Interrupt input timing
t
INTL
t
INTL
t
INTH
INTP3
INTP0 - INTP2
RESET input timing
t
RSL
RESET
58
µ
PD780204, 780205, 780206, 780208
11. CHARACTERISTIC CURVE (REFERENCE VALUE)
(1)
µ
PD780204, 780205
10.0
5.0
1.0
0.5
0.1
0.05
0.01
0.005
0.001023456789
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
f
X
= 5.0 MHz
f
XT
= 32.768 kHz
PCC = 04H
PCC = B0H
PCC = 30H, HALT 
(X1 oscillates, XT1 oscillates)
HALT (X1 stops, XT1 oscillates)
STOP (X1 stops, XT1 oscillates)
I
DD
vs. V
DD
(Main system clock: 5.0 MHz)
Supply current I
DD
[mA]
Supply voltage V
DD
[V]
(T
A
= 25 ˚C)
59
µ
PD780204, 780205, 780206, 780208
I
DD
vs. f
X
(V
DD
= 5 V, T
A
= 25 ˚C)
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
Clock oscillation frequency f
X
[MHz]
Supply current I
DD
[mA]
0 1 2 3 4 5 6
1
2
3
4
5
6
7
8
9
10
11
0
60
µ
PD780204, 780205, 780206, 780208
V
OL
vs. I
OL
(Port 1)
Low-level output current I
OL
[mA]
Low-level output voltage V
OL
[V]
(T
A
= 25 ˚C)
30
20
10
00 0.5 1.0 1.5
V
DD
= 5 V V
DD
= 4 V
V
DD
= 6 V V
DD
= 3 V
V
OL
vs. I
OL
(Ports 0, 2, 3)
Low-level output current I
OL
[mA]
Low-level output voltage V
OL
[V]
(T
A
= 25 ˚C)
30
20
10
00 0.5 1.0 1.5
V
DD
= 5 V V
DD
= 4 V
V
DD
= 6 V V
DD
= 3 V
61
µ
PD780204, 780205, 780206, 780208
V
OL
vs. I
OL
(Port 7)
Low-level output current I
OL
[mA]
Low-level output voltage V
OL
[V]
(T
A
= 25 ˚C)
30
20
10
00 0.5 1.0 1.5
V
DD
= 5 V V
DD
= 4 V
V
DD
= 6 V V
DD
= 3 V
62
µ
PD780204, 780205, 780206, 780208
VDD – VOH vs. IOH (Port 8 - Port 12)
High-level output current IOH [mA]
High-level output voltage VDD – VOH [V]
(TA = 25 ˚C)
–30
–20
–10
00 1.0 2.0 3.0
VDD = 5 V
VDD = 4 V
VDD = 6 V
VDD = 3 V
VDD – VOH vs. IOH (Port 0 - Port 3)
High-level output current IOH [mA]
High-level output voltage VDD – VOH [V]
(TA = 25 ˚C)
–10
–5
00 0.5 1.0 1.5
VDD = 4 V
VDD = 3 V
V
DD
= 6 V
VDD = 5 V
63
µ
PD780204, 780205, 780206, 780208
(2)
µ
PD780206, 780208
10.0
5.0
1.0
0.5
0.1
0.05
0.01
0.005
0.0010 2 3 4 5 6 7 8 9
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
f
X
= 5.0 MHz
f
XT
= 32.768 kHz
PCC = 04H
PCC = B0H
PCC = 30H, HALT 
(X1 oscillates, XT1 oscillates)
I
DD
vs. V
DD
(Main system clock: 5.0 MHz)
Supply current I
DD
[mA]
Supply voltage V
DD
[V]
(T
A
= 25 ˚C)
64
µ
PD780204, 780205, 780206, 780208
I
DD
vs. f
X
(V
DD
= 5 V, T
A
= 25 ˚C)
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
Clock oscillation frequency f
X
[MHz]
Supply current I
DD
[mA]
0 1 2 3 4 5 6
1
2
3
4
5
6
7
8
9
10
11
0
65
µ
PD780204, 780205, 780206, 780208
V
OL
vs. I
OL
(Port 1)
Low-level output current I
OL
[mA]
Low-level output voltage V
OL
[V]
(T
A
= 25 ˚C)
30
20
10
00 0.5 1.0 1.5
V
DD
= 5 VV
DD
= 4 V
V
DD
= 6 V V
DD
= 3 V
V
OL
vs. I
OL
(Ports 0, 2, 3)
Low-level output current I
OL
[mA]
Low-level output voltage V
OL
[V]
(T
A
= 25 ˚C)
30
20
10
00 0.5 1.0 1.5
V
DD
= 5 V V
DD
= 4 V
V
DD
= 6 V V
DD
= 3 V
66
µ
PD780204, 780205, 780206, 780208
V
OL
vs. I
OL
(Port 7)
Low-level output current I
OL
[mA]
Low-level output voltage V
OL
[V]
(T
A
= 25 ˚C)
30
20
10
00 0.5 1.0 1.5
V
DD
= 5 V V
DD
= 4 V
V
DD
= 6 V
V
DD
= 3 V
67
µ
PD780204, 780205, 780206, 780208
VDD – VOH vs. IOH (Port 8 - Port 12)
High-level output current IOH [mA]
High-level output voltage VDD – VOH [V]
(TA = 25 ˚C)
–30
–20
–10
00 1.0 2.0 3.0
VDD = 5 V VDD = 4 V
V
DD
= 6 V
VDD = 3 V
VDD – VOH vs. IOH (Port 0 - Port 3)
High-level output current IOH [mA]
High-level output voltage VDD – VOH [V]
(TA = 25 ˚C)
–10
–5
00 0.5 1.0 1.5
V
DD
= 6 V
VDD = 5 V
VDD = 3 V
V
DD
= 4 V
68
µ
PD780204, 780205, 780206, 780208
12. PACKAGE DRAWING
Remark The dimensions and materials of the ES model are the same as the mass-produced model.
J
N
M
P
80
81 50
100 PIN PLASTIC QFP (14 × 20)
100
131
30
51
G
detail of lead end
S
5°±5°
C
D
A
B
H
Q
K
L
F
M
I
P100GF-65-3BA1-2
ITEM MILLIMETERS INCHES
A
B
C
D
F
G
H
I
J
K
L
23.6±0.4
14.0±0.2
0.6
0.30±0.10
0.15
20.0±0.2
0.929±0.016
0.031
0.024
0.006
0.026 (T.P.)
0.795
NOTE
M
N0.10
0.15
1.8±0.2
0.65 (T.P.)
0.006
0.031+0.009
–0.008
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
0.012
0.551
0.8±0.2
0.071
P 2.7 0.106
0.693±0.016
17.6±0.4
0.8
+0.008
–0.009
Q0.1±0.1 0.004±0.004
S 3.0 MAX. 0.119 MAX.
+0.10
–0.05
+0.009
–0.008
+0.004
–0.005
+0.009
–0.008
+0.004
–0.003
0.004
69
µ
PD780204, 780205, 780206, 780208
13. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the
µ
PD780204, 780205, 780206, and 780208.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 13-1. Soldering Conditions for Surface-Mount Type
µ
PD780204GF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)
µ
PD780205GF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)
µ
PD780206GF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)
µ
PD780208GF-×××-3BA: 100-pin plastic QFP (14 × 20 mm)
Soldering Method Soldering Conditions Recommended
Condition Symbol
Infrared reflow Package peak temperature: 235 ˚C, Duration: 30 sec. max. (at 210 ˚C or above), IR35-00-3
Number of times: Thrice max.
VPS Package peak temperature: 215 ˚C, Duration: 40 sec. max. (at 200 ˚C or above), VP15-00-3
Number of times: Thrice max.
Wave soldering Solder bath temperature: 260 ˚C max. Duration: 10 sec. max. WS60-00-1
Number of times: Once
Preliminary heat temperature: 120 ˚C max. (Package surface temperature)
Partial heating Pin temperature: 300 ˚C max., Duration: 3 sec. max. (per device side) —
Caution Using more than one soldering method should be avoided (except in the case of partial heating).
70
µ
PD780204, 780205, 780206, 780208
APPENDIX A. DEVELOPMENT TOOLS
The following tools are available for development of systems using the
µ
PD780204, 780205, 780206, and 780208:
Language Processing Software
RA78K/0Note 1, 2, 3, 4 Assembler package common to 78K/0 series
CC78K/0Note 1, 2, 3, 4 C compiler package common to 78K/0 series
DF780208Note 1, 2, 3, 4 Device file for
µ
PD780208 subseries
CC78K/0-LNote 1, 2, 3, 4 C compiler library source file common to 78K/0 series
PROM Writing Tools
PG-1500 PROM programmer
PA-78P0208GF Programmer adapter connectd to PG-1500
PA-78P0208KL-T
PG-1500 ControllerNote 1, 2 Control program for PG-1500
Debugging Tools
IE-78000-R In-circuit emulator common to 78K/0 series
IE-78000-R-A In-circuit emulator common to 78K/0 series (for integrated debugger)
IE-78000-R-BK Break board common to 78K/0 series
IE-780208-R-EM Emulation board for evaluating
µ
PD780208 subseries
EP-78064GF-R Emulation probe common to
µ
PD78064 subseries
EV-9200GF-100
Socket mounted to target system created for 100-pin plastic QFP (GF-3BA type)
SM78K0
Note 5, 6, 7
System simulator common to 78K/0 series
ID78K0Note 4, 5, 6, 7 Integrated debugger for IE-78000-R-A
SD78K/0Note 1, 2 Screen debugger for IE-78000-R
DF780208Note 1, 2, 4, 5, 6, 7 Device file for
µ
PD780208 subseries
Real-time OS
RX78K/0Note 1, 2, 3, 4 Real-time OS for 78K/0 series
MX78K0Note 1, 2, 3, 4 OS for 78K/0 series
Notes 1. PC-9800 series (MS-DOSTM) based
2. IBM PC/ATTM and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 series 300TM (HP-UXTM) based
4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (Sun OSTM) based, EWS4800 series (EWS-UX/V)
based
5. PC-9800 series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party
development tools.
2.
RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF780208.
71
µ
PD780204, 780205, 780206, 780208
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note 3 Fuzzy knowledge data creation tool
FT9080Note 1/FT9085Note 2 Translator
FI78K0Note 1, 2 Fuzzy inference module
FD78K0Note 1, 2 Fuzzy inference debugger
Notes 1. PC-9800 series (MS-DOS) based
2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based
3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
Remark Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party development
tools.
72
µ
PD780204, 780205, 780206, 780208
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name Document No.
Japanese English
µ
PD780208 subseries user’s manual U11302J U11302E
µ
PD780204, 780205, 780206, 780208 data sheet U10436J This document
µ
PD78P0208 data sheet U11295J U11295E
µ
PD780208 subseries special function register list U10997J —
78K/0 series user’s manual - instruction IEU-849 IEU-1372
78K/0 series instruction list U10903J —
78K/0 series instruction set U10904J —
78K/0 series application note - Basic (II) U10121J U10121E
Caution The documents listed above are subject to change without notice. Be sure to use the latest
documents for designing your system.
73
µ
PD780204, 780205, 780206, 780208
Development Tool Documents (User’s Manual)
Document Name Document No.
Japanese English
RA78K series assembler package Operation EEU-809 EEU-1399
Language EEU-815 EEU-1404
RA78K0 assembler package Operation U11802J U11802E
Assembly language U11801J U11801E
Structured assembly U11789J U11789E
language
RA78K series structured assembler preprocessor EEU-817 EEU-1402
CC78K series C compiler Operation EEU-656 EEU-1280
Language EEU-655 EEU-1284
CC78K0 C compiler Operation U11517J U11517E
Language U11518J U11518E
CC78K series library source file EEU-777 —
CC78K/0 C compiler application note
Programming know-how
EEA-618 EEA-1208
PG-1500 PROM programmer EEU-651 EEU-1335
PG-1500 controller PC-9800 series (MS-DOS) base EEU-704 EEU-1291
PG-1500 controller IBM PC series (PC DOS) base EEU-5008 U10540E
IE-78000-R EEU-810 U11376E
IE-78000-R-A U10057J U10057E
IE-78000-R-BK EEU-867 EEU-1427
IE-780208-R-EM EEU-977 EEU-1501
EP-78064 EEU-934 EEU-1469
SM78K0 system simulator Reference U10181J U10181E
SM78K series system simulator
External parts user-open
U10092J U10092E
interface specification
SD78K/0 screen debugger PC-9800 series (MS-DOS) base
Introduction EEU-852 U10539E
Reference U10952J —
SD78K/0 screen debugger IBM PC/AT (PC DOS) base
Introduction EEU-5024 EEU-1414
Reference U11279J U11279E
ID78K0 integrated debugger EWS based Reference U11151J —
ID78K0 integrated debugger PC based Reference U11539J U11539E
ID78K0 integrated debugger Windows based Guide U11649J U11649E
Caution The documents listed above are subject to change without notice. Be sure to use the latest
documents for designing your system.
74
µ
PD780204, 780205, 780206, 780208
Documents Related to Embedded Software (User’s Manual)
Document Name Document No.
Japanese English
Fundamental U11537J —
78K/0 series real-time OS Installation U11536J —
Technical U11538J —
78K/0 series OS MX78K0 Fundamental EEU-5010 —
Fuzzy knowledge data creation tool EEU-829 EEU-1438
78K/0, 78K/II, 87AD series fuzzy inference development suppport system - EEU-862 EEU-1444
translator
78K/0 series fuzzy inference development support system - fuzzy inference EEU-858 EEU-1441
module
78K/0 series fuzzy inference development support system - fuzzy inference EEU-921 EEU-1458
debugger
Other Related Documents
Document Name Document No.
Japanese English
IC package manual C10943X
Semiconductor device mounting technology manual C10535J C10535E
Quality grade on NEC semiconductor devices C11531J C11531E
NEC semiconductor device reliability/quality control system C10983J C10983E
Static electricity discharge (ESD) test MEM-539 —
Semiconductor device quality guarantee guide C11893J MEI-1202
Product guide related to microcomputer - other manufacturers U11416J —
Caution The documents listed above are subject to change without notice. Be sure to use the latest
documents for designing your system.
75
µ
PD780204, 780205, 780206, 780208
[MEMO]
76
µ
PD780204, 780205, 780206, 780208
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
77
µ
PD780204, 780205, 780206, 780208
NEC Electronics Inc. (U.S.)
Mountain View, California
Tel: 800-366-9782
Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel:2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel:253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel:040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
France
Tel:01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby Sweden
Tel: 8-63 80 820
Fax: 8-63 80 388
Regional Inf ormation
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J96. 3
78
µ
PD780204, 780205,780206, 780208
The documents referred to in this publication may include preliminary versions. However, preliminary versions are not
marked as such.
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5