MT9JBF25672AKIZ-1G4K1 - Micron Technology Inc.

DDR3 SDRAM ULP Mini-UDIMM

MT9JBF25672AKZ – 2GB

Features

• DDR3 functionality and operations supported as

defined in the component data sheet

• 244-pin, ultra-low profile, 17.9mm, mini-unbuffered

dual in-line memory module (ULP Mini-UDIMM)

• Fast data transfer rates: PC3-12800, PC3-10600,

PC3-8500, or PC3-6400

• 2GB (256 Meg x 72)

• VDD = 1.5V ±0.075V

• VDDSPD = 3.0–3.6V

• Supports ECC error detection and correction

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Single-rank

• On-board I2C temperature sensor with integrated

serial presence-detect (SPD) EEPROM

• 8 internal device banks

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• Selectable BC4 or BL8 on-the-fly (OTF)

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

Figure 1: 244-Pin ULP Mini-UDIMM

Module height: 17.9mm (0.705in)

Options Marking

• Operating temperature

– Commercial (0°C ≤ TA ≤ +70°C) None

– Industrial (–40°C ≤ TA ≤ +85°C)1I

• Package

– 244-pin halogen-free ULP Mini-

UDIMM

• Frequency/CAS latency

– 1.25ns @ CL = 11 (DDR3-1600) -1G6

– 1.5ns @ CL = 9 (DDR3-1333) -1G4

– 1.87ns @ CL = 7 (DDR3-1066) -1G1

Note: 1. Contact Micron for industrial temperature

module offerings.

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s) tRCD

(ns)

tRP

(ns)

tRC

(ns)CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5

-1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125

-1G4 PC3-10600 – 1333 1333 1066 1066 800 667 13.125 13.125 49.125

-1G1 PC3-8500 – – – 1066 1066 800 667 13.125 13.125 50.625

-1G0 PC3-8500 – – – 1066 – 800 667 15 15 52.5

-80B PC3-6400 – – – – – 800 667 15 15 52.5

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 2GB

Refresh count 8K

Row address 32K A[14:0]

Device bank address 8 BA[2:0]

Device configuration 2Gb (256 Meg x 8)

Column address 1K A[9:0]

Module rank address 1 S0#

Table 3: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41J256M8,1 2Gb DDR3 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT9JBF25672AK(I)Z-1G6__ 2GB 256 Meg x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT9JBF25672AK(I)Z-1G4__ 2GB 256 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

MT9JBF25672AK(I)Z-1G1__ 2GB 256 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Notes: 1. The data sheet for the base device can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT9JBF25672AKZ-1G4K1.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Features

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Pin Assignments

Table 4: Pin Assignments

244-Pin DDR3 Mini-UDIMM Front 244-Pin DDR3 Mini-UDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VTT 31 DQ24 61 VDD 92 DQ40 123 VTT 153 DQ29 183 A3 214 DQ45

2 VREFDQ 32 DQ25 62 A2 93 DQ41 124 VSS 154 VSS 184 A1 215 VSS

3 VSS 33 VSS 63 VDD 94 VSS 125 DQ4 155 DM3 185 VDD 216 DM5

4 DQ0 34 DQS3# 64 CK1 95 DQS5# 126 DQ5 156 NC 186 CK0 217 NC

5 DQ1 35 DQS3 65 CK1# 96 DQS5 127 VSS 157 VSS 187 CK0# 218 VSS

6 VSS 36 VSS 66 VDD 97 VSS 128 DM0 158 DQ30 188 VDD 219 DQ46

7 DQS0# 37 DQ26 67 VREFCA 98 DQ42 129 NC 159 DQ31 189 VDD 220 DQ47

8 DQS0 38 DQ27 68 VDD 99 DQ43 130 VSS 160 VSS 190 EVENT# 221 VSS

9 VSS 39 VSS 69 NC 100 VSS 131 DQ6 161 CB4 191 A0 222 DQ52

10 DQ2 40 CB0 70 VDD 101 DQ48 132 DQ7 162 CB5 192 VDD 223 DQ53

11 DQ3 41 CB1 71 A10 102 DQ49 133 VSS 163 VSS 193 BA1 224 VSS

12 VSS 42 VSS 72 BA0 103 VSS 134 DQ12 164 DM8 194 VDD 225 DM6

13 DQ8 43 DQS8# 73 VDD 104 DQS6# 135 DQ13 165 NC 195 RAS# 226 NC

14 DQ9 44 DQS8 74 WE# 105 DQS6 136 VSS 166 VSS 196 CS0# 227 VSS

15 VSS 45 VSS 75 CAS# 106 VSS 137 DM1 167 CB6 197 VDD 228 DQ54

16 DQS1# 46 CB2 76 VDD 107 DQ50 138 NC 168 CB7 198 ODT0 229 DQ55

17 DQS1 47 CB3 77 NC 108 DQ51 139 VSS 169 VSS 199 A13 230 VSS

18 VSS 48 VSS 78 NC 109 VSS 140 DQ14 170 NC 200 VDD 231 DQ60

19 DQ10 49 NC 79 VDD 110 DQ56 141 DQ15 171 NC 201 NC 232 DQ61

20 DQ11 50 RESET# 80 NC 111 DQ57 142 VSS 172 NC 202 NC 233 VSS

21 VSS 51 CKE0 81 NC 112 VSS 143 DQ20 173 VDD 203 VSS 234 DM7

22 DQ16 52 VDD 82 VSS 113 DQS7# 144 DQ21 174 NC 204 DQ36 235 NC

23 DQ17 53 BA2 83 DQ32 114 DQS7 145 VSS 175 A14 205 DQ37 236 VSS

24 VSS 54 NC 84 DQ33 115 VSS 146 DM2 176 VDD 206 VSS 237 DQ62

25 DQS2# 55 VDD 85 VSS 116 DQ58 147 NC 177 A12 207 DM4 238 DQ63

26 DQS2 56 A11 86 DQS4# 117 DQ59 148 VSS 178 A9 208 NC 239 VSS

27 VSS 57 A7 87 DQS4 118 VSS 149 DQ22 179 VDD 209 VSS 240 VDDSPD

28 DQ18 58 VDD 88 VSS 119 SA0 150 DQ23 180 A8 210 DQ38 241 SA1

29 DQ19 59 A5 89 DQ34 120 SCL 151 VSS 181 A6 211 DQ39 242 SDA

30 VSS 60 A4 90 DQ35 121 SA2 152 DQ28 182 VDD 212 VSS 243 VSS

91 VSS 122 VTT 213 DQ44 244 VTT

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Pin Assignments

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Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 5: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments Table for density-specific

addressing information.

BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command.

CKx,

CKx#

Input Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DRAM.

DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input

(LVCMOS)

Reset: RESET# is an active LOW asychronous input that is connected to each DRAM

and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-

ized as though a normal power-up was executed.

Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-

dress range on the I2C bus.

SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-

cation to and from the temperature sensor/SPD EEPROM on the I2C bus.

CBx I/O Check bits: Used for system error detection and correction.

DQx I/O Data input/output: Bidirectional data bus.

DQSx,

DQSx#

I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with

read data; input with write data; center-aligned with write data.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Pin Descriptions

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Table 5: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sen-

sor/SPD EEPROM on the I2C bus.

TDQSx,

TDQSx#

Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD

MODE command to the extended mode register (EMR). When TDQS is enabled, DM is

disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are

no function.

Err_Out# Output

(open drain)

Parity error output: Parity error found on the command and address bus.

EVENT# Output

(open drain)

Temperature event:The EVENT# pin is asserted by the temperature sensor when criti-

cal temperature thresholds have been exceeded.

VDD Supply Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the

module VDD.

VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.

VREFCA Supply Reference voltage: Control, command, and address VDD/2.

VREFDQ Supply Reference voltage: DQ, DM VDD/2.

VSS Supply Ground.

VTT Supply Termination voltage: Used for control, command, and address VDD/2.

NC – No connect: These pins are not connected on the module.

NF – No function: These pins are connected within the module, but provide no functional-

ity.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Pin Descriptions

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DQ Map

Table 6: Component-to-Module DQ Map

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U1 0 6 131 U2 0 18 28

1 1 5 1 21 144

2 3 11 2 23 150

3 5 126 3 17 23

4 2 10 4 22 149

5 4 125 5 16 22

6 7 132 6 19 29

7 0 4 7 20 143

U4 8 34 89 U5 0 50 107

9 37 205 1 53 223

10 39 211 2 55 229

11 33 84 3 49 102

12 38 210 4 54 228

13 32 83 5 48 101

14 35 90 6 51 108

15 36 204 7 52 222

U6 0 61 232 U7 0 45 214

1 62 237 1 46 219

2 56 110 2 40 92

3 59 117 3 43 99

4 60 231 4 44 213

5 63 238 5 47 220

6 57 111 6 41 93

7 58 116 7 42 98

U8 0 CB0 40 U9 0 29 153

1 CB1 41 1 30 158

2 CB2 46 2 24 31

3 CB3 47 3 27 38

4 CB4 161 4 28 152

5 CB5 162 5 31 159

6 CB6 167 6 25 32

7 CB7 168 7 26 37

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

DQ Map

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Table 6: Component-to-Module DQ Map (Continued)

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U10 0 9 14

1 14 140

2 12 134

3 11 20

4 8 13

5 15 141

6 13 135

7 10 19

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

DQ Map

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Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQ DQS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM CS# DQ DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

U10

DM CS# DQ DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM CS# DQ DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM CS# DQ DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM CS# DQ DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM CS# DQ DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM CS# DQ DQS#

DQS0#

DQS0

DM0

S0#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM CS# DQ DQS#

DQS8#

DQS8

DM8

BA[2:0]

A[14:0]

RAS#

CAS#

WE#

CKE0

ODT0

RESET#

BA[2:0]: DDR3 SDRAM

A[14:0]: DDR3 SDRAM

RAS#: DDR3 SDRAM

CAS#: DDR3 SDRAM

WE#: DDR3 SDRAM

CKE0: DDR3 SDRAM

ODT0: DDR3 SDRAM

RESET#: DDR3 SDRAM

DDR3 SDRAM X 9

CK0

CK0#

CK1

CK1#

VREFCA

VSS

DDR3 SDRAM

VDD

Control, command,

and address termination

VDDSPD

Temperature Sensor/

SPD EEPROM

VTT

DDR3 SDRAM

VREFDQ

Clock, control, command, and address line terminations:

CKE0, A[14:0],

RAS#, CAS#, WE#,

ODT0, BA[2:0], S0#

DDR3

SDRAM

VTT

CK#

DDR3

SDRAM

VDD

VSS

Temperature

sensor/

SPD EEPROM

A1 A2

SA0 SA1

SDA

SCL

EVT

EVENT#

SA2

Note: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor

that is tied to ground. It is used for the calibration of the component’s ODT and output

driver.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Functional Block Diagram

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General Description

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-

ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-

tially an 8n-prefetch architecture with an interface designed to transfer two data words

per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-

ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-

nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers

at the I/O pins.

DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals.

Fly-By Topology

DDR3 modules use faster clock speeds than earlier DDR technologies, making signal

quality more important than ever. For improved signal quality, the clock, control, com-

mand, and address buses have been routed in a fly-by topology, where each clock, con-

trol, command, and address pin on each DRAM is connected to a single trace and ter-

minated (rather than a tree structure, where the termination is off the module near the

connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-

nals can be easily accounted for by using the write-leveling feature of DDR3.

Temperature Sensor with Serial Presence-Detect EEPROM

Thermal Sensor Operations

The temperature from the integrated thermal sensor is monitored and converts into a

digital word via the I2C bus. System designers can use the user-programmable registers

to create a custom temperature-sensing solution based on system requirements. Pro-

gramming and configuration details comply with JEDEC standard No. 21-C page 4.7-1,

"Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor."

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JE-

DEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Mod-

ules." These bytes identify module-specific timing parameters, configuration informa-

tion, and physical attributes. The remaining 128 bytes of storage are available for use by

the customer. System READ/WRITE operations between the master (system logic) and

the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock)

SDA (data), and SA (address) pins. Write protect (WP) is connected to VSS, permanently

disabling hardware write protection. For further information refer to Micron technical

note TN-04-42, "Memory Module Serial Presence-Detect."

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

General Description

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in each device's data sheet is not implied. Exposure to ab-

solute maximum rating conditions for extended periods may adversely affect reliability.

Table 7: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.4 1.975 V

VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V

Table 8: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.425 1.5 1.575 V

VREFCA(DC) Input reference voltage command/address bus 0.49 × VDD 0.5 ×

VDD

0.51 × VDD V

VREFDQ(DC) I/O reference voltage DQ bus 0.49 × VDD 0.5 ×

VDD

0.51 × VDD V

IVTT Termination reference current from VTT –600 – +600 mA

VTT Termination reference voltage (DC) –

command/address bus

0.49 × VDD -

20mV

0.5 ×

VDD

0.51 × VDD +

20mV

V 1

IIInput leakage current;

Any input 0V ≤ VIN ≤ VDD; VREF in-

put 0V ≤ VIN ≤ 0.95V (All other pins

not under test = 0V)

Address

inputs,

RAS#,CAS#,

WE#, S#,

CKE, ODT,

BA, CK, CK#

–18 0 18 µA

DM –2 0 2

IOZ Output leakage current;

0V ≤ VOUT ≤ VDD; DQ and ODT are

disabled; ODT is HIGH

DQ, DQS,

DQS#

–5 0 5 µA

IVREF VREF supply leakage current;

VREFDQ = VDD/2 or VREFCA = VDD/2

(All other pins not under test = 0V)

–9 0 9 µA

TAModule ambient operating tem-

perature

Commercial 0 – 70 °C 2, 3

Industrial –40 – 85

TCDDR3 SDRAM component case op-

erating temperature

Commercial 0 – 85 °C 2, 3, 4

Industrial –40 – 95

Notes: 1. VTT termination voltage in excess of the stated limit will adversely affect the command

and address signals’ voltage margin and will reduce timing margins.

2. TA and TC are simultaneous requirements.

3. For further information, refer to technical note TN-00-08: “Thermal Applications,”

available on Micron’s Web site.

4. The refresh rate is required to double when 85°C < TC ≤ 95°C.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Electrical Specifications

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DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR3 component data sheets.

Component specifications are available on Micron’s web site. Module speed grades cor-

relate with component speed grades, as shown below.

Table 9: Module and Component Speed Grades

DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-2G1 -093

-1G9 -107

-1G6 -125

-1G4 -15E

-1G1 -187E

-1G0 -187

-80C -25E

-80B -25

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to simulate the signal characteristics of the system's

memory bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

DRAM Operating Conditions

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IDD Specifications

Table 10: DDR3 IDD Specifications and Conditions – 2GB (Die Revision D)

Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-

ponent data sheet.

Parameter Symbol 1600 1333 1066 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 855 765 675 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRE-

CHARGE

IDD1 945 900 855 mA

Precharge power-down current: Slow exit IDD2P0 108 180 108 mA

Precharge power-down current: Fast exit IDD2P1 315 270 225 mA

Precharge quiet standby current IDD2Q 360 315 270 mA

Precharge standby current IDD2N 378 333 288 mA

Precharge standby ODT current IDD2NT 450 405 360 mA

Active power-down current IDD3P 360 315 270 mA

Active standby current IDD3N 405 360 315 mA

Burst read operating current IDD4R 1620 1440 1260 mA

Burst write operating current IDD4W 1665 1485 1305 mA

Refresh current IDD5B 1935 1800 1710 mA

Self refresh temperature current: MAX TC = 85°C IDD6 108 108 108 mA

Self refresh temperature current (SRT-enabled):

MAX TC = 95°C

IDD6ET 135 135 135 mA

All banks interleaved read current IDD7 3915 3465 3015 mA

Reset current IDD8 126 126 126 mA

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

IDD Specifications

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Table 11: DDR3 IDD Specifications and Conditions – 2GB (Die Revision K)

Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) com-

ponent data sheet.

Parameter Symbol 1600 1333 1066 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 378 369 351 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRE-

CHARGE

IDD1 504 486 450 mA

Precharge power-down current: Slow exit IDD2P0 108 108 108 mA

Precharge power-down current: Fast exit IDD2P1 135 135 135 mA

Precharge quiet standby current IDD2Q 198 198 198 mA

Precharge standby current IDD2N 207 207 207 mA

Precharge standby ODT current IDD2NT 306 288 261 mA

Active power-down current IDD3P 198 198 198 mA

Active standby current IDD3N 315 297 279 mA

Burst read operating current IDD4R 900 792 675 mA

Burst write operating current IDD4W 927 819 711 mA

Refresh current IDD5B 1638 1629 1611 mA

Self refresh temperature current: MAX TC = 85°C IDD6 108 108 108 mA

Self refresh temperature current (SRT-enabled):

MAX TC = 95°C

IDD6ET 135 135 135 mA

All banks interleaved read current IDD7 1467 1413 1152 mA

Reset current IDD8 126 126 126 mA

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

IDD Specifications

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Temperature Sensor with Serial Presence-Detect EEPROM

The temperature sensor continuously monitors the module's temperature and can be

read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC

standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with

Temperature Sensor."

Serial Presence-Detect

For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.

Table 12: Temperature Sensor with SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 3.0 3.6 V

Supply current: VDD = 3.3V IDD – 2.0 mA

Input high voltage: Logic 1; SCL, SDA VIH VDDSPD x 0.7 VDDSPD + 1 V

Input low voltage: Logic 0; SCL, SDA VIL –0.5 VDDSPD x 0.3 V

Output low voltage: IOUT = 2.1mA VOL – 0.4 V

Input current IIN –5.0 5.0 µA

Temperature sensing range – –40 125 °C

Temperature sensor accuracy (class B) – –1.0 1.0 °C

Table 13: Temperature Sensor and SPD EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Time bus must be free before a new transition can

start

tBUF 4.7 – µs

SDA fall time tF 20 300 ns

SDA rise time tR – 1000 ns

Data hold time tHD:DAT 200 900 ns

Start condition hold time tH:STA 4.0 – µs

Clock HIGH period tHIGH 4.0 50 µs

Clock LOW period tLOW 4.7 – µs

SCL clock frequency tSCL 10 100 kHz

Data setup time tSU:DAT 250 – ns

Start condition setup time tSU:STA 4.7 – µs

Stop condition setup time tSU:STO 4.0 – µs

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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EVENT# Pin

The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD

EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be

set up in the sensor’s configuration register.

EVENT# has three defined modes of operation: interrupt mode, compare mode, and

critical temperature mode. Event thresholds are programmed in the 0x01 register using

a hysteresis. The alarm window provides a comparison window, with upper and lower

limits set in the alarm upper boundary register and the alarm lower boundary register,

respectively. When the alarm window is enabled, EVENT# will trigger whenever the

temperature is outside the MIN or MAX values set by the user.

The interrupt mode enables software to reset EVENT# after a critical temperature

threshold has been detected. Threshold points are set in the configuration register by

the user. This mode triggers the critical temperature limit and both the MIN and MAX of

the temperature window.

The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by

the user and returns to the logic HIGH state only when the temperature falls below the

programmed thresholds.

Critical temperature mode triggers EVENT# only when the temperature has exceeded

the programmed critical trip point. When the critical trip point has been reached, the

temperature sensor goes into comparator mode, and the critical EVENT# cannot be

cleared through software.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Temperature Sensor with Serial Presence-Detect EEPROM

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Module Dimensions

Figure 3: 244-Pin DDR3 ULP Mini-UDIMM

82.15 (3.234)

81.85 (3.222)

Front view

17.91 (0.705)

17.89 (0.704)

10.0 (0.394)

TYP

1.0 (0.039)

TYP

45° X4

1.0 (0.039) R

0.5 (0.02) R

1.8 (0.071) D

6.0 (0.236)

TYP

2.0 (0.079)

TYP

78.0 (3.071)

TYP

0.6 (0.024)

TYP

0.45 (0.018)

TYP

Pin 1 Pin 122

43.9 (1.73)

TYP

Back view

3.3 (0.13)

TYP

3.6 (0.142) TYP

33.6 (1.323)

TYP

38.4 (1.512)

TYP

3.2 (0.126)

TYP

3.80 (0.15)

MAX

1.1 (0.043)

0.9 (0.035)

Pin 244 Pin 123

U1 U2

U4 U5

U6 U7 U8 U9 U10

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

2GB (x72, ECC, SR) 244-Pin DDR3 SDRAM ULP Mini-UDIMM

Module Dimensions

PDF: 09005aef83e0c154

jbf9c256x72akz.pdf - Rev. F 5/13 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.