K4C89183AF
- 1 - REV. 0.7 Jan. 2005
288Mb x18 Network-DRAM2 Specification
Version 0.7
K4C89183AF
- 2 - REV. 0.7 Jan. 2005
Revision History
Version 0.0 (Oct. 2002)
- First Release
Version 0.01 (Nov. 2002)
- Changed die revision from D-die to F-die
- Corrected typo
- Corrected DQS to DS and QS(DQS -> DS and QS) in AC timing table and timing diagram.
Version 0.1 (Apr. 2003)
- Added 800Mbps(400Mhz) product
- Changed operating temperature from Ta to Tc.
- Changed capacitance of ADDR/CMD/CLK
- Changed tDSS(DS input Falling Edge to Clock Setup Time)
- Added CL7 for 800Mbps
- Deleted TSOP package outline
Version 0.11 (Apr. 2003)
- Corrected typo in page 3.(Deleted bi-directional strobe)
- Corrected min. Vref to VDDQ/2x95% in page 7
Version 0.2 (Aug. 2003)
- Added package physical dimension
- Extracted 800Mbps(G7) binning from target spec ( G7 will be added in the future)
- Changed DC test condition
- Changed low frequency spec like below
- Changed AC test load picture
Version 0.3 (Nov. 2003)
- Changed Packge type from die-exposed to full molded
- Changed Package code in Partnumber
From To
Min Max Min Max
Addr/CMD/CLK 1.5 2.5 1.5 3.0
From To
F6 FB F5 G7 F6 FB F5
CL4 0.9 0.9 1.0 0.75 0.75 0.8 1.0
CL5 0.9 0.9 1.0 0.75 0.75 0.8 1.0
CL6 0.9 0.9 1.0 0.75 0.75 0.8 1.0
CL7 - - - 0.75 - - -
From To Changed point
IDD1S,IDD2N,IDD2P,IDD5,IDD6 IDD1S,IDD2N,IDD2P,IDD5B,IDD6 Changed condition
- IDD4W, IDD4R newly inserted
From To
Unit : ns F6 FB F5 F6 FB F5
tCK max@CL=4 7.5 7.5 7.5 6.0 6.0 6.0
tCK max@CL=5 7.5 7.5 7.5 6.0 6.0 6.0
tCK max@CL=6 7.5 7.5 7.5 6.0 6.0 6.0
K4C89183AF
- 3 - REV. 0.7 Jan. 2005
Version 0.31 (Mar., 2004)
- Corrected typo. in page 7 (Changed operating Temperature to 85’C, case temperature)
Version 0.4 (Jun., 2004)
- Changed from "target" to "Preliminary"
- Changed min. tCK@CL5 to 3.5ns in "-F6"
Version 0.5 (Aug., 2004)
- Deleted self-refresh function and BL2 from spec
Version 0.51 (Aug., 2004)
- Corrected error in page 54, "Package Out line Drawing". (Just 4 balls were missing in drawing)
Version 0.6 (Nov., 2004)
- Deleted "preliminary"
- Changed current value in page 9
Version 0.7 (Jan., 2005)
- Deleted the tDQSQA in page 11
- Deleted the tSSK in page 11
From To
F6 F6
tCK Clock Cycle Time (min) CL = 4 4.0 ns 4.0 ns
CL = 5 3.33 ns 3.5 ns
CL = 6 3.0ns 3.0ns
K4C89183AF
- 4 - REV. 0.7 Jan. 2005
4,194,304-WORDS x 4 BANKS x 18-BITS DOUBLE DATA RATE Network-DRAM
DESCRIPTION
K4C89183AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89183AF is organized as
4,194,304-words x 4 banks x18 bits. K4C89183AF feature a fully synchronous operation referenced to clock edge whereby all opera-
tions are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89183AF can oper-
ate fast core cycle compared with regular DDR SDRAM.
K4C89183AF is suitable for Server, Network and other applications where large memory density and low power consumption are
required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition.
FEATURES
Parameter K4C89183AF
F6 FB F5
tCK Clock Cycle Time (min) CL = 4 4.0 ns 4.5 ns 5.0 ns
CL = 5 3.5 ns 3.75 ns 4.5 ns
CL = 6 3.0ns 3.33 ns 4.0 ns
tRC Random Read/Write Cycle Time (min) 20.0 ns 22.5 ns 25 ns
tRAC Random Access Time (min) 20.0 ns 22.5 ns 25 ns
IDD1S Operating Current (single bank) (max) 320mA 300mA 280mA
IDD2P Power Down Current (max) 70mA 65mA 60mA
• Fully Synchronous Operation
- Double Data Rate (DDR)
- Data input/output are synchronized with both edges of DS / QS.
- Differential Clock (CLK and CLK) inputs
- CS, FN and all address input signals are sampled on the positive edge of CLK.
- Output data (DQs and QS) is aligned to the crossings of CLK and CLK.
• Fast clock cycle time of 3.0 ns minimum
- Clock : 333 MHz maximum
- Data : 666 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Uni-directional Data St robe
• Distributed Auto-Refresh cycle in 3.9us
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
- CAS Laatency = 4, 5, 6
- Burst Length = 4
• Organization : 4,194,304 words x 4 banks x 18 bits
• Power Supply Voltage VDD : 2.5V ± 0.125V
• VDDQ : 1.4V ∼ 1.9V
• 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) and HSTL
• Package : 60Ball BGA, 1.0mm x 1.0mm Ball pitch
• Notice : Network-DRAM is tradema rk of Samsung Electronics., Co LTD
K4C89183AF
- 5 - REV. 0.7 Jan. 2005
Pin Names
Pin Name
A0 ~ A14 Address Input
BA0, BA1 Bank Address
DQ0 ~ DQ17 Data Input/Output
CS Chip Select
FN Function Control
PD Power Down Control
CLK, CLK Clock Input
DS/QS Write/Read data strobe
VDD Power (+2.5V)
VSS Ground
VDDQ Power (+1.8V)
(for I/O buffer)
VSSQ Ground
(for I/O buffer)
VREF Reference Voltage
NC No Connection
ball pitch=1.0 x 1.0mm
PIN ASSIGNMENT (TOP VIEW)
x18
Index
Vss
DQ16
DQ15
DQ14
DQ12
DQ11
DQ10
DQ9
VREF
CLK
A12
A11
A8
A5
VSS
DQ17
VssQ
VDDQ
DQ13
VssQ
VDDQ
VssQ
DS
Vss
CLK
PD
A9
A7
A6
A4
DQ0
VDDQ
VssQ
DQ4
VDDQ
VssQ
VDDQ
QS
VDD
FN
CS
BA1
A0
A2
A3
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
DQ8
A14
A13
NC
BA0
A10
A1
VDD
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
K4C89183AF
- 6 - REV. 0.7 Jan. 2005
Block Diagram
CLK
CLK
PD
DLL
CLOCK
BUFFER
COMMAND
DECODER
CS
FN
CONTROL
GENERATOR
SIGNAL
ADDRESS
BUFFER
MODE
REGISTER
UPPER ADDRESS
LATCH
LOWER ADDRESS
LATCH
COLUMN DECODER
ROW DECODER
BANK #3
BANK #2
BANK #1
BANK #0
MEMORY
CELL
ARRAY
DATA
CONTROL AND LATCH
CIRCUIT
BURST
COUNTER
READ
DATA
BUFFER
WRITE
DATA
BUFFER
DQ BUFFER
A0 ~ A14
BA0, BA1
REFRESH
COUNTER
WRITE ADDRESS
LATCH
ADDRESS
COMPARATOR
DS
DQ0 ~ DQ17
To Each Block
Note : The K4C89183AD configuration is 4 Bank of 32768 x 128 x 18 of cell array with the DQ pins numbered DQ0~DQ17.
QS
K4C89183AF
- 7 - REV. 0.7 Jan. 2005
Absolute Maximum Ratings
Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-
cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
Recommended DC,AC Operating Conditions (Notes : 1) (Tcase = 0 ~ 85 OC)
Symbol Parameter Rating Units Notes
VDD Power Supply Voltage -0.3 ~ 3.3 V
VDDQ Power Supply Voltage (for I/O buffer) -0.3 ~ VDD + 0.3 V
VIN Input Voltage -0.3 ~ VDD + 0.3 V
VOUT DQ pin Voltage -0.3 ~ VDDQ + 0.3 V
VREF Input Reference Voltage -0.3 ~ VDDQ + 0.3 V
TOPR Operating Temperature 0 ~ 85 OCCase Temp.
TSTG Storage Temperature -55 ~ 150 OC
TSOLDER Soldering Temperature(10s) 260 OC
PDPower Dissipation 2 W
IOUT Short Circuit Output Current ± 50 mA
Symbol Parameter Min Typ Max Units Notes
VDD Power Supply V oltage 2.375 2.5 2.625 V
VDDQ Power Supply Voltage (for I/O Buffer) 1.7 1.8 1.9 V
VREF Input Reference Voltage VDDQ/2x95% VDDQ/2 VDDQ/2x105% V 2
VIH (DC) Input DC high Voltage VREF+0.125 - VDDQ+0.2 V 5
VIL(DC) Input DC Low Voltage -0.1 - VREF-0.125 V 5
VICK (DC) Differential Clock DC Input Voltage -0.1 - VDDQ+0.1 V 10
VID (DC) Input Differential Voltage. CLK and CLK Inputs (DC) 0.4 - VDDQ+0.2 V 7,10
VIH (AC) Input AC High Voltage VREF+0.2 - VDDQ+0.2 V 3,6
VIL (AC) Input AC Low Voltage -0.1 - VREF-0.2 V 4,6
VID (AC) Input Differential Voltage. CLK and CLK Inputs (AC) 0.55 - VDDQ+0.2 V 7,10
VX (AC) Differential AC Input Cross Point Voltage VDDQ/2-0.125 - VDDQ/2+0.125 V 8,10
VISO (AC) Differential Clock AC Middle Level VDDQ/2-0.125 - VDDQ/2+0.125 V 9,10
K4C89183AF
- 8 - REV. 0.7 Jan. 2005
1. All voltages are referenced to Vss, VssQ.
2. VREF is expected to track variations in VddQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ± 2% of VREF (DC).
3. Overshoot Iimit : VIH(max.) = VddQ + 0.7V with a pulse width <= 5ns
4. Undershoot Iimit : VIL(min.) = -0.7V with a pulse width <= 5ns
5. VIH(DC) and VIL(DC) are levels to maintain the current logic state.
6. VIH(AC) and VIL(AC) are levels to change to the new logic state.
7. VID is magnitude of the difference between CLK input level and CLK input level.
8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device.
9. VISO means [VICK(CLK) + VICK(CLK)]/2
10. Refer to the figure below.
Notes:
11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of VREF(DC) ± 0.04V.
Pin Capacitance (VDD= 2.5V, VDDQ = 1.8V, f = 1 MHz, Ta = 25oC)
Note : These parameters are periodically sampled and not 100% tested.
Symbol Parameter Min Max Delts Units
CIN Input Pin Capacitance 1.5 3.0 0.25 pF
CINC Clock Pin (CLK, CLK) Capacitance 1.5 3.0 0.25 pF
CI/O DQ, DS, QS Capacitance 2.5 3.5 0.5 pF
CNC NC Pin Capacitance - 1.5 - pF
CLK
CLK
VSS
VID(AC)
0 V Differential
VISO
VSS
VICK
VISO(min)
VXVX
VXVX
VICK VICK VICK
VISO(max)
VXVID(AC)
K4C89183AF
- 9 - REV. 0.7 Jan. 2005
DC Characteristics and Operating Conditions (VDD = 2.5V ± 0 .12 5V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)
Parameter Symbol Max Units Notes
F6 FB F5
Operating Current
One bank Read or Write operation;
tCK = min, IRC = min, IOUT = 0mA;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;
Address inputs change up to 2 times during minimum IRC,
Read data change twice per clock cycle
IDD1S 320 300 280
mA
1, 2
Standby Current
All Banks : inactive state;
tCK=min, CS = VIH, PD = VIH;
0V ≤ VIN ≤ VIL(AC)(max.), V IH(AC)(min.) ≤ VIH ≤ VDDQ;
Other input signals change one time during 4*tCK,
DQ and DS inputs change twice per clock cycle
IDD2N 100 95 90 1
Standby (Power Down) Current
All Banks : inactive state;
tCK=min, PD = VIL (Power Down);
CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC)(max), VIH(AC)(min) ≤ VIN ≤ VDDQ;
Other input signals change one time during 4*tCK,
DQ and DS inputs are floating(VDDQ/2)
IDD2P 70 65 60 1
Write Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
tCK = min, IRC = min;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;
Address inputs change once per clock cycle,
DQ and DS inputs change twice per clock cycle
IDD4W 650 600 550 1
Read Operating Current(4 Banks)
4 Bank intereaved continuous burst write operation;
tCK = min, IRC = min, IOUT = 0mA;
Burst Length = 4, CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC)(min.) ≤ VIN ≤ VDDQ;
Address inputs change once per clock cycle,
Read data change twice per clock cycle
IDD4R 650 600 550 1,2
Burst Auto-Refresh Current
Refresh command at every IREFC interval;
tCK = min, IREFC= min;
CAS Latency = 6, Free running QS mode;
0V ≤ VIN ≤ VIL(AC) (max.), VIH(AC) (min.) ≤ VIN ≤ VDDQ;
Address change up to 2 times during minimum IREFC,
DQ and DS inputs change twice per clock cycle
IDD5B 250 235 210 1,3
K4C89183AF
- 10 - REV. 0.7 Jan. 2005
DC Characteristics and Operating Conditions (VDD = 2.5V ± 0.125V, VDDQ = 1.8V ± 0.1V, Tcase = 0~85 °C)
Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
tCK, tRC and IRC.
2. These parameters depend on the output loading. The specified va lues are obtained with the output open.
3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI specification
4. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
Parameter Symbol Min Max Unit Notes
Input Leakage Current (0V<=VIN<=VddQ, All other pins not under test = 0V) ILI -5 5 uA
Output Leakage Current (Output disabled, 0V<=VOUT<=VddQ) ILO -5 5 uA
VREF Current IREF -5 5 uA
Normal O utput
Driver
Output DC Current
(VDDQ = 1.7 ~ 1.9V)
VOH = 1.420V IOH(DC) -5.6 -
mA
4
VOL = 0.280V IOL(DC) 5.6 - 4
Strong Output
Driver VOH = 1.420V IOH(DC) -9.8 - 4
VOL = 0.280V IOL(DC) 9.8 - 4
Weak Output
Driver VOH = 1.420V IOH(DC) -2.8 - 4
VOL = 0.280V IOL(DC) 2.8 -
Normal O utput
Driver
Output DC Current
(VDDQ = 1.4 ~ 1.6V)
VOH = VDDQ - 0.4 IOH(DC) -4 -
mA
3
VOL = 0.4V IOL(DC) -4 - 3
Strong Output
Driver VOH = VDDQ - 0.4 IOH(DC) -8 - 3
VOL = 0.4V IOL(DC) -8 - 3
Weak Output
Driver Not defined IOH(DC) --
Not defined IOL(DC) --
K4C89183AF
- 11 - REV. 0.7 Jan. 2005
AC Characteristics and Operating Conditions (Notes : 1, 2)
Symbol Parameter F6 FB F5 Units Notes
Min Max Min Max Min Max
tRC Random Cycle Time 20.0 - 22.5 - 25 -
ns
3
tCK Clock Cycle Time
CL = 4 4.0 6.0 4.5 6.0 5.0 6.0 3
CL = 5 3.33 6.0 3.75 6.0 4.5 6.0 3
CL = 6 3.0 6.0 3.33 6.0 4.0 6.0 3
tRAC Random Access Time - 20.0 - 22.5 - 25 3
tCH Clock High Time 0.45*tCK -0.45*tCK -0.45*tCK -3
tCL Clock Low Time 0.45*tCK -0.45*tCK -0.45*tCK -3
tCKQS QS Access Time from CLK -0.45 0.45 -0.45 0.45 -0.5 0.5 3, 8
tQSQ Data Output Skew from QS - 0.2 - 0.25 - 0.3 4
tAC Data Access Time from CLK -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8
tOH Data Output Hold Time from CLK -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8
tHP CLK half period ( minium of Actual tCH, tCL)min(tCH,
tCL)-min(tCH,
tCL)-min(tCH,
tCL)-3
tQSP QS(Read) Pulse Widt h tHP-tQHS -tHP-tQHS -tHP-tQHS -4, 8
tQSQV Data Output Valid Time from QS tHP-tQHS -tHP-tQHS -tHP-tQHS -4, 8
tQHS DQ, QS Hold skew factor - 0.055x
tCK+0.17 -0.055x
tCK+0.17 -0.055x
tCK+0.17
tDQSS DS(Write) Low to High Setup Time 0.8*tCK 1.2*tCK 0.8*tCK 1.2*tCK 0.8*tCK 1.2*tCK 3
tDSPRE DS(Write) Preamble Pulse Width 0.4*tCK -0.4*tCK -0.4*tCK -4
tDSPRES DS First Input Setup Time 0 - 0 - 0 - 3
tDSPREH DS First Low Input Hold Time 0.3*tCK -0.3*tCK -0.3*tCK -3
tDSP DS High or Low Input Pulse Width 0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK 0.45*tCK 0.55*tCK 4
tDSS DS Input Falling Edge to Clock Setup
Time
CL = 4 0. 75 - 0.8 - 1.0 - 3, 4
CL = 5 0. 75 - 0.8 - 1.0 - 3, 4
CL = 6 0. 75 - 0.8 - 1.0 - 3, 4
CL = 7 ------ 3, 4
tDSPST DS(Wri te) Postamble Pulse Width 0.45*tCK -0.45*tCK 0.45*tCK -4
tDSPSTH DS(Write) Postamble Hold Time
CL = 4 0. 75 - 0.8 - 1.0 - 3, 4
CL = 5 0. 75 - 0.8 - 1.0 - 3, 4
CL = 6 0.75 - 0.8 - 1.0 3, 4
CL = 7 ------ 3, 4
tDS Data Input Setup Time from DS 0.3 - 0.35 - 0.4 - 4
tDH Data Input Hold Time from DS 0.3 - 0.35 - 0.4 - 4
tIS Command / Address Input Setup Time 0.6 - 0.6 - 0.7 - 3
tIH Command / Address Input Hold Time 0.6 - 0.6 - 0.7 - 3
K4C89183AF
- 12 - REV. 0.7 Jan. 2005
AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)
Symbol Parameter F6 FB F5 Units Notes
Min Max Min Max Min Max
tLZ Data-out Low Impedance Time from CLK -0.5 - -0.5 - -0.6 - 3, 6, 8
tHZ Data-out High Impedance Time from CLK - 0.5 - 0.5 - 0.6 3, 7, 8
tQPDH Last Output to PD High Hold Time 0 - 0 - 0 -
tPDEX Power Down Exit Time 0.6 - 0.6 - 0.7 - 3
tTInput Transition Time 0.1 1 0.1 1 0.1 1
tFPDL PD Low Input Window for Self-Refres h Entry -0.5*tCK 5-0.5*tCK 5-0.5*tCK 53
tREFI Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 0.4 3. 9 us 5
tPAUSE Pause Time after Power-up 200 - 200 - 200 -
IRC Random Read/Write Cycle Time
(Applicable to Same Bank)
CL = 4 5-5-5-
Cycle
CL = 5 6-6-6-
CL = 6 7-7-7-
CL = 7 ------
IRCD RDA/WRA to LAL Command Input Delay
(Applicable to Same Bank) 111111
IRAS LAL to RDA/WRA Command Input Delay
(Applicable to Same Bank)
CL = 4 4-4-4-
CL = 5 5-5-5-
CL = 6 6-6-6-
CL = 7 ------
IRBD Random Bank Access Delay
(Applicable to Other Bank) 2-2-2-
IRWD LAL following RDA to WRA Delay
(Applicable to Other Bank) BL = 4 3 - 3 - 3 -
IWRD LAL following WRA to RDA Delay
(Applicable to Other Bank) 1-1-1-
IRSC Mode Register Set Cycle Time
CL = 4 7-7-7-
CL = 5 7-7-7-
CL = 6 7-7-7-
CL = 7
IPD PD Low to Inactive State of Input Buffer - 2 - 2 - 2
IPDA PD High to Active State of Inp ut Buffer 1 - 1 - 1 -
IPDV Power down mode valid from REF com-
mand
CL = 4 19 - 19 - 19 -
CL = 5 23 - 23 - 23 -
CL = 6 25 - 25 - 25 -
CL = 7
IREFC Auto-Refresh Cycle Time
CL = 4 19 - 19 - 19 -
CL = 5 23 - 23 - 23 -
CL = 6 25 - 25 - 25 -
CL = 7
ILOCK DLL Lock-on Time (Applicable to RDA command) 200 - 200 - 200 -
K4C89183AF
- 13 - REV. 0.7 Jan. 2005
AC Test Conditions
Symbol Parameter Value Units Notes
VIH(min) Input high voltage (minimum) VREF + 0.2 V
VIL (max) Input low voltage (maximum) VREF - 0.2 V
VREF Input re ference volt ag e VddQ/2 V
VTT Termination voltage VREF V
VSWING Input signal peak to peak swing 0.7 V
VRDifferential clock input reference level VX(AC) V
VID(AC) Input differential voltage 1.0 V
SLEW Input signal minimum slew rate 2.5 V/ns
VOTR Output timing measurement reference voltage VddQ/2 V 9
VIH min(AC)
VREF
VIL max(AC)
VSWING
VddQ
Vss
VTT
Output
Slew=(VIHmin(AC) - VILmax(AC))/∆T
∆T∆T
Notes : 1. Transition times are measured between VIH min(DC) and VIL max(DC).
Transition (rise and fall) of input signals have a fixed slope.
2. If the result of nominal calculation with regard to tCK contains more than
one decimal place, the result is rounded up to the nearest decimal place.
(i.e., tDQSS = 0.8*tCK, tCK = 3.3ns, 0.8*3.3 ns = 2.64 ns is rounded up to 2.7 ns.)
3. These parameters are measured from the differential clock (CLK and CLK) AC cross point.
4. These parameters are measured from signal transition poin t of DS crossing VREF level.
5. The tREFI (MAX.) applies to equally distributed refresh method.
The tREFI (MIN.) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always . In
other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the
maximum.
6. Low Impedance State is speified at VddQ/2± 0.2V fro m stead y state.
7. High Impedance State is specified where output buffer is no longer driven.
8. These parameters depend on the clock jitter. These parameters are measured at stable clock.
9. Output timing is measured by using Normal driver strength at VDDQ = 1.7V ~ 1.9V.
Output timing is measured by using Strong driver strength at VDDQ = 1.4V ~ 1.6V
AC Test Load
25 Ω
Measurement Point
K4C89183AF
- 14 - REV. 0.7 Jan. 2005
Power Up Sequence
1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.
2. Apply VDD before or at the same time as VDDQ.
3. Apply VDDQ before or at the same time as VREF.
4. Start clock (CLK, CLK) and maintain stable condition for 200us (min.).
5. After stable power and clock, apply DESL and take PD = H.
6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1)
7. Issue MRS for set CAS Latency (CL), Burst Ty pe (BT), and Burst Length (BL). (Note : 1)
8. Issue two or more Auto-Refresh commands. (Note:1)
9. Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note : 1. Sequence 6, 7 and 8 can be issued in random order.
2. L=Logic Low, H = Logic High
DESL RDA MRS DESL RDA MRS DESL WRA REF WRA REFDESL DESL
EMRS MRS
op-code op-code
VDD
VDDQ
VREF
CLK
CLK
PD
Command
Address
DQ
DS
∼
∼
∼
∼
∼
∼
∼
∼∼
∼
∼
∼∼
∼∼
∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼
∼
∼
∼∼
∼∼
∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼
∼
∼
∼∼
∼∼
∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼
∼
∼
∼∼
∼∼
∼∼
∼
∼
∼
∼
∼
∼
∼
∼
∼∼
∼
∼
∼∼
∼∼
∼∼
∼
200 µs(min) IPDA lRSC lRSC lREFC
2.5V(TYP)
1.8V(TYP)
0.9V(TYP)
lREFC
tPDEX
200 clock cycle(min)
QS
EMRS
Hi-Z
QS
(Free Running mode)
(Uni-QS mode)
MRS Auto Refresh cycle Normal Operation
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
Low
K4C89183AF
- 15 - REV. 0.7 Jan. 2005
tCK
tCK tCH tCL
tIS tIH
tIPW
1st
tIS tIH
2nd
tIS tIH
1st
tIS tIH
2nd
tIPW
tIS tIH
UA, BA
tIS tIH
LA
tDS tDH
CLK
CK
CS
FN
A0-A14
BA0.BA1
DS
DQn (Input)
~
~
Basic Timing Diagrams
Timing of the CLK, CLK
Input Timing
tCH tCL
tCK
tTtT
VIH
VIH(AC)
VIL(AC)
VIL
CLK
CLK
CLK
VIH
VIL
VID(AC)
CK
VXVXVX
~
~
~
~~
~~
~~
~~
~~
~~
~~
~
Command and Address
tDH
tDS
tDS tDH
DQm (Input)
~
~~
~
tDH
tDS
Data
Refer to the Command Truth Table.
K4C89183AF
- 16 - REV. 0.7 Jan. 2005
Q0
LAL
(after RDA)
tIS tIH
tCH tCL tCK
tCKQS
tCKQS tQSP tQSP
tCKQS
tQSQ
tLZ tQSQV
tAC
tQSQV
tQSQ
tHZ
tQSQ
Low
High-Z
CK
CK
Input
(Control &
Addresses)
CAS latency = 4
LQS/UQS
(Output)
DQ
(Output)
Read Timing (Burst Length = 4)
Low
DESL
LDS/UDS
(Input)
Q1 Q2 Q3
tAC tAC tOH
0123456789101112131415161718
Q0
tCKQS
tCKQS tQSP tQSP
tCKQS
tQSQ
tLZ tQSQV
tAC
tQSQV
tQSQ
tHZ
tQSQ
Low
High-Z
CAS latency = 5
LQS/UQS
(Output)
DQ
(Output)
Low
Q1 Q2 Q3
tAC tAC tOH
Note : DQ0 to DQ17 are aligned with LQS.
Unidirectional DS/QS mode
DQ18 to DQ35 are aligned with UQS.
Q0
tCKQS
tCKQS tQSP tQSP
tCKQS
tQSQ
tLZ tQSQV
tAC
tQSQV
tQSQ
tHZ
tQSQ
Low
High-Z
CAS latency = 6
LQS/UQS
(Output)
DQ
(Output)
Low
Q1 Q2 Q3
tAC tAC tOH