DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4030B
gates
Quadruple exclusive-OR gate
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Quadruple exclusive-OR gate HEF4030B
gates
DESCRIPTION
The HEF4030B provides the positive quadruple
exclusive-OR function. The outputs are fully buffered for
highest noise immunity and pattern insensitivity of output
impedance.
Fig.1 Functional diagram.
HEF4030BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4030BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4030BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
Fig.2 Logic diagram (one gate).
TRUTH TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
I1I2O1
LLL
HLH
LHH
HHL
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995 3
Philips Semiconductors Product specification
Quadruple exclusive-OR gate HEF4030B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤20 ns
VDD
VSYMBOL TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In→On5 85 175 ns 57 ns +(0,55 ns/pF) CL
HIGH to LOW 10 tPHL 35 75 ns 24 ns +(0,23 ns/pF) CL
15 30 55 ns 22 ns +(0,16 ns/pF) CL
5 75 150 ns 47 ns +(0,55 ns/pF) CL
LOW to HIGH 10 tPLH 30 65 ns 19 ns +(0,23 ns/pF) CL
15 25 50 ns 17 ns +(0,16 ns/pF) CL
Output transition times 5 60 120 ns 10 ns +(1,0 ns/pF) CL
HIGH to LOW 10 tTHL 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 1 100 fi+∑(foCL) ×VDD2where
dissipation per 10 4 900 fi+∑(foCL) ×VDD2fi= input freq. (MHz)
package (P) 15 14 400 fi+∑(foCL) ×VDD2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
