2Mx36 & 4Mx18 DDRII CIO b2 SRAM
K7I643682M
K7I641882M
- 4 - Rev. 1.3 March 2007
PIN CONFIGURATIONS(TOP VIEW) K7I643682M(2Mx36)
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb.
2. BW0 controls write to DQ0:DQ8, BW1 controls write to DQ9:DQ17, BW2 controls write to DQ18:DQ26 and BW3 controls write to DQ27:DQ35.
12345678910 11
ACQ NC/SA* SA R/W BW2KBW1LD SA SA CQ
BNC DQ27 DQ18 SA BW3KBW0SA NC NC DQ8
CNC NC DQ28 VSS SA SA0 SA VSS NC DQ17 DQ7
DNC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16
ENC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6
FNC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5
GNC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14
HDoff VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ
JNC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4
KNC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3
LNC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2
MNC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1
NNC DQ35 DQ25 VSS SA SA SA VSS NC NC DQ10
PNC NC DQ26 SA SA C SA SA NC DQ9 DQ0
RTDO TCK SA SA SA C SA SA SA TMS TDI
PIN NAME
Notes: 1. C, C, K or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it
cannot be connected to ground or left unconnected
.
3. Not connected to chip pad internally.
SYMBOL PIN NUMBERS DESCRIPTION NOTE
K, K 6B, 6A Input Clock
C, C 6P, 6R Input Clock for Output Data 1
CQ, CQ 11A, 1A Output Echo Clock
Doff 1H DLL Disable when low
SA0 6C Burst Count Address Inputs
SA 3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R Address Inputs
DQ0-35
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
Data Inputs Outputs
R/W 4A Read, Write Control Pin, Read active
when high
LD 8A Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1,BW2, BW37B,7A,5A,5B Block Write Control Pin,active when low
VREF 2H,10H Input Reference Voltage
ZQ 11H Output Driver Impedance Control Input 2
VDD 5F,7F,5G,7G,5H,7H,5J,7J,5K,7K Power Supply (1.8 V)
VDDQ 4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L Output Power Supply (1.5V or 1.8V)
VSS 4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N Ground
TMS 10R JTAG Test Mode Select
TDI 11R JTAG Test Data Input
TCK 2R JTAG Test Clock
TDO 1R JTAG Test Data Output
NC
2A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
No Connect 3