HD64F2623FA20J - Hitachi Semiconductor

Hitachi 16-Bit Single-Chip Microcomputer

H8S/2626 Series, H8S/2623 Series

H8S/2626F-ZTAT™,

H8S/2623F-ZTAT™

H8S/2626 Series

H8S/2626 HD6432626

H8S/2625 HD6432625

H8S/2624 HD6432624

H8S/2623 Series

H8S/2623 HD6432623

H8S/2622 HD6432622

H8S/2621 HD6432621

H8S/2626F-ZTAT™

HD64F2626

H8S/2623F-ZTAT™

HD64F2623

Hardware Manual

ADE-602-164B

Rev. 3.0

5/25/00

Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

Preface

The H8S/2626 Series and H8S/2623 Series are series of high-performance microcontrollers with a

32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for system

configuration.

The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit

general registers with a 32-bit internal configuration, and a concise and optimized instruction set.

The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based

on the high-level language C can also be run efficiently.

The address space is divided into eight areas. The data bus width and access states can be selected

for each of these areas, and various kinds of memory can be connected fast and easily.

Single-power-supply flash memory (F-ZTAT™*), and mask ROM versions are available,

providing a quick and flexible response to conditions from ramp-up through full-scale volume

production, even for applications with frequently changing specifications.

On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse

generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller

area network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports.

In addition, data transfer controller (DTC) is provided, enabling high-speed data transfer without

CPU intervention.

Use of the H8S/2626 Series or H8S/2623 Series enables easy implementation of compact, high-

performance systems capable of processing large volumes of data.

This manual describes the hardware of the H8S/2626 Series and H8S/2623 Series. Refer to the

H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the

instruction set.

Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Revisions and Additions in this Edition

Page Item Revisions (See Manual for Details)

All Amendments associated with addition

of H8S/2626 Series

2 to 5 Table 1-1 Overview Following items amended due to

addition of H8S/2626 Series

WDT, D/A converter, I/O ports, memory,

interrupt controller, power-down mode,

product lineup

7 Figure 1-2 Internal Block Diagram Added

9 Figure 1-4 Pin Arrangement Added

14 to 17 Table 1-3 Pin Functions in Each Operating

Mode

Added

18, 22 Table 1-4 Pin Functions Clock: OSC1, OSC2 (subclock pins)

added

I/O ports: Note added to Port A

61 Figure 2-14 Processing States Note added

62 Figure 2-15 State Transitions Note 3. added

66 2.8.6 Power-Down State Description amended

76 3.2.3 Pin Function Control Register (PFCR) Bit 5 description amended

84 Figure 4-1 Exception Sources Note 2. added

85 Table 4-2 Exception Vector Table Exception handling source ÒDirect

transitionsÓ added

90 Figure 4-4 Interrupt Sources and Number of

Interrupts

Internal interrupt ÒWDTÓ amended

99 Table 5-3 Correspondence between Interrupt

Sources and IPR Settings

Amended

103 5.3 Interrupt Sources Internal interrupt sources amended

105 to

107

Table 5-4 Interrupt Sources, Vector

Addresses, and Interrupt Priorities

Amended

130, 131 6.3.4 Operation in Transitions to Power-Down

Modes

Amended

148 7.2.6 Pin Function Control Register (PFCR) Bit 5 description amended

209 9.1 Overview Description amended

210 to

212

Table 9-1 Port Functions Ports 9, A, and F amended

230, 231 9.4 Port 9 Description of pins DA2 and DA3 added

Page Item Revisions (See Manual for Details)

232 to

239

9.5 Port A Description of pins OSC2 and OSC1

added

273 to

278

9.10 Port F Description of BUZZ pin added

397 to

416

Section 12 Watchdog Timer WDT1 related description added

524 15.2.1 Master Control Register (MCR) R/W of bits 6, 4, 3 amended

525 15.2.2 General Status Register (GSR) R/W of bits 7 to 4 amended

528 Figure 15-2 Detailed Description of One Bit Note added

529 Table 15-3 Setting Range for TSEG1 and

TSEG2 in BCR

Note added

531 15.2.4 Mailbox Configuration Register

(MBCR)

R/W of bit 8 amended

532 15.2.5 Transmit Wait Register (TXPR) R/W of bit 8 amended

533 15.2.6 Transmit Wait Cancel Register (TXCR) R/W of bit 8 amended

534 15.2.7 Transmit Acknowledge Register

(TXACK)

R/W of bit 8 amended

535 15.2.8 Abort Acknowledge Register (ABACK) R/W of bit 8 amended

536 15.2.9 Receive Complete Register (RXPR) Description amended

537 15.2.10 Remote Request Register (RFPR) Description amended

538, 540 15.2.11 Interrupt Register (IRR) R/W of bit 10 amended

Bit 8 description amended

543 to

545

15.2.13 Interrupt Mask Register (IMR) R/W of bits 8 to 5, 3, 2 amended

Bit descriptions amended

546 15.2.16 Unread Message Status Register

(UMSR)

Description amended

547, 548 15.2.17 Local Acceptance Filter Masks

(LAFML, LAFMH)

R/W of bits 12 to 10 amended

Bit descriptions amended

549, 550 15.2.18 Message Control (MC0 to MC15) R/W of MCx[1] bits amended

Description of MCx[1] bits 3 to 0

amended

553, 554 15.2.19 Message Data (MD0 to MD15) Bit descriptions amended

559 15.3.2 Initialization after Hardware Reset IRR0 Clearing Added

559 Bit Rate Settings Variable SJW restriction amended

Page Item Revisions (See Manual for Details)

563 15.3.3 Transmit Mode

Initialization (After Hardware Reset Only)

IRR0 Clearing Added

566 Message transmission and interrupts ·Message transmission completion

and interrupt Description amended

568 15.3.4 Receive Mode

Initialization (After Hardware Reset Only)

IRR0 Clearing Added

575 15.3.5 HCAN Sleep Mode

Clearing by CAN bus operation

Description amended

580 15.5 Usage Notes

1. Reset Description amended

7. Register retention during standby Added

603 to

610

Section 17 D/A Converter

[Provided in the H8S/2626 Series only]

Added

629, 630 19.5.6 Flash Memory Power Control Register

(FLPWCR)

Added

667 19.12 Flash Memory and Power-Down States Amendments associated with addition

of subclock function

675 to

686

Section 20 Clock Pulse Generator Amendments associated with addition

of subclock function

687 to

702

Section 21A Power-Down Modes

[H8S/2623 Series] (no subclock function)

Divided by series

690 21A.2.1 Standby Control Register (SBYCR) Initial value of bits 6 and 4 amended

703 to

728

Section 21B Power-Down Modes

[H8S/2626 Series] (subclock function provided)

Divided by series

708 21B.2.1 Standby Control Register (SBYCR) Initial value of bits 6 and 4 amended

729 Table 22-1 Absolute Maximum Ratings Amendments associated with addition

of pins OSC1 and OSC2

730 to

732

Table 22-2 DC Characteristics Amendments associated with addition

of pins OSC1 and OSC2

Amendments associated with addition

of subclock function

Amendments associated with addition

of D/A converter

733 Figure 22-1 Output Load Circuit Amended

734 Table 22-4 Clock Timing Amendments associated with addition

of subclock function

736 Table 22-5 Control Signal Timing Conditions: ¿ value amended

738 Table 22-6 Bus Timing Conditions: ¿ value amended

Page Item Revisions (See Manual for Details)

745, 746 Table 22-7 Timing of On-Chip Supporting

Modules

Conditions: ¿ value amended

BUZZ output delay time added

749 Figure 22-22 WDT1 Output Timing Added

750 Table 22-8 A/D Conversion Characteristics Conversion time amended

751 22.5 D/A Conversion Characteristics Added

830 to

844

B.1 Address Added

H'FDAC DADR2

H'FDAD DADR3

H'FDAE DADR23

H'FFA2 TCSR1/TCNT1

H'FFA3 TCNT1

H'FFAC FLPWCR

845 to

994

B.2 Functions Registers for which amendments have

been made in this manual

H'F800 MCR

H'F801 GSR

H'F804 MBCR

H'F806 TXPR

H'F808 TXCR

H'F80A TXACK

H'F80C ABACK

H'F812 IRR

H'F816 IMR

H'F81C LAFML

H'F81E LAFMH

H'F820ÑH'F898 MC0ÑMC15

H'F8B0ÑH'F928 MD0ÑMD15

H'FDE4 SBYCR

H'FDE6 SCKCR

H'FDE8ÑH'FDEA

MSTPCRAÑMSTPCRC

H'FDEB PFCR

H'FDEC LPWRCR

H'FE39 PADDR

H'FE40 PAPCR

H'FE47 PAODR

H'FEC0ÑH'FECC IPRAÑIPRM

H'FF09 PADR

H'FFB9 PORTA

1006 Figure C-4 (e) Port A Block Diagram (Pins

PA4 and PA5)

Amended

1016 Figure C-9 (c) Port F Block Diagram in the

H8S/2626 Series (Pin PF1)

Added

1027 Appendix F Product Code Lineup Addition of H8S/2626 Series

Contents

Section 1 Overview........................................................................................................... 1

1.1 Overview............................................................................................................................ 1

1.2 Internal Block Diagram ..................................................................................................... 6

1.3 Pin Descriptions................................................................................................................. 8

1.3.1 Pin Arrangement .................................................................................................. 8

1.3.2 Pin Functions in Each Operating Mode................................................................ 10

1.3.3 Pin Functions........................................................................................................ 18

Section 2 CPU..................................................................................................................... 23

2.1 Overview............................................................................................................................ 23

2.1.1 Features ................................................................................................................ 23

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 24

2.1.3 Differences from H8/300 CPU............................................................................. 25

2.1.4 Differences from H8/300H CPU.......................................................................... 25

2.2 CPU Operating Modes ...................................................................................................... 26

2.3 Address Space.................................................................................................................... 31

2.4 Register Configuration ......................................................................................................32

2.4.1 Overview.............................................................................................................. 32

2.4.2 General Registers.................................................................................................. 33

2.4.3 Control Registers.................................................................................................. 34

2.4.4 Initial Register Values.......................................................................................... 36

2.5 Data Formats...................................................................................................................... 37

2.5.1 General Register Data Formats ............................................................................ 37

2.5.2 Memory Data Formats.......................................................................................... 39

2.6 Instruction Set.................................................................................................................... 40

2.6.1 Overview.............................................................................................................. 40

2.6.2 Instructions and Addressing Modes ..................................................................... 41

2.6.3 Table of Instructions Classified by Function........................................................ 43

2.6.4 Basic Instruction Formats..................................................................................... 52

2.7 Addressing Modes and Effective Address Calculation..................................................... 54

2.7.1 Addressing Mode.................................................................................................. 54

2.7.2 Effective Address Calculation.............................................................................. 57

2.8 Processing States ............................................................................................................... 61

2.8.1 Overview.............................................................................................................. 61

2.8.2 Reset State............................................................................................................ 62

2.8.3 Exception-Handling State .................................................................................... 63

2.8.4 Program Execution State...................................................................................... 66

2.8.5 Bus-Released State............................................................................................... 66

2.8.6 Power-Down State................................................................................................ 66

2.9 Basic Timing...................................................................................................................... 67

2.9.1 Overview.............................................................................................................. 67

2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 67

2.9.3 On-Chip Supporting Module Access Timing....................................................... 69

2.9.4 On-Chip HCAN Module Access Timing ............................................................. 71

2.9.5 External Address Space Access Timing............................................................... 72

2.10 Usage Note ........................................................................................................................ 72

2.10.1 TAS Instruction.................................................................................................... 72

Section 3 MCU Operating Modes................................................................................ 73

3.1 Overview............................................................................................................................ 73

3.1.1 Operating Mode Selection.................................................................................... 73

3.1.2 Register Configuration ......................................................................................... 74

3.2 Register Descriptions......................................................................................................... 74

3.2.1 Mode Control Register (MDCR).......................................................................... 74

3.2.2 System Control Register (SYSCR) ...................................................................... 75

3.2.3 Pin Function Control Register (PFCR) ................................................................ 76

3.3 Operating Mode Descriptions............................................................................................ 78

3.3.1 Mode 4.................................................................................................................. 78

3.3.2 Mode 5.................................................................................................................. 78

3.3.3 Mode 6.................................................................................................................. 78

3.3.4 Mode 7.................................................................................................................. 78

3.4 Pin Functions in Each Operating Mode............................................................................. 79

3.5 Address Map in Each Operating Mode ............................................................................. 79

Section 4 Exception Handling........................................................................................ 83

4.1 Overview............................................................................................................................ 83

4.1.1 Exception Handling Types and Priority ............................................................... 83

4.1.2 Exception Handling Operation............................................................................. 84

4.1.3 Exception Vector Table........................................................................................ 84

4.2 Reset.................................................................................................................................. 86

4.2.1 Overview.............................................................................................................. 86

4.2.2 Reset Sequence..................................................................................................... 86

4.2.3 Interrupts after Reset............................................................................................ 88

4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 88

4.3 Traces ................................................................................................................................ 89

4.4 Interrupts............................................................................................................................ 90

4.5 Trap Instruction ................................................................................................................. 91

4.6 Stack Status after Exception Handling.............................................................................. 92

4.7 Notes on Use of the Stack.................................................................................................. 93

Section 5 Interrupt Controller........................................................................................ 95

5.1 Overview............................................................................................................................ 95

iii

5.1.1 Features ................................................................................................................ 95

5.1.2 Block Diagram ..................................................................................................... 96

5.1.3 Pin Configuration ................................................................................................. 97

5.1.4 Register Configuration ......................................................................................... 97

5.2 Register Descriptions......................................................................................................... 98

5.2.1 System Control Register (SYSCR) ...................................................................... 98

5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 99

5.2.3 IRQ Enable Register (IER) .................................................................................. 100

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 101

5.2.5 IRQ Status Register (ISR).................................................................................... 102

5.3 Interrupt Sources................................................................................................................ 103

5.3.1 External Interrupts................................................................................................ 103

5.3.2 Internal Interrupts................................................................................................. 104

5.3.3 Interrupt Exception Handling Vector Table......................................................... 104

5.4 Interrupt Operation............................................................................................................ 108

5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 108

5.4.2 Interrupt Control Mode 0...................................................................................... 111

5.4.3 Interrupt Control Mode 2...................................................................................... 113

5.4.4 Interrupt Exception Handling Sequence .............................................................. 115

5.4.5 Interrupt Response Times..................................................................................... 116

5.5 Usage Notes....................................................................................................................... 117

5.5.1 Contention between Interrupt Generation and Disabling..................................... 117

5.5.2 Instructions that Disable Interrupts ...................................................................... 118

5.5.3 Times when Interrupts are Disabled..................................................................... 118

5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 119

5.6 DTC Activation by Interrupt ............................................................................................. 119

5.6.1 Overview.............................................................................................................. 119

5.6.2 Block Diagram...................................................................................................... 119

5.6.3 Operation.............................................................................................................. 120

Section 6 PC Break Controller (PBC)......................................................................... 123

6.1 Overview............................................................................................................................ 123

6.1.1 Features ................................................................................................................ 123

6.1.2 Block Diagram...................................................................................................... 124

6.1.3 Register Configuration ......................................................................................... 125

6.2 Register Descriptions......................................................................................................... 125

6.2.1 Break Address Register A (BARA) ..................................................................... 125

6.2.2 Break Address Register B (BARB)...................................................................... 126

6.2.3 Break Control Register A (BCRA) ...................................................................... 126

6.2.4 Break Control Register B (BCRB)....................................................................... 128

6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 128

6.3 Operation ........................................................................................................................... 129

6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 129

6.3.2 PC Break Interrupt Due to Data Access............................................................... 129

6.3.3 Notes on PC Break Interrupt Handling ................................................................ 130

6.3.4 Operation in Transitions to Power-Down Modes ................................................ 130

6.3.5 PC Break Operation in Continuous Data Transfer............................................... 131

6.3.6 When Instruction Execution is Delayed by One State ......................................... 132

6.3.7 Additional Notes .................................................................................................. 133

Section 7 Bus Controller.................................................................................................. 135

7.1 Overview............................................................................................................................ 135

7.1.1 Features ................................................................................................................ 135

7.1.2 Block Diagram...................................................................................................... 136

7.1.3 Pin Configuration ................................................................................................. 137

7.1.4 Register Configuration ......................................................................................... 138

7.2 Register Descriptions......................................................................................................... 139

7.2.1 Bus Width Control Register (ABWCR)............................................................... 139

7.2.2 Access State Control Register (ASTCR).............................................................. 140

7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 141

7.2.4 Bus Control Register H (BCRH).......................................................................... 145

7.2.5 Bus Control Register L (BCRL)........................................................................... 147

7.2.6 Pin Function Control Register (PFCR) ................................................................ 148

7.3 Overview of Bus Control................................................................................................... 150

7.3.1 Area Partitioning .................................................................................................. 150

7.3.2 Bus Specifications................................................................................................ 151

7.3.3 Memory Interfaces................................................................................................ 152

7.3.4 Interface Specifications for Each Area................................................................. 153

7.4 Basic Bus Interface............................................................................................................ 154

7.4.1 Overview.............................................................................................................. 154

7.4.2 Data Size and Data Alignment ............................................................................. 154

7.4.3 Valid Strobes........................................................................................................ 156

7.4.4 Basic Timing ........................................................................................................ 157

7.4.5 Wait Control......................................................................................................... 165

7.5 Burst ROM Interface ......................................................................................................... 167

7.5.1 Overview.............................................................................................................. 167

7.5.2 Basic Timing ........................................................................................................ 167

7.5.3 Wait Control......................................................................................................... 169

7.6 Idle Cycle........................................................................................................................... 170

7.6.1 Operation.............................................................................................................. 170

7.6.2 Pin States in Idle Cycle ........................................................................................ 172

7.7 Write Data Buffer Function............................................................................................... 173

7.8 Bus Release........................................................................................................................ 174

7.8.1 Overview.............................................................................................................. 174

7.8.2 Operation.............................................................................................................. 174

7.8.3 Pin States in External Bus Released State............................................................ 175

7.8.4 Transition Timing................................................................................................. 176

7.8.5 Usage Note ........................................................................................................... 177

7.9 Bus Arbitration.................................................................................................................. 177

7.9.1 Overview.............................................................................................................. 177

7.9.2 Operation.............................................................................................................. 177

7.9.3 Bus Transfer Timing ............................................................................................ 178

7.10 Resets and the Bus Controller............................................................................................ 178

Section 8 Data Transfer Controller (DTC) ................................................................ 179

8.1 Overview............................................................................................................................ 179

8.1.1 Features ................................................................................................................ 179

8.1.2 Block Diagram...................................................................................................... 180

8.1.3 Register Configuration ......................................................................................... 181

8.2 Register Descriptions......................................................................................................... 182

8.2.1 DTC Mode Register A (MRA)............................................................................. 182

8.2.2 DTC Mode Register B (MRB)............................................................................. 184

8.2.3 DTC Source Address Register (SAR).................................................................. 185

8.2.4 DTC Destination Address Register (DAR).......................................................... 185

8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 185

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 186

8.2.7 DTC Enable Registers (DTCER) ......................................................................... 186

8.2.8 DTC Vector Register (DTVECR)........................................................................ 187

8.2.9 Module Stop Control Register A (MSTPCRA).................................................... 188

8.3 Operation ........................................................................................................................... 189

8.3.1 Overview.............................................................................................................. 189

8.3.2 Activation Sources................................................................................................ 191

8.3.3 DTC Vector Table................................................................................................ 192

8.3.4 Location of Register Information in Address Space............................................ 195

8.3.5 Normal Mode........................................................................................................ 196

8.3.6 Repeat Mode ........................................................................................................ 197

8.3.7 Block Transfer Mode............................................................................................ 198

8.3.8 Chain Transfer...................................................................................................... 200

8.3.9 Operation Timing ................................................................................................. 201

8.3.10 Number of DTC Execution States........................................................................ 202

8.3.11 Procedures for Using DTC................................................................................... 204

8.3.12 Examples of Use of the DTC................................................................................ 205

8.4 Interrupts............................................................................................................................ 208

8.5 Usage Notes....................................................................................................................... 208

Section 9 I/O Ports ............................................................................................................ 209

9.1 Overview............................................................................................................................ 209

9.2 Port 1.................................................................................................................................. 213

9.2.1 Overview.............................................................................................................. 213

9.2.2 Register Configuration ......................................................................................... 214

9.2.3 Pin Functions........................................................................................................ 216

9.3 Port 4.................................................................................................................................. 228

9.3.1 Overview.............................................................................................................. 228

9.3.2 Register Configuration ......................................................................................... 229

9.3.3 Pin Functions........................................................................................................ 229

9.4 Port 9.................................................................................................................................. 230

9.4.1 Overview.............................................................................................................. 230

9.4.2 Register Configuration ......................................................................................... 231

9.4.3 Pin Functions........................................................................................................ 231

9.5 Port A................................................................................................................................. 232

9.5.1 Overview.............................................................................................................. 232

9.5.2 Register Configuration ......................................................................................... 233

9.5.3 Pin Functions........................................................................................................ 236

9.5.4 MOS Input Pull-Up Function............................................................................... 239

9.6 Port B................................................................................................................................. 240

9.6.1 Overview.............................................................................................................. 240

9.6.2 Register Configuration ......................................................................................... 241

9.6.3 Pin Functions........................................................................................................ 243

9.6.4 MOS Input Pull-Up Function............................................................................... 252

9.7 Port C................................................................................................................................. 253

9.7.1 Overview.............................................................................................................. 253

9.7.2 Register Configuration ......................................................................................... 254

9.7.3 Pin Functions........................................................................................................ 257

9.7.4 MOS Input Pull-Up Function............................................................................... 262

9.8 Port D................................................................................................................................. 263

9.8.1 Overview.............................................................................................................. 263

9.8.2 Register Configuration ......................................................................................... 264

9.8.3 Pin Functions........................................................................................................ 266

9.8.4 MOS Input Pull-Up Function............................................................................... 267

9.9 Port E................................................................................................................................. 268

9.9.1 Overview.............................................................................................................. 268

9.9.2 Register Configuration ......................................................................................... 269

9.9.3 Pin Functions........................................................................................................ 271

9.9.4 MOS Input Pull-Up Function............................................................................... 272

9.10 Port F ................................................................................................................................. 273

9.10.1 Overview.............................................................................................................. 273

9.10.2 Register Configuration ......................................................................................... 274

9.10.3 Pin Functions........................................................................................................ 276

Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 279

10.1 Overview............................................................................................................................ 279

10.1.1 Features ................................................................................................................ 279

vii

10.1.2 Block Diagram...................................................................................................... 283

10.1.3 Pin Configuration ................................................................................................. 284

10.1.4 Register Configuration ......................................................................................... 286

10.2 Register Descriptions......................................................................................................... 288

10.2.1 Timer Control Register (TCR) ............................................................................. 288

10.2.2 Timer Mode Register (TMDR) ............................................................................ 293

10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 295

10.2.4 Timer Interrupt Enable Register (TIER).............................................................. 308

10.2.5 Timer Status Register (TSR)................................................................................ 311

10.2.6 Timer Counter (TCNT)........................................................................................ 315

10.2.7 Timer General Register (TGR) ............................................................................ 316

10.2.8 Timer Start Register (TSTR)................................................................................ 317

10.2.9 Timer Synchro Register (TSYR).......................................................................... 318

10.2.10 Module Stop Control Register A (MSTPCRA).................................................... 319

10.3 Interface to Bus Master...................................................................................................... 320

10.3.1 16-Bit Registers.................................................................................................... 320

10.3.2 8-Bit Registers...................................................................................................... 320

10.4 Operation ........................................................................................................................... 322

10.4.1 Overview.............................................................................................................. 322

10.4.2 Basic Functions .................................................................................................... 323

10.4.3 Synchronous Operation........................................................................................ 329

10.4.4 Buffer Operation .................................................................................................. 331

10.4.5 Cascaded Operation.............................................................................................. 335

10.4.6 PWM Modes ........................................................................................................ 337

10.4.7 Phase Counting Mode .......................................................................................... 342

10.5 Interrupts............................................................................................................................ 349

10.5.1 Interrupt Sources and Priorities............................................................................ 349

10.5.2 DTC Activation.................................................................................................... 351

10.5.3 A/D Converter Activation.................................................................................... 351

10.6 Operation Timing .............................................................................................................. 352

10.6.1 Input/Output Timing ............................................................................................ 352

10.6.2 Interrupt Signal Timing........................................................................................ 356

10.7 Usage Notes....................................................................................................................... 360

Section 11 Programmable Pulse Generator (PPG) .................................................... 371

11.1 Overview............................................................................................................................ 371

11.1.1 Features ................................................................................................................ 371

11.1.2 Block Diagram...................................................................................................... 372

11.1.3 Pin Configuration ................................................................................................. 373

11.1.4 Registers............................................................................................................... 374

11.2 Register Descriptions......................................................................................................... 375

11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 375

11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 376

viii

11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 377

11.2.4 Notes on NDR Access.......................................................................................... 377

11.2.5 PPG Output Control Register (PCR).................................................................... 379

11.2.6 PPG Output Mode Register (PMR)...................................................................... 381

11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 384

11.2.8 Module Stop Control Register A (MSTPCRA).................................................... 384

11.3 Operation ........................................................................................................................... 385

11.3.1 Overview.............................................................................................................. 385

11.3.2 Output Timing...................................................................................................... 386

11.3.3 Normal Pulse Output............................................................................................ 387

11.3.4 Non-Overlapping Pulse Output............................................................................ 389

11.3.5 Inverted Pulse Output........................................................................................... 392

11.3.6 Pulse Output Triggered by Input Capture ............................................................ 393

11.4 Usage Notes....................................................................................................................... 394

Section 12 Watchdog Timer ............................................................................................. 397

12.1 Overview............................................................................................................................ 397

12.1.1 Features ................................................................................................................ 397

12.1.2 Block Diagram...................................................................................................... 398

12.1.3 Pin Configuration ................................................................................................. 400

12.1.4 Register Configuration ......................................................................................... 400

12.2 Register Descriptions......................................................................................................... 401

12.2.1 Timer Counter (TCNT)........................................................................................ 401

12.2.2 Timer Control/Status Register (TCSR)................................................................ 401

12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 406

12.2.4 Pin Function Control Register (PFCR) ................................................................ 407

12.2.5 Notes on Register Access..................................................................................... 408

12.3 Operation ........................................................................................................................... 410

12.3.1 Watchdog Timer Operation.................................................................................. 410

12.3.2 Interval Timer Operation...................................................................................... 412

12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 412

12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 413

12.4 Interrupts............................................................................................................................ 414

12.5 Usage Notes....................................................................................................................... 414

12.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 414

12.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 415

12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 415

12.5.4 System Reset by WDTOVF Signal...................................................................... 415

12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 415

Section 13 Serial Communication Interface (SCI) .................................................... 417

13.1 Overview............................................................................................................................ 417

13.1.1 Features ................................................................................................................ 417

13.1.2 Block Diagram...................................................................................................... 419

13.1.3 Pin Configuration ................................................................................................. 420

13.1.4 Register Configuration ......................................................................................... 421

13.2 Register Descriptions......................................................................................................... 422

13.2.1 Receive Shift Register (RSR)............................................................................... 422

13.2.2 Receive Data Register (RDR) .............................................................................. 422

13.2.3 Transmit Shift Register (TSR).............................................................................. 423

13.2.4 Transmit Data Register (TDR)............................................................................. 423

13.2.5 Serial Mode Register (SMR)................................................................................ 424

13.2.6 Serial Control Register (SCR).............................................................................. 427

13.2.7 Serial Status Register (SSR)................................................................................. 431

13.2.8 Bit Rate Register (BRR)....................................................................................... 435

13.2.9 Smart Card Mode Register (SCMR).................................................................... 444

13.2.10 Module Stop Control Register B (MSTPCRB).................................................... 445

13.3 Operation ........................................................................................................................... 447

13.3.1 Overview.............................................................................................................. 447

13.3.2 Operation in Asynchronous Mode........................................................................ 449

13.3.3 Multiprocessor Communication Function............................................................ 460

13.3.4 Operation in Clocked Synchronous Mode ........................................................... 468

13.4 SCI Interrupts .................................................................................................................... 476

13.5 Usage Notes....................................................................................................................... 478

Section 14 Smart Card Interface...................................................................................... 487

14.1 Overview............................................................................................................................ 487

14.1.1 Features ................................................................................................................ 487

14.1.2 Block Diagram...................................................................................................... 488

14.1.3 Pin Configuration ................................................................................................. 489

14.1.4 Register Configuration ......................................................................................... 490

14.2 Register Descriptions......................................................................................................... 491

14.2.1 Smart Card Mode Register (SCMR).................................................................... 491

14.2.2 Serial Status Register (SSR)................................................................................. 493

14.2.3 Serial Mode Register (SMR)................................................................................ 495

14.2.4 Serial Control Register (SCR).............................................................................. 497

14.3 Operation ........................................................................................................................... 498

14.3.1 Overview.............................................................................................................. 498

14.3.2 Pin Connections.................................................................................................... 498

14.3.3 Data Format.......................................................................................................... 500

14.3.4 Register Settings................................................................................................... 502

14.3.5 Clock .................................................................................................................... 504

14.3.6 Data Transfer Operations ..................................................................................... 506

14.3.7 Operation in GSM Mode...................................................................................... 513

14.3.8 Operation in Block Transfer Mode ...................................................................... 514

14.4 Usage Notes....................................................................................................................... 515

Section 15 Hitachi Controller Area Network (HCAN)............................................ 519

15.1 Overview............................................................................................................................ 519

15.1.1 Features ................................................................................................................ 519

15.1.2 Block Diagram...................................................................................................... 520

15.1.3 Pin Configuration ................................................................................................. 521

15.1.4 Register Configuration ......................................................................................... 522

15.2 Register Descriptions......................................................................................................... 524

15.2.1 Master Control Register (MCR)........................................................................... 524

15.2.2 General Status Register (GSR)............................................................................. 525

15.2.3 Bit Configuration Register (BCR)........................................................................ 527

15.2.4 Mailbox Configuration Register (MBCR)............................................................ 531

15.2.5 Transmit Wait Register (TXPR) .......................................................................... 532

15.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 533

15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 534

15.2.8 Abort Acknowledge Register (ABACK).............................................................. 535

15.2.9 Receive Complete Register (RXPR).................................................................... 536

15.2.10 Remote Request Register (RFPR)........................................................................ 537

15.2.11 Interrupt Register (IRR) ....................................................................................... 538

15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 542

15.2.13 Interrupt Mask Register (IMR) ............................................................................ 543

15.2.14 Receive Error Counter (REC) .............................................................................. 545

15.2.15 Transmit Error Counter (TEC)............................................................................. 546

15.2.16 Unread Message Status Register (UMSR) ........................................................... 546

15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 547

15.2.18 Message Control (MC0 to MC15)........................................................................ 549

15.2.19 Message Data (MD0 to MD15)............................................................................ 553

15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 555

15.3 Operation ........................................................................................................................... 556

15.3.1 Hardware and Software Resets............................................................................. 556

15.3.2 Initialization after Hardware Reset ...................................................................... 559

15.3.3 Transmit Mode ..................................................................................................... 562

15.3.4 Receive Mode....................................................................................................... 568

15.3.5 HCAN Sleep Mode .............................................................................................. 574

15.3.6 HCAN Halt Mode ................................................................................................ 576

15.3.7 Interrupt Interface................................................................................................. 576

15.3.8 DTC Interface....................................................................................................... 578

15.4 CAN Bus Interface............................................................................................................ 579

15.5 Usage Notes....................................................................................................................... 580

Section 16 A/D Converter ................................................................................................. 581

16.1 Overview............................................................................................................................ 581

16.1.1 Features ................................................................................................................ 581

16.1.2 Block Diagram...................................................................................................... 582

16.1.3 Pin Configuration ................................................................................................. 583

16.1.4 Register Configuration ......................................................................................... 584

16.2 Register Descriptions......................................................................................................... 585

16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 585

16.2.2 A/D Control/Status Register (ADCSR)................................................................ 586

16.2.3 A/D Control Register (ADCR)............................................................................. 589

16.2.4 Module Stop Control Register A (MSTPCRA).................................................... 590

16.3 Interface to Bus Master...................................................................................................... 591

16.4 Operation ........................................................................................................................... 592

16.4.1 Single Mode (SCAN = 0)..................................................................................... 592

16.4.2 Scan Mode (SCAN = 1) ....................................................................................... 594

16.4.3 Input Sampling and A/D Conversion Time.......................................................... 596

16.4.4 External Trigger Input Timing ............................................................................. 597

16.5 Interrupts............................................................................................................................ 598

16.6 Usage Notes....................................................................................................................... 598

Section 17 D/A Converter [Provided in the H8S/2626 Series only].................... 603

17.1 Overview............................................................................................................................ 603

17.1.1 Features ................................................................................................................ 603

17.1.2 Block Diagram...................................................................................................... 604

17.1.3 Pin Configuration ................................................................................................. 605

17.1.4 Register Configuration ......................................................................................... 605

17.2 Register Descriptions......................................................................................................... 606

17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3).................................................. 606

17.2.2 D/A Control Register 23 (DACR23).................................................................... 606

17.2.3 Module Stop Control Register C (MSTPCRC).................................................... 608

17.3 Operation ........................................................................................................................... 609

Section 18 RAM................................................................................................................... 611

18.1 Overview............................................................................................................................ 611

18.1.1 Block Diagram...................................................................................................... 611

18.1.2 Register Configuration ......................................................................................... 612

18.2 Register Descriptions......................................................................................................... 612

18.2.1 System Control Register (SYSCR) ...................................................................... 612

18.3 Operation ........................................................................................................................... 613

18.4 Usage Notes....................................................................................................................... 613

Section 19 ROM................................................................................................................... 615

19.1 Features.............................................................................................................................. 615

19.2 Overview............................................................................................................................ 616

19.2.1 Block Diagram...................................................................................................... 616

19.2.2 Mode Transitions.................................................................................................. 617

19.2.3 On-Board Programming Modes........................................................................... 618

xii

19.2.4 Flash Memory Emulation in RAM....................................................................... 620

19.2.5 Differences between Boot Mode and User Program Mode.................................. 621

19.2.6 Block Configuration............................................................................................. 622

19.3 Pin Configuration .............................................................................................................. 622

19.4 Register Configuration ...................................................................................................... 623

19.5 Register Descriptions......................................................................................................... 623

19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 623

19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 626

19.5.3 Erase Block Register 1 (EBR1)............................................................................ 627

19.5.4 Erase Block Register 2 (EBR2)............................................................................ 627

19.5.5 RAM Emulation Register (RAMER)................................................................... 628

19.5.6 Flash Memory Power Control Register (FLPWCR)............................................ 629

19.5.7 Serial Control Register X (SCRX)....................................................................... 630

19.6 On-Board Programming Modes........................................................................................ 631

19.6.1 Boot Mode............................................................................................................ 631

19.6.2 User Program Mode ............................................................................................. 636

19.7 Flash Memory Programming/Erasing................................................................................ 638

19.7.1 Program Mode...................................................................................................... 640

19.7.2 Program-Verify Mode.......................................................................................... 641

19.7.3 Erase Mode........................................................................................................... 645

19.7.4 Erase-Verify Mode............................................................................................... 645

19.8 Protection........................................................................................................................... 647

19.8.1 Hardware Protection............................................................................................. 647

19.8.2 Software Protection.............................................................................................. 648

19.8.3 Error Protection.................................................................................................... 649

19.9 Flash Memory Emulation in RAM.................................................................................... 651

19.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 653

19.11 Flash Memory Programmer Mode .................................................................................... 653

19.11.1 Socket Adapter Pin Correspondence Diagram................................................... 654

19.11.2 Programmer Mode Operation............................................................................. 656

19.11.3 Memory Read Mode........................................................................................... 657

19.11.4 Auto-Program Mode .......................................................................................... 660

19.11.5 Auto-Erase Mode................................................................................................ 662

19.11.6 Status Read Mode............................................................................................... 664

19.11.7 Status Polling...................................................................................................... 665

19.11.8 Programmer Mode Transition Time................................................................... 665

19.11.9 Notes on Memory Programming........................................................................ 666

19.12 Flash Memory and Power-Down States............................................................................ 667

19.12.1 Note on Power-Down States .............................................................................. 667

19.13 Flash Memory Programming and Erasing Precautions..................................................... 668

19.14 Note on Switching from F-ZTAT Version to Mask ROM Version.................................. 673

xiii

Section 20 Clock Pulse Generator .................................................................................. 675

20.1 Overview............................................................................................................................ 675

20.1.1 Block Diagram...................................................................................................... 676

20.1.2 Register Configuration ......................................................................................... 676

20.2 Register Descriptions......................................................................................................... 677

20.2.1 System Clock Control Register (SCKCR) ........................................................... 677

20.2.2 Low-Power Control Register (LPWRCR)............................................................ 678

20.3 Oscillator............................................................................................................................ 679

20.3.1 Connecting a Crystal Resonator........................................................................... 679

20.3.2 External Clock Input ............................................................................................ 682

20.4 PLL Circuit........................................................................................................................ 684

20.5 Medium-Speed Clock Divider........................................................................................... 684

20.6 Bus Master Clock Selection Circuit.................................................................................. 684

20.7 Subclock Oscillator............................................................................................................ 685

20.8 Subclock Waveform Shaping Circuit................................................................................ 686

20.9 Note on Crystal Resonator................................................................................................. 686

Section 21A Power-Down Modes [H8S/2623 Series] ............................................. 687

21A.1 Overview........................................................................................................................ 687

21A.1.1 Register Configuration ................................................................................... 690

21A.2 Register Descriptions...................................................................................................... 690

21A.2.1 Standby Control Register (SBYCR) .............................................................. 690

21A.2.2 System Clock Control Register (SCKCR) ..................................................... 692

21A.2.3 Low-Power Control Register (LPWRCR)...................................................... 693

21A.2.4 Module Stop Control Register (MSTPCR).................................................... 694

21A.3 Medium-Speed Mode..................................................................................................... 695

21A.4 Sleep Mode..................................................................................................................... 696

21A.4.1 Sleep Mode..................................................................................................... 696

21A.4.2 Exiting Sleep Mode........................................................................................ 696

21A.5 Module Stop Mode......................................................................................................... 696

21A.5.1 Module Stop Mode......................................................................................... 696

21A.5.2 Usage Notes.................................................................................................... 698

21A.6 Software Standby Mode................................................................................................. 698

21A.6.1 Software Standby Mode ................................................................................. 698

21A.6.2 Clearing Software Standby Mode.................................................................. 698

21A.6.3 Setting Oscillation Stabilization Time after Clearing Software

Standby Mode ................................................................................................ 699

21A.6.4 Software Standby Mode Application Example.............................................. 700

21A.6.5 Usage Notes.................................................................................................... 701

21A.7 Hardware Standby Mode................................................................................................ 701

21A.7.1 Hardware Standby Mode................................................................................ 701

21A.7.2 Hardware Standby Mode Timing................................................................... 702

21A.8 ø Clock Output Disabling Function................................................................................ 702

xiv

Section 21B Power-Down Modes [H8S/2626 Series] ............................................. 703

21B.1 Overview........................................................................................................................ 703

21B.1.1 Register Configuration ................................................................................... 707

21B.2 Register Descriptions...................................................................................................... 708

21B.2.1 Standby Control Register (SBYCR) .............................................................. 708

21B.2.2 System Clock Control Register (SCKCR) ..................................................... 710

21B.2.3 Low-Power Control Register (LPWRCR)...................................................... 711

21B.2.4 Timer Control/Status Register (TCSR).......................................................... 713

21B.2.5 Module Stop Control Register (MSTPCR).................................................... 715

21B.3 Medium-Speed Mode..................................................................................................... 716

21B.4 Sleep Mode..................................................................................................................... 717

21B.4.1 Sleep Mode..................................................................................................... 717

21B.4.2 Exiting Sleep Mode........................................................................................ 717

21B.5 Module Stop Mode......................................................................................................... 717

21B.5.1 Module Stop Mode......................................................................................... 717

21B.5.2 Usage Notes.................................................................................................... 719

21B.6 Software Standby Mode................................................................................................. 719

21B.6.1 Software Standby Mode ................................................................................. 719

21B.6.2 Clearing Software Standby Mode .................................................................. 719

21B.6.3 Setting Oscillation Stabilization Time after Clearing Software

Standby Mode ................................................................................................ 720

21B.6.4 Software Standby Mode Application Example.............................................. 721

21B.6.5 Usage Notes.................................................................................................... 722

21B.7 Hardware Standby Mode................................................................................................ 722

21B.7.1 Hardware Standby Mode................................................................................ 722

21B.7.2 Hardware Standby Mode Timing................................................................... 723

21B.8 Watch Mode ................................................................................................................... 723

21B.8.1 Watch Mode ................................................................................................... 723

21B.8.2 Exiting Watch Mode ...................................................................................... 724

21B.8.3 Notes............................................................................................................... 724

21B.9 Sub-Sleep Mode ............................................................................................................. 725

21B.9.1 Sub-Sleep Mode ............................................................................................. 725

21B.9.2 Exiting Sub-Sleep Mode ................................................................................ 725

21B.10 Sub-Active Mode............................................................................................................ 726

21B.10.1 Sub-Active Mode............................................................................................ 726

21B.10.2 Exiting Sub-Active Mode............................................................................... 726

21B.11 Direct Transitions........................................................................................................... 727

21B.11.1 Overview of Direct Transitions...................................................................... 727

21B.12 ø Clock Output Disabling Function................................................................................ 727

Section 22 Electrical Characteristics.............................................................................. 729

22.1 Absolute Maximum Ratings.............................................................................................. 729

22.2 DC Characteristics............................................................................................................. 730

22.3 AC Characteristics............................................................................................................. 733

22.3.1 Clock Timing........................................................................................................ 734

22.3.2 Control Signal Timing.......................................................................................... 735

22.3.3 Bus Timing........................................................................................................... 737

22.3.4 Timing of On-Chip Supporting Modules............................................................. 743

22.4 A/D Conversion Characteristics........................................................................................ 747

22.5 D/A Conversion Characteristics........................................................................................ 748

22.6 Flash Memory Characteristics........................................................................................... 749

22.7 Usage Note ........................................................................................................................ 750

Appendix A Instruction Set.............................................................................................. 751

A.1 Instruction List................................................................................................................... 751

A.2 Instruction Codes............................................................................................................... 776

A.3 Operation Code Map.......................................................................................................... 791

A.4 Number of States Required for Instruction Execution...................................................... 795

A.5 Bus States During Instruction Execution .......................................................................... 806

A.6 Condition Code Modification............................................................................................ 820

Appendix B Internal I/O Register.................................................................................. 826

B.1 Address.............................................................................................................................. 826

B.2 Functions............................................................................................................................ 841

Appendix C I/O Port Block Diagrams.......................................................................... 991

C.1 Port 1 Block Diagrams ...................................................................................................... 991

C.2 Port 4 Block Diagram........................................................................................................ 997

C.3 Port 9 Block Diagram........................................................................................................ 997

C.4 Port A Block Diagrams...................................................................................................... 998

C.5 Port B Block Diagram ....................................................................................................... 1003

C.6 Port C Block Diagrams...................................................................................................... 1004

C.7 Port D Block Diagram ....................................................................................................... 1008

C.8 Port E Block Diagram........................................................................................................ 1009

C.9 Port F Block Diagrams...................................................................................................... 1010

Appendix D Pin States....................................................................................................... 1019

D.1 Port States in Each Mode .................................................................................................. 1019

Appendix E Timing of Transition to and Recovery from Hardware

Standby Mode.............................................................................................. 1022

Appendix F Product Code Lineup................................................................................. 1023

Appendix G Package Dimensions.................................................................................. 1024

xvi

Section 1 Overview

1.1 Overview

The H8S/2626 Series and H8S/2623 Series are series of microcomputers (MCUs) that integrate

peripheral functions required for system configuration together with an H8S/2600 CPU employing

an original Hitachi architecture.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general

registers and a concise, optimized instruction set designed for high-speed operation, and can

address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300

and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,

H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include a data transfer controller

(DTC) bus master, ROM and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse

generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller

area network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports.

The on-chip ROM is 256-kbyte flash memory (F-ZTAT™)* or 256-, 128-, or 64-kbyte mask

ROM. The ROM is connected to the CPU by a 16-bit data bus, enabling both byte and word data

to be accessed in one state. Instruction fetching has been speeded up, and processing speed

increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or

external expansion mode.

The features of the H8S/2626 Series and H8S/2623 Series are shown in table 1-1.

Note: * F-ZTAT is a trademark of Hitachi, Ltd.

Table 1-1 Overview

Item Specifications

CPU • General-register machine

 Sixteen 16-bit general registers

(also usable as sixteen 8-bit registers or eight 32-bit registers)

• High-speed operation suitable for realtime control

 Maximum operating frequency: 20 MHz

 High-speed arithmetic operations

8/16/32-bit register-register add/subtract: 50 ns

16 × 16-bit register-register multiply: 200 ns

16 × 16 + 42-bit multiply and accumulate: 200 ns

32 ÷ 16-bit register-register divide: 1000 ns

• Instruction set suitable for high-speed operation

 69 basic instructions

 8/16/32-bit move/arithmetic and logic instructions

 Unsigned/signed multiply and divide instructions

 Multiply-and accumulate instruction

 Powerful bit-manipulation instructions

• Two CPU operating modes

 Normal mode: 64-kbyte address space

(Not available in the H8S/2626 Series or H8S/2623 Series)

 Advanced mode: 16-Mbyte address space

Bus controller • Address space divided into 8 areas, with bus specifications settable

independently for each area

• Choice of 8-bit or 16-bit access space for each area

• 2-state or 3-state access space can be designated for each area

• Number of program wait states can be set for each area

• Burst ROM directly connectable

• External bus release function

PC break

controller • Supports debugging functions by means of PC break interrupts

• Two break channels

Item Specifications

Data transfer

controller (DTC) • Can be activated by internal interrupt or software

• Multiple transfers or multiple types of transfer possible for one activation

source

• Transfer possible in repeat mode, block transfer mode, etc.

• Request can be sent to CPU for interrupt that activated DTC

16-bit timer-pulse

unit (TPU) • 6-channel 16-bit timer

• Pulse input/output processing capability for up to 16 pins

• Automatic 2-phase encoder count capability

Programmable

pulse generator

(PPG)

• Maximum 8-bit pulse output possible with TPU as time base

• Output trigger selectable in 4-bit groups

• Non-overlap margin can be set

• Direct output or inverse output setting

Watchdog timer

(WDT), 2 channels

(H8S/2626 Series)

• Watchdog timer or interval timer selectable

• Subclock operation possible (one channel only)

Watchdog timer

(WDT), 1 channel

(H8S/2623 Series)

• Watchdog timer or interval timer selectable

Serial communi-

cation interface

(SCI), 3 channels

(SCI0 to SCI2)

• Asynchronous mode or synchronous mode selectable

• Multiprocessor communication function

• Smart card interface function

Hitachi controller

area network

(HCAN),

1 channel

• CAN: Ver. 2.0B compliant

• Buffer size: 15 transmit/receive buffers, one transmit-only buffer

• Receive message filtering

A/D converter • Resolution: 10 bits

• Input: 16 channels

• 13.3 µs minimum conversion time (at 20 MHz operation)

• Single or scan mode selectable

• Sample-and-hold function

• A/D conversion can be activated by external trigger or timer trigger

D/A converter

(H8S/2626 Series

only)

• Resolution: 8 bits

• Output: 2 channels

Item Specifications

I/O ports

(H8S/2626 Series) • 51 input/output pins, 17 input-only pins

I/O ports

(H8S/2623 Series) • 53 input/output pins, 17 input-only pins

Memory • Flash memory or masked ROM

• High-speed static RAM

Product Name ROM RAM

H8S/2626, H8S/2623 256 kbytes 12 kbytes

H8S/2625*, H8S/2622 128 kbytes 8 kbytes

H8S/2624*, H8S/2621 64 kbytes 4 kbytes

Note: * In planning stage

Interrupt controller • Seven external interrupt pins (NMI, IRQ0 to IRQ5)

• Internal interrupt sources

H8S/2626: 48

H8S/2623: 47

• Eight priority levels settable

Power-down state • Medium-speed mode

• Sleep mode

• Module stop mode

• Software standby mode

• Hardware standby mode

• Subclock operation (H8S/2626 Series only)

Operating modes • Four MCU operating modes External Data Bus

Mode CPU Operating

Mode Description On-Chip

ROM Initial

Width Max.

Width

4 Advanced On-chip ROM disabled

expansion mode Disabled 16 bits 16 bits

5 On-chip ROM disabled

expansion mode Disabled 8 bits 16 bits

6 On-chip ROM enabled

expansion mode Enabled 8 bits 16 bits

7 Single-chip mode Enabled — —

Item Specifications

Clock pulse

generator • Built-in PLL circuit (×1, ×2, ×4)

• Input clock frequency: 2 to 20 MHz

Package • 100-pin plastic QFP (FP-100B)

Product lineup Model

Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Package

HD6432626*

HD6432623*HD64F2626

HD64F2623 256 k/12 k FP-100B

HD6432625*

HD6432622*— 128 k/8 k FP-100B

HD6432624*

HD6432621*— 64 k/4 k FP-100B

Note: * In planning stage

1.2 Internal Block Diagram

Figures 1-1 and 1-2 show internal block diagrams of the H8S/2623 Series and H8S/2626 Series.

Internal data bus

Peripheral data bus

Peripheral address bus

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Port D

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PVCC1

PVCC2

PVCC3

PVCC4

VCC

VSS

PA5

PA4

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PB1/A9/TIOCB3

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

P97/AN15

P96/AN14

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

HRxD

HTxD

Vref

AVCC

AVSS

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB/A23

P12/PO10/TIOCC0/TCLKA/A22

P11/PO9/TIOCB0/A21

P10/PO8/TIOCA0/A20

PF7/ø

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR/ADTRG/IRQ3

PF2/WAIT/BREQO

PF1/BACK

PF0/BREQ/IRQ2

ROM

(Mask ROM,

flash memory*1)

PC break controller

(2 channels)

RAM

WDT × 1 channel

TPU

SCI × 3 channels

HCAN × 1 channel

A/D converter

PPG

MD2

MD1

MD0

EXTAL

XTAL

PLLVCC

PLLCAP

PLLVSS

STBY

RES

WDTOVF

NMI

FWE*2

H8S/2600 CPU

DTC

Interrupt controller

Port 4Port 1

Internal address bus

Notes: 1. Applies to the H8S/2623 only.

2. The FWE pin is used only in the flash memory version.

Port E

Port APort BPort CPort 9

Bus controller

Clock pulse

generator

PLL

Port F

Figure 1-1 Internal Block Diagram

Internal data bus

Peripheral data bus

Peripheral address bus

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Port D

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PVCC1

PVCC2

PVCC3

PVCC4

VCC

VSS

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PB1/A9/TIOCB3

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

P97/AN15/DA3

P96/AN14/DA2

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

HRxD

HTxD

Vref

AVCC

AVSS

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB/A23

P12/PO10/TIOCC0/TCLKA/A22

P11/PO9/TIOCB0/A21

P10/PO8/TIOCA0/A20

PF7/ø

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR/ADTRG/IRQ3

PF2/WAIT/BREQO

PF1/BACK

PF0/BREQ/IRQ2

ROM

(mask ROM or

flash memory*1)

PC break controller

(2 channels)

RAM

WDT × 2 channels

TPU

SCI × 3 channels

HCAN × 1 channel

A/D converter

PPG

MD2

MD1

MD0

OSC1

OSC2

EXTAL

XTAL

PLLVCC

PLLCAP

PLLVSS

STBY

RES

WDTOVF

NMI

FWE*2

H8S/2600 CPU

DTC

Interrupt controller

Port 4Port 1

Internal address bus

Notes: 1. Applies to the H8S/2626 only.

2. The FWE pin is provided in the flash memory version only.

Port E

D/A converter

PLL

Port APort BPort CPort 9

Port F

Clock pulse

generator

Bus controller

Figure 1-2 Internal Block Diagram

1.3 Pin Descriptions

1.3.1 Pin Arrangement

Figures 1-3 and 1-4 show pin arrangements of the H8S/2623 Series and H8S/2626 Series.

100

Top view

(FP-100B)

P13/PO11/TIOCD0/TCLKB/A23

P14/PO12/TIOCA1/IRQ0

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/IRQ1

P17/PO15/TIOCB2/TCLKD

VCC

HTxD

VSS

HRxD

PE0/D0

PE1/D1

PE2/D2

PE3/D3

PE4/D4

VSS

PE5/D5

PVCC1

PE6/D6

PE7/D7

PD0/D8

PD1/D9

PD2/D10

PD3/D11

PD4/D12

PD5/D13

PA4

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PVCC2

PB1/A9/TIOCB3

VSS

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

PD7/D15

PD6/D14

PF0/BREQ/IRQ2

PF1/BACK

PF2/WAIT/BREQO

PF3/LWR/ADTRG/IRQ3

PF4/HWR

PF5/PD

PF6/AS

PF7/ø

FWE

EXTAL

VSS

XTAL

VCC

STBY

NMI

RES

PLLVCC

PLLCAP

PLLVSS

MD2

MD1

VSS

MD0

PVCC3

PA5

AVCC

Vref

P40/AN0

P41/AN1

P42/AN2

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

P90/AN8

P91/AN9

P92/AN10

P93/AN11

P94/AN12

P95/AN13

P96/AN14

P97/AN15

AVSS

VSS

WDTOVF

PVCC4

P10/PO8/TIOCA0/A20

P11/PO9/TIOCB0/A21

P12/PO10/TIOCC0/TCLKA/A22

Figure 1-3 Pin Arrangement (FP-100B: Top View)

100

Top view

(FP-100B)

P13/PO11/TIOCD0/TCLKB/A23

P14/PO12/TIOCA1/IRQ0

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/IRQ1

P17/PO15/TIOCB2/TCLKD

VCC

HTxD

VSS

HRxD

PE0/D0

PE1/D1

PE2/D2

PE3/D3

PE4/D4

VSS

PE5/D5

PVCC1

PE6/D6

PE7/D7

PD0/D8

PD1/D9

PD2/D10

PD3/D11

PD4/D12

PD5/D13

OSC1

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PVCC2

PB1/A9/TIOCB3

VSS

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ



PC1/A1/RxD0

PC0/A0/TxD0

PD7/D15

PD6/D14

PF0/BREQ/IRQ2

PF1/BACK/BUZZ

PF2/WAIT/BREQO

PF3/LWR/ADTRG/IRQ



PF4/HWR

PF5/PD

PF6/AS

PF7/ø

FWE

EXTAL

VSS

XTAL

VCC

STBY

NMI

RES

PLLVCC

PLLCAP

PLLVSS

MD2

MD1

VSS

MD0

PVCC3

OSC2

AVCC

Vref

P40/AN0

P41/AN1

P42/AN2

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

P90/AN8

P91/AN9

P92/AN10

P93/AN11

P94/AN12

P95/AN13

P96/AN14/DA2

P97/AN15/DA3

AVSS

VSS

WDTOVF

PVCC4

P10/PO8/TIOCA0/A20

P11/PO9/TIOCB0/A21

P12/PO10/TIOCC0/TCLKA/A22

Figure 1-4 Pin Arrangement (FP-100B: Top View)

1.3.2 Pin Functions in Each Operating Mode

Tables 1-2 and 1-3 show the pin functions in each of the operating modes of the H8S/2623 Series

and H8S/2626 Series.

Table 1-2 Pin Functions in Each Operating Mode

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

1 P13/PO11/TIOCD0/

TCLKB/A23 P13/PO11/TIOCD0/

TCLKB

2 P14/PO12/TIOCA1/

IRQ0 P14/PO12/TIOCA1/

IRQ0

3 P15/PO13/TIOCB1/

TCLKC P15/PO13/TIOCB1/

TCLKC

4 P16/PO14/TIOCA2/

IRQ1 P16/PO14/TIOCA2/

IRQ1

5 P17/PO15/TIOCB2/

TCLKD P17/PO15/TIOCB2/

TCLKD

6 VCC VCC VCC VCC

7 HTxD HTxD HTxD HTxD

8 VSS VSS VSS VSS

9 HRxD HRxD HRxD HRxD

10 PE0/D0 PE0/D0 PE0/D0 PE0

11 PE1/D1 PE1/D1 PE1/D1 PE1

12 PE2/D2 PE2/D2 PE2/D2 PE2

13 PE3/D3 PE3/D3 PE3/D3 PE3

14 PE4/D4 PE4/D4 PE4/D4 PE4

15 VSS VSS VSS VSS

16 PE5/D5 PE5/D5 PE5/D5 PE5

17 PVCC1 PVCC1 PVCC1 PVCC1

18 PE6/D6 PE6/D6 PE6/D6 PE6

19 PE7/D7 PE7/D7 PE7/D7 PE7

20 D8 D8 D8 PD0

21 D9 D9 D9 PD1

22 D10 D10 D10 PD2

23 D11 D11 D11 PD3

24 D12 D12 D12 PD4

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

25 D13 D13 D13 PD5

26 D14 D14 D14 PD6

27 D15 D15 D15 PD7

28 A0 A0 PC0/A0/TxD0 PC0/TxD0

29 A1 A1 PC1/A1/RxD0 PC1/RxD0

30 A2 A2 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4

31 A3 A3 PC3/A3/TxD1 PC3/TxD1

32 A4 A4 PC4/A4/RxD1 PC4/RxD1

33 A5 A5 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5

34 A6 A6 PC6/A6 PC6

35 A7 A7 PC7/A7 PC7

36 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/TIOCA3

37 VSS VSS VSS VSS

38 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/TIOCB3

39 PVCC2 PVCC2 PVCC2 PVCC2

40 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/TIOCC3

41 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/TIOCD3

42 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/TIOCA4

43 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/TIOCB4

44 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/TIOCA5

45 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/TIOCB5

46 PA0/A16 PA0/A16 PA0/A16 PA0

47 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2

48 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2

49 PA3/A19/SCK2 PA3/A19/SCK2 PA3/A19/SCK2 PA3/SCK2

50 PA4 PA4 PA4 PA4

51 PA5 PA5 PA5 PA5

52 PVCC3 PVCC3 PVCC3 PVCC3

53 MD0 MD0 MD0 MD0

54 VSS VSS VSS VSS

55 MD1 MD1 MD1 MD1

56 MD2 MD2 MD2 MD2

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

57 PLLVSS PLLVSS PLLVSS PLLVSS

58 PLLCAP PLLCAP PLLCAP PLLCAP

59 PLLVCC PLLVCC PLLVCC PLLVCC

60 RES RES RES RES

61 NMI NMI NMI NMI

62 STBY STBY STBY STBY

63 VCC VCC VCC VCC

64 XTAL XTAL XTAL XTAL

65 VSS VSS VSS VSS

66 EXTAL EXTAL EXTAL EXTAL

67 FWE FWE FWE FWE

68 PF7/ø PF7/ø PF7/ø PF7/ø

69 AS AS AS PF6

70 RD RD RD PF5

71 HWR HWR HWR PF4

72 PF3/LWR/ADTRG/

IRQ3 PF3/LWR/ADTRG/

IRQ3 PF3/ADTRG/

IRQ3

73 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2

74 PF1/BACK PF1/BACK PF1/BACK PF1

75 PF0/BREQ/IRQ2 PF0/BREQ/IIRQ2 PF0/BREQ/IIRQ2 PF0/IRQ2

76 AVCC AVCC AVCC AVCC

77 Vref Vref Vref Vref

78 P40/AN0 P40/AN0 P40/AN0 P40/AN0

79 P41/AN1 P41/AN1 P41/AN1 P41/AN1

80 P42/AN2 P42/AN2 P42/AN2 P42/AN2

81 P43/AN3 P43/AN3 P43/AN3 P43/AN3

82 P44/AN4 P44/AN4 P44/AN4 P44/AN4

83 P45/AN5 P45/AN5 P45/AN5 P45/AN5

84 P46/AN6 P46/AN6 P46/AN6 P46/AN6

85 P47/AN7 P47/AN7 P47/AN7 P47/AN7

86 P90/AN8 P90/AN8 P90/AN8 P90/AN8

87 P91/AN9 P91/AN9 P91/AN9 P91/AN9