HD64F2623FA20J - Hitachi Semiconductor

Hitachi 16-Bit Single-Chip Microcomputer

H8S/2626 Series, H8S/2623 Series

H8S/2626F-ZTAT™,

H8S/2623F-ZTAT™

H8S/2626 Series

H8S/2626 HD6432626

H8S/2625 HD6432625

H8S/2624 HD6432624

H8S/2623 Series

H8S/2623 HD6432623

H8S/2622 HD6432622

H8S/2621 HD6432621

H8S/2626F-ZTAT™

HD64F2626

H8S/2623F-ZTAT™

HD64F2623

Hardware Manual

ADE-602-164B

Rev. 3.0

5/25/00

Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

Preface

The H8S/2626 Series and H8S/2623 Series are series of high-performance microcontrollers with a

32-bit H8S/2600 CPU core, and a set of on-chip supporting modules required for system

configuration.

The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit

general registers with a 32-bit internal configuration, and a concise and optimized instruction set.

The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based

on the high-level language C can also be run efficiently.

The address space is divided into eight areas. The data bus width and access states can be selected

for each of these areas, and various kinds of memory can be connected fast and easily.

Single-power-supply flash memory (F-ZTAT™*), and mask ROM versions are available,

providing a quick and flexible response to conditions from ramp-up through full-scale volume

production, even for applications with frequently changing specifications.

On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse

generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller

area network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports.

In addition, data transfer controller (DTC) is provided, enabling high-speed data transfer without

CPU intervention.

Use of the H8S/2626 Series or H8S/2623 Series enables easy implementation of compact, high-

performance systems capable of processing large volumes of data.

This manual describes the hardware of the H8S/2626 Series and H8S/2623 Series. Refer to the

H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the

instruction set.

Note: * F-ZTAT (Flexible-ZTAT) is a trademark of Hitachi, Ltd.

Revisions and Additions in this Edition

Page Item Revisions (See Manual for Details)

All Amendments associated with addition

of H8S/2626 Series

2 to 5 Table 1-1 Overview Following items amended due to

addition of H8S/2626 Series

WDT, D/A converter, I/O ports, memory,

interrupt controller, power-down mode,

product lineup

7 Figure 1-2 Internal Block Diagram Added

9 Figure 1-4 Pin Arrangement Added

14 to 17 Table 1-3 Pin Functions in Each Operating

Mode

Added

18, 22 Table 1-4 Pin Functions Clock: OSC1, OSC2 (subclock pins)

added

I/O ports: Note added to Port A

61 Figure 2-14 Processing States Note added

62 Figure 2-15 State Transitions Note 3. added

66 2.8.6 Power-Down State Description amended

76 3.2.3 Pin Function Control Register (PFCR) Bit 5 description amended

84 Figure 4-1 Exception Sources Note 2. added

85 Table 4-2 Exception Vector Table Exception handling source ÒDirect

transitionsÓ added

90 Figure 4-4 Interrupt Sources and Number of

Interrupts

Internal interrupt ÒWDTÓ amended

99 Table 5-3 Correspondence between Interrupt

Sources and IPR Settings

Amended

103 5.3 Interrupt Sources Internal interrupt sources amended

105 to

107

Table 5-4 Interrupt Sources, Vector

Addresses, and Interrupt Priorities

Amended

130, 131 6.3.4 Operation in Transitions to Power-Down

Modes

Amended

148 7.2.6 Pin Function Control Register (PFCR) Bit 5 description amended

209 9.1 Overview Description amended

210 to

212

Table 9-1 Port Functions Ports 9, A, and F amended

230, 231 9.4 Port 9 Description of pins DA2 and DA3 added

Page Item Revisions (See Manual for Details)

232 to

239

9.5 Port A Description of pins OSC2 and OSC1

added

273 to

278

9.10 Port F Description of BUZZ pin added

397 to

416

Section 12 Watchdog Timer WDT1 related description added

524 15.2.1 Master Control Register (MCR) R/W of bits 6, 4, 3 amended

525 15.2.2 General Status Register (GSR) R/W of bits 7 to 4 amended

528 Figure 15-2 Detailed Description of One Bit Note added

529 Table 15-3 Setting Range for TSEG1 and

TSEG2 in BCR

Note added

531 15.2.4 Mailbox Configuration Register

(MBCR)

R/W of bit 8 amended

532 15.2.5 Transmit Wait Register (TXPR) R/W of bit 8 amended

533 15.2.6 Transmit Wait Cancel Register (TXCR) R/W of bit 8 amended

534 15.2.7 Transmit Acknowledge Register

(TXACK)

R/W of bit 8 amended

535 15.2.8 Abort Acknowledge Register (ABACK) R/W of bit 8 amended

536 15.2.9 Receive Complete Register (RXPR) Description amended

537 15.2.10 Remote Request Register (RFPR) Description amended

538, 540 15.2.11 Interrupt Register (IRR) R/W of bit 10 amended

Bit 8 description amended

543 to

545

15.2.13 Interrupt Mask Register (IMR) R/W of bits 8 to 5, 3, 2 amended

Bit descriptions amended

546 15.2.16 Unread Message Status Register

(UMSR)

Description amended

547, 548 15.2.17 Local Acceptance Filter Masks

(LAFML, LAFMH)

R/W of bits 12 to 10 amended

Bit descriptions amended

549, 550 15.2.18 Message Control (MC0 to MC15) R/W of MCx[1] bits amended

Description of MCx[1] bits 3 to 0

amended

553, 554 15.2.19 Message Data (MD0 to MD15) Bit descriptions amended

559 15.3.2 Initialization after Hardware Reset IRR0 Clearing Added

559 Bit Rate Settings Variable SJW restriction amended

Page Item Revisions (See Manual for Details)

563 15.3.3 Transmit Mode

Initialization (After Hardware Reset Only)

IRR0 Clearing Added

566 Message transmission and interrupts ·Message transmission completion

and interrupt Description amended

568 15.3.4 Receive Mode

Initialization (After Hardware Reset Only)

IRR0 Clearing Added

575 15.3.5 HCAN Sleep Mode

Clearing by CAN bus operation

Description amended

580 15.5 Usage Notes

1. Reset Description amended

7. Register retention during standby Added

603 to

610

Section 17 D/A Converter

[Provided in the H8S/2626 Series only]

Added

629, 630 19.5.6 Flash Memory Power Control Register

(FLPWCR)

Added

667 19.12 Flash Memory and Power-Down States Amendments associated with addition

of subclock function

675 to

686

Section 20 Clock Pulse Generator Amendments associated with addition

of subclock function

687 to

702

Section 21A Power-Down Modes

[H8S/2623 Series] (no subclock function)

Divided by series

690 21A.2.1 Standby Control Register (SBYCR) Initial value of bits 6 and 4 amended

703 to

728

Section 21B Power-Down Modes

[H8S/2626 Series] (subclock function provided)

Divided by series

708 21B.2.1 Standby Control Register (SBYCR) Initial value of bits 6 and 4 amended

729 Table 22-1 Absolute Maximum Ratings Amendments associated with addition

of pins OSC1 and OSC2

730 to

732

Table 22-2 DC Characteristics Amendments associated with addition

of pins OSC1 and OSC2

Amendments associated with addition

of subclock function

Amendments associated with addition

of D/A converter

733 Figure 22-1 Output Load Circuit Amended

734 Table 22-4 Clock Timing Amendments associated with addition

of subclock function

736 Table 22-5 Control Signal Timing Conditions: ¿ value amended

738 Table 22-6 Bus Timing Conditions: ¿ value amended

Page Item Revisions (See Manual for Details)

745, 746 Table 22-7 Timing of On-Chip Supporting

Modules

Conditions: ¿ value amended

BUZZ output delay time added

749 Figure 22-22 WDT1 Output Timing Added

750 Table 22-8 A/D Conversion Characteristics Conversion time amended

751 22.5 D/A Conversion Characteristics Added

830 to

844

B.1 Address Added

H'FDAC DADR2

H'FDAD DADR3

H'FDAE DADR23

H'FFA2 TCSR1/TCNT1

H'FFA3 TCNT1

H'FFAC FLPWCR

845 to

994

B.2 Functions Registers for which amendments have

been made in this manual

H'F800 MCR

H'F801 GSR

H'F804 MBCR

H'F806 TXPR

H'F808 TXCR

H'F80A TXACK

H'F80C ABACK

H'F812 IRR

H'F816 IMR

H'F81C LAFML

H'F81E LAFMH

H'F820ÑH'F898 MC0ÑMC15

H'F8B0ÑH'F928 MD0ÑMD15

H'FDE4 SBYCR

H'FDE6 SCKCR

H'FDE8ÑH'FDEA

MSTPCRAÑMSTPCRC

H'FDEB PFCR

H'FDEC LPWRCR

H'FE39 PADDR

H'FE40 PAPCR

H'FE47 PAODR

H'FEC0ÑH'FECC IPRAÑIPRM

H'FF09 PADR

H'FFB9 PORTA

1006 Figure C-4 (e) Port A Block Diagram (Pins

PA4 and PA5)

Amended

1016 Figure C-9 (c) Port F Block Diagram in the

H8S/2626 Series (Pin PF1)

Added

1027 Appendix F Product Code Lineup Addition of H8S/2626 Series

Contents

Section 1 Overview........................................................................................................... 1

1.1 Overview............................................................................................................................ 1

1.2 Internal Block Diagram ..................................................................................................... 6

1.3 Pin Descriptions................................................................................................................. 8

1.3.1 Pin Arrangement .................................................................................................. 8

1.3.2 Pin Functions in Each Operating Mode................................................................ 10

1.3.3 Pin Functions........................................................................................................ 18

Section 2 CPU..................................................................................................................... 23

2.1 Overview............................................................................................................................ 23

2.1.1 Features ................................................................................................................ 23

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU.................................. 24

2.1.3 Differences from H8/300 CPU............................................................................. 25

2.1.4 Differences from H8/300H CPU.......................................................................... 25

2.2 CPU Operating Modes ...................................................................................................... 26

2.3 Address Space.................................................................................................................... 31

2.4 Register Configuration ......................................................................................................32

2.4.1 Overview.............................................................................................................. 32

2.4.2 General Registers.................................................................................................. 33

2.4.3 Control Registers.................................................................................................. 34

2.4.4 Initial Register Values.......................................................................................... 36

2.5 Data Formats...................................................................................................................... 37

2.5.1 General Register Data Formats ............................................................................ 37

2.5.2 Memory Data Formats.......................................................................................... 39

2.6 Instruction Set.................................................................................................................... 40

2.6.1 Overview.............................................................................................................. 40

2.6.2 Instructions and Addressing Modes ..................................................................... 41

2.6.3 Table of Instructions Classified by Function........................................................ 43

2.6.4 Basic Instruction Formats..................................................................................... 52

2.7 Addressing Modes and Effective Address Calculation..................................................... 54

2.7.1 Addressing Mode.................................................................................................. 54

2.7.2 Effective Address Calculation.............................................................................. 57

2.8 Processing States ............................................................................................................... 61

2.8.1 Overview.............................................................................................................. 61

2.8.2 Reset State............................................................................................................ 62

2.8.3 Exception-Handling State .................................................................................... 63

2.8.4 Program Execution State...................................................................................... 66

2.8.5 Bus-Released State............................................................................................... 66

2.8.6 Power-Down State................................................................................................ 66

2.9 Basic Timing...................................................................................................................... 67

2.9.1 Overview.............................................................................................................. 67

2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 67

2.9.3 On-Chip Supporting Module Access Timing....................................................... 69

2.9.4 On-Chip HCAN Module Access Timing ............................................................. 71

2.9.5 External Address Space Access Timing............................................................... 72

2.10 Usage Note ........................................................................................................................ 72

2.10.1 TAS Instruction.................................................................................................... 72

Section 3 MCU Operating Modes................................................................................ 73

3.1 Overview............................................................................................................................ 73

3.1.1 Operating Mode Selection.................................................................................... 73

3.1.2 Register Configuration ......................................................................................... 74

3.2 Register Descriptions......................................................................................................... 74

3.2.1 Mode Control Register (MDCR).......................................................................... 74

3.2.2 System Control Register (SYSCR) ...................................................................... 75

3.2.3 Pin Function Control Register (PFCR) ................................................................ 76

3.3 Operating Mode Descriptions............................................................................................ 78

3.3.1 Mode 4.................................................................................................................. 78

3.3.2 Mode 5.................................................................................................................. 78

3.3.3 Mode 6.................................................................................................................. 78

3.3.4 Mode 7.................................................................................................................. 78

3.4 Pin Functions in Each Operating Mode............................................................................. 79

3.5 Address Map in Each Operating Mode ............................................................................. 79

Section 4 Exception Handling........................................................................................ 83

4.1 Overview............................................................................................................................ 83

4.1.1 Exception Handling Types and Priority ............................................................... 83

4.1.2 Exception Handling Operation............................................................................. 84

4.1.3 Exception Vector Table........................................................................................ 84

4.2 Reset.................................................................................................................................. 86

4.2.1 Overview.............................................................................................................. 86

4.2.2 Reset Sequence..................................................................................................... 86

4.2.3 Interrupts after Reset............................................................................................ 88

4.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 88

4.3 Traces ................................................................................................................................ 89

4.4 Interrupts............................................................................................................................ 90

4.5 Trap Instruction ................................................................................................................. 91

4.6 Stack Status after Exception Handling.............................................................................. 92

4.7 Notes on Use of the Stack.................................................................................................. 93

Section 5 Interrupt Controller........................................................................................ 95

5.1 Overview............................................................................................................................ 95

iii

5.1.1 Features ................................................................................................................ 95

5.1.2 Block Diagram ..................................................................................................... 96

5.1.3 Pin Configuration ................................................................................................. 97

5.1.4 Register Configuration ......................................................................................... 97

5.2 Register Descriptions......................................................................................................... 98

5.2.1 System Control Register (SYSCR) ...................................................................... 98

5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)........................... 99

5.2.3 IRQ Enable Register (IER) .................................................................................. 100

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 101

5.2.5 IRQ Status Register (ISR).................................................................................... 102

5.3 Interrupt Sources................................................................................................................ 103

5.3.1 External Interrupts................................................................................................ 103

5.3.2 Internal Interrupts................................................................................................. 104

5.3.3 Interrupt Exception Handling Vector Table......................................................... 104

5.4 Interrupt Operation............................................................................................................ 108

5.4.1 Interrupt Control Modes and Interrupt Operation................................................ 108

5.4.2 Interrupt Control Mode 0...................................................................................... 111

5.4.3 Interrupt Control Mode 2...................................................................................... 113

5.4.4 Interrupt Exception Handling Sequence .............................................................. 115

5.4.5 Interrupt Response Times..................................................................................... 116

5.5 Usage Notes....................................................................................................................... 117

5.5.1 Contention between Interrupt Generation and Disabling..................................... 117

5.5.2 Instructions that Disable Interrupts ...................................................................... 118

5.5.3 Times when Interrupts are Disabled..................................................................... 118

5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 119

5.6 DTC Activation by Interrupt ............................................................................................. 119

5.6.1 Overview.............................................................................................................. 119

5.6.2 Block Diagram...................................................................................................... 119

5.6.3 Operation.............................................................................................................. 120

Section 6 PC Break Controller (PBC)......................................................................... 123

6.1 Overview............................................................................................................................ 123

6.1.1 Features ................................................................................................................ 123

6.1.2 Block Diagram...................................................................................................... 124

6.1.3 Register Configuration ......................................................................................... 125

6.2 Register Descriptions......................................................................................................... 125

6.2.1 Break Address Register A (BARA) ..................................................................... 125

6.2.2 Break Address Register B (BARB)...................................................................... 126

6.2.3 Break Control Register A (BCRA) ...................................................................... 126

6.2.4 Break Control Register B (BCRB)....................................................................... 128

6.2.5 Module Stop Control Register C (MSTPCRC).................................................... 128

6.3 Operation ........................................................................................................................... 129

6.3.1 PC Break Interrupt Due to Instruction Fetch........................................................ 129

6.3.2 PC Break Interrupt Due to Data Access............................................................... 129

6.3.3 Notes on PC Break Interrupt Handling ................................................................ 130

6.3.4 Operation in Transitions to Power-Down Modes ................................................ 130

6.3.5 PC Break Operation in Continuous Data Transfer............................................... 131

6.3.6 When Instruction Execution is Delayed by One State ......................................... 132

6.3.7 Additional Notes .................................................................................................. 133

Section 7 Bus Controller.................................................................................................. 135

7.1 Overview............................................................................................................................ 135

7.1.1 Features ................................................................................................................ 135

7.1.2 Block Diagram...................................................................................................... 136

7.1.3 Pin Configuration ................................................................................................. 137

7.1.4 Register Configuration ......................................................................................... 138

7.2 Register Descriptions......................................................................................................... 139

7.2.1 Bus Width Control Register (ABWCR)............................................................... 139

7.2.2 Access State Control Register (ASTCR).............................................................. 140

7.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 141

7.2.4 Bus Control Register H (BCRH).......................................................................... 145

7.2.5 Bus Control Register L (BCRL)........................................................................... 147

7.2.6 Pin Function Control Register (PFCR) ................................................................ 148

7.3 Overview of Bus Control................................................................................................... 150

7.3.1 Area Partitioning .................................................................................................. 150

7.3.2 Bus Specifications................................................................................................ 151

7.3.3 Memory Interfaces................................................................................................ 152

7.3.4 Interface Specifications for Each Area................................................................. 153

7.4 Basic Bus Interface............................................................................................................ 154

7.4.1 Overview.............................................................................................................. 154

7.4.2 Data Size and Data Alignment ............................................................................. 154

7.4.3 Valid Strobes........................................................................................................ 156

7.4.4 Basic Timing ........................................................................................................ 157

7.4.5 Wait Control......................................................................................................... 165

7.5 Burst ROM Interface ......................................................................................................... 167

7.5.1 Overview.............................................................................................................. 167

7.5.2 Basic Timing ........................................................................................................ 167

7.5.3 Wait Control......................................................................................................... 169

7.6 Idle Cycle........................................................................................................................... 170

7.6.1 Operation.............................................................................................................. 170

7.6.2 Pin States in Idle Cycle ........................................................................................ 172

7.7 Write Data Buffer Function............................................................................................... 173

7.8 Bus Release........................................................................................................................ 174

7.8.1 Overview.............................................................................................................. 174

7.8.2 Operation.............................................................................................................. 174

7.8.3 Pin States in External Bus Released State............................................................ 175

7.8.4 Transition Timing................................................................................................. 176

7.8.5 Usage Note ........................................................................................................... 177

7.9 Bus Arbitration.................................................................................................................. 177

7.9.1 Overview.............................................................................................................. 177

7.9.2 Operation.............................................................................................................. 177

7.9.3 Bus Transfer Timing ............................................................................................ 178

7.10 Resets and the Bus Controller............................................................................................ 178

Section 8 Data Transfer Controller (DTC) ................................................................ 179

8.1 Overview............................................................................................................................ 179

8.1.1 Features ................................................................................................................ 179

8.1.2 Block Diagram...................................................................................................... 180

8.1.3 Register Configuration ......................................................................................... 181

8.2 Register Descriptions......................................................................................................... 182

8.2.1 DTC Mode Register A (MRA)............................................................................. 182

8.2.2 DTC Mode Register B (MRB)............................................................................. 184

8.2.3 DTC Source Address Register (SAR).................................................................. 185

8.2.4 DTC Destination Address Register (DAR).......................................................... 185

8.2.5 DTC Transfer Count Register A (CRA) .............................................................. 185

8.2.6 DTC Transfer Count Register B (CRB)............................................................... 186

8.2.7 DTC Enable Registers (DTCER) ......................................................................... 186

8.2.8 DTC Vector Register (DTVECR)........................................................................ 187

8.2.9 Module Stop Control Register A (MSTPCRA).................................................... 188

8.3 Operation ........................................................................................................................... 189

8.3.1 Overview.............................................................................................................. 189

8.3.2 Activation Sources................................................................................................ 191

8.3.3 DTC Vector Table................................................................................................ 192

8.3.4 Location of Register Information in Address Space............................................ 195

8.3.5 Normal Mode........................................................................................................ 196

8.3.6 Repeat Mode ........................................................................................................ 197

8.3.7 Block Transfer Mode............................................................................................ 198

8.3.8 Chain Transfer...................................................................................................... 200

8.3.9 Operation Timing ................................................................................................. 201

8.3.10 Number of DTC Execution States........................................................................ 202

8.3.11 Procedures for Using DTC................................................................................... 204

8.3.12 Examples of Use of the DTC................................................................................ 205

8.4 Interrupts............................................................................................................................ 208

8.5 Usage Notes....................................................................................................................... 208

Section 9 I/O Ports ............................................................................................................ 209

9.1 Overview............................................................................................................................ 209

9.2 Port 1.................................................................................................................................. 213

9.2.1 Overview.............................................................................................................. 213

9.2.2 Register Configuration ......................................................................................... 214

9.2.3 Pin Functions........................................................................................................ 216

9.3 Port 4.................................................................................................................................. 228

9.3.1 Overview.............................................................................................................. 228

9.3.2 Register Configuration ......................................................................................... 229

9.3.3 Pin Functions........................................................................................................ 229

9.4 Port 9.................................................................................................................................. 230

9.4.1 Overview.............................................................................................................. 230

9.4.2 Register Configuration ......................................................................................... 231

9.4.3 Pin Functions........................................................................................................ 231

9.5 Port A................................................................................................................................. 232

9.5.1 Overview.............................................................................................................. 232

9.5.2 Register Configuration ......................................................................................... 233

9.5.3 Pin Functions........................................................................................................ 236

9.5.4 MOS Input Pull-Up Function............................................................................... 239

9.6 Port B................................................................................................................................. 240

9.6.1 Overview.............................................................................................................. 240

9.6.2 Register Configuration ......................................................................................... 241

9.6.3 Pin Functions........................................................................................................ 243

9.6.4 MOS Input Pull-Up Function............................................................................... 252

9.7 Port C................................................................................................................................. 253

9.7.1 Overview.............................................................................................................. 253

9.7.2 Register Configuration ......................................................................................... 254

9.7.3 Pin Functions........................................................................................................ 257

9.7.4 MOS Input Pull-Up Function............................................................................... 262

9.8 Port D................................................................................................................................. 263

9.8.1 Overview.............................................................................................................. 263

9.8.2 Register Configuration ......................................................................................... 264

9.8.3 Pin Functions........................................................................................................ 266

9.8.4 MOS Input Pull-Up Function............................................................................... 267

9.9 Port E................................................................................................................................. 268

9.9.1 Overview.............................................................................................................. 268

9.9.2 Register Configuration ......................................................................................... 269

9.9.3 Pin Functions........................................................................................................ 271

9.9.4 MOS Input Pull-Up Function............................................................................... 272

9.10 Port F ................................................................................................................................. 273

9.10.1 Overview.............................................................................................................. 273

9.10.2 Register Configuration ......................................................................................... 274

9.10.3 Pin Functions........................................................................................................ 276

Section 10 16-Bit Timer Pulse Unit (TPU).................................................................. 279

10.1 Overview............................................................................................................................ 279

10.1.1 Features ................................................................................................................ 279

vii

10.1.2 Block Diagram...................................................................................................... 283

10.1.3 Pin Configuration ................................................................................................. 284

10.1.4 Register Configuration ......................................................................................... 286

10.2 Register Descriptions......................................................................................................... 288

10.2.1 Timer Control Register (TCR) ............................................................................. 288

10.2.2 Timer Mode Register (TMDR) ............................................................................ 293

10.2.3 Timer I/O Control Register (TIOR) ..................................................................... 295

10.2.4 Timer Interrupt Enable Register (TIER).............................................................. 308

10.2.5 Timer Status Register (TSR)................................................................................ 311

10.2.6 Timer Counter (TCNT)........................................................................................ 315

10.2.7 Timer General Register (TGR) ............................................................................ 316

10.2.8 Timer Start Register (TSTR)................................................................................ 317

10.2.9 Timer Synchro Register (TSYR).......................................................................... 318

10.2.10 Module Stop Control Register A (MSTPCRA).................................................... 319

10.3 Interface to Bus Master...................................................................................................... 320

10.3.1 16-Bit Registers.................................................................................................... 320

10.3.2 8-Bit Registers...................................................................................................... 320

10.4 Operation ........................................................................................................................... 322

10.4.1 Overview.............................................................................................................. 322

10.4.2 Basic Functions .................................................................................................... 323

10.4.3 Synchronous Operation........................................................................................ 329

10.4.4 Buffer Operation .................................................................................................. 331

10.4.5 Cascaded Operation.............................................................................................. 335

10.4.6 PWM Modes ........................................................................................................ 337

10.4.7 Phase Counting Mode .......................................................................................... 342

10.5 Interrupts............................................................................................................................ 349

10.5.1 Interrupt Sources and Priorities............................................................................ 349

10.5.2 DTC Activation.................................................................................................... 351

10.5.3 A/D Converter Activation.................................................................................... 351

10.6 Operation Timing .............................................................................................................. 352

10.6.1 Input/Output Timing ............................................................................................ 352

10.6.2 Interrupt Signal Timing........................................................................................ 356

10.7 Usage Notes....................................................................................................................... 360

Section 11 Programmable Pulse Generator (PPG) .................................................... 371

11.1 Overview............................................................................................................................ 371

11.1.1 Features ................................................................................................................ 371

11.1.2 Block Diagram...................................................................................................... 372

11.1.3 Pin Configuration ................................................................................................. 373

11.1.4 Registers............................................................................................................... 374

11.2 Register Descriptions......................................................................................................... 375

11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 375

11.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 376

viii

11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 377

11.2.4 Notes on NDR Access.......................................................................................... 377

11.2.5 PPG Output Control Register (PCR).................................................................... 379

11.2.6 PPG Output Mode Register (PMR)...................................................................... 381

11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 384

11.2.8 Module Stop Control Register A (MSTPCRA).................................................... 384

11.3 Operation ........................................................................................................................... 385

11.3.1 Overview.............................................................................................................. 385

11.3.2 Output Timing...................................................................................................... 386

11.3.3 Normal Pulse Output............................................................................................ 387

11.3.4 Non-Overlapping Pulse Output............................................................................ 389

11.3.5 Inverted Pulse Output........................................................................................... 392

11.3.6 Pulse Output Triggered by Input Capture ............................................................ 393

11.4 Usage Notes....................................................................................................................... 394

Section 12 Watchdog Timer ............................................................................................. 397

12.1 Overview............................................................................................................................ 397

12.1.1 Features ................................................................................................................ 397

12.1.2 Block Diagram...................................................................................................... 398

12.1.3 Pin Configuration ................................................................................................. 400

12.1.4 Register Configuration ......................................................................................... 400

12.2 Register Descriptions......................................................................................................... 401

12.2.1 Timer Counter (TCNT)........................................................................................ 401

12.2.2 Timer Control/Status Register (TCSR)................................................................ 401

12.2.3 Reset Control/Status Register (RSTCSR)............................................................ 406

12.2.4 Pin Function Control Register (PFCR) ................................................................ 407

12.2.5 Notes on Register Access..................................................................................... 408

12.3 Operation ........................................................................................................................... 410

12.3.1 Watchdog Timer Operation.................................................................................. 410

12.3.2 Interval Timer Operation...................................................................................... 412

12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 412

12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 413

12.4 Interrupts............................................................................................................................ 414

12.5 Usage Notes....................................................................................................................... 414

12.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 414

12.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 415

12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 415

12.5.4 System Reset by WDTOVF Signal...................................................................... 415

12.5.5 Internal Reset in Watchdog Timer Mode............................................................. 415

Section 13 Serial Communication Interface (SCI) .................................................... 417

13.1 Overview............................................................................................................................ 417

13.1.1 Features ................................................................................................................ 417

13.1.2 Block Diagram...................................................................................................... 419

13.1.3 Pin Configuration ................................................................................................. 420

13.1.4 Register Configuration ......................................................................................... 421

13.2 Register Descriptions......................................................................................................... 422

13.2.1 Receive Shift Register (RSR)............................................................................... 422

13.2.2 Receive Data Register (RDR) .............................................................................. 422

13.2.3 Transmit Shift Register (TSR).............................................................................. 423

13.2.4 Transmit Data Register (TDR)............................................................................. 423

13.2.5 Serial Mode Register (SMR)................................................................................ 424

13.2.6 Serial Control Register (SCR).............................................................................. 427

13.2.7 Serial Status Register (SSR)................................................................................. 431

13.2.8 Bit Rate Register (BRR)....................................................................................... 435

13.2.9 Smart Card Mode Register (SCMR).................................................................... 444

13.2.10 Module Stop Control Register B (MSTPCRB).................................................... 445

13.3 Operation ........................................................................................................................... 447

13.3.1 Overview.............................................................................................................. 447

13.3.2 Operation in Asynchronous Mode........................................................................ 449

13.3.3 Multiprocessor Communication Function............................................................ 460

13.3.4 Operation in Clocked Synchronous Mode ........................................................... 468

13.4 SCI Interrupts .................................................................................................................... 476

13.5 Usage Notes....................................................................................................................... 478

Section 14 Smart Card Interface...................................................................................... 487

14.1 Overview............................................................................................................................ 487

14.1.1 Features ................................................................................................................ 487

14.1.2 Block Diagram...................................................................................................... 488

14.1.3 Pin Configuration ................................................................................................. 489

14.1.4 Register Configuration ......................................................................................... 490

14.2 Register Descriptions......................................................................................................... 491

14.2.1 Smart Card Mode Register (SCMR).................................................................... 491

14.2.2 Serial Status Register (SSR)................................................................................. 493

14.2.3 Serial Mode Register (SMR)................................................................................ 495

14.2.4 Serial Control Register (SCR).............................................................................. 497

14.3 Operation ........................................................................................................................... 498

14.3.1 Overview.............................................................................................................. 498

14.3.2 Pin Connections.................................................................................................... 498

14.3.3 Data Format.......................................................................................................... 500

14.3.4 Register Settings................................................................................................... 502

14.3.5 Clock .................................................................................................................... 504

14.3.6 Data Transfer Operations ..................................................................................... 506

14.3.7 Operation in GSM Mode...................................................................................... 513

14.3.8 Operation in Block Transfer Mode ...................................................................... 514

14.4 Usage Notes....................................................................................................................... 515

Section 15 Hitachi Controller Area Network (HCAN)............................................ 519

15.1 Overview............................................................................................................................ 519

15.1.1 Features ................................................................................................................ 519

15.1.2 Block Diagram...................................................................................................... 520

15.1.3 Pin Configuration ................................................................................................. 521

15.1.4 Register Configuration ......................................................................................... 522

15.2 Register Descriptions......................................................................................................... 524

15.2.1 Master Control Register (MCR)........................................................................... 524

15.2.2 General Status Register (GSR)............................................................................. 525

15.2.3 Bit Configuration Register (BCR)........................................................................ 527

15.2.4 Mailbox Configuration Register (MBCR)............................................................ 531

15.2.5 Transmit Wait Register (TXPR) .......................................................................... 532

15.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 533

15.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 534

15.2.8 Abort Acknowledge Register (ABACK).............................................................. 535

15.2.9 Receive Complete Register (RXPR).................................................................... 536

15.2.10 Remote Request Register (RFPR)........................................................................ 537

15.2.11 Interrupt Register (IRR) ....................................................................................... 538

15.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 542

15.2.13 Interrupt Mask Register (IMR) ............................................................................ 543

15.2.14 Receive Error Counter (REC) .............................................................................. 545

15.2.15 Transmit Error Counter (TEC)............................................................................. 546

15.2.16 Unread Message Status Register (UMSR) ........................................................... 546

15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 547

15.2.18 Message Control (MC0 to MC15)........................................................................ 549

15.2.19 Message Data (MD0 to MD15)............................................................................ 553

15.2.20 Module Stop Control Register C (MSTPCRC).................................................... 555

15.3 Operation ........................................................................................................................... 556

15.3.1 Hardware and Software Resets............................................................................. 556

15.3.2 Initialization after Hardware Reset ...................................................................... 559

15.3.3 Transmit Mode ..................................................................................................... 562

15.3.4 Receive Mode....................................................................................................... 568

15.3.5 HCAN Sleep Mode .............................................................................................. 574

15.3.6 HCAN Halt Mode ................................................................................................ 576

15.3.7 Interrupt Interface................................................................................................. 576

15.3.8 DTC Interface....................................................................................................... 578

15.4 CAN Bus Interface............................................................................................................ 579

15.5 Usage Notes....................................................................................................................... 580

Section 16 A/D Converter ................................................................................................. 581

16.1 Overview............................................................................................................................ 581

16.1.1 Features ................................................................................................................ 581

16.1.2 Block Diagram...................................................................................................... 582

16.1.3 Pin Configuration ................................................................................................. 583

16.1.4 Register Configuration ......................................................................................... 584

16.2 Register Descriptions......................................................................................................... 585

16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 585

16.2.2 A/D Control/Status Register (ADCSR)................................................................ 586

16.2.3 A/D Control Register (ADCR)............................................................................. 589

16.2.4 Module Stop Control Register A (MSTPCRA).................................................... 590

16.3 Interface to Bus Master...................................................................................................... 591

16.4 Operation ........................................................................................................................... 592

16.4.1 Single Mode (SCAN = 0)..................................................................................... 592

16.4.2 Scan Mode (SCAN = 1) ....................................................................................... 594

16.4.3 Input Sampling and A/D Conversion Time.......................................................... 596

16.4.4 External Trigger Input Timing ............................................................................. 597

16.5 Interrupts............................................................................................................................ 598

16.6 Usage Notes....................................................................................................................... 598

Section 17 D/A Converter [Provided in the H8S/2626 Series only].................... 603

17.1 Overview............................................................................................................................ 603

17.1.1 Features ................................................................................................................ 603

17.1.2 Block Diagram...................................................................................................... 604

17.1.3 Pin Configuration ................................................................................................. 605

17.1.4 Register Configuration ......................................................................................... 605

17.2 Register Descriptions......................................................................................................... 606

17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3).................................................. 606

17.2.2 D/A Control Register 23 (DACR23).................................................................... 606

17.2.3 Module Stop Control Register C (MSTPCRC).................................................... 608

17.3 Operation ........................................................................................................................... 609

Section 18 RAM................................................................................................................... 611

18.1 Overview............................................................................................................................ 611

18.1.1 Block Diagram...................................................................................................... 611

18.1.2 Register Configuration ......................................................................................... 612

18.2 Register Descriptions......................................................................................................... 612

18.2.1 System Control Register (SYSCR) ...................................................................... 612

18.3 Operation ........................................................................................................................... 613

18.4 Usage Notes....................................................................................................................... 613

Section 19 ROM................................................................................................................... 615

19.1 Features.............................................................................................................................. 615

19.2 Overview............................................................................................................................ 616

19.2.1 Block Diagram...................................................................................................... 616

19.2.2 Mode Transitions.................................................................................................. 617

19.2.3 On-Board Programming Modes........................................................................... 618

xii

19.2.4 Flash Memory Emulation in RAM....................................................................... 620

19.2.5 Differences between Boot Mode and User Program Mode.................................. 621

19.2.6 Block Configuration............................................................................................. 622

19.3 Pin Configuration .............................................................................................................. 622

19.4 Register Configuration ...................................................................................................... 623

19.5 Register Descriptions......................................................................................................... 623

19.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 623

19.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 626

19.5.3 Erase Block Register 1 (EBR1)............................................................................ 627

19.5.4 Erase Block Register 2 (EBR2)............................................................................ 627

19.5.5 RAM Emulation Register (RAMER)................................................................... 628

19.5.6 Flash Memory Power Control Register (FLPWCR)............................................ 629

19.5.7 Serial Control Register X (SCRX)....................................................................... 630

19.6 On-Board Programming Modes........................................................................................ 631

19.6.1 Boot Mode............................................................................................................ 631

19.6.2 User Program Mode ............................................................................................. 636

19.7 Flash Memory Programming/Erasing................................................................................ 638

19.7.1 Program Mode...................................................................................................... 640

19.7.2 Program-Verify Mode.......................................................................................... 641

19.7.3 Erase Mode........................................................................................................... 645

19.7.4 Erase-Verify Mode............................................................................................... 645

19.8 Protection........................................................................................................................... 647

19.8.1 Hardware Protection............................................................................................. 647

19.8.2 Software Protection.............................................................................................. 648

19.8.3 Error Protection.................................................................................................... 649

19.9 Flash Memory Emulation in RAM.................................................................................... 651

19.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 653

19.11 Flash Memory Programmer Mode .................................................................................... 653

19.11.1 Socket Adapter Pin Correspondence Diagram................................................... 654

19.11.2 Programmer Mode Operation............................................................................. 656

19.11.3 Memory Read Mode........................................................................................... 657

19.11.4 Auto-Program Mode .......................................................................................... 660

19.11.5 Auto-Erase Mode................................................................................................ 662

19.11.6 Status Read Mode............................................................................................... 664

19.11.7 Status Polling...................................................................................................... 665

19.11.8 Programmer Mode Transition Time................................................................... 665

19.11.9 Notes on Memory Programming........................................................................ 666

19.12 Flash Memory and Power-Down States............................................................................ 667

19.12.1 Note on Power-Down States .............................................................................. 667

19.13 Flash Memory Programming and Erasing Precautions..................................................... 668

19.14 Note on Switching from F-ZTAT Version to Mask ROM Version.................................. 673

xiii

Section 20 Clock Pulse Generator .................................................................................. 675

20.1 Overview............................................................................................................................ 675

20.1.1 Block Diagram...................................................................................................... 676

20.1.2 Register Configuration ......................................................................................... 676

20.2 Register Descriptions......................................................................................................... 677

20.2.1 System Clock Control Register (SCKCR) ........................................................... 677

20.2.2 Low-Power Control Register (LPWRCR)............................................................ 678

20.3 Oscillator............................................................................................................................ 679

20.3.1 Connecting a Crystal Resonator........................................................................... 679

20.3.2 External Clock Input ............................................................................................ 682

20.4 PLL Circuit........................................................................................................................ 684

20.5 Medium-Speed Clock Divider........................................................................................... 684

20.6 Bus Master Clock Selection Circuit.................................................................................. 684

20.7 Subclock Oscillator............................................................................................................ 685

20.8 Subclock Waveform Shaping Circuit................................................................................ 686

20.9 Note on Crystal Resonator................................................................................................. 686

Section 21A Power-Down Modes [H8S/2623 Series] ............................................. 687

21A.1 Overview........................................................................................................................ 687

21A.1.1 Register Configuration ................................................................................... 690

21A.2 Register Descriptions...................................................................................................... 690

21A.2.1 Standby Control Register (SBYCR) .............................................................. 690

21A.2.2 System Clock Control Register (SCKCR) ..................................................... 692

21A.2.3 Low-Power Control Register (LPWRCR)...................................................... 693

21A.2.4 Module Stop Control Register (MSTPCR).................................................... 694

21A.3 Medium-Speed Mode..................................................................................................... 695

21A.4 Sleep Mode..................................................................................................................... 696

21A.4.1 Sleep Mode..................................................................................................... 696

21A.4.2 Exiting Sleep Mode........................................................................................ 696

21A.5 Module Stop Mode......................................................................................................... 696

21A.5.1 Module Stop Mode......................................................................................... 696

21A.5.2 Usage Notes.................................................................................................... 698

21A.6 Software Standby Mode................................................................................................. 698

21A.6.1 Software Standby Mode ................................................................................. 698

21A.6.2 Clearing Software Standby Mode.................................................................. 698

21A.6.3 Setting Oscillation Stabilization Time after Clearing Software

Standby Mode ................................................................................................ 699

21A.6.4 Software Standby Mode Application Example.............................................. 700

21A.6.5 Usage Notes.................................................................................................... 701

21A.7 Hardware Standby Mode................................................................................................ 701

21A.7.1 Hardware Standby Mode................................................................................ 701

21A.7.2 Hardware Standby Mode Timing................................................................... 702

21A.8 ø Clock Output Disabling Function................................................................................ 702

xiv

Section 21B Power-Down Modes [H8S/2626 Series] ............................................. 703

21B.1 Overview........................................................................................................................ 703

21B.1.1 Register Configuration ................................................................................... 707

21B.2 Register Descriptions...................................................................................................... 708

21B.2.1 Standby Control Register (SBYCR) .............................................................. 708

21B.2.2 System Clock Control Register (SCKCR) ..................................................... 710

21B.2.3 Low-Power Control Register (LPWRCR)...................................................... 711

21B.2.4 Timer Control/Status Register (TCSR).......................................................... 713

21B.2.5 Module Stop Control Register (MSTPCR).................................................... 715

21B.3 Medium-Speed Mode..................................................................................................... 716

21B.4 Sleep Mode..................................................................................................................... 717

21B.4.1 Sleep Mode..................................................................................................... 717

21B.4.2 Exiting Sleep Mode........................................................................................ 717

21B.5 Module Stop Mode......................................................................................................... 717

21B.5.1 Module Stop Mode......................................................................................... 717

21B.5.2 Usage Notes.................................................................................................... 719

21B.6 Software Standby Mode................................................................................................. 719

21B.6.1 Software Standby Mode ................................................................................. 719

21B.6.2 Clearing Software Standby Mode .................................................................. 719

21B.6.3 Setting Oscillation Stabilization Time after Clearing Software

Standby Mode ................................................................................................ 720

21B.6.4 Software Standby Mode Application Example.............................................. 721

21B.6.5 Usage Notes.................................................................................................... 722

21B.7 Hardware Standby Mode................................................................................................ 722

21B.7.1 Hardware Standby Mode................................................................................ 722

21B.7.2 Hardware Standby Mode Timing................................................................... 723

21B.8 Watch Mode ................................................................................................................... 723

21B.8.1 Watch Mode ................................................................................................... 723

21B.8.2 Exiting Watch Mode ...................................................................................... 724

21B.8.3 Notes............................................................................................................... 724

21B.9 Sub-Sleep Mode ............................................................................................................. 725

21B.9.1 Sub-Sleep Mode ............................................................................................. 725

21B.9.2 Exiting Sub-Sleep Mode ................................................................................ 725

21B.10 Sub-Active Mode............................................................................................................ 726

21B.10.1 Sub-Active Mode............................................................................................ 726

21B.10.2 Exiting Sub-Active Mode............................................................................... 726

21B.11 Direct Transitions........................................................................................................... 727

21B.11.1 Overview of Direct Transitions...................................................................... 727

21B.12 ø Clock Output Disabling Function................................................................................ 727

Section 22 Electrical Characteristics.............................................................................. 729

22.1 Absolute Maximum Ratings.............................................................................................. 729

22.2 DC Characteristics............................................................................................................. 730

22.3 AC Characteristics............................................................................................................. 733

22.3.1 Clock Timing........................................................................................................ 734

22.3.2 Control Signal Timing.......................................................................................... 735

22.3.3 Bus Timing........................................................................................................... 737

22.3.4 Timing of On-Chip Supporting Modules............................................................. 743

22.4 A/D Conversion Characteristics........................................................................................ 747

22.5 D/A Conversion Characteristics........................................................................................ 748

22.6 Flash Memory Characteristics........................................................................................... 749

22.7 Usage Note ........................................................................................................................ 750

Appendix A Instruction Set.............................................................................................. 751

A.1 Instruction List................................................................................................................... 751

A.2 Instruction Codes............................................................................................................... 776

A.3 Operation Code Map.......................................................................................................... 791

A.4 Number of States Required for Instruction Execution...................................................... 795

A.5 Bus States During Instruction Execution .......................................................................... 806

A.6 Condition Code Modification............................................................................................ 820

Appendix B Internal I/O Register.................................................................................. 826

B.1 Address.............................................................................................................................. 826

B.2 Functions............................................................................................................................ 841

Appendix C I/O Port Block Diagrams.......................................................................... 991

C.1 Port 1 Block Diagrams ...................................................................................................... 991

C.2 Port 4 Block Diagram........................................................................................................ 997

C.3 Port 9 Block Diagram........................................................................................................ 997

C.4 Port A Block Diagrams...................................................................................................... 998

C.5 Port B Block Diagram ....................................................................................................... 1003

C.6 Port C Block Diagrams...................................................................................................... 1004

C.7 Port D Block Diagram ....................................................................................................... 1008

C.8 Port E Block Diagram........................................................................................................ 1009

C.9 Port F Block Diagrams...................................................................................................... 1010

Appendix D Pin States....................................................................................................... 1019

D.1 Port States in Each Mode .................................................................................................. 1019

Appendix E Timing of Transition to and Recovery from Hardware

Standby Mode.............................................................................................. 1022

Appendix F Product Code Lineup................................................................................. 1023

Appendix G Package Dimensions.................................................................................. 1024

xvi

Section 1 Overview

1.1 Overview

The H8S/2626 Series and H8S/2623 Series are series of microcomputers (MCUs) that integrate

peripheral functions required for system configuration together with an H8S/2600 CPU employing

an original Hitachi architecture.

The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general

registers and a concise, optimized instruction set designed for high-speed operation, and can

address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300

and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,

H8/300L, or H8/300H Series.

On-chip peripheral functions required for system configuration include a data transfer controller

(DTC) bus master, ROM and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse

generator (PPG), watchdog timer (WDT), serial communication interface (SCI), Hitachi controller

area network (HCAN), A/D converter, D/A converter (H8S/2626 Series only), and I/O ports.

The on-chip ROM is 256-kbyte flash memory (F-ZTAT™)* or 256-, 128-, or 64-kbyte mask

ROM. The ROM is connected to the CPU by a 16-bit data bus, enabling both byte and word data

to be accessed in one state. Instruction fetching has been speeded up, and processing speed

increased.

Four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or

external expansion mode.

The features of the H8S/2626 Series and H8S/2623 Series are shown in table 1-1.

Note: * F-ZTAT is a trademark of Hitachi, Ltd.

Table 1-1 Overview

Item Specifications

CPU • General-register machine

 Sixteen 16-bit general registers

(also usable as sixteen 8-bit registers or eight 32-bit registers)

• High-speed operation suitable for realtime control

 Maximum operating frequency: 20 MHz

 High-speed arithmetic operations

8/16/32-bit register-register add/subtract: 50 ns

16 × 16-bit register-register multiply: 200 ns

16 × 16 + 42-bit multiply and accumulate: 200 ns

32 ÷ 16-bit register-register divide: 1000 ns

• Instruction set suitable for high-speed operation

 69 basic instructions

 8/16/32-bit move/arithmetic and logic instructions

 Unsigned/signed multiply and divide instructions

 Multiply-and accumulate instruction

 Powerful bit-manipulation instructions

• Two CPU operating modes

 Normal mode: 64-kbyte address space

(Not available in the H8S/2626 Series or H8S/2623 Series)

 Advanced mode: 16-Mbyte address space

Bus controller • Address space divided into 8 areas, with bus specifications settable

independently for each area

• Choice of 8-bit or 16-bit access space for each area

• 2-state or 3-state access space can be designated for each area

• Number of program wait states can be set for each area

• Burst ROM directly connectable

• External bus release function

PC break

controller • Supports debugging functions by means of PC break interrupts

• Two break channels

Item Specifications

Data transfer

controller (DTC) • Can be activated by internal interrupt or software

• Multiple transfers or multiple types of transfer possible for one activation

source

• Transfer possible in repeat mode, block transfer mode, etc.

• Request can be sent to CPU for interrupt that activated DTC

16-bit timer-pulse

unit (TPU) • 6-channel 16-bit timer

• Pulse input/output processing capability for up to 16 pins

• Automatic 2-phase encoder count capability

Programmable

pulse generator

(PPG)

• Maximum 8-bit pulse output possible with TPU as time base

• Output trigger selectable in 4-bit groups

• Non-overlap margin can be set

• Direct output or inverse output setting

Watchdog timer

(WDT), 2 channels

(H8S/2626 Series)

• Watchdog timer or interval timer selectable

• Subclock operation possible (one channel only)

Watchdog timer

(WDT), 1 channel

(H8S/2623 Series)

• Watchdog timer or interval timer selectable

Serial communi-

cation interface

(SCI), 3 channels

(SCI0 to SCI2)

• Asynchronous mode or synchronous mode selectable

• Multiprocessor communication function

• Smart card interface function

Hitachi controller

area network

(HCAN),

1 channel

• CAN: Ver. 2.0B compliant

• Buffer size: 15 transmit/receive buffers, one transmit-only buffer

• Receive message filtering

A/D converter • Resolution: 10 bits

• Input: 16 channels

• 13.3 µs minimum conversion time (at 20 MHz operation)

• Single or scan mode selectable

• Sample-and-hold function

• A/D conversion can be activated by external trigger or timer trigger

D/A converter

(H8S/2626 Series

only)

• Resolution: 8 bits

• Output: 2 channels

Item Specifications

I/O ports

(H8S/2626 Series) • 51 input/output pins, 17 input-only pins

I/O ports

(H8S/2623 Series) • 53 input/output pins, 17 input-only pins

Memory • Flash memory or masked ROM

• High-speed static RAM

Product Name ROM RAM

H8S/2626, H8S/2623 256 kbytes 12 kbytes

H8S/2625*, H8S/2622 128 kbytes 8 kbytes

H8S/2624*, H8S/2621 64 kbytes 4 kbytes

Note: * In planning stage

Interrupt controller • Seven external interrupt pins (NMI, IRQ0 to IRQ5)

• Internal interrupt sources

H8S/2626: 48

H8S/2623: 47

• Eight priority levels settable

Power-down state • Medium-speed mode

• Sleep mode

• Module stop mode

• Software standby mode

• Hardware standby mode

• Subclock operation (H8S/2626 Series only)

Operating modes • Four MCU operating modes External Data Bus

Mode CPU Operating

Mode Description On-Chip

ROM Initial

Width Max.

Width

4 Advanced On-chip ROM disabled

expansion mode Disabled 16 bits 16 bits

5 On-chip ROM disabled

expansion mode Disabled 8 bits 16 bits

6 On-chip ROM enabled

expansion mode Enabled 8 bits 16 bits

7 Single-chip mode Enabled — —

Item Specifications

Clock pulse

generator • Built-in PLL circuit (×1, ×2, ×4)

• Input clock frequency: 2 to 20 MHz

Package • 100-pin plastic QFP (FP-100B)

Product lineup Model

Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Package

HD6432626*

HD6432623*HD64F2626

HD64F2623 256 k/12 k FP-100B

HD6432625*

HD6432622*— 128 k/8 k FP-100B

HD6432624*

HD6432621*— 64 k/4 k FP-100B

Note: * In planning stage

1.2 Internal Block Diagram

Figures 1-1 and 1-2 show internal block diagrams of the H8S/2623 Series and H8S/2626 Series.

Internal data bus

Peripheral data bus

Peripheral address bus

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Port D

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PVCC1

PVCC2

PVCC3

PVCC4

VCC

VSS

PA5

PA4

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PB1/A9/TIOCB3

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

P97/AN15

P96/AN14

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

HRxD

HTxD

Vref

AVCC

AVSS

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB/A23

P12/PO10/TIOCC0/TCLKA/A22

P11/PO9/TIOCB0/A21

P10/PO8/TIOCA0/A20

PF7/ø

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR/ADTRG/IRQ3

PF2/WAIT/BREQO

PF1/BACK

PF0/BREQ/IRQ2

ROM

(Mask ROM,

flash memory*1)

PC break controller

(2 channels)

RAM

WDT × 1 channel

TPU

SCI × 3 channels

HCAN × 1 channel

A/D converter

PPG

MD2

MD1

MD0

EXTAL

XTAL

PLLVCC

PLLCAP

PLLVSS

STBY

RES

WDTOVF

NMI

FWE*2

H8S/2600 CPU

DTC

Interrupt controller

Port 4Port 1

Internal address bus

Notes: 1. Applies to the H8S/2623 only.

2. The FWE pin is used only in the flash memory version.

Port E

Port APort BPort CPort 9

Bus controller

Clock pulse

generator

PLL

Port F

Figure 1-1 Internal Block Diagram

Internal data bus

Peripheral data bus

Peripheral address bus

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Port D

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PVCC1

PVCC2

PVCC3

PVCC4

VCC

VSS

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PB1/A9/TIOCB3

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

P97/AN15/DA3

P96/AN14/DA2

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

HRxD

HTxD

Vref

AVCC

AVSS

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/TCLKB/A23

P12/PO10/TIOCC0/TCLKA/A22

P11/PO9/TIOCB0/A21

P10/PO8/TIOCA0/A20

PF7/ø

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR/ADTRG/IRQ3

PF2/WAIT/BREQO

PF1/BACK

PF0/BREQ/IRQ2

ROM

(mask ROM or

flash memory*1)

PC break controller

(2 channels)

RAM

WDT × 2 channels

TPU

SCI × 3 channels

HCAN × 1 channel

A/D converter

PPG

MD2

MD1

MD0

OSC1

OSC2

EXTAL

XTAL

PLLVCC

PLLCAP

PLLVSS

STBY

RES

WDTOVF

NMI

FWE*2

H8S/2600 CPU

DTC

Interrupt controller

Port 4Port 1

Internal address bus

Notes: 1. Applies to the H8S/2626 only.

2. The FWE pin is provided in the flash memory version only.

Port E

D/A converter

PLL

Port APort BPort CPort 9

Port F

Clock pulse

generator

Bus controller

Figure 1-2 Internal Block Diagram

1.3 Pin Descriptions

1.3.1 Pin Arrangement

Figures 1-3 and 1-4 show pin arrangements of the H8S/2623 Series and H8S/2626 Series.

100

Top view

(FP-100B)

P13/PO11/TIOCD0/TCLKB/A23

P14/PO12/TIOCA1/IRQ0

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/IRQ1

P17/PO15/TIOCB2/TCLKD

VCC

HTxD

VSS

HRxD

PE0/D0

PE1/D1

PE2/D2

PE3/D3

PE4/D4

VSS

PE5/D5

PVCC1

PE6/D6

PE7/D7

PD0/D8

PD1/D9

PD2/D10

PD3/D11

PD4/D12

PD5/D13

PA4

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PVCC2

PB1/A9/TIOCB3

VSS

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

PD7/D15

PD6/D14

PF0/BREQ/IRQ2

PF1/BACK

PF2/WAIT/BREQO

PF3/LWR/ADTRG/IRQ3

PF4/HWR

PF5/PD

PF6/AS

PF7/ø

FWE

EXTAL

VSS

XTAL

VCC

STBY

NMI

RES

PLLVCC

PLLCAP

PLLVSS

MD2

MD1

VSS

MD0

PVCC3

PA5

AVCC

Vref

P40/AN0

P41/AN1

P42/AN2

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

P90/AN8

P91/AN9

P92/AN10

P93/AN11

P94/AN12

P95/AN13

P96/AN14

P97/AN15

AVSS

VSS

WDTOVF

PVCC4

P10/PO8/TIOCA0/A20

P11/PO9/TIOCB0/A21

P12/PO10/TIOCC0/TCLKA/A22

Figure 1-3 Pin Arrangement (FP-100B: Top View)

100

Top view

(FP-100B)

P13/PO11/TIOCD0/TCLKB/A23

P14/PO12/TIOCA1/IRQ0

P15/PO13/TIOCB1/TCLKC

P16/PO14/TIOCA2/IRQ1

P17/PO15/TIOCB2/TCLKD

VCC

HTxD

VSS

HRxD

PE0/D0

PE1/D1

PE2/D2

PE3/D3

PE4/D4

VSS

PE5/D5

PVCC1

PE6/D6

PE7/D7

PD0/D8

PD1/D9

PD2/D10

PD3/D11

PD4/D12

PD5/D13

OSC1

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PVCC2

PB1/A9/TIOCB3

VSS

PB0/A8/TIOCA3

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ



PC1/A1/RxD0

PC0/A0/TxD0

PD7/D15

PD6/D14

PF0/BREQ/IRQ2

PF1/BACK/BUZZ

PF2/WAIT/BREQO

PF3/LWR/ADTRG/IRQ



PF4/HWR

PF5/PD

PF6/AS

PF7/ø

FWE

EXTAL

VSS

XTAL

VCC

STBY

NMI

RES

PLLVCC

PLLCAP

PLLVSS

MD2

MD1

VSS

MD0

PVCC3

OSC2

AVCC

Vref

P40/AN0

P41/AN1

P42/AN2

P43/AN3

P44/AN4

P45/AN5

P46/AN6

P47/AN7

P90/AN8

P91/AN9

P92/AN10

P93/AN11

P94/AN12

P95/AN13

P96/AN14/DA2

P97/AN15/DA3

AVSS

VSS

WDTOVF

PVCC4

P10/PO8/TIOCA0/A20

P11/PO9/TIOCB0/A21

P12/PO10/TIOCC0/TCLKA/A22

Figure 1-4 Pin Arrangement (FP-100B: Top View)

1.3.2 Pin Functions in Each Operating Mode

Tables 1-2 and 1-3 show the pin functions in each of the operating modes of the H8S/2623 Series

and H8S/2626 Series.

Table 1-2 Pin Functions in Each Operating Mode

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

1 P13/PO11/TIOCD0/

TCLKB/A23 P13/PO11/TIOCD0/

TCLKB

2 P14/PO12/TIOCA1/

IRQ0 P14/PO12/TIOCA1/

IRQ0

3 P15/PO13/TIOCB1/

TCLKC P15/PO13/TIOCB1/

TCLKC

4 P16/PO14/TIOCA2/

IRQ1 P16/PO14/TIOCA2/

IRQ1

5 P17/PO15/TIOCB2/

TCLKD P17/PO15/TIOCB2/

TCLKD

6 VCC VCC VCC VCC

7 HTxD HTxD HTxD HTxD

8 VSS VSS VSS VSS

9 HRxD HRxD HRxD HRxD

10 PE0/D0 PE0/D0 PE0/D0 PE0

11 PE1/D1 PE1/D1 PE1/D1 PE1

12 PE2/D2 PE2/D2 PE2/D2 PE2

13 PE3/D3 PE3/D3 PE3/D3 PE3

14 PE4/D4 PE4/D4 PE4/D4 PE4

15 VSS VSS VSS VSS

16 PE5/D5 PE5/D5 PE5/D5 PE5

17 PVCC1 PVCC1 PVCC1 PVCC1

18 PE6/D6 PE6/D6 PE6/D6 PE6

19 PE7/D7 PE7/D7 PE7/D7 PE7

20 D8 D8 D8 PD0

21 D9 D9 D9 PD1

22 D10 D10 D10 PD2

23 D11 D11 D11 PD3

24 D12 D12 D12 PD4

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

25 D13 D13 D13 PD5

26 D14 D14 D14 PD6

27 D15 D15 D15 PD7

28 A0 A0 PC0/A0/TxD0 PC0/TxD0

29 A1 A1 PC1/A1/RxD0 PC1/RxD0

30 A2 A2 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4

31 A3 A3 PC3/A3/TxD1 PC3/TxD1

32 A4 A4 PC4/A4/RxD1 PC4/RxD1

33 A5 A5 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5

34 A6 A6 PC6/A6 PC6

35 A7 A7 PC7/A7 PC7

36 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/TIOCA3

37 VSS VSS VSS VSS

38 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/TIOCB3

39 PVCC2 PVCC2 PVCC2 PVCC2

40 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/TIOCC3

41 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/TIOCD3

42 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/TIOCA4

43 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/TIOCB4

44 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/TIOCA5

45 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/TIOCB5

46 PA0/A16 PA0/A16 PA0/A16 PA0

47 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2

48 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2

49 PA3/A19/SCK2 PA3/A19/SCK2 PA3/A19/SCK2 PA3/SCK2

50 PA4 PA4 PA4 PA4

51 PA5 PA5 PA5 PA5

52 PVCC3 PVCC3 PVCC3 PVCC3

53 MD0 MD0 MD0 MD0

54 VSS VSS VSS VSS

55 MD1 MD1 MD1 MD1

56 MD2 MD2 MD2 MD2

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

57 PLLVSS PLLVSS PLLVSS PLLVSS

58 PLLCAP PLLCAP PLLCAP PLLCAP

59 PLLVCC PLLVCC PLLVCC PLLVCC

60 RES RES RES RES

61 NMI NMI NMI NMI

62 STBY STBY STBY STBY

63 VCC VCC VCC VCC

64 XTAL XTAL XTAL XTAL

65 VSS VSS VSS VSS

66 EXTAL EXTAL EXTAL EXTAL

67 FWE FWE FWE FWE

68 PF7/ø PF7/ø PF7/ø PF7/ø

69 AS AS AS PF6

70 RD RD RD PF5

71 HWR HWR HWR PF4

72 PF3/LWR/ADTRG/

IRQ3 PF3/LWR/ADTRG/

IRQ3 PF3/ADTRG/

IRQ3

73 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2

74 PF1/BACK PF1/BACK PF1/BACK PF1

75 PF0/BREQ/IRQ2 PF0/BREQ/IIRQ2 PF0/BREQ/IIRQ2 PF0/IRQ2

76 AVCC AVCC AVCC AVCC

77 Vref Vref Vref Vref

78 P40/AN0 P40/AN0 P40/AN0 P40/AN0

79 P41/AN1 P41/AN1 P41/AN1 P41/AN1

80 P42/AN2 P42/AN2 P42/AN2 P42/AN2

81 P43/AN3 P43/AN3 P43/AN3 P43/AN3

82 P44/AN4 P44/AN4 P44/AN4 P44/AN4

83 P45/AN5 P45/AN5 P45/AN5 P45/AN5

84 P46/AN6 P46/AN6 P46/AN6 P46/AN6

85 P47/AN7 P47/AN7 P47/AN7 P47/AN7

86 P90/AN8 P90/AN8 P90/AN8 P90/AN8

87 P91/AN9 P91/AN9 P91/AN9 P91/AN9

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

88 P92/AN10 P92/AN10 P92/AN10 P92/AN10

89 P93/AN11 P93/AN11 P93/AN11 P93/AN11

90 P94/AN12 P94/AN12 P94/AN12 P94/AN12

91 P95/AN13 P95/AN13 P95/AN13 P95/AN13

92 P96/AN14 P96/AN14 P96/AN14 P96/AN14

93 P97/AN15 P97/AN15 P97/AN15 P97/AN15

94 AVSS AVSS AVSS AVSS

95 VSS VSS VSS VSS

96 WDTOVF WDTOVF WDTOVF WDTOVF

97 PVCC4 PVCC4 PVCC4 PVCC4

98 P10/PO8/TIOCA0/

A20 P10/PO8/TIOCA0/

A20 P10/PO8/TIOCA0

99 P11/PO9/TIOCB0/

A21 P11/PO9/TIOCB0/

A21 P11/PO9/TIOCB0

100 P12/PO10/TIOCC0/

TCLKA/A22 P12/PO10/TIOCC0/

TCLKA

Note: NC pins should be connected to VSS or left open.

Table 1-3 Pin Functions in Each Operating Mode

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

1 P13/PO11/TIOCD0/

TCLKB/A23 P13/PO11/TIOCD0/

TCLKB

2 P14/PO12/TIOCA1/

IRQ0 P14/PO12/TIOCA1/

IRQ0

3 P15/PO13/TIOCB1/

TCLKC P15/PO13/TIOCB1/

TCLKC

4 P16/PO14/TIOCA2/

IRQ1 P16/PO14/TIOCA2/

IRQ1

5 P17/PO15/TIOCB2/

TCLKD P17/PO15/TIOCB2/

TCLKD

6 VCC VCC VCC VCC

7 HTxD HTxD HTxD HTxD

8 VSS VSS VSS VSS

9 HRxD HRxD HRxD HRxD

10 PE0/D0 PE0/D0 PE0/D0 PE0

11 PE1/D1 PE1/D1 PE1/D1 PE1

12 PE2/D2 PE2/D2 PE2/D2 PE2

13 PE3/D3 PE3/D3 PE3/D3 PE3

14 PE4/D4 PE4/D4 PE4/D4 PE4

15 VSS VSS VSS VSS

16 PE5/D5 PE5/D5 PE5/D5 PE5

17 PVCC1 PVCC1 PVCC1 PVCC1

18 PE6/D6 PE6/D6 PE6/D6 PE6

19 PE7/D7 PE7/D7 PE7/D7 PE7

20 D8 D8 D8 PD0

21 D9 D9 D9 PD1

22 D10 D10 D10 PD2

23 D11 D11 D11 PD3

24 D12 D12 D12 PD4

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

25 D13 D13 D13 PD5

26 D14 D14 D14 PD6

27 D15 D15 D15 PD7

28 A0 A0 PC0/A0/TxD0 PC0/TxD0

29 A1 A1 PC1/A1/RxD0 PC1/RxD0

30 A2 A2 PC2/A2/SCK0/IRQ4 PC2/SCK0/IRQ4

31 A3 A3 PC3/A3/TxD1 PC3/TxD1

32 A4 A4 PC4/A4/RxD1 PC4/RxD1

33 A5 A5 PC5/A5/SCK1/IRQ5 PC5/SCK1/IRQ5

34 A6 A6 PC6/A6 PC6

35 A7 A7 PC7/A7 PC7

36 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/A8/TIOCA3 PB0/TIOCA3

37 VSS VSS VSS VSS

38 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/A9/TIOCB3 PB1/TIOCB3

39 PVCC2 PVCC2 PVCC2 PVCC2

40 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/A10/TIOCC3 PB2/TIOCC3

41 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/A11/TIOCD3 PB3/TIOCD3

42 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/A12/TIOCA4 PB4/TIOCA4

43 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/A13/TIOCB4 PB5/TIOCB4

44 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/A14/TIOCA5 PB6/TIOCA5

45 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/A15/TIOCB5 PB7/TIOCB5

46 PA0/A16 PA0/A16 PA0/A16 PA0

47 PA1/A17/TxD2 PA1/A17/TxD2 PA1/A17/TxD2 PA1/TxD2

48 PA2/A18/RxD2 PA2/A18/RxD2 PA2/A18/RxD2 PA2/RxD2

49 PA3/A19/SCK2 PA3/A19/SCK2 PA3/A19/SCK2 PA3/SCK2

50 OSC1 OSC1 OSC1 OSC1

51 OSC2 OSC2 OSC2 OSC2

52 PVCC3 PVCC3 PVCC3 PVCC3

53 MD0 MD0 MD0 MD0

54 VSS VSS VSS VSS

55 MD1 MD1 MD1 MD1

56 MD2 MD2 MD2 MD2

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

57 PLLVSS PLLVSS PLLVSS PLLVSS

58 PLLCAP PLLCAP PLLCAP PLLCAP

59 PLLVCC PLLVCC PLLVCC PLLVCC

60 RES RES RES RES

61 NMI NMI NMI NMI

62 STBY STBY STBY STBY

63 VCC VCC VCC VCC

64 XTAL XTAL XTAL XTAL

65 VSS VSS VSS VSS

66 EXTAL EXTAL EXTAL EXTAL

67 FWE FWE FWE FWE

68 PF7/ø PF7/ø PF7/ø PF7/ø

69 AS AS AS PF6

70 RD RD RD PF5

71 HWR HWR HWR PF4

72 PF3/LWR/ADTRG/

IRQ3 PF3/LWR/ADTRG/

IRQ3 PF3/ADTRG/

IRQ3

73 PF2/WAIT/BREQO PF2/WAIT/BREQO PF2/WAIT/BREQO PF2

74 PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BACK/BUZZ PF1/BUZZ

75 PF0/BREQ/IRQ2 PF0/BREQ/IIRQ2 PF0/BREQ/IIRQ2 PF0/IRQ2

76 AVCC AVCC AVCC AVCC

77 Vref Vref Vref Vref

78 P40/AN0 P40/AN0 P40/AN0 P40/AN0

79 P41/AN1 P41/AN1 P41/AN1 P41/AN1

80 P42/AN2 P42/AN2 P42/AN2 P42/AN2

81 P43/AN3 P43/AN3 P43/AN3 P43/AN3

82 P44/AN4 P44/AN4 P44/AN4 P44/AN4

83 P45/AN5 P45/AN5 P45/AN5 P45/AN5

84 P46/AN6 P46/AN6 P46/AN6 P46/AN6

85 P47/AN7 P47/AN7 P47/AN7 P47/AN7

86 P90/AN8 P90/AN8 P90/AN8 P90/AN8

87 P91/AN9 P91/AN9 P91/AN9 P91/AN9

Pin No. Pin Name

FP-100B Mode 4 Mode 5 Mode 6 Mode 7

88 P92/AN10 P92/AN10 P92/AN10 P92/AN10

89 P93/AN11 P93/AN11 P93/AN11 P93/AN11

90 P94/AN12 P94/AN12 P94/AN12 P94/AN12

91 P95/AN13 P95/AN13 P95/AN13 P95/AN13

92 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2 P96/AN14/DA2

93 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3 P97/AN15/DA3

94 AVSS AVSS AVSS AVSS

95 VSS VSS VSS VSS

96 WDTOVF WDTOVF WDTOVF WDTOVF

97 PVCC4 PVCC4 PVCC4 PVCC4

98 P10/PO8/TIOCA0/

A20 P10/PO8/TIOCA0/

A20 P10/PO8/TIOCA0

99 P11/PO9/TIOCB0/

A21 P11/PO9/TIOCB0/

A21 P11/PO9/TIOCB0

100 P12/PO10/TIOCC0/

TCLKA/A22 P12/PO10/TIOCC0/

TCLKA

Note: NC pins should be connected to VSS or left open.

1.3.3 Pin Functions

Table 1-4 summarizes the pin functions.

Table 1-4 Pin Functions

Type Symbol I/O Pin Name Function

Power supply VCC Input Power supply For connection to the power supply.

Connect all VCC pins to the system

power supply.

PVCC1 Input Port power supply Port power supply pins. Connect all

PVCC2 Input Port power supply these pins to the same power supply.

PVCC3 Input Port power supply

PVCC4 Input Port power supply

VSS Input Ground For connection to the power supply

(0 V). Connect all VSS pins to the system

power supply (0 V).

Clock PLLVCC Input PLL power supply On-chip PLL oscillator power supply

PLLVSS Input PLL ground On-chip PLL oscillator ground

PLLCAP Input PLL capacitance On-chip PLL oscillator external

capacitance pin

XTAL Input Crystal For connection to a crystal resonator.

For examples of crystal resonator

connection and external clock input, see

section 20, Clock Pulse Generator.

EXTAL Input External clock For connection to a crystal resonator.

For examples of crystal resonator

connection and external clock input, see

section 20, Clock Pulse Generator.

OSC1*1Input Subclock For connection to a recommended

32.768 kHz resonator. For examples of

crystal resonator connection, see

section 20, Clock Pulse Generator.

OSC2*1Input Subclock For connection to a recommended

32.768 kHz resonator. For examples of

crystal resonator connection, see

section 20, Clock Pulse Generator.

ø Output System clock Supplies the system clock to external

devices.

Type Symbol I/O Pin Name Function

Operating

mode control MD2 to

MD0 Input Mode pins These pins set the operating mode. The

relation between the settings of pins

MD2 to MD0 and the operating mode is

shown below. Inputs at these pins

should not be changed during

operation.

MD2 MD1 MD0 Operating Mode

000—

1—

10—

1—

1 0 0 Mode 4

1 Mode 5

1 0 Mode 6

1 Mode 7

System

control RES Input Reset input When this pin is driven low, the chip is

reset.

STBY Input Standby When this pin is driven low, a transition

is made to hardware standby mode.

BREQ Input Bus request Used by an external bus master to issue

a bus request to the chip.

BREQO Output Bus request

output External bus request signal used when

an internal bus master accesses

external space in the external bus-

released state.

BACK Output Bus request

acknowledge Indicates that the bus has been

released to an external bus master.

FWE Input Flash write enable Pin for use by flash memory

Interrupts NMI Input Nonmaskable

interrupt Requests a nonmaskable interrupt. If

this pin is not used, it should be fixed

high.

IRQ5 to

IRQ0 Input Interrupt request

5 to 0 These pins request a maskable

interrupt.

Address bus A23 to A0 Output Address bus These pins output address signals.

Type Symbol I/O Pin Name Function

Data bus D15 to D0 Input/

output Data bus Bidirectional data bus

Bus control AS Output Address strobe Goes low to indicate valid address

output on the address bus.

RD Output Read Goes low to indicate reading from the

external address space.

HWR Output High write Strobe signal indicating writing to the

external address space; indicates valid

data on the upper data bus (D15 to D8).

LWR Output Low write Strobe signal indicating writing to the

external address space; indicates valid

data on the lower data bus (D7 to D0).

WAIT Input Wait Requests insertion of wait states in bus

cycles during access to 3-state external

address space.

16-bit timer-

pulse unit

(TPU)

TCLKD to

TCLKA Input Clock input

D to A These pins input an external clock.

TIOCA0,

TIOCB0,

TIOCC0,

TIOCD0

Input/

output Input capture/

output compare

match A0 to D0

The TGR0A to TGR0D input capture

input/output compare output/PWM

output pins

TIOCA1,

TIOCB1 Input/

output Input capture/

output compare

match A1 and B1

The TGR1A and TGR1B input capture

input/output compare output/PWM

output pins

TIOCA2,

TIOCB2 Input/

output Input capture/

output compare

match A2 and B2

The TGR2A and TGR2B input capture

input/output compare output/PWM

output pins

TIOCA3,

TIOCB3,

TIOCC3,

TIOCD3

Input/

output Input capture/

output compare

match A3 to D3

The TGR3A to TGR3D input capture

input/output compare output/PWM

output pins

TIOCA4,

TIOCB4 Input/

output Input capture/

output compare

match A4 and B4

The TGR4A and TGR4B input capture

input/output compare output/PWM

output pins

TIOCA5,

TIOCB5 Input/

output Input capture/

output compare

match A5 and B5

The TGR5A and TGR5B input capture

input/output compare output/PWM

output pins

Type Symbol I/O Pin Name Function

Programmable

pulse

generator

(PPG)

PO15 to

PO8 Output Pulse output

15 to 8 Pulse output pins

Watchdog

timer (WDT) WDTOVF Output Watchdog timer

overflow The counter overflow signal output pin

in watchdog timer mode

Serial

communication

interface (SCI)/

TxD2,

TxD1,

TxD0

Output Transmit data Data output pins

smart card

interface RxD2,

RxD1,

RxD0

Input Receive data Data input pins

SCK2,

SCK1,

SCK0

Input/

output Serial clock Clock input/output pins

Hitachi

controller area HTxD Output HCAN transmit

data The CAN bus transmission pin

network

(HCAN) HRxD Input HCAN receive

data The CAN bus reception pin

A/D converter AN15 to

AN0 Input Analog 15 to 0 Analog input pins

ADTRG Input A/D conversion

external trigger

input

Pin for input of an external trigger to

start A/D conversion

D/A converter

pin DA3, DA2 Output Analog output D/A converter analog output pins

A/D converter,

D/A converter AVCC Input Analog power

supply The power supply pin for the A/D and

D/A converters. When the A/D and D/A

converters are not used, connect this

pin to the system power supply (+5 V).

AVSS Input Analog ground The ground pin and reference voltage

for the A/D and D/A converters.

Connect this pin to the system power

supply (0 V).

Vref Input Analog reference

power supply The reference voltage input pin for the

A/D and D/A converters. When the A/D

and D/A converters are not used,

connect this pin to the system power

supply (+5 V).

Type Symbol I/O Pin Name Function

I/O ports P17 to

P10 Input/

output Port 1 Eight input/output pins. Input or output

can be selected for each pin in the port

1 data direction register (P1DDR).

P47 to

P40 Input Port 4 Eight input pins

P97 to

P90 Input Port 9 Eight input pins

PA5 to

PA0*2Input/

output Port A Six input/output pins. Input or output

can be selected for each pin in the port

A data direction register (PADDR).

PB7 to

PB0 Input/

output Port B Eight input/output pins. Input or output

can be selected for each pin in the port

B data direction register (PBDDR).

PC7 to

PC0 Input/

output Port C Eight input/output pins. Input or output

can be selected for each pin in the port

C data direction register (PCDDR).

PD7 to

PD0 Input/

output Port D Eight input/output pins. Input or output

can be selected for each pin in the port

D data direction register (PDDDR).

PE7 to

PE0 Input/

output Port E Eight input/output pins. Input or output

can be selected for each pin in the port

E data direction register (PEDDR).

PF7 to

PF0 Input/

output Port F Eight input/output pins. Input or output

can be selected for each pin in the port

F data direction register (PFDDR).

Notes: 1. Applies to the H8S/2626 Series only.

2. PA3 to PA0 in the H8S/2626 Series.

Section 2 CPU

2.1 Overview

The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit

general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is

ideal for realtime control.

2.1.1 Features

The H8S/2600 CPU has the following features.

• Upward-compatible with H8/300 and H8/300H CPUs

 Can execute H8/300 and H8/300H object programs

• General-register architecture

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-nine basic instructions

 8/16/32-bit arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

 Multiply-and-accumulate instruction

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte address space

 Program: 16 Mbytes

 Data: 16 Mbytes (4 Gbytes architecturally)

• High-speed operation

 All frequently-used instructions execute in one or two states

 Maximum clock rate : 20 MHz

 8/16/32-bit register-register add/subtract : 50 ns

 8 × 8-bit register-register multiply : 150 ns

 16 ÷ 8-bit register-register divide : 600 ns

 16 × 16-bit register-register multiply : 200 ns

 32 ÷ 16-bit register-register divide : 1000 ns

• Two CPU operating modes

 Normal mode*

 Advanced mode

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

• Power-down state

 Transition to power-down state by SLEEP instruction

 CPU clock speed selection

2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU

The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

• Register configuration

The MAC register is supported only by the H8S/2600 CPU.

• Basic instructions

The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the

H8S/2600 CPU.

• Number of execution states

The number of execution states of the MULXU and MULXS instructions is different in each

CPU.

Execution States

Instruction Mnemonic H8S/2600 H8S/2000

MULXU MULXU.B Rs, Rd 3 12

MULXU.W Rs, ERd 4 20

MULXS MULXS.B Rs, Rd 4 13

MULXS.W Rs, ERd 5 21

In addition, there are differences in address space, CCR and EXR register functions, power-down

modes, etc., depending on the model.

2.1.3 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.

• More general registers and control registers

 Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been

added.

• Expanded address space

 Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.

 Advanced mode supports a maximum 16-Mbyte address space.

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

• Enhanced addressing

 The addressing modes have been enhanced to make effective use of the 16-Mbyte address

space.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 Signed multiply and divide instructions have been added.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

2.1.4 Differences from H8/300H CPU

In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.

• Additional control register

 One 8-bit and two 32-bit control registers have been added.

• Enhanced instructions

 Addressing modes of bit-manipulation instructions have been enhanced.

 A multiply-and-accumulate instruction has been added.

 Two-bit shift instructions have been added.

 Instructions for saving and restoring multiple registers have been added.

 A test and set instruction has been added.

• Higher speed

 Basic instructions execute twice as fast.

2.2 CPU Operating Modes

The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode* supports a

maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address

space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for

program and data areas combined). The mode is selected by the mode pins of the microcontroller.

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

CPU operating modes

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

Normal mode*

Advanced mode

Maximum 64 kbytes, program

and data areas combined

Maximum 16-Mbytes for

program and data areas

combined

Figure 2-1 CPU Operating Modes

(1) Normal Mode (Not Available in the H8S/2626 Series or H8S/2623 Series)

The exception vector table and stack have the same structure as in the H8/300 CPU.

Address Space: A maximum address space of 64 kbytes can be accessed.

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain

any value, even when the corresponding general register (Rn) is used as an address register. If the

general register is referenced in the register indirect addressing mode with pre-decrement (@–Rn)

or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding

extended register (En) will be affected.

Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of

effective addresses (EA) are valid.

Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area

starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16

bits (figure 2-2). The exception vector table differs depending on the microcontroller. For details

of the exception vector table, see section 4, Exception Handling.

H'0000

H'0001

H'0002

H'0003

H'0004

H'0005

H'0006

H'0007

H'0008

H'0009

H'000A

H'000B

Reset exception vector

Manual reset exception vector*

Exception vector 1

Exception vector 2

Exception

vector table

(Reserved for system use)

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

Figure 2-2 Exception Vector Table (Normal Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in the instruction code to specify a memory operand that

contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16-

bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note

that this area is also used for the exception vector table.

Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call,

and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto

the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is

not pushed onto the stack. For details, see section 4, Exception Handling.

(a) Subroutine Branch (b) Exception Handling

(16 bits) EXR*1

Reserved*1,*3

CCR

CCR*3

(16 bits)

SP SP

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored when returning.

(SP )

Figure 2-3 Stack Structure in Normal Mode

(2) Advanced Mode

Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally

a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4

Gbytes for program and data areas combined).

Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as

the upper 16-bit segments of 32-bit registers or address registers.

Instruction Set: All instructions and addressing modes can be used.

Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top

area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32

bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4).

For details of the exception vector table, see section 4, Exception Handling.

H'00000000

H'00000003

H'00000004

H'0000000B

H'0000000C

Exception vector table

Reserved

Reset exception vector

(Reserved for system use)

Reserved

Exception vector 1

Reserved

Manual reset exception vector*

H'00000010

H'00000008

H'00000007

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

Figure 2-4 Exception Vector Table (Advanced Mode)

The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses

an 8-bit absolute address included in the instruction code to specify a memory operand that

contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing

a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as

H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the

first part of this range is also the exception vector table.

Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a

subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR)

are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When

EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.

(a) Subroutine Branch (b) Exception Handling

(24 bits)

EXR*1

Reserved*1,*3

CCR

(24 bits)

SP SP

Notes: 1.

When EXR is not used it is not stored on the stack.

SP when EXR is not used.

Ignored when returning.

(SP )

Reserved

Figure 2-5 Stack Structure in Advanced Mode

2.3 Address Space

Figure 2-6 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear

access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte

(architecturally 4-Gbyte) address space in advanced mode.

(b) Advanced Mode

H'0000

H'FFFF

H'00000000

H'FFFFFFFF

H'00FFFFFF

(a) Normal Mode*

Data area

Program area

Cannot be

used by the

H8S/2626

Series or

H8S/2623

Series

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

Figure 2-6 Memory Map

2.4 Register Configuration

2.4.1 Overview

The CPU has the internal registers shown in figure 2-7. There are two types of registers: general

registers and control registers.

————

I2 I1 I0EXR 76543210

23 0

15 07 07 0

R0H

R1H

R2H

R3H

R4H

R5H

R6H

R7H

R0L

R1L

R2L

R3L

R4L

R5L

R6L

R7L

General Registers (Rn) and Extended Registers (En)

Control Registers (CR)

Legend Stack pointer

Program counter

Extended control register

Trace bit

Interrupt mask bits

Condition-code register

Interrupt mask bit

User bit or interrupt mask bit*

SP:

PC:

EXR:

I2 to I0:

CCR:

UI:

Note: * Cannot be used as an interrupt mask bit in the H8S/2626 Series or H8S/2623 Series.

ER0

ER1

ER2

ER3

ER4

ER5

ER6

ER7 (SP)

HUNZVCCCR 76543210

Sign extension

63 32

031

MAC MACL

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Multiply-accumulate register

MAC:

MACH

Figure 2-7 CPU Registers

2.4.2 General Registers

The CPU has eight 32-bit general registers. These general registers are all functionally alike and

can be used as both address registers and data registers. When a general register is used as a data

as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R

(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit

registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and

RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit

registers.

Figure 2-8 illustrates the usage of the general registers. The usage of each register can be selected

independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers

ER registers

(ER0 to ER7)

E registers (extended registers)

(E0 to E7)

R registers

(R0 to R7)

RH registers

(R0H to R7H)

RL registers

(R0L to R7L)

Figure 2-8 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register

function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the

stack.

Free area

Stack area

SP (ER7)

Figure 2-9 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),

8-bit condition-code register (CCR), and 64-bit multiply-accumulate register (MAC).

(1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the

CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant

PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.)

(2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three

interrupt mask bits (I2 to I0).

Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed

in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is

executed.

Bits 6 to 3—Reserved: They are always read as 1.

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to

7). For details, refer to section 5, Interrupt Controller.

Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. All interrupts, including NMI, are disabled for three states after one of these

instructions is executed, except for STC.

(3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status

information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z),

overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted

regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception-

handling sequence. For details, refer to section 5, Interrupt Controller.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the

LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask

bit. For details, refer to section 5, Interrupt Controller.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0

otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is

set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,

SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or

borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and

XORC instructions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other

times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave some or all of the flag bits unchanged. For the action of each instruction

on the flag bits, refer to Appendix A.1, List of Instructions.

Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC

instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch

(Bcc) instructions.

(4) Multiply-Accumulate Register (MAC): This 64-bit register stores the results of multiply-

and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The

lower 10 bits of MACH are valid; the upper bits are a sign extension.

2.4.4 Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the

trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits

and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.

The stack pointer should therefore be initialized by an MOV.L instruction executed immediately

after a reset.

2.5 Data Formats

The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data.

Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte

operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit

BCD data.

2.5.1 General Register Data Formats

Figure 2-10 shows the data formats in general registers.

76543210 Don’t care

Don’t care 76543210

Don’t careUpper Lower

LSB

MSB LSB

Data Type Register Number Data Format

1-bit data

4-bit BCD data

Byte data

RnH

RnL

RnH

RnL

RnH

RnL

MSB

Don’t care Upper Lower

Don’t care

Don’t care 70

Figure 2-10 General Register Data Formats

MSB LSB

Word data

LSB

MSB

En Rn

General register ER

General register E

General register R

General register RH

General register RL

Most significant bit

Least significant bit

Legend

ERn:

En:

Rn:

RnH:

RnL:

MSB:

LSB:

MSB LSB

Longword data ERn

Data Type Register Number Data Format

Figure 2-10 General Register Data Formats (cont)

2.5.2 Memory Data Formats

Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data

in memory, but word or longword data must begin at an even address. If an attempt is made to

access word or longword data at an odd address, no address error occurs but the least significant

bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to

instruction fetches.

76543210

MSB LSB

MSB

LSB

MSB

LSB

Data Type Data Format

1-bit data

Byte data

Word data

Longword data

Address

Address L

Address 2M

Address 2M + 1

Address 2N

Address 2N + 1

Address 2N + 2

Address 2N + 3

Figure 2-11 Memory Data Formats

When ER7 is used as an address register to access the stack, the operand size should be word size

or longword size.

2.6 Instruction Set

2.6.1 Overview

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in

table 2-1.

Table 2-1 Instruction Classification

Function Instructions Size Types

Data transfer MOV BWL 5

POP*1, PUSH*1WL

LDM, STM L

MOVFPE*3, MOVTPE*3B

Arithmetic ADD, SUB, CMP, NEG BWL 23

operations ADDX, SUBX, DAA, DAS B

INC, DEC BWL

ADDS, SUBS L

MULXU, DIVXU, MULXS, DIVXS BW

EXTU, EXTS WL

TAS*4B

MAC, LDMAC, STMAC, CLRMAC —

Logic operations AND, OR, XOR, NOT BWL 4

Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR B14

Branch Bcc*2, JMP, BSR, JSR, RTS — 5

System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9

Block data transfer EEPMOV — 1

Notes: B-byte size; W-word size; L-longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @-SP.

2. Bcc is the general name for conditional branch instructions.

3. Not available in the H8S/2626 Series or H8S/2623 Series.

4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

2.6.2 Instructions and Addressing Modes

Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU

can use.

Table 2-2 Combinations of Instructions and Addressing Modes

Addressing Modes

Function

Data

transfer

Arithmetic

operations

Instruction

MOV BWL BWL BWL BWL BWL BWL B BWL — BWL — — — —

POP, PUSH — — ——————— ————WL

LDM, STM — — ——————— ————L

ADD, CMP BWL BWL ——————— —————

SUB WLBWL——————— —————

ADDX, SUBX B B ——————— —————

ADDS, SUBS — L ——————— —————

INC, DEC — BWL ——————— —————

DAA, DAS — B ——————— —————

NEG —BWL——————— —————

EXTU, EXTS — WL ——————— —————

TAS*2—— B —————— —————

MAC —— ——— ——— —————

CLRMAC — — ——————— ————

MOVEPE*1,—— —————B — —————

MOVTPE*1

MULXU, — BW ——————— —————

DIVXU

MULXS, — BW ——————— —————

DIVXS

LDMAC, — L ——————— —————

STMAC

#xx

@ERn

@(d:16,ERn)

@(d:32,ERn)

@–ERn/@ERn+

@aa:8

@aa:16

@aa:24

@aa:32

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

Addressing Modes

Function

Logic

operations

System

control

Block data transfer

Shift

Bit manipulation

Branch

Instruction

AND, OR, BWL BWL ——————— —————

XOR

ANDC, B — ——————— —————

ORC, XORC

Bcc, BSR — — ——————— — ——

JMP, JSR — — —————— ——— —

RTS —— ——————— ————

TRAPA — — ——————— ————

RTE —— ——————— ————

SLEEP — — ——————— ————

LDC B B WWWW—W— W————

STC —B WWWW—W— W————

NOT —BWL——————— —————

—BWL——————— —————

—B B ———BB— B ————

NOP —— ——————— ————

—— ——————— ————BW

Legend

B: Byte

W: Word

L: Longword

#xx

@ERn

@(d:16,ERn)

@(d:32,ERn)

@–ERn/@ERn+

@aa:8

@aa:16

@aa:24

@aa:32

@(d:8,PC)

@(d:16,PC)

@@aa:8

—

Notes: 1. Not available in the H8S/2626 Series or H8S/2623 Series.

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

2.6.3 Table of Instructions Classified by Function

Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3

is defined below.

Operation Notation

Rd General register (destination)*

Rs General register (source)*

Rn General register*

ERn General register (32-bit register)

MAC Multiply-accumulate register (32-bit register)

(EAd) Destination operand

(EAs) Source operand

EXR Extended control register

CCR Condition-code register

N N (negative) flag in CCR

Z Z (zero) flag in CCR

V V (overflow) flag in CCR

C C (carry) flag in CCR

PC Program counter

SP Stack pointer

#IMM Immediate data

disp Displacement

+ Addition

– Subtraction

×Multiplication

÷ Division

∧Logical AND

∨Logical OR

⊕Logical exclusive OR

→Move

¬ NOT (logical complement)

:8/:16/:24/:32 8-, 16-, 24-, or 32-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit registers (ER0 to ER7).

Table 2-3 Instructions Classified by Function

Type Instruction Size*1Function

Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead)

Moves data between two general registers or between a

general register and memory, or moves immediate data

to a general register.

MOVFPE B Cannot be used in the H8S/2626 Series or H8S/2623

Series.

MOVTPE B Cannot be used in the H8S/2626 Series or H8S/2623

Series.

POP W/L @SP+ → Rn

Pops a register from the stack. POP.W Rn is identical to

MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L

@SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a register onto the stack. PUSH.W Rn is

identical to MOV.W Rn, @–SP. PUSH.L ERn is identical

to MOV.L ERn, @–SP.

LDM L @SP+ → Rn (register list)

Pops two or more general registers from the stack.

STM L Rn (register list) → @–SP

Pushes two or more general registers onto the stack.

Type Instruction Size*1Function

Arithmetic

operations ADD

SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general

registers, or on immediate data and data in a general

byte data in a general register. Use the SUBX or ADD

instruction.)

ADDX

SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on

byte data in two general registers, or on immediate data

and data in a general register.

INC

DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2.

(Byte operands can be incremented or decremented by

1 only.)

ADDS

SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a

32-bit register.

DAA

DAS B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a

general register by referring to the CCR to produce 4-bit

BCD data.

MULXU B/W Rd × Rs → Rd

Performs unsigned multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits ×

16 bits → 32 bits.

MULXS B/W Rd × Rs → Rd

Performs signed multiplication on data in two general

registers: either 8 bits × 8 bits → 16 bits or 16 bits ×

16 bits → 32 bits.

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit

remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-

bit remainder.

Type Instruction Size*1Function

Arithmetic

operations DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general

registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit

remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-

bit remainder.

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another

general register or with immediate data, and sets CCR

bits according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two's complement (arithmetic complement) of

data in a general register.

EXTU W/L Rd (zero extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size,

or the lower 16 bits of a 32-bit register to longword size,

by padding with zeros on the left.

EXTS W/L Rd (sign extension) → Rd

Extends the lower 8 bits of a 16-bit register to word size,

or the lower 16 bits of a 32-bit register to longword size,

by extending the sign bit.

TAS B @ERd – 0, 1 → (<bit 7> of @ERd)*2

Tests memory contents, and sets the most significant bit

(bit 7) to 1.

MAC — (EAs) × (EAd) + MAC → MAC

Performs signed multiplication on memory contents and

adds the result to the multiply-accumulate register. The

following operations can be performed:

16 bits × 16 bits + 32 bits → 32 bits, saturating

16 bits × 16 bits + 42 bits → 42 bits, non-saturating

CLRMAC — 0 → MAC

Clears the multiply-accumulate register to zero.

LDMAC

STMAC L Rs → MAC, MAC → Rd

Transfers data between a general register and a

multiply-accumulate register.

Type Instruction Size*1Function

Logic

operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register

and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register

and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general

NOT B/W/L ¬ (Rd) → (Rd)

Takes the one's complement of general register

contents.

Shift

operations SHAL

SHAR B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

1-bit or 2-bit shift is possible.

SHLL

SHLR B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

1-bit or 2-bit shift is possible.

ROTL

ROTR B/W/L Rd (rotate) → Rd

Rotates general register contents.

1-bit or 2-bit rotation is possible.

ROTXL

ROTXR B/W/L Rd (rotate) → Rd

Rotates general register contents through the carry flag.

1-bit or 2-bit rotation is possible.

Type Instruction Size*1Function

Bit-

manipulation

instructions

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory

operand to 1. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory

operand to 0. The bit number is specified by 3-bit

immediate data or the lower three bits of a general

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory

operand. The bit number is specified by 3-bit immediate

data or the lower three bits of a general register.

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory

operand and sets or clears the Z flag accordingly. The

bit number is specified by 3-bit immediate data or the

lower three bits of a general register.

BAND

BIAND

C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general

carry flag.

C ∧ ¬ (<bit-No.> of <EAd>) → C

ANDs the carry flag with the inverse of a specified bit in

a general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

BOR

BIOR

C ∨ (<bit-No.> of <EAd>) → C

ORs the carry flag with a specified bit in a general

carry flag.

C ∨ ¬ (<bit-No.> of <EAd>) → C

ORs the carry flag with the inverse of a specified bit in a

general register or memory operand and stores the

result in the carry flag.

The bit number is specified by 3-bit immediate data.

Type Instruction Size*1Function

Bit-

manipulation

instructions

BXOR

BIXOR

C ⊕ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with a specified bit in a

general register or memory operand and stores the

result in the carry flag.

C ⊕ ¬ (<bit-No.> of <EAd>) → C

Exclusive-ORs the carry flag with the inverse of a

specified bit in a general register or memory operand

and stores the result in the carry flag.

The bit number is specified by 3-bit immediate data.

BLD

BILD

(<bit-No.> of <EAd>) → C

Transfers a specified bit in a general register or memory

operand to the carry flag.

¬ (<bit-No.> of <EAd>) → C

Transfers the inverse of a specified bit in a general

The bit number is specified by 3-bit immediate data.

BST

BIST

C → (<bit-No.> of <EAd>)

Transfers the carry flag value to a specified bit in a

general register or memory operand.

¬ C → (<bit-No.> of <EAd>)

Transfers the inverse of the carry flag value to a

specified bit in a general register or memory operand.

The bit number is specified by 3-bit immediate data.

Type Instruction Size*1Function

Branch

instructions Bcc — Branches to a specified address if a specified condition

is true. The branching conditions are listed below.

Mnemonic Description Condition

BRA(BT) Always (true) Always

BRN(BF) Never (false) Never

BHI High C ∨ Z = 0

BLS Low or same C ∨ Z = 1

BCC(BHS) Carry clear

(high or same) C = 0

BCS(BLO) Carry set (low) C = 1

BNE Not equal Z = 0

BEQ Equal Z = 1

BVC Overflow clear V = 0

BVS Overflow set V = 1

BPL Plus N = 0

BMI Minus N = 1

BGE Greater or equal N ⊕ V = 0

BLT Less than N ⊕ V = 1

BGT Greater than Z∨(N ⊕ V) = 0

BLE Less or equal Z∨(N ⊕ V) = 1

JMP — Branches unconditionally to a specified address.

BSR — Branches to a subroutine at a specified address.

JSR — Branches to a subroutine at a specified address.

RTS — Returns from a subroutine

Type Instruction Size*1Function

System control TRAPA — Starts trap-instruction exception handling.

instructions RTE — Returns from an exception-handling routine.

SLEEP — Causes a transition to a power-down state.

LDC B/W (EAs) → CCR, (EAs) → EXR

Moves the source operand contents or immediate data

to CCR or EXR. Although CCR and EXR are 8-bit

registers, word-size transfers are performed between

them and memory. The upper 8 bits are valid.

STC B/W CCR → (EAd), EXR → (EAd)

Transfers CCR or EXR contents to a general register or

memory. Although CCR and EXR are 8-bit registers,

word-size transfers are performed between them and

memory. The upper 8 bits are valid.

ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR

Logically ANDs the CCR or EXR contents with

immediate data.

ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR

Logically ORs the CCR or EXR contents with immediate

data.

XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR

Logically exclusive-ORs the CCR or EXR contents with

immediate data.

NOP — PC + 2 → PC

Only increments the program counter.

Type Instruction Size*1Function

Block data

transfer

instruction

EEPMOV.B

EEPMOV.W

—

if R4L ≠ 0 then

Repeat @ER5+ → @ER6+

R4L–1 → R4L

Until R4L = 0

else next;

if R4 ≠ 0 then

Repeat @ER5+ → @ER6+

R4–1 → R4

Until R4 = 0

else next;

Transfers a data block according to parameters set in

general registers R4L or R4, ER5, and ER6.

R4L or R4: size of block (bytes)

ER5: starting source address

ER6: starting destination address

Execution of the next instruction begins as soon as the

transfer is completed.

Notes: 1. Size refers to the operand size.

B: Byte

W: Word

L: Longword

2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

2.6.4 Basic Instruction Formats

The H8S/2626 Series and H8S/2623 Series instructions consist of 2-byte (1-word) units. An

instruction consists of an operation field (op field), a register field (r field), an effective address

extension (EA field), and a condition field (cc).

(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the

operation to be carried out on the operand. The operation field always includes the first four bits of

the instruction. Some instructions have two operation fields.

(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data

registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register

field.

(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute

address, or a displacement.

(4) Condition Field: Specifies the branching condition of Bcc instructions.

Figure 2-12 shows examples of instruction formats.

op rn rm

NOP, RTS, etc.

ADD.B Rn, Rm, etc.

MOV.B @(d:16, Rn), Rm, etc.

(1) Operation field only

(2) Operation field and register fields

(3) Operation field, register fields, and effective address extension

rn rm

EA (disp)

(4) Operation field, effective address extension, and condition field

op cc EA (disp) BRA d:16, etc

Figure 2-12 Instruction Formats (Examples)

2.7 Addressing Modes and Effective Address Calculation

2.7.1 Addressing Mode

The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of

these addressing modes. Arithmetic and logic instructions can use the register direct and

immediate modes. Data transfer instructions can use all addressing modes except program-counter

relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or

absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and

BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.

Table 2-4 Addressing Modes

No. Addressing Mode Symbol

1 Register direct Rn

2 Register indirect @ERn

3 Register indirect with displacement @(d:16,ERn)/@(d:32,ERn)

4 Register indirect with post-increment

@–ERn

5 Absolute address @aa:8/@aa:16/@aa:24/@aa:32

6 Immediate #xx:8/#xx:16/#xx:32

7 Program-counter relative @(d:8,PC)/@(d:16,PC)

8 Memory indirect @@aa:8

(1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit

general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit

registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified

as 32-bit registers.

(2) Register Indirect—@ERn: The register field of the instruction code specifies an address

instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00).

(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit

displacement contained in the instruction is added to an address register (ERn) specified by the

displacement is sign-extended when added.

(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn:

• Register indirect with post-increment—@ERn+

The register field of the instruction code specifies an address register (ERn) which contains the

address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address

access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or

longword transfer instruction, the register value should be even.

• Register indirect with pre-decrement—@-ERn

The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field

in the instruction code, and the result becomes the address of a memory operand. The result is

also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer

instruction, or 4 for longword transfer instruction. For word or longword transfer instruction,

the register value should be even.

(5) Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the

absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits

long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32).

To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits

(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).

For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can

access the entire address space.

A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8

bits are all assumed to be 0 (H'00).

Table 2-5 indicates the accessible absolute address ranges.

Table 2-5 Absolute Address Access Ranges

Absolute Address Normal Mode*Advanced Mode

Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF

16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF,

H'FF8000 to H'FFFFFF

32 bits (@aa:32) H'000000 to H'FFFFFF

Program instruction

address 24 bits (@aa:24)

Note: *Not available in the H8S/2626 Series or H8S/2623 Series.

(6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit

(#xx:16), or 32-bit (#xx:32) immediate data as an operand.

The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit

manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit

number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a

vector address.

(7) Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and

BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and

added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch

address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the

displacement is added is the address of the first byte of the next instruction, so the possible

branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to

+16384 words) from the branch instruction. The resulting value should be an even number.

(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

instruction code contains an 8-bit absolute address specifying a memory operand. This memory

operand contains a branch address. The upper bits of the absolute address are all assumed to be 0,

so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in

advanced mode). In normal mode* the memory operand is a word operand and the branch address

is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of

which is assumed to be all 0 (H'00).

Note that the first part of the address range is also the exception vector area. For further details,

refer to section 4, Exception Handling.

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

(a) Normal Mode*(b) Advanced Mode

Branch address

Specified

by @aa:8 Specified

by @aa:8 Reserved

Branch address

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

Figure 2-13 Branch Address Specification in Memory Indirect Mode

If an odd address is specified in word or longword memory access, or as a branch address, the

least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched

at the address preceding the specified address. (For further information, see section 2.5.2, Memory

Data Formats.)

2.7.2 Effective Address Calculation

Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal

mode* the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.

Note: * Cannot be set in the H8S/2626 Series or H8S/2623 Series.

Table 2-6 Effective Address Calculation

pre-decrement

• Register indirect with post-increment @ERn+

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

1 Register direct (Rn)

op rm rn Operand is general register contents.

@(d:16, ERn) or @(d:32, ERn)

• Register indirect with pre-decrement @–ERn

General register contents

Sign extension disp

General register contents

1, 2, or 4

General register contents

1, 2, or 4

Byte

Word

Longword

Operand Size Value added

31 0

31 0 31 0

31 0

op r

rop

disp

24 23

Don’t care

24 23

Don’t care

24 23

Don’t care

24 23

Don’t care

@aa:8

Absolute address

@aa:16

@aa:32

6Immediate #xx:8/#xx:16/#xx:32

31 08 7

Operand is immediate data.

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

@aa:24

31 0

16 15

31 0

24 23

31 0

op abs

abs

op IMM

H'FFFF

Don’t care

24 23

Don’t care

24 23

Don’t care

24 23

Don’t care Sign extension

7Program-counter relative

@(d:8, PC)/@(d:16, PC)

8Memory indirect @@aa:8

• Normal mode*

• Advanced mode

No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)

31 8 7

disp

H'000000

abs

H'000000

31 0

24 23

31 0

16 15

31 0

24 23

op disp

op abs

Sign

extension

PC contents

abs

Memory contents

H'00

Don’t care

24 23

Don’t care

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

2.8 Processing States

2.8.1 Overview

The CPU has five main processing states: the reset state, exception handling state, program

execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the

processing states. Figure 2-15 indicates the state transitions.

Reset state

The CPU and all on-chip supporting modules have been

initialized and are stopped.

Exception-handling

state

A transient state in which the CPU changes the normal

processing flow in response to a reset, interrupt, or trap

instruction.

Program execution

state

The CPU executes program instructions in sequence.

Bus-released state

The external bus has been released in response to a bus

request signal from a bus master other than the CPU.

Power-down state

CPU operation is stopped

to conserve power.*

Sleep mode

Software standby

mode

Hardware standby

mode

Processing

states

Note:

*The power-down state also includes a medium-speed mode, module stop mode,

subactive mode, subsleep mode, and watch mode. Subclock functions (subactive

mode, subsleep mode, and watch mode) are not available in the H8S/2623 Series,

but are available in the H8S/2626 Series.

Figure 2-14 Processing States

Exception handling state

Bus-released state

Hardware standby mode*

Software standby mode

Reset state *

Sleep mode

Power-down state*

Program execution state

End of bus request

Bus request

Interrupt request

External interrupt request

RES= High

Request for exception handling

STBY= High, RES= Low

End of bus

request

Bus request

SLEEP

instruction

with

SSBY = 0

SLEEP

instruction

with

SSBY = 1

Notes: 1.

From any state except hardware standby mode, a transition to the reset state occurs whenever RES

goes low. A transition can also be made to the reset state when the

watchdog timer overflows.

From any state, a transition to hardware standby mode occurs when STBY goes low.

Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode in the

H8S/2626 Series. See section 21B, Power-Down Modes.

End of exception

handling

Reset state

Figure 2-15 State Transitions

2.8.2 Reset State

When the RES input goes low all current processing stops and the CPU enters the reset state. All

interrupts are masked in the reset state. Reset exception handling starts when the RES signal

changes from low to high.

The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,

Watchdog Timer.

2.8.3 Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address

(vector) from the exception vector table and branches to that address.

(1) Types of Exception Handling and Their Priority

Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7

indicates the types of exception handling and their priority. Trap instruction exception handling is

always accepted, in the program execution state.

Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.

Table 2-7 Exception Handling Types and Priority

Priority Type of Exception Detection Timing Start of Exception Handling

High Reset Synchronized with clock Exception handling starts

immediately after a low-to-high

transition at the RES pin, or

when the watchdog timer

overflows.

Trace End of instruction

execution or end of

exception-handling

sequence*1

When the trace (T) bit is set to

1, the trace starts at the end of

the current instruction or current

exception-handling sequence

Interrupt End of instruction

execution or end of

exception-handling

sequence*2

When an interrupt is requested,

exception handling starts at the

end of the current instruction or

current exception-handling

sequence

Low

Trap instruction When TRAPA instruction

is executed Exception handling starts when

a trap (TRAPA) instruction is

executed*3

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not

executed at the end of the RTE instruction.

2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,

or immediately after reset exception handling.

3. Trap instruction exception handling is always accepted, in the program execution state.

(2) Reset Exception Handling

After the RES pin has gone low and the reset state has been entered, when RES pin goes high

again, reset exception handling starts. The CPU enters the reset state when the RES is low. When

reset exception handling starts the CPU fetches a start address (vector) from the exception vector

table and starts program execution from that address. All interrupts, including NMI, are disabled

during reset exception handling and after it ends.

(3) Traces

Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR

is set to 1. When trace mode is established, trace exception handling starts at the end of each

instruction.

At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode

is cleared. Interrupt masks are not affected.

The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to

return from the trace exception-handling routine, trace mode is entered again. Trace exception-

handling is not executed at the end of the RTE instruction.

Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.

(4) Interrupt Exception Handling and Trap Instruction Exception Handling

When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer

(ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU

alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start

address (vector) from the exception vector table and program execution starts from that start

address.

Figure 2-16 shows the stack after exception handling ends.

CCR

(24 bits)

CCR

(24 bits)

EXR

Reserved*1

(a) Interrupt control mode 0 (b) Interrupt control mode 2

CCR

CCR*1

(16 bits)

CCR

CCR*1

(16 bits)

EXR

Reserved*1

Normal mode*2

Advanced mode

Notes: 1. Ignored when returning.

2. Not available in the H8S/2626 Series or H8S/2623 Series.

Figure 2-16 Stack Structure after Exception Handling (Examples)

2.8.4 Program Execution State

In this state the CPU executes program instructions in sequence.

2.8.5 Bus-Released State

This is a state in which the bus has been released in response to a bus request from a bus master

other than the CPU. While the bus is released, the CPU halts operations.

Bus masters other than the CPU are data transfer controller (DTC).

For further details, refer to section 7, Bus Controller.

2.8.6 Power-Down State

The power-down state includes both modes in which the CPU stops operating and modes in which

the CPU does not stop. There are five modes in which the CPU stops operating: sleep mode,

software standby mode, hardware standby mode, subsleep mode*, and watch mode*. There are

also three other power-down modes: medium-speed mode, module stop mode, and subactive

mode*. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock.

Module stop mode permits halting of the operation of individual modules, other than the CPU.

Subactive mode*, subsleep mode*, and watch mode* are power-down states using subclock input.

For details, refer to section 21, Power-Down Modes.

Note: * Supported only in the H8S/2626 Series; not available in the H8S/2623 Series.

2.9 Basic Timing

2.9.1 Overview

The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one

rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of

one, two, or three states. Different methods are used to access on-chip memory, on-chip

supporting modules, and the external address space.

2.9.2 On-Chip Memory (ROM, RAM)

On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and

word transfer instruction. Figure 2-17 shows the on-chip memory access cycle. Figure 2-18 shows

the pin states.

Internal address bus

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Bus cycle

Address

Read data

Write data

Read

access

Write

access

Figure 2-17 On-Chip Memory Access Cycle

Bus cycle

RetainedAddress bus

HWR, LWR

Data bus

High

h-impedance state

Figure 2-18 Pin States during On-Chip Memory Access

2.9.3 On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits

wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the

access timing for the on-chip supporting modules. Figure 2-20 shows the pin states.

Bus cycle

T1 T2

Address

Read data

Write data

Internal read signal

Internal data bus

Internal write signal

Internal data bus

Read

access

Write

access

Internal address bus

Figure 2-19 On-Chip Supporting Module Access Cycle

Bus cycle

T1 T2

Retained

Address bus

HWR, LWR

Data bus

High

High-impedance state

Figure 2-20 Pin States during On-Chip Supporting Module Access Cycle

2.9.4 On-Chip HCAN Module Access Timing

On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait

states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access

timing is shown in figures 2-21 and 2-22, and the pin states in figure 2-23.

Internal address bus

HCAN read signal

Internal data bus

HCAN write signal

Internal data bus

Bus cycle

Address

Read

Write

Read data

Write data

T2 T4

Figure 2-21 On-Chip HCAN Module Access Cycle (No Wait State)

Internal address bus

HCAN read signal

Internal data bus

HCAN write signal

Internal data bus

Bus cycle

Address

Read

Write

T2 Tw

Read data

Write data

Tw T4

Figure 2-22 On-Chip HCAN Module Access Cycle (Wait States Inserted)

T1 T3

T2 T4

Bus cycle

HWR, LWR

Data bus

High

RetainedAddress bus

High-impedance state

Figure 2-23 Pin States in On-Chip HCAN Module Access

2.9.5 External Address Space Access Timing

The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or

three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to

section 7, Bus Controller.

2.10 Usage Note

2.10.1 TAS Instruction

Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS

instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS

instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or

ER5 is used.

Section 3 MCU Operating Modes

3.1 Overview

3.1.1 Operating Mode Selection

The H8S/2626 Series and H8S/2623 Series have four operating modes (modes 4 to 7). These

modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the

initial bus width setting, by setting the mode pins (MD2 to MD0).

Table 3-1 lists the MCU operating modes.

Table 3-1 MCU Operating Mode Selection

MCU CPU External Data Bus

Operating

Mode MD2 MD1 MD0 Operating

Mode Description On-Chip

ROM Initial

Width Max.

Width

0*000— — — —

1*1—

2*10

3*1

4 1 0 0 Advanced On-chip ROM disabled,

expanded mode Disabled 16 bits 16 bits

5 1 8 bits 16 bits

6 1 0 On-chip ROM enabled,

expanded mode Enabled 8 bits 16 bits

7 1 Single-chip mode —

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

The CPU’s architecture allows for 4 Gbytes of address space, but the H8S/2626 Series and

H8S/2623 Series actually access a maximum of 16 Mbytes.

Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral

devices.

The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program

execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus

controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit

access is selected for all areas, 8-bit bus mode is set.

Note that the functions of each pin depend on the operating mode.

The H8S/2626 Series and H8S/2623 Series can be used only in modes 4 to 7. This means that the

mode pins must be set to select one of these modes. Do not change the inputs at the mode pins

during operation.

3.1.2 Register Configuration

The H8S/2626 Series and H8S/2623 Series have a mode control register (MDCR) that indicates

the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) that controls

the operation of the H8S/2626 Series or H8S/2623 Series chip. Table 3-2 summarizes these

registers.

Table 3-2 MCU Registers

Name Abbreviation R/W Initial Value Address*

Mode control register MDCR R/W Undetermined H'FDE7

System control register SYSCR R/W H'01 H'FDE5

Pin function control register PFCR R/W H'0D/H'00 H'FDEB

Note: * Lower 16 bits of the address.

3.2 Register Descriptions

3.2.1 Mode Control Register (MDCR)

—

R/W

—

MDS0

—*

MDS2

—*

MDS1

—*

Note: * Determined by pins MD2 to MD0.

Bit

Initial value

R/W

MDCR is an 8-bit register that indicates the current operating mode of the H8S/2626 Series or

H8S/2623 Series chip.

Bit 7—Reserved: Only 1 should be written to this bit.

Bits 6 to 3—Reserved: These bits are always read as 0 and cannot be modified.

Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins

MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0.

MDS2 to MDS0 are read-only bits-they cannot be written to. The mode pin (MD2 to MD0) input

levels are latched into these bits when MDCR is read. These latches are canceled by a reset.

3.2.2 System Control Register (SYSCR)

MACS

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

—

Bit

Initial value

R/W

SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation

for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and

enables or disables on-chip RAM.

SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in

software standby mode.

Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the

MAC instruction.

Bit 7

MACS Description

0 Non-saturating calculation for MAC instruction (Initial value)

1 Saturating calculation for MAC instruction

Bit 6—Reserved: This bit is always read as 0 and cannot be modified.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control

mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,

Interrupt Control Modes and Interrupt Operation.

Bit 5 Bit 4 Interrupt

INTM1 INTM0 Control Mode Description

0 0 0 Control of interrupts by I bit (Initial value)

1 — Setting prohibited

1 0 2 Control of interrupts by I2 to I0 bits and IPR

1 — Setting prohibited

Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input.

Bit 3

NMIEG Description

0 An interrupt is requested at the falling edge of NMI input (Initial value)

1 An interrupt is requested at the rising edge of NMI input

Bit 2—Reserved: Only 0 should be written to this bit.

Bit 1—Reserved: This bit is always read as 0 and cannot be modified.

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset status is released. It is not initialized in software standby mode.

Bit 0

RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

Note: When the DTC is used, the RAME bit must be set to 1.

3.2.3 Pin Function Control Register (PFCR)

—

R/W

—

R/W

BUZZE

R/W

—

R/W

AE3

1/0

R/W

AE0

1/0

R/W

AE2

1/0

R/W

AE1

R/W

Bit

Initial value

R/W

PFCR is an 8-bit readable/writable register that performs address output control in external

expanded mode.

PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous

state in software standby mode.

Bits 7 to 4—Reserved: Only 0 should be written to these bits.

Bit 5—BUZZE Output Enable (BUZZE): This bit is for use only in the H8S/2626. Only 0

should be writtn to this bit.

Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling

of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is

enabled for address output, the address is output regardless of the corresponding DDR setting.

When a pin is disabled for address output, it becomes an output port when the corresponding DDR

bit is set to 1.

Bit 3 Bit 2 Bit 1 Bit 0

AE3 AE2 AE1 AE0 Description

0000A8–A23 address output disabled (Initial value*)

1 A8 address output enabled; A9–A23 address output disabled

1 0 A8, A9 address output enabled; A10–A23 address output

disabled

1 A8–A10 address output enabled; A11–A23 address output

disabled

1 0 0 A8–A11 address output enabled; A12–A23 address output

disabled

1 A8–A12 address output enabled; A13–A23 address output

disabled

1 0 A8–A13 address output enabled; A14–A23 address output

disabled

1 A8–A14 address output enabled; A15–A23 address output

disabled

1000A8–A15 address output enabled; A16–A23 address output

disabled

1 A8–A16 address output enabled; A17–A23 address output

disabled

1 0 A8–A17 address output enabled; A18–A23 address output

disabled

1 A8–A18 address output enabled; A19–A23 address output

disabled

1 0 0 A8–A19 address output enabled; A20–A23 address output

disabled

1 A8–A20 address output enabled; A21–A23 address output

disabled (Initial value*)

1 0 A8–A21 address output enabled; A22, A23 address output

disabled

1 A8–A23 address output enabled

Note: *In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.

In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.

Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to

3.3 Operating Mode Descriptions

3.3.1 Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of

port F carries bus control signals.

The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-

bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.

3.3.2 Mode 5

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports 1, A, B, and C, function as an address bus, ports D and E function as a data bus, and part of

port F carries bus control signals.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-

bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and

port E becomes a data bus.

3.3.3 Mode 6

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.

Ports 1, A, B, and C, function as input port pins immediately after a reset. Address output can be

performed by setting the corresponding DDR (data direction register) bits to 1.

Port D function as a data bus, and part of port F carries data bus signals.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-

bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and

port E becomes a data bus.

3.3.4 Mode 7

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,

but external addresses cannot be accessed.

All I/O ports are available for use as input-output ports.

3.4 Pin Functions in Each Operating Mode

The pin functions of ports 1 and A to F vary depending on the operating mode. Table 3-3 shows

their functions in each operating mode.

Table 3-3 Pin Functions in Each Mode

Port Mode 4 Mode 5 Mode 6 Mode 7

Port 1 P10 A A P*/A P

P11 to P13 P*/A P*/A P*/A P

Port A PA4 to PA0 A A P*/A P

Port B A A P*/A P

Port C A A P*/A P

Port D DDDP

Port E P/D*P*/D P*/D P

Port F PF7 P/C*P/C*P/C*P*/C

PF6 to PF4 CCCP

PF3 P/C*P*/C P*/C

PF2 to PF0 P*/C P*/C P*/C

Legend

P: I/O port

A: Address bus output

D: Data bus I/O

C: Control signals, clock I/O

*: After reset

3.5 Address Map in Each Operating Mode

An address map of the H8S/2623 and H8S/2626 is shown in figure 3-1, and an address map of the

H8S/2622, and H8S/2625 in figure 3-2, and an address map of the H8S/2621 and H8S/2624 in

figure 3-3.

The address space is 16 Mbytes in modes 4 to 7 (advanced modes).

The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus

Controller.

External address

space On-chip ROM On-chip ROM

Internal I/O registers

Reserved area

On-chip RAM*

External area

Internal I/O registers

Reserved area

On-chip RAM*

Internal I/O registers

On-chip RAM

On-chip RAM*

External area

On-chip RAM

Internal I/O registers Internal I/O registers

External address

space

H'000000 H'000000 H'000000

H'FFB000

H'FFC000

H'FFEFC0

H'FFFFC0

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFF800

H'FFB000

H'040000

H'FFC000

H'FFEFC0

H'FFFFC0

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFF800

H'FFC000

H'FFEFBF

H'FFFFC0

H'FFFFFF

H'FFFF3F

H'FFFF60

H'FFF800

H'03FFFF

Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.

Modes 4 and 5

(advanced expanded modes

with on-chip ROM disabled)

Mode 6

(advanced expanded mode

with on-chip ROM enabled)

Mode 7

(advanced single-chip mode)

Figure 3-1 Memory Map in Each Operating Mode in the H8S/2623 and H8S/2626

External address

space

On-chip ROM On-chip ROM

Internal I/O registers

Reserved area

On-chip RAM*

External area

Internal I/O registers

Reserved area

On-chip RAM*

Internal I/O registers

On-chip RAM

On-chip RAM*

External area

On-chip RAM

Internal I/O registers Internal I/O registers

External address

space

H'000000 H'000000

H'020000

H'000000

H'FFB000

H'FFD000

H'FFEFC0

H'FFFFC0

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFF800

H'FFB000

H'040000

H'FFD000

H'FFEFC0

H'FFFFC0

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFF800

H'FFD000

H'FFEFBF

H'FFFFC0

H'FFFFFF

H'FFFF3F

H'FFFF60

H'FFF800

H'01FFFF

Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.

Modes 4 and 5

(advanced expanded modes

with on-chip ROM disabled)

Mode 6

(advanced expanded mode

with on-chip ROM enabled)

Mode 7

(advanced single-chip mode)

Figure 3-2 Memory Map in Each Operating Mode in the H8S/2622 and H8S/2625

External address

space

On-chip ROM On-chip ROM

Internal I/O registers

Reserved area

On-chip RAM*

External area

Internal I/O registers

Reserved area

On-chip RAM*

Internal I/O registers

On-chip RAM

On-chip RAM*

External area

On-chip RAM

Internal I/O registers Internal I/O registers

External address

space

H'000000 H'000000

H'010000

H'000000

H'FFB000

H'FFE000

H'FFEFC0

H'FFFFC0

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFF800

H'FFB000

H'040000

H'FFE000

H'FFEFC0

H'FFFFC0

H'FFFFFF

H'FFFF40

H'FFFF60

H'FFF800

H'FFE000

H'FFEFBF

H'FFFFC0

H'FFFFFF

H'FFFF3F

H'FFFF60

H'FFF800

H'00FFFF

Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0.

Modes 4 and 5

(advanced expanded modes

with on-chip ROM disabled)

Mode 6

(advanced expanded mode

with on-chip ROM enabled)

Mode 7

(advanced single-chip mode)

Figure 3-3 Memory Map in Each Operating Mode in the H8S/2621 and H8S/2624

Section 4 Exception Handling

4.1 Overview

4.1.1 Exception Handling Types and Priority

As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.

Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur

simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions

are accepted at all times, in the program execution state.

Exception handling sources, the stack structure, and the operation of the CPU vary depending on

the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.

Table 4-1 Exception Types and Priority

Priority Exception Type Start of Exception Handling

High Reset Starts immediately after a low-to-high transition at the RES

pin, or when the watchdog timer overflows. The CPU enters

the reset state when the RES pin is low.

Trace*1Starts when execution of the current instruction or exception

handling ends, if the trace (T) bit is set to 1

Direct transition Starts when a direction transition occurs as the result of

SLEEP instruction execution.

Interrupt Starts when execution of the current instruction or exception

handling ends, if an interrupt request has been issued*2

Low Trap instruction (TRAPA)*3Started by execution of a trap instruction (TRAPA)

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not

executed after execution of an RTE instruction.

2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC

instruction execution, or on completion of reset exception handling.

3. Trap instruction exception handling requests are accepted at all times in program

execution state.

4.1.2 Exception Handling Operation

Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:

1. The program counter (PC), condition code register (CCR), and extended register (EXR) are

pushed onto the stack.

2. The interrupt mask bits are updated. The T bit is cleared to 0.

3. A vector address corresponding to the exception source is generated, and program execution

starts from that address.

For a reset exception, steps 2 and 3 above are carried out.

4.1.3 Exception Vector Table

The exception sources are classified as shown in figure 4-1. Different vector addresses are

assigned to different exception sources.

Table 4-2 lists the exception sources and their vector addresses.

Exception

sources

Reset

Trace

Interrupts

Trap instruction

Reset

Manual reset*1

External interrupts: NMI, IRQ5 to IRQ0

Internal interrupts: 47 interrupt sources*2 in

on-chip supporting modules

Notes: 1.

2. Not available in the H8S/2626 Series or H8S/2623 Series.

48 interrupt sources in the H8S/2626 Series.

Figure 4-1 Exception Sources

Table 4-2 Exception Vector Table

Vector Address*1

Exception Source Vector Number Advanced Mode

Reset 0 H'0000 to H'0003

Manual reset*31 H'0004 to H'0007

Reserved 2 H'0008 to H'000B

3 H'000C to H'000F

4 H'0010 to H'0013

Trace 5 H'0014 to H'0017

Direct transitions*4 (H8S/2626 only) 6 H'0018 to H'001B

External interrupt NMI 7 H'001C to H'001F

Trap instruction (4 sources) 8 H'0020 to H'0023

9 H'0024 to H'0027

10 H'0028 to H'002B

11 H'002C to H'002F

Reserved 12 H'0030 to H'0033

13 H'0034 to H'0037

14 H'0038 to H'003B

15 H'003C to H'003F

External interrupt IRQ0 16 H'0040 to H'0043

IRQ1 17 H'0044 to H'0047

IRQ2 18 H'0048 to H'004B

IRQ3 19 H'004C to H'004F

IRQ4 20 H'0050 to H'0053

IRQ5 21 H'0054 to H'0057

Reserved 22 H'0058 to H'005B

23 H'005C to H'005F

Internal interrupt*224



127

H'0060 to H'0063



H'01FC to H'01FF

Notes: 1. Lower 16 bits of the address.

2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling

Vector Table.

3. Not available in the H8S/2626 Series or H8S/2623 Series.

4. See section 21B.11, Direct Transitions, for details.

4.2 Reset

4.2.1 Overview

A reset has the highest exception priority.

When the RES pin goes low, all processing halts and the H8S/2626 Series or H8S/2623 Series

enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip

supporting modules. Immediately after a reset, interrupt control mode 0 is set.

Reset exception handling begins when the RES pin changes from low to high.

The chip can also be reset by overflow of the watchdog timer. For details see section 12,

Watchdog Timer.

4.2.2 Reset Sequence

The chip enters the reset state when the RES pin goes low.

To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the

chip during operation, hold the RES pin low for at least 20 states.

When the RES pin goes high after being held low for the necessary time, the chip starts reset

exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip supporting modules are

initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figures 4-2 and 4-3 show examples of the reset sequence.

Address bus

Vector fetch Internal

processing Prefetch of first

program instruction

(1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002)

(2) (4) Start address (contents of reset exception handling vector address)

(5) Start address ((5) = (2) (4))

(6) First program instruction

RES

(1) (5)

High

(2) (4)

(3)

(6)

HWR, LWR

D15 to D0

Note: * Three program wait states are inserted.

Figure 4-2 Reset Sequence (Modes 4 and 5)

RES

Internal

address bus

Internal read

signal

Internal write

signal

Internal data

bus

Vector fetch

(1) (3) (5)

High

Internal

processing

Prefetch of

first program

instruction

(2) (4)

(1) (3) Reset exception handling vector address (when reset, (1) = H'000000,

(3) = H'000002)

(2) (4) Start address (contents of reset exception handling vector address)

(5) Start address ((5) = (2) (4))

(6) First program instruction

(6)

Figure 4-3 Reset Sequence (Modes 6 and 7)

4.2.3 Interrupts after Reset

If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and

CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,

including NMI, are disabled immediately after a reset. Since the first instruction of a program is

always executed immediately after the reset state ends, make sure that this instruction initializes

the stack pointer (example: MOV.L #xx: 32, SP).

4.2.4 State of On-Chip Supporting Modules after Reset Release

After reset release, MSTPCRA to MSTPCRC are initialized to H'3F, H'FF, and H'FF, respectively,

and all modules except the DTC enter module stop mode. Consequently, on-chip supporting

module registers cannot be read or written to. Register reading and writing is enabled when

module stop mode is exited.

4.3 Traces

Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control

mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,

Interrupt Controller.

If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on

completion of each instruction.

Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking.

Table 4-3 shows the state of CCR and EXR after execution of trace exception handling.

Interrupts are accepted even within the trace exception handling routine.

The T bit saved on the stack retains its value of 1, and when control is returned from the trace

exception handling routine by the RTE instruction, trace mode resumes.

Trace exception handling is not carried out after execution of the RTE instruction.

Table 4-3 Status of CCR and EXR after Trace Exception Handling

CCR EXR

Interrupt Control Mode I UI I2 to I0 T

0 Trace exception handling cannot be used.

21——0

Legend

1: Set to 1

0: Cleared to 0

—: Retains value prior to execution.

4.4 Interrupts

Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and

internal sources (H8S/2626 Series: 48, H8S/2623 Series: 47) in the on-chip supporting modules.

Figure 4-4 classifies the interrupt sources and the number of interrupts of each type.

The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),

16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller

(DTC), PC break controller (PBC), Hitachi controller area network (HCAN), and A/D converter.

Each interrupt source has a separate vector address.

NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The

interrupt controller has two interrupt control modes and can assign interrupts other than NMI to

eight priority/mask levels to enable multiplexed interrupt control.

For details of interrupts, see section 5, Interrupt Controller.

Interrupts

External

interrupts

Internal

interrupts

NMI (1)

IRQ5 to IRQ0 (6)

WDT* H8S/2626 Series (2), H8S/2623 Series (1)

TPU (26)

SCI (12)

DTC (1)

PBC (1)

HCAN (5)

A/D converter (1)

Numbers in parentheses are the numbers of interrupt sources.

*When the watchdog timer is used as an interval timer, it generates an interrupt

request at each counter overflow.

Notes:

Figure 4-4 Interrupt Sources and Number of Interrupts

4.5 Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction

exception handling can be executed at all times in the program execution state.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector

number from 0 to 3, as specified in the instruction code.

Table 4-4 shows the status of CCR and EXR after execution of trap instruction exception

handling.

Table 4-4 Status of CCR and EXR after Trap Instruction Exception Handling

CCR EXR

Interrupt Control Mode I UI I2 to I0 T

01———

21——0

Legend

1: Set to 1

0: Cleared to 0

—: Retains value prior to execution.

4.6 Stack Status after Exception Handling

Figures 4-5 (1) and 4-5 (2) show the stack after completion of trap instruction exception handling

and interrupt exception handling.

SP CCR

CCR*

(16 bits)

CCR

CCR*

(16 bits)

Reserved*

EXR

(a) Interrupt control mode 0 (b) Interrupt control mode 2

Note: * Ignored on return.

Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the

H8S/2626 Series or H8S/2623 Series)

SP CCR

(24bits)

CCR

(24bits)

Reserved*

EXR

(a) Interrupt control mode 0 (b) Interrupt control mode 2

Note: * Ignored on return.

Figure 4-5 (2) Stack Status after Exception Handling (Advanced Modes)

4.7 Notes on Use of the Stack

When accessing word data or longword data, the H8S/2626 Series or H8S/2623 Series assumes

that the lowest address bit is 0. The stack should always be accessed by word transfer instruction

or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be

kept even. Use the following instructions to save registers:

PUSH.W Rn (or MOV.W Rn, @-SP)

PUSH.L ERn (or MOV.L ERn, @-SP)

Use the following instructions to restore registers:

POP.W Rn (or MOV.W @SP+, Rn)

POP.L ERn (or MOV.L @SP+, ERn)

Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what

happens when the SP value is odd.

Legend

Note: This diagram illustrates an example in which the interrupt control mode

is 0, in advanced mode.

CCR

R1L

H'FFFEFA

H'FFFEFB

H'FFFEFC

H'FFFEFD

H'FFFEFF

MOV.B R1L, @–ER7

SP set to H'FFFEFF

TRAP instruction executed

Data saved above SP Contents of CCR lost

CCR: Condition code register

PC: Program counter

R1L: General register R1L

SP: Stack pointer

Figure 4-6 Operation when SP Value is Odd

Section 5 Interrupt Controller

5.1 Overview

5.1.1 Features

The H8S/2626 Series and H8S/2623 Series control interrupts by means of an interrupt controller.

The interrupt controller has the following features:

• Two interrupt control modes

 Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in

the system control register (SYSCR).

• Priorities settable with IPR

 An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority

levels can be set for each module for all interrupts except NMI.

 NMI is assigned the highest priority level of 8, and can be accepted at all times.

• Independent vector addresses

 All interrupt sources are assigned independent vector addresses, making it unnecessary for

the source to be identified in the interrupt handling routine.

• Seven external interrupts

 NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling

edge can be selected for NMI.

 Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5

to IRQ0.

• DTC control

 DTC activation is performed by means of interrupts.

5.1.2 Block Diagram

A block diagram of the interrupt controller is shown in Figure 5-1.

SYSCR

NMI input

IRQ input

Internal interrupt

request

SWDTEND to

SLE0

INTM1 INTM0

NMIEG

NMI input unit

IRQ input unit

ISR

ISCR IER

IPR

Interrupt controller

Priority

determination

Interrupt

request

Vector

number

I2 to I0 CCR

EXR

CPU

ISCR

IER

ISR

IPR

SYSCR

: IRQ sense control register

: IRQ enable register

: IRQ status register

: Interrupt priority register

: System control register

Legend

Figure 5-1 Block Diagram of Interrupt Controller

5.1.3 Pin Configuration

Table 5-1 summarizes the pins of the interrupt controller.

Table 5-1 Interrupt Controller Pins

Name Symbol I/O Function

Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or

falling edge can be selected

External interrupt

requests 5 to 0 IRQ5 to IRQ0 Input Maskable external interrupts; rising, falling, or

both edges, or level sensing, can be selected

5.1.4 Register Configuration

Table 5-2 summarizes the registers of the interrupt controller.

Table 5-2 Interrupt Controller Registers

Name Abbreviation R/W Initial Value Address*1

System control register SYSCR R/W H'01 H'FDE5

IRQ sense control register H ISCRH R/W H'00 H'FE12

IRQ sense control register L ISCRL R/W H'00 H'FE13

IRQ enable register IER R/W H'00 H'FE14

IRQ status register ISR R/(W)*2H'00 H'FE15

Interrupt priority register A IPRA R/W H'77 H'FEC0

Interrupt priority register B IPRB R/W H'77 H'FEC1

Interrupt priority register C IPRC R/W H'77 H'FEC2

Interrupt priority register D IPRD R/W H'77 H'FEC3

Interrupt priority register E IPRE R/W H'77 H'FEC4

Interrupt priority register F IPRF R/W H'77 H'FEC5

Interrupt priority register G IPRG R/W H'77 H'FEC6

Interrupt priority register H IPRH R/W H'77 H'FEC7

Interrupt priority register I IPRI R/W H'77 H'FEC8

Interrupt priority register J IPRJ R/W H'77 H'FEC9

Interrupt priority register K IPRK R/W H'77 H'FECA

Interrupt priority register M IPRM R/W H'77 H'FECC

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, for flag clearing.

5.2 Register Descriptions

5.2.1 System Control Register (SYSCR)

MACS

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

—

Bit

Initial value

R/W

SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the

detected edge for NMI.

Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control

SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in

software standby mode.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two

interrupt control modes for the interrupt controller.

Bit 5 Bit 4 Interrupt

INTM1 INTM0 Control Mode Description

0 0 0 Interrupts are controlled by I bit (Initial value)

1 — Setting prohibited

1 0 2 Interrupts are controlled by bits I2 to I0, and IPR

1 — Setting prohibited

Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.

Bit 3

NMIEG Description

0 Interrupt request generated at falling edge of NMI input (Initial value)

1 Interrupt request generated at rising edge of NMI input

5.2.2 Interrupt Priority Registers A to K, M (IPRA to IPRK, IPRM)

—

IPR6

R/W

IPR5

R/W

IPR4

R/W

—

IPR0

R/W

IPR2

R/W

IPR1

R/W

Bit

Initial value

R/W

The IPR registers are twelve 8-bit readable/writable registers that set priorities (levels 7 to 0) for

interrupts other than NMI.

The correspondence between IPR settings and interrupt sources is shown in table 5-3.

The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.

The IPR registers are initialized to H'77 by a reset and in hardware standby mode.

They are not initialized in software standby mode.

Bits 7 and 3—Reserved: These bits are always read as 0 and cannot be modified.

Table 5-3 Correspondence between Interrupt Sources and IPR Settings

Bits

IPRA IRQ0 IRQ1

IPRB IRQ2

IRQ3 IRQ4

IRQ5

IPRC —*1DTC

IPRD WDT0 —*1

IPRE PC break A/D converter, WDT1*2

IPRF TPU channel 0 TPU channel 1

IPRG TPU channel 2 TPU channel 3

IPRH TPU channel 4 TPU channel 5

IPRI —*1—*1

IPRJ —*1SCI channel 0

IPRK SCI channel 1 SCI channel 2

IPRM HCAN —*1

Notes: 1. Reserved bits. These bits are always read as 1 and cannot be modified.

2. Valid only in the H8S/2626 Series.

100

As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range

from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding

interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority

level, level 7, by setting H'7.

When interrupt requests are generated, the highest-priority interrupt according to the priority

levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt

mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if

the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to

the CPU.

5.2.3 IRQ Enable Register (IER)

—

R/W

—

R/W

IRQ5E

R/W

IRQ4E

R/W

IRQ3E

R/W

IRQ0E

R/W

IRQ2E

R/W

IRQ1E

R/W

Bit

Initial value

R/W

IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests

IRQ5 to IRQ0.

IER is initialized to H'00 by a reset and in hardware standby mode.

They are not initialized in software standby mode.

Bits 7 and 6—Reserved: Only 0 should be written to these bits.

Bits 5 to 0—IRQ5 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ5 to

IRQ0 are enabled or disabled.

Bit n

IRQnE Description

0 IRQn interrupts disabled (Initial value)

1 IRQn interrupts enabled

(n = 5 to 0)

101

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)

ISCRH

—

R/W

—

R/W

—

R/W

—

R/W

IRQ5SCB

R/W

IRQ4SCA

R/W

IRQ5SCA

R/W

IRQ4SCB

R/W

Bit

Initial value

R/W

ISCRL

IRQ3SCB

R/W

IRQ3SCA

R/W

IRQ2SCB

R/W

IRQ2SCA

R/W

IRQ1SCB

R/W

IRQ0SCA

R/W

IRQ1SCA

R/W

IRQ0SCB

R/W

Bit

Initial value

R/W

The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or

both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0.

The ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.

They are not initialized in software standby mode.

Bits 15 to 12—Reserved: Only 0 should be written to these bits.

Bits 11 to 0: IRQ7 Sense Control A and B (IRQ5SCA, IRQ5SCB) to IRQ0 Sense Control A and

B (IRQ0SCA, IRQ0SCB)

Bits 11 to 0

IRQ5SCB to

IRQ0SCB IRQ5SCA to

IRQ0SCA Description

0 0 Interrupt request generated at IRQ5 to IRQ0 input low level

(Initial value)

1 Interrupt request generated at falling edge of IRQ5 to IRQ0 input

1 0 Interrupt request generated at rising edge of IRQ5 to IRQ0 input

1 Interrupt request generated at both falling and rising edges of

IRQ5 to IRQ0 input

102

5.2.5 IRQ Status Register (ISR)

—

R/(W)*

—

R/(W)*

IRQ5F

R/(W)*

IRQ4F

R/(W)*

IRQ3F

R/(W)*

IRQ0F

R/(W)*

IRQ2F

R/(W)*

IRQ1F

R/(W)*

Bit

Initial value

R/W

Note: * Only 0 can be written, to clear the flag.

ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt

requests.

ISR is initialized to H'00 by a reset and in hardware standby mode.

They are not initialized in software standby mode.

Bits 7 and 6—Reserved: Only 0 should be written to these bits.

Bits 5 to 0—IRQ5 to IRQ0 flags (IRQ5F to IRQ0F): These bits indicate the status of IRQ7 to

IRQ0 interrupt requests.

Bit n

IRQnF Description

0 [Clearing conditions] (Initial value)

• Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag

• When interrupt exception handling is executed when low-level detection is set

(IRQnSCB = IRQnSCA = 0) and IRQn input is high

• When IRQn interrupt exception handling is executed when falling, rising, or both-edge

detection is set (IRQnSCB = 1 or IRQnSCA = 1)

• When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the

DTC is cleared to 0

1 [Setting conditions]

• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =

• When a falling edge occurs in IRQn input when falling edge detection is set

(IRQnSCB = 0, IRQnSCA = 1)

• When a rising edge occurs in IRQn input when rising edge detection is set

(IRQnSCB = 1, IRQnSCA = 0)

• When a falling or rising edge occurs in IRQn input when both-edge detection is set

(IRQnSCB = IRQnSCA = 1) (n = 5 to 0)

103

5.3 Interrupt Sources

Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts (48

sources: H8S/2626 Series, 47 sources: H8S/2623 Series).

5.3.1 External Interrupts

There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to

restore the H8S/2626 Series or H8S/2623 Series chip from software standby mode.

NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU

regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG

bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling

edge on the NMI pin.

The vector number for NMI interrupt exception handling is 7.

IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5

to IRQ0. Interrupts IRQ5 to IRQ0 have the following features:

• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling

edge, rising edge, or both edges, at pins IRQ5 to IRQ0.

• Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER.

• The interrupt priority level can be set with IPR.

• The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0

by software.

A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2.

IRQn interrupt

request

IRQnE

IRQnF

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input

Note: n: 5 to 0

Figure 5-2 Block Diagram of Interrupts IRQ5 to IRQ0

104

Figure 5-3 shows the timing of setting IRQnF.

IRQn

input pin

IRQnF

Figure 5-3 Timing of Setting IRQnF

The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16.

Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for

input or output. However, when a pin is used as an external interrupt input pin, do not clear the

corresponding DDR to 0 and use the pin as an I/O pin for another function.

5.3.2 Internal Interrupts

There are 48 sources for internal interrupts from on-chip supporting modules in the H8S/2626

Series, and 47 in the H8S/2623 Series.

• For each on-chip supporting module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1

for a particular interrupt source, an interrupt request is issued to the interrupt controller.

• The interrupt priority level can be set by means of IPR.

• The DTC can be activated by a TPU, 8-bit timer, SCI, or other interrupt request. When the

DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not

affected.

5.3.3 Interrupt Exception Handling Vector Table

Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority.

Priorities among modules can be set by means of the IPR. The situation when two or more

modules are set to the same priority, and priorities within a module, are fixed as shown in

table 5-4.

105

Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities

Origin of

Vector

Address*

Interrupt Source Interrupt

Source Vector

Number Advanced

Mode IPR Priority

NMI External 7 H'001C High

IRQ0 pin 16 H'0040 IPRA6 to 4

IRQ1 17 H'0044 IPRA2 to 0

IRQ2

IRQ3 18

19 H'0048

H'004C IPRB6 to 4

IRQ4

IRQ5 20

21 H'0050

H'0054 IPRB2 to 0

Reserved — 22

23 H'0058

H'005C IPRC6 to 4

SWDTEND (software activation

interrupt end) DTC 24 H'0060 IPRC2 to 0

WOVI0 (interval timer) Watchdog

timer 0 25 H'0064 IPRD6 to 4

Reserved — 26 H'0068 IPRD2 to 0

PC break PC break 27 H'006C IPRE6 to 4

ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to 0

WOVI1 (interval timer)

(H8S/2626 Series only) Watchdog

timer 1 29 H'0074

Reserved — 30

31 H'0078

H'007C

TGI0A (TGR0A input

capture/compare match)

TGI0B (TGR0B input

capture/compare match)

TGI0C (TGR0C input

capture/compare match)

TGI0D (TGR0D input

capture/compare match)

TCI0V (overflow 0)

TPU

channel 0 32

H'0080

H'0084

H'0088

H'008C

H'0090

IPRF6 to 4

Reserved — 37

H'0094

H'0098

H'009C Low

106

Origin of

Vector

Address*

Interrupt Source Interrupt

Source Vector

Number Advanced

Mode IPR Priority

TGI1A (TGR1A input

capture/compare match)

TGI1B (TGR1B input

capture/compare match)

TCI1V (overflow 1)

TCI1U (underflow 1)

TPU

channel 1 40

H'00A0

H'00A4

H'00A8

H'00AC

IPRF2 to 0 High

TGI2A (TGR2A input

capture/compare match)

TGI2B (TGR2B input

capture/compare match)

TCI2V (overflow 2)

TCI2U (underflow 2)

TPU

channel 2 44

H'00B0

H'00B4

H'00B8

H'00BC

IPRG6 to 4

TGI3A (TGR3A input

capture/compare match)

TGI3B (TGR3B input

capture/compare match)

TGI3C (TGR3C input

capture/compare match)

TGI3D (TGR3D input

capture/compare match)

TCI3V (overflow 3)

TPU

channel 3 48

H'00C0

H'00C4

H'00C8

H'00CC

H'00D0

IPRG2 to 0

Reserved — 53

H'00D4

H'00D8

H'00DC

TGI4A (TGR4A input

capture/compare match)

TGI4B (TGR4B input

capture/compare match)

TCI4V (overflow 4)

TCI4U (underflow 4)

TPU

channel 4 56

H'00E0

H'00E4

H'00E8

H'00EC

IPRH6 to 4

TGI5A (TGR5A input

capture/compare match)

TGI5B (TGR5B input

capture/compare match)

TCI5V (overflow 5)

TCI5U (underflow 5)

TPU

channel 5 60

H'00F0

H'00F4

H'00F8

H'00FC

IPRH2 to 0

Low

107

Origin of

Vector

Address*

Interrupt Source Interrupt

Source Vector

Number Advanced

Mode IPR Priority

Reserved — 64

H'0100

H'0104

H'0108

IPRI6 to 4 High

67 H'010C

H'0110

H'0114

H'0118

IPRI2 to 0

71 H'011C

H'0120

H'0124

H'0128

H'012C

IPRJ6 to 4

H'0130

H'0134

H'0138

H'013C

ERI0 (receive error 0)

RXI0 (reception completed 0)

TXI0 (transmit data empty 0)

TEI0 (transmission end 0)

SCI

channel 0 80

H'0140

H'0144

H'0148

H'014C

IPRJ2 to 0

ERI1 (receive error 1)

RXI1 (reception completed 1)

TXI1 (transmit data empty 1)

TEI1 (transmission end 1)

SCI

channel 1 84

H'0150

H'0154

H'0158

H'015C

IPRK6 to 4

ERI2 (receive error 2)

RXI2 (reception completed 2)

TXI2 (transmit data empty 2)

TEI2 (transmission end 2)

SCI

channel 2 88

H'0160

H'0164

H'0168

H'016C

IPRK2 to 0

ERS0

OVR0

RM0

RM1

HCAN 104

105

106

107

H'01A0

H'01A4

H'01A8

H'01AC

IPRM6 to 4

SLE0 108 H'01B0 IPRM2 to 0 Low

Note: * Lower 16 bits of the start address.

108

5.4 Interrupt Operation

5.4.1 Interrupt Control Modes and Interrupt Operation

Interrupt operations in the H8S/2626 Series and H8S/2623 Series differ depending on the interrupt

control mode.

NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In

the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for

each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt

sources for which the enable bits are set to 1 are controlled by the interrupt controller.

Table 5-5 shows the interrupt control modes.

The interrupt controller performs interrupt control according to the interrupt control mode set by

the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated

by the I and UI bits in the CPU’s CCR, and bits I2 to I0 in EXR.

Table 5-5 Interrupt Control Modes

Interrupt SYSCR Priority Setting Interrupt

Control Mode INTM1 INTM0 Registers Mask Bits Description

0 0 0 — I Interrupt mask control is

performed by the I bit.

— 1 — — Setting prohibited

2 1 0 IPR I2 to I0 8-level interrupt mask control

is performed by bits I2 to I0.

8 priority levels can be set with

IPR.

— 1 — — Setting prohibited

109

Figure 5-4 shows a block diagram of the priority decision circuit.

Interrupt

acceptance

control

8-level

mask control

Default priority

determination Vector number

Interrupt control mode 2

IPR

Interrupt source

I2 to I0

Interrupt

control

mode 0 I

Figure 5-4 Block Diagram of Interrupt Control Operation

(1) Interrupt Acceptance Control

In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.

Table 5-6 shows the interrupts selected in each interrupt control mode.

Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1)

Interrupt Mask Bits

Interrupt Control Mode I Selected Interrupts

0 0 All interrupts

1 NMI interrupts

2*All interrupts

* : Don't care

110

(2) 8-Level Control

In interrupt control mode 2, 8-level mask level determination is performed for the selected

interrupts in interrupt acceptance control according to the interrupt priority level (IPR).

The interrupt source selected is the interrupt with the highest priority level, and whose priority

level set in IPR is higher than the mask level.

Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2)

Interrupt Control Mode Selected Interrupts

0 All interrupts

2 Highest-priority-level (IPR) interrupt whose priority level is greater

than the mask level (IPR > I2 to I0).

(3) Default Priority Determination

When an interrupt is selected by 8-level control, its priority is determined and a vector number is

generated.

If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the

interrupt source with the highest priority according to the preset default priorities is selected and

has a vector number generated.

Interrupt sources with a lower priority than the accepted interrupt source are held pending.

Table 5-8 shows operations and control signal functions in each interrupt control mode.

Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode

Interrupt

Control Setting Interrupt

Acceptance Control 8-Level Control Default Priority T

Mode INTM1 INTM0 I I2 to I0 IPR Determination (Trace)

000 IM X — —*2—

210 X—*1IM PR T

Legend

: Interrupt operation control performed

X : No operation. (All interrupts enabled)

IM : Used as interrupt mask bit

PR : Sets priority.

— : Not used.

Notes: 1. Set to 1 when interrupt is accepted.

2. Keep the initial setting.

111

5.4.2 Interrupt Control Mode 0

Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by

means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and

disabled when set to 1.

Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case.

[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt

request is sent to the interrupt controller.

[2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I

bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.

[3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to

the priority system is accepted, and other interrupt requests are held pending.

[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

[5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the

interrupt handling routine.

[6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.

[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling

routine starts at the address indicated by the contents of that vector address.

112

Program execution status

Interrupt generated?

NMI

IRQ0

IRQ1

SLE0

I=0

Save PC and CCR

I←1

Read vector address

Branch to interrupt handling routine

Yes

Yes No

Yes

Hold pending

Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in

Interrupt Control Mode 0

113

5.4.3 Interrupt Control Mode 2

Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts

by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR.

Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case.

[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt

request is sent to the interrupt controller.

[2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest

priority according to the interrupt priority levels set in IPR is selected, and lower-priority

interrupt requests are held pending. If a number of interrupt requests with the same priority are

generated at the same time, the interrupt request with the highest priority according to the

priority system shown in table 5-4 is selected.

[3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set

in EXR. An interrupt request with a priority no higher than the mask level set at that time is

held pending, and only an interrupt request with a priority higher than the interrupt mask level

is accepted.

[4] When an interrupt request is accepted, interrupt exception handling starts after execution of the

current instruction has been completed.

[5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC

saved on the stack shows the address of the first instruction to be executed after returning from

the interrupt handling routine.

[6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of

the accepted interrupt.

If the accepted interrupt is NMI, the interrupt mask level is set to H'7.

[7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling

routine starts at the address indicated by the contents of that vector address.

114

Yes

Program execution status

Interrupt generated?

NMI

Level 6 interrupt?

Mask level 5

or below?

Level 7 interrupt?

Mask level 6

or below?

Save PC, CCR, and EXR

Clear T bit to 0

Update mask level

Read vector address

Branch to interrupt handling routine

Hold pending

Level 1 interrupt?

Mask level 0?

Yes

No Yes

Yes

Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in

Interrupt Control Mode 2

115

5.4.4 Interrupt Exception Handling Sequence

Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case

where interrupt control mode 0 is set in advanced mode, and the program area and stack area are

in on-chip memory.

(14)(12)(10)(8)(6)(4)(2)

(1) (5) (7) (9) (11) (13)

Interrupt service

routine instruction

prefetch

Internal

operation

Vector fetchStack

Instruction

prefetch Internal

operation

Interrupt

acceptance

Interrupt level determination

Wait for end of instruction

Interrupt

request signal

Internal

address bus

Internal

read signal

Internal

write signal

Internal

data us

(3)

(1)

(2) (4)

(3)

(5)

(7)

Instruction prefetch address (Not executed.

This is the contents of the saved PC, the return address.)

Instruction code (Not executed.)

Instruction prefetch address (Not executed.)

SP-2

SP-4

Saved PC and saved CCR

Vector address

Interrupt handling routine start address (vector

address contents)

Interrupt handling routine start address ((13) = (10) (12))

First instruction of interrupt handling routine

(6) (8)

(9) (11)

(10) (12)

(13)

(14)

Figure 5-7 Interrupt Exception Handling

116

5.4.5 Interrupt Response Times

The H8S/2626 Series and H8S/2623 Series are capable of fast word transfer to on-chip memory,

and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-

speed processing.

Table 5-9 shows interrupt response times - the interval between generation of an interrupt request

and execution of the first instruction in the interrupt handling routine. The execution status

symbols used in table 5-9 are explained in table 5-10.

Table 5-9 Interrupt Response Times

Normal Mode*5Advanced Mode

No. Execution Status INTM1 = 0 INTM1 = 1 INTM1 = 0 INTM1 = 1

1 Interrupt priority determination*133 33

2 Number of wait states until executing

instruction ends*21 to

(19+2·SI)1 to

(19+2·SI)

3 PC, CCR, EXR stack save 2·SK3·SK2·SK3·SK

4 Vector fetch SISI2·SI2·SI

5 Instruction fetch*32·SI2·SI2·SI2·SI

6 Internal processing*422 22

Total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33

Notes: 1. Two states in case of internal interrupt.

2. Refers to MULXS and DIVXS instructions.

3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.

4. Internal processing after interrupt acceptance and internal processing after vector fetch.

5. Not available in the H8S/2626 Series or H8S/2623 Series.

117

Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses

Object of Access

External Device

8 Bit Bus 16 Bit Bus

Symbol Internal

Memory 2-State

Access 3-State

Access 2-State

Access 3-State

Access

Instruction fetch SI1 4 6+2m 2 3+m

Branch address read SJ

Stack manipulation SK

Legend

m : Number of wait states in an external device access.

5.5 Usage Notes

5.5.1 Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective

after execution of the instruction.

In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or

MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will

still be enabled on completion of the instruction, and so interrupt exception handling for that

interrupt will be executed on completion of the instruction. However, if there is an interrupt

request of higher priority than that interrupt, interrupt exception handling will be executed for the

higher-priority interrupt, and the lower-priority interrupt will be ignored.

The same also applies when an interrupt source flag is cleared to 0.

Figure 5-8 shows an example in which the TCIEV bit in the TPU’s TIER0 register is cleared to 0.

118

Internal

address bus

Internal

write signal

TCIEV

TCFV

TCIV

interrupt signal

TIER0 write cycle by CPU TCIV exception handling

TIER0 address

Figure 5-8 Contention between Interrupt Generation and Disabling

The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while

the interrupt is masked.

5.5.2 Instructions that Disable Interrupts

Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these

instructions is executed, all interrupts including NMI are disabled and the next instruction is

always executed. When the I bit is set by one of these instructions, the new value becomes valid

two states after execution of the instruction ends.

5.5.3 Times when Interrupts are Disabled

There are times when interrupt acceptance is disabled by the interrupt controller.

The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has

updated the mask level with an LDC, ANDC, ORC, or XORC instruction.

119

5.5.4 Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the move is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

L1: EEPMOV.W

MOV.W R4,R4

BNE L1

5.6 DTC Activation by Interrupt

5.6.1 Overview

The DTC can be activated by an interrupt. In this case, the following options are available:

• Interrupt request to CPU

• Activation request to DTC

• Selection of a number of the above

For details of interrupt requests that can be used with to activate the DTC, see section 8, Data

Transfer Controller.

5.6.2 Block Diagram

Figure 5-9 shows a block diagram of the DTC interrupt controller.

120

Selection

circuit

DTCER

DTVECR

Control logic

Determination of

priority CPU

DTC

DTC activation

request vector

number

Clear signal

CPU interrupt

request vector

number

Select

signal

Interrupt

request

Interrupt source

clear signal

IRQ

interrupt

On-chip

supporting

module

Clear signal

Interrupt controller I, I2 to I0

SWDTE

clear signal

Figure 5-9 Interrupt Control for DTC

5.6.3 Operation

The interrupt controller has three main functions in DTC control.

(1) Selection of Interrupt Source: Interrupt sources can be specified as DTC activation requests

or CPU interrupt requests by means of the DTCE bit of DTCERA to DTCERG in the DTC.

After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the

CPU in accordance with the specification of the DISEL bit of MRB in the DTC.

When the DTC has performed the specified number of data transfers and the transfer counter value

is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data

transfer.

(2) Determination of Priority: The DTC activation source is selected in accordance with the

default priority order, and is not affected by mask or priority levels. See section 8.3.3, DTC Vector

Table, for the respective priorities.

(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU

interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception

handling.

Table 5-11 summarizes interrupt source selection and interrupt source clearance control according

to the settings of the DTCE bit of DTCERA to DTCERG in the DTC, and the DISEL bit of MRB

in the DTC.

121

Table 5-11 Interrupt Source Selection and Clearing Control

Settings

DTC Interrupt Source Selection/Clearing Control

DTCE DISEL DTC CPU

0*X

10 X

** XX

Legend

: The relevant interrupt is used. Interrupt source clearing is performed.

(The CPU should clear the source flag in the interrupt handling routine.)

O : The relevant interrupt is used. The interrupt source is not cleared.

X : The relevant bit cannot be used.

*: Don’t care

(4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DTC reads or

writes to the prescribed register, and are not dependent upon the DTCE and DISEL bits.

122

123

Section 6 PC Break Controller (PBC)

6.1 Overview

The PC break controller (PBC) provides functions that simplify program debugging. Using these

functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with

the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC:

instruction fetch, data read, data write, and data read/write.

6.1.1 Features

The PC break controller has the following features:

• Two break channels (A and B)

• The following can be set as break compare conditions:

 24 address bits

Bit masking possible

 Bus cycle

Instruction fetch

Data access: data read, data write, data read/write

 Bus master

Either CPU or CPU/DTC can be selected

• The timing of PC break exception handling after the occurrence of a break condition is as

follows:

 Immediately before execution of the instruction fetched at the set address (instruction fetch)

 Immediately after execution of the instruction that accesses data at the set address (data

access)

• Module stop mode can be set

 The initial setting is for PBC operation to be halted. Register access is enabled by clearing

module stop mode.

124

6.1.2 Block Diagram

Figure 6-1 shows a block diagram of the PC break controller.

Output control

Mask control

Output control

Match signal

PC break

interrupt

Match signal

Mask control

BARA BCRA

BARB BCRB

Comparator Control

logic

Comparator Control

logic

Internal address

Access

status

Figure 6-1 Block Diagram of PC Break Controller

125

6.1.3 Register Configuration

Table 6-1 shows the PC break controller registers.

Table 6-1 PC Break Controller Registers

Initial Value

Name Abbreviation R/W Reset Manual Reset*3Address*1

Break address register A BARA R/W H'000000 Retained H'FE00

Break address register B BARB R/W H'000000 Retained H'FE04

Break control register A BCRA R/(W)*2H'00 Retained H'FE08

Break control register B BCRB R/(W)*2H'00 Retained H'FE09

Module stop control register C MSTPCRC R/W H'FF Retained H'FDEA

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, for flag clearing.

3. Not available in the H8S/2626 Series or H8S/2623 Series.

6.2 Register Descriptions

6.2.1 Break Address Register A (BARA)

Bit

Initial value

R/W —

—

Unde-

fined —

—

Unde-

fined R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

R/W

BAA

• • •

BARA is a 32-bit readable/writable register that specifies the channel A break address.

BAA23 to BAA0 are initialized to H'000000 by a reset and in hardware standby mode.

Bits 31 to 24—Reserved: These bits return an undefined value if read, and cannot be modified.

Bits 23 to 0—Break Address A23 to A0 (BAA23–BAA0): These bits hold the channel A PC

break address.

126

6.2.2 Break Address Register B (BARB)

BARB is the channel B break address register. The bit configuration is the same as for BARA.

6.2.3 Break Control Register A (BCRA)

Bit

Initial value

R/W

Note: * Only 0 can be written, for flag clearing.

R/(W)*

CMFA

R/W

CDA

R/W

BAMRA2

R/W

BAMRA1

R/W

BAMRA0

R/W

CSELA1

R/W

CSELA0

R/W

BIEA

BCRA is an 8-bit readable/writable register that controls channel A PC breaks. BCRA (1) selects

the break condition bus master, (2) specifies bits subject to address comparison masking, and (3)

specifies whether the break condition is applied to an instruction fetch or a data access. It also

contains a condition match flag.

BCRA is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—Condition Match Flag A (CMFA): Set to 1 when a break condition set for channel A is

satisfied. This flag is not cleared to 0.

Bit 7

CMFA Description

0 [Clearing condition]

When 0 is written to CMFA after reading CMFA = 1 (Initial value)

1 [Setting condition]

When a condition set for channel A is satisfied

Bit 6—CPU Cycle/DTC Cycle Select A (CDA): Selects the channel A break condition bus

master.

Bit 6

CDA Description

0 PC break is performed when CPU is bus master (Initial value)

1 PC break is performed when CPU or DTC is bus master

127

Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2 to BAMRA0): These bits

specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked.

Bit 5 Bit 4 Bit 3

BAMRA2 BAMRA1 BAMRA0 Description

0 0 0 All BARA bits are unmasked and included in break conditions

(Initial value)

1 BAA0 (lowest bit) is masked, and not included in break

conditions

1 0 BAA1–0 (lower 2 bits) are masked, and not included in break

conditions

1 BAA2–0 (lower 3 bits) are masked, and not included in break

conditions

1 0 0 BAA3–0 (lower 4 bits) are masked, and not included in break

conditions

1 BAA7–0 (lower 8 bits) are masked, and not included in break

conditions

1 0 BAA11–0 (lower 12 bits) are masked, and not included in break

conditions

1 BAA15–0 (lower 16 bits) are masked, and not included in break

conditions

Bits 2 and 1—Break Condition Select A (CSELA1, CSELA0): These bits select an instruction

fetch, data read, data write, or data read/write cycle as the channel A break condition.

Bit 2 Bit 1

CSELA1 CSELA0 Description

0 0 Instruction fetch is used as break condition (Initial value)

1 Data read cycle is used as break condition

1 0 Data write cycle is used as break condition

1 Data read/write cycle is used as break condition

Bits 0—Break Interrupt Enable A (BIEA): Enables or disables channel A PC break interrupts.

Bit 0

BIEA Description

0 PC break interrupts are disabled (Initial value)

1 PC break interrupts are enabled

128

6.2.4 Break Control Register B (BCRB)

BCRB is the channel B break control register. The bit configuration is the same as for BCRA.

6.2.5 Module Stop Control Register C (MSTPCRC)

MSTPC7

R/W

Bit

Initial value

R/W

MSTPC6

R/W

MSTPC5

R/W

MSTPC4

R/W

MSTPC3

R/W

MSTPC2

R/W

MSTPC1

R/W

MSTPC0

R/W

MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPC4 bit is set to 1, PC break controller operation is stopped at the end of the bus

cycle, and module stop mode is entered. Register read/write accesses are not possible in module

stop mode. For details, see section 20.5, Module Stop Mode.

MSTPCRC is initialized to H'FF by a power on reset and in hardware standby mode. It is not

initialized in software standby mode.

Bit 4—Module Stop (MSTPC4): Specifies the PC break controller module stop mode.

Bit 4

MSTPC4 Description

0 PC break controller module stop mode is cleared

1 PC break controller module stop mode is set (Initial value)

129

6.3 Operation

The operation flow from break condition setting to PC break interrupt exception handling is shown

in sections 6.3.1 and 6.3.2, taking the example of channel A.

6.3.1 PC Break Interrupt Due to Instruction Fetch

(1) Initial settings

 Set the break address in BARA. For a PC break caused by an instruction fetch, set the

address of the first instruction byte as the break address.

 Set the break conditions in BCRA.

BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must

be the CPU. Set 0 to select the CPU.

BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.

BCRA bits 2–1 (CSELA1–0): Set 00 to specify an instruction fetch as the break condition.

BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.

(2) Satisfaction of break condition

 When the instruction at the set address is fetched, a PC break request is generated

immediately before execution of the fetched instruction, and the condition match flag

(CMFA) is set.

(3) Interrupt handling

 After priority determination by the interrupt controller, PC break interrupt exception

handling is started.

6.3.2 PC Break Interrupt Due to Data Access

(1) Initial settings

 Set the break address in BARA. For a PC break caused by a data access, set the target

ROM, RAM, I/O, or external address space address as the break address. Stack operations

and branch address reads are included in data accesses.

 Set the break conditions in BCRA.

BCRA bit 6 (CDA): Select the bus master.

BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.

BCRA bits 2–1 (CSELA1–0): Set 01, 10, or 11 to specify data access as the break

condition.

BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.

130

(2) Satisfaction of break condition

 After execution of the instruction that performs a data access on the set address, a PC break

request is generated and the condition match flag (CMFA) is set.

(3) Interrupt handling

 After priority determination by the interrupt controller, PC break interrupt exception

handling is started.

6.3.3 Notes on PC Break Interrupt Handling

(1) The PC break interrupt is shared by channels A and B. The channel from which the request

was issued must be determined by the interrupt handler.

(2) The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB

after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be

requested after interrupt handling ends.

(3) A PC break interrupt generated when the DTC is the bus master is accepted after the bus has

been transferred to the CPU by the bus controller.

6.3.4 Operation in Transitions to Power-Down Modes

The operation when a PC break interrupt is set for an instruction fetch at the address after a

SLEEP instruction is shown below.

(1) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to

sleep mode, or from subactive mode to subsleep mode:

After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep

mode, and PC break interrupt handling is executed. After execution of PC break interrupt

handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2

(A)).

(2) When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to

subactive mode:

After execution of the SLEEP instruction, a transition is made to subactive mode via direct

transition exception handling. After the transition, PC break interrupt handling is executed,

then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B))

(Supported only in the H8S/2626 Series).

(3) When the SLEEP instruction causes a transition from subactive mode to high-speed (medium-

speed) mode:

131

After execution of the SLEEP instruction, and following the clock oscillation settling time, a

transition is made to high-speed (medium-speed) mode via direct transition exception

handling. After the transition, PC break interrupt handling is executed, then the instruction at

the address after the SLEEP instruction is executed (figure 6-2 (C)) (Supported only in the

H8S/2626 Series).

(4) When the SLEEP instruction causes a transition to software standby mode or watch mode:

After execution of the SLEEP instruction, a transition is made to the respective mode, and PC

break interrupt handling is not executed. However, the CMFA or CMFB flag is set (figure 6-2

(D)).

SLEEP instruction

execution

High-speed

(medium-speed)

mode

SLEEP instruction

execution

Subactive

mode

System clock

→ subclock

Direct transition

exception handling

PC break exception

handling

Execution of instruction

after sleep instruction

Subclock →

system clock,

oscillation settling time

SLEEP instruction

execution

Transition to

respective mode

Direct transition

exception handling

PC break exception

handling

Execution of instruction

after sleep instruction

PC break exception

handling

Execution of instruction

after sleep instruction

Note: *Supported only in the H8S/2626 Series.

(A)

(B)*(C)*

(D)

SLEEP instruction

execution

Figure 6-2 Operation in Power-Down Mode Transitions

6.3.5 PC Break Operation in Continuous Data Transfer

If a PC break interrupt is generated when the following operations are being performed, exception

handling is executed on completion of the specified transfer.

(1) When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction:

PC break exception handling is executed after all data transfers have been completed and the

EEPMOV.B instruction has ended.

(2) When a PC break interrupt is generated at a DTC transfer address:

PC break exception handling is executed after the DTC has completed the specified number of

data transfers, or after data for which the DISEL bit is set to 1 has been transferred.

132

6.3.6 When Instruction Execution is Delayed by One State

Caution is required in the following cases, as instruction execution is one state later than usual.

(1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a

one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on-

chip ROM or RAM is always delayed by one state.

(2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or

RAM space, and that address is used for data access, the instruction that executes the data

access is one state later than in normal operation.

(3) When break interruption by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction has one of the addressing

modes shown below, and that address indicates on-chip ROM or RAM, and that address is

used for data access, the instruction will be one state later than in normal operation.

@ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC),

@(d:16,PC), @@aa:8

(4) When break interruption by instruction fetch is set and a break interrupt is generated, if the

executing instruction immediately preceding the set instruction is NOP or SLEEP, or has

#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the

instruction will be one state later than in normal operation.

133

6.3.7 Additional Notes

(1) When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP,

TRAPA, RTE, or RTS instruction:

Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS

instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the

instruction fetch at the next address.

(2) When the I bit is set by an LDC, ANDC, ORC, or XORC instruction, a PC break interrupt

becomes valid two states after the end of the executing instruction. If a PC break interrupt is

set for the instruction following one of these instructions, since interrupts, including NMI, are

disabled for a 3-state period in the case of LDC, ANDC, ORC, and XORC, the next instruction

is always executed. For details, see section 5, Interrupt Controller.

(3) When a PC break is set for an instruction fetch at the address following a Bcc instruction:

A PC break interrupt is generated if the instruction at the next address is executed in

accordance with the branch condition, but is not generated if the instruction at the next address

is not executed.

(4) When a PC break is set for an instruction fetch at the branch destination address of a Bcc

instruction:

A PC break interrupt is generated if the instruction at the branch destination is executed in

accordance with the branch condition, but is not generated if the instruction at the branch

destination is not executed.

134

135

Section 7 Bus Controller

7.1 Overview

The H8S/2626 Series and H8S/2623 Series have an on-chip bus controller (BSC) that manages the

external address space divided into eight areas. The bus specifications, such as bus width and

number of access states, can be set independently for each area, enabling multiple memories to be

connected easily.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus

masters: the CPU and data transfer controller (DTC).

7.1.1 Features

The features of the bus controller are listed below.

• Manages external address space in area units

 Manages the external space as 8 areas of 2-Mbytes

 Bus specifications can be set independently for each area

 Burst ROM interface can be set

• Basic bus interface

 8-bit access or 16-bit access can be selected for each area

 2-state access or 3-state access can be selected for each area

 Program wait states can be inserted for each area

• Burst ROM interface

 Burst ROM interface can be set for area 0

 Choice of 1- or 2-state burst access

• Idle cycle insertion

 An idle cycle can be inserted in case of an external read cycle between different areas

 An idle cycle can be inserted in case of an external write cycle immediately after an

external read cycle

• Write buffer functions

 External write cycle and internal access can be executed in parallel

• Bus arbitration function

 Includes a bus arbiter that arbitrates bus mastership among the CPU and DTC

136

• Other features

 External bus release function

7.1.2 Block Diagram

Figure 7-1 shows a block diagram of the bus controller.

Area decoder

Bus

controller

ABWCR

ASTCR

BCRH

BCRL

Internal

address bus

External bus control signals

Legend

ABWCR: Bus width control register

ASTCR: Access state control register

BCRH: Bus control register H

BCRL: Bus control register L

WCRH: Wait control register H

WCRL: Wait control register L

BREQ

BACK

BREQO

Internal control

signals

Wait

controller WCRH

WCRL

Bus mode signal

Bus arbiter

CPU bus request signal

DTC bus request signal

CPU bus acknowledge signal

DTC bus acknowledge signal

WAIT

Internal data bus

Figure 7-1 Block Diagram of Bus Controller

137

7.1.3 Pin Configuration

Table 7-1 summarizes the pins of the bus controller.

Table 7-1 Bus Controller Pins

Name Symbol I/O Function

Address strobe AS Output Strobe signal indicating that address output on address

bus is enabled.

Read RD Output Strobe signal indicating that external space is being

read.

High write HWR Output Strobe signal indicating that external space is to be

written, and upper half (D15 to D8) of data bus is

enabled.

Low write LWR Output Strobe signal indicating that external space is to be

written, and lower half (D7 to D0) of data bus is enabled.

Wait WAIT Input Wait request signal when accessing external 3-state

access space.

Bus request BREQ Input Request signal that releases bus to external device.

Bus request

acknowledge BACK Output Acknowledge signal indicating that bus has been

released.

Bus request output BREQO Output External bus request signal used when internal bus

master accesses external space when external bus is

released.

138

7.1.4 Register Configuration

Table 7-2 summarizes the registers of the bus controller.

Table 7-2 Bus Controller Registers

Initial Value

Name Abbreviation R/W Reset Manual Reset*3Address*1

Bus width control register ABWCR R/W H'FF/H'00*2Retained H'FED0

Access state control register ASTCR R/W H'FF Retained H'FED1

Wait control register H WCRH R/W H'FF Retained H'FED2

Wait control register L WCRL R/W H'FF Retained H'FED3

Bus control register H BCRH R/W H'D0 Retained H'FED4

Bus control register L BCRL R/W H'08 Retained H'FED5

Pin function control register PFCR R/W H'0D/H'00 Retained H'FDEB

Notes: 1. Lower 16 bits of the address.

2. Determined by the MCU operating mode.

3. Not available in the H8S/2623 Series.

139

7.2 Register Descriptions

7.2.1 Bus Width Control Register (ABWCR)

ABW7

R/W

ABW6

R/W

ABW5

R/W

ABW4

R/W

ABW3

R/W

ABW0

R/W

ABW2

R/W

ABW1

R/W

Bit :

Initial value :

Modes 5 to 7

Mode 4

:R/W

Initial value :

:R/W

ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or

16-bit access.

ABWCR sets the data bus width for the external memory space. The bus width for on-chip

memory and internal I/O registers is fixed regardless of the settings in ABWCR.

After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 5 to 7, and to

H'00 in mode 4. It is not initialized in software standby mode.

Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the

corresponding area is to be designated for 8-bit access or 16-bit access.

Bit n

ABWn Description

0 Area n is designated for 16-bit access

1 Area n is designated for 8-bit access

(n = 7 to 0)

140

7.2.2 Access State Control Register (ASTCR)

AST7

R/W

AST6

R/W

AST5

R/W

AST4

R/W

AST3

R/W

AST0

R/W

AST2

R/W

AST1

R/W

Bit

Initial value

R/W

ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access

space or a 3-state access space.

ASTCR sets the number of access states for the external memory space. The number of access

states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.

ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the

corresponding area is to be designated as a 2-state access space or a 3-state access space.

Wait state insertion is enabled or disabled at the same time.

Bit n

ASTn Description

0 Area n is designated for 2-state access

Wait state insertion in area n external space is disabled

1 Area n is designated for 3-state access (Initial value)

Wait state insertion in area n external space is enabled

(n = 7 to 0)

141

7.2.3 Wait Control Registers H and L (WCRH, WCRL)

WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait

states for each area.

Program waits are not inserted in the case of on-chip memory or internal I/O registers.

WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not

initialized in software standby mode.

(1) WCRH

W71

R/W

W70

R/W

W61

R/W

W60

R/W

W51

R/W

W40

R/W

W50

R/W

W41

R/W

Bit

Initial value

R/W

Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of

program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set

to 1.

Bit 7 Bit 6

W71 W70 Description

0 0 Program wait not inserted when external space area 7 is accessed

1 1 program wait state inserted when external space area 7 is accessed

1 0 2 program wait states inserted when external space area 7 is accessed

1 3 program wait states inserted when external space area 7 is accessed

(Initial value)

Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of

program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set

to 1.

Bit 5 Bit 4

W61 W60 Description

0 0 Program wait not inserted when external space area 6 is accessed

1 1 program wait state inserted when external space area 6 is accessed

1 0 2 program wait states inserted when external space area 6 is accessed

1 3 program wait states inserted when external space area 6 is accessed

(Initial value)

142

Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of

program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set

to 1.

Bit 3 Bit 2

W51 W50 Description

0 0 Program wait not inserted when external space area 5 is accessed

1 1 program wait state inserted when external space area 5 is accessed

1 0 2 program wait states inserted when external space area 5 is accessed

1 3 program wait states inserted when external space area 5 is accessed

(Initial value)

Bits 1 and 0—Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of

program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set

to 1.

Bit 1 Bit 0

W41 W40 Description

0 0 Program wait not inserted when external space area 4 is accessed

1 1 program wait state inserted when external space area 4 is accessed

1 0 2 program wait states inserted when external space area 4 is accessed

1 3 program wait states inserted when external space area 4 is accessed

(Initial value)

143

(2) WCRL

W31

R/W

W30

R/W

W21

R/W

W20

R/W

W11

R/W

W00

R/W

W10

R/W

W01

R/W

Bit

Initial value

R/W

Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of

program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set

to 1.

Bit 7 Bit 6

W31 W30 Description

0 0 Program wait not inserted when external space area 3 is accessed

1 1 program wait state inserted when external space area 3 is accessed

1 0 2 program wait states inserted when external space area 3 is accessed

1 3 program wait states inserted when external space area 3 is accessed

(Initial value)

Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of

program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set

to 1.

Bit 5 Bit 4

W21 W20 Description

0 0 Program wait not inserted when external space area 2 is accessed

1 1 program wait state inserted when external space area 2 is accessed

1 0 2 program wait states inserted when external space area 2 is accessed

1 3 program wait states inserted when external space area 2 is accessed

(Initial value)

144

Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of

program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set

to 1.

Bit 3 Bit 2

W11 W10 Description

0 0 Program wait not inserted when external space area 1 is accessed

1 1 program wait state inserted when external space area 1 is accessed

1 0 2 program wait states inserted when external space area 1 is accessed

1 3 program wait states inserted when external space area 1 is accessed

(Initial value)

Bits 1 and 0—Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of

program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set

to 1.

Bit 1 Bit 0

W01 W00 Description

0 0 Program wait not inserted when external space area 0 is accessed

1 1 program wait state inserted when external space area 0 is accessed

1 0 2 program wait states inserted when external space area 0 is accessed

1 3 program wait states inserted when external space area 0 is accessed

(Initial value)

145

7.2.4 Bus Control Register H (BCRH)

ICIS1

R/W

ICIS0

R/W

BRSTRM

R/W

BRSTS1

R/W

BRSTS0

R/W

—

R/W

—

R/W

—

R/W

Bit

Initial value

R/W

BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle

insertion, and the memory interface for area 0.

BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted

between bus cycles when successive external read cycles are performed in different areas.

Bit 7

ICIS1 Description

0 Idle cycle not inserted in case of successive external read cycles in different areas

1 Idle cycle inserted in case of successive external read cycles in different areas

(Initial value)

Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted

between bus cycles when successive external read and external write cycles are performed .

Bit 6

ICIS0 Description

0 Idle cycle not inserted in case of successive external read and external write cycles

1 Idle cycle inserted in case of successive external read and external write cycles

(Initial value)

Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM

interface.

Bit 5

BRSTRM Description

0 Area 0 is basic bus interface (Initial value)

1 Area 0 is burst ROM interface

146

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM

interface.

Bit 4

BRSTS1 Description

0 Burst cycle comprises 1 state

1 Burst cycle comprises 2 states (Initial value)

Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a

burst ROM interface burst access.

Bit 3

BRSTS0 Description

0 Max. 4 words in burst access (Initial value)

1 Max. 8 words in burst access

Bits 2 to 0—Reserved: Only 0 should be written to these bits.

147

7.2.5 Bus Control Register L (BCRL)

BRLE

R/W

BREQOE

R/W

—

R/W

—

R/W

WAITE

R/W

—

R/W

WDBE

R/W

Bit

Initial value

R/W

BCRL is an 8-bit readable/writable register that performs selection of the external bus-released

state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of

WAIT pin input.

BCRL is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.

Bit 7

BRLE Description

0 External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O

ports. (Initial value)

1 External bus release is enabled.

Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master

to drop the bus request signal (BREQ) in the external bus release state, when an internal bus

master performs an external space access, or when a refresh request is generated.

Bit 6

BREQOE Description

0BREQO output disabled. BREQO can be used as I/O port. (Initial value)

1BREQO output enabled.

Bit 5—Reserved: This bit cannot be modified and is always read as 0.

Bit 4—Reserved: Only 0 should be written to this bit.

Bit 3—Reserved: Only 1 should be written to this bit.

Bit 2—Reserved: Only 0 should be written to this bit.

148

Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is

used for an external write cycle.

Bit 1

WDBE Description

0 Write data buffer function not used (Initial value)

1 Write data buffer function used

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT

pin.

Bit 0

WAITE Description

0 Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. (Initial value)

1 Wait input by WAIT pin enabled

7.2.6 Pin Function Control Register (PFCR)

—

R/W

—

R/W

BUZZE

R/W

—

R/W

AE3

1/0

R/W

AE0

1/0

R/W

AE2

1/0

R/W

AE1

R/W

Bit

Initial value

R/W

PFCR is an 8-bit readable/writable register that performs address output control in external

expanded mode.

PFCR is initialized to H'0D/H'00 by a reset and in hardware standby mode. It retains its previous

state in software standby mode.

Bits 7 and 6—Reserved: Only 0 should be written to these bits.

Bit 5—BUZZ Output Enable (BUZZE): Enables or disables BUZZ output from the PF1 pin. For

details, see section 12.2.4, Pin Function Control Register (PFCR).

Bit 4—Reserved: Only 0 should be written to this bit.

Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling

of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is

enabled for address output, the address is output regardless of the corresponding DDR setting.

When a pin is disabled for address output, it becomes an output port when the corresponding DDR

bit is set to 1.

149

Bit 3 Bit 2 Bit 1 Bit 0

AE3 AE2 AE1 AE0 Description

0000A8–A23 address output disabled (Initial value*)

1 A8 address output enabled; A9–A23 address output disabled

1 0 A8, A9 address output enabled; A10–A23 address output

disabled

1 A8–A10 address output enabled; A11–A23 address output

disabled

1 0 0 A8–A11 address output enabled; A12–A23 address output

disabled

1 A8–A12 address output enabled; A13–A23 address output

disabled

1 0 A8–A13 address output enabled; A14–A23 address output

disabled

1 A8–A14 address output enabled; A15–A23 address output

disabled

1000A8–A15 address output enabled; A16–A23 address output

disabled

1 A8–A16 address output enabled; A17–A23 address output

disabled

1 0 A8–A17 address output enabled; A18–A23 address output

disabled

1 A8–A18 address output enabled; A19–A23 address output

disabled

1 0 0 A8–A19 address output enabled; A20–A23 address output

disabled

1 A8–A20 address output enabled; A21–A23 address output

disabled (Initial value*)

1 0 A8–A21 address output enabled; A22, A23 address output

disabled

1 A8–A23 address output enabled

Note: *In expanded mode with ROM, bits AE3 to AE0 are initialized to B'0000.

In ROMless expanded mode, bits AE3 to AE0 are initialized to B'1101.

Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to

150

7.3 Overview of Bus Control

7.3.1 Area Partitioning

In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to

7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it

controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the

memory map.

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

Area 0

(2Mbytes)

H'000000

H'FFFFFF

(1) (2)

H'0000

H'1FFFFF

H'200000 Area 1

(2Mbytes)

H'3FFFFF

H'400000 Area 2

(2Mbytes)

H'5FFFFF

H'600000 Area 3

(2Mbytes)

H'7FFFFF

H'800000 Area 4

(2Mbytes)

H'9FFFFF

H'A00000 Area 5

(2Mbytes)

H'BFFFFF

H'C00000 Area 6

(2Mbytes)

H'DFFFFF

H'E00000 Area 7

(2Mbytes)

H'FFFF

Advanced mode Normal mode*

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

Figure 7-2 Overview of Area Partitioning

151

7.3.2 Bus Specifications

The external space bus specifications consist of three elements: bus width, number of access

states, and number of program wait states.

The bus width and number of access states for on-chip memory and internal I/O registers are

fixed, and are not affected by the bus controller.

(1) Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an

8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is

selected functions as a16-bit access space.

If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit

access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is

always set.

(2) Number of Access States: Two or three access states can be selected with ASTCR. An area

for which 2-state access is selected functions as a 2-state access space, and an area for which 3-

state access is selected functions as a 3-state access space.

With the burst ROM interface, the number of access states may be determined without regard to

ASTCR.

When 2-state access space is designated, wait insertion is disabled.

(3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the

number of program wait states to be inserted automatically is selected with WCRH and WCRL.

From 0 to 3 program wait states can be selected.

Table 7-3 shows the bus specifications for each basic bus interface area.

152

Table 7-3 Bus Specifications for Each Area (Basic Bus Interface)

ABWCR ASTCR WCRH, WCRL Bus Specifications (Basic Bus Interface)

ABWn ASTn Wn1 Wn0 Bus Width Access States Program Wait

States

00——16 2 0

100 3 0

10 2

10——8 2 0

100 3 0

10 2

7.3.3 Memory Interfaces

The H8S/2626 Series and H8S/2623 Series memory interfaces comprise a basic bus interface that

allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct

connection of burst ROM. The memory interface can be selected independently for each area.

An area for which the basic bus interface is designated functions as normal space, and an area for

which the burst ROM interface is designated functions as burst ROM space.

153

7.3.4 Interface Specifications for Each Area

The initial state of each area is basic bus interface, 3-state access space. The initial bus width is

selected according to the operating mode. The bus specifications described here cover basic items

only, and the sections on each memory interface (7.4 and 7.5) should be referred to for further

details.

Area 0: Area 0 includes on-chip ROM, and in ROM-disabled expansion mode, all of area 0 is

external space. In ROM-enabled expansion mode, the space excluding on-chip ROM is external

space.

Either basic bus interface or burst ROM interface can be selected for area 0.

Areas 1 to 6: In external expansion mode, all of areas 1 to 6 is external space.

Only the basic bus interface can be used for areas 1 to 6.

Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode,

the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip

RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the

RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes

external space.

Only the basic bus interface can be used for the area 7.

154

7.4 Basic Bus Interface

7.4.1 Overview

The basic bus interface enables direct connection of ROM, SRAM, and so on.

The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7-

3).

7.4.2 Data Size and Data Alignment

Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus

controller has a data alignment function, and when accessing external space, controls whether the

upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus

specifications for the area being accessed (8-bit access space or 16-bit access space) and the data

size.

8-Bit Access Space: Figure 7-3 illustrates data alignment control for the 8-bit access space. With

the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of

data that can be accessed at one time is one byte: a word transfer instruction is performed as two

byte accesses, and a longword transfer instruction, as four byte accesses.

D15 D8 D7 D0

Upper data bus

Lower data bus

Byte size

Word size 1st bus cycle

2nd bus cycle

Longword size 1st bus cycle

2nd bus cycle

3rd bus cycle

4th bus cycle

Figure 7-3 Access Sizes and Data Alignment Control (8-Bit Access Space)

155

16-Bit Access Space: Figure 7-4 illustrates data alignment control for the 16-bit access space.

With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are

used for accesses. The amount of data that can be accessed at one time is one byte or one word,

and a longword transfer instruction is executed as two word transfer instructions.

In byte access, whether the upper or lower data bus is used is determined by whether the address is

even or odd. The upper data bus is used for an even address, and the lower data bus for an odd

address.

D15 D8 D7 D0

Upper data bus

Byte size

Word size

1st bus cycle

2nd bus cycle

Longword

size

• Even address

Byte size • Odd address

Lower data bus

Figure 7-4 Access Sizes and Data Alignment Control (16-Bit Access Space)

156

7.4.3 Valid Strobes

Table 7-4 shows the data buses used and valid strobes for the access spaces.

In a read, the RD signal is valid without discrimination between the upper and lower halves of the

data bus.

In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the

lower half.

Table 7-4 Data Buses Used and Valid Strobes

Area Access

Size Read/

Write Address Valid

Strobe Upper Data Bus

(D15 to D8) Lower data bus

(D7 to D0)

8-bit access Byte Read — RD Valid Invalid

space Write — HWR Hi-Z

16-bit access Byte Read Even RD Valid Invalid

space Odd Invalid Valid

Write Even HWR Valid Hi-Z

Odd LWR Hi-Z Valid

Word Read — RD Valid Valid

Write — HWR, LWR Valid Valid

Note: Hi-Z: High impedance.

Invalid: Input state; input value is ignored.

157

7.4.4 Basic Timing

8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space.

When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.

The LWR pin is fixed high. Wait states cannot be inserted.

Bus cycle

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Figure 7-5 Bus Timing for 8-Bit 2-State Access Space

158

8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space.

When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.

The LWR pin is fixed high. Wait states can be inserted.

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Figure 7-6 Bus Timing for 8-Bit 3-State Access Space

159

16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access

space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used

for the even address, and the lower half (D7 to D0) for the odd address.

Wait states cannot be inserted.

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Figure 7-7 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access)

160

Bus cycle

T1T2

Address bus

D15 to D8 Invalid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 High impedance

D7 to D0 Valid

Write

High

Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)

161

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 Valid

Write

Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)

162

16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access

space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used

for the even address, and the lower half (D7 to D0) for the odd address.

Wait states can be inserted.

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Invalid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 High impedance

Write

High

Figure 7-10 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)

163

Bus cycle

T1T2

Address bus

D15 to D8 Invalid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 High impedance

D7 to D0 Valid

Write

High

Figure 7-11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)

164

Bus cycle

T1T2

Address bus

D15 to D8 Valid

D7 to D0 Valid

Read

HWR

LWR

D15 to D8 Valid

D7 to D0 Valid

Write

Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)

165

7.4.5 Wait Control

When accessing external space, the H8S/2626 Series or H8S/2623 Series can extend the bus cycle

by inserting one or more wait states (Tw). There are two ways of inserting wait states: program

wait insertion and pin wait insertion using the WAIT pin.

Program Wait Insertion

From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an

individual area basis in 3-state access space, according to the settings of WCRH and WCRL.

Pin Wait Insertion

Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program

wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the

WAIT pin is low at the falling edge of ø in the last T2 or Tw state, a Tw state is inserted. If the

WAIT pin is held low, Tw states are inserted until it goes high.

This is useful when inserting four or more Tw states, or when changing the number of Tw states for

different external devices.

The WAITE bit setting applies to all areas.

166

Figure 7-13 shows an example of wait state insertion timing.

By program wait

Address bus

Data bus Read data

Read

HWR, LWR

Write data

Write

Note: indicates the timing of WAIT pin sampling.

WAIT

Data bus

T2TwTwTwT3

By WAIT pin

Figure 7-13 Example of Wait State Insertion Timing

The settings after a reset are: 3-state access, 3 program wait state insertion, and WAIT input

disabled.

167

7.5 Burst ROM Interface

7.5.1 Overview

With the H8S/2626 Series and H8S/2623 Series, external space area 0 can be designated as burst

ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables

16-bit configuration ROM with burst access capability to be accessed at high speed.

Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.

Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU

instruction fetches only. One or two states can be selected for burst access.

7.5.2 Basic Timing

The number of states in the initial cycle (full access) of the burst ROM interface is in accordance

with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state

insertion is possible. One or two states can be selected for the burst cycle, according to the setting

of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst

ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR.

When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when

the BRSTS0 bit is set to 1, burst access of up to 8 words is performed.

The basic access timing for burst ROM space is shown in figures 7-14 (a) and (b). The timing

shown in figure 7-14 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and

that in figure 7-14 (b) is for the case where both these bits are cleared to 0.

168

Address bus

Data bus

T2T3T1T2T1

Full access

Burst access

Only lower address changed

Read data Read data Read data

Figure 7-14 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)

169

Address bus

Data bus

T2T1T1

Full access

Burst access

Only lower address changed

Read data Read data Read data

Figure 7-14 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)

7.5.3 Wait Control

As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT

pin can be used in the initial cycle (full access) of the burst ROM interface. See section 7.4.5, Wait

Control.

Wait states cannot be inserted in a burst cycle.

170

7.6 Idle Cycle

7.6.1 Operation

When the H8S/2626 Series or H8S/2623 Series accesses external space , it can insert a 1-state idle

cycle (TI) between bus cycles in the following two cases: (1) when read accesses between different

areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By

inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a

long output floating time, and high-speed memory, I/O interfaces, and so on.

(1) Consecutive Reads between Different Areas

If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle

cycle is inserted at the start of the second read cycle.

Figure 7-15 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,

each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in

cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,

and a data collision is prevented.

Address bus

Bus cycle A

Data bus

T2T3T1T2

Bus cycle B Bus cycle A Bus cycle B

Long output

floating time

Data

collision

(a) Idle cycle not inserted

(ICIS1 = 0) (b) Idle cycle inserted

(Initial value ICIS1 = 1)

Address bus

Data bus

T2T3TIT1T2

CS* (area A)

CS* (area B)

CS* (area A)

CS* (area B)

Note: * The CS signals are generated off-chip.

Figure 7-15 Example of Idle Cycle Operation (1)

171

(2) Write after Read

If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle

cycle is inserted at the start of the write cycle.

Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read

cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an

idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and

the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.

Address bus

Bus cycle A

T2T3T1T2

Bus cycle B

Address bus

Bus cycle A

T2T3TIT1

Bus cycle B

CS* (area A)

CS* (area B)

CS* (area A)

CS* (area B)

(a) Idle cycle not inserted

(ICIS1 = 0) (b) Idle cycle inserted

(Initial value ICIS1 = 1)

Note: * The CS signals are generated off-chip.

Possibility of overlap between

CS (area B) and RD

Figure 7-16 Example of Idle Cycle Operation (2)

172

7.6.2 Pin States in Idle Cycle

Table 7-5 shows pin states in an idle cycle.

Table 7-5 Pin States in Idle Cycle

Pins Pin State

A23 to A0 Contents of next bus cycle

D15 to D0 High impedance

AS High

RD High

HWR High

LWR High

173

7.7 Write Data Buffer Function

The H8S/2626 Series and H8S/2623 Series have a write data buffer function in the external data

bus. Using the write data buffer function enables external writes to be executed in parallel with

internal accesses. The write data buffer function is made available by setting the WDBE bit in

BCRL to 1.

Figure 7-17 shows an example of the timing when the write data buffer function is used. When

this function is used, if an external write continues for 2 states or longer, and there is an internal

access next, only an external write is executed in the first state, but from the next state onward an

internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the

external write rather than waiting until it ends.

Internal address bus

A23 to A0

External write cycle

HWR, LWR

T2TWTWT3

On-chip memory read Internal I/O register read

Internal read signal

D15 to D0

External address

Internal memory

External

space

write

Internal I/O register address

Figure 7-17 Example of Timing when Write Data Buffer Function is Used

174

7.8 Bus Release

7.8.1 Overview

The H8S/2626 Series and H8S/2623 Series can release the external bus in response to a bus

request from an external device. In the external bus released state, the internal bus master

continues to operate as long as there is no external access.

If an internal bus master wants to make an external access in the external bus released state, it can

issue a bus request off-chip.

7.8.2 Operation

In external expansion mode, the bus can be released to an external device by setting the BRLE bit

in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2626 Series or

H8S/2623 Series. When the BREQ pin is sampled, at the prescribed timing the BACK pin is

driven low, and the address bus, data bus, and bus control signals are placed in the high-

impedance state, establishing the external bus-released state.

In the external bus released state, an internal bus master can perform accesses using the internal

bus. When an internal bus master wants to make an external access, it temporarily defers

activation of the bus cycle, and waits for the bus request from the external bus master to be

dropped.

If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external

access in the external bus released state, the BREQO pin is driven low and a request can be made

off-chip to drop the bus request.

When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the

external bus released state is terminated.

If an external bus release request and internal bus master external access occur simultaneously, the

order of priority is as follows:

(High) External bus release > Internal bus master external access (Low)

175

7.8.3 Pin States in External Bus Released State

Table 7-6 shows pin states in the external bus released state.

Table 7-6 Pin States in Bus Released State

Pins Pin State

A23 to A0 High impedance

D15 to D0 High impedance

AS High impedance

RD High impedance

HWR High impedance

LWR High impedance

176

7.8.4 Transition Timing

Figure 7-18 shows the timing for transition to the bus-released state.

CPU

cycle

External bus released stateCPU cycle

Address

T0T1T2

Address bus

Data bus

HWR, LWR

BREQ

BACK

High impedance

Minimum

1 state

BREQO*

[1] [2] [3] [4] [5] [6]

[1]

[2]

[3]

[4]

[5]

[6]

Note: * Output only when BREQOE is set to 1.

Low level of BREQ pin is sampled at rise of T2 state.

BACK pin is driven low at end of CPU read cycle, releasing bus to external

bus master.

BREQ pin state is still sampled in external bus released state.

High level of BREQ pin is sampled.

BACK pin is driven high, ending bus release cycle.

BREQO signal goes high 1.5 clocks after BACK signal goes high.

High impedance

RD High impedance

Figure 7-18 Bus-Released State Transition Timing

177

7.8.5 Usage Note

If MSTPCR is set to H'FFFFFF or H'EFFFFF and a transition is made to sleep mode, the external

bus release function will halt. Therefore, these values should not be set in MSTPCR if the external

bus release function is to be used in sleep mode.

7.9 Bus Arbitration

7.9.1 Overview

The H8S/2626 Series and H8S/2623 Series have a bus arbiter that arbitrates bus master operations.

There are two bus masters, the CPU and DTC, which perform read/write operations when they

have possession of the bus. Each bus master requests the bus by means of a bus request signal. The

bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a

bus request acknowledge signal. The selected bus master then takes possession of the bus and

begins its operation.

7.9.2 Operation

The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master making the request. If there are bus requests from

more than one bus master, the bus request acknowledge signal is sent to the one with the highest

priority. When a bus master receives the bus request acknowledge signal, it takes possession of the

bus until that signal is canceled.

The order of priority of the bus masters is as follows:

(High) DTC > CPU (Low)

An internal bus access by an internal bus master, and external bus release, can be executed in

parallel.

In the event of simultaneous external bus release request, and internal bus master external access

request generation, the order of priority is as follows:

(High) External bus release > Internal bus master external access (Low)

178

7.9.3 Bus Transfer Timing

Even if a bus request is received from a bus master with a higher priority than that of the bus

master that has acquired the bus and is currently operating, the bus is not necessarily transferred

immediately. There are specific times at which each bus master can relinquish the bus.

CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,

the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of

the bus is as follows:

• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in

discrete operations, as in the case of a longword-size access, the bus is not transferred between

the operations. See Appendix A-5, Bus States During Instruction Execution, for timings at

which the bus is not transferred.

• If the CPU is in sleep mode, it transfers the bus immediately.

DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.

The DTC can release the bus after a vector read, a register information read (3 states), a single data

transfer, or a register information write (3 states). It does not release the bus during a register

information read (3 states), a single data transfer, or a register information write (3 states).

7.10 Resets and the Bus Controller

In a reset, the H8S/2626 Series or H8S/2623 Series, including the bus controller, enters the reset

state at that point, and an executing bus cycle is discontinued.

179

Section 8 Data Transfer Controller (DTC)

8.1 Overview

The H8S/2626 Series and H8S/2623 Series include a data transfer controller (DTC). The DTC can

be activated by an interrupt or software, to transfer data.

8.1.1 Features

The features of the DTC are:

• Transfer possible over any number of channels

 Transfer information is stored in memory

 One activation source can trigger a number of data transfers (chain transfer)

• Wide range of transfer modes

 Normal, repeat, and block transfer modes available

 Incrementing, decrementing, and fixing of source and destination addresses can be selected

• Direct specification of 16-Mbyte address space possible

 24-bit transfer source and destination addresses can be specified

• Transfer can be set in byte or word units

• A CPU interrupt can be requested for the interrupt that activated the DTC

 An interrupt request can be issued to the CPU after one data transfer ends

 An interrupt request can be issued to the CPU after the specified data transfers have

completely ended

• Activation by software is possible

• Module stop mode can be set

 The initial setting enables DTC registers to be accessed. DTC operation is halted by setting

module stop mode.

180

8.1.2 Block Diagram

Figure 8-1 shows a block diagram of the DTC.

The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to

the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register

information.

Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.

Interrupt

request

Interrupt controller DTC

Internal address bus

DTC service

request

Control logic

MRA MRB

CRA

CRB

DAR

SAR

CPU interrupt

request

On-chip

RAM

Internal data bus

Legend

MRA, MRB

CRA, CRB

SAR

DAR

DTCERA to DTCERG

DTVECR

DTCERA

DTCERG

DTVECR

: DTC mode registers A and B

: DTC transfer count registers A and B

: DTC source address register

: DTC destination address register

: DTC enable registers A to G

: DTC vector register

Figure 8-1 Block Diagram of DTC

181

8.1.3 Register Configuration

Table 8-1 summarizes the DTC registers.

Table 8-1 DTC Registers

Name Abbreviation R/W Initial Value Address*1

DTC mode register A MRA —*2Undefined —*3

DTC mode register B MRB —*2Undefined —*3

DTC source address register SAR —*2Undefined —*3

DTC destination address register DAR —*2Undefined —*3

DTC transfer count register A CRA —*2Undefined —*3

DTC transfer count register B CRB —*2Undefined —*3

DTC enable registers DTCER R/W H'00 H'FE16 to H'FE1C

DTC vector register DTVECR R/W H'00 H'FE1F

Module stop control register MSTPCRA R/W H'3F H'FDE8

Notes: 1. Lower 16 bits of the address.

2. Registers within the DTC cannot be read or written to directly.

3. Register information is located in on-chip RAM addresses H'EBC0 to H'EFBF. It cannot

be located in external memory space. When the DTC is used, the RAME bit in SYSCR

must be set to 1.

182

8.2 Register Descriptions

8.2.1 DTC Mode Register A (MRA)

SM1 6

SM0 5

DM1 4

DM0 3

MD1 0

MD0 1

DTS

Bit

Initial value

—

Unde-

fined

R/W : —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined

MRA is an 8-bit register that controls the DTC operating mode.

Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is

to be incremented, decremented, or left fixed after a data transfer.

Bit 7 Bit 6

SM1 SM0 Description

0 — SAR is fixed

1 0 SAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

1 SAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether

DAR is to be incremented, decremented, or left fixed after a data transfer.

Bit 5 Bit 4

DM1 DM0 Description

0 — DAR is fixed

1 0 DAR is incremented after a transfer

(by +1 when Sz = 0; by +2 when Sz = 1)

1 DAR is decremented after a transfer

(by –1 when Sz = 0; by –2 when Sz = 1)

183

Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.

Bit 3 Bit 2

MD1 MD0 Description

0 0 Normal mode

1 Repeat mode

1 0 Block transfer mode

1—

Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination

side is set to be a repeat area or block area, in repeat mode or block transfer mode.

Bit 1

DTS Description

0 Destination side is repeat area or block area

1 Source side is repeat area or block area

Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.

Bit 0

Sz Description

0 Byte-size transfer

1 Word-size transfer

184

8.2.2 DTC Mode Register B (MRB)

CHNE 6

DISEL 5

—4

—3

—0

—

—1

—

Bit

Initial value

R/W : —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined —

Unde-

fined

MRB is an 8-bit register that controls the DTC operating mode.

Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a

number of data transfers can be performed consecutively in response to a single transfer request.

In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,

clearing of the interrupt source flag, and clearing of DTCER is not performed.

Bit 7

CHNE Description

0 End of DTC data transfer (activation waiting state is entered)

1 DTC chain transfer (new register information is read, then data is transferred)

Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are

disabled or enabled after a data transfer.

Bit 6

DISEL Description

0 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is

0 (the DTC clears the interrupt source flag of the activating interrupt to 0)

1 After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the

interrupt source flag of the activating interrupt to 0)

Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2626 Series and

H8S/2623 Series, and should always be written with 0.

185

8.2.3 DTC Source Address Register (SAR)

23 22 21 20 19 43210

Bit

Initial value

—

Unde-

fined

R/W : —

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.

For word-size transfer, specify an even source address.

8.2.4 DTC Destination Address Register (DAR)

23 22 21 20 19 43210

Bit

Initial value

—

Unde-

fined

R/W : —

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

DAR is a 24-bit register that designates the destination address of data to be transferred by the

DTC. For word-size transfer, specify an even destination address.

8.2.5 DTC Transfer Count Register A (CRA)

15 14 13 12 11109876543210

CRAH CRAL

Bit

Initial value

—

Unde-

fined

R/W : —

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits

(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL

functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is

transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is

repeated.

186

8.2.6 DTC Transfer Count Register B (CRB)

15 14 13 12 11109876543210

Bit

Initial value

————————————————

Unde-

fined Unde-

fined

Unde-

fined Unde-

fined

Unde-

fined Unde-

fined

Unde-

fined Unde-

fined

Unde-

fined Unde-

fined

R/W :

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000.

8.2.7 DTC Enable Registers (DTCER)

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE0

R/W

DTCE2

R/W

DTCE1

R/W

Bit

Initial value

R/W

The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to

DTCERG, with bits corresponding to the interrupt sources that can control enabling and disabling

of DTC activation. These bits enable or disable DTC service for the corresponding interrupt

sources.

The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.

Bit n—DTC Activation Enable (DTCEn)

Bit n

DTCEn Description

0 DTC activation by this interrupt is disabled (Initial value)

[Clearing conditions]

• When the DISEL bit is 1 and the data transfer has ended

• When the specified number of transfers have ended

1 DTC activation by this interrupt is enabled

[Holding condition]

When the DISEL bit is 0 and the specified number of transfers have not ended

(n = 7 to 0)

A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence

between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number

generated for each interrupt controller.

187

For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and

writing. If all interrupts are masked, multiple activation sources can be set at one time by writing

data after executing a dummy read on the relevant register.

8.2.8 DTC Vector Register (DTVECR)

SWDTE

R/(W)*1

DTVEC6

R/(W)*2

DTVEC5

R/(W)*2

DTVEC4

R/(W)*2

DTVEC3

R/(W)*2

DTVEC0

R/(W)*2

DTVEC2

R/(W)*2

DTVEC1

R/(W)*2

Notes: 1. Only 1 can be written to the SWDTE bit.

2. Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.

Bit

Initial value

R/W

DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by

software, and sets a vector number for the software activation interrupt.

DTVECR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by

software.

Bit 7

SWDTE Description

0 DTC software activation is disabled (Initial value)

[Clearing conditions]

• When the DISEL bit is 0 and the specified number of transfers have not ended

• When 0 s written to the DISEL bit after a software-activated data transfer end

interrupt (SWDTEND) request has been sent to the CPU

1 DTC software activation is enabled

[Holding conditions]

• When the DISEL bit is 1 and data transfer has ended

• When the specified number of transfers have ended

• During data transfer due to software activation

Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits

specify a vector number for DTC software activation.

The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit left-

shift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.

188

8.2.9 Module Stop Control Register A (MSTPCRA)

MSTPA7

R/W

Bit

Initial value

R/W

MSTPA6

R/W

MSTPA5

R/W

MSTPA4

R/W

MSTPA3

R/W

MSTPA2

R/W

MSTPA1

R/W

MSTPA0

R/W

MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPA6 bit in MSTPCRA is set to 1, the DTC operation stops at the end of the bus

cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTPA6

bit while the DTC is operating. For details, see section 20.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode.

Bit 6

MSTPA6 Description

0 DTC module stop mode cleared (Initial value)

1 DTC module stop mode set

189

8.3 Operation

8.3.1 Overview

When activated, the DTC reads register information that is already stored in memory and transfers

data on the basis of that register information. After the data transfer, it writes updated register

information back to memory. Pre-storage of register information in memory makes it possible to

transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to

perform a number of transfers with a single activation.

Figure 8-2 shows a flowchart of DTC operation.

Start

Read DTC vector Next transfer

Read register information

Data transfer

Write register information

Clear an activation flag

CHNE=1

End

Yes

Transfer Counter= 0

or DISEL= 1

Clear DTCER

Interrupt exception

handling

Figure 8-2 Flowchart of DTC Operation

190

The DTC transfer mode can be normal mode, repeat mode, or block transfer mode.

The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the

transfer destination address. After each transfer, SAR and DAR are independently incremented,

decremented, or left fixed.

Table 8-2 outlines the functions of the DTC.

Table 8-2 DTC Functions

Address Registers

Transfer Mode Activation Source Transfer

Source Transfer

Destination

• Normal mode

 One transfer request transfers one

byte or one word

 Memory addresses are incremented

or decremented by 1 or 2

 Up to 65,536 transfers possible

• Repeat mode

 One transfer request transfers one

byte or one word

 Memory addresses are incremented

or decremented by 1 or 2

 After the specified number of

transfers (1 to 256), the initial state

resumes and operation continues

• Block transfer mode

 One transfer request transfers a block

of the specified size

 Block size is from 1 to 256 bytes or

words

 Up to 65,536 transfers possible

 A block area can be designated at

either the source or destination

• IRQ

• TPU TGI

• SCI TXI or RXI

• A/D converter ADI

• Software

• HCAN RM0

24 bits 24 bits

191

8.3.2 Activation Sources

The DTC operates when activated by an interrupt or by a write to DTVECR by software. An

interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER

bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a

CPU interrupt source when the bit is cleared to 0.

At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the

activation source or corresponding DTCER bit is cleared. Table 8-3 shows activation source and

DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag

of SCI0.

Table 8-3 Activation Source and DTCER Clearance

Activation Source

When the DISEL Bit Is 0 and

the Specified Number of

Transfers Have Not Ended

When the DISEL Bit Is 1, or when

the Specified Number of Transfers

Have Ended

Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1

An interrupt is issued to the CPU

Interrupt activation The corresponding DTCER bit

remains set to 1

The activation source flag is

cleared to 0

The corresponding DTCER bit is cleared

to 0

The activation source flag remains set to 1

A request is issued to the CPU for the

activation source interrupt

Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt

Controller.

On-chip

supporting

module

IRQ interrupt

DTVECR

Selection circuit

Interrupt controller CPU

DTC

DTCER

Clear

controller

Select

Interrupt

request

Source flag cleared

Clear

Clear request

Interrupt mask

Figure 8-3 Block Diagram of DTC Activation Source Control

192

When an interrupt has been designated a DTC activation source, existing CPU mask level and

interrupt controller priorities have no effect. If there is more than one activation source at the same

time, the DTC operates in accordance with the default priorities.

8.3.3 DTC Vector Table

Figure 8-4 shows the correspondence between DTC vector addresses and register information.

Table 8-4 shows the correspondence between activation and vector addresses. When the DTC is

activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where

<< 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.

The DTC reads the start address of the register information from the vector address set for each

activation source, and then reads the register information from that start address. The register

information can be placed at predetermined addresses in the on-chip RAM. The start address of

the register information should be an integral multiple of four.

The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte

unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip

RAM.

Note: * Not available in the H8S/2626 Series or H8S/2623 Series.

start address Register information

Chain transfer

DTC vector

address

Figure 8-4 Correspondence between DTC Vector Address and Register Information

193

Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs

Interrupt Source

Origin of

Interrupt

Source Vector

Number Vector

Address DTCE*Priority

Write to DTVECR Software DTVECR H'0400+

(DTVECR

[6:0]

<<1)

— High

IRQ0 External pin 16 H'0420 DTCEA7

IRQ1 17 H'0422 DTCEA6

IRQ2 18 H'0424 DTCEA5

IRQ3 19 H'0426 DTCEA4

IRQ4 20 H'0428 DTCEA3

IRQ5 21 H'042A DTCEA2

Reserved 22 H'042C DTCEA1

23 H'042E DTCEA0

ADI (A/D conversion end) A/D 28 H'0438 DTCEB6

TGI0A (GR0A compare match/

input capture) TPU

channel 0 32 H'0440 DTCEB5

TGI0B (GR0B compare match/

input capture) 33 H'0442 DTCEB4

TGI0C (GR0C compare match/

input capture) 34 H'0444 DTCEB3

TGI0D (GR0D compare match/

input capture) 35 H'0446 DTCEB2

TGI1A (GR1A compare match/

input capture) TPU

channel 1 40 H'0450 DTCEB1

TGI1B (GR1B compare match/

input capture) 41 H'0452 DTCEB0

TGI2A (GR2A compare match/

input capture) TPU

channel 2 44 H'0458 DTCEC7

TGI2B (GR2B compare match/

input capture) 45 H'045A DTCEC6 Low

194

Interrupt Source

Origin of

Interrupt

Source Vector

Number Vector

Address DTCE Priority

TGI3A (GR3A compare match/

input capture) TPU

channel 3 48 H'0460 DTCEC5 High

TGI3B (GR3B compare match/

input capture) 49 H'0462 DTCEC4

TGI3C (GR3C compare match/

input capture) 50 H'0464 DTCEC3

TGI3D (GR3D compare match/

input capture) 51 H'0466 DTCEC2

TGI4A (GR4A compare match/

input capture) TPU

channel 4 56 H'0470 DTCEC1

TGI4B (GR4B compare match/

input capture) 57 H'0472 DTCEC0

TGI5A (GR5A compare match/

input capture) TPU

channel 5 60 H'0478 DTCED5

TGI5B (GR5B compare match/

input capture) 61 H'047A DTCED4

Reserved — 64 H'0480 DTCED3

65 H'0482 DTCED2

68 H'0488 DTCED1

69 H'048A DTCED0

72 H'0120 DTCEE7

73 H'0124 DTCEE6

74 H'0128 DTCEE5

75 H'012C DTCEE4

RXI0 (reception complete 0) SCI 81 H'04A2 DTCEE3

TXI0 (transmit data empty 0) channel 0 82 H'04A4 DTCEE2

RXI1 (reception complete 1) SCI 85 H'04AA DTCEE1

TXI1 (transmit data empty 1) channel 1 86 H'04AC DTCEE0

RXI2 (reception complete 2) SCI 89 H'04B2 DTCEF7

TXI2 (transmit data empty 2) channel 2 90 H'04B4 DTCEF6

RM0 HCAN 106 H'04D4 DTCEG5 Low

Note: *DTCE bits with no corresponding interrupt are reserved, and should be written with 0.

195

8.3.4 Location of Register Information in Address Space

Figure 8-5 shows how the register information should be located in the address space.

Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address

of the register information (contents of the vector address). In the case of chain transfer, register

information should be located in consecutive areas.

Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).

information

start address

Chain

transfer Register information

for 2nd transfer in

chain transfer

MRA SAR

MRB DAR

CRA CRB

4 bytes

Lower address

CRA CRB

MRA

0 123

SAR

MRB DAR

Figure 8-5 Location of Register Information in Address Space

196

8.3.5 Normal Mode

In normal mode, one operation transfers one byte or one word of data.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a

CPU interrupt can be requested.

Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in

normal mode.

Table 8-5 Register Information in Normal Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count register A CRA Designates transfer count

DTC transfer count register B CRB Not used

Transfer

SAR DAR

Figure 8-6 Memory Mapping in Normal Mode

197

8.3.6 Repeat Mode

In repeat mode, one operation transfers one byte or one word of data.

From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the

initial state of the transfer counter and the address register specified as the repeat area is restored,

and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and

therefore CPU interrupts cannot be requested when DISEL = 0.

Table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in

repeat mode.

Table 8-6 Register Information in Repeat Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count register AH CRAH Holds number of transfers

DTC transfer count register AL CRAL Designates transfer count

DTC transfer count register B CRB Not used

Transfer

SAR or

DAR DAR or

SAR

Repeat area

Figure 8-7 Memory Mapping in Repeat Mode

198

8.3.7 Block Transfer Mode

In block transfer mode, one operation transfers one block of data. Either the transfer source or the

transfer destination is designated as a block area.

The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size

counter and the address register specified as the block area is restored. The other address register

is then incremented, decremented, or left fixed.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a

CPU interrupt is requested.

Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory

mapping in block transfer mode.

Table 8-7 Register Information in Block Transfer Mode

Name Abbreviation Function

DTC source address register SAR Designates source address

DTC destination address register DAR Designates destination address

DTC transfer count register AH CRAH Holds block size

DTC transfer count register AL CRAL Designates block size count

DTC transfer count register B CRB Transfer count

199

Transfer

SAR or

DAR DAR or

SAR

Block area

First block

Nth block

Figure 8-8 Memory Mapping in Block Transfer Mode

200

8.3.8 Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in

response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data

transfers, can be set independently.

Figure 8-9 shows the memory map for chain transfer.

Source

Destination

DTC vector

address Register information

start address

CHNE = 1

CHNE = 0

Figure 8-9 Chain Transfer Memory Map

In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the

end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt

source flag for the activation source is not affected.

201

8.3.9 Operation Timing

Figures 8-10 to 8-12 show an example of DTC operation timing.

DTC activation

request

DTC

request

Address

Vector read

Transfer

information read Transfer

information write

Data transfer

Read Write

Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)

Read Write Read Write

Data transfer

Transfer

information write

Transfer

information read

Vector read

DTC activation

request

DTC request

Address

Figure 8-11 DTC Operation Timing (Example of Block Transfer Mode,

with Block Size of 2)

202

Read Write Read Write

Address

DTC activation

request

DTC

request Data transfer Data transfer

Transfer

information

write

Transfer

information

write

Transfer

information

read

Transfer

information

read

Vector read

Figure 8-12 DTC Operation Timing (Example of Chain Transfer)

8.3.10 Number of DTC Execution States

Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number

of states required for each execution status.

Table 8-8 DTC Execution Statuses

Mode Vector Read

Read/Write

JData Read

KData Write

Internal

Operations

Normal 1 6 1 1 3

Repeat 1 6 1 1 3

Block transfer 1 6 N N 3

N: Block size (initial setting of CRAH and CRAL)

203

Table 8-9 Number of States Required for Each Execution Status

Object to be Accessed

On-

Chip

RAM

On-

Chip

ROM On-Chip I/O

Registers External Devices

Bus width 32 16 8 16 8 16

Access states 11222323

Execution Vector read SI— 1 — — 4 6+2m 2 3+m

status Register

information

read/write

SJ1 ———————

Byte data read SK112223+m23+m

Word data read SK114246+2m 2 3+m

Byte data write SL112223+m23+m

Word data write SL114246+2m 2 3+m

Internal operation SM1

The number of execution states is calculated from the formula below. Note that Σ means the sum

of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,

plus 1).

Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM

For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,

and data is transferred from the on-chip ROM to an internal I/O register, the time required for the

DTC operation is 13 states. The time from activation to the end of the data write is 10 states.

204

8.3.11 Procedures for Using DTC

Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows:

[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.

[2] Set the start address of the register information in the DTC vector address.

[3] Set the corresponding bit in DTCER to 1.

[4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC

is activated when an interrupt used as an activation source is generated.

[5] After the end of one data transfer, or after the specified number of data transfers have ended,

the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue

transferring data, set the DTCE bit to 1.

Activation by Software: The procedure for using the DTC with software activation is as follows:

[1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.

[2] Set the start address of the register information in the DTC vector address.

[3] Check that the SWDTE bit is 0.

[4] Write 1 to SWDTE bit and the vector number to DTVECR.

[5] Check the vector number written to DTVECR.

[6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,

the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit

to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the

SWDTE bit is held at 1 and a CPU interrupt is requested.

205

8.3.12 Examples of Use of the DTC

(1) Normal Mode

An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.

[1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =

1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have

any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the

SCI RDR address in SAR, the start address of the RAM area where the data will be received in

DAR, and 128 (H'0080) in CRA. CRB can be set to any value.

[2] Set the start address of the register information at the DTC vector address.

[3] Set the corresponding bit in DTCER to 1.

[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception

complete (RXI) interrupt. Since the generation of a receive error during the SCI reception

operation will disable subsequent reception, the CPU should be enabled to accept receive error

interrupts.

[5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an

RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR

to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is

automatically cleared to 0.

[6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the

DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt

handling routine should perform wrap-up processing.

206

(2) Chain Transfer

An example of DTC chain transfer is shown in which pulse output is performed using the PPG.

Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle

updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain

transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing

of the activation source and interrupt generation at the end of the specified number of transfers are

restricted to the second half of the chain transfer (transfer when CHNE = 0).

[1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,

MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to

chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH

address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.

[2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing

(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 =

MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address

in DAR, and the data table size in CRA. CRB can be set to any value.

[3] Locate the TPU transfer register information consecutively after the NDR transfer register

information.

[4] Set the start address of the NDR transfer register information to the DTC vector address.

[5] Set the bit corresponding to TGIA in DTCER to 1.

[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA

interrupt with TIER.

[7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and

NDER for which output is to be performed to 1. Using PCR, select the TPU compare match

to be used as the output trigger.

[8] Set the CST bit in TSTR to 1, and start the TCNT count operation.

[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and

the set value of the next output trigger period is transferred to TGRA. The activation source

TGFA flag is cleared.

[10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the

TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to

the CPU. Termination processing should be performed in the interrupt handling routine.

207

(3) Software Activation

An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means

of software activation. The transfer source address is H'1000 and the destination address is

H'2000. The vector number is H'60, so the vector address is H'04C0.

[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination

address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =

0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =

0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,

and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.

[2] Set the start address of the register information at the DTC vector address (H'04C0).

[3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated

by software.

[4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.

[5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this

indicates that the write failed. This is presumably because an interrupt occurred between steps

3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.

[6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.

[7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear

the SWDTE bit to 0 and perform other wrap-up processing.

208

8.4 Interrupts

An interrupt request is issued to the CPU when the DTC finishes the specified number of data

transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,

the interrupt set as the activation source is generated. These interrupts to the CPU are subject to

CPU mask level and interrupt controller priority level control.

In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)

is generated.

When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers

have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is

generated. The interrupt handling routine should clear the SWDTE bit to 0.

When the DTC is activated by software, an SWDTEND interrupt is not generated during a data

transfer wait or during data transfer even if the SWDTE bit is set to 1.

8.5 Usage Notes

Module Stop: When the MSTPA6 bit in MSTPCRA is set to 1, the DTC clock stops, and the

DTC enters the module stop state. However, 1 cannot be written in the MSTPA6 bit while the

DTC is operating.

On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip

RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.

DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and

BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing

data after executing a dummy read on the relevant register.

209

Section 9 I/O Ports

9.1 Overview

The H8S/2626 Series and H8S/2623 Series have seven I/O ports (ports 1 and A to F), and two

input-only ports (ports 4 and 9).

Table 9-1 summarizes the port functions. The pins of each port also have other functions.

Each I/O port includes a data direction register (DDR) that controls input/output, a data register

(DR) that stores output data, and a port register (PORT) used to read the pin states. The input-only

ports do not have a DR or DDR register.

Ports A to E have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS

input pull-up control register (PCR) to control the on/off state of MOS input pull-up.

Ports A to C include an open-drain control register (ODR) that controls the on/off state of the

output buffer PMOS.

Ports 10 to 13, A0 to A3, and B to E can drive a single TTL load and 50 pF capacitive load when

used as expansion bus control signal output pins. In other cases these ports, together with ports 14

to 17 and 3, can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a

Darlington transistor when in output mode. Ports 1, A, B, and C can drive an LED (10 mA sink

current).

See appendix C, I/O Port Block Diagrams, for a block diagram of each port.

210

Table 9-1 Port Functions

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port 1 • 8-bit I/O

port

• Schmitt-

triggered

input (P16

and P14)

P17/PO15/TIOCB2/TCLKD

P16/PO14/TIOCA2/IRQ1

P15/PO13/TIOCB1/TCLKC

P14/PO12/TIOCA1/IRQ0

P13/PO11/TIOCD0/

TCLKB/A23

P12/PO10/TIOCC0/

TCLKA/A22

P11/PO9/TIOCB0/A21

P10/PO8/TIOCA0/A20

8-bit I/O port also functioning as TPU I/O

pins (TCLKA, TCLKB, TCLKC, TCLKD,

TIOCA0, TIOCB0, TIOCC0, TIOCD0,

TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG

output pins (PO15 to PO8), interrupt input

pins (IRQ0, IRQ1), and address outputs

(A20 to A23)

8-bit I/O port

also function-

ing as TPU

I/O pins

(TCLKA,

TCLKB,

TCLKC,

TCLKD,

TIOCA0,

TIOCB0,

TIOCC0,

TIOCD0,

TIOCA1,

TIOCB1,

TIOCA2,

TIOCB2),

PPG output

pins (PO15 to

PO8), and

interrupt input

pins (IRQ0,

IRQ1)

Port 4 • 8-bit input

port P47/AN7

P46/AN6

P45/AN5

P44/AN4

P43/AN3

P42/AN2

P41/AN1

P40/AN0

8-bit input port also functioning as A/D converter analog

inputs (AN7 to AN0)

Port 9 • 8-bit input

port P97/AN15/DA3*1

P96/AN14/DA2*1

P95/AN13

P94/AN12

P93/AN11

P92/AN10

P91/AN9

P90/AN8

8-bit input port also functioning as A/D converter analog

inputs (AN15 to AN8) and D/A converter analog outputs

(DA3, DA2)

211

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port A

*2• 6-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PA5

PA4

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

6-bit I/O port also functioning as SCI

(channel 2) I/O pins (TxD2, RxD2, SCK2),

and address outputs (A19 to A16)

6-bit I/O port

also function-

ing as SCI

(channel 2)

I/O pins

(TxD2, RxD2,

SCK2)

Port B • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PB1/A9/TIOCB3

PB0/A8/TIOCA3

8-bit I/O port also functioning as TPU I/O

pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4,

TIOCD3, TIOCC3, TIOCB3, TIOCA3) and

address outputs (A15 to A8)

8-bit I/O port

also function-

ing as TPU

I/O pins

(TIOCB5,

TIOCA5,

TIOCB4,

TIOCA4,

TIOCD3,

TIOCC3,

TIOCB3,

TIOCA3)

Port C • 8-bit I/O

port

• Built-in

MOS input

pull-up

• Open-drain

output

capability

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

Address output (A7 to A0) 8-bit I/O port

also function-

ing as SCI

(channel 0, 1)

I/O pins

(TxD0, RxD0,

SCK0, TxD1,

RxD1, SCK1),

interrupt input

pins (IRQ4,

IRQ5), and

address

outputs (A7 to

A0)

8-bit I/O port

also function-

ing as SCI

(channel 0, 1)

I/O pins

(TxD0, RxD0,

SCK0, TxD1,

RxD1, SCK1)

and interrupt

input pins

(IRQ4, IRQ5)

Port D • 8-bit I/O

port

• Built-in

MOS input

pull-up

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Data bus input/output I/O port

212

Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7

Port E • 8-bit I/O

port

• Built-in

MOS input

pull-up

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

In 8-bit bus mode: I/O port

In 16-bit bus mode: data bus input/output I/O port

Port F • 8-bit I/O

port PF7/ø When DDR = 0: input port

When DDR = 1 (after reset): ø output When DDR =

0 (after reset):

input port

When DDR =

1: ø output

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR/ADTRG/IRQ3

AS, RD, HWR, LWR output

ADTRG, IRQ3 input I/O port

ADTRG,

IRQ3 input

PF2/WAIT/BREQO When WAITE = 0 and BREQOE = 0 (after

reset): I/O port

When WAITE = 1 and BREQOE = 0:

WAIT input

When WAITE = 0 and BREQOE = 1:

BREQO input

I/O port

PF1/BACK/BUZZ*3

PF0/BREQ/IRQ2

When BRLE = 0 (after reset): I/O port

When BRLE = 1: BREQ input, BACK output,

BUZZ output, IRQ2 input

I/O port,

BUZZ output,

IRQ2 input

Notes: 1. DA3 and DA2 are outputs in the H8S/2626 Series only.

2. In the H8S/2626 Series, PA5 and PA4 are OSC2 and OSC1, respectively.

3. BUZZ output pin in the H8S/2626 Series only.

213

9.2 Port 1

9.2.1 Overview

Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O

pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1,

TIOCB1, TIOCA2, and TIOCB2), external interrupt pins (IRQ0 and IRQ1), and address bus

output pins (A23 to A20). Port 1 pin functions change according to the operating mode.

Figure 9-1 shows the port 1 pin configuration.

P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input)

P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input)

P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input)

P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input)

P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input) / A23 (output)

P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input) / A22 (output)

P11 (I/O) / PO9 (output) / TIOCB0 (I/O) / A21 (output)

P10 (I/O) / PO8 (output) / TIOCA0 (I/O) / A20 (output)

Port 1

Port 1 pins

Pin functions in modes 4 to 6

P17 (I/O) / PO15 (output) / TIOCB2 (I/O) / TCLKD (input)

P16 (I/O) / PO14 (output) / TIOCA2 (I/O) / IRQ1 (input)

P15 (I/O) / PO13 (output) / TIOCB1 (I/O) / TCLKC (input)

P14 (I/O) / PO12 (output) / TIOCA1 (I/O) / IRQ0 (input)

P13 (I/O) / PO11 (output) / TIOCD0 (I/O) / TCLKB (input)

P12 (I/O) / PO10 (output) / TIOCC0 (I/O) / TCLKA (input)

P11 (I/O) / PO9 (output) / TIOCB0 (I/O)

P10 (I/O) / PO8 (output) / TIOCA0 (I/O)

Pin functions in mode 7

Figure 9-1 Port 1 Pin Functions

214

9.2.2 Register Configuration

Table 9-2 shows the port 1 register configuration.

Table 9-2 Port 1 Registers

Name Abbreviation R/W Initial Value Address*

Port 1 data direction register P1DDR W H'00 H'FE30

Port 1 data register P1DR R/W H'00 H'FF00

Port 1 register PORT1 R Undefined H'FFB0

Note: * Lower 16 bits of the address.

Port 1 Data Direction Register (P1DDR)

Bit:76543210

P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read.

Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit

to 0 makes the pin an input pin.

P1DDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port 1 Data Register (P1DR)

Bit:76543210

P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10).

P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

215

Port 1 Register (PORT1)

Bit:76543210

P17 P16 P15 P14 P13 P12 P11 P10

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins P17 to P10.

PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port 1 pins (P17 to P10) must always be performed on P1DR.

If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1

read is performed while P1DDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORT1 contents are determined by the pin states, as

P1DDR and P1DR are initialized. PORT1 retains its prior state in software standby mode.

216

9.2.3 Pin Functions

Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB,

TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and

TIOCB2), external interrupt input pins (IRQ0 and IRQ1), and address bus output pins (A23 to

A20). Port 1 pin functions are shown in table 9-3.

Table 9-3 Port 1 Pin Functions

Pin Selection Method and Pin Functions

P17/PO15/

TIOCB2/TCLKD The pin function is switched as shown below according to the combination of

the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0

in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in

TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR.

TPU Channel

2 Setting Table Below (1) Table Below (2)

P17DDR — 0 1 1

NDER15 — — 0 1

Pin function TIOCB2 output P17

input P17

output PO15

output

TIOCB2 input *1

TCLKD input *2

Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 =

2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2

to TPSC0 = B'111.

TCLKD input when channels 2 and 4 are set to phase counting

mode.

TPU Channel

2 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than B'10 B'10

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

217

Pin Selection Method and Pin Functions

P16/PO14/

TIOCA2/IRQ1 The pin function is switched as shown below according to the combination of

the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0

in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and

bit P16DDR.

TPU Channel

2 Setting Table Below (1) Table Below (2)

P16DDR — 0 1 1

NDER14 — — 0 1

Pin function TIOCA2 output P16

input P16

output PO14

output

TIOCA2 input *1

IRQ1 input

TPU Channel

2 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than B'01 B'01

Output

function — Output

compare

output

— PWM

mode 1

output *2

PWM

mode 2

output

—

x: Don’t care

Notes: 1. TIOCA2 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 =

2. TIOCB2 output is disabled.

218

Pin Selection Method and Pin Functions

P15/PO13/

TIOCB1/TCLKC The pin function is switched as shown below according to the combination of

the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0

in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in

TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.

TPU Channel

1 Setting Table Below (1) Table Below (2)

P15DDR — 0 1 1

NDER13 — — 0 1

Pin function TIOCB1 output P15

input P15

output PO13

output

TIOCB1 input *1

TCLKC input *2

Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3

to IOB0 = B'10xx.

2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2

to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is

TPSC2 to TPSC0 = B'101.

TCLKC input when channels 2 and 4 are set to phase counting

mode.

TPU Channel

1 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than

B'10

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

219

Pin Selection Method and Pin Functions

P14/PO12/

TIOCA1/IRQ0 The pin function is switched as shown below according to the combination of

the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0

in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and

bit P14DDR.

TPU Channel

1 Setting Table Below (1) Table Below (2)

P14DDR — 0 1 1

NDER12 — — 0 1

Pin function TIOCA1 output P14

input P14

output PO12

output

TIOCA1 input *1

IRQ0 input

TPU Channel

1 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other

than

B'xx00

Other than B'xx00

CCLR1,

CCLR0 — — — — Other

than B'01 B'01

Output

function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don't care

Notes: 1. TIOCA1 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to

IOA0 = B'10xx.

2. TIOCB1 output is disabled.

220

Pin Selection Method and Pin Functions

P13/PO11/

TIOCD0/TCLKB/

A23

The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),

bits TPSC2 to TPSC0 in TCR0 to TCR2, bits AE3 to AE0 in PFCR, bit

NDER11 in NDERH, and bit P13DDR.

Operating

mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1110 B'1111

TPU Channel

0 Setting Table

Below (1) Table Below (2) —

P13DDR — 0 1 1 —

NDER11 — — 0 1 —

Pin function TIOCD0

output P13 input P13 output PO11

output A23 output

TIOCD0 input *1

TCLKB input *2

Operating

mode Mode 7

AE3 to AE0 —

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P13DDR — 0 1 1

NDER11 — — 0 1

Pin function TIOCD0

output P13 input P13 output PO11 output

TIOCD0 input *1

TCLKB input *2

Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 =

B'10xx.

2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to

TPSC0 = B'101.

TCLKB input when channels 1 and 5 are set to phase counting

mode.

221

Pin Selection Method and Pin Functions

P13/PO11/

TIOCD0/TCLKB/ TPU Channel

0 Setting (2) (1) (2) (2) (1) (2)

A23 (cont) MD3 to MD0 B'0000 B'0010 B'0011

IOD3 to IOD0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'110

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

222

Pin Selection Method and Pin Functions

P12/PO10/

TIOCC0/TCLKA/

A22

The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0),

bits TPSC2 to TPSC0 in TCR0 to TCR5, bits AE3 to AE0 in PFCR, bit

NDER10 in NDERH, and bit P12DDR.

Operating

mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1110 B'1111

TPU Channel

0 Setting Table

Below (1) Table Below (2) —

P12DDR — 0 1 1 —

NDER10 — — 0 1 —

Pin function TIOCC0

output P12

input P12

output PO10

output A22 output

TIOCC0 input *1

TCLKA input *2

Operating

mode Mode 7

AE3 to AE0 —

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P12DDR — 0 1 1

NDER10 — — 0 1

Pin function TIOCC0

output P12 input P12 output PO10 output

TIOCC0 input *1

TCLKA input *2

223

Pin Selection Method and Pin Functions

P12/PO10/

TIOCC0/TCLKA/ TPU Channel

0 Setting (2) (1) (2) (1) (1) (2)

A22 (cont) MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOC3 to IOC0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'101

Output

function — Output

compare

output

— PWM

mode 1

output*3

PWM

mode 2

output

—

x: Don’t care

Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =

B'10xx.

2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to

TPSC0 = B'100.

TCLKA input when channels 1 and 5 are set to phase counting

mode.

3. TIOCD0 output is disabled.

When BFA = 1 or BFB = 1 in TMDR0, output is disabled and

setting (2) applies.

224

Pin Selection Method and Pin Functions

P11/PO9/TIOCB0/

A21 The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, and bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in

TCR0, bits AE3 to AE0 in PFCR, bit NDER9 in NDERH, and bit P11DDR.

Operating

mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1101 B'1110 to

B'1111

TPU Channel

0 Setting Table

Below (1) Table Below (2) —

P11DDR — 0 1 1 —

NDER9 — — 0 1 —

Pin function TIOCB0

output P11

input P11

output PO9

output A21 output

TIOCB0 input *

Operating

mode Mode 7

AE3 to AE0 —

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P11DDR — 0 1 1

NDER9 — — 0 1

Pin function TIOCB0

output P11 input P11 output PO9 output

TIOCB0 input *

Note: *TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 =

B'10xx.

225

Pin Selection Method and Pin Functions

P11/PO9/TIOCB0/

A21 (cont) TPU Channel

0 Setting (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOB3 to IOB0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

— B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'010

Output

function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

226

Pin Selection Method and Pin Functions

P10/PO8/TIOCA0/

A20 The pin function is switched as shown below according to the combination of

the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in

TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0),

bits AE3 to AE0 in PFCR, bit NDER8 in NDERH, and bit P10DDR.

Operating

mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1110 B'1101 to

B'1111

TPU Channel

0 Setting Table

Below (1) Table Below (2) —

P10DDR — 0 1 1 —

NDER8 — — 0 1 —

Pin function TIOCA0

output P10

input P10

output PO8

output A20 output

TIOCA0 input *1

Operating

mode Mode 7

AE3 to AE0 —

TPU Channel

0 Setting Table

Below (1) Table Below (2)

P10DDR — 0 1 1

NDER8 — — 0 1

Pin function TIOCA0

output P10 input P10 output PO8 output

TIOCA0 input *1

227

Pin Selection Method and Pin Functions

P10/PO8/TIOCA0/

A20 (cont) TPU Channel

0 Setting (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOA3 to IOA0 B'0000

B'0100

B'1xxx

B'0001 to

B'0011

B'0101 to

B'0111

B'xx00 Other than B'xx00

CCLR2 to

CCLR0 — — — — Other

than

B'001

Output

function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don’t care

Notes: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 =

B'10xx.

2. TIOCB0 output is disabled.

228

9.3 Port 4

9.3.1 Overview

Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins

(AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 9-2 shows the port

4 pin configuration.

P47

P46

P45

P44

P43

P42

P41

P40

(input) /

AN7 (input)

AN6 (input)

AN5 (input)

AN4 (input)

AN3 (input)

AN2 (input)

AN1 (input)

AN0 (input)

Port 4 pins

Port 4

Figure 9-2 Port 4 Pin Functions

229

9.3.2 Register Configuration

Table 9-4 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a

data direction register or data register.

Table 9-4 Port 4 Registers

Name Abbreviation R/W Initial Value Address*

Port 4 register PORT4 R Undefined H'FFB3

Note: * Lower 16 bits of the address.

Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.

Bit:76543210

P47 P46 P45 P44 P43 P42 P41 P40

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins P47 to P40.

9.3.3 Pin Functions

Port 4 pins also function as A/D converter analog input pins (AN0 to AN7).

230

9.4 Port 9

9.4.1 Overview

Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins

(AN8 to AN15) and D/A converter analog output pins (DA3, DA2). Port 9 pin functions are the

same in all operating modes. Figure 9-3 shows the port 9 pin configuration.

P97

P96

P95

P94

P93

P92

P91

P90

(input) /

AN15 (input) / DA3 (output)*

AN14 (input) / DA2 (output)*

AN13 (input)

AN12 (input)

AN11 (input)

AN10 (input)

AN9 (input)

AN8 (input)

Port 9 pins

Port 9

Note: *DA3 and DA2 are outputs in the H8S/2626 Series only.

Figure 9-3 Port 9 Pin Functions

231

9.4.2 Register Configuration

Table 9-5 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a

data direction register or data register.

Table 9-5 Port 9 Registers

Name Abbreviation R/W Initial Value Address*

Port 9 register PORT9 R Undefined H'FFB8

Note: * Lower 16 bits of the address.

Port 9 Register (PORT9): The pin states are always read when a port 9 read is performed.

Bit:76543210

P97 P96 P95 P94 P93 P92 P91 P90

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins P97 to P90.

9.4.3 Pin Functions

Port 9 pins also function as A/D converter analog input pins (AN8 to AN15) and D/A converter

analog output pins (DA3, DA2).

232

9.5 Port A

9.5.1 Overview

Port A is a 6-bit I/O port. Port A pins also function as address bus outputs and SCI2 I/O pins

(SCK2, RxD2, and TxD2). The pin functions change according to the operating mode.

Port A has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-4 shows the port A pin configuration.

PA5*

PA4*

PA3/A19/SCK2

PA2/A18/RxD2

PA1/A17/TxD2

PA0/A16

Port A pins

Pin functions in mode 7

PA5 (I/O)

PA4 (I/O)

PA3 (I/O) / A19 (output) / SCK2 (I/O)

PA2 (I/O) / A18 (output) / RxD2 (input)

PA1 (I/O) / A17 (output) / TxD2 (output)

PA0 (I/O) / A16 (output)

Pin functions in modes 4 to 6

PA5 (I/O)

PA4 (I/O)

PA3 (I/O) / SCK2 (output)

PA2 (I/O) / RxD2 (input)

PA1 (I/O) / TxD2 (output)

PA0 (I/O)

Port A

Note: *In the H8S/2626 Series, PA5 and PA4 are OSC2 and OSC1, respectively.

Figure 9-4 Port A Pin Functions

233

9.5.2 Register Configuration

Table 9-6 shows the port A register configuration.

Table 9-6 Port A Registers

Name Abbreviation R/W Initial Value*2Address*1

Port A data direction register PADDR W H'0 H'FE39

Port A data register PADR R/W H'0 H'FF09

Port A register PORTA R Undefined H'FFB9

Port A MOS pull-up control register PAPCR R/W H'0 H'FE40

Port A open-drain control register PAODR R/W H'0 H'FE47

Notes: 1. Lower 16 bits of the address.

2. Value of bits 3 to 0.

Port A Data Direction Register (PADDR)

Bit:76543210

——

PA5DDR*PA4DDR*PA3DDR PA2DDR PA1DDR PA0DDR

Initial value : Undefined Undefined 000000

R/W:——WWWWWW

Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read.

PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port A. PADDR cannot be read; if it is, an undefined value will be read.

Bits 7 and 6 are reserved; they return an undetermined value if read.

PADDR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its

prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address

output pins retain their output state or become high-impedance when a transition is made to

software standby mode.

• Modes 4 to 6

The corresponding port A pins become address outputs in accordance with the setting of bits

AE3 to AE0 in PFCR, irrespective of the value of bits PA5DDR to PA0DDR. When pins are

not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an

output port, while clearing the bit to 0 makes the pin an input port.

234

• Mode 7

Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing

the bit to 0 makes the pin an input port.

Port A Data Register (PADR)

Bit:76543210

— — PA5DR*PA4DR*PA3DR PA2DR PA1DR PA0DR

Initial value : Undefined Undefined 000000

R/W : — — R/W R/W R/W R/W R/W R/W

Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read.

PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA5 to

PA0).

Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.

PADR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its

prior state in software standby mode.

Port A Register (PORTA)

Bit:76543210

— — PA5*2PA4*2PA3 PA2 PA1 PA0

Initial value : Undefined Undefined —*1—*1—*1—*1—*1—*1

R/W:——RRRRRR

Notes: 1. Determined by state of pins PA5 to PA0.

2. In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if

read.

PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port A pins (PA5 to PA0) must always be performed on PADR.

Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.

If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A

read is performed while PADDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as

PADDR and PADR are initialized. PORTA retains its prior state in software standby mode.

235

Port A MOS Pull-Up Control Register (PAPCR)

Bit:76543210

——

PA5PCR*PA4PCR*PA3PCR PA2PCR PA1PCR PA0PCR

Initial value : Undefined Undefined 000000

R/W : — — R/W R/W R/W R/W R/W R/W

Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read.

PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port A on an individual bit basis.

Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. In

modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s

SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS

input pull-up for that pin.

In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,

and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up

for that pin.

PAPCR is initialized to H'0 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its

prior state in software standby mode.

Port A Open Drain Control Register (PAODR)

Bit:76543210

——

PA5ODR*PA4ODR*PA3ODR PA2ODR PA1ODR PA0ODR

Initial value : Undefined Undefined 000000

R/W : — — R/W R/W R/W R/W R/W R/W

Note: * In the H8S/2626 Series bits 5 and 4 are reserved, and will return an undefined value if read.

PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each

port A pin (PA5 to PA0).

Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.

When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,

setting a PAODR bit makes the corresponding port A pin an NMOS open-drain output, while

clearing the bit to 0 makes the pin a CMOS output.

PAODR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its

prior state in software standby mode.

236

9.5.3 Pin Functions

Port A pins also function as SCI input/output pins (TxD2, RxD2, SCK2) and address bus output

pins (A19 to A16). Port A pin functions are shown in table 9-7.

Table 9-7 Port A Pin Functions

Pin Selection Method and Pin Functions

PA5*The pin function is switched as shown below according to bit PA5DDR.

PA5DDR 0 1

Pin function PA5 input PA5 output

Note: * In the H8S/2626 Series, PA5 is OSC2.

PA4*The pin function is switched as shown below according to bit PA4DDR.

PA4DDR 0 1

Pin function PA4 input PA4 output

Note: * In the H8S/2626 Series, PA4 is OSC1.

PA3/A19/SCK2 The pin function is switched as shown below according to the operating mode,

bits AE3 to AE0 in PFCR, bit C/A in SMR and bits CKE0 and CKE1 in SCR of

SCI2, and bit PA3DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1011 B'1100 to B'1111

CKE1 0 1 —

C/A01——

CKE0 0 1 — — —

PA3DDR 0 1 — — — —

Pin function PA3

input PA3

output SCK2

input A19 output

Operating mode Mode 7

CKE1 0 1

C/A01—

CKE0 0 1 — —

PA3DDR 0 1 — — —

Pin function PA3

input PA3

output SCK2

input

237

Pin Selection Method and Pin Functions

PA2/A18/RxD2 The pin function is switched as shown below according to the operating mode,

bits AE3 to AE0 in PFCR, bit RE in SCR of SCI2, and bit PA2DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1011 B'1011 to B'1111

RE 0 1 —

PA2DDR 0 1 — —

Pin function PA2 input PA2 output RxD2 input A18 output

Operating mode Mode 7

RE 0 1

PA2DDR 0 1 —

Pin function PA2 input PA2 output RxD2 input

PA1/A17/TxD2 The pin function is switched as shown below according to the operating mode,

bits AE3 to AE0 in PFCR, bit TE in SCR of SCI2, and bit PA1DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1001 B'1010 to B'1111

TE 0 1 —

PA1DDR 0 1 — —

Pin function PA1 input PA1 output TxD2 output A17 output

Operating mode Mode 7

TE 0 1

PA1DDR 0 1 —

Pin function PA1 input PA1 output TxD2 output

238

Pin Selection Method and Pin Functions

PA0/A16 The pin function is switched as shown below according to the operating mode,

bits AE3 to AE0 in PFCR, and bit PA0DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'1000 B'1001 to B'1111

PA0DDR 0 1 —

Pin function PA0 input PA0 output A16 output

Operating mode Mode 7

PA0DDR 0 1

Pin function PA0 input PA0 output

239

9.5.4 MOS Input Pull-Up Function

Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input

pull-up can be specified as on or off on an individual bit basis.

In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the SCI’s

SCMR, SMR, and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS

input pull-up for that pin.

In mode 7, if a pin is in the input state in accordance with the settings in the SCI’s SCMR, SMR,

and SCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up

for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-8 summarizes the MOS input pull-up states.

Table 9-8 MOS Input Pull-Up States (Port A)

Pin States Power-On

Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

Address output or

SCI output OFF OFF OFF OFF

Other than above ON/OFF ON/OFF

Legend:

OFF : MOS input pull-up is always off.

ON/OFF : On when PADDR = 0 and PAPCR = 1; otherwise off.

240

9.6 Port B

9.6.1 Overview

Port B is an 8-bit I/O port. Port B pins also function as TPU I/O pins (TIOCA3, TIOCB3,

TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5) and as address outputs; the pin

functions change according to the operating mode.

Port B has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-5 shows the port B pin configuration.

PB7/A15/TIOCB5

PB6/A14/TIOCA5

PB5/A13/TIOCB4

PB4/A12/TIOCA4

PB3/A11/TIOCD3

PB2/A10/TIOCC3

PB1/A9 /TIODB3

PB0/A8 /TIOCA3

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

(I/O) /

A15

A14

A13

A12

A11

A10

(output) / TIOCB5 (I/O)

(output) / TIOCA5 (I/O)

(output) / TIOCB4 (I/O)

(output) / TIOCA4 (I/O)

(output) / TIOCD3 (I/O)

(output) / TIOCC3 (I/O)

(output) / TIOCB3 (I/O)

(output) / TIOCA3 (I/O)

Port B pins

Pin functions in mode 7

Pin functions in modes 4 to 6

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

(I/O) / TIOCB5 (I/O)

(I/O) / TIOCA5 (I/O)

(I/O) / TIOCB4 (I/O)

(I/O) / TIOCA4 (I/O)

(I/O) / TIOCD3 (I/O)

(I/O) / TIOCC3 (I/O)

(I/O) / TIOCB3 (I/O)

(

I/O

)

/ TIOCA3

(

I/O

)

Port B

Figure 9-5 Port B Pin Functions

241

9.6.2 Register Configuration

Table 9-9 shows the port B register configuration.

Table 9-9 Port B Registers

Name Abbreviation R/W Initial Value Address*

Port B data direction register PBDDR W H'00 H'FE3A

Port B data register PBDR R/W H'00 H'FF0A

Port B register PORTB R Undefined H'FFBA

Port B MOS pull-up control register PBPCR R/W H'00 H'FE41

Port B open-drain control register PBODR R/W H'00 H'FE48

Note: * Lower 16 bits of the address.

Port B Data Direction Register (PBDDR)

Bit:76543210

PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.

PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode. The OPE bit in SBYCR is used to select whether the address output pins

retain their output state or become high-impedance when a transition is made to software standby

mode.

• Modes 4 to 6

The corresponding port B pins become address outputs in accordance with the setting of bits

AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as

address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port,

while clearing the bit to 0 makes the pin an input port.

• Mode 7

Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing

the bit to 0 makes the pin an input port.

242

Port B Data Register (PBDR)

Bit:76543210

PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to

PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior

state in software standby mode.

Port B Register (PORTB)

Bit:76543210

PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PB7 to PB0.

PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port B pins (PB7 to PB0) must always be performed on PBDR.

If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B

read is performed while PBDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTB contents are determined by the pin states, as

PBDDR and PBDR are initialized. PORTB retains its prior state in software standby mode.

243

Port B MOS Pull-Up Control Register (PBPCR)

Bit:76543210

PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port B on an individual bit basis.

In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s

TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for

that pin.

In mode 7, if a pin is in the input state in accordance with the settings in the TPU’s TIOR and in

DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.

PBPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port B Open Drain Control Register (PBODR)

Bit:76543210

PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PBODR is an 8-bit readable/writable register that controls the PMOS on/off state for each port B

pin (PB7 to PB0).

When pins are not address outputs in accordance with the setting of bits AE3 to AE0 in PFCR,

setting a PBODR bit makes the corresponding port B pin an NMOS open-drain output, while

clearing the bit to 0 makes the pin a CMOS output.

PBODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

9.6.3 Pin Functions

Port B pins also function as TPU input/output pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3,

TIOCA4, TIOCB4, TIOCA5, TIOCB5) and address bus output pins (A15 to A8). Port B pin

functions are shown in table 9-10.

244

Table 9-10 Port B Pin Functions

Pin Selection Method and Pin Functions

PB7/A15/

TIOCB5 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR5, bits

IOB3 to IOB0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5, and bit PB7DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'0111 B'1000 to B'1111

TPU channel 5

settings (1) in table

below (2) in table

below —

PB7DDR — 0 1 —

Pin function TIOCB5 output PB7 input PB7 output A15 output

TIOCB5 input*

Operating mode Mode 7

TPU channel 5

settings (1) in table below (2) in table below

PB7DDR — 0 1

Pin function TIOCB5 output PB7 input PB7 output

TIOCB5 input*

TPU channel 5

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

— B'xx00 Not B'xx00

CCLR1, CCLR0 — — — — Not B'10 B'10

Output function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

Note: * TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 = 1.

245

Pin Selection Method and Pin Functions

PB6/A14/

TIOCA5 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR5, bits

IOA3 to IOA0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5, and bit PB6DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'0110 B'0111 to B'1111

TPU channel 5

settings (1) in table

below (2) in table

below —

PB6DDR — 0 1 —

Pin function TIOCA5 output PB6 input PB6 output A14 output

TIOCA5 input*1

Operating mode Mode 7

TPU channel 5

settings (1) in table below (2) in table below

PB6DDR — 0 1

Pin function TIOCA5 output PB6 input PB6 output

TIOCA5 input*1

TPU channel 5

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

B'xx00 Not

B'xx00 Not B'xx00

CCLR1, CCLR0 — — — — Not B'01 B'01

Output function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don’t care

Notes: 1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 = 1.

2. TIOCB5 is disabled for output.

246

Pin Selection Method and Pin Functions

PB5/A13/

TIOCB4 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 4 settings by bits MD3 to MD0 in TMDR4, bits

IOB3 to IOB0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4, and bit PB5DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'0101 B'0110 to B'1111

TPU channel 4

settings (1) in table

below (2) in table

below —

PB5DDR — 0 1 —

Pin function TIOCB4 output PB5 input PB5 output A13 output

TIOCB4 input*

Operating mode Mode 7

TPU channel 4

settings (1) in table below (2) in table below

PB5DDR — 0 1

Pin function TIOCB4 output PB5 input PB5 output

TIOCB4 input*

TPU channel 5

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000, B'01xx B'0010 B'0011

IOB3 to IOB0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

— B'xx00 Not B'xx00

CCLR1, CCLR0 — — — — Not B'10 B'10

Output function 1 Output

compare

output

1 1 PWM

mode 2

output

x: Don’t care

Note: *TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx, and IOB3 to IOB0 =

B'10xx.

247

Pin Selection Method and Pin Functions

PB4/A12/

TIOCA4 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 5 settings by bits MD3 to MD0 in TMDR4, bits

IOA3 to IOA0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4, and bit PB4DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'0100 B'0101 to B'1111

TPU channel 4

settings (1) in table

below (2) in table

below —

PB4DDR — 0 1 —

Pin function TIOCA4 output PB4 input PB4 output A12 output

TIOCA4 input*1

Operating mode Mode 7

TPU channel 4

settings (1) in table below (2) in table below

PB4DDR — 0 1

Pin function TIOCA4 output PB4 input PB4 output

TIOCA4 input*1

TPU channel 4

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011

IOA3 to IOA0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

B'xx00 Not

B'xx00 Not B'xx00

CCLR1, CCLR0 — — — — Not B'01 B'01

Output function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don’t care

Notes: 1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01xx, and IOA3 to IOA0 =

B'10xx.

2. TIOCB4 is disabled for output.

248

Pin Selection Method and Pin Functions

PB3/A11/

TIOCD3 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits

IOD3 to IOD0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3, and bit PB3DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'0011 B'0100 to B'1111

TPU channel 3

settings (1) in table

below (2) in table

below —

PB3DDR — 0 1 —

Pin function TIOCD3 output PB3 input PB3 output A11 output

TIOCD3 input*

Operating mode Mode 7

TPU channel 3

settings (1) in table below (2) in table below

PB3DDR — 0 1

Pin function TIOCD3 output PB3 input PB3 output

TIOCD3 input*

TPU channel 3

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOD3 to IOD0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

— B'xx00 Not B'xx00

CCLR2 to

CCLR0 — — — — Not B'110 B'110

Output function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

Note *TIOCD3 input when MD3 to MD0 = B'0000 or B'01xx, and IOD3 to IOD0 =

B'10xx.

249

Pin Selection Method and Pin Functions

PB2/A10/

TIOCC3 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits

IOC3 to IOC0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3, and bit PB2DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'0010 B'0011 to B'1111

TPU channel 3

settings (1) in table

below (2) in table

below —

PB2DDR — 0 1 —

Pin function TIOCC3 output PB2 input PB2 output A10 output

TIOCC3 input*1

Operating mode Mode 7

TPU channel 3

settings (1) in table below (2) in table below

PB2DDR — 0 1

Pin function TIOCC3 output PB2 input PB2 output

TIOCC3 input*1

TPU channel 3

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOC3 to IOC0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

B'xx00 Not

B'xx00 Not B'xx00

CCLR2 to

CCLR0 — — — — Not B'101 B'101

Output function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don’t care

Notes: 1. TIOCC3 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx.

2. TIOCD3 is disabled for output.

250

Pin Selection Method and Pin Functions

PB1/A9/

TIOCB3 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits

IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3, and bit PB1DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 to B'0001 B'0010 to B'1111

TPU channel 3

settings (1) in table

below (2) in table

below —

PB1DDR — 0 1 —

Pin function TIOCB3 output PB1 input PB1 output A9 output

TIOCB3 input*

Operating mode Mode 7

TPU channel 3

settings (1) in table below (2) in table below

PB1DDR — 0 1

Pin function TIOCB3 output PB1 input PB1 output

TIOCB3 input*

TPU channel 3

settings (2) (1) (2) (2) (1) (2)

MD3 to MD0 B'0000 B'0010 B'0011

IOB3 to IOB0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

— B'xx00 Not B'xx00

CCLR2 to

CCLR0 — — — — Not B'010 B'010

Output function — Output

compare

output

— — PWM

mode 2

output

—

x: Don’t care

Note: *TIOCB3 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx.

251

Pin Selection Method and Pin Functions

PB0/A8/

TIOCA3 The pin function is switched as shown below according to the operating mode, bits

AE3 to AE0 in PFCR, the TPU channel 3 settings by bits MD3 to MD0 in TMDR3, bits

IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3, and bit PB0DDR.

Operating mode Modes 4 to 6

AE3 to AE0 B'0000 B'0001 to B'1111

TPU channel 3

settings (1) in table

below (2) in table

below —

PB0DDR — 0 1 —

Pin function TIOCA3 output PB0 input PB0 output A8 output

TIOCA3 input*1

Operating mode Mode 7

TPU channel 3

settings (1) in table below (2) in table below

PB0DDR — 0 1

Pin function TIOCA3 output PB0 input PB0 output

TIOCA3 input*1

TPU channel 3

settings (2) (1) (2) (1) (1) (2)

MD3 to MD0 B'0000 B'001x B'0010 B'0011

IOA3 to IOA0 B'0000,

B'0100,

B'1xxx

B'0001 to

B'0011,

B'0101 to

B'0111

B'xx00 Not

B'xx00 Not B'xx00

CCLR2 to

CCLR0 — — — — Not B'001 B'001

Output function — Output

compare

output

— PWM

mode 1

output*2

PWM

mode 2

output

—

x: Don’t care

Notes: 1. TIOCA3 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx.

2. TIOCB3 is disabled for output.

252

9.6.4 MOS Input Pull-Up Function

Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input

pull-up can be specified as on or off on an individual bit basis.

In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in the TPU’s

TIOR, and in DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for

that pin.

In mode 7, if a pin is in the input state in accordance with the settings in the TPU’s TIOR and in

DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-11 summarizes the MOS input pull-up states.

Table 9-11 MOS Input Pull-Up States (Port B)

Pin States Power-On

Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

Address output or

TPU output OFF OFF OFF OFF

Other than above ON/OFF ON/OFF

Legend:

OFF : MOS input pull-up is always off.

ON/OFF : On when PBDDR = 0 and PBPCR = 1; otherwise off.

253

9.7 Port C

9.7.1 Overview

Port C is an 8-bit I/O port. Port C has an address bus output function, SCI I/O pins (TxD0, RxD0,

SCK0, TxD1, RxD1 and SCK1), and external interrupt input pins (IRQ4 and IRQ5), and the pin

functions change according to the operating mode.

Port C has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-6 shows the port C pin configuration.

PC7/A7

PC6/A6

PC5/A5/SCK1/IRQ5

PC4/A4/RxD1

PC3/A3/TxD1

PC2/A2/SCK0/IRQ4

PC1/A1/RxD0

PC0/A0/TxD0

Port C

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

(input) /

(

input

)

(output)

(output) / SCK1 (I/O) / IRQ5 (input)

(output) / RxD1 (input)

(output) / TxD1 (output)

(output) / SCK0 (I/O) / IRQ4 (input)

(output) / RxD0 (input)

(

output

)

/ TxD0

(

output

)

Port C pins

Pin functions in mode 6 Pin functions in mode 7

(output)

Pin functions in modes 4 and 5

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

(I/O)

(I/O) / SCK1 (I/O) / IRQ5 (input)

(I/O) / RxD1 (input)

(I/O) / TxD1 (output)

(I/O) / SCK0 (I/O) / IRQ4 (input)

(I/O) / RxD0 (input)

(I/O) / TxD0 (output)

Figure 9-6 Port C Pin Functions

254

9.7.2 Register Configuration

Table 9-12 shows the port C register configuration.

Table 9-12 Port C Registers

Name Abbreviation R/W Initial Value Address*

Port C data direction register PCDDR W H'00 H'FE3B

Port C data register PCDR R/W H'00 H'FF0B

Port C register PORTC R Undefined H'FFBB

Port C MOS pull-up control register PCPCR R/W H'00 H'FE42

Port C open-drain control register PCODR R/W H'00 H'FE49

Note: * Lower 16 bits of the address.

Port C Data Direction Register (PCDDR)

Bit:76543210

PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.

PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode. As the SCI is initialized, pin states are determined by the PCDDR and

PCDR specifications. The OPE bit in SBYCR is used to select whether the address output pins

retain their output state or become high-impedance when a transition is made to software standby

mode.

• Modes 4 and 5

The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits.

• Mode 6

Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while

clearing the bit to 0 makes the pin an input port.

• Mode 7

Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing

the bit to 0 makes the pin an input port.

255

Port C Data Register (PCDR)

Bit:76543210

PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to

PC0).

PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port C Register (PORTC)

Bit:76543210

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PC7 to PC0.

PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port C pins (PC7 to PC0) must always be performed on PCDR.

If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C

read is performed while PCDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTC contents are determined by the pin states, as

PCDDR and PCDR are initialized. PORTC retains its prior state in software standby mode.

256

Port C MOS Pull-Up Control Register (PCPCR)

Bit:76543210

PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port C on an individual bit basis.

In modes 6 and 7, if a pin is in the input state in accordance with the settings in the SCI’s SMR

and SCR, and in PCDDR, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-

up for that pin.

PCPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port C Open Drain Control Register (PCODR)

Bit:76543210

PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PCODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port C

pin (PC7 to PC0).

If the setting of bits AE3 to AE0 in PFCR is other than address output, setting a PCODR bit to 1

makes the corresponding port C pin an NMOS open-drain output, while clearing the bit to 0 makes

the pin a CMOS output.

PCODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state

after a manual reset, and in software standby mode.

257

9.7.3 Pin Functions

Port C pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1),

interrupt input pins (IRQ4 and IRQ5), and address bus outputs. The pin functions differ between

modes 4 and 5, mode 6, and mode 7. Port C pin functions are shown in table 9-13.

Table 9-13 Port C Pin Functions

Pin Selection Method and Pin Functions

PC7/A7 The pin function is switched as shown below according to the operating mode

and bit PC7DDR.

Operating

Mode Modes 4

and 5 Mode 6 Mode 7

PC7DDR — 0101

Pin function A7

output PC7

input A7

output PC7

input PC7

output

PC6/A6 The pin function is switched as shown below according to the operating mode

and bit PC6DDR.

Operating

Mode Modes 4

and 5 Mode 6 Mode 7

PC6DDR — 0101

Pin function A6

output PC6

input A6

output PC6

input PC6

output

258

Pin Selection Method and Pin Functions

PC5/A5/SCK1/

IRQ5 The pin function is switched as shown below according to the operating mode,

bit C/A in the SCI1’s SMR, bits CKE0 and CKE1 in SCR, and bit PC5DDR.

Operating

Mode Modes 4

and 5 Mode 6

PC5DDR — 0 1

CKE1 — 0 1 —

C/A—01——

CKE0 — 0 1 — — —

Pin function A5

output PC5

input SCK1

output SCK1

input A5

output

IRQ5 input

Operating

Mode Mode 7

CKE1 0 1

C/A01—

CKE0 0 1 — —

PC5DDR 0 1 — — —

Pin function PC5

input PC5

output SCK1

input

IRQ5 input

259

Pin Selection Method and Pin Functions

PC4/A4/RxD1 The pin function is switched as shown below according to the operating mode,

bit RE in the SCI1’s SCR, and bit PC4DDR.

Operating

Mode Modes 4

and 5 Mode 6

PC4DDR — 0 1

RE —01—

Pin function A4 output PC4 input RxD1 input A4 output

Operating

Mode Mode 7

RE 0 1

PC4DDR 0 1 —

Pin function PC4 input PC4 output RxD1 input

PC3/A3/TxD1 The pin function is switched as shown below according to the operating mode,

bit TE in the SCI1’s SCR, and bit PC3DDR.

Operating

Mode Modes 4

and 5 Mode 6

PC3DDR — 0 1

TE —01—

Pin function A3 output PC3 input TxD1 output A3 output

Operating

Mode Mode 7

TE 0 1

PC3DDR 0 1 —

Pin function PC3 input PC3 output TxD1 output

260

Pin Selection Method and Pin Functions

PC2/A2/SCK0/

IRQ4 The pin function is switched as shown below according to the operating mode,

bit C/A in the SCI0’s SMR, bits CKE0 and CKE1 in SCR, and bit PC2DDR.

Operating

Mode Modes 4

and 5 Mode 6

PC2DDR — 0 1

CKE1 — 0 1 —

C/A—01——

CKE0 — 0 1 — — —

Pin function A2

output PC2

input SCK0

output SCK0

input A2

output

IRQ4 input

Operating

Mode Mode 7

CKE1 0 1

C/A01—

CKE0 0 1 — —

PC2DDR 0 1 — — —

Pin function PC2

input PC2

output SCK0

input

IRQ4 input

261

Pin Selection Method and Pin Functions

PC1/A1/RxD0 The pin function is switched as shown below according to the operating mode,

bit RE in the SCI0’s SCR, and bit PC1DDR.

Operating

Mode Modes 4

and 5 Mode 6

PC1DDR — 0 1

RE —01—

Pin function A1 output PC1 input RxD0 input A1 output

Operating

Mode Mode 7

RE 0 1

PC1DDR 0 1 —

Pin function PC1 input PC1 output RxD0 input

PC0/A0/TxD0 The pin function is switched as shown below according to the operating mode,

bit TE in the SCI0’s SCR, and bit PC0DDR.

Operating

Mode Modes 4

and 5 Mode 6

PC0DDR — 0 1

TE —01—

Pin function A0 output PC0 input TxD0 output A0 output

Operating

Mode Mode 7

TE 0 1

PC0DDR 0 1 —

Pin function PC0 input PC0 output TxD0 output

262

9.7.4 MOS Input Pull-Up Function

Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS

input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an

individual bit basis.

In modes 6 and 7, if a pin is in the input state in accordance with the settings in the SCI’s SMR

and SCR, of pins IRQ4 and IRQ5, and in PCDDR, setting the corresponding PCPCR bit to 1 turns

on the MOS input pull-up for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-14 summarizes the MOS input pull-up states.

Table 9-14 MOS Input Pull-Up States (Port C)

Pin States Power-On

Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

Address output OFF OFF OFF OFF

Other than above ON/OFF ON/OFF

Legend:

OFF : MOS input pull-up is always off.

ON/OFF : On when PCDDR = 0 and PCPCR = 1; otherwise off.

263

9.8 Port D

9.8.1 Overview

Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change

according to the operating mode.

Port D has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-7 shows the port D pin configuration.

PD7/D15

PD6/D14

PD5/D13

PD4/D12

PD3/D11

PD2/D10

PD1/D9

PD0/D8

Port D

D15

D14

D13

D12

D11

D10

(I/O)

Port D pins Pin functions in modes 4 to 6

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

(I/O)

Pin functions in mode 7

Figure 9-7 Port D Pin Functions

264

9.8.2 Register Configuration

Table 9-15 shows the port D register configuration.

Table 9-15 Port D Registers

Name Abbreviation R/W Initial Value Address*

Port D data direction register PDDDR W H'00 H'FE3C

Port D data register PDDR R/W H'00 H'FF0C

Port D register PORTD R Undefined H'FFBC

Port D MOS pull-up control register PDPCR R/W H'00 H'FE43

Note: * Lower 16 bits of the address.

Port D Data Direction Register (PDDDR)

Bit:76543210

PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.

PDDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

• Modes 4 to 6

The input/output direction specification by PDDDR is ignored, and port D is automatically

designated for data I/O.

• Mode 7

Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing

the bit to 0 makes the pin an input port.

265

Port D Data Register (PDDR)

Bit:76543210

PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to

PD0).

PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port D Register (PORTD)

Bit:76543210

PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PD7 to PD0.

PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port D pins (PD7 to PD0) must always be performed on PDDR.

If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D

read is performed while PDDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as

PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode.

266

Port D MOS Pull-Up Control Register (PDPCR)

Bit:76543210

PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port D on an individual bit basis.

When a PDDDR bit is cleared to 0 (input port setting) in mode 7, setting the corresponding

PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin.

PDPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

9.8.3 Pin Functions

In modes 4 to 6, port D pins automatically function as data bus input/output pins (D15 to D8). In

mode 7, each pin in port D functions as an input/output port, and input or output can be specified

individually for each pin. Port D pin functions are shown in table 9-16.

Table 9-16 Port D Pin Functions

Pin Selection Method and Pin Functions

PD7/D15,

PD6/D14, The pin function is switched as shown below according to the operating mode and

PDDDR.

PD5/D13, Operating mode Modes 4 to 6 Mode 7

PD4/D12, PDnDDR — 0 1

PD3/D11,

PD2/D10,

PD1/D9,

Pin function Data bus input/

output

(D15 to D8)

PDn input PDn output

PD0/D8 n: 7 to 0

267

9.8.4 MOS Input Pull-Up Function

Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS

input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit

basis.

When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on

the MOS input pull-up for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-17 summarizes the MOS input pull-up states.

Table 9-17 MOS Input Pull-Up States (Port D)

Modes Power-On

Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

4 to 6 OFF OFF OFF OFF

7 ON/OFF ON/OFF

Legend:

OFF : MOS input pull-up is always off.

ON/OFF : On when PDDDR = 0 and PDPCR = 1; otherwise off.

268

9.9 Port E

9.9.1 Overview

Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change

according to the operating mode and whether 8-bit or 16-bit bus mode is selected.

Port E has a built-in MOS input pull-up function that can be controlled by software.

Figure 9-8 shows the port E pin configuration.

PE7/D7

PE6/D6

PE5/D5

PE4/D4

PE3/D3

PE2/D2

PE1/D1

PE0/D0

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

(I/O) /

Port E pins Pin functions in modes 4 to 6

Pin functions in mode 7

(I/O)

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

(I/O)

Port E

Figure 9-8 Port E Pin Functions

269

9.9.2 Register Configuration

Table 9-18 shows the port E register configuration.

Table 9-18 Port E Registers

Name Abbreviation R/W Initial Value Address*

Port E data direction register PEDDR W H'00 H'FE3D

Port E data register PEDR R/W H'00 H'FF0D

Port E register PORTE R Undefined H'FFBD

Port E MOS pull-up control register PEPCR R/W H'00 H'FE44

Note: *Lower 16 bits of the address.

Port E Data Direction Register (PEDDR)

Bit:76543210

PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.

PEDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

• Modes 4 to 6

When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit

to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the

pin an input port.

When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is

ignored, and port E is designated for data I/O.

For details of 8-bit and 16-bit bus modes, see section 7, Bus Controller.

• Mode 7

Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the

bit to 0 makes the pin an input port.

270

Port E Data Register (PEDR)

Bit:76543210

PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0).

PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port E Register (PORTE)

Bit:76543210

PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PE7 to PE0.

PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port E pins (PE7 to PE0) must always be performed on PEDR.

If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E

read is performed while PEDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTE contents are determined by the pin states, as

PEDDR and PEDR are initialized. PORTE retains its prior state in software standby mode.

271

Port E MOS Pull-Up Control Register (PEPCR)

Bit:76543210

PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function

incorporated into port E on an individual bit basis.

When a PEDDR bit is cleared to 0 (input port setting) with 8-bit bus mode selected in mode 4 to 6,

or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the

corresponding pin.

PEPCR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

9.9.3 Pin Functions

Port E pins also function as data bus input/output pins (D7 to D0). If at least one of areas 0 to 7 is

designated as 16-bit bus space in modes 4 to 6, port E pins automatically function as data bus

input/output pins. If all areas are designated as 8-bit bus space in modes 4 to 6, or in mode 7, each

pin in port E functions as an input/output port, and input or output can be specified individually

for each pin. Port E pin functions are shown in table 9-19.

Table 9-19 Port E Pin Functions

Pin Selection Method and Pin Functions

PE7/D7,

PE6/D6, The pin function is switched as shown below according to the operating mode,

ABWCR in the bus controller, and PEDDR.

PE5/D5, Operating mode Modes 4 to 6 Mode 7

PE4/D4, ABWCR H'FF Not H'FF — —

PE3/D3, PEnDDR 0 1 — 0 1

PE2/D2,

PE1/D1,

PE0/D0

Pin function PEn input PEn output Data bus

input/output

(D7 to D0)

PEn input PEn output

n: 7 to 0

272

9.9.4 MOS Input Pull-Up Function

Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS

input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7,

and can be specified as on or off on an individual bit basis.

When a PEDDR bit is cleared to 0 in mode 4 to 6 when 8-bit bus mode is selected, or in mode 7,

setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin.

The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.

The prior state is retained in software standby mode.

Table 9-20 summarizes the MOS input pull-up states.

Table 9-20 MOS Input Pull-Up States (Port E)

Modes Power-On

Reset Hardware

Standby Mode Software

Standby Mode In Other

Operations

7 OFF OFF ON/OFF ON/OFF

4 to 6 8-bit bus

16-bit bus OFF OFF

Legend:

OFF : MOS input pull-up is always off.

ON/OFF : On when PEDDR = 0 and PEPCR = 1; otherwise off.

273

9.10 Port F

9.10.1 Overview

Port F is an 8-bit I/O port. Port F pins also function as external interrupt input pins (IRQ2 and

IRQ3), BUZZ output pin*, A/D trigger input pin (ADTRG), bus control signal input/output pins

(AS, RD, HWR, LWR, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin.

Note: * BUZZ output pin in the H8S/2626 Series only.

Figure 9-9 shows the port F pin configuration.

PF7/ø

PF6/AS

PF5/RD

PF4/HWR

PF3/LWR/ADTRG/IRQ3

PF2/WAIT /BREQO

PF1/BACK/BUZZ*

PF0/BREQ/IRQ2

Port F

Port F pins

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

(input) / ø (output)

(I/O)

(I/O) / ADTRG (input) / IRQ3 (input)

(I/O)

(I/O) / BUZZ (output)*

(I/O) / IRQ2 (input)

Pin functions in mode 7

PF7 (input) / ø (output)

AS (output)

RD (output)

HWR (output)

PF3 (I/O) / LWR (output) / ADTRG (input) / IRQ3 (input)

PF2 (I/O) /WAIT (input) / BREQO (output)

PF1 (I/O) / BACK (output) / BUZZ (output)*

PF0 (I/O) / BREQ (input) / IRQ2 (input)

Pin functions in modes 4 to 6

Note: *BUZZ output pin in the H8S/2626 Series only.

Figure 9-9 Port F Pin Functions

274

9.10.2 Register Configuration

Table 9-21 shows the port F register configuration.

Table 9-21 Port F Registers

Name Abbreviation R/W Initial Value Address*1

Port F data direction register PFDDR W H'80/H'00*2H'FE3E

Port F data register PFDR R/W H'00 H'FF0E

Port F register PORTF R Undefined H'FFBE

Notes: 1. Lower 16 bits of the address.

2. Initial value depends on the mode.

Port F Data Direction Register (PFDDR)

Bit:76543210

PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR

Modes 4 to 6

Initial value : 1 0 0 0 0 0 0 0

R/W:WWWWWWWW

Mode 7

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.

PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to

H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used

to select whether the bus control output pins retain their output state or become high-impedance

when a transition is made to software standby mode.

• Modes 4 to 6

Pin PF7 functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an

input port when the bit is cleared to 0.

The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are

automatically designated as bus control outputs (AS, RD, HWR, and LWR).

Pins PF2 to PF0 are designated as bus control input/output pins (WAIT, BREQO, BACK,

BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes

the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input

port.

275

• Mode 7

Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in

the case of pin PF7, the ø output pin. Clearing the bit to 0 makes the pin an input port.

Port F Data Register (PFDR)

Bit:76543210

PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0).

PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in

software standby mode.

Port F Register (PORTF)

Bit:76543210

PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

Initial value : —*—*—*—*—*—*—*—*

R/W:RRRRRRRR

Note: *Determined by state of pins PF7 to PF0.

PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port F pins (PF7 to PF0) must always be performed on PFDR.

If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F

read is performed while PFDDR bits are cleared to 0, the pin states are read.

After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as

PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.

276

9.10.3 Pin Functions

Port F pins also function as external interrupt input pins (IRQ2 and IRQ3), BUZZ output pin*,

A/D trigger input pin (ADTRG), bus control signal input/output pins (AS, RD, HWR, LWR,

WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. The pin functions differ

between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9-22.

Note: * BUZZ output pin in the H8S/2626 Series only.

Table 9-22 Port F Pin Functions

Pin Selection Method and Pin Functions

PF7/ø The pin function is switched as shown below according to bit PF7DDR.

PF7DDR 0 1

Pin function PF7 input ø output

PF6/AS The pin function is switched as shown below according to the operating mode

and bit PF6DDR.

Operating

Mode Modes 4 to 6 Mode 7

PF6DDR — 0 1

Pin function AS output PF6 input PF6 output

PF5/RD The pin function is switched as shown below according to the operating mode

and bit PF5DDR.

Operating

Mode Modes 4 to 6 Mode 7

PF5DDR — 0 1

Pin function RD output PF5 input PF5 output

PF4/HWR The pin function is switched as shown below according to the operating mode

and bit PF4DDR.

Operating

Mode Modes 4 to 6 Mode 7

PF4DDR — 0 1

Pin function HWR output PF4 input PF4 output

277

Pin Selection Method and Pin Functions

PF3/LWR/

ADTRG/IRQ3 The pin function is switched as shown below according to the operating mode,

the bus mode, A/D converter bits TRGS1 and TRGS0, and bit PF3DDR.

Operating

Mode Modes 4 to 6 Mode 7

Bus mode 16-bit bus

mode 8-bit bus mode —

PF3DDR — 0101

Pin function LWR PF3 input PF3 output PF3 input PF3 output

output ADTRG input∗1

IRQ3 input∗2

Notes: 1. ADTRG input when TRGS0 = TRGS1 = 1.

2. When used as an external interrupt input pin, do not use as an I/O

pin for another function.

PF2/WAIT/

BREQO The pin function is switched as shown below according to the combination of

the operating mode, and bits BREQOE, WAITE, ABW5 to ABW2, and

PF2DDR.

Operating

Mode Modes 4 to 6 Mode 7

BREQOE 0 1 —

WAITE 0 1 — —

PF2DDR 0 1 — — 0 1

Pin function PF2

input PF2

output WAIT

input BREQO

output PF2

input PF2

output

PF1/BACK/

BUZZ*The pin function is switched as shown below according to the combination of

the operating mode, and bits BRLE, BUZZE, and PF1DDR.

Operating

Mode Modes 4 to 6 Mode 7

BRLE 0 1 —

BUZZE 0 1 — 0 1

PF1DDR 0 1 — — 0 1 —

Pin function PF1

input PF1

output BUZZ*

output BACK

output PF1

input PF1

output BUZZ*

output

Note: * BUZZ output pin in the H8S/2626 Series only.

278

Pin Selection Method and Pin Functions

PF0/BREQ/IRQ2 The pin function is switched as shown below according to the combination of

the operating mode, and bits BRLE and PF0DDR.

Operating

Mode Modes 4 to 6 Mode 7

BRLE 0 1 —

PF0DDR 0 1 — 0 1

Pin function PF0

input PF0

output BREQ

input PF0

output

IRQ2 input

279

Section 10 16-Bit Timer Pulse Unit (TPU)

10.1 Overview

The H8S/2626 Series and H8S/2623 Series have an on-chip 16-bit timer pulse unit (TPU) that

comprises six 16-bit timer channels.

10.1.1 Features

• Maximum 16-pulse input/output

 A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,

and two each for channels 1, 2, 4, and 5), each of which can be set independently as an

output compare/input capture register

 TGRC and TGRD for channels 0 and 3 can also be used as buffer registers

• Selection of 8 counter input clocks for each channel

• The following operations can be set for each channel:

 Waveform output at compare match: Selection of 0, 1, or toggle output

 Input capture function: Selection of rising edge, falling edge, or both edge detection

 Counter clear operation: Counter clearing possible by compare match or input capture

 Synchronous operation:

Multiple timer counters (TCNT) can be written to simultaneously

Simultaneous clearing by compare match and input capture possible

 PWM mode: Any PWM output duty can be set

 Maximum of 15-phase PWM output possible by combination with synchronous operation

• Buffer operation settable for channels 0 and 3

 Input capture register double-buffering possible

 Automatic rewriting of output compare register possible

• Phase counting mode settable independently for each of channels 1, 2, 4, and 5

 Two-phase encoder pulse up/down-count possible

• Cascaded operation

 Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel

4) overflow/underflow

• Fast access via internal 16-bit bus

 Fast access is possible via a 16-bit bus interface

280

• 26 interrupt sources

 For channels 0 and 3, four compare match/input capture dual-function interrupts and one

overflow interrupt can be requested independently

 For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one

overflow interrupt, and one underflow interrupt can be requested independently

• Automatic transfer of register data

 Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer

controller (DTC)

• Programmable pulse generator (PPG) output trigger can be generated

 Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger

• A/D converter conversion start trigger can be generated

 Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter

conversion start trigger

• Module stop mode can be set

 As the initial setting, TPU operation is halted. Register access is enabled by exiting module

stop mode.

Table 10-1 lists the functions of the TPU.

281

Table 10-1 TPU Functions

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

Count clock ø/1

ø/4

ø/16

ø/64

TCLKA

TCLKB

TCLKC

TCLKD

ø/1

ø/4

ø/16

ø/64

ø/256

TCLKA

TCLKB

ø/1

ø/4

ø/16

ø/64

ø/1024

TCLKA

TCLKB

TCLKC

ø/1

ø/4

ø/16

ø/64

ø/256

ø/1024

ø/4096

TCLKA

ø/1

ø/4

ø/16

ø/64

ø/1024

TCLKA

TCLKC

ø/1

ø/4

ø/16

ø/64

ø/256

TCLKA

TCLKC

TCLKD

General registers TGR0A

TGR0B TGR1A

TGR1B TGR2A

TGR2B TGR3A

TGR3B TGR4A

TGR4B TGR5A

TGR5B

General registers/

buffer registers TGR0C

TGR0D — — TGR3C

TGR3D ——

I/O pins TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1 TIOCA2

TIOCB2 TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4 TIOCA5

TIOCB5

Counter clear

function TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

TGR

compare

match or

input

capture

Compare 0 output

match 1 output

output Toggle

output

Input capture

function

Synchronous

operation

PWM mode

Phase counting

mode — —

Buffer operation —— ——

282

Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5

DTC

activation TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

TGR

compare

match or

input capture

A/D

converter

trigger

TGR0A

compare

match or

input capture

TGR1A

compare

match or

input capture

TGR2A

compare

match or

input capture

TGR3A

compare

match or

input capture

TGR4A

compare

match or

input capture

TGR5A

compare

match or

input capture

PPG

trigger TGR0A/

TGR0B

compare

match or

input capture

TGR1A/

TGR1B

compare

match or

input capture

TGR2A/

TGR2B

compare

match or

input capture

TGR3A/

TGR3B

compare

match or

input capture

——

Interrupt

sources 5 sources

• Compare

match or

input

capture 0A

• Compare

match or

input

capture 0B

• Compare

match or

input

capture 0C

• Compare

match or

input

capture 0D

• Overflow

4 sources

• Compare

match or

input

capture 1A

• Compare

match or

input

capture 1B

• Overflow

• Underflow

4 sources

• Compare

match or

input

capture 2A

• Compare

match or

input

capture 2B

• Overflow

• Underflow

5 sources

• Compare

match or

input

capture 3A

• Compare

match or

input

capture 3B

• Compare

match or

input

capture 3C

• Compare

match or

input

capture 3D

• Overflow

4 sources

• Compare

match or

input

capture 4A

• Compare

match or

input

capture 4B

• Overflow

• Underflow

4 sources

• Compare

match or

input

capture 5A

• Compare

match or

input

capture 5B

• Overflow

• Underflow

Legend

: Possible

— : Not possible

283

10.1.2 Block Diagram

Figure 10-1 shows a block diagram of the TPU.

Channel 3

TMDR

TIORL

TSR

TCR

TIORH

TIER

TGRA

TCNT

TGRB

TGRC

TGRD

Channel 4

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Control logic TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Control logic for channels 3 to 5

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

TGRC

Channel 1

TMDR

TSR

TCR

TIOR

TIER

TGRA

TCNT

TGRB

Channel 0

TMDR

TSR

TCR

TIORH

TIER

Control logic for channels 0 to 2

TGRA

TCNT

TGRB

TGRD

TSYRTSTR

Input/output pins

TIOCA3

TIOCB3

TIOCC3

TIOCD3

TIOCA4

TIOCB4

TIOCA5

TIOCB5

Clock input

ø/1

ø/4

ø/16

ø/64

ø/256

ø/1024

ø/4096

TCLKA

TCLKB

TCLKC

TCLKD

Input/output pins

TIOCA0

TIOCB0

TIOCC0

TIOCD0

TIOCA1

TIOCB1

TIOCA2

TIOCB2

Interrupt request signals

Channel 3:

Channel 4:

Channel 5:

Interrupt request signals

Channel 0:

Channel 1:

Channel 2:

Internal data bus

PPG output trigger signal

A/D converter convertion start signal

TIORL

Module data bus

TGI3A

TGI3B

TGI3C

TGI3D

TCI3V

TGI4A

TGI4B

TCI4V

TCI4U

TGI5A

TGI5B

TCI5V

TCI5U

TGI0A

TGI0B

TGI0C

TGI0D

TCI0V

TGI1A

TGI1B

TCI1V

TCI1U

TGI2A

TGI2B

TCI2V

TCI2U

Channel 3:

Channel 4:

Channel 5:

Internal clock:

External clock:

Channel 0:

Channel 1:

Channel 2:

Legend

TSTR: Timer start register

TSYR: Timer synchro register

TCR: Timer control register

TMDR: Timer mode register

TIOR (H, L): Timer I/O control registers (H, L)

TIER: Timer interrupt enable register

TSR: Timer status register

TGR (A, B, C, D): Timer general registers (A, B, C, D)

Channel 2 Common Channel 5

Bus interface

Figure 10-1 Block Diagram of TPU

284

10.1.3 Pin Configuration

Table 10-2 summarizes the TPU pins.

Table 10-2 TPU Pins

Channel Name Symbol I/O Function

All Clock input A TCLKA Input External clock A input pin

(Channel 1 and 5 phase counting mode A

phase input)

Clock input B TCLKB Input External clock B input pin

(Channel 1 and 5 phase counting mode B

phase input)

Clock input C TCLKC Input External clock C input pin

(Channel 2 and 4 phase counting mode A

phase input)

Clock input D TCLKD Input External clock D input pin

(Channel 2 and 4 phase counting mode B

phase input)

0 Input capture/out

compare match A0 TIOCA0 I/O TGR0A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B0 TIOCB0 I/O TGR0B input capture input/output compare

output/PWM output pin

Input capture/out

compare match C0 TIOCC0 I/O TGR0C input capture input/output compare

output/PWM output pin

Input capture/out

compare match D0 TIOCD0 I/O TGR0D input capture input/output compare

output/PWM output pin

1 Input capture/out

compare match A1 TIOCA1 I/O TGR1A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B1 TIOCB1 I/O TGR1B input capture input/output compare

output/PWM output pin

2 Input capture/out

compare match A2 TIOCA2 I/O TGR2A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B2 TIOCB2 I/O TGR2B input capture input/output compare

output/PWM output pin

285

Channel Name Symbol I/O Function

3 Input capture/out

compare match A3 TIOCA3 I/O TGR3A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B3 TIOCB3 I/O TGR3B input capture input/output compare

output/PWM output pin

Input capture/out

compare match C3 TIOCC3 I/O TGR3C input capture input/output compare

output/PWM output pin

Input capture/out

compare match D3 TIOCD3 I/O TGR3D input capture input/output compare

output/PWM output pin

4 Input capture/out

compare match A4 TIOCA4 I/O TGR4A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B4 TIOCB4 I/O TGR4B input capture input/output compare

output/PWM output pin

5 Input capture/out

compare match A5 TIOCA5 I/O TGR5A input capture input/output compare

output/PWM output pin

Input capture/out

compare match B5 TIOCB5 I/O TGR5B input capture input/output compare

output/PWM output pin

286

10.1.4 Register Configuration

Table 10-3 summarizes the TPU registers.

Table 10-3 TPU Registers

Channel Name Abbreviation R/W Initial Value Address*1

0 Timer control register 0 TCR0 R/W H'00 H'FF10

Timer mode register 0 TMDR0 R/W H'C0 H'FF11

Timer I/O control register 0H TIOR0H R/W H'00 H'FF12

Timer I/O control register 0L TIOR0L R/W H'00 H'FF13

Timer interrupt enable register 0 TIER0 R/W H'40 H'FF14

Timer status register 0 TSR0 R/(W)*2H'C0 H'FF15

Timer counter 0 TCNT0 R/W H'0000 H'FF16

Timer general register 0A TGR0A R/W H'FFFF H'FF18

Timer general register 0B TGR0B R/W H'FFFF H'FF1A

Timer general register 0C TGR0C R/W H'FFFF H'FF1C

Timer general register 0D TGR0D R/W H'FFFF H'FF1E

1 Timer control register 1 TCR1 R/W H'00 H'FF20

Timer mode register 1 TMDR1 R/W H'C0 H'FF21

Timer I/O control register 1 TIOR1 R/W H'00 H'FF22

Timer interrupt enable register 1 TIER1 R/W H'40 H'FF24

Timer status register 1 TSR1 R/(W)*2H'C0 H'FF25

Timer counter 1 TCNT1 R/W H'0000 H'FF26

Timer general register 1A TGR1A R/W H'FFFF H'FF28

Timer general register 1B TGR1B R/W H'FFFF H'FF2A

2 Timer control register 2 TCR2 R/W H'00 H'FF30

Timer mode register 2 TMDR2 R/W H'C0 H'FF31

Timer I/O control register 2 TIOR2 R/W H'00 H'FF32

Timer interrupt enable register 2 TIER2 R/W H'40 H'FF34

Timer status register 2 TSR2 R/(W)*2H'C0 H'FF35

Timer counter 2 TCNT2 R/W H'0000 H'FF36

Timer general register 2A TGR2A R/W H'FFFF H'FF38

Timer general register 2B TGR2B R/W H'FFFF H'FF3A

287

Channel Name Abbreviation R/W Initial Value Address*1

3 Timer control register 3 TCR3 R/W H'00 H'FE80

Timer mode register 3 TMDR3 R/W H'C0 H'FE81

Timer I/O control register 3H TIOR3H R/W H'00 H'FE82

Timer I/O control register 3L TIOR3L R/W H'00 H'FE83

Timer interrupt enable register 3 TIER3 R/W H'40 H'FE84

Timer status register 3 TSR3 R/(W)*2H'C0 H'FE85

Timer counter 3 TCNT3 R/W H'0000 H'FE86

Timer general register 3A TGR3A R/W H'FFFF H'FE88

Timer general register 3B TGR3B R/W H'FFFF H'FE8A

Timer general register 3C TGR3C R/W H'FFFF H'FE8C

Timer general register 3D TGR3D R/W H'FFFF H'FE8E

4 Timer control register 4 TCR4 R/W H'00 H'FE90

Timer mode register 4 TMDR4 R/W H'C0 H'FE91

Timer I/O control register 4 TIOR4 R/W H'00 H'FE92

Timer interrupt enable register 4 TIER4 R/W H'40 H'FE94

Timer status register 4 TSR4 R/(W)*2H'C0 H'FE95

Timer counter 4 TCNT4 R/W H'0000 H'FE96

Timer general register 4A TGR4A R/W H'FFFF H'FE98

Timer general register 4B TGR4B R/W H'FFFF H'FE9A

5 Timer control register 5 TCR5 R/W H'00 H'FEA0

Timer mode register 5 TMDR5 R/W H'C0 H'FEA1

Timer I/O control register 5 TIOR5 R/W H'00 H'FEA2

Timer interrupt enable register 5 TIER5 R/W H'40 H'FEA4

Timer status register 5 TSR5 R/(W)*2H'C0 H'FEA5

Timer counter 5 TCNT5 R/W H'0000 H'FEA6

Timer general register 5A TGR5A R/W H'FFFF H'FEA8

Timer general register 5B TGR5B R/W H'FFFF H'FEAA

All Timer start register TSTR R/W H'00 H'FEB0

Timer synchro register TSYR R/W H'00 H'FEB1

Module stop control register A MSTPCRA R/W H'3F H'FDE8

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, for flag clearing.

288

10.2 Register Descriptions

10.2.1 Timer Control Register (TCR)

Channel 0: TCR0

Channel 3: TCR3

Bit:76543210

CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Channel 1: TCR1

Channel 2: TCR2

Channel 4: TCR4

Channel 5: TCR5

Bit:76543210

— CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0

Initial value : 0 0 0 0 0 0 0 0

R/W : — R/W R/W R/W R/W R/W R/W R/W

The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR

registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and

in hardware standby mode.

TCR register settings should be made only when TCNT operation is stopped.

289

Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter

clearing source.

Channel Bit 7

CCLR2 Bit 6

CCLR1 Bit 5

CCLR0 Description

0, 3 0 0 0 TCNT clearing disabled (Initial value)

1 TCNT cleared by TGRA compare match/input

capture

1 0 TCNT cleared by TGRB compare match/input

capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*1

1 0 0 TCNT clearing disabled

1 TCNT cleared by TGRC compare match/input

capture*2

1 0 TCNT cleared by TGRD compare match/input

capture*2

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*1

Channel Bit 7

Reserved*3Bit 6

CCLR1 Bit 5

CCLR0 Description

1, 2, 4, 5 0 0 0 TCNT clearing disabled (Initial value)

1 TCNT cleared by TGRA compare match/input

capture

1 0 TCNT cleared by TGRB compare match/input

capture

1 TCNT cleared by counter clearing for another

channel performing synchronous clearing/

synchronous operation*1

Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.

2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the

buffer register setting has priority, and compare match/input capture does not occur.

3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be

modified.

290

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.

When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both

edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is

ignored and the phase counting mode setting has priority.

Bit 4

CKEG1 Bit 3

CKEG0 Description

0 0 Count at rising edge (Initial value)

1 Count at falling edge

1 — Count at both edges

Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is

ignored if the input clock is ø/1, or when overflow/underflow of another channel is selected.

Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter

clock. The clock source can be selected independently for each channel. Table 10-4 shows the

clock sources that can be set for each channel.

Table 10-4 TPU Clock Sources

Internal Clock External Clock

Overflow/

Underflow

on Another

Channel ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096 TCLKA TCLKB TCLKC TCLKD Channel

Legend

: Setting

Blank : No setting

291

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

0000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 External clock: counts on TCLKD pin input

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

1000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 Internal clock: counts on ø/256

1 Counts on TCNT2 overflow/underflow

Note: This setting is ignored when channel 1 is in phase counting mode.

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

2000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKB pin input

1 0 External clock: counts on TCLKC pin input

1 Internal clock: counts on ø/1024

Note: This setting is ignored when channel 2 is in phase counting mode.

292

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

3000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 Internal clock: counts on ø/1024

1 0 Internal clock: counts on ø/256

1 Internal clock: counts on ø/4096

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

4000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on ø/1024

1 Counts on TCNT5 overflow/underflow

Note: This setting is ignored when channel 4 is in phase counting mode.

Channel Bit 2

TPSC2 Bit 1

TPSC1 Bit 0

TPSC0 Description

5000Internal clock: counts on ø/1 (Initial value)

1 Internal clock: counts on ø/4

1 0 Internal clock: counts on ø/16

1 Internal clock: counts on ø/64

1 0 0 External clock: counts on TCLKA pin input

1 External clock: counts on TCLKC pin input

1 0 Internal clock: counts on ø/256

1 External clock: counts on TCLKD pin input

Note: This setting is ignored when channel 5 is in phase counting mode.

293

10.2.2 Timer Mode Register (TMDR)

Channel 0: TMDR0

Channel 3: TMDR3

Bit:76543210

— — BFB BFA MD3 MD2 MD1 MD0

Initial value : 1 1 0 0 0 0 0 0

R/W : — — R/W R/W R/W R/W R/W R/W

Channel 1: TMDR1

Channel 2: TMDR2

Channel 4: TMDR4

Channel 5: TMDR5

Bit:76543210

— — — — MD3 MD2 MD1 MD0

Initial value : 1 1 0 0 0 0 0 0

R/W : — — — — R/W R/W R/W R/W

The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode

for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers

are initialized to H'C0 by a reset, and in hardware standby mode.

TMDR register settings should be made only when TCNT operation is stopped.

Bits 7 and 6—Reserved: These bits are always read as 1 and cannot be modified.

Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or

TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer

In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and

cannot be modified.

Bit 5

BFB Description

0 TGRB operates normally (Initial value)

1 TGRB and TGRD used together for buffer operation

294

Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or

TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer

In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot

be modified.

Bit 4

BFA Description

0 TGRA operates normally (Initial value)

1 TGRA and TGRC used together for buffer operation

Bits 3 to 0—Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode.

Bit 3

MD3*1Bit 2

MD2*2Bit 1

MD1 Bit 0

MD0 Description

0000Normal operation (Initial value)

1 Reserved

1 0 PWM mode 1

1 PWM mode 2

1 0 0 Phase counting mode 1

1 Phase counting mode 2

1 0 Phase counting mode 3

1 Phase counting mode 4

1***—

*: Don’t care

Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.

2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always

be written to MD2.

295

10.2.3 Timer I/O Control Register (TIOR)

Channel 0: TIOR0H

Channel 1: TIOR1

Channel 2: TIOR2

Channel 3: TIOR3H

Channel 4: TIOR4

Channel 5: TIOR5

Bit:76543210

IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Channel 0: TIOR0L

Channel 3: TIOR3L

Bit:76543210

IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the

The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR

registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR

registers are initialized to H'00 by a reset, and in hardware standby mode.

Care is required since TIOR is affected by the TMDR setting. The initial output specified by

TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in

PWM mode 2, the output at the point at which the counter is cleared to 0 is specified.

296

Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0)

I/O Control D3 to D0 (IOD3 to IOD0):

Bits IOB3 to IOB0 specify the function of TGRB.

Bits IOD3 to IOD0 specify the function of TGRD.

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

0 0000 TGR0B Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0B

is input

capture

Capture input

source is

TIOCB0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/count clock

Input capture at TCNT1

count- up/count-down*1

*: Don’t care

297

Channel Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 Description

0 0000 TGR0D Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0D

is input

capture

Capture input

source is

TIOCD0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/count clock

Input capture at TCNT1

count-up/count-down*1

*: Don’t care

Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1

count clock, this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

298

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

1 0000 TGR1B Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR1B

is input

capture

Capture input

source is

TIOCB1 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR0C

compare match/

input capture

Input capture at generation of

TGR0C compare match/input

capture

*: Don’t care

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

2 0000 TGR2B Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR2B

is input

capture

Capture input

source is

TIOCB2 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

299

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

3 0000 TGR3B Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3B

is input

capture

Capture input

source is

TIOCB3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down*1

*: Don’t care

300

Channel Bit 7

IOD3 Bit 6

IOD2 Bit 5

IOD1 Bit 4

IOD0 Description

3 0000 TGR3D Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3D

is input

capture

Capture input

source is

TIOCD3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down*1

*: Don’t care

Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4

count clock, this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

301

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

4 0000 TGR4B Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR4B

is input

capture

Capture input

source is

TIOCB4 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR3C

compare match/

input capture

Input capture at generation of

TGR3C compare match/

input capture

*: Don’t care

Channel Bit 7

IOB3 Bit 6

IOB2 Bit 5

IOB1 Bit 4

IOB0 Description

5 0000 TGR5B Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR5B

is input

capture

Capture input

source is

TIOCB5 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

302

Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0)

I/O Control C3 to C0 (IOC3 to IOC0):

IOA3 to IOA0 specify the function of TGRA.

IOC3 to IOC0 specify the function of TGRC.

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

0 0000 TGR0A Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0A

is input

capture

Capture input

source is

TIOCA0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/ count clock

Input capture at TCNT1

count-up/count-down

*: Don’t care

303

Channel Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 Description

0 0000 TGR0C Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR0C

is input

capture

Capture input

source is

TIOCC0 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

1/count clock

Input capture at TCNT1

count-up/count-down

*: Don’t care

Note: 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

304

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

1 0000 TGR1A Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR1A

is input

capture

Capture input

source is

TIOCA1 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR0A

compare match/

input capture

Input capture at generation of

channel 0/TGR0A compare

match/input capture

*: Don’t care

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

2 0000 TGR2A Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR2A

is input

capture

Capture input

source is

TIOCA2 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

305

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

3 0000 TGR3A Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3A

is input

capture

Capture input

source is

TIOCA3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down

*: Don’t care

306

Channel Bit 3

IOC3 Bit 2

IOC2 Bit 1

IOC1 Bit 0

IOC0 Description

3 0000 TGR3C Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR3C

is input

capture

Capture input

source is

TIOCC3 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is channel

4/count clock

Input capture at TCNT4

count-up/count-down

*: Don’t care

Note: 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

307

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

4 0000 TGR4A Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

100

TGR4A

is input

capture

Capture input

source is

TIOCA4 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

1** Capture input

source is TGR3A

compare match/

input capture

Input capture at generation of

TGR3A compare match/input

capture

*: Don’t care

Channel Bit 3

IOA3 Bit 2

IOA2 Bit 1

IOA1 Bit 0

IOA0 Description

5 0000 TGR5A Output disabled (Initial value)

is output

compare

Initial output is 0

output 0 output at compare match

1 output at compare match

Toggle output at compare

match

1 0 0 Output disabled

1 Initial output is 1 0 output at compare match

10 output 1 output at compare match

1 Toggle output at compare

match

1*0

TGR5A

is input

capture

Capture input

source is

TIOCA5 pin

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

*: Don’t care

308

10.2.4 Timer Interrupt Enable Register (TIER)

Channel 0: TIER0

Channel 3: TIER3

Bit:76543210

TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA

Initial value : 0 1 0 0 0 0 0 0

R/W : R/W — — R/W R/W R/W R/W R/W

Channel 1: TIER1

Channel 2: TIER2

Channel 4: TIER4

Channel 5: TIER5

Bit:76543210

TTGE — TCIEU TCIEV — — TGIEB TGIEA

Initial value : 0 1 0 0 0 0 0 0

R/W : R/W — R/W R/W — — R/W R/W

The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for

each channel. The TPU has six TIER registers, one for each channel. The TIER registers are

initialized to H'40 by a reset, and in hardware standby mode.

309

Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D

conversion start requests by TGRA input capture/compare match.

Bit 7

TTGE Description

0 A/D conversion start request generation disabled (Initial value)

1 A/D conversion start request generation enabled

Bit 6—Reserved: This bit is always read as 1 and cannot be modified.

Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by

the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCIEU Description

0 Interrupt requests (TCIU) by TCFU disabled (Initial value)

1 Interrupt requests (TCIU) by TCFU enabled

Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by

the TCFV flag when the TCFV flag in TSR is set to 1.

Bit 4

TCIEV Description

0 Interrupt requests (TCIV) by TCFV disabled (Initial value)

1 Interrupt requests (TCIV) by TCFV enabled

Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the

TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.

Bit 3

TGIED Description

0 Interrupt requests (TGID) by TGFD bit disabled (Initial value)

1 Interrupt requests (TGID) by TGFD bit enabled

310

Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the

TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.

Bit 2

TGIEC Description

0 Interrupt requests (TGIC) by TGFC bit disabled (Initial value)

1 Interrupt requests (TGIC) by TGFC bit enabled

Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the

TGFB bit when the TGFB bit in TSR is set to 1.

Bit 1

TGIEB Description

0 Interrupt requests (TGIB) by TGFB bit disabled (Initial value)

1 Interrupt requests (TGIB) by TGFB bit enabled

Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the

TGFA bit when the TGFA bit in TSR is set to 1.

Bit 0

TGIEA Description

0 Interrupt requests (TGIA) by TGFA bit disabled (Initial value)

1 Interrupt requests (TGIA) by TGFA bit enabled

311

10.2.5 Timer Status Register (TSR)

Channel 0: TSR0

Channel 3: TSR3

Bit:76543210

— — — TCFV TGFD TGFC TGFB TGFA

Initial value : 1 1 0 0 0 0 0 0

R/W : — — — R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: *Only 0 can be written, for flag clearing.

Channel 1: TSR1

Channel 2: TSR2

Channel 4: TSR4

Channel 5: TSR5

Bit:76543210

TCFD — TCFU TCFV — — TGFB TGFA

Initial value : 1 1 0 0 0 0 0 0

R/W : R — R/(W)*R/(W)*— — R/(W)*R/(W)*

Note: *Only 0 can be written, for flag clearing.

The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR

registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in

hardware standby mode.

312

Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT

counts in channels 1, 2, 4, and 5.

In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.

Bit 7

TCFD Description

0 TCNT counts down

1 TCNT counts up (Initial value)

Bit 6—Reserved: This bit is always read as 1 and cannot be modified.

Bit 5—Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred

when channels 1, 2, 4, and 5 are set to phase counting mode.

In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified.

Bit 5

TCFU Description

0 [Clearing condition] (Initial value)

When 0 is written to TCFU after reading TCFU = 1

1 [Setting condition]

When the TCNT value underflows (changes from H'0000 to H'FFFF)

Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred.

Bit 4

TCFV Description

0 [Clearing condition] (Initial value)

When 0 is written to TCFV after reading TCFV = 1

1 [Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000 )

313

Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the

occurrence of TGRD input capture or compare match in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.

Bit 3

TGFD Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFD after reading TGFD = 1

1 [Setting conditions]

• When TCNT = TGRD while TGRD is functioning as output compare register

• When TCNT value is transferred to TGRD by input capture signal while TGRD is

functioning as input capture register

Bit 2—Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the

occurrence of TGRC input capture or compare match in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.

Bit 2

TGFC Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFC after reading TGFC = 1

1 [Setting conditions]

• When TCNT = TGRC while TGRC is functioning as output compare register

• When TCNT value is transferred to TGRC by input capture signal while TGRC is

functioning as input capture register

314

Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the

occurrence of TGRB input capture or compare match.

Bit 1

TGFB Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFB after reading TGFB = 1

1 [Setting conditions]

• When TCNT = TGRB while TGRB is functioning as output compare register

• When TCNT value is transferred to TGRB by input capture signal while TGRB is

functioning as input capture register

Bit 0—Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the

occurrence of TGRA input capture or compare match.

Bit 0

TGFA Description

0 [Clearing conditions] (Initial value)

• When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0

• When 0 is written to TGFA after reading TGFA = 1

1 [Setting conditions]

• When TCNT = TGRA while TGRA is functioning as output compare register

• When TCNT value is transferred to TGRA by input capture signal while TGRA is

functioning as input capture register

315

10.2.6 Timer Counter (TCNT)

Channel 0: TCNT0 (up-counter)

Channel 1: TCNT1 (up/down-counter*)

Channel 2: TCNT2 (up/down-counter*)

Channel 3: TCNT3 (up-counter)

Channel 4: TCNT4 (up/down-counter*)

Channel 5: TCNT5 (up/down-counter*)

Bit :1514131211109876543210

Initial value : 0 0 0 0000000000000

R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Note: *These counters can be used as up/down-counters only in phase counting mode or when

counting overflow/underflow on another channel. In other cases they function as up-

counters.

The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel.

The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.

The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit

unit.

316

10.2.7 Timer General Register (TGR)

Bit :1514131211109876543210

Initial value : 1 1 1 1111111111111

R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

The TGR registers are 16-bit registers with a dual function as output compare and input capture

registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels

1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as

buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby

mode.

The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.

Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.

317

10.2.8 Timer Start Register (TSTR)

Bit:76543210

— — CST5 CST4 CST3 CST2 CST1 CST0

Initial value : 0 0 0 0 0 0 0 0

R/W : — — R/W R/W R/W R/W R/W R/W

TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.

TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating

mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

Bits 7 and 6—Reserved: Should always be written with 0.

Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for

TCNT.

Bit n

CSTn Description

0 TCNTn count operation is stopped (Initial value)

1 TCNTn performs count operation n = 5 to 0

Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the

counter stops but the TIOC pin output compare output level is retained. If TIOR is written to

when the CST bit is cleared to 0, the pin output level will be changed to the set initial output

value.

318

10.2.9 Timer Synchro Register (TSYR)

Bit:76543210

— — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0

Initial value : 0 0 0 0 0 0 0 0

R/W : — — R/W R/W R/W R/W R/W R/W

TSYR is an 8-bit readable/writable register that selects independent operation or synchronous

operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when

the corresponding bit in TSYR is set to 1.

TSYR is initialized to H'00 by a reset, and in hardware standby mode.

Bits 7 and 6—Reserved: Should always be written with 0.

Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is

independent of or synchronized with other channels.

When synchronous operation is selected, synchronous presetting of multiple channels*1, and

synchronous clearing through counter clearing on another channel*2 are possible.

Bit n

SYNCn Description

0 TCNTn operates independently (TCNT presetting/clearing is unrelated to

other channels) (Initial value)

1 TCNTn performs synchronous operation

TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0

Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.

2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source

must also be set by means of bits CCLR2 to CCLR0 in TCR.

319

10.2.10 Module Stop Control Register A (MSTPCRA)

Bit:76543210

MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

Initial value : 0 0 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRA is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle

and a transition is made to module stop mode. Registers cannot be read or written to in module

stop mode. For details, see section 20.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 5—Module Stop (MSTPA5): Specifies the TPU module stop mode.

Bit 5

MSTPA5 Description

0 TPU module stop mode cleared

1 TPU module stop mode set (Initial value)

320

10.3 Interface to Bus Master

10.3.1 16-Bit Registers

TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these

registers can be read and written to in 16-bit units.

These registers cannot be read or written to in 8-bit units; 16-bit access must always be used.

An example of 16-bit register access operation is shown in figure 10-2.

Bus interface

Internal data bus

Bus

master Module

data bus

TCNTH TCNTL

Figure 10-2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)]

10.3.2 8-Bit Registers

Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these

registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit

units.

321

Examples of 8-bit register access operation are shown in figures 10-3 to 10-5.

Bus interface

Internal data bus

LModule

data bus

TCR

Bus

master

Figure 10-3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]

Bus interface

Internal data bus

LModule

data bus

TMDR

Bus

master

Figure 10-4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]

Bus interface

Internal data bus

LModule

data bus

TCR TMDR

Bus

master

Figure 10-5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]

322

10.4 Operation

10.4.1 Overview

Operation in each mode is outlined below.

Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting,

and is also capable of free-running operation, synchronous counting, and external event counting.

Each TGR can be used as an input capture register or output compare register.

Synchronous Operation: When synchronous operation is designated for a channel, TCNT for

that channel performs synchronous presetting. That is, when TCNT for a channel designated for

synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at

the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer

synchronization bits in TSYR for channels designated for synchronous operation.

Buffer Operation

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the relevant channel is

transferred to TGR.

• When TGR is an input capture register

When input capture occurs, the value in TCNT is transfer to TGR and the value previously

held in TGR is transferred to the buffer register.

Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4

counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32-

bit counter.

PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of

TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the

setting of each TGR register.

Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the

phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When

phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT

performs up- or down-counting.

This can be used for two-phase encoder pulse input.

323

10.4.2 Basic Functions

Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for

the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic

counter, and so on.

• Example of count operation setting procedure

Figure 10-6 shows an example of the count operation setting procedure.

Select counter clock

Operation selection

Select counter clearing source

Periodic counter

Set period

Start count operation

[1]

[2]

[4]

[3]

[5]

Free-running counter

Start count operation

<Free-running counter>

[5]

[1]

[2]

[3]

[4]

[5]

Select output compare register

Select the counter

clock with bits

TPSC2 to TPSC0 in

TCR. At the same

time, select the

input clock edge

with bits CKEG1

and CKEG0 in TCR.

For periodic counter

operation, select the

TGR to be used as

the TCNT clearing

source with bits

CCLR2 to CCLR0 in

TCR.

Designate the TGR

selected in [2] as an

output compare

TIOR.

Set the periodic

counter cycle in the

TGR selected in [2].

Set the CST bit in

TSTR to 1 to start

the counter

operation.

Figure 10-6 Example of Counter Operation Setting Procedure

324

• Free-running count operation and periodic count operation

Immediately after a reset, the TPU’s TCNT counters are all designated as free-running

counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-

count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000),

the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at

this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from

H'0000.

Figure 10-7 illustrates free-running counter operation.

TCNT value

H'FFFF

H'0000

CST bit

TCFV

Time

Figure 10-7 Free-Running Counter Operation

When compare match is selected as the TCNT clearing source, the TCNT counter for the

relevant channel performs periodic count operation. The TGR register for setting the period is

designated as an output compare register, and counter clearing by compare match is selected

by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts

up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When

the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared

to H'0000.

If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an

interrupt. After a compare match, TCNT starts counting up again from H'0000.

325

Figure 10-8 illustrates periodic counter operation.

TCNT value

TGR

H'0000

CST bit

TGF

Time

Counter cleared by TGR

compare match

Flag cleared by software or

DTC activation

Figure 10-8 Periodic Counter Operation

Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the

corresponding output pin using compare match.

• Example of setting procedure for waveform output by compare match

Figure 10-9 shows an example of the setting procedure for waveform output by compare match

Select waveform output mode

Output selection

Set output timing

Start count operation

[1]

[2]

[3]

[1] Select initial value 0 output or 1 output, and

compare match output value 0 output, 1 output,

or toggle output, by means of TIOR. The set

initial value is output at the TIOC pin until the

first compare match occurs.

[2] Set the timing for compare match generation in

TGR.

[3] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-9 Example Of Setting Procedure For Waveform Output By Compare Match

326

• Examples of waveform output operation

Figure 10-10 shows an example of 0 output/1 output.

In this example TCNT has been designated as a free-running counter, and settings have been

made so that 1 is output by compare match A, and 0 is output by compare match B. When the

set level and the pin level coincide, the pin level does not change.

TCNT value

H'FFFF

H'0000

TIOCA

TIOCB

Time

TGRA

TGRB

No change No change

1 output

0 output

Figure 10-10 Example of 0 Output/1 Output Operation

Figure 10-11 shows an example of toggle output.

In this example TCNT has been designated as a periodic counter (with counter clearing

performed by compare match B), and settings have been made so that output is toggled by both

compare match A and compare match B.

TCNT value

H'FFFF

H'0000

TIOCB

TIOCA

Time

TGRB

TGRA

Toggle output

Counter cleared by TGRB compare match

Figure 10-11 Example of Toggle Output Operation

327

Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC

pin input edge.

Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3,

and 4, it is also possible to specify another channel’s counter input clock or compare match signal

as the input capture source.

Note: When another channel’s counter input clock is used as the input capture input for channels

0 and 3, ø/1 should not be selected as the counter input clock used for input capture input.

Input capture will not be generated if ø/1 is selected.

• Example of input capture operation setting procedure

Figure 10-12 shows an example of the input capture operation setting procedure.

Select input capture input

Input selection

Start count

[1]

[2]

[1] Designate TGR as an input capture register by

means of TIOR, and select rising edge, falling

edge, or both edges as the input capture source

and input signal edge.

[2] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-12 Example of Input Capture Operation Setting Procedure

328

• Example of input capture operation

Figure 10-13 shows an example of input capture operation.

In this example both rising and falling edges have been selected as the TIOCA pin input

capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,

and counter clearing by TGRB input capture has been designated for TCNT.

TCNT value

H'0180

H'0000

TIOCA

TGRA

Time

H'0010

H'0005

Counter cleared by TIOCB

input (falling edge)

H'0160

H'0005 H'0160 H'0010

TGRB H'0180

TIOCB

Figure 10-13 Example of Input Capture Operation

329

10.4.3 Synchronous Operation

In synchronous operation, the values in a number of TCNT counters can be rewritten

simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared

simultaneously by making the appropriate setting in TCR (synchronous clearing).

Synchronous operation enables TGR to be incremented with respect to a single time base.

Channels 0 to 5 can all be designated for synchronous operation.

Example of Synchronous Operation Setting Procedure: Figure 10-14 shows an example of the

synchronous operation setting procedure.

Set synchronous

operation

Synchronous operation

selection

Set TCNT

Synchronous presetting

[1]

[2]

Synchronous clearing

Select counter

clearing source

[3]

Start count [5]

Set synchronous

counter clearing

[4]

Start count [5]

Clearing

sourcegeneration

channel?

Yes

[1]

[2]

[3]

[4]

[5]

Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous

operation.

When the TCNT counter of any of the channels designated for synchronous operation is

written to, the same value is simultaneously written to the other TCNT counters.

Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,

etc.

Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing

source.

Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.

Figure 10-14 Example of Synchronous Operation Setting Procedure

330

Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation.

In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to

2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous

clearing has been set for the channel 1 and 2 counter clearing source.

Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this

time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed

for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle.

For details of PWM modes, see section 10.4.6, PWM Modes.

TCNT0 to TCNT2 values

H'0000

TIOC0A

TIOC1A

Time

TGR0B

Synchronous clearing by TGR0B compare match

TGR2A

TGR1A

TGR2B

TGR0A

TGR1B

TIOC2A

Figure 10-15 Example of Synchronous Operation

331

10.4.4 Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer

registers.

Buffer operation differs depending on whether TGR has been designated as an input capture

Table 10-5 shows the register combinations used in buffer operation.

Table 10-5 Register Combinations in Buffer Operation

Channel Timer General Register Buffer Register

0 TGR0A TGR0C

TGR0B TGR0D

3 TGR3A TGR3C

TGR3B TGR3D

• When TGR is an output compare register

When a compare match occurs, the value in the buffer register for the corresponding channel is

transferred to the timer general register.

This operation is illustrated in figure 10-16.

Buffer register Timer general

Compare match signal

Figure 10-16 Compare Match Buffer Operation

332

• When TGR is an input capture register

When input capture occurs, the value in TCNT is transferred to TGR and the value previously

held in the timer general register is transferred to the buffer register.

This operation is illustrated in figure 10-17.

Buffer register Timer general

Input capture

signal

Figure 10-17 Input Capture Buffer Operation

Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer

operation setting procedure.

Select TGR function

Buffer operation

Set buffer operation

Start count

[1]

[2]

[3]

[1] Designate TGR as an input capture register or

output compare register by means of TIOR.

[2] Designate TGR for buffer operation with bits

BFA and BFB in TMDR.

[3] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-18 Example of Buffer Operation Setting Procedure

333

Examples of Buffer Operation

• When TGR is an output compare register

Figure 10-19 shows an operation example in which PWM mode 1 has been designated for

channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used

in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0

output at compare match B.

As buffer operation has been set, when compare match A occurs the output changes and the

value in buffer register TGRC is simultaneously transferred to timer general register TGRA.

This operation is repeated each time compare match A occurs.

For details of PWM modes, see section 10.4.6, PWM Modes.

TCNT value

TGR0B

H'0000

TGR0C

Time

TGR0A

H'0200 H'0520

TIOCA

H'0200

H'0450 H'0520

H'0450

TGR0A H'0450H'0200

Transfer

Figure 10-19 Example of Buffer Operation (1)

334

• When TGR is an input capture register

Figure 10-20 shows an operation example in which TGRA has been designated as an input

capture register, and buffer operation has been designated for TGRA and TGRC.

Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling

edges have been selected as the TIOCA pin input capture input edge.

As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of

input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.

TCNT value

H'09FB

H'0000

TGRC

Time

H'0532

TIOCA

TGRA H'0F07H'0532

H'0F07

H'0532

H'0F07

H'09FB

Figure 10-20 Example of Buffer Operation (2)

335

10.4.5 Cascaded Operation

In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit

counter.

This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow

of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR.

Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

Table 10-6 shows the register combinations used in cascaded operation.

Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid

and the counter operates independently in phase counting mode.

Table 10-6 Cascaded Combinations

Combination Upper 16 Bits Lower 16 Bits

Channels 1 and 2 TCNT1 TCNT2

Channels 4 and 5 TCNT4 TCNT5

Example of Cascaded Operation Setting Procedure: Figure 10-21 shows an example of the

setting procedure for cascaded operation.

Set cascading

Cascaded operation

Start count

[1]

[2]

[1] Set bits TPSC2 to TPSC0 in the channel 1

(channel 4) TCR to B’111 to select TCNT2

(TCNT5) overflow/underflow counting.

[2] Set the CST bit in TSTR for the upper and lower

channel to 1 to start the count operation.

Figure 10-21 Cascaded Operation Setting Procedure

336

Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon

TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated

as input capture registers, and TIOC pin rising edge has been selected.

When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of

the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.

TCNT2

clock

TCNT2 H'FFFF H'0000 H'0001

TIOCA1,

TIOCA2

TGR1A H'03A2

TGR2A H'0000

TCNT1

clock

TCNT1 H'03A1 H'03A2

Figure 10-22 Example of Cascaded Operation (1)

Figure 10-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been

set for TCNT1, and phase counting mode has been designated for channel 2.

TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow.

TCLKA

TCNT2 FFFD

TCNT1 0001

TCLKB

FFFE FFFF 0000 0001 0002 0001 0000 FFFF

0000 0000

Figure 10-23 Example of Cascaded Operation (2)

337

10.4.6 PWM Modes

In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be

selected as the output level in response to compare match of each TGR.

Designating TGR compare match as the counter clearing source enables the period to be set in that

also possible.

There are two PWM modes, as described below.

• PWM mode 1

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and

TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is

output from the TIOCA and TIOCC pins at compare matches A and C, and the output

specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B

and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired

TGRs are identical, the output value does not change when a compare match occurs.

In PWM mode 1, a maximum 8-phase PWM output is possible.

• PWM mode 2

PWM output is generated using one TGR as the cycle register and the others as duty registers.

The output specified in TIOR is performed by means of compare matches. Upon counter

clearing by a synchronization register compare match, the output value of each pin is the initial

value set in TIOR. If the set values of the cycle and duty registers are identical, the output

value does not change when a compare match occurs.

In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with

synchronous operation.

The correspondence between PWM output pins and registers is shown in table 10-7.

338

Table 10-7 PWM Output Registers and Output Pins

Output Pins

Channel Registers PWM Mode 1 PWM Mode 2

0 TGR0A TIOCA0 TIOCA0

TGR0B TIOCB0

TGR0C TIOCC0 TIOCC0

TGR0D TIOCD0

1 TGR1A TIOCA1 TIOCA1

TGR1B TIOCB1

2 TGR2A TIOCA2 TIOCA2

TGR2B TIOCB2

3 TGR3A TIOCA3 TIOCA3

TGR3B TIOCB3

TGR3C TIOCC3 TIOCC3

TGR3D TIOCD3

4 TGR4A TIOCA4 TIOCA4

TGR4B TIOCB4

5 TGR5A TIOCA5 TIOCA5

TGR5B TIOCB5

Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.

339

Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode

setting procedure.

Select counter clock

PWM mode

Select counter clearing source

Select waveform output level

[1]

[2]

[3]

Set TGR [4]

Set PWM mode [5]

Start count [6]

[1] Select the counter clock with bits TPSC2 to

TPSC0 in TCR. At the same time, select the

input clock edge with bits CKEG1 and CKEG0 in

TCR.

[2] Use bits CCLR2 to CCLR0 in TCR to select the

TGR to be used as the TCNT clearing source.

[3] Use TIOR to designate the TGR as an output

compare register, and select the initial value and

output value.

[4] Set the cycle in the TGR selected in [2], and set

the duty in the other the TGR.

[5] Select the PWM mode with bits MD3 to MD0 in

TMDR.

[6] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-24 Example of PWM Mode Setting Procedure

Examples of PWM Mode Operation: Figure 10-25 shows an example of PWM mode 1

operation.

In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA

initial output value and output value, and 1 is set as the TGRB output value.

In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as

the duty.

340

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

Counter cleared by

TGRA compare match

Figure 10-25 Example of PWM Mode Operation (1)

Figure 10-26 shows an example of PWM mode 2 operation.

In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match

is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output

value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM

waveform.

In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as

the duty.

TCNT value

TGR1B

H'0000

TIOCA0

Counter cleared by TGR1B

compare match

TGR1A

TGR0D

TGR0C

TGR0B

TGR0A

TIOCB0

TIOCC0

TIOCD0

TIOCA1

Time

Figure 10-26 Example of PWM Mode Operation (2)

341

Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM

mode.

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

0% duty

TGRB rewritten

TGRB

rewritten

TGRB rewritten

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty register

compare matches occur simultaneously

TCNT value

TGRA

H'0000

TIOCA

Time

TGRB

100% duty

TGRB rewritten

Output does not change when cycle register and duty

0% duty

Figure 10-27 Example of PWM Mode Operation (3)

342

10.4.7 Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and

TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.

When phase counting mode is set, an external clock is selected as the counter input clock and

TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits

CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of

TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be

used.

When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow

occurs while TCNT is counting down, the TCFU flag is set.

The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of

whether TCNT is counting up or down.

Table 10-8 shows the correspondence between external clock pins and channels.

Table 10-8 Phase Counting Mode Clock Input Pins

External Clock Pins

Channels A-Phase B-Phase

When channel 1 or 5 is set to phase counting mode TCLKA TCLKB

When channel 2 or 4 is set to phase counting mode TCLKC TCLKD

Example of Phase Counting Mode Setting Procedure: Figure 10-28 shows an example of the

phase counting mode setting procedure.

Select phase counting mode

Phase counting mode

Start count

[1]

[2]

[1] Select phase counting mode with bits MD3 to

MD0 in TMDR.

[2] Set the CST bit in TSTR to 1 to start the count

operation.

Figure 10-28 Example of Phase Counting Mode Setting Procedure

343

Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or

down according to the phase difference between two external clocks. There are four modes,

according to the count conditions.

• Phase counting mode 1

Figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9

summarizes the TCNT up/down-count conditions.

TCNT value

Time

Down-countUp-count

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Figure 10-29 Example of Phase Counting Mode 1 Operation

Table 10-9 Up/Down-Count Conditions in Phase Counting Mode 1

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

High level

High level Down-count

Low level

High level

Low level

Legend: Rising edge

: Falling edge

344

• Phase counting mode 2

Figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10

summarizes the TCNT up/down-count conditions.

TCNT value

Time

Down-countUp-count

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4)

TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4)

Figure 10-30 Example of Phase Counting Mode 2 Operation

Table 10-10 Up/Down-Count Conditions in Phase Counting Mode 2

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Don’t care

Low level Don’t care

High level Up-count

High level Don’t care

Low level Don’t care

High level Don’t care

Low level Down-count

Legend: Rising edge

: Falling edge

345

• Phase counting mode 3

Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11

summarizes the TCNT up/down-count conditions.

TCNT value

Time

Up-count

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Down-count

Figure 10-31 Example of Phase Counting Mode 3 Operation

Table 10-11 Up/Down-Count Conditions in Phase Counting Mode 3

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Don’t care

Low level Don’t care

High level Up-count

High level Down-count

Low level Don’t care

High level Don’t care

Low level Don’t care

Legend: Rising edge

: Falling edge

346

• Phase counting mode 4

Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12

summarizes the TCNT up/down-count conditions.

Time

TCLKA (channels 1 and 5)

TCLKC (channels 2 and 4)

TCLKB (channels 1 and 5)

TCLKD (channels 2 and 4)

Up-count Down-count

TCNT value

Figure 10-32 Example of Phase Counting Mode 4 Operation

Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4

TCLKA (Channels 1 and 5)

TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5)

TCLKD (Channels 2 and 4) Operation

High level Up-count

Low level

Low level Don’t care

High level

High level Down-count

Low level

High level Don’t care

Low level

Legend: Rising edge

: Falling edge

347

Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase

counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo

motor 2-phase encoder pulses in order to detect the position or speed.

Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input

to TCLKA and TCLKB.

Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C

are used for the compare match function, and are set with the speed control period and position

control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer

mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and

detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.

TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and

TGR0C compare matches are selected as the input capture source, and store the up/down-counter

values for the control periods.

This procedure enables accurate position/speed detection to be achieved.

348

TCNT1

TCNT0

Channel 1

TGR1A

(speed period capture)

TGR0A (speed control period)

TGR1B

(position period capture)

TGR0C

(position control period)

TGR0B (pulse width capture)

TGR0D (buffer operation)

Channel 0

TCLKA

TCLKB

Edge

detection

circuit

–

Figure 10-33 Phase Counting Mode Application Example

349

10.5 Interrupts

10.5.1 Interrupt Sources and Priorities

There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT

overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled

bit, allowing generation of interrupt request signals to be enabled or disabled individually.

When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the

corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The

interrupt request is cleared by clearing the status flag to 0.

Relative channel priorities can be changed by the interrupt controller, but the priority order within

a channel is fixed. For details, see section 5, Interrupt Controller.

Table 10-13 lists the TPU interrupt sources.

350

Table 10-13 TPU Interrupts

Channel Interrupt

Source Description DTC Activation Priority

0 TGI0A TGR0A input capture/compare match Possible High

TGI0B TGR0B input capture/compare match Possible

TGI0C TGR0C input capture/compare match Possible

TGI0D TGR0D input capture/compare match Possible

TCI0V TCNT0 overflow Not possible

1 TGI1A TGR1A input capture/compare match Possible

TGI1B TGR1B input capture/compare match Possible

TCI1V TCNT1 overflow Not possible

TCI1U TCNT1 underflow Not possible

2 TGI2A TGR2A input capture/compare match Possible

TGI2B TGR2B input capture/compare match Possible

TCI2V TCNT2 overflow Not possible

TCI2U TCNT2 underflow Not possible

3 TGI3A TGR3A input capture/compare match Possible

TGI3B TGR3B input capture/compare match Possible

TGI3C TGR3C input capture/compare match Possible

TGI3D TGR3D input capture/compare match Possible

TCI3V TCNT3 overflow Not possible

4 TGI4A TGR4A input capture/compare match Possible

TGI4B TGR4B input capture/compare match Possible

TCI4V TCNT4 overflow Not possible

TCI4U TCNT4 underflow Not possible

5 TGI5A TGR5A input capture/compare match Possible

TGI5B TGR5B input capture/compare match Possible

TCI5V TCNT5 overflow Not possible

TCI5U TCNT5 underflow Not possible Low

Note: This table shows the initial state immediately after a reset. The relative channel priorities

can be changed by the interrupt controller.

351

Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is

set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare

match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The

TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each

for channels 1, 2, 4, and 5.

Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the

TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt

request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for

each channel.

Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the

TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt

request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one

each for channels 1, 2, 4, and 5.

10.5.2 DTC Activation

The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For

details, see section 8, Data Transfer Controller.

A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,

four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

10.5.3 A/D Converter Activation

The A/D converter can be activated by the TGRA input capture/compare match for a channel.

If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a

TGRA input capture/compare match on a particular channel, a request to start A/D conversion is

sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D

converter side at this time, A/D conversion is started.

In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D

converter conversion start sources, one for each channel.

352

10.6 Operation Timing

10.6.1 Input/Output Timing

TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and

figure 10-35 shows TCNT count timing in external clock operation.

TCNT

input clock

Internal clock

N–1 N N+1 N+2

Falling edge Rising edge

Figure 10-34 Count Timing in Internal Clock Operation

TCNT

input clock

External clock

N–1 N N+1 N+2

Rising edge Falling edge

Falling edge

Figure 10-35 Count Timing in External Clock Operation

353

Output Compare Output Timing: A compare match signal is generated in the final state in

which TCNT and TGR match (the point at which the count value matched by TCNT is updated).

When a compare match signal is generated, the output value set in TIOR is output at the output

compare output pin. After a match between TCNT and TGR, the compare match signal is not

generated until the TCNT input clock is generated.

Figure 10-36 shows output compare output timing.

TGR

TCNT

input clock

N N+1

Compare

match signal

TIOC pin

Figure 10-36 Output Compare Output Timing

Input Capture Signal Timing: Figure 10-37 shows input capture signal timing.

TCNT

Input capture

input

N N+1 N+2

NN+2

TGR

Input capture

signal

Figure 10-37 Input Capture Input Signal Timing

354

Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the

timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows

the timing when counter clearing by input capture occurrence is specified.

TCNT

Counter

clear signal

Compare

match signal

TGR N

N H'0000

Figure 10-38 Counter Clear Timing (Compare Match)

TCNT

Counter clear

signal

Input capture

signal

TGR

N H'0000

Figure 10-39 Counter Clear Timing (Input Capture)

355

Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation.

TGRA,

TGRB

Compare

match signal

TCNT

TGRC,

TGRD

n n+1

Figure 10-40 Buffer Operation Timing (Compare Match)

TGRA,

TGRB

TCNT

Input capture

signal

TGRC,

TGRD

n N+1

N N+1

Figure 10-41 Buffer Operation Timing (Input Capture)

356

10.6.2 Interrupt Signal Timing

TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for

setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal

timing.

TGR

TCNT

TCNT input

clock

N N+1

Compare

match signal

TGF flag

TGI interrupt

Figure 10-42 TGI Interrupt Timing (Compare Match)

357

TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting

of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.

TGR

TCNT

Input capture

signal

TGF flag

TGI interrupt

Figure 10-43 TGI Interrupt Timing (Input Capture)

358

TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV

flag in TSR by overflow occurrence, and TCIV interrupt request signal timing.

Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and

TCIU interrupt request signal timing.

Overflow

signal

TCNT

(overflow)

TCNT input

clock

H'FFFF H'0000

TCFV flag

TCIV interrupt

Figure 10-44 TCIV Interrupt Setting Timing

Underflow signal

TCNT

(underflow)

TCNT

input clock

H'0000 H'FFFF

TCFU flag

TCIU interrupt

Figure 10-45 TCIU Interrupt Setting Timing

359

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing

0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10-46 shows the

timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag

clearing by the DTC.

Status flag

Write signal

Address

TSR address

Interrupt

request

signal

TSR write cycle

T1 T2

Figure 10-46 Timing for Status Flag Clearing by CPU

Interrupt

request

signal

Status flag

Address

Source address

DTC

read cycle

T1 T2

Destination

address

T1 T2

DTC

write cycle

Figure 10-47 Timing for Status Flag Clearing by DTC Activation

360

10.7 Usage Notes

Note that the kinds of operation and contention described below occur during TPU operation.

Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of

single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not

operate properly with a narrower pulse width.

In phase counting mode, the phase difference and overlap between the two input clocks must be at

least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10-48 shows the input clock

conditions in phase counting mode.

Overlap

Phase

differ-

ence

Phase

differ-

ence

Overlap

TCLKA

(TCLKC)

TCLKB

(TCLKD)

Pulse width Pulse width

Notes: Phase difference and overlap

Pulse width : 1.5 states or more

: 2.5 states or more

Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode

Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in

the final state in which it matches the TGR value (the point at which the count value matched by

TCNT is updated). Consequently, the actual counter frequency is given by the following formula:

f = ø

(N + 1)

Where f : Counter frequency

ø : Operating frequency

N : TGR set value

361

Contention between TCNT Write and Clear Operations: If the counter clear signal is

generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT

write is not performed.

Figure 10-49 shows the timing in this case.

Counter clear

signal

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

N H'0000

Figure 10-49 Contention between TCNT Write and Clear Operations

362

Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2

state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.

Figure 10-50 shows the timing in this case.

TCNT input

clock

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

N M

TCNT write data

Figure 10-50 Contention between TCNT Write and Increment Operations

363

Contention between TGR Write and Compare Match: If a compare match occurs in the T2

state of a TGR write cycle, the TGR write takes precedence and the compare match signal is

inhibited. A compare match does not occur even if the same value as before is written.

Figure 10-51 shows the timing in this case.

Compare

match signal

Write signal

Address

TGR address

TCNT

TGR write cycle

T1 T2

N M

TGR write data

TGR

N N+1

Inhibited

Figure 10-51 Contention between TGR Write and Compare Match

364

Contention between Buffer Register Write and Compare Match: If a compare match occurs in

the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the

data prior to the write.

Figure 10-52 shows the timing in this case.

Compare

match signal

Write signal

Address

Buffer register

address

Buffer

TGR write cycle

T1 T2

TGR

N M

Buffer register write data

Figure 10-52 Contention between Buffer Register Write and Compare Match

365

Contention between TGR Read and Input Capture: If the input capture signal is generated in

the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer.

Figure 10-53 shows the timing in this case.

Input capture

signal

Read signal

Address

TGR address

TGR

TGR read cycle

T1 T2

Internal

data bus

X M

Figure 10-53 Contention between TGR Read and Input Capture

366

Contention between TGR Write and Input Capture: If the input capture signal is generated in

the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to

TGR is not performed.

Figure 10-54 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

TGR write cycle

T1 T2

TGR

TGR address

Figure 10-54 Contention between TGR Write and Input Capture

367

Contention between Buffer Register Write and Input Capture: If the input capture signal is

generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the

write to the buffer register is not performed.

Figure 10-55 shows the timing in this case.

Input capture

signal

Write signal

Address

TCNT

Buffer register write cycle

T1 T2

TGR

Buffer

Buffer register

address

Figure 10-55 Contention between Buffer Register Write and Input Capture

368

Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and

counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing

takes precedence.

Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing

source, and H'FFFF is set in TGR.

Counter

clear signal

TCNT input

clock

TCNT

TGF

Disabled

TCFV

H'FFFF H'0000

Figure 10-56 Contention between Overflow and Counter Clearing

369

Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-

count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write

takes precedence and the TCFV/TCFU flag in TSR is not set.

Figure 10-57 shows the operation timing when there is contention between TCNT write and

overflow.

Write signal

Address

TCNT address

TCNT

TCNT write cycle

T1 T2

H'FFFF M

TCNT write data

TCFV flag

Figure 10-57 Contention between TCNT Write and Overflow

Multiplexing of I/O Pins: In the H8S/2626 Series and H8S/2623 Series, the TCLKA input pin is

multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the

TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.

When an external clock is input, compare match output should not be performed from a

multiplexed pin.

Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been

requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.

Interrupts should therefore be disabled before entering module stop mode.

370

371

Section 11 Programmable Pulse Generator (PPG)

11.1 Overview

The H8S/2626 Series and H8S/2623 Series have an on-chip programmable pulse generator (PPG)

that provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG

pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both

simultaneously and independently.

11.1.1 Features

PPG features are listed below.

• 8-bit output data

 Maximum 8-bit data can be output, and output can be enabled on a bit-by-bit basis

• Two output groups

 Output trigger signals can be selected in 4-bit groups to provide up to two different 4-bit

outputs

• Selectable output trigger signals

 Output trigger signals can be selected for each group from the compare match signals of

four TPU channels

• Non-overlap mode

 A non-overlap margin can be provided between pulse outputs

• Can operate together with the data transfer controller (DTC)

 The compare match signals selected as output trigger signals can activate the DTC for

sequential output of data without CPU intervention

• Settable inverted output

 Inverted data can be output for each group

• Module stop mode can be set

 As the initial setting, PPG operation is halted. Register access is enabled by exiting module

stop mode

372

11.1.2 Block Diagram

Figure 11-1 shows a block diagram of the PPG.

Compare match signals

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Legend : PPG output mode register

: PPG output control register

: Next data enable register H

: Next data enable register L

: Next data register H

: Next data register L

: Output data register H

: Output data register L

Internal

data bus

PMR

PCR

NDERH

NDERL

NDRH

NDRL

PODRH

PODRL

Pulse output

pins, group 3

Pulse output

pins, group 2

Pulse output

pins, group 1

Pulse output

pins, group 0

PODRH

PODRL

NDRH

NDRL

Control logic

NDERH

PMR

NDERL

PCR

Figure 11-1 Block Diagram of PPG

373

11.1.3 Pin Configuration

Table 11-1 summarizes the PPG pins.

Table 11-1 PPG Pins

Name Symbol I/O Function

Pulse output 8 PO8 Output Group 2 pulse output

Pulse output 9 PO9 Output

Pulse output 10 PO10 Output

Pulse output 11 PO11 Output

Pulse output 12 PO12 Output Group 3 pulse output

Pulse output 13 PO13 Output

Pulse output 14 PO14 Output

Pulse output 15 PO15 Output

374

11.1.4 Registers

Table 11-2 summarizes the PPG registers.

Table 11-2 PPG Registers

Name Abbreviation R/W Initial Value Address*1

PPG output control register PCR R/W H'FF H'FE26

PPG output mode register PMR R/W H'F0 H'FE27

Next data enable register H NDERH R/W H'00 H'FE28

Next data enable register L*4NDERL R/W H'00 H'FE29

Output data register H PODRH R/(W)*2H'00 H'FE2A

Output data register L*4PODRL R/(W)*2H'00 H'FE2B

Next data register H NDRH R/W H'00 H'FE2C*3

H'FE2E

Next data register L*4NDRL R/W H'00 H'FE2D*3

H'FE2F

Port 1 data direction register P1DDR W H'00 H'FE30

Module stop control register A MSTPCRA R/W H'3F H'FDE8

Notes: 1. Lower 16 bits of the address.

2. Bits used for pulse output cannot be written to.

3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR

setting, the NDRH address is H'FE2C. When the output triggers are different, the

NDRH address is H'FE2E for group 2 and H'FE2C for group 3

Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by

the PCR setting, the NDRL address is H'FE2D. When the output triggers are different,

the NDRL address is H'FE2F for group 0 and H'FE2D for group 1.

4. The H8S/2626 Series and H8S/2623 Series have no pins corresponding to PODRL

(pulse output groups 0 and 1).

375

11.2 Register Descriptions

11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)

NDERH

Bit:76543210

NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

NDERL

Bit:76543210

NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a

bit-by-bit basis.

If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically

transferred to the corresponding PODR bit when the TPU compare match event specified by PCR

occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from

NDR to PODR and the output value does not change.

NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They

are not initialized in software standby mode.

NDERH Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or

disable pulse output on a bit-by-bit basis.

Bits 7 to 0

NDER15 to NDER8 Description

0 Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not

transferred to POD15 to POD8) (Initial value)

1 Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred

to POD15 to POD8)

376

NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or

disable pulse output on a bit-by-bit basis.

Bits 7 to 0

NDER7 to NDER0 Description

0 Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not

transferred to POD7 to POD0) (Initial value)

1 Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to

POD7 to POD0)

11.2.2 Output Data Registers H and L (PODRH, PODRL)

PODRH

Bit:76543210

POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8

Initial value : 0 0 0 0 0 0 0 0

R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

PODRL

Bit:76543210

POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*

Note: *A bit that has been set for pulse output by NDER is read-only.

PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse

output. However, the H8S/2626 Series and H8S/2623 Series have no pins corresponding to

PODRL.

377

11.2.3 Next Data Registers H and L (NDRH, NDRL)

NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output.

During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in

PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH

and NDRL addresses differ depending on whether pulse output groups have the same output

trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access.

NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are

not initialized in software standby mode.

11.2.4 Notes on NDR Access

The NDRH and NDRL addresses differ depending on whether pulse output groups have the same

output trigger or different output triggers.

Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the

same compare match event, the NDRH address is H'FE2C. The upper 4 bits belong to group 3

and the lower 4 bits to group 2. Address H'FE2E consists entirely of reserved bits that cannot be

modified and are always read as 1.

Address H'FE2C

Bit:76543210

NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Address H'FE2E

Bit:76543210

————————

Initial value : 1 1 1 1 1 1 1 1

R/W:————————

If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address

is H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F

consists entirely of reserved bits that cannot be modified and are always read as 1. However, the

H8S/2626 Series and H8S/2623 Series have no output pins corresponding to pulse output groups 0

and 1.

378

Address H'FE2D

Bit:76543210

NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Address H'FE2F

Bit:76543210

————————

Initial value : 1 1 1 1 1 1 1 1

R/W:————————

Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by

different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FE2C and

the address of the lower 4 bits (group 2) is H'FE2E. Bits 3 to 0 of address H'FE2C and bits 7 to 4

of address H'FE2E are reserved bits that cannot be modified and are always read as 1.

Address H'FE2C

Bit:76543210

NDR15 NDR14 NDR13 NDR12 — — — —

Initial value : 0 0 0 0 1 1 1 1

R/W : R/W R/W R/W R/W — — — —

Address H'FE2E

Bit:76543210

— — — — NDR11 NDR10 NDR9 NDR8

Initial value : 1 1 1 1 0 0 0 0

R/W : — — — — R/W R/W R/W R/W

If pulse output groups 0 and 1 are triggered by different compare match event, the address of the

upper 4 bits in NDRL (group 1) is H'FE2D and the address of the lower 4 bits (group 0) is

H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that

cannot be modified and are always read as 1. However, the H8S/2626 Series and H8S/2623 Series

have no output pins corresponding to pulse output groups 0 and 1.

379

Address H'FE2D

Bit:76543210

NDR7 NDR6 NDR5 NDR4 — — — —

Initial value : 0 0 0 0 1 1 1 1

R/W : R/W R/W R/W R/W — — — —

Address H'FE2F

Bit:76543210

— — — — NDR3 NDR2 NDR1 NDR0

Initial value : 1 1 1 1 0 0 0 0

R/W : — — — — R/W R/W R/W R/W

11.2.5 PPG Output Control Register (PCR)

Bit:76543210

G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a

group-by-group basis.

PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits

select the compare match that triggers pulse output group 3 (pins PO15 to PO12).

Description

Bit 7

G3CMS1 Bit 6

G3CMS0 Output Trigger for Pulse Output Group 3

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

380

Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits

select the compare match that triggers pulse output group 2 (pins PO11 to PO8).

Description

Bit 5

G2CMS1 Bit 4

G2CMS0 Output Trigger for Pulse Output Group 2

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits

select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the

H8S/2626 Series and H8S/2623 Series have no output pins corresponding to pulse output group 1.

Description

Bit 3

G1CMS1 Bit 2

G1CMS0 Output Trigger for Pulse Output Group 1

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits

select the compare match that triggers pulse output group 0 (pins PO3 to PO0). However, the

H8S/2626 Series and H8S/2623 Series have no output pins corresponding to pulse output group 0.

Description

Bit 1

G0CMS1 Bit 0

G0CMS0 Output Trigger for Pulse Output Group 0

0 0 Compare match in TPU channel 0

1 Compare match in TPU channel 1

1 0 Compare match in TPU channel 2

1 Compare match in TPU channel 3 (Initial value)

381

11.2.6 PPG Output Mode Register (PMR)

Bit:76543210

G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV

Initial value : 1 1 1 1 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping

operation for each group.

The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB

and the non-overlap margin is set in TGRA. The output values change at compare match A and B.

For details, see section 11.3.4, Non-Overlapping Pulse Output.

PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output

group 3 (pins PO15 to PO12).

Bit 7

G3INV Description

0 Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH)

(Initial value)

Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output

group 2 (pins PO11 to PO8).

Bit 6

G2INV Description

0 Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH)

1 Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH)

(Initial value)

382

Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output

group 1 (pins PO7 to PO4). However, the H8S/2626 Series and H8S/2623 Series have no pins

corresponding to pulse output group 1.

Bit 5

G1INV Description

0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL)

(Initial value)

Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output

group 0 (pins PO3 to PO0). However, the H8S/2626 Series and H8S/2623 Series have no pins

corresponding to pulse output group 0.

Bit 4

G0INV Description

0 Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL)

1 Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL)

(Initial value)

Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse

output group 3 (pins PO15 to PO12).

Bit 3

G3NOV Description

0 Normal operation in pulse output group 3 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse

output group 2 (pins PO11 to PO8).

Bit 2

G2NOV Description

0 Normal operation in pulse output group 2 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

383

Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse

output group 1 (pins PO7 to PO4). However, the H8S/2626 Series and H8S/2623 Series have no

pins corresponding to pulse output group 1.

Bit 1

G1NOV Description

0 Normal operation in pulse output group 1 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse

output group 0 (pins PO3 to PO0). However, the H8S/2626 Series and H8S/2623 Series have no

pins corresponding to pulse output group 0.

Bit 0

G0NOV Description

0 Normal operation in pulse output group 0 (output values updated at compare match A

in the selected TPU channel) (Initial value)

1 Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at

compare match A or B in the selected TPU channel)

384

11.2.7 Port 1 Data Direction Register (P1DDR)

Bit:76543210

P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR

Initial value : 0 0 0 0 0 0 0 0

R/W:WWWWWWWW

P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the

pins of port 1.

Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must

be set to 1. For further information about P1DDR, see section 9.2, Port 1.

11.2.8 Module Stop Control Register A (MSTPCRA)

Bit:76543210

MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

Initial value : 0 0 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRA is a 16-bit readable/writable register that performs module stop mode control.

When the MSTPA3 bit in MSTPCRA is set to 1, PPG operation stops at the end of the bus cycle

and a transition is made to module stop mode. Registers cannot be read or written to in module

stop mode. For details, see section 20.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 3—Module Stop (MSTPA3): Specifies the PPG module stop mode.

Bit 3

MSTPA3 Description

0 PPG module stop mode cleared

1 PPG module stop mode set (Initial value)

385

11.3 Operation

11.3.1 Overview

PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In

this state the corresponding PODR contents are output.

When the compare match event specified by PCR occurs, the corresponding NDR bit contents are

transferred to PODR to update the output values.

Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating

conditions.

Output trigger signal

Pulse output pin Internal data bus

Normal output/inverted output



PODRQD

NDER

NDRQD

DDR

Figure 11-2 PPG Output Operation

Table 11-3 PPG Operating Conditions

NDER DDR Pin Function

0 0 Generic input port

1 Generic output port

1 0 Generic input port (but the PODR bit is a read-only bit, and when

compare match occurs, the NDR bit value is transferred to the PODR bit)

1 PPG pulse output

Sequential output of data of up to 16 bits is possible by writing new output data to NDR before

the next compare match. For details of non-overlapping operation, see section 11.3.4, Non-

Overlapping Pulse Output.

386

11.3.2 Output Timing

If pulse output is enabled, NDR contents are transferred to PODR and output when the specified

compare match event occurs. Figure 11-3 shows the timing of these operations for the case of

normal output in groups 2 and 3, triggered by compare match A.

TCNT N N+1

TGRA N

Compare match

A signal

NDRH

PODRH

PO8 to PO15

Figure 11-3 Timing of Transfer and Output of NDR Contents (Example)

387

11.3.3 Normal Pulse Output

Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for

setting up normal pulse output.

Select TGR functions [1]

Set TGRA value

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Normal PPG output

Yes

TPU setup

Port and

PPG setup

TPU setup

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

Compare match?

[1] Set TIOR to make TGRA an output

compare register (with output

disabled)

[2] Set the PPG output trigger period

[3] Select the counter clock source

with bits TPSC2 to TPSC0 in TCR.

Select the counter clear source

with bits CCLR1 and CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC can also be set up to

transfer data to NDR.

[5] Set the initial output values in

PODR.

[6]

Set the DDR and NDER bits for the

pins to be used for pulse output to 1.

[7] Select the TPU compare match

event to be used as the output

trigger in PCR.

[8] Set the next pulse output values in

NDR.

[9] Set the CST bit in TSTR to 1 to

start the TCNT counter.

[10]

At each TGIA interrupt, set the next

output values in NDR.

Figure 11-4 Setup Procedure for Normal Pulse Output (Example)

388

Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows

an example in which pulse output is used for cyclic five-phase pulse output.

TCNT value TCNT

TGRA

H'0000

NDRH

00 80 C0 40 60 20 30 10 18 08 88

PODRH

PO15

PO14

PO13

PO12

PO11

Time

Compare match

C080 40 60 20 30 10 18 08 88 80 C0 40

Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output)

[1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output

compare register and the counter will be cleared by compare match A. Set the trigger period in

TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt.

[2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0

bits in PCR to select compare match in the TPU channel set up in the previous step to be the

output trigger. Write output data H'80 in NDRH.

[3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH

contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the

next output data (H'C0) in NDRH.

[4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained

subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA

interrupts. If the DTC is set for activation by this interrupt, pulse output can be obtained

without imposing a load on the CPU.

389

11.3.4 Non-Overlapping Pulse Output

Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample

procedure for setting up non-overlapping pulse output.

Select TGR functions [1]

Set TGR values

Set counting operation

Select interrupt request

Set initial output data

Enable pulse output

Select output trigger

Set next pulse

output data

Start counter

Set next pulse

output data

Compare match? No

Yes

TPU setup

PPG setup

TPU setup

Non-overlapping

PPG output

Set non-overlapping groups

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[1] Set TIOR to make TGRA and

TGRB an output compare registers

(with output disabled)

[2] Set the pulse output trigger period

in TGRB and the non-overlap

margin in TGRA.

[3] Select the counter clock source

with bits TPSC2 to TPSC0 in TCR.

Select the counter clear source

with bits CCLR1 and CCLR0.

[4] Enable the TGIA interrupt in TIER.

The DTC can also be set up to

transfer data to NDR.

[5] Set the initial output values in

PODR.

[6] Set the DDR and NDER bits for the

pins to be used for pulse output to

[7] Select the TPU compare match

event to be used as the pulse

output trigger in PCR.

[8] In PMR, select the groups that will

operate in non-overlap mode.

[9] Set the next pulse output values in

NDR.

[10] Set the CST bit in TSTR to 1 to

start the TCNT counter.

[11] At each TGIA interrupt, set the next

output values in NDR.

Figure 11-6 Setup Procedure for Non-Overlapping Pulse Output (Example)

390

Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-

Overlapping Output): Figure 11-7 shows an example in which pulse output is used for four-

phase complementary non-overlapping pulse output.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRH

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Non-overlap margin

Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary)

391

[1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are

output compare registers. Set the trigger period in TGRB and the non-overlap margin in

TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1

to enable the TGIA interrupt.

[2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0

bits in PCR to select compare match in the TPU channel set up in the previous step to be the

output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.

Write output data H'95 in NDRH.

[3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs,

outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0

to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt

handling routine writes the next output data (H'65) in NDRH.

[4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by

writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC is set for activation by

this interrupt, pulse output can be obtained without imposing a load on the CPU.

392

11.3.5 Inverted Pulse Output

If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the

inverse of the PODR contents can be output.

Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the

settings of figure 11-7.

TCNT value

TCNT

TGRB

TGRA

H'0000

NDRH 95 65 59 56 95 65

00 95 05 65 41 59 50 56 14 95 05 65

PODRL

PO15

PO14

PO13

PO12

PO11

PO10

PO9

PO8

Time

Figure 11-8 Inverted Pulse Output (Example)

393

11.3.6 Pulse Output Triggered by Input Capture

Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA

functions as an input capture register in the TPU channel selected by PCR, pulse output will be

triggered by the input capture signal.

Figure 11-9 shows the timing of this output.

TIOC pin

Input capture

signal

NDR

PODR

Figure 11-9 Pulse Output Triggered by Input Capture (Example)

394

11.4 Usage Notes

Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions

such as the TPU. When output by another peripheral function is enabled, the corresponding pins

cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits

takes place, regardless of the usage of the pins.

Pin functions should be changed only under conditions in which the output trigger event will not

occur.

Note on Non-Overlapping Output: During non-overlapping operation, the transfer of NDR bit

values to PODR bits takes place as follows.

• NDR bits are always transferred to PODR bits at compare match A.

• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred

if their value is 1.

Figure 11-10 illustrates the non-overlapping pulse output operation.

Compare match A

Compare match B

Pulse

output

pin Normal output/inverted output



PODRQD

NDER

NDRQD

Internal data bus

DDR

Figure 11-10 Non-Overlapping Pulse Output

395

Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before

compare match A. The NDR contents should not be altered during the interval from compare

match B to compare match A (the non-overlap margin).

This can be accomplished by having the TGIA interrupt handling routine write the next data in

NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must

be written before the next compare match B occurs.

Figure 11-11 shows the timing of this operation.

0/1 output0 output 0/1 output0 output

Do not write

to NDR here

Write to NDR

here

Compare match A

Compare match B

NDR

PODR

Do not write

to NDR here

Write to NDR

here

Write to NDR Write to NDR

Figure 11-11 Non-Overlapping Operation and NDR Write Timing

396

397

Section 12 Watchdog Timer

12.1 Overview

A single on-chip watchdog timer channel (WDT0) is provided in the H8S/2623 Series, and two

watchdog timer channels (WDT0 and WDT1) in the H8S/2626 Series. The WDT outputs an

overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter,

allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for

the H8S/2626 Series or H8S/2623 Series.

When this watchdog function is not needed, the WDT can be used as an interval timer. In interval

timer operation, an interval timer interrupt is generated each time the counter overflows.

12.1.1 Features

WDT features are listed below.

• Switchable between watchdog timer mode and interval timer mode

• WDTOVF output when in watchdog timer mode

If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether the LSI

is internally reset or an NMI interrupt is generated at the same time.

• Interrupt generation when in interval timer mode

If the counter overflows, the WDT generates an interval timer interrupt.

• WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be

selected

The maximum interval of the WDT is given as a system clock cycle × 131072 × 256.

A subclock may be selected for the input counter of WDT1.

Where a subclock is selected, the maximum interval is given as a subclock cycle × 256 × 256.

• Selected clock can be output from the BUZZ output pin (WDT1)

398

12.1.2 Block Diagram

Figures 12-1 (a) and 12-1 (b) show block diagrams of the WDT.

Overflow

Interrupt

control

WOVI 0

(interrupt request

signal)

WDTOVF

Internal reset signal*Reset

control

RSTCSR TCNT TSCR

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

Clock Clock

select

Internal clock

sources

Bus

interface

Module bus

Legend

TCSR

TCNT

RSTCSR

Note: * The type of internal reset signal depends on a register setting.

: Timer control/status register

: Timer counter

: Reset control/status register

Internal bus

WDT

Figure 12-1 (a) Block Diagram of WDT0

399

Overflow

Interrupt

control

Reset

control

WOVI1

(Interrupt request signal)

BUZZ

Internal reset signal*

TCNT TCSR

ø/2

ø/64

ø/128

ø/512

ø/2048

ø/8192

ø/32768

ø/131072

Clock Clock

select

Internal clock

Bus

interface

Internal bus

Module bus

TCSR :

TCNT : Timer control/status register

Timer counter

WDT

Legend:

Note: * An internal reset signal can be generated by setting the register.

Internal NMI

Interrupt request signal

øSUB/2

øSUB/4

øSUB/8

øSUB/16

øSUB/32

øSUB/64

øSUB/128

øSUB/256

Figure 12-1 (b) Block Diagram of WDT1

400

12.1.3 Pin Configuration

Table 12-1 describes the WDT output pin.

Table 12-1 WDT Pin

Name Symbol I/O Function

Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog

timer mode

Buzzer output*BUZZ Output Outputs clock selected by watchdog timer

(WDT1)

Note: * Cannot be used in the H8S/2623 Series.

12.1.4 Register Configuration

Table 12-2 summarizes the WDT register configuration. These registers control clock selection,

WDT mode switching, and the reset signal.

Table 12-2 WDT Registers

Address*1

Channel Name Abbreviation R/W Initial Value Write*2Read

0 Timer control/status register 0 TCSR0 R/(W)*3H'18 H'FF74 H'FF74

Timer counter 0 TCNT0 R/W H'00 H'FF74 H'FF75

Reset control/status register RSTCSR R/(W)*3H'1F H'FF76 H'FF77

1*4Timer control/status register 1 TCSR1 R/(W)*3H'00 H'FFA2 H'FFA2

Timer counter 1 TCNT1 R/W H'00 H'FFA2 H'FFA3

All Pin function control register PFCR R/W H'0D/H'00 H'FDEB

Notes: 1. Lower 16 bits of the address.

2. For details of write operations, see section 12.2.4, Notes on Register Access.

3. Only a write of 0 is permitted to bit 7, to clear the flag.

4. Cannot be used in the H8S/2623 Series.

401

12.2 Register Descriptions

12.2.1 Timer Counter (TCNT)

Bit:76543210

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

TCNT is an 8-bit readable/writable* up-counter.

When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal

clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from

H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) or an interval timer

interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.

TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared

to 0. It is not initialized in software standby mode.

Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see

section 12.2.5, Notes on Register Access.

12.2.2 Timer Control/Status Register (TCSR)

TCSR0

Bit:76543210

OVF WT/IT TME — — CKS2 CKS1 CKS0

Initial value : 0 0 0 1 1 0 0 0

R/W : R/(W)*R/W R/W — — R/W R/W R/W

Note: *Only a 0 can be written, for flag clearing.

TCSR1*1

Bit:76543210

OVF WT/IT TME PSS RST/NMI CKS2 CKS1 CKS0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/(W)*2R/W R/W R/W R/W R/W R/W R/W

Notes: 1. Cannot be used in the H8S/2623 Series.

2. Only a 0 can be written, for flag clearing.

402

TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be

input to TCNT, and the timer mode.

TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not

initialized in software standby mode.

Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see

section 12.2.5, Notes on Register Access.

Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00.

Bit 7

OVF Description

0 [Clearing conditions] (Initial value)

• Cleared when 0 is written to the TME bit (Only applies to WDT1)

• Cleared by reading TCSR when OVF = 1, then writing 0 to OVF

1 [Setting condition]

When TCNT overflows (changes from H'FF to H'00)

When internal reset request generation is selected in watchdog timer mode, OVF is

cleared automatically by the internal reset.

Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or

interval timer. When TCNT overflows, WDT0 generates the WDTOVF signal when in watchdog

timer mode, or a WOVI interrupt request to the CPU when in interval timer mode. WDT1

generates a reset or NMI interrupt request when in watchdog timer mode, or a WOVI interrupt

request to the CPU when in interval timer mode.

WDT0 Mode Select

WDT0

WT/IT Description

0 Interval timer mode: WDT0 requests an interval timer interrupt (WOVI)

from the CPU when the TCNT overflows. (Initial value)

1 Watchdog timer mode: WDT0 outputs a WDTOVF signal when the TCNT overflows.*

Note: *For details on a TCNT overflow in watchdog timer mode, see section 12.2.3, Reset

Control/Status Register (RSTCSR).

403

WDT1 Mode Select*

WDT1

WT/IT Description

0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI)

from the CPU when the TCNT overflows. (Initial value)

1 Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from

the CPU when the TCNT overflows.

Note: *Cannot be used in the H8S/2623 Series.

Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.

Bit 5

TME Description

0 TCNT is initialized to H'00 and halted (Initial value)

1 TCNT counts

WDT0 TCSR Bit 4—Reserved Bit: This bit is always read as 1 and cannot be modified.

WDT1 TCSR Bit 4—Prescaler Select (PSS): This bit is used to select an input clock source for

the TCNT of WDT1.

See the descriptions of Clock Select 2 to 0 for details.

This bit cannot be used in the H8S/2623 Series.

WDT1 TCSR

Bit 4

PSS Description

0 The TCNT counts frequency-division clock pulses of the ø based

prescaler (PSM). (Initial value)

1 The TCNT counts frequency-division clock pulses of the ø SUB-based prescaler

(PSS).

404

WDT0 TCSR Bit 3—Reserved Bit: This bit is always read as 1 and cannot be modified.

WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal

reset request and an NMI request when the TCNT overflows during the watchdog timer mode.

This bit cannot be used in the H8S/2623 Series.

Bit 3

RTS/NMI Description

0 NMI request. (Initial value)

1 Internal reset request.

Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock

sources, obtained by dividing the system clock (ø) or subclock (ø SUB), for input to TCNT.

WDT0 Input Clock Select

Bit 2 Bit 1 Bit 0 Description

CKS2 CKS1 CKS0 Clock Overflow Period* (where ø = 20 MHz)

0 0 0 ø/2 (initial value) 25.6 µs

1 ø/64 819.2 µs

1 0 ø/128 1.6 ms

1 ø/512 6.6 ms

1 0 0 ø/2048 26.2 ms

1 ø/8192 104.9 ms

1 0 ø/32768 419.4 ms

1 ø/131072 1.68 s

Note: *An overflow period is the time interval between the start of counting up from H'00 on the

TCNT and the occurrence of a TCNT overflow.

405

WDT1 Input Clock Select*2

Description

Bit 4 Bit 2 Bit 1 Bit 0 Overflow Period*1 (where ø = 20 MHz)

PSS CKS2 CKS1 CKS0 Clock (where ø SUB = 32.768 kHz)

0000 ø/2 (initial value) 25.6 µs

1 ø/64 819.2 µs

1 0 ø/128 1.6 ms

1 ø/512 6.6 ms

1 0 0 ø/2048 26.2 ms

1 ø/8192 104.9 ms

1 0 ø/32768 419.4 ms

1 ø/131072 1.68 s

1000 øSUB/2 15.6 ms

1 øSUB/4 31.3 ms

1 0 øSUB/8 62.5 ms

1 øSUB/16 125 ms

1 0 0 øSUB/32 250 ms

1 øSUB/64 500 ms

1 0 øSUB/128 1 s

1 øSUB/256 2 s

Notes: 1. An overflow period is the time interval between the start of counting up from H'00 on the

TCNT and the occurrence of a TCNT overflow.

2. Cannot be used in the H8S/2623 Series.

406

12.2.3 Reset Control/Status Register (RSTCSR)

Bit:76543210

WOVF RSTE RSTS — — — — —

Initial value : 0 0 0 1 1 1 1 1

R/W : R/(W)*R/W R/W — — — — —

Note: *Only 0 can be written, for flag clearing.

RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset

signal when TCNT overflows, and selects the type of internal reset signal.

RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal

reset signal caused by overflows.

Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details

see section 12.2.5, Notes on Register Access.

Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from

H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.

Bit 7

WOVF Description

0 [Clearing condition] (Initial value)

Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF

1 [Setting condition]

Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer

operation

Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the chip if

TCNT overflows during watchdog timer operation.

Bit 6

RSTE Description

0 Reset signal is not generated if TCNT overflows* (Initial value)

1 Reset signal is generated if TCNT overflows

Note: *The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.

407

Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows

during watchdog timer operation.

For details of the types of reset, see section 4, Exception Handling.

Bit 5

RSTS Description

0 Power-on reset (Initial value)

1 Setting prohibited

Bits 4 to 0—Reserved: These bits are always read as 1 and cannot be modified.

12.2.4 Pin Function Control Register (PFCR)

Bit:76543210

— — BUZZE — AE3 AE2 AE1 AE0

Initial value : 0 0 0 0 1/0 1/0 0 1/0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

PFCR is an 8-bit readable/writable register that performs address output control in external

expanded mode.

Only bit 5 is described here. For details of the other bits, see section 7.2.6, Pin Function Control

Bit 5—BUZZ Output Enable (BUZZE)*: Enables or disables BUZZ output from the PF1 pin.

The WDT1 input clock selected with bits PSS and CKS2 to CKS0 is output as the BUZZ signal.

Note: * In the H8S/2623 Series this bit is reserved, and must be written with 0.

Bit 5

BUZZE Description

0 Functions as PF1 I/O pin (Initial value)

1 Functions as BUZZ output pin

408

12.2.5 Notes on Register Access

The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being

more difficult to write to. The procedures for writing to and reading these registers are given

below.

Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.

They cannot be written to with byte instructions.

Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the

same write address. For a write to TCNT, the upper byte of the written word must contain H'5A

and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written

word must contain H'A5 and the lower byte must contain the write data. This transfers the write

data from the lower byte to TCNT or TCSR.

TCNT write

TCSR write

Address: H'FF74

H'5A Write data

15 8 7 0

H'A5 Write data

15 8 7 0

Figure 12-2 Format of Data Written to TCNT and TCSR

409

Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address

H'FF76. It cannot be written to with byte instructions.

Figure 12-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF

bit differs from that for writing to the RSTE and RSTS bits.

To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the

lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write

to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the

write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits,

but has no effect on the WOVF bit.

H'A5 H'00

15 8 7 0

H'5A Write data

15 8 7 0

Writing 0 to WOVF bit

Writing to RSTE and RSTS bits

Address: H'FF76

Figure 12-3 Format of Data Written to RSTCSR

Reading TCNT, TCSR, and RSTCSR (WDT0): These registers are read in the same way as

other registers. The read addresses are H'FF74 for TCSR, H'FF75 for TCNT, and H'FF77 for

RSTCSR.

410

12.3 Operation

12.3.1 Watchdog Timer Operation

To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and TME bit to 1. Software

must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before

overflows occurs. This ensures that TCNT does not overflow while the system is operating

normally. If TCNT overflows without being rewritten because of a system crash or other error, in

the WDT0 the WDTOVF signal is output. This is shown in figure 12-4. This WDTOVF signal can

be used to reset the system. The WDTOVF signal is output for 132 states when RSTE = 1, and for

130 states when RSTE = 0.

If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the chip

internally is generated at the same time as the WDTOVF signal. This reset can be selected as a

power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The

internal reset signal is output for 518 states.

If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a

WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.

In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system

clock periods (516ø) (515 or 516 states when the clock source is øSUB (PSS = 1)). This is

illustrated in figure 12-4 (b).

An NMI request from the watchdog timer and an interrupt request from the NMI pin are both

treated as having the same vector. So, avoid handling an NMI request from the watchdog timer

and an interrupt request from the NMI pin at the same time.

411

TCNT count

H'00 Time

H'FF

WT/IT=1

TME=1 H'00 written

to TCNT WT/IT=1

TME=1 H'00 written

to TCNT

132 states*2

518 states

WDTOVF signal

Internal reset signal*1

WT/IT

TME

Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1.

2. 130 states when the RSTE bit is cleared to 0.

Overflow

WDTOVF and

internal reset are

generated

WOVF=1

: Timer mode select bit

: Timer enable bit

Legend

Figure 12-4 (a) WDT0 Watchdog Timer Operation

TCNT value

H'00 Time

H'FF

WT/IT= 1

TME= 1 Write H'00'

to TCNT WT/IT= 1

TME= 1 Write H'00'

to TCNT

515/516 states

Internal

reset signal

WT/IT

TME

Overflow

Occurrence

of internal reset

WOVF= 1*

: Timer Mode Select bit

: Timer Enable bit

Note: *The WOVF bit is set to 1 and then cleared to 0 by an internal reset.

Figure 12-4 (b) WDT1 Operation in Watchdog Timer Mode

412

12.3.2 Interval Timer Operation

To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1.

An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the

WDT is operating as an interval timer, as shown in figure 12-5. This function can be used to

generate interrupt requests at regular intervals.

TCNT count

H'00 Time

H'FF

WT/IT=0

TME=1 WOVI

Overflow Overflow Overflow Overflow

Legend

WOVI: Interval timer interrupt re

uest

eneration

WOVI WOVI WOVI

Figure 12-5 Interval Timer Operation

12.3.3 Timing of Setting Overflow Flag (OVF)

The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an

interval timer interrupt (WOVI) is requested. This timing is shown in figure 12-6.

With WDT1, the OVF bit of the TCSR is set to 1 and a simultaneous NMI interrupt is requested

when the TCNT overflows if the NMI request has been chosen in the watchdog timer mode.

413

TCNT H'FF H'00

Overflow signal

(internal signal)

OVF

Figure 12-6 Timing of Setting of OVF

12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)

In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At

the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR

is set to 1, an internal reset signal is generated for the entire chip. Figure 12-7 shows the timing in

this case.

TCNT H'FF H'00

Overflow signal

(internal signal)

WOVF

WDTOVF signal

Internal reset

signal

132 states

518 states (WDT0)

515/516 states

(

WDT1

)

Figure 12-7 Timing of Setting of WOVF

414

12.4 Interrupts

During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).

The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be

cleared to 0 in the interrupt handling routine.

If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated

when a TCNT overflow occurs.

12.5 Usage Notes

12.5.1 Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write

takes priority and the timer counter is not incremented. Figure 12-8 shows this operation.

Address

Internal write signal

TCNT input clock

TCNT NM

T1T2

TCNT write cycle

Counter write data

Figure 12-8 Contention between TCNT Write and Increment

415

12.5.2 Changing Value of PSS and CKS2 to CKS0

If bits PSS and CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could

occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0)

before changing the value of bits PSS and CKS2 to CKS0.

12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is

operating, errors could occur in the incrementation. Software must stop the watchdog timer (by

clearing the TME bit to 0) before switching the mode.

12.5.4 System Reset by WDTOVF Signal

If the WDTOVF output signal is input to the RES pin of the H8S/2626 Series or H8S/2623 Series,

the chip will not be initialized correctly. Make sure that the WDTOVF signal is not input logically

to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown

in figure 12-9.

Reset input

Reset signal to entire system

H8S/2626 Series or

H8S/2623 Series

RES

WDTOVF

Figure 12-9 Circuit for System Reset by WDTOVF Signal (Example)

12.5.5 Internal Reset in Watchdog Timer Mode

The H8S/2626 Series or H8S/2623 Series is not reset internally if TCNT overflows while the

RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TCSR of the WDT are

reset.

TCNT, TCSR, and RSTCSR cannot be written to while the WDTOVF signal is low. Also note

that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg,

therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.

416

417

Section 13 Serial Communication Interface (SCI)

13.1 Overview

The H8S/2626 Series and H8S/2623 Series have three independent serial communication interface

(SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial

communication. A function is also provided for serial communication between processors

(multiprocessor communication function).

13.1.1 Features

SCI features are listed below.

• Choice of asynchronous or clocked synchronous serial communication mode

Asynchronous mode

 Serial data communication executed using asynchronous system in which synchronization

is achieved character by character

Serial data communication can be carried out with standard asynchronous communication

chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous

Communication Interface Adapter (ACIA)

 A multiprocessor communication function is provided that enables serial data

communication with a number of processors

 Choice of 12 serial data transfer formats

Data length : 7 or 8 bits

Stop bit length : 1 or 2 bits

Parity : Even, odd, or none

Multiprocessor bit : 1 or 0

 Receive error detection : Parity, overrun, and framing errors

 Break detection : Break can be detected by reading the RxD pin level directly in

case of a framing error

Clocked Synchronous mode

 Serial data communication synchronized with a clock

Serial data communication can be carried out with other chips that have a synchronous

communication function

 One serial data transfer format

Data length : 8 bits

 Receive error detection : Overrun errors detected

418

• Full-duplex communication capability

 The transmitter and receiver are mutually independent, enabling transmission and reception

to be executed simultaneously

 Double-buffering is used in both the transmitter and the receiver, enabling continuous

transmission and continuous reception of serial data

• Choice of LSB-first or MSB-first transfer

 Can be selected regardless of the communication mode* (except in the case of

asynchronous mode 7-bit data)

Note: * Descriptions in this section refer to LSB-first transfer.

• On-chip baud rate generator allows any bit rate to be selected

• Choice of serial clock source: internal clock from baud rate generator or external clock from

SCK pin

• Four interrupt sources

 Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive

error — that can issue requests independently

 The transmit-data-empty interrupt and receive data full interrupts can activate the data

transfer controller (DTC) to execute data transfer

• Module stop mode can be set

 As the initial setting, SCI operation is halted. Register access is enabled by exiting module

stop mode.

419

13.1.2 Block Diagram

Figure 13-1 shows a block diagram of the SCI.

Bus interface

TDR

RSR

RDR

Module data bus

TSR

SCMR

SSR

SCR

Transmission/

reception control

BRR

Baud rate

generator

Internal

data bus

RxD

TxD

SCK

Parity generation

Parity check

Clock

External clock

ø/4

ø/16

ø/64

TXI

TEI

RXI

ERI

SMR

Legend

RSR

RDR

TSR

TDR

SMR

SCR

SSR

SCMR

BRR

: Receive shift register

: Receive data register

: Transmit shift register

: Transmit data register

: Serial mode register

: Serial control register

: Serial status register

: Smart card mode register

: Bit rate register

Figure 13-1 Block Diagram of SCI

420

13.1.3 Pin Configuration

Table 13-1 shows the serial pins for each SCI channel.

Table 13-1 SCI Pins

Channel Pin Name Symbol*I/O Function

0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output

Receive data pin 0 RxD0 Input SCI0 receive data input

Transmit data pin 0 TxD0 Output SCI0 transmit data output

1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output

Receive data pin 1 RxD1 Input SCI1 receive data input

Transmit data pin 1 TxD1 Output SCI1 transmit data output

2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output

Receive data pin 2 RxD2 Input SCI2 receive data input

Transmit data pin 2 TxD2 Output SCI2 transmit data output

Note: *Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel

designation.

421

13.1.4 Register Configuration

The SCI has the internal registers shown in table 13-2. These registers are used to specify

asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control

transmitter/receiver.

Table 13-2 SCI Registers

Channel Name Abbreviation R/W Initial Value Address*1

0 Serial mode register 0 SMR0 R/W H'00 H'FF78

Bit rate register 0 BRR0 R/W H'FF H'FF79

Serial control register 0 SCR0 R/W H'00 H'FF7A

Transmit data register 0 TDR0 R/W H'FF H'FF7B

Serial status register 0 SSR0 R/(W)*2H'84 H'FF7C

Receive data register 0 RDR0 R H'00 H'FF7D

Smart card mode register 0 SCMR0 R/W H'F2 H'FF7E

1 Serial mode register 1 SMR1 R/W H'00 H'FF80

Bit rate register 1 BRR1 R/W H'FF H'FF81

Serial control register 1 SCR1 R/W H'00 H'FF82

Transmit data register 1 TDR1 R/W H'FF H'FF83

Serial status register 1 SSR1 R/(W)*2H'84 H'FF84

Receive data register 1 RDR1 R H'00 H'FF85

Smart card mode register 1 SCMR1 R/W H'F2 H'FF86

2 Serial mode register 2 SMR2 R/W H'00 H'FF88

Bit rate register 2 BRR2 R/W H'FF H'FF89

Serial control register 2 SCR2 R/W H'00 H'FF8A

Transmit data register 2 TDR2 R/W H'FF H'FF8B

Serial status register 2 SSR2 R/(W)*2H'84 H'FF8C

Receive data register 2 RDR2 R H'00 H'FF8D

Smart card mode register 2 SCMR2 R/W H'F2 H'FF8E

All Module stop control register B MSTPCRB R/W H'FF H'FDE9

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, for flag clearing.

422

13.2 Register Descriptions

13.2.1 Receive Shift Register (RSR)

—

Bit

R/W

RSR is a register used to receive serial data.

The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the

LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is

transferred to RDR automatically.

RSR cannot be directly read or written to by the CPU.

13.2.2 Receive Data Register (RDR)

Bit

Initial value

R/W

RDR is a register that stores received serial data.

When the SCI has received one byte of serial data, it transfers the received serial data from RSR to

RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.

Since RSR and RDR function as a double buffer in this way, enables continuous receive

operations to be performed.

RDR is a read-only register, and cannot be written to by the CPU.

RDR is initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep

mode, or module stop mode.

423

13.2.3 Transmit Shift Register (TSR)

—

Bit

R/W

TSR is a register used to transmit serial data.

To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then

sends the data to the TxD pin starting with the LSB (bit 0).

When transmission of one byte is completed, the next transmit data is transferred from TDR to

TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not

performed if the TDRE bit in SSR is set to 1.

TSR cannot be directly read or written to by the CPU.

13.2.4 Transmit Data Register (TDR)

R/W

Bit

Initial value

R/W

TDR is an 8-bit register that stores data for serial transmission.

When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and

starts serial transmission. Continuous serial transmission can be carried out by writing the next

transmit data to TDR during serial transmission of the data in TSR.

TDR can be read or written to by the CPU at all times.

TDR is initialized to H'FF by a reset, in standby mode, watch mode, subactive mode, subsleep

mode, or module stop mode.

424

13.2.5 Serial Mode Register (SMR)

C/A

R/W

CHR

R/W

O/E

R/W

STOP

R/W

CKS0

R/W

CKS1

R/W

Bit

Initial value

R/W

SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate

generator clock source.

SMR can be read or written to by the CPU at all times.

SMR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in

module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.

Bit 7—Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode

as the SCI operating mode.

Bit 7

C/ADescription

0 Asynchronous mode (Initial value)

1 Clocked synchronous mode

Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In

clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.

Bit 6

CHR Description

0 8-bit data (Initial value)

1 7-bit data*

Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible

to choose between LSB-first or MSB-first transfer.

425

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is

performed in transmission, and parity bit checking in reception. In clocked synchronous mode

with a multiprocessor format, parity bit addition and checking is not performed, regardless of the

PE bit setting.

Bit 5

PE Description

0 Parity bit addition and checking disabled (Initial value)

1 Parity bit addition and checking enabled*

Note:*When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to

transmit data before transmission. In reception, the parity bit is checked for the parity (even

or odd) specified by the O/E bit.

Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and

checking.

The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and

checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode,

when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor

format is used.

Bit 4

O/EDescription

0 Even parity*1 (Initial value)

1 Odd parity*2

Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is even.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is even.

2. When odd parity is set, parity bit addition is performed in transmission so that the total

number of 1 bits in the transmit character plus the parity bit is odd.

In reception, a check is performed to see if the total number of 1 bits in the receive

character plus the parity bit is odd.

426

Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.

The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the

STOP bit setting is invalid since stop bits are not added.

Bit 3

STOP Description

0 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end

of a transmit character before it is sent. (Initial value)

1 2 stop bits:In transmission, two 1 bits (stop bits) are added to the end of a transmit

character before it is sent.

In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second

stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit

character.

Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format

is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in

asynchronous mode; it is invalid in clocked synchronous mode.

For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor

Communication Function.

Bit 2

MP Description

0 Multiprocessor function disabled (Initial value)

1 Multiprocessor format selected

427

Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the

baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the

setting of bits CKS1 and CKS0.

For the relation between the clock source, the bit rate register setting, and the baud rate, see

section 13.2.8, Bit Rate Register.

Bit 1 Bit 0

CKS1 CKS0 Description

0 0 ø clock (Initial value)

1 ø/4 clock

1 0 ø/16 clock

1 ø/64 clock

13.2.6 Serial Control Register (SCR)

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

Bit

Initial value

R/W

SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output

in asynchronous mode, and interrupt requests, and selection of the serial clock source.

SCR can be read or written to by the CPU at all times.

SCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in

module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt

(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE

flag in SSR is set to 1.

Bit 7

TIE Description

0 Transmit data empty interrupt (TXI) requests disabled (Initial value)

1 Transmit data empty interrupt (TXI) requests enabled

Note: TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then

clearing it to 0, or clearing the TIE bit to 0.

428

Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)

request and receive error interrupt (ERI) request generation when serial receive data is transferred

from RSR to RDR and the RDRF flag in SSR is set to 1.

Bit 6

RIE Description

0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

disabled* (Initial value)

1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request

enabled

Note:*RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF

flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.

Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.

Bit 5

TE Description

0 Transmission disabled*1 (Initial value)

1 Transmission enabled*2

Notes: 1. The TDRE flag in SSR is fixed at 1.

2. In this state, serial transmission is started when transmit data is written to TDR and the

TDRE flag in SSR is cleared to 0.

SMR setting must be performed to decide the transfer format before setting the TE bit

to 1.

Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.

Bit 4

RE Description

0 Reception disabled*1 (Initial value)

1 Reception enabled*2

Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which

retain their states.

2. Serial reception is started in this state when a start bit is detected in asynchronous

mode or serial clock input is detected in clocked synchronous mode.

SMR setting must be performed to decide the transfer format before setting the RE bit

to 1.

429

Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.

The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1.

The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0.

Bit 3

MPIE Description

0 Multiprocessor interrupts disabled (normal reception performed) (Initial value)

[Clearing conditions]

• When the MPIE bit is cleared to 0

• When MPB= 1 data is received

1 Multiprocessor interrupts enabled*

Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting

of the RDRF, FER, and ORER flags in SSR are disabled until data with the

multiprocessor bit set to 1 is received.

Note: *When receive data including MPB = 0 is received, receive data transfer from RSR to RDR,

receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not

performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to

1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts

(when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.

Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt

(TEI) request generation when there is no valid transmit data in TDR in MSB data transmission.

Bit 2

TEIE Description

0 Transmit end interrupt (TEI) request disabled* (Initial value)

1 Transmit end interrupt (TEI) request enabled*

Note: *TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it

to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.

430

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock

source and enable or disable clock output from the SCK pin. The combination of the CKE1 and

CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or

the serial clock input pin.

The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in

asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case

of external clock operation (CKE1 = 1). Note that the SCI’s operating mode must be decided using

SMR before setting the CKE1 and CKE0 bits.

For details of clock source selection, see table 13.9 in section 13.3, Operation.

Bit 1 Bit 0

CKE1 CKE0 Description

0 0 Asynchronous mode Internal clock/SCK pin functions as I/O port*1

Clocked synchronous

mode Internal clock/SCK pin functions as serial clock

output*1

1 Asynchronous mode Internal clock/SCK pin functions as clock output*2

Clocked synchronous

mode Internal clock/SCK pin functions as serial clock

output

1 0 Asynchronous mode External clock/SCK pin functions as clock input*3

Clocked synchronous

mode External clock/SCK pin functions as serial clock

input

1 Asynchronous mode External clock/SCK pin functions as clock input*3

Clocked synchronous

mode External clock/SCK pin functions as serial clock

input

Notes: 1. Initial value

2. Outputs a clock of the same frequency as the bit rate.

3. Inputs a clock with a frequency 16 times the bit rate.

431

13.2.7 Serial Status Register (SSR)

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FER

R/(W)*

PER

R/(W)*

MPBT

R/W

TEND

MPB

Bit

Initial value

R/W

Note: * Only 0 can be written, for flag clearing.

SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and

multiprocessor bits.

SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags

TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be

read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.

SSR is initialized to H'84 by a reset, in standby mode, watch mode, subactive mode, subsleep

mode, or module stop mode.

Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from

TDR to TSR and the next serial data can be written to TDR.

Bit 7

TDRE Description

0 [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

1 [Setting conditions] (Initial value)

• When the TE bit in SCR is 0

• When data is transferred from TDR to TSR and data can be written to TDR

432

Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.

Bit 6

RDRF Description

0 [Clearing conditions] (Initial value)

• When 0 is written to RDRF after reading RDRF = 1

• When the DTC is activated by an RXI interrupt and reads data from RDR

1 [Setting condition]

When serial reception ends normally and receive data is transferred from RSR to RDR

Note: RDR and the RDRF flag are not affected and retain their previous values when an error is

detected during reception or when the RE bit in SCR is cleared to 0.

If reception of the next data is completed while the RDRF flag is still set to 1, an overrun

error will occur and the receive data will be lost.

Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,

causing abnormal termination.

Bit 5

ORER Description

0 [Clearing condition] (Initial value)*1

When 0 is written to ORER after reading ORER = 1

1 [Setting condition]

When the next serial reception is completed while RDRF = 1*2

Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

2. The receive data prior to the overrun error is retained in RDR, and the data received

subsequently is lost. Also, subsequent serial reception cannot be continued while the

ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

433

Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in

asynchronous mode, causing abnormal termination.

Bit 4

FER Description

0 [Clearing condition] (Initial value)*1

When 0 is written to FER after reading FER = 1

1 [Setting condition]

When the SCI checks whether the stop bit at the end of the receive data when

reception ends, and the stop bit is 0 *2

Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit

is not checked. If a framing error occurs, the receive data is transferred to RDR but the

RDRF flag is not set. Also, subsequent serial reception cannot be continued while the

FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be

continued, either.

Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity

addition in asynchronous mode, causing abnormal termination.

Bit 3

PER Description

0 [Clearing condition] (Initial value)*1

When 0 is written to PER after reading PER = 1

1 [Setting condition]

When, in reception, the number of 1 bits in the receive data plus the parity bit does not

match the parity setting (even or odd) specified by the O/E bit in SMR*2

Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is

cleared to 0.

2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not

set. Also, subsequent serial reception cannot be continued while the PER flag is set to

1. In clocked synchronous mode, serial transmission cannot be continued, either.

434

Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of

the transmit character is sent, and transmission has been ended.

The TEND flag is read-only and cannot be modified.

Bit 2

TEND Description

0 [Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and writes data to TDR

1 [Setting conditions] (Initial value)

• When the TE bit in SCR is 0

• When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character

Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in

asynchronous mode, MPB stores the multiprocessor bit in the receive data.

MPB is a read-only bit, and cannot be modified.

Bit 1

MPB Description

0 [Clearing condition] (Initial value)*

When data with a 0 multiprocessor bit is received

1 [Setting condition]

When data with a 1 multiprocessor bit is received

Note: *Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor

format.

Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using

multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to

the transmit data.

The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting,

and in clocked synchronous mode.

Bit 0

MPBT Description

0 Data with a 0 multiprocessor bit is transmitted (Initial value)

1 Data with a 1 multiprocessor bit is transmitted

435

13.2.8 Bit Rate Register (BRR)

R/W

Bit

Initial value

R/W

BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate

generator operating clock selected by bits CKS1 and CKS0 in SMR.

BRR can be read or written to by the CPU at all times.

BRR is initialized to H'FF by a reset and in hardware standby mode. It retains its previous state in

module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.

As baud rate generator control is performed independently for each channel, different values can

be set for each channel.

Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR

settings in clocked synchronous mode.

436

Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode)

ø = 2 MHz ø = 2.097152 MHz ø = 2.4576 MHz ø = 3 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03

150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16

300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16

600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16

1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16

2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16

4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34

9600 — — — 0 6 –2.48 0 7 0.00 0 9 –2.34

19200 ——————0 3 0.00 0 4 –2.34

31250 0 1 0.00 ——————0 2 0.00

38400 ——————0 1 0.00 — — —

ø = 3.6864 MHz ø = 4 MHz ø = 4.9152 MHz ø = 5 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25

150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16

300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16

600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16

1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16

2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16

4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36

9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73

19200 0 5 0.00 — — — 0 7 0.00 0 7 1.73

31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00

38400 0 2 0.00 — — — 0 3 0.00 0 3 1.73

437

ø = 6 MHz ø = 6.144 MHz ø = 7.3728 MHz ø = 8 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03

150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16

300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16

600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16

1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16

2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16

4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16

9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16

19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16

31250 0 5 0.00 0 5 2.40 — — — 0 7 0.00

38400 0 4 –2.34 0 4 0.00 0 5 0.00 — — —

ø = 9.8304 MHz ø = 10 MHz ø = 12 MHz ø = 12.288 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08

150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00

300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00

600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00

1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00

2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00

4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00

9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00

19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00

31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40

38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00

438

ø = 14 MHz ø = 14.7456 MHz ø = 16 MHz ø = 17.2032 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 2 248 –0.17 3 64 0.70 3 70 0.03 3 75 0.48

150 2 181 0.13 2 191 0.00 2 207 0.13 2 223 0.00

300 2 90 0.13 2 95 0.00 2 103 0.13 2 111 0.00

600 1 181 0.13 1 191 0.00 1 207 0.13 1 223 0.00

1200 1 90 0.13 1 95 0.00 1 103 0.13 1 111 0.00

2400 0 181 0.13 0 191 0.00 0 207 0.13 0 223 0.00

4800 0 90 0.13 0 95 0.00 0 103 0.13 0 111 0.00

9600 0 45 –0.93 0 47 0.00 0 51 0.13 0 55 0.00

19200 0 22 –0.93 0 23 0.00 0 25 0.13 0 27 0.00

31250 0 13 0.00 0 14 –1.70 0 15 0.00 0 13 1.20

38400 ———0 110.00 0 12 0.13 0 13 0.00

ø = 18 MHz ø = 19.6608 MHz ø = 20 MHz

Bit Rate

(bit/s) n N Error

(%) n N Error

(%)

110 3 79 –0.12 3 86 0.31 3 88 –0.25

150 2 233 0.16 2 255 0.00 3 64 0.16

300 2 116 0.16 2 127 0.00 2 129 0.16

600 1 233 0.16 1 255 0.00 2 64 0.16

1200 1 116 0.16 1 127 0.00 1 129 0.16

2400 0 233 0.16 0 255 0.00 1 64 0.16

4800 0 116 0.16 0 127 0.00 0 129 0.16

9600 0 58 –0.69 0 63 0.00 0 64 0.16

19200 0 28 1.02 0 31 0.00 0 32 –1.36

31250 0 17 0.00 0 19 –1.70 0 19 0.00

38400 0 14 –2.34 0 15 0.00 0 15 1.73

439

Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)

Bit Rate ø = 2 MHz ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz

(bit/s) n N n N n N n N n N n N

110 3 70 — —

250 2 124 2 249 3 124 — — 3 249

500 1 249 2 124 2 249 — — 3 124 — —

1 k 1 124 1 249 2 124 — — 2 249 — —

2.5 k 0 199 1 99 1 199 1 249 2 99 2 124

5 k 0 99 0 199 1 99 1 124 1 199 1 249

10 k 0 49 0 99 0 199 0 249 1 99 1 124

25 k 0 19 0 39 0 79 0 99 0 159 0 199

50 k 0 9 0 19 0 39 0 49 0 79 0 99

100 k 0 4 0 9 0 19 0 24 0 39 0 49

250 k 0 1 0 3 0 7 0 9 0 15 0 19

500 k 0 0*0 1 03 04 07 09

1 M 0 0*01 03 04

2.5 M 0 0*01

5 M 00*

Note: As far as possible, the setting should be made so that the error is no more than 1%.

Legend

Blank : Cannot be set.

— : Can be set, but there will be a degree of error.

*: Continuous transfer is not possible.

440

The BRR setting is found from the following formulas.

Asynchronous mode:

N = ø

64 × 22n–1 × B × 106 – 1

Clocked synchronous mode:

N = ø

8 × 22n–1 × B × 106 – 1

Where B: Bit rate (bit/s)

N: BRR setting for baud rate generator (0 ≤ N ≤ 255)

ø: Operating frequency (MHz)

n: Baud rate generator input clock (n = 0 to 3)

(See the table below for the relation between n and the clock.)

SMR Setting

n Clock CKS1 CKS0

0ø 0 0

1 ø/4 0 1

2 ø/16 1 0

3 ø/64 1 1

The bit rate error in asynchronous mode is found from the following formula:

Error (%) = { ø × 106

(N + 1) × B × 64 × 22n–1 – 1} × 100

441

Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6

and 13-7 show the maximum bit rates with external clock input.

Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)

ø (MHz) Maximum Bit Rate (bit/s) n N

2 62500 0 0

2.097152 65536 0 0

2.4576 76800 0 0

3 93750 0 0

3.6864 115200 0 0

4 125000 0 0

4.9152 153600 0 0

5 156250 0 0

6 187500 0 0

6.144 192000 0 0

7.3728 230400 0 0

8 250000 0 0

9.8304 307200 0 0

10 312500 0 0

12 375000 0 0

12.288 384000 0 0

14 437500 0 0

14.7456 460800 0 0

16 500000 0 0

17.2032 537600 0 0

18 562500 0 0

19.6608 614400 0 0

20 625000 0 0

442

Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)

ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)

2 0.5000 31250

2.097152 0.5243 32768

2.4576 0.6144 38400

3 0.7500 46875

3.6864 0.9216 57600

4 1.0000 62500

4.9152 1.2288 76800

5 1.2500 78125

6 1.5000 93750

6.144 1.5360 96000

7.3728 1.8432 115200

8 2.0000 125000

9.8304 2.4576 153600

10 2.5000 156250

12 3.0000 187500

12.288 3.0720 192000

14 3.5000 218750

14.7456 3.6864 230400

16 4.0000 250000

17.2032 4.3008 268800

18 4.5000 281250

19.6608 4.9152 307200

20 5.0000 312500

443

Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)

ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)

2 0.3333 333333.3

4 0.6667 666666.7

6 1.0000 1000000.0

8 1.3333 1333333.3

10 1.6667 1666666.7

12 2.0000 2000000.0

14 2.3333 2333333.3

16 2.6667 2666666.7

18 3.0000 3000000.0

20 3.3333 3333333.3

444

13.2.9 Smart Card Mode Register (SCMR)

—

SDIR

R/W

SMIF

R/W

SINV

R/W

—

Bit

Initial value

R/W

SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous

mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication

mode. The descriptions in this chapter refer to LSB-first transfer.

For details of the other bits in SCMR, see 14.2.1, Smart Card Mode Register (SCMR).

SCMR is initialized to H'F2 by a reset and in hardware standby mode. It retains its previous state

in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode.

Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion

format.

This bit is valid when 8-bit data is used as the transmit/receive format.

Bit 3

SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

445

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV

bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the

O/E bit in SMR.

Bit 2

SINV Description

0 TDR contents are transmitted without modification (Initial value)

Receive data is stored in RDR without modification

1 TDR contents are inverted before being transmitted

Receive data is stored in RDR in inverted form

Bit 1—Reserved: This bit is always read as 1 and cannot be modified.

Bit 0—Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a

normal SCI, 0 should be written in this bit.

Bit 0

SMIF Description

0 Operates as normal SCI (smart card interface function disabled) (Initial value)

1 Smart card interface function enabled

13.2.10 Module Stop Control Register B (MSTPCRB)

MSTPB7

R/W

MSTPB6

R/W

MSTPB5

R/W

MSTPB4

R/W

MSTPB3

R/W

MSTPB0

R/W

MSTPB2

R/W

MSTPB1

R/W

Bit

Initial value

R/W

MSTPCRB

MSTPCRB is 8-bit readable/writable registers that perform module stop mode control.

When one of bits MSTPB7 to MSTPB5 is set to 1, SCI0, SCI1, or SCI2, respectively, stops

operation at the end of the bus cycle, and enters module stop mode. For details, see section 20.5,

Module Stop Mode.

MSTPCRB is initialized to H'FF by a reset and in hardware standby mode. They are not

initialized in software standby mode.

446

Bit 7—Module Stop (MSTPB7): Specifies the SCI0 module stop mode.

Bit 7

MSTPB7 Description

0 SCI0 module stop mode is cleared

1 SCI0 module stop mode is set (Initial value)

Bit 6—Module Stop (MSTPB6): Specifies the SCI1 module stop mode.

Bit 6

MSTPB6 Description

0 SCI1 module stop mode is cleared

1 SCI1 module stop mode is set (Initial value)

Bit 5—Module Stop (MSTPB5): Specifies the SCI2 module stop mode.

Bit 5

MSTPB5 Description

0 SCI2 module stop mode is cleared

1 SCI2 module stop mode is set (Initial value)

447

13.3 Operation

13.3.1 Overview

The SCI can carry out serial communication in two modes: asynchronous mode in which

synchronization is achieved character by character, and clocked synchronous mode in which

synchronization is achieved with clock pulses.

Selection of asynchronous or clocked synchronous mode and the transmission format is made

using SMR as shown in table 13-8. The SCI clock is determined by a combination of the C/A bit

in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13-9.

Asynchronous Mode

• Data length: Choice of 7 or 8 bits

• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the

combination of these parameters determines the transfer format and character length)

• Detection of framing, parity, and overrun errors, and breaks, during reception

• Choice of internal or external clock as SCI clock source

 When internal clock is selected:

The SCI operates on the baud rate generator clock and a clock with the same frequency as

the bit rate can be output

 When external clock is selected:

A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate

generator is not used)

Clocked Synchronous Mode

• Transfer format: Fixed 8-bit data

• Detection of overrun errors during reception

• Choice of internal or external clock as SCI clock source

 When internal clock is selected:

The SCI operates on the baud rate generator clock and a serial clock is output off-chip

 When external clock is selected:

The on-chip baud rate generator is not used, and the SCI operates on the input serial clock

448

Table 13-8 SMR Settings and Serial Transfer Format Selection

SMR Settings SCI Transfer Format

Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multi

Processor Parity Stop Bit

C/ACHR MP PE STOP Mode Length Bit Bit Length

00000Asynchronous 8-bit data No No 1 bit

1mode 2 bits

1 0 Yes 1 bit

1 2 bits

1 0 0 7-bit data No 1 bit

1 2 bits

1 0 Yes 1 bit

1 2 bits

0 1 — 0 Asynchronous

mode (multi- 8-bit data Yes No 1 bit

—1 processor format) 2 bits

1 — 0 7-bit data 1 bit

— 1 2 bits

1 ————Clocked

synchronous mode 8-bit data No None

Table 13-9 SMR and SCR Settings and SCI Clock Source Selection

SMR SCR Setting SCI Transmit/Receive Clock

Bit 7 Bit 1 Bit 0 Clock

C/ACKE1 CKE0 Mode Source SCK Pin Function

0 0 0 Asynchronous Internal SCI does not use SCK pin

1mode Outputs clock with same frequency as bit

rate

1 0 External Inputs clock with frequency of 16 times

1the bit rate

1 0 0 Clocked

synchronous Internal Outputs serial clock

1mode

1 0 External Inputs serial clock

449

13.3.2 Operation in Asynchronous Mode

In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the

start of communication and stop bits indicating the end of communication. Serial communication

is thus carried out with synchronization established on a character-by-character basis.

Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex

communication. Both the transmitter and the receiver also have a double-buffered structure, so

that data can be read or written during transmission or reception, enabling continuous data

transfer.

Figure 13-2 shows the general format for asynchronous serial communication.

In asynchronous serial communication, the transmission line is usually held in the mark state (high

level). The SCI monitors the transmission line, and when it goes to the space state (low level),

recognizes a start bit and starts serial communication.

One serial communication character consists of a start bit (low level), followed by data (in LSB-

first order), a parity bit (high or low level), and finally stop bits (high level).

In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in

reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the

length of one bit, so that the transfer data is latched at the center of each bit.

LSB

Start

bit

MSB

Idle state

(mark state)

Stop bit

Transmit/receive data

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

1 1

Serial

data Parity

bit

1 bit 1 or

2 bits

7 or 8 bits 1 bit,

or none

One unit of transfer data (character or frame)

Figure 13-2 Data Format in Asynchronous Communication

(Example with 8-Bit Data, Parity, Two Stop Bits)

450

Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in

asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting.

Table 13-10 Serial Transfer Formats (Asynchronous Mode)

—

8-bit data

STOP

7-bit data

STOP

8-bit data

STOP STOP

8-bit data

STOP

7-bit data

STOP

8-bit data

MPB STOP

8-bit data

MPB STOP STOP

7-bit data

STOPMPB

7-bit data

STOPMPB STOP

7-bit data

STOPSTOP

CHR

STOP

SMR Settings

123456789101112

Serial Transfer Format and Frame Length

STOP

8-bit data

STOP

7-bit data

STOP

Legend

S : Start bit

STOP : Stop bit

P : Parity bit

MPB : Multiprocessor bit

451

Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock

input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A

bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see

table 13-9.

When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate

used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3.

1 frame

D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1

Figure 13-3 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode)

Data Transfer Operations:

• SCI initialization (asynchronous mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0,

then initialize the SCI as described below.

When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared

to 0 before making the change using the following procedure. When the TE bit is cleared to 0,

the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not

change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

When an external clock is used the clock should not be stopped during operation, including

initialization, since operation is uncertain.

452

Figure 13-4 shows a sample SCI initialization flowchart.

Wait

Start initialization

Set data transfer format in

SMR and SCMR

[1]

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0)

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in

SCR to 1, and set RIE, TIE, TEIE,

and MPIE bits [4]

1-bit interval elapsed?

[1] Set the clock selection in SCR.

Be sure to clear bits RIE, TIE,

TEIE, and MPIE, and bits TE and

RE, to 0.

When the clock is selected in

asynchronous mode, it is output

immediately after SCR settings are

made.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the

bit rate to BRR. Not necessary if an

external clock is used.

[4] Wait at least one bit interval, then

set the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and

MPIE bits.

Setting the TE and RE bits enables

the TxD and RxD pins to be used.

Figure 13-4 Sample SCI Initialization Flowchart

453

• Serial data transmission (asynchronous mode)

Figure 13-5 shows a sample flowchart for serial transmission.

The following procedure should be used for serial data transmission.

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR

and clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and

set DDR to 1

Clear TE bit in SCR to 0

TDRE=1

All data transmitted?

TEND= 1

Break output?

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a frame

of 1s is output, and transmission is

enabled.

[2] SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission,

read 1 from the TDRE flag to

confirm that writing is possible,

then write data to TDR, and then

clear the TDRE flag to 0. Checking

and clearing of the TDRE flag is

automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request, and date is

written to TDR.

[4] Break output at the end of serial

transmission:

To output a break in serial

transmission, set DDR for the port

corresponding to the TxD pin to 1,

clear DR to 0, then clear the TE bit

in SCR to 0.

Figure 13-5 Sample Serial Transmission Flowchart

454

In serial transmission, the SCI operates as described below.

[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to

TDR, and transfers the data from TDR to TSR.

[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission.

If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.

The serial transmit data is sent from the TxD pin in the following order.

[a] Start bit:

One 0-bit is output.

[b] Transmit data:

8-bit or 7-bit data is output in LSB-first order.

[c] Parity bit or multiprocessor bit:

One parity bit (even or odd parity), or one multiprocessor bit is output.

A format in which neither a parity bit nor a multiprocessor bit is output can also be

selected.

[d] Stop bit(s):

One or two 1-bits (stop bits) are output.

[e] Mark state:

1 is output continuously until the start bit that starts the next transmission is sent.

[3] The SCI checks the TDRE flag at the timing for sending the stop bit.

If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent,

and then serial transmission of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the

“mark state” is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at

this time, a TEI interrupt request is generated.

455

Figure 13-6 shows an example of the operation for transmission in asynchronous mode.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

TXI interrupt

request generated Data written to TDR and

TDRE flag cleared to 0 in

TXI interrupt service routine TEI interrupt

request generated

Idle state

(mark state)

TXI interrupt

request generated

Figure 13-6 Example of Operation in Transmission in Asynchronous Mode

(Example with 8-Bit Data, Parity, One Stop Bit)

456

• Serial data reception (asynchronous mode)

Figure 13-7 shows a sample flowchart for serial reception.

The following procedure should be used for serial data reception.

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Read ORER, PER, and

FER flags in SSR

Error processing

(Continued on next page)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

PER∨FER∨ORER= 1

RDRF= 1

All data received?

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error processing and

break detection:

If a receive error occurs, read the

ORER, PER, and FER flags in

SSR to identify the error. After

performing the appropriate error

processing, ensure that the

ORER, PER, and FER flags are

all cleared to 0. Reception cannot

be resumed if any of these flags

are set to 1. In the case of a

framing error, a break can be

detected by reading the value of

the input port corresponding to

the RxD pin.

SCI status check and receive

data read :

Read SSR and check that RDRF

= 1, then read the receive data in

RDR and clear the RDRF flag to

0. Transition of the RDRF flag

from 0 to 1 can also be identified

by an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the stop bit for the current

frame is received, read the

RDRF flag, read RDR, and clear

the RDRF flag to 0. The RDRF

flag is cleared automatically

when DTC is activated by an RXI

interrupt and the RDR value is

read.

[1]

[2] [3]

[4]

[5]

Figure 13-7 Sample Serial Reception Data Flowchart

457

<End>

[3]

Error processing

Parity error processing

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error processing

Yes

Overrun error processing

ORER= 1

FER= 1

Break?

PER= 1

Clear RE bit in SCR to 0

Figure 13-7 Sample Serial Reception Data Flowchart (cont)

458

In serial reception, the SCI operates as described below.

[1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal

synchronization and starts reception.

[2] The received data is stored in RSR in LSB-to-MSB order.

[3] The parity bit and stop bit are received.

After receiving these bits, the SCI carries out the following checks.

[a] Parity check:

The SCI checks whether the number of 1 bits in the receive data agrees with the parity

(even or odd) set in the O/E bit in SMR.

[b] Stop bit check:

The SCI checks whether the stop bit is 1.

If there are two stop bits, only the first is checked.

[c] Status check:

The SCI checks whether the RDRF flag is 0, indicating that the receive data can be

transferred from RSR to RDR.

If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in

RDR.

If a receive error* is detected in the error check, the operation is as shown in table 13-11.

Note: * Subsequent receive operations cannot be performed when a receive error has occurred.

Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be

cleared to 0.

[4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt

(RXI) request is generated.

Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a

receive error interrupt (ERI) request is generated.

459

Table 13-11 Receive Errors and Conditions for Occurrence

Receive Error Abbreviation Occurrence Condition Data Transfer

Overrun error ORER When the next data reception is

completed while the RDRF flag

in SSR is set to 1

Receive data is not

transferred from RSR to

RDR.

Framing error FER When the stop bit is 0 Receive data is transferred

from RSR to RDR.

Parity error PER When the received data differs

from the parity (even or odd) set

in SMR

Receive data is transferred

from RSR to RDR.

Figure 13-8 shows an example of the operation for reception in asynchronous mode.

RDRF

FER

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0

1 1

DataStart

bit Parity

bit Stop

bit Start

bit Data Parity

bit Stop

bit

RXI interrupt

request

generated ERI interrupt request

generated by framing

error

Idle state

(mark state)

RDR data read and RDRF

flag cleared to 0 in RXI

interrupt service routine

Figure 13-8 Example of SCI Operation in Reception

(Example with 8-Bit Data, Parity, One Stop Bit)

460

13.3.3 Multiprocessor Communication Function

The multiprocessor communication function performs serial communication using the

multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous

mode. Use of this function enables data transfer to be performed among a number of processors

sharing transmission lines.

When multiprocessor communication is carried out, each receiving station is addressed by a

unique ID code.

The serial communication cycle consists of two component cycles: an ID transmission cycle

which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used

to differentiate between the ID transmission cycle and the data transmission cycle.

The transmitting station first sends the ID of the receiving station with which it wants to perform

serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data

with a 0 multiprocessor bit added.

The receiving station skips the data until data with a 1 multiprocessor bit is sent.

When data with a 1 multiprocessor bit is received, the receiving station compares that data with its

own ID. The station whose ID matches then receives the data sent next. Stations whose ID does

not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this

way, data communication is carried out among a number of processors.

Figure 13-9 shows an example of inter-processor communication using the multiprocessor format.

Data Transfer Format: There are four data transfer formats.

When the multiprocessor format is specified, the parity bit specification is invalid.

For details, see table 13-10.

Clock: See the section on asynchronous mode.

461

Transmitting

station

Receiving

station A

(ID= 01)

Receiving

station B

(ID= 02)

Receiving

station C

(ID= 03)

Receiving

station D

(ID= 04)

Serial transmission line

Serial

data

ID transmission cycle=

receiving station

specification

Data transmission cycle=

Data transmission to

receiving station specified by ID

(MPB= 1) (MPB= 0)

H'01 H'AA

Legend

MPB: Multiprocessor bit

Figure 13-9 Example of Inter-Processor Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)

Data Transfer Operations:

• Multiprocessor serial data transmission

Figure 13-10 shows a sample flowchart for multiprocessor serial data transmission.

The following procedure should be used for multiprocessor serial data transmission.

462

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

set MPBT bit in SSR

Yes

Read TEND flag in SSR

[3]

Yes

[4]

Clear DR to 0 and set DDR to 1

Clear TE bit in SCR to 0

TDRE= 1

All data transmitted?

TEND= 1

Break output?

Clear TDRE flag to 0

SCI initialization:

The TxD pin is automatically

designated as the transmit data

output pin.

After the TE bit is set to 1, a

frame of 1s is output, and

transmission is enabled.

SCI status check and transmit

data write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR. Set the

MPBT bit in SSR to 0 or 1.

Finally, clear the TDRE flag to 0.

Serial transmission continuation

procedure:

To continue serial transmission,

be sure to read 1 from the TDRE

flag to confirm that writing is

possible, then write data to TDR,

and then clear the TDRE flag to

0. Checking and clearing of the

TDRE flag is automatic when the

DTC is activated by a transmit

data empty interrupt (TXI)

request, and data is written to

TDR.

Break output at the end of serial

transmission:

To output a break in serial

transmission, set the port DDR to

1, clear DR to 0, then clear the

TE bit in SCR to 0.

[1]

[2]

[3]

[4]

Figure 13-10 Sample Multiprocessor Serial Transmission Flowchart

463

In serial transmission, the SCI operates as described below.

[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to

TDR, and transfers the data from TDR to TSR.

[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission.

If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.

The serial transmit data is sent from the TxD pin in the following order.

[a] Start bit:

One 0-bit is output.

[b] Transmit data:

8-bit or 7-bit data is output in LSB-first order.

[c] Multiprocessor bit

One multiprocessor bit (MPBT value) is output.

[d] Stop bit(s):

One or two 1-bits (stop bits) are output.

[e] Mark state:

1 is output continuously until the start bit that starts the next transmission is sent.

[3] The SCI checks the TDRE flag at the timing for sending the stop bit.

If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and

then serial transmission of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the

mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this

time, a transmission end interrupt (TEI) request is generated.

464

Figure 13-11 shows an example of SCI operation for transmission using the multiprocessor

format.

TDRE

TEND

1 frame

D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1

1 1

DataStart

bit

Multi-

proce-

ssor

bit Stop

bit Start

bit Data Multi-

proces-

sor bit Stop

bit

TXI interrupt

request generated Data written to TDR

and TDRE flag cleared to

0 in TXI interrupt service

routine

TEI interrupt

request generated

Idle state

(mark state)

TXI interrupt

request generated

Figure 13-11 Example of SCI Operation in Transmission

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

• Multiprocessor serial data reception

Figure 13-12 shows a sample flowchart for multiprocessor serial reception.

The following procedure should be used for multiprocessor serial data reception.

465

Yes

<End>

[1]

Initialization

Start reception

Yes

[4]

Clear RE bit in SCR to 0

Error processing

(Continued on

next page)

[5]

Yes

FER∨ORER= 1

RDRF= 1

All data received?

Read MPIE bit in SCR [2]

Read ORER and FER flags in SSR

Read RDRF flag in SSR [3]

Read receive data in RDR

Yes

This station’s ID?

Read ORER and FER flags in SSR

Yes

Read RDRF flag in SSR

Yes

FER∨ORER= 1

Read receive data in RDR

RDRF= 1

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

ID reception cycle:

Set the MPIE bit in SCR to 1.

SCI status check, ID reception

and comparison:

Read SSR and check that the

RDRF flag is set to 1, then read

the receive data in RDR and

compare it with this station’s ID.

If the data is not this station’s ID,

set the MPIE bit to 1 again, and

clear the RDRF flag to 0.

If the data is this station’s ID,

clear the RDRF flag to 0.

SCI status check and data

reception:

Read SSR and check that the

RDRF flag is set to 1, then read

the data in RDR.

Receive error processing and

break detection:

If a receive error occurs, read the

ORER and FER flags in SSR to

identify the error. After

performing the appropriate error

processing, ensure that the

ORER and FER flags are all

cleared to 0.

Reception cannot be resumed if

either of these flags is set to 1.

In the case of a framing error, a

break can be detected by reading

the RxD pin value.

[1]

[2]

[3]

[4]

[5]

Figure 13-12 Sample Multiprocessor Serial Reception Flowchart

466

<End>

Error processing

Yes

Clear ORER, PER, and

FER flags in SSR to 0

Yes

Framing error processing

Overrun error processing

ORER= 1

FER= 1

Break?

Clear RE bit in SCR to 0

[5]

Figure 13-12 Sample Multiprocessor Serial Reception Flowchart (cont)

467

Figure 13-13 shows an example of SCI operation for multiprocessor format reception.

MPIE

RDR

value

0D0 D1 D7 1 1 0 D0 D1 D7 0 1

1 1

Data (ID1)Start

bit MPB Stop

bit Start

bit Data (Data1) MPB Stop

bit

RXI interrupt

request

(multiprocessor

interrupt)

generated

MPIE = 0

Idle state

(mark state)

RDRF

RDR data read

and RDRF flag

cleared to 0 in

RXI interrupt

service routine

If not this station’s ID,

MPIE bit is set to 1

again

RXI interrupt request is

not generated, and RDR

retains its state

ID1

(a) Data does not match station’s ID

MPIE

RDR

value

0D0 D1 D7 1 1 0 D0 D1 D7 0 1

1 1

Data (ID2)Start

bit MPB Stop

bit Start

bit Data (Data2) MPB Stop

bit

RXI interrupt

request

(multiprocessor

interrupt)

generated

MPIE = 0

Idle state

(mark state)

RDRF

RDR data read and

RDRF flag cleared

to 0 in RXI interrupt

service routine

Matches this station’s ID,

so reception continues, and

data is received in RXI

interrupt service routine

MPIE bit set to 1

again

ID2

(b) Data matches station’s ID

Data2ID1

Figure 13-13 Example of SCI Operation in Reception

(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)

468

13.3.4 Operation in Clocked Synchronous Mode

In clocked synchronous mode, data is transmitted or received in synchronization with clock

pulses, making it suitable for high-speed serial communication.

Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex

communication by use of a common clock. Both the transmitter and the receiver also have a

double-buffered structure, so that data can be read or written during transmission or reception,

enabling continuous data transfer.

Figure 13-14 shows the general format for clocked synchronous serial communication.

Don’t

care

Don’t

care

One unit of transfer data (character or frame)

Bit 0

Serial

data

Serial

clock

Bit 1 Bit 3 Bit 4 Bit 5

LSB MSB

Bit 2 Bit 6 Bit 7

Note: * High except in continuous transfer

Figure 13-14 Data Format in Synchronous Communication

In clocked synchronous serial communication, data on the transmission line is output from one

falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of

the serial clock.

In clocked serial communication, one character consists of data output starting with the LSB and

ending with the MSB. After the MSB is output, the transmission line holds the MSB state.

In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the

serial clock.

Data Transfer Format: A fixed 8-bit data format is used.

No parity or multiprocessor bits are added.

Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial

clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the

CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9.

When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.

469

Eight serial clock pulses are output in the transfer of one character, and when no transfer is

performed the clock is fixed high. When only receive operations are performed, however, the

serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to

perform receive operations in units of one character, you should select an external clock as the

clock source.

Data Transfer Operations:

• SCI initialization (clocked synchronous mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0,

then initialize the SCI as described below.

When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared

to 0 before making the change using the following procedure. When the TE bit is cleared to 0,

the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not

change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

Figure 13-15 shows a sample SCI initialization flowchart.

Wait

Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared

to 0 or set to 1 simultaneously.

Start initialization

Set data transfer format in

SMR and SCMR

Yes

Set value in BRR

Clear TE and RE bits in SCR to 0

[2]

[3]

Set TE and RE bits in SCR to 1, and

set RIE, TIE, TEIE, and MPIE bits [4]

1-bit interval elapsed?

[1]

[1] Set the clock selection in SCR. Be sure

to clear bits RIE, TIE, TEIE, and MPIE,

TE and RE, to 0.

[2] Set the data transfer format in SMR

and SCMR.

[3] Write a value corresponding to the bit

rate to BRR. Not necessary if an

external clock is used.

[4] Wait at least one bit interval, then set

the TE bit or RE bit in SCR to 1.

Also set the RIE, TIE, TEIE, and MPIE

bits.

Setting the TE and RE bits enables the

TxD and RxD pins to be used.

Set CKE1 and CKE0 bits in SCR

(TE, RE bits 0)

Figure 13-15 Sample SCI Initialization Flowchart

470

• Serial data transmission (clocked synchronous mode)

Figure 13-16 shows a sample flowchart for serial transmission.

The following procedure should be used for serial data transmission.

<End>

[1]

Yes

Initialization

Start transmission

Read TDRE flag in SSR [2]

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

Read TEND flag in SSR

[3]

Clear TE bit in SCR to 0

TDRE= 1

All data transmitted?

TEND= 1

[1] SCI initialization:

The TxD pin is automatically

designated as the transmit data output

pin.

[2] SCI status check and transmit data

write:

Read SSR and check that the TDRE

flag is set to 1, then write transmit data

to TDR and clear the TDRE flag to 0.

[3] Serial transmission continuation

procedure:

To continue serial transmission, be

sure to read 1 from the TDRE flag to

confirm that writing is possible, then

write data to TDR, and then clear the

TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request and data is

written to TDR.

Figure 13-16 Sample Serial Transmission Flowchart

471

In serial transmission, the SCI operates as described below.

[1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to

TDR, and transfers the data from TDR to TSR.

[2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts

transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty interrupt

(TXI) is generated.

When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an

external clock has been specified, data is output synchronized with the input clock.

The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with

the MSB (bit 7).

[3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).

If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission

of the next frame is started.

If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the

TxD pin maintains its state.

If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated.

[4] After completion of serial transmission, the SCK pin is fixed high.

Figure 13-17 shows an example of SCI operation in transmission.

Transfer direction

Bit 0

Serial data

Serial clock

1 frame

TDRE

TEND

Bit 1 Bit 7 Bit 0 Bit 1 Bit 7Bit 6

Data written to TDR

and TDRE flag

cleared to 0 in TXI

interrupt service routine

TEI interrupt

request generated

TXI interrupt

request generated

TXI interrupt

request generated

Figure 13-17 Example of SCI Operation in Transmission

472

• Serial data reception (clocked synchronous mode)

Figure 13-18 shows a sample flowchart for serial reception.

The following procedure should be used for serial data reception.

When changing the operating mode from asynchronous to clocked synchronous, be sure to

check that the ORER, PER, and FER flags are all cleared to 0.

The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor

receive operations will be possible.

473

Yes

<End>

[1]

Initialization

Start reception

[2]

Yes

Read RDRF flag in SSR [4]

[5]

Clear RE bit in SCR to 0

Error processing

(Continued below)

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER= 1

RDRF= 1

All data received?

Read ORER flag in SSR

[1]

[2] [3]

[4]

[5]

SCI initialization:

The RxD pin is automatically

designated as the receive data

input pin.

Receive error processing:

If a receive error occurs, read the

ORER flag in SSR , and after

performing the appropriate error

processing, clear the ORER flag

to 0. Transfer cannot be resumed

if the ORER flag is set to 1.

SCI status check and receive

data read:

Read SSR and check that the

RDRF flag is set to 1, then read

the receive data in RDR and

clear the RDRF flag to 0.

Transition of the RDRF flag from

0 to 1 can also be identified by

an RXI interrupt.

Serial reception continuation

procedure:

To continue serial reception,

before the MSB (bit 7) of the

current frame is received, finish

reading the RDRF flag, reading

RDR, and clearing the RDRF flag

to 0. The RDRF flag is cleared

automatically when the DTC is

activated by a receive data full

interrupt (RXI) request and the

RDR value is read.

<End>

Error processing

Overrun error processing

[3]

Clear ORER flag in SSR to 0

Figure 13-18 Sample Serial Reception Flowchart

474

In serial reception, the SCI operates as described below.

[1] The SCI performs internal initialization in synchronization with serial clock input or output.

[2] The received data is stored in RSR in LSB-to-MSB order.

After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be

transferred from RSR to RDR.

If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a

receive error is detected in the error check, the operation is as shown in table 13-11.

Neither transmit nor receive operations can be performed subsequently when a receive error

has been found in the error check.

[3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt

(RXI) request is generated.

Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error

interrupt (ERI) request is generated.

Figure 13-19 shows an example of SCI operation in reception.

Bit 7

Serial

data

Serial

clock

1 frame

RDRF

ORER

Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7

RXI interrupt request

generated RDR data read and

RDRF flag cleared to 0

in RXI interrupt service

routine

RXI interrupt request

generated ERI interrupt request

generated by overrun

error

Figure 13-19 Example of SCI Operation in Reception

• Simultaneous serial data transmission and reception (clocked synchronous mode)

Figure 13-20 shows a sample flowchart for simultaneous serial transmit and receive operations.

The following procedure should be used for simultaneous serial data transmit and receive

operations.

475

Yes

<End>

[1]

Initialization

Start transmission/reception

[5]

Error processing

[3]

Read receive data in RDR, and

clear RDRF flag in SSR to 0

Yes

ORER= 1

All data received?

[2]

Read TDRE flag in SSR

Yes

TDRE= 1

Write transmit data to TDR and

clear TDRE flag in SSR to 0

Yes

RDRF= 1

Read ORER flag in SSR

[4]

Read RDRF flag in SSR

Clear TE and RE bits in SCR to 0

Note: When switching from transmit or receive operation to simultaneous

transmit and receive operations, first clear the TE bit and RE bit to

0, then set both these bits to 1 simultaneously.

[1]

[2]

[3]

[4]

[5]

SCI initialization:

The TxD pin is designated as the

transmit data output pin, and the

RxD pin is designated as the

receive data input pin, enabling

simultaneous transmit and receive

operations.

SCI status check and transmit data

write:

Read SSR and check that the

TDRE flag is set to 1, then write

transmit data to TDR and clear the

TDRE flag to 0.

Transition of the TDRE flag from 0

to 1 can also be identified by a TXI

interrupt.

Receive error processing:

If a receive error occurs, read the

ORER flag in SSR , and after

performing the appropriate error

processing, clear the ORER flag to

0. Transmission/reception cannot be

resumed if the ORER flag is set to

SCI status check and receive data

read:

Read SSR and check that the

RDRF flag is set to 1, then read the

receive data in RDR and clear the

RDRF flag to 0. Transition of the

RDRF flag from 0 to 1 can also be

identified by an RXI interrupt.

Serial transmission/reception

continuation procedure:

To continue serial transmission/

reception, before the MSB (bit 7) of

the current frame is received, finish

reading the RDRF flag, reading

RDR, and clearing the RDRF flag to

0. Also, before the MSB (bit 7) of

the current frame is transmitted,

read 1 from the TDRE flag to

confirm that writing is possible.

Then write data to TDR and clear

the TDRE flag to 0.

Checking and clearing of the TDRE

flag is automatic when the DTC is

activated by a transmit data empty

interrupt (TXI) request and data is

written to TDR. Also, the RDRF flag

is cleared automatically when the

DTC is activated by a receive data

full interrupt (RXI) request and the

RDR value is read.

Figure 13-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

476

13.4 SCI Interrupts

The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt

(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)

request. Table 13-12 shows the interrupt sources and their relative priorities. Individual interrupt

sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of

interrupt request is sent to the interrupt controller independently.

When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag

in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to

perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is

performed by the DTC. The DTC cannot be activated by a TEI interrupt request.

When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,

PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can

activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data

transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.

477

Table 13-12 SCI Interrupt Sources

Channel Interrupt

Source Description DTC

Activation Priority*

0 ERI Interrupt due to receive error (ORER, FER,

or PER) Not possible High

RXI Interrupt due to receive data full state (RDRF) Possible

TXI Interrupt due to transmit data empty state

(TDRE) Possible

TEI Interrupt due to transmission end (TEND) Not possible

1 ERI Interrupt due to receive error (ORER, FER,

or PER) Not possible

RXI Interrupt due to receive data full state (RDRF) Possible

TXI Interrupt due to transmit data empty state

(TDRE) Possible

TEI Interrupt due to transmission end (TEND) Not possible

2 ERI Interrupt due to receive error (ORER, FER,

or PER) Not possible

RXI Interrupt due to receive data full state (RDRF) Possible

TXI Interrupt due to transmit data empty state

(TDRE) Possible

TEI Interrupt due to transmission end (TEND) Not possible Low

Note: *This table shows the initial state immediately after a reset. Relative priorities among

channels can be changed by means of the interrupt controller.

A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The

TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a

TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance,

with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be

accepted in this case.

478

13.5 Usage Notes

The following points should be noted when using the SCI.

Relation between Writes to TDR and the TDRE Flag

The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from

TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.

Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is

written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has

not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1

before writing transmit data to TDR.

Operation when Multiple Receive Errors Occur Simultaneously

If a number of receive errors occur at the same time, the state of the status flags in SSR is as

shown in table 13-13. If there is an overrun error, data is not transferred from RSR to RDR, and

the receive data is lost.

Table 13-13 State of SSR Status Flags and Transfer of Receive Data

SSR Status Flags Receive Data Transfer

RDRF ORER FER PER RSR to RDR Receive Error Status

1100X Overrun error

0010 Framing error

0001 Parity error

1110X Overrun error + framing error

1101X Overrun error + parity error

0011 Framing error + parity error

1111X Overrun error + framing error +

parity error

Notes: : Receive data is transferred from RSR to RDR.

X: Receive data is not transferred from RSR to RDR.

479

Break Detection and Processing (Asynchronous Mode Only): When framing error (FER)

detection is performed, a break can be detected by reading the RxD pin value directly. In a break,

the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag

(PER) may also be set.

Note that, since the SCI continues the receive operation after receiving a break, even if the FER

flag is cleared to 0, it will be set to 1 again.

Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port

whose direction (input or output) is determined by DR and DDR. This can be used to send a break.

Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced

by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1).

Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1.

To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.

When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission

state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.

Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only):

Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if

the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting

transmission.

Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode:

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer

rate.

In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs

internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the

basic clock. This is illustrated in figure 13-21.

480

Internal basic

clock

16 clocks

8 clocks

Receive data

(RxD)

Synchronization

sampling timing

Start bit D0 D1

Data sampling

timing

15 0 7 15 007

Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode

Thus the reception margin in asynchronous mode is given by formula (1) below.

M = | (0.5 – 1

2N ) – (L – 0.5) F – | D – 0.5 |

N (1 + F) | × 100%

... Formula (1)

Where M : Reception margin (%)

N : Ratio of bit rate to clock (N = 16)

D : Clock duty (D = 0 to 1.0)

L : Frame length (L = 9 to 12)

F : Absolute value of clock rate deviation

Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by

formula (2) below.

When D = 0.5 and F = 0,

M = (0.5 – 1

2 × 16 ) × 100%

= 46.875% ... Formula (2)

However, this is only the computed value, and a margin of 20% to 30% should be allowed in

system design.

481

Restrictions on Use of DTC

• When an external clock source is used as the serial clock, the transmit clock should not be

input until at least 5 ø clock cycles after TDR is updated by the DTC. Misoperation may occur

if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 13-22)

• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI

reception end interrupt (RXI).

LSB

Serial data

SCK

D1 D3 D4 D5D2 D6 D7

Note: When operating on an external clock, set t >4 clocks.

TDRE

Figure 13-22 Example of Clocked Synchronous Transmission by DTC

Operation in Case of Mode Transition

• Transmission

Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module

stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition.

TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby

mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and

becomes high-level output after the relevant mode is cleared. If a transition is made during

transmission, the data being transmitted will be undefined. When transmitting without

changing the transmit mode after the relevant mode is cleared, transmission can be started by

setting TE to 1 again, and performing the following sequence: SSR read -> TDR write ->

TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode,

the procedure must be started again from initialization. Figure 13-23 shows a sample flowchart

for mode transition during transmission. Port pin states are shown in figures 13-24 and 13-25.

Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a

transition from transmission by DTC transfer to module stop mode, software standby mode,

watch mode, subactive mode, or subsleep mode transition. To perform transmission with the

DTC after the relevant mode is cleared, setting TE and TIE to 1 will set the TXI flag and start

DTC transmission.

482

• Reception

Receive operation should be stopped (by clearing RE to 0) before making a module stop mode,

software standby mode, watch mode, subactive mode, or subsleep mode transition. RSR,

RDR, and SSR are reset. If a transition is made without stopping operation, the data being

received will be invalid.

To continue receiving without changing the reception mode after the relevant mode is cleared,

set RE to 1 before starting reception. To receive with a different receive mode, the procedure

must be started again from initialization.

Figure 13-26 shows a sample flowchart for mode transition during reception.

Read TEND flag in SSR

TE = 0

Transition to software

standby mode, etc.

Exit from software

standby mode, etc.

Change

operating mode? No

All data

transmitted?

TEND = 1

Yes

[1]

[3]

[2]

TE = 1Initialization

[1] Data being transmitted is interrupted.

After exiting software standby mode,

etc., normal CPU transmission is

possible by setting TE to 1, reading

SSR, writing TDR, and clearing

TDRE to 0, but note that if the DTC

has been activated, the remaining

data in DTCRAM will be transmitted

when TE and TIE are set to 1.

[2] If TIE and TEIE are set to 1, clear

them to 0 in the same way.

[3] Includes module stop mode, watch

mode, subactive mode, and subsleep

mode.

Figure 13-23 Sample Flowchart for Mode Transition during Transmission

483

SCK output pin

TE bit

TxD output pin Port input/output High outputPort input/output High output Start Stop

Start of transmission End of

transmission

Port input/output

SCI TxD output Port SCI TxD

output

Port

Transition

to software

standby

Exit from

software

standby

Figure 13-24 Asynchronous Transmission Using Internal Clock

Port input/output

Last TxD bit held

High output*Port input/output Marking output

Port input/output

SCI TxD output PortPort

Note: * Initialized by software standby.

SCK output pin

TE bit

TxD output pin

SCI TxD

output

Start of transmission End of

transmission

Transition

to software

standby

Exit from

software

standby

Figure 13-25 Synchronous Transmission Using Internal Clock

484

RE = 0

Transition to software

standby mode, etc.

Read receive data in RDR

Read RDRF flag in SSR

Exit from software

standby mode, etc.

Change

operating mode? No

RDRF = 1

Yes

No [1]

[2]

RE = 1Initialization

[1] Receive data being received

becomes invalid.

[2] Includes module stop mode,

watch mode, subactive mode,

and subsleep mode.

Figure 13-26 Sample Flowchart for Mode Transition during Reception

485

Switching from SCK Pin Function to Port Pin Function:

• Problem in Operation: When switching the SCK pin function to the output port function (high-

level output) by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0,

CKE0 = 0, and TE = 1 (synchronous mode), low-level output occurs for one half-cycle.

1. End of serial data transmission

2. TE bit = 0

3. C/A bit = 0 ... switchover to port output

4. Occurrence of low-level output (see figure 13-27)

SCK/port

Data

C/A

CKE1

CKE0

Bit 7Bit 6

1. End of transmission 4. Low-level output

3. C/A = 0

2. TE = 0

Half-cycle low-level output

Figure 13-27 Operation when Switching from SCK Pin Function to Port Pin Function

486

• Sample Procedure for Avoiding Low-Level Output: As this sample procedure temporarily

places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an

external circuit.

With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following

settings in the order shown.

1. End of serial data transmission

2. TE bit = 0

3. CKE1 bit = 1

4. C/A bit = 0 ... switchover to port output

5. CKE1 bit = 0

SCK/port

Data

C/A

CKE1

CKE0

Bit 7Bit 6

1. End of transmission

3. CKE1 = 1 5. CKE1 = 0

4. C/A = 0

2. TE = 0

High-level output

Figure 13-28 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)

487

Section 14 Smart Card Interface

14.1 Overview

The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification

Card) as a serial communication interface extension function.

Switching between the normal serial communication interface and the Smart Card interface is

carried out by means of a register setting.

14.1.1 Features

Features of the Smart Card interface supported by the H8S/2626 Series and H8S/2623 Series are

as follows.

• Asynchronous mode

 Data length: 8 bits

 Parity bit generation and checking

 Transmission of error signal (parity error) in receive mode

 Error signal detection and automatic data retransmission in transmit mode

 Direct convention and inverse convention both supported

• On-chip baud rate generator allows any bit rate to be selected

• Three interrupt sources

 Three interrupt sources (transmit data empty, receive data full, and transmit/receive error)

that can issue requests independently

 The transmit data empty interrupt and receive data full interrupt can activate the data

transfer controller (DTC) to execute data transfer

488

14.1.2 Block Diagram

Figure 14-1 shows a block diagram of the Smart Card interface.

Bus interface

TDR

RSR

RDR

Module data bus

TSR

SCMR

SSR

SCR

Transmission/

reception control

BRR

Baud rate

generator

Internal

data bus

RxD

TxD

SCK

Parity generation

Parity check

Clock

ø/4

ø/16

ø/64

TXI

RXI

ERI

SMR

Legend

SCMR

RSR

RDR

TSR

TDR

SMR

SCR

SSR

BRR

: Smart Card mode register

: Receive shift register

: Receive data register

: Transmit shift register

: Transmit data register

: Serial mode register

: Serial control register

: Serial status register

: Bit rate register

Figure 14-1 Block Diagram of Smart Card Interface

489

14.1.3 Pin Configuration

Table 14-1 shows the Smart Card interface pin configuration.

Table 14-1 Smart Card Interface Pins

Channel Pin Name Symbol I/O Function

0 Serial clock pin 0 SCK0 I/O SCI0 clock input/output

Receive data pin 0 RxD0 Input SCI0 receive data input

Transmit data pin 0 TxD0 Output SCI0 transmit data output

1 Serial clock pin 1 SCK1 I/O SCI1 clock input/output

Receive data pin 1 RxD1 Input SCI1 receive data input

Transmit data pin 1 TxD1 Output SCI1 transmit data output

2 Serial clock pin 2 SCK2 I/O SCI2 clock input/output

Receive data pin 2 RxD2 Input SCI2 receive data input

Transmit data pin 2 TxD2 Output SCI2 transmit data output

490

14.1.4 Register Configuration

Table 14-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR,

TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register

descriptions in section 13, Serial Communication Interface.

Table 14-2 Smart Card Interface Registers

Channel Name Abbreviation R/W Initial Value Address*1

0 Serial mode register 0 SMR0 R/W H'00 H'FF78

Bit rate register 0 BRR0 R/W H'FF H'FF79

Serial control register 0 SCR0 R/W H'00 H'FF7A

Transmit data register 0 TDR0 R/W H'FF H'FF7B

Serial status register 0 SSR0 R/(W)*2H'84 H'FF7C

Receive data register 0 RDR0 R H'00 H'FF7D

Smart card mode

1 Serial mode register 1 SMR1 R/W H'00 H'FF80

Bit rate register 1 BRR1 R/W H'FF H'FF81

Serial control register 1 SCR1 R/W H'00 H'FF82

Transmit data register 1 TDR1 R/W H'FF H'FF83

Serial status register 1 SSR1 R/(W)*2H'84 H'FF84

Receive data register 1 RDR1 R H'00 H'FF85

Smart card mode

2 Serial mode register 2 SMR2 R/W H'00 H'FF88

Bit rate register 2 BRR2 R/W H'FF H'FF89

Serial control register 2 SCR2 R/W H'00 H'FF8A

Transmit data register 2 TDR2 R/W H'FF H'FF8B

Serial status register 2 SSR2 R/(W)*2H'84 H'FF8C

Receive data register 2 RDR2 R H'00 H'FF8D

Smart card mode

All Module stop control

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, for flag clearing.

491

14.2 Register Descriptions

Registers added with the Smart Card interface and bits for which the function changes are

described here.

14.2.1 Smart Card Mode Register (SCMR)

Bit:76543210

— — — — SDIR SINV — SMIF

Initial value : 1 1 1 1 0 0 1 0

R/W : — — — — R/W R/W — R/W

SCMR is an 8-bit readable/writable register that selects the Smart Card interface function.

SCMR is initialized to H'F2 by a reset and in standby mode.

Bits 7 to 4—Reserved: These bits are always read as 1 and cannot be modified.

Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion

format.

Bit 3

SDIR Description

0 TDR contents are transmitted LSB-first (Initial value)

Receive data is stored in RDR LSB-first

1 TDR contents are transmitted MSB-first

Receive data is stored in RDR MSB-first

492

Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This

function is used together with the SDIR bit for communication with an inverse convention card.

The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures,

see section 14.3.4, Register Settings.

Bit 2

SINV Description

0 TDR contents are transmitted as they are (Initial value)

Receive data is stored as it is in RDR

1 TDR contents are inverted before being transmitted

Receive data is stored in inverted form in RDR

Bit 1—Reserved: This bit is always read as 1 and cannot be modified.

Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface

function.

Bit 0

SMIF Description

0 Smart Card interface function is disabled (Initial value)

1 Smart Card interface function is enabled

493

14.2.2 Serial Status Register (SSR)

Bit:76543210

TDRE RDRF ORER ERS PER TEND MPB MPBT

Initial value : 1 0 0 0 0 1 0 0

R/W : R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R R R/W

Note: *Only 0 can be written, for flag clearing.

Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting

conditions for bit 2, TEND, are also different.

Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial

Status Register (SSR).

Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the

error signal sent back from the receiving end in transmission. Framing errors are not detected in

Smart Card interface mode.

Bit 4

ERS Description

0 Normal reception, with no error signal

[Clearing conditions] (Initial value)

• Upon reset, and in standby mode or module stop mode

• When 0 is written to ERS after reading ERS = 1

1 Error signal sent from receiver indicating detection of parity error

[Setting condition]

When the low level of the error signal is sampled

Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous

state.

494

Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial

Status Register (SSR).

However, the setting conditions for the TEND bit, are as shown below.

Bit 2

TEND Description

0 Transmission is in progress

[Clearing conditions]

• When 0 is written to TDRE after reading TDRE = 1

• When the DTC is activated by a TXI interrupt and write data to TDR

1 Transmission has ended (Initial value)

[Setting conditions]

• Upon reset, and in standby mode or module stop mode

• When the TE bit in SCR is 0 and the ERS bit is also 0

• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a

1-byte serial character when GM = 0 and BLK = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.5 etu after transmission of a

1-byte serial character when GM = 0 and BLK = 1

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1 and BLK = 0

• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a

1-byte serial character when GM = 1 and BLK = 1

Note: etu: Elementary Time Unit (time for transfer of 1 bit)

495

14.2.3 Serial Mode Register (SMR)

Bit:76543210

GM BLK PE O/EBCP1 BCP0 CKS1 CKS0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Note: When the smart card interface is used, be sure to make the 1 setting shown for bit 5.

The function of bits 7, 6, 3, and 2 of SMR changes in Smart Card interface mode.

Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode.

This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set

to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced

and clock output control mode addition is performed. The contents of the clock output control

mode addition are specified by bits 1 and 0 of the serial control register (SCR).

Bit 7

GM Description

0 Normal smart card interface mode operation (Initial value)

• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of

start bit

• Clock output ON/OFF control only

1 GSM mode smart card interface mode operation

• TEND flag generation 11.0 etu after beginning of start bit

• High/low fixing control possible in addition to clock output ON/OFF control (set by

SCR)

Note: etu: Elementary time unit (time for transfer of 1 bit)

496

Bit 6—Block Transfer Mode (BLK): Selects block transfer mode.

Bit 6

BLK Description

0 Normal Smart Card interface mode operation

• Error signal transmission/detection and automatic data retransmission performed

• TXI interrupt generated by TEND flag

• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)

1 Block transfer mode operation

• Error signal transmission/detection and automatic data retransmission not

performed

• TXI interrupt generated by TDRE flag

• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)

Bits 3 and 2—Basic Clock Pulse 1 and 2 (BCP1, BCP0): These bits specify the number of basic

clock periods in a 1-bit transfer interval on the Smart Card interface.

Bit 3 Bit 2

BCP1 BCP0 Description

0 1 32 clock periods (Initial value)

0 64 clock periods

1 1 372 clock periods

0 256 clock periods

Bits 5, 4, 1, and 0: Operate in the same way as for the normal SCI. For details, see section 13.2.5,

serial mode register (SMR).

497

14.2.4 Serial Control Register (SCR)

Bit:76543210

TIE RIE TE RE MPIE TEIE CKE1 CKE0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial

mode register (SMR) is set to 1.

Bits 7 to 2—Operate in the same way as for the normal SCI.

For details, see section 13.2.6, Serial Control Register (SCR).

Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock

source and enable or disable clock output from the SCK pin.

In smart card interface mode, in addition to the normal switching between clock output enabling

and disabling, the clock output can be specified as to be fixed high or low.

SCMR SMR SCR Setting

SMIF C/A, GM CKE1 CKE0 SCK Pin Function

0 See the SCI

1 0 0 0 Operates as port I/O pin

1 0 0 1 Outputs clock as SCK output pin

1 1 0 0 Operates as SCK output pin, with output fixed

low

1 1 0 1 Outputs clock as SCK output pin

1 1 1 0 Operates as SCK output pin, with output fixed

high

1 1 1 1 Outputs clock as SCK output pin

498

14.3 Operation

14.3.1 Overview

The main functions of the Smart Card interface are as follows.

• One frame consists of 8-bit data plus a parity bit.

• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of

one bit) is left between the end of the parity bit and the start of the next frame.

• If a parity error is detected during reception, a low error signal level is output for one etu

period, 10.5 etu after the start bit.

• If the error signal is sampled during transmission, the same data is transmitted automatically

after the elapse of 2 etu or longer. (except in block transfer mode)

• Only asynchronous communication is supported; there is no clocked synchronous

communication function.

14.3.2 Pin Connections

Figure 14-2 shows a schematic diagram of Smart Card interface related pin connections.

In communication with an IC card, since both transmission and reception are carried out on a

single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The

data transmission line should be pulled up to the VCC power supply with a resistor.

When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is

input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock.

LSI port output is used as the reset signal.

Other pins must normally be connected to the power supply or ground.

499

TxD

RxD

SCK

Rx (port)

H8S/2626 Series or

H8S/2623 Series

I/O

CLK

RST

VCC

Connected equipment

IC card

Data line

Clock line

Reset line

Figure 14-2 Schematic Diagram of Smart Card Interface Pin Connections

Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed

transmission/reception is possible, enabling self-diagnosis to be carried out.

500

14.3.3 Data Format

(1) Normal Transfer Mode

Figure 14-3 shows the normal Smart Card interface data format. In reception in this mode, a parity

check is carried out on each frame, and if an error is detected an error signal is sent back to the

transmitting end, and retransmission of the data is requested. If an error signal is sampled during

transmission, the same data is retransmitted.

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When there is no parity error

Transmitting station output

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

When a parity error occurs

Transmitting station output

Receiving station

output

: Start bit

: Data bits

: Parity bit

: Error signal

Legend

D0 to D7

Figure 14-3 Normal Smart Card Interface Data Format

501

The operation sequence is as follows.

[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start

bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

[4] The receiving station carries out a parity check.

If there is no parity error and the data is received normally, the receiving station waits for

reception of the next data.

If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)

to request retransmission of the data. After outputting the error signal for the prescribed length

of time, the receiving station places the signal line in the high-impedance state again. The

signal line is pulled high again by a pull-up resistor.

[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data

frame.

If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous

data.

(2) Block Transfer Mode

The operation sequence in block transfer mode is as follows.

[1] When the data line in not in use it is in the high-impedance state, and is fixed high with a pull-

up resistor.

[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start

bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

[3] With the Smart Card interface, the data line then returns to the high-impedance state. The data

line is pulled high with a pull-up resistor.

[4] After reception, a parity error check is carried out, but an error signal is not output even if an

error has occurred. When an error occurs reception cannot be continued, so the error flag

should be cleared to 0 before the parity bit of the next frame is received.

[5] The transmitting station proceeds to transmit the next data frame.

502

14.3.4 Register Settings

Table 14-3 shows a bit map of the registers used by the smart card interface.

Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described

below.

Table 14-3 Smart Card Interface Register Settings

Bit

SMR GM BLK 1 O/EBCP1 BCP0 CKS1 CKS0

BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0

SCR TIE RIE TE RE 0 0 CKE1*CKE0

TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0

SSR TDRE RDRF ORER ERS PER TEND 0 0

RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0

SCMR ————SDIR SINV — SMIF

Notes: — : Unused bit.

*: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0.

SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in

GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1

if of the inverse convention type.

Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. Bits BCP1 and

BCP0 select the number of basic clock periods in a 1-bit transfer interval. For details, see section

14.3.5, Clock.

The BLK bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer

mode.

BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of

calculating the value to be set.

SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.

For details, see section 13, Serial Communication Interface.

Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these

bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in

SMR is set to 1, clock output is performed. The clock output can also be fixed high or low.

503

Smart Card Mode Register (SCMR) Setting:

The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the

inverse convention type.

The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the

inverse convention type.

The SMIF bit is set to 1 in the case of the Smart Card interface.

Examples of register settings and the waveform of the start character are shown below for the two

types of IC card (direct convention and inverse convention).

• Direct convention (SDIR = SINV = O/E = 0)

Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp

AZZAZZZAAZ(Z) (Z) State

With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to

state A, and transfer is performed in LSB-first order. The start character data above is H'3B.

The parity bit is 1 since even parity is stipulated for the Smart Card.

• Inverse convention (SDIR = SINV = O/E = 1)

Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp

AZZAAAAAAZ(Z) (Z) State

With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level

to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F.

The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card.

With the H8S/2626 Series and H8S/2623 Series, inversion specified by the SINV bit applies

only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity

mode (the same applies to both transmission and reception).

504

14.3.5 Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the

transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1,

CKS0, BCP1 and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below.

Table 14-5 shows some sample bit rates.

If clock output is selected by setting CKE0 to 1, a clock is output from the SCK pin. The clock

frequency is determined by the bit rate and the setting of bits BCP1 and BCP0.

B = ø

S × 22n+1 × (N + 1) × 106

Where: N = Value set in BRR (0 ≤ N ≤ 255)

B = Bit rate (bit/s)

ø = Operating frequency (MHz)

n = See table 14-4

S = Number of internal clocks in 1-bit period, set by BCP1 and BCP0

Table 14-4 Correspondence between n and CKS1, CKS0

n CKS1 CKS0

000

210

Table 14-5 Examples of Bit Rate B (bit/s) for Various BRR Settings

(When n = 0 and S = 372)

ø (MHz)

N 10.00 10.714 13.00 14.285 16.00 18.00 20.00

0 13441 14400 17473 19200 21505 24194 26882

1 6720 7200 8737 9600 10753 12097 13441

2 4480 4800 5824 6400 7168 8065 8961

Note: Bit rates are rounded to the nearest whole number.

505

The method of calculating the value to be set in the bit rate register (BRR) from the operating

frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the

smaller error is specified.

N = ø

S × 22n+1 × B × 106 – 1

Table 14-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0 and S = 372)

ø (MHz)

7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00

bit/s N Error N Error N Error N Error N Error N Error N Error N Error

9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99 2 6.60

Table 14-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)

(when S = 372)

ø (MHz) Maximum Bit Rate (bit/s) N n

7.1424 9600 0 0

10.00 13441 0 0

10.7136 14400 0 0

13.00 17473 0 0

14.2848 19200 0 0

16.00 21505 0 0

18.00 24194 0 0

20.00 26882 0 0

The bit rate error is given by the following formula:

Error (%) = ( ø

S × 22n+1 × B × (N + 1) × 106 – 1) × 100

506

14.3.6 Data Transfer Operations

Initialization: Before transmitting and receiving data, initialize the SCI as described below.

Initialization is also necessary when switching from transmit mode to receive mode, or vice versa.

[1] Clear the TE and RE bits in SCR to 0.

[2] Clear the error flags ERS, PER, and ORER in SSR to 0.

[3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, CKS0 bits in SMR. Set the PE bit to 1.

[4] Set the SMIF, SDIR, and SINV bits in SCMR.

When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,

and are placed in the high-impedance state.

[5] Set the value corresponding to the bit rate in BRR.

[6] Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.

If the CKE0 bit is set to 1, the clock is output from the SCK pin.

[7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE

bit and RE bit at the same time, except for self-diagnosis.

507

Serial Data Transmission: As data transmission in smart card mode involves error signal

sampling and retransmission processing, the processing procedure is different from that for the

normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation

between a transmit operation and the internal registers.

[1] Perform Smart Card interface mode initialization as described above in Initialization.

[2] Check that the ERS error flag in SSR is cleared to 0.

[3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1.

[4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation.

The TEND flag is cleared to 0.

[5] When transmitting data continuously, go back to step [2].

[6] To end transmission, clear the TE bit to 0.

With the above processing, interrupt servicing or data transfer by the DTC is possible.

If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt

requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error

occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt

requests are enabled, a transfer error interrupt (ERI) request will be generated.

The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND

flag set timing is shown in figure 14-6.

If the DTC is activated by a TXI request, the number of bytes set in the DTC can be transmitted

automatically, including automatic retransmission.

For details, see Interrupt Operation and Data Transfer Operation by DTC below.

Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.

508

Initialization

Yes

Clear TE bit to 0

Start transmission

Start

Yes

End

Write data to TDR,

and clear TDRE flag

in SSR to 0

Error processing

TEND=1?

All data transmitted?

TEND=1?

ERS=0?

Figure 14-4 Example of Transmission Processing Flow

509

(1) Data write

TDR TSR

(shift register)

Data 1

(2) Transfer from

TDR to TSR Data 1 Data 1 ; Data remains in TDR

(3) Serial data output

Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first

transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has

been completed.

In case of normal transmission: TEND flag is set

In case of transmit error: ERS flag is set

Steps (2) and (3) above are repeated until the TEND flag is set

I/O signal line output

Data 1 Data 1

Figure 14-5 Relation Between Transmit Operation and Internal Registers

Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data

12.5etu

TXI

(TEND interrupt)

11.0etu

Guard

time

When GM = 1

Legend

Ds : Start bit

D0 to D7 : Data bits

Dp : Parity bit

DE : Error signal

When GM = 0

Figure 14-6 TEND Flag Generation Timing in Transmission Operation

510

Serial Data Reception (Except Block Transfer Mode): Data reception in Smart Card mode uses

the same processing procedure as for the normal SCI. Figure 14-7 shows an example of the

transmission processing flow.

[1] Perform Smart Card interface mode initialization as described above in Initialization.

[2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the

appropriate receive error processing, then clear both the ORER and the PER flag to 0.

[3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1.

[4] Read the receive data from RDR.

[5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2].

[6] To end reception, clear the RE bit to 0.

Initialization

Read RDR and clear

RDRF flag in SSR to 0

Clear RE bit to 0

Start reception

Start

Error processing

Yes

ORER = 0 and

PER = 0

RDRF=1?

All data received?

Yes

Figure 14-7 Example of Reception Processing Flow

511

With the above processing, interrupt servicing or data transfer by the DTC is possible.

If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests

are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in

reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI)

request will be generated.

If the DTC is activated by an RXI request, the receive data in which the error occurred is skipped,

and only the number of bytes of receive data set in the DTC are transferred.

For details, see Interrupt Operation and Data Transfer Operation by DTC below.

If a parity error occurs during reception and the PER is set to 1, the received data is still

transferred to RDR, and therefore this data can be read.

Note: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.

Mode Switching Operation: When switching from receive mode to transmit mode, first confirm

that the receive operation has been completed, then start from initialization, clearing RE bit to 0

and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the

receive operation has been completed.

When switching from transmit mode to receive mode, first confirm that the transmit operation has

been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The

TEND flag can be used to check that the transmit operation has been completed.

Fixing Clock Output Level: When the GM bit in SMR is set to 1, the clock output level can be

fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be

made the specified width.

Figure 14-8 shows the timing for fixing the clock output level. In this example, GSM is set to 1,

CKE1 is cleared to 0, and the CKE0 bit is controlled.

SCK

Specified pulse width

SCR write

(CKE0 = 0) SCR write

(CKE0 = 1)

Specified pulse width

Figure 14-8 Timing for Fixing Clock Output Level

Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart

card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI)

512

requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is

not used in this mode.

When the TEND flag in SSR is set to 1, a TXI interrupt request is generated.

When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated.

When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.

The relationship between the operating states and interrupt sources is shown in table 14-8.

Note: For block transfer mode, see section 13.4, SCI Interrupts.

Table 14-8 Smart Card Mode Operating States and Interrupt Sources

Operating State Flag Enable Bit Interrupt Source DTC Activation

Transmit

Mode Normal

operation TEND TIE TXI Possible

Error ERS RIE ERI Not possible

Receive

Mode Normal

operation RDRF RIE RXI Possible

Error PER, ORER RIE ERI Not possible

Data Transfer Operation by DTC: In smart card mode, as with the normal SCI, transfer can be

carried out using the DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time

as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated

beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer

of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0

when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the same

data automatically. During this period, TEND remains cleared to 0 and the DTC is not activated.

Therefore, the SCI and DTC will automatically transmit the specified number of bytes, including

retransmission in the event of an error. However, the ERS flag is not cleared automatically when

an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be

generated in the event of an error, and the ERS flag will be cleared.

When performing transfer using the DTC, it is essential to set and enable the DTC before carrying

out SCI setting. For details of the DTC setting procedures, see section 8, Data Transfer Controller

(DTC).

In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to

1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be

activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is

cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an error

flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI

interrupt request is sent to the CPU. Therefore, the error flag should be cleared.

513

Note: For block transfer mode, see section 13.4, SCI Interrupts.

14.3.7 Operation in GSM Mode

Switching the Mode: When switching between smart card interface mode and software standby

mode, the following switching procedure should be followed in order to maintain the clock duty.

• When changing from smart card interface mode to software standby mode

[1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to

the value for the fixed output state in software standby mode.

[2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive

operation. At the same time, set the CKE1 bit to the value for the fixed output state in software

standby mode.

[3] Write 0 to the CKE0 bit in SCR to halt the clock.

[4] Wait for one serial clock period.

During this interval, clock output is fixed at the specified level, with the duty preserved.

[5] Make the transition to the software standby state.

• When returning to smart card interface mode from software standby mode

[6] Exit the software standby state.

[7] Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the

normal duty.

[1] [2] [3] [4] [5] [6] [7]

Software

standby

Normal operation Normal operation

Figure 14-9 Clock Halt and Restart Procedure

514

Powering On: To secure the clock duty from power-on, the following switching procedure should

be followed.

[1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor

to fix the potential.

[2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR.

[3] Set SMR and SCMR, and switch to smart card mode operation.

[4] Set the CKE0 bit in SCR to 1 to start clock output.

14.3.8 Operation in Block Transfer Mode

Operation in block transfer mode is the same as in SCI asynchronous mode, except for the

following points. For details, see section 13.3.2, Operation in Asynchronous Mode.

(1) Data Format

The data format is 8 bits with parity. There is no stop bit, but there is a 2-bit (1-bit or more in

reception) error guard time.

Also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go

to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor.

(2) Transmit/Receive Clock

Only an internal clock generated by the on-chip baud rate generator can be used as the

transmit/receive clock. The number of basic clock periods in a 1-bit transfer interval can be set to

32, 64, 372, or 256 with bits BCP1 and BCP0. For details, see section 14.3.5, Clock.

(3) ERS (FER) Flag

As with the normal Smart Card interface, the ERS flag indicates the error signal status, but since

error signal transmission and reception is not performed, this flag is always cleared to 0.

515

14.4 Usage Notes

The following points should be noted when using the SCI as a Smart Card interface.

Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In

Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, or

256 times the transfer rate (as determined by bits BCP1 and BCP0).

In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs

internal synchronization. Receive data is latched internally at the rising edge of the 16th, 32nd,

186th, or 128th pulse of the basic clock. Figure 14-10 shows the receive data sampling timing

when using a clock of 372 times the transfer rate.

Internal

basic

clock

372 clocks

186 clocks

Receive

data (RxD)

Synchro-

nization

sampling

timing

D0 D1

Data

sampling

timing

185 371 0

371

185 0

Start bit

Figure 14-10 Receive Data Sampling Timing in Smart Card Mode

(Using Clock of 372 Times the Transfer Rate)

516

Thus the reception margin in asynchronous mode is given by the following formula.

Formula for reception margin in smart card interface mode

M = (0.5 – 1

2N ) – (L – 0.5) F –  D – 0.5

N (1 + F) × 100%

Where M: Reception margin (%)

N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)

D: Clock duty (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute value of clock frequency deviation

Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin

formula is as follows.

When D = 0.5 and F = 0,

M = (0.5 – 1/2 × 372) × 100%

= 49.866%

Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by

the SCI in receive mode and transmit mode as described below.

• Retransfer operation when SCI is in receive mode

Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode.

[1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically

set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The

PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.

[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.

[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.

[4] If no error is found when the received parity bit is checked, the receive operation is judged to

have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE

bit in SCR is enabled at this time, an RXI interrupt request is generated.

If DTC data transfer by an RXI source is enabled, the contents of RDR can be read

automatically. When the RDR data is read by the DTC, the RDRF flag is automatically cleared

to 0.

[5] When a normal frame is received, the pin retains the high-impedance state at the timing for

error signal transmission.

517

D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp(DE)DsD0D1D2D3D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

RDRF

[1]

PER

[2]

[3]

[4]

Figure 14-11 Retransfer Operation in SCI Receive Mode

• Retransfer operation when SCI is in transmit mode

Figure 14-12 illustrates the retransfer operation when the SCI is in transmit mode.

[6] If an error signal is sent back from the receiving end after transmission of one frame is

completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI

interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next

parity bit is sampled.

[7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality

is received.

[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.

[9] If an error signal is not sent back from the receiving end, transmission of one frame, including

a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE

bit in SCR is enabled at this time, a TXI interrupt request is generated.

If data transfer by the DTC by means of the TXI source is enabled, the next data can be written

to TDR automatically. When data is written to TDR by the DTC, the TDRE bit is

automatically cleared to 0.

D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp (DE) DsD0D1D2D3D4Ds

Transfer

frame n+1

Retransferred framenth transfer frame

TDRE

TEND

[6]

FER/ERS

Transfer to TSR from TDR

[7] [9]

[8]

Transfer to TSR from TDR Transfer to TSR

from TDR

Figure 14-12 Retransfer Operation in SCI Transmit Mode

518

519

Section 15 Hitachi Controller Area Network (HCAN)

15.1 Overview

The HCAN is a module for controlling a controller area network (CAN) for realtime

communication in vehicular and industrial equipment systems, etc. The H8S/2626 Series and

H8S/2623 Series have a single-channel on-chip HCAN module.

Reference: BOSCH CAN Specification Version 2.0 1991, Robert Bosch GmbH

15.1.1 Features

• CAN version: Bosch 2.0B active compatible

 Communication systems:

NRZ (Non-Return to Zero) system (with bit-stuffing function)

Broadcast communication system

 Transmission path: Bidirectional 2-wire serial communication

 Communication speed: Max. 1 Mbps

 Data length: 0 to 8 bytes

• Number of channels: 1

• Data buffers: 16 (one receive-only buffer and 15 buffers settable for transmission/reception)

• Data transmission: Choice of two methods:

 Mailbox (buffer) number order (low-to-high)

 Message priority (identifier) high-to-low order

• Data reception: Two methods:

 Message identifier match (transmit/receive-setting buffers)

 Reception with message identifier masked (receive-only)

• CPU interrupts: Five interrupt vectors:

 Error interrupt

 Reset processing interrupt

 Message reception interrupt (mailbox 1 to 15)

 Message reception interrupt (mailbox 0)

 Message transmission interrupt

• HCAN operating modes: Support for various modes:

 Hardware reset

 Software reset

 Normal status (error-active, error-passive)

 Bus off status

520

 HCAN configuration mode

 HCAN sleep mode

 HCAN halt mode

• Other features: DTC can be activated by message reception mailbox (HCAN mailbox 0 only)

15.1.2 Block Diagram

Figure 15-1 shows a block diagram of the HCAN.

Peripheral address bus

Peripheral data bus

HTxD

MBI

Message buffer

HRxD

MPI

Microprocessor interface

(CDLC)

CAN

Data Link Controller

Bosch CAN 2.0B active

CPU interface

Control register

Status register

HCAN

Tx buffer

Rx buffer

Message control

Message data

MC0–MC15, MD0–MD15

LAFM

Mailboxes

Figure 15-1 HCAN Block Diagram

Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter

mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.) Transmit messages

are written by the CPU. For receive messages, the data received by the CDLC is stored

automatically.

Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status

CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of

messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames,

error frames, overload frames, inter-frame spacing), as well as CRC checking, bus arbitration, and

other functions.

521

15.1.3 Pin Configuration

Table 15-1 shows the HCAN’s pins.

When using HCAN pins, settings must be made in the HCAN configuration mode (during

initialization: MCR0 = 1 and GSR3 = 1).

Table 15-1 HCAN Pins

Name Abbreviation Input/Output Function

HCAN transmit data pin HTxD Output CAN bus transmission pin

HCAN receive data pin HRxD Input CAN bus reception pin

A bus driver is necessary between the pins and the CAN bus. A Philips PCA82C250 compatible

model is recommended.

522

15.1.4 Register Configuration

Table 15-2 lists the HCAN’s registers.

Table 15-2 HCAN Registers

Name Abbreviation R/W Initial Value Address*Access Size

Master control register MCR R/W H'01 H'F800 8 bits 16 bits

General status register GSR R/W H'0C H'F801 8 bits

Bit configuration register BCR R/W H'0000 H'F802 8/16 bits

Mailbox configuration register MBCR R/W H'0100 H'F804 8/16 bits

Transmit wait register TXPR R/W H'0000 H'F806 8/16 bits

Transmit wait cancel register TXCR R/W H'0000 H'F808 8/16 bits

Transmit acknowledge register TXACK R/W H'0000 H'F80A 8/16 bits

Abort acknowledge register ABACK R/W H'0000 H'F80C 8/16 bits

Receive complete register RXPR R/W H'0000 H'F80E 8/16 bits

Remote request register RFPR R/W H'0000 H'F810 8/16 bits

Interrupt register IRR R/W H'0100 H'F812 8/16 bits

Mailbox interrupt mask register MBIMR R/W H'FFFF H'F814 8/16 bits

Interrupt mask register IMR R/W H'FEFF H'F816 8/16 bits

Receive error counter REC R H'00 H'F818 8 bits 16 bits

Transmit error counter TEC R H'00 H'F819 8 bits

Unread message status register UMSR R/W H'0000 H'F81A 8/16 bits

Local acceptance filter mask L LAFML R/W H'0000 H'F81C 8/16 bits

Local acceptance filter mask H LAFMH R/W H'0000 H'F81E 8/16 bits

523

Name Abbreviation R/W Initial Value Address*Access Size

Message control 0 [1:8] MC0 [1:8] R/W Undefined H'F820 8/16 bits

Message control 1 [1:8] MC1 [1:8] R/W Undefined H'F828 8/16 bits

Message control 2 [1:8] MC2 [1:8] R/W Undefined H'F830 8/16 bits

Message control 3 [1:8] MC3 [1:8] R/W Undefined H'F838 8/16 bits

Message control 4 [1:8] MC4 [1:8] R/W Undefined H'F840 8/16 bits

Message control 5 [1:8] MC5 [1:8] R/W Undefined H'F848 8/16 bits

Message control 6 [1:8] MC6 [1:8] R/W Undefined H'F850 8/16 bits

Message control 7 [1:8] MC7 [1:8] R/W Undefined H'F858 8/16 bits

Message control 8 [1:8] MC8 [1:8] R/W Undefined H'F860 8/16 bits

Message control 9 [1:8] MC9 [1:8] R/W Undefined H'F868 8/16 bits

Message control 10 [1:8] MC10 [1:8] R/W Undefined H'F870 8/16 bits

Message control 11 [1:8] MC11 [1:8] R/W Undefined H'F878 8/16 bits

Message control 12 [1:8] MC12 [1:8] R/W Undefined H'F880 8/16 bits

Message control 13 [1:8] MC13 [1:8] R/W Undefined H'F888 8/16 bits

Message control 14 [1:8] MC14 [1:8] R/W Undefined H'F890 8/16 bits

Message control 15 [1:8] MC15 [1:8] R/W Undefined H'F898 8/16 bits

Message data 0 [1:8] MD0 [1:8] R/W Undefined H'F8B0 8/16 bits

Message data 1 [1:8] MD1 [1:8] R/W Undefined H'F8B8 8/16 bits

Message data 2 [1:8] MD2 [1:8] R/W Undefined H'F8C0 8/16 bits

Message data 3 [1:8] MD3 [1:8] R/W Undefined H'F8C8 8/16 bits

Message data 4 [1:8] MD4 [1:8] R/W Undefined H'F8D0 8/16 bits

Message data 5 [1:8] MD5 [1:8] R/W Undefined H'F8D8 8/16 bits

Message data 6 [1:8] MD6 [1:8] R/W Undefined H'F8E0 8/16 bits

Message data 7 [1:8] MD7 [1:8] R/W Undefined H'F8E8 8/16 bits

Message data 8 [1:8] MD8 [1:8] R/W Undefined H'F8F0 8/16 bits

Message data 9 [1:8] MD9 [1:8] R/W Undefined H'F8F8 8/16 bits

Message data 10 [1:8] MD10 [1:8] R/W Undefined H'F900 8/16 bits

Message data 11 [1:8] MD11 [1:8] R/W Undefined H'F908 8/16 bits

Message data 12 [1:8] MD12 [1:8] R/W Undefined H'F910 8/16 bits

Message data 13 [1:8] MD13 [1:8] R/W Undefined H'F918 8/16 bits

Message data 14 [1:8] MD14 [1:8] R/W Undefined H'F920 8/16 bits

Message data 15 [1:8] MD15 [1:8] R/W Undefined H'F928 8/16 bits

Module stop control

Note: *Lower 16 bits of the address.

524

15.2 Register Descriptions

15.2.1 Master Control Register (MCR)

The master control register (MCR) is an 8-bit readable/writable register that controls the CAN

interface.

MCR

Bit: 7 6 5 4 3 2 1 0

MCR7 — MCR5 — — MCR2 MCR1 MCR0

Initial value: 0 0 0 0 0 0 0 1

R/W: R/W R R/W R R R/W R/W R/W

Bit 7—HCAN Sleep Mode Release (MCR7): Enables or disables HCAN sleep mode release by

bus operation.

Bit 7: MCR7 Description

0 HCAN sleep mode release by CAN bus operation disabled (Initial value)

1 HCAN sleep mode release by CAN bus operation enabled

Bit 6—Reserved: This bit always reads 0. The write value should always be 0.

Bit 5—HCAN Sleep Mode (MCR5): Enables or disables HCAN sleep mode transition.

Bit 5: MCR5 Description

0 HCAN sleep mode released (Initial value)

1 Transition to HCAN sleep mode enabled

Bits 4 and 3—Reserved: These bits always read 0. The write value should always be 0.

Bit 2—Message Transmission Method (MCR2): Selects the transmission method for transmit

messages.

Bit 2: MCR2 Description

0 Transmission order determined by message identifier priority (Initial value)

1 Transmission order determined by mailbox (buffer) number priority

(TXPR1 > TXPR15)

525

Bit 1—Halt Request (MCR1): Controls halting of the HCAN module.

Bit 1: MCR1 Description

0 HCAN normal operating mode (Initial value)

1 HCAN halt mode transition request

Bit 0—Reset Request (MCR0): Controls resetting of the HCAN module.

Bit 0: MCR0 Description

0 Normal operating mode (MCR0 = 0 and GSR3 = 0)

[Setting condition]

When 0 is written after an HCAN reset

1 HCAN reset mode transition request (Initial value)

In order for GSR3 to change from 1 to 0 after 0 is written to MCR0, time is required before the

HCAN is internally reset. There is consequently a delay before GSR3 is cleared to 0 after MCR0

is cleared to 0.

15.2.2 General Status Register (GSR)

The general status register (GSR) is an 8-bit readable/writable register that indicates the status of

the CAN bus.

GSR

Bit: 7 6 5 4 3 2 1 0

— — — — GSR3 GSR2 GSR1 GSR0

Initial value: 0 0 0 0 1 1 0 0

R/W: R R R R R R R R

Bits 7 to 4—Reserved: These bits always read 0. The write value should always be 0.

526

Bit 3—Reset Status Bit (GSR3): Indicates whether the HCAN module is in the normal operating

state or the reset state. Writes are invalid.

Bit 3: GSR3 Description

0 Normal operating state

[Setting condition]

After an HCAN internal reset

1 Configuration mode

[Reset condition]

MCR0 reset mode and sleep mode (Initial value)

Bit 2—Message Transmission Status Flag (GSR2): Flag that indicates whether the module is

currently in the message transmission period. The “message transmission period” is the period

from the start of message transmission (SOF) until the end of a 3-bit intermission interval after

EOF (End of Frame). Writes are invalid.

Bit 2: GSR2 Description

0 Message transmission period

1 [Reset Condition]

Idle period (Initial value)

Bit 1—Transmit/Receive Warning Flag (GSR1): Flag that indicates an error warning. Writes

are invalid.

Bit 1: GSR1 Description

0 [Reset condition]

When TEC < 96 and REC < 96 or TEC ≥ 256 (Initial value)

1 When TEC ≥ 96 or REC ≥ 96

Bit 0—Bus Off Flag (GSR0): Flag that indicates the bus off state. Writes are invalid.

Bit 0: GSR0 Description

0 [Reset condition]

Recovery from bus off state (Initial value)

1 When TEC ≥ 256 (bus off state)

527

15.2.3 Bit Configuration Register (BCR)

The bit configuration register (BCR) is a 16-bit readable/writable register that is used to set CAN

bit timing parameters and the baud rate prescaler.

BCR

Bit: 15 14 13 12 11 10 9 8

BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 and 14—Resynchronization Jump Width (SJW): These bits set the bit synchronization

range.

Bit 15:

BCR7 Bit 14:

BCR6 Description

0 0 Bit synchronization width = 1 time quantum (Initial value)

1 Bit synchronization width = 2 time quanta

1 0 Bit synchronization width = 3 time quanta

1 Bit synchronization width = 4 time quanta

Bits 13 to 8—Baud Rate Prescaler (BRP): These bits are used to set the CAN bus baud rate.

Bit 13:

BCR5 Bit 12:

BCR4 Bit 11:

BCR3 Bit 10:

BCR2 Bit 9:

BCR1 Bit 8:

BCR0 Description

0000002 × system clock (Initial value)

0000014 × system clock

0000106 × system clock

⋅

111111128 × system clock

528

SYNC_SEG PRSEG PHSEG1 PHSEG2

1-bit time

Legend

Note: *The Time Quanta value for TSEG1 and TSEG2 is the TSEG value + 1.

1-bit time (8–25 time quanta)

Quantum

1 TSEG1 (time segment 1)*

2–16

TSEG2 (time segment 2)

2–8

SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal

bit edge transitions occur in this segment.)

PRSEG: Segment for compensating for physical delay between networks.

PHSEG1: Buffer segment for correcting phase drift (positive). (This segment is extended

when synchronization (resynchronization) is established.)

PHSEG2: Buffer segment for correcting phase drift (negative). (This segment is

shortened when synchronization (resynchronization) is established.)

Figure 15-2 Detailed Description of One Bit

HCAN bit rate calculation:

fCLK

2 × (BRP + 1) × (1 + TSEG1 + TSEG2)

Bit rate =

Note: fCLK = ø (system clock)

The BCR values are used for BRP, TSEG1, and TSEG2.

BCR Setting Constraints

TSEG1 > TSEG2 ≥ SJW (SJW = 1 to 4)

1 + TSEG1 + TSEG2 = 8 to 25 time quanta

These constraints allow the setting range shown in table 15-3 for TSEG1 and TSEG2 in BCR.

529

Table 15-3 Setting Range for TSEG1 and TSEG2 in BCR

TSEG2 (BCR [14:12])

001 010 011 100 101 110 111

Value 2345678

TSEG1 0011 4 No Yes No No No No No

(BCR [11:8]) 0100 5 Yes*Yes Yes No No No No

0101 6 Yes*Yes Yes Yes No No No

0110 7 Yes*Yes Yes Yes Yes No No

0111 8 Yes*Yes Yes Yes Yes Yes No

1000 9 Yes*Yes Yes Yes Yes Yes Yes

1001 10 Yes*Yes Yes Yes Yes Yes Yes

1010 11 Yes*Yes Yes Yes Yes Yes Yes

1011 12 Yes*Yes Yes Yes Yes Yes Yes

1100 13 Yes*Yes Yes Yes Yes Yes Yes

1101 14 Yes*Yes Yes Yes Yes Yes Yes

1110 15 Yes*Yes Yes Yes Yes Yes Yes

1111 16 Yes*Yes Yes Yes Yes Yes Yes

Note: *Do not set a Baud Rate Prescaler (BRP) value of B'000000 (2 × system clock).

Bit 7—Bit Sample Point (BSP): Sets the point at which data is sampled.

Bit 7: BCR15 Description

0 Bit sampling at one point (end of time segment 1 (TSEG1)) (Initial value)

1 Bit sampling at three points (end of TSEG1 and preceding and following

time quanta)

530

Bits 6 to 4—Time Segment 2 (TSEG2): These bits are used to set the segment for correcting 1-

bit time error. A value from 2 to 8 can be set.

Bit 6:

BCR14 Bit 5:

BCR13 Bit 4:

BCR12 Description

0 0 0 Setting prohibited (Initial value)

1 TSEG2 = 2 time quanta

1 0 TSEG2 = 3 time quanta

1 TSEG2 = 4 time quanta

1 0 0 TSEG2 = 5 time quanta

1 TSEG2 = 6 time quanta

1 0 TSEG2 = 7 time quanta

1 TSEG2 = 8 time quanta

Bits 3 to 0—Time Segment 1 (TSEG1): These bits are used to set the segment for absorbing

output buffer, CAN bus, and input buffer delay. A value from 1 to 16 can be set.

Bit 3:

BCR11 Bit 2:

BCR10 Bit 1:

BCR9 Bit 0:

BCR8 Description

0000Setting prohibited (Initial value)

0001Setting prohibited

0010Setting prohibited

0011TSEG1 = 4 time quanta

0100TSEG1 = 5 time quanta

⋅

1111TSEG1 = 16 time quanta

531

15.2.4 Mailbox Configuration Register (MBCR)

The mailbox configuration register (MBCR) is a 16-bit readable/writable register that is used to set

mailbox (buffer) transmission/reception.

MBCR

Bit: 15 14 13 12 11 10 9 8

MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1 —

Initial value: 0 0 0 0 0 0 0 1

R/W: R/W R/W R/W R/W R/W R/W R/W R

Bit: 7 6 5 4 3 2 1 0

MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Mailbox Setting Register (MBCR7 to MBCR1, MBCR15 to

MBCR8): These bits set the polarity of the corresponding mailboxes.

Bit x: MBCRx Description

0 Corresponding mailbox is set for transmission (Initial value)

1 Corresponding mailbox is set for reception

Bit 8—Reserved: This bit always reads 1. The write value should always be 1.

532

15.2.5 Transmit Wait Register (TXPR)

The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a

transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).

TXPR

Bit: 15 14 13 12 11 10 9 8

TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R

Bit: 7 6 5 4 3 2 1 0

TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Transmit Wait Register (TXPR7 to TXPR1, TXPR15 to TXPR8):

These bits set a transmit wait for the corresponding mailboxes.

Bit x: TXPRx Description

0 Transmit message idle state in corresponding mailbox (Initial value)

[Clearing condition]

Message transmission completion and cancellation completion

1 Transmit message transmit wait in corresponding mailbox (CAN bus

arbitration)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

533

15.2.6 Transmit Wait Cancel Register (TXCR)

The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls

cancellation of transmit wait messages in mailboxes (buffers).

TXCR

Bit: 15 14 13 12 11 10 9 8

TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R

Bit: 7 6 5 4 3 2 1 0

TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register (TXCR7 to TXCR1, TXCR15 to

TXCR8): These bits control cancellation of transmit wait messages in the corresponding HCAN

mailboxes.

Bit x: TXCRx Description

0 Transmit message cancellation idle state in corresponding mailbox

(Initial value)

[Clearing condition]

Completion of TXPR clearing (when transmit message is canceled normally)

1 TXPR cleared for corresponding mailbox (transmit message cancellation)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

534

15.2.7 Transmit Acknowledge Register (TXACK)

The transmit acknowledge register (TXACK) is a 16-bit readable/writable register containing

status flags that indicate normal transmission of mailbox (buffer) transmit messages.

TXACK

Bit: 15 14 13 12 11 10 9 8

TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R

Bit: 7 6 5 4 3 2 1 0

TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Transmit Acknowledge Register (TXACK7 to TXACK1, TXACK15

to TXACK8): These bits indicate that a transmit message in the corresponding HCAN mailbox

has been transmitted normally.

Bit x: TXACKx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of message transmission for corresponding mailbox

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

535

15.2.8 Abort Acknowledge Register (ABACK)

The abort acknowledge register (ABACK) is a 16-bit readable/writable register containing status

flags that indicate normal cancellation (aborting) of a mailbox (buffer) transmit messages.

ABACK

Bit: 15 14 13 12 11 10 9 8

ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R

Bit: 7 6 5 4 3 2 1 0

ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 9 and 7 to 0—Abort Acknowledge Register (ABACK7 to ABACK1, ABACK15 to

ABACK8): These bits indicate that a transmit message in the corresponding mailbox has been

canceled (aborted) normally.

Bit x: ABACKx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of transmit message cancellation for corresponding mailbox

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

536

15.2.9 Receive Complete Register (RXPR)

The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags

that indicate normal reception of messages (data frame or remote frame) in mailboxes (buffers).

In the case of remote frame reception, the corresponding remote request register (RFPR) is also set

simultaneously.

RXPR

Bit: 15 14 13 12 11 10 9 8

RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 0—Receive Complete Register (RXPR7 to RXPR0, RXPR15 to RXPR8): These bits

indicate that a receive message has been received normally in the corresponding mailbox.

Bit x: RXPRx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of message (data frame or remote frame) reception in

corresponding mailbox

537

15.2.10 Remote Request Register (RFPR)

The remote request register (RFPR) is a 16-bit readable/writable register containing status flags

that indicate normal reception of remote frames in mailboxes (buffers). When a bit in this register

is set, the corresponding reception complete bit is set simultaneously.

RFPR

Bit: 15 14 13 12 11 10 9 8

RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 0—Remote Request Register (RFPR7 to PFPR0, RFPR15 to PFDR8): These bits

indicate that a remote frame has been received normally in the corresponding mailbox.

Bit x: RFPRx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Completion of remote frame reception in corresponding mailbox

538

15.2.11 Interrupt Register (IRR)

The interrupt register (IRR) is a 16-bit readable/writable register containing status flags for the

various interrupt sources.

IRR

Bit: 15 14 13 12 11 10 9 8

IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0

Initial value: 0 0 0 0 0 0 0 1

R/W: R/W R/W R/W R/W R/W R R R/W

Bit: 7 6 5 4 3 2 1 0

— — — IRR12 — — IRR9 IRR8

Initial value: 0 0 0 0 0 0 0 0

R/W: — — — R/W — — R R/W

Bit 15—Overload Frame/Bus Off Recovery Interrupt Flag (IRR7): Status flag indicating that

the HCAN has transmitted an overload frame or recovered from the bus off state.

Bit 15: IRR7 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Overload frame transmission or recovery from bus off state

[Setting conditions]

Error active/passive state

• When overload frame is transmitted

Bus off state

• When 11 recessive bits is received 128 times (REC ≥ 128)

Bit 14—Bus Off Interrupt Flag (IRR6): Status flag indicating the bus off state caused by the

transmit error counter.

Bit 14: IRR6 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Bus off state caused by transmit error

[Setting condition]

When TEC ≥ 256

539

Bit 13—Error Passive Interrupt Flag (IRR5): Status flag indicating the error passive state

caused by the transmit/receive error counter.

Bit 13: IRR5 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Error passive state caused by transmit/receive error

[Setting condition]

When TEC ≥ 128 or REC ≥ 128

Bit 12—Receive Overload Warning Interrupt Flag (IRR4): Status flag indicating the error

warning state caused by the receive error counter.

Bit 12: IRR4 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Error warning state caused by receive error

[Setting condition]

When REC ≥ 96

Bit 11—Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error

warning state caused by the transmit error counter.

Bit 11: IRR3 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Error warning state caused by transmit error

[Setting condition]

When TEC ≥ 96

Bit 10—Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote

frame has been received in a mailbox (buffer).

Bit 10: IRR2 Description

0 [Clearing condition]

Clearing of all bits in RFPR (remote request register) of mailbox for which

receive interrupt requests are enabled by MBIMR (Initial value)

1 Remote frame received and stored in mailbox

[Setting conditions]

When remote frame reception is completed, when corresponding

MBIMR = 0

540

Bit 9—Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer)

receive message has been received normally.

Bit 9: IRR1 Description

0 [Clearing condition]

Clearing of all bits in RXPR (receive complete register) of mailbox for which

receive interrupt requests are enabled by MBIMR (Initial value)

1 Data frame or remote frame received and stored in mailbox

[Setting conditions]

When data frame or remote frame reception is completed, when

corresponding MBIMR = 0

Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been

reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after

reset input or recovery from software standby mode, interrupt handling will be performed as soon

as interrupts are enabled by the interrupt controller.

Bit 8: IRR0 Description

0 [Clearing condition]

Writing 1

1 Hardware reset (HCAN module stop*, software standby) (Initial value)

[Setting condition]

When reset processing is completed after a hardware reset (HCAN module

stop*, software standby)

Note: *After reset or hardware standby release, the module stop bit is initialized to 1, and so the

HCAN enters the module stop state.

Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0.

Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit

due to bus operation when the HCAN module is in HCAN sleep mode.

Bit 4: IRR12 Description

0 CAN bus idle state (Initial value)

[Clearing condition]

Writing 1

1 CAN bus operation in HCAN sleep mode

[Setting condition]

Bus operation (dominant bit detection) in HCAN sleep mode

541

Bit 1—Unread Interrupt Flag (IRR9): Status flag indicating that a receive message has been

overwritten while still unread.

Bit 1: IRR9 Description

0 [Clearing condition]

Clearing of all bits in UMSR (unread message status register) (Initial value)

1 Unread message overwrite

[Setting condition]

When UMSR (unread message status register) is set

Bit 0—Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit

message can be stored in the mailbox.

Bit 0: IRR8 Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Transmit message has been transmitted or aborted, and new message can

be stored

[Setting condition]

When TXPR (transmit wait register) is cleared by completion of transmission

or completion of transmission abort

542

15.2.12 Mailbox Interrupt Mask Register (MBIMR)

The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing

flags that enable or disable individual mailbox (buffer) interrupt requests.

MBIMR

Bit: 15 14 13 12 11 10 9 8

MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0

Initial value: 1 1 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8

Initial value: 1 1 1 1 1 1 1 1

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 0—Mailbox Interrupt Mask (MBIMRx) (MBIMR7 to MBIMR0, MBIMR15 to

MBIMR8): Flags that enable or disable individual mailbox interrupt requests.

Bit x: MBIMRx Description

0 [Transmitting]

Interrupt request to CPU due to TXPR clearing

[Receiving]

Interrupt request to CPU due to RXPR setting

1 Interrupt requests to CPU disabled (Initial value)

543

15.2.13 Interrupt Mask Register (IMR)

The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that

enable or disable requests by individual interrupt sources.

IMR

Bit: 15 14 13 12 11 10 9 8

IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1 —

Initial value: 1 1 1 1 1 1 1 0

R/W: R/W R/W R/W R/W R/W R/W R/W R

Bit: 7 6 5 4 3 2 1 0

— — — IMR12 — — IMR9 IMR8

Initial value: 1 1 1 1 1 1 1 1

R/W: R R R R/W R R R/W R/W

Bit 15—Overload Frame/Bus Off Recovery Interrupt Mask (IMR7): Enables or disables

overload frame/bus off recovery interrupt requests.

Bit 15: IMR7 Description

0 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7

enabled

1 Overload frame/bus off recovery interrupt request (OVR0) to CPU by IRR7

disabled (Initial value)

Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused

by the transmit error counter.

Bit 14: IMR6 Description

0 Bus off interrupt request (ERS0) to CPU by IRR6 enabled

1 Bus off interrupt request (ERS0) to CPU by IRR6 disabled (Initial value)

Bit 13—Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt

requests caused by the transmit/receive error counter.

Bit 13: IMR5 Description

0 Error passive interrupt request (ERS0) to CPU by IRR5 enabled

1 Error passive interrupt request (ERS0) to CPU by IRR5 disabled

(Initial value)

544

Bit 12—Receive Overload Warning Interrupt Mask (IMR4): Enables or disables error warning

interrupt requests caused by the receive error counter.

Bit 12: IMR4 Description

0 REC error warning interrupt request (OVR0) to CPU by IRR4 enabled

1 REC error warning interrupt request (OVR0) to CPU by IRR4 disabled

(Initial value)

Bit 11—Transmit Overload Warning Interrupt Mask (IMR3): Enables or disables error

warning interrupt requests caused by the transmit error counter.

Bit 11: IMR3 Description

0 TEC error warning interrupt request (OVR0) to by IRR3 CPU enabled

1 TEC error warning interrupt request (OVR0) to by IRR3 CPU disabled

(Initial value)

Bit 10—Remote Frame Request Interrupt Mask (IMR2): Enables or disables remote frame

reception interrupt requests.

Bit 10: IMR2 Description

0 Remote frame reception interrupt request (OVR0) to CPU by IRR2 enabled

1 Remote frame reception interrupt request (OVR0) to CPU by IRR2 disabled

(Initial value)

Bit 9—Receive Message Interrupt Mask (IMR1): Enables or disables message reception

interrupt requests.

Bit 9: IMR1 Description

0 Message reception interrupt request (RM1) to CPU by IRR1 enabled

1 Message reception interrupt request (RM1) to CPU by IRR1 disabled

(Initial value)

Bit 8—Reserved: This bit always reads 0. The write value should always be 0.

Bits 7 to 5, 3, and 2—Reserved: These bits always read 1. The write value should always be 1.

545

Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to

bus operation in sleep mode.

Bit 4: IMR12 Description

0 Bus operation interrupt request (OVR0) to CPU by IRR12 enabled

1 Bus operation interrupt request (OVR0) to CPU by IRR12 disabled

(Initial value)

Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite

interrupt requests.

Bit 1: IMR9 Description

0 Unread message overwrite interrupt request (OVR0) to CPU by IRR9

enabled

1 Unread message overwrite interrupt request (OVR0) to CPU by IRR9

disabled (Initial value)

Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt

requests.

Bit 0: IMR8 Description

0 Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled

1 Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled

(Initial value)

15.2.14 Receive Error Counter (REC)

The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating

the number of receive message errors on the CAN bus. The count value is stipulated in the CAN

protocol.

REC

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

546

15.2.15 Transmit Error Counter (TEC)

The transmit error counter (TEC) is an 8-bit read-only register that functions as a counter

indicating the number of transmit message errors on the CAN bus. The count value is stipulated in

the CAN protocol.

TEC

Bit: 7 6 5 4 3 2 1 0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

15.2.16 Unread Message Status Register (UMSR)

The unread message status register (UMSR) is a 16-bit readable/writable register containing status

flags that indicate, for individual mailboxes (buffers), that a received message has been

overwritten by a new receive message before being read. When a message is overwritten by a new

receive message, the old data is lost.

UMSR

Bit: 15 14 13 12 11 10 9 8

UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bits 15 to 0—Unread Message Status Flags (UMSR7 to UMSR0, UMSR15 to UMSR8):

Status flags indicating that an unread receive message has been overwritten.

547

Bit x: UMSRx Description

0 [Clearing condition]

Writing 1 (Initial value)

1 Unread receive message is overwritten by a new message

[Setting condition]

When a new message is received before RXPR is cleared x = 0 to 15

15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)

The local acceptance filter masks (LAFML, LAFMH) are 16-bit readable/writable registers that

filter receive messages to be stored in the receive-only mailbox (MC0, MD0) according to the

identifier. In these registers, consist of LAFMH15 (MSB) to LAFMH5 (LSB) are 11

standard/extended identifier bits, and LAFMH1 (MSB) to LAFML0 (LSB) are 18 extended

identifier bits.

LAFML

Bit: 15 14 13 12 11 10 9 8

LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

Bit: 7 6 5 4 3 2 1 0

LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

LAFMH

Bit: 15 14 13 12 11 10 9 8

LAFMH7 LAFMH6 LAFMH5 ———LAFMH1 LAFMH0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R R R R/W R/W

Bit: 7 6 5 4 3 2 1 0

LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

548

LAFMH Bits 7 to 0 and 15 to 13–11-Bit Identifier Filter (LAFMH7 to LAFMH5, LAFMH15

to LAFMH8): Filter mask bits for the first 11 bits of the receive message identifier (for both

standard and extended identifiers).

Bit x: LAFMHx Description

0 Stored in MC0, MD0 (receive-only mailbox) depending on bit match between

MC0 message identifier and receive message identifier (Initial value)

1 Stored in MC0, MD0 (receive-only mailbox) regardless of bit match between

MC0 message identifier and receive message identifier

LAFMH Bits 12 to 10—Reserved: These bits always read 0. The write value should always be 0.

LAFMH Bits 9 and 8, LAFML bits 15 to 0–18-Bit Identifier Filter (LAFMH1, LAFMH0,

LAFML7 to LAFML0, LAFML15 to LAFML8): Filter mask bits for the 18 bits of the receive

message identifier (extended).

Bit x: LAFMHx

LAFMLx Description

0 Stored in MC0 (receive-only mailbox) depending on bit match between MC0

message identifier and receive message identifier (Initial value)

1 Stored in MC0 (receive-only mailbox) regardless of bit match between MC0

message identifier and receive message identifier

549

15.2.18 Message Control (MC0 to MC15)

The message control register sets (MC0 to MC15) consist of eight 8-bit readable/writable registers

(MCx[1] to MCx[8]). The HCAN has 16 sets of these registers (MC0 to MC15).

The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).

MCx [1]

Bit: 7 6 5 4 3 2 1 0

— — — — DLC3 DLC2 DLC1 DLC0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [2]

Bit: 7 6 5 4 3 2 1 0

————————

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [3]

Bit: 7 6 5 4 3 2 1 0

————————

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [4]

Bit: 7 6 5 4 3 2 1 0

————————

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [5]

Bit: 7 6 5 4 3 2 1 0

STD_ID2 STD_ID1 STD_ID0 RTR IDE —EXD_ID17EXD_ID16

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

550

MCx [6]

Bit: 7 6 5 4 3 2 1 0

STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [7]

Bit: 7 6 5 4 3 2 1 0

EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MCx [8]

Bit: 7 6 5 4 3 2 1 0

EXD_ID15 EXD_ID14EXD_ID13 EXD_ID12EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

*:Undefined

x = 0 to 15

MCx[1] Bits 7 to 4—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

MCx[1] Bits 3 to 0—Data Length Code (DLC): These bits indicate the required length of data

frames and remote frames.

Bit 3:

DLC3 Bit 2:

DLC2 Bit 1:

DLC1 Bit 0:

DLC0 Description

0000Data length = 0 byte

1 Data length = 1 byte

1 0 Data length = 2 bytes

1 Data length = 3 bytes

1 0 0 Data length = 4 bytes

1 Data length = 5 bytes

1 0 Data length = 6 bytes

1 Data length = 7 bytes

1 0/1 0/1 0/1 Data length = 8 bytes

551

MCx[2] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

MCx[3] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

MCx[4] Bits 7 to 0—Reserved: The initial value of these bits is undefined; they must be

initialized (by writing 0 or 1).

MCx[6] Bits 7 to 0—Standard Identifier (STD_ID10 to STD_ID3):

MCx[5] Bits 7 to 5—Standard Identifier (STD_ID2 to STD_ID0):

These bits set the identifier (standard identifier) of data frames and remote frames.

Standard identifier

SOF ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

STD_IDxx

IDE

SRR

Figure 15-3 Standard Identifier

MCx[5] Bit 4—Remote Transmission Request (RTR): Used to distinguish between data frames

and remote frames.

Bit 4: RTR Description

0 Data frame

1 Remote frame

MCx[5] Bit 3—Identifier Extension (IDE): Used to distinguish between the standard format and

extended format of data frames and remote frames.

Bit 3: IDE Description

0 Standard format

1 Extended format

MCx[5] Bit 2—Reserved: The initial value of this bit is undefined; it must be initialized (by

writing 0 or 1).

552

MCx[5] Bits 1 and 0—Extended Identifier (EXD_ID17, EXD_ID16):

MCx[8] Bits 7 to 0—Extended Identifier (EXD_ID15 to EXD_ID8):

MCx[7] Bits 7 to 0—Extended Identifier (EXD_ID7 to EXD_ID0):

These bits set the identifier (extended identifier) of data frames and remote frames.

Extended Identifier

IDE ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5

EXD_IDxx

ID4 ID3 ID2 ID1 ID0 RTR R1

EXD_IDxx

Figure 15-4 Extended Identifier

553

15.2.19 Message Data (MD0 to MD15)

The message data register sets (MD0 to MD15) consist of eight 8-bit readable/writable registers

(MDx[1] to MDx[8]). The HCAN has 16 sets of these registers (MD0 to MD15).

The initial value of these registers is undefined, so they must be initialized (by writing 0 or 1).

MDx [1]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MDx [2]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MDx [3]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MDx [4]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MDx [5]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

554

MDx [6]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MDx [7]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MDx [8]

Bit: 7 6 5 4 3 2 1 0

Initial value: ********

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

*:Undefined

x = 0 to 15

555

15.2.20 Module Stop Control Register C (MSTPCRC)

Bit: 7 6 5 4 3 2 1 0

MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

Initial value: 11111111

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPC3 bit is set to 1, HCAN operation is stopped at the end of the bus cycle, and

module stop mode is entered. Register read/write accesses are not possible in module stop mode.

For details, see section 20.5, Module Stop Mode.

MSTPCRC is initialized to H'FF by a reset, and in hardware standby mode. It is not initialized in

software standby mode.

Bit 3—Module Stop (MSTPC3): Specifies the HCAN module stop mode.

Bit 3: MSTPC3 Description

0 HCAN module stop mode is cleared

1 HCAN module stop mode is set (Initial value)

556

15.3 Operation

15.3.1 Hardware and Software Resets

The HCAN can be reset by a hardware reset or software reset.

Hardware Reset (HCAN Module Stop, Reset*, Hardware*/Software Standby): Initialization

is performed by automatic setting of the MCR reset request bit (MCR0) in MCR and the reset state

bit (GSR3) in GSR within the HCAN (hardware reset). At the same time, all internal registers are

initialized. However mailbox contents are retained. A flowchart of this reset is shown in figure

15-5.

Note: * In a reset and in hardware standby mode, the module stop bit is initialized to 1 and the

HCAN enters the module stop state.

Software Reset (Write to MCR0): In normal operation initialization is performed by setting the

MCR reset request bit (MCR0) in MCR (Software reset). With this kind of reset, if the CAN

controller is performing a communication operation (transmission or reception), the initialization

state is not entered until the message has been completed. During initialization, the reset state bit

(GSR3) in GSR is set. In this kind of initialization, the error counters (TEC and REC) are

initialized but other registers and RAM (mailboxes) are not. A flowchart of this reset is shown in

figure 15-6.

557

IRR0 = 1 (automatic)*1

GSR3 = 1 (automatic)

Initialization of HCAN module

Clear IRR0

BCR setting

MBCR setting

Mailbox (RAM) initialization

Message transmission method initialization

Hardware reset

MCR0 = 1 (automatic)

GSR3 = 0?

GSR3 = 0 & 11

recessive bits received?

CAN bus communication enabled

IMR setting (interrupt mask setting)

MBIMR setting (interrupt mask setting)

MC[x] setting (receive identifier setting)

LAFM setting (receive identifier mask setting)

MCR0 = 0

Bit configuration mode

Period in which BCR, MBCR, etc.,

are initialized

: Settings by user

: Processing by hardware

Yes

Notes: 1. When IRR0 is set to 1 (automatically) due to a hardware reset*2, a "hardware reset

initiated reset processing" interrupt is generated.

2. In a reset and in hardware standby mode, the module stop bit is initialized to 1 and

the HCAN enters the module stop state.

Figure 15-5 Hardware Reset Flowchart

558

Initialization of REC and TEC only

MCR0 = 1

GSR3 = 1 (automatic)

Bus idle?

CAN bus communication enabled

: Settings by user

: Processing by hardware

Yes

MCR0 = 0

GSR3 = 0? No

IMR setting

MBIMR setting

MC[x] setting

LAFM setting

OK?

Yes

Correction

BCR setting

MBCR setting

Mailbox (RAM) initialization

Message transmission method

initialization

OK?

GSR3 = 0 & 11

recessive bits received?

Figure 15-6 Software Reset Flowchart

559

15.3.2 Initialization after Hardware Reset

After a hardware reset, the following initialization processing should be carried out:

• Clearing of IRR0 bit in interrupt register (IRR)

• Bit rate setting

• Mailbox transmit/receive settings

• Mailbox (RAM) initialization

• Message transmission method setting

These initial settings must be made while the HCAN is in bit configuration mode. Configuration

mode is a state in which the reset request bit (MCR0) in the master control register (MCR) is 1 and

the reset status bit in the general status register (GSR) is also 1 (GSR3 = 1). Configuration mode is

exited by clearing the reset request bit in MCR to 0; when MCR0 is cleared to 0, the HCAN

automatically clears the reset state bit (GSR3) in the general status register (GSR). The power-up

sequence then begins, and communication with the CAN bus is possible as soon as the sequence

ends. The power-up sequence consists of the detection of 11 consecutive recessive bits.

IRR0 Clearing: The reset interrupt flag (IRR0) is always set after a reset or recovery from

software standby mode. As an HCAN interrupt is initiated immediately when interrupts are

enabled, IRR0 should be cleared.

Bit Rate Settings: As bit rate settings, a baud rate setting and bit timing setting must be made

each time a CAN node begins communication. The baud rate and bit timing settings are made in

the bit configuration register (BCR).

a. Note

BCR can be written to at all times, but should only be modified in configuration mode.

Settings should be made so that all CAN controllers connected to the CAN bus have the same

baud rate and bit width.

Limits for the settable variables (TSEG1, TSEG2, BRP, sample point, and SJW) are shown in

table 15-4.

560

Table 15-4 BCR Setting Limits

Name Abbreviation Bits Initial

Value Min.

Value Max.

Value

Time segment 1 TSEG1 40315

Time segment 2 TSEG2 3017

Baud rate prescaler BRP 60063

Sample point SAM 1001

Re-synchronization jump width SJW 2013

b. Settable Variable Limits

• The bit width consists of the total of the settable Time Quanta (TQ). TQ (number of system

clocks) is determined by the baud rate prescaler (BRP).

2 × (BRP + 1)

fCLK

TQ =

• The value of SJW is stipulated in the CAN specifications.

4 SJW ≥ 1

• The minimum value of TSEG1 is stipulated in the CAN specifications.

TSEG1 > TSEG2

• The minimum value of TSEG2 is stipulated in the CAN specifications.

TSEG2 ≥ SJW

The following formula is used to calculate the baud rate.

fCLK

2 × (BRP + 1) × (1 + TSEG1 + TSEG2)

Bit rate [b/s] =

Note: fCLK = φ (system clock)

The BCR values are used for BRP, TSEG1, and TSEG2.

Example: With a 1 Mb/s baud rate and a 20 MHz input clock:

20 MHz

2 × (0 + 1) × (1 + 5 + 4)

1 Mb/s =

561

Item Set Values Actual Values

fCLK 20 MHz —

BRP 0 (B'000000) System clock × 2

TSEG1 4 (B'0100) 5TQ

TSEG2 3 (B'011) 4TQ

Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receive-

only, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set

for transmission or reception must be designated either for transmission use or for reception use

before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while

mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software

reset.

• Setting for transmission

Transmit mailbox setting (mailboxes 1 to 15)

Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding

mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so

this setting is not necessary.

• Setting for reception

Transmit/receive mailbox setting (mailboxes 1 to 15)

Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding

mailbox for reception use. When setting mailboxes for reception, to improve message

transmission efficiency, high-priority messages should be set in low-to-high mailbox order

(priority order: mailbox 1 (MCx[1]) > mailbox 15 (MCx[15]).

• Receive-only mailbox (mailbox 0)

No setting is necessary, as this mailbox is always used for reception.

Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings: After power is supplied,

all registers and RAM (message control/data, control registers, status registers, etc.) are initialized.

Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined.

Initial values must therefore be set in all the mailboxes (by writing 0s or 1s).

Setting the Message Transmission Method: Either of the following message transmission

methods can be selected with the message transmission method bit (MCR2) in the master control

a. Transmission order determined by message identifier priority

b. Transmission order determined by mailbox number priority

562

When a is selected, if a number of messages are designated as waiting for transmission (TXPR =

1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is stored

in the transmit buffer. CAN bus arbitration is then carried out for the message in the transmit

buffer, and message transmission is performed when the transmission right is acquired. When the

TXPR bit is set, internal arbitration is performed again, and the highest-priority message is found

and stored in the transmit buffer.

When b is selected, if a number of messages are designated as waiting for transmission (TXPR =

1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:

mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit

buffer, and message transmission is performed when the bus is acquired.

15.3.3 Transmit Mode

Message transmission is performed using mailboxes 1 to 15. The transmission procedure is

described below, and a transmission flowchart is shown in figure 15-7.

Initialization (after hardware reset only)

a. Clearing of IRR0 bit in interrupt register (IRR)

b. Bit rate settings

c. Mailbox transmit/receive settings

d. Mailbox initialization

e. Message transmission method setting

Interrupt and transmit data settings

a. CPU interrupt source setting

b. Arbitration field setting

c. Control field setting

d. Data field setting

Message transmission and interrupts

a. Message transmission wait

b. Message transmission completion and interrupt

c. Message transmission abort

d. Message retransmission

563

Initialization (After Hardware Reset Only): These settings should be made while the HCAN is

in bit configuration mode.

• IRR0 clearing

The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby

mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0

should be cleared.

• Bit rate settings

Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit

Rate setting in 15.3.2 Initialization after Hardware Reset for details.

• Mailbox transmit/receive settings

Mailbox transmit/receive settings should be made in advance. A total of 15 mailbox can be set

for transmission or reception (mailboxes 1 to 15). To set a mailbox for transmission, clear the

corresponding bit to 0 in the mailbox configuration register (MBCR). Refer to Mailbox

transmit/receive settings in 15.3.2 Initialization after Hardware Reset for details.

• Mailbox initialization

As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial

values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to

the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Setting in

15.3.2, Initialization after a Hardware Reset, for details.

• Message transmission method setting

Set the transmission method for mailboxes designated for transmission. The following two

transmission methods can be used. Refer to Message transmission method settings in 15.3.2

Initialization after Hardware Reset for details.

a. Transmission order determined by message identifier priority

b. Transmission order determined by mailbox number priority

564

Initialization (after hardware reset only)

IRR0 clearing

BCR setting

MBCR setting

Mailbox initialization

Message transmission method setting

Interrupt settings

Transmit data setting

Arbitration field setting

Control field setting

Data field setting

Message transmission wait

TXPR setting

Bus idle? No

Message transmission

GSR2 = 0 (during transmission only)

Transmission completed? No

TXACK = 1

IRR8 = 1

IMR8 = 1? Yes

Interrupt to CPU

Clear TXACK

Clear IRR8

End of transmission

: Settings by user

: Processing by hardware

Yes

Figure 15-7 Transmission Flowchart

565

Interrupt and Transmit Data Settings: When mailbox initialization is finished, CPU interrupt

source settings and data settings must be made. Interrupt source settings are made in the mailbox

interrupt register (MBIMR) and interrupt mask register (IMR), while transmit data settings are

made by writing the necessary data from the arbitration field, control field, and data field,

described below, in the corresponding message control (MCx[1]–MCx[8]) and message data

(MDx[1]–MDx[8]).

• CPU interrupt source settings

Transmission acknowledge and transmission abort acknowledge interrupts can be masked for

individual mailboxes in the mailbox interrupt mask register (MBIMR). Interrupt register (IRR)

interrupts can be masked in the interrupt mask register (IMR).

• Arbitration field setting

In the arbitration field, the 11-bit identifier (STD_ID0–STD_ID10) and RTR bit (standard

format) or 29-bit identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) and IDE.RTR bit

(extended format) are set. The registers to be set are MCx[5]–MCx[8].

• Control field setting

In the control field, the byte length of the data to be transmitted is set in DLC0–DLC3. The

• Data field setting

In the data field, the data to be transmitted is set in byte units in the range of 0 to 8 bytes. The

registers to be set are MDx[1]–MDx[8].

The number of bytes in the data actually transmitted depends on the data length code (DLC) in the

control field. If a value exceeding the value set in DLC is set in the data field, only the number of

bytes set in DLC will actually be transmitted.

Message Transmission and Interrupts:

• Message transmission wait

If message transmission is to be performed after completion of the message control (MCx[1]–

MCx[8]) and message data (MDx[1]–MDx[8]).settings, transmission is started by setting the

corresponding mailbox transmit wait bit (TXPR1–TXPR15) to 1 in the transmit wait register

(TXPR). The following two transmission methods can be used:

a. Transmission order determined by message identifier priority

b. Transmission order determined by mailbox number priority

When a is selected, if a number of messages are designated as waiting for transmission (TXPR

= 1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:

mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the

transmit buffer, and message transmission is performed when the bus is acquired.

566

When b is selected, if a number of messages are designated as waiting for transmission (TXPR

= 1), the message with the highest priority set in the message identifier (MCx[5]–MCx[8]) is

stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the

transmit buffer, and message transmission is performed when the transmission right is

acquired. When the TXPR bit is set, internal arbitration is performed again, the highest-priority

message is found and stored in the transmit buffer, CAN bus arbitration is carried out in the

same way, and message transmission is performed when the transmission right is acquired.

• Message transmission completion and interrupt

When a message is transmitted error-free using the above procedure, the corresponding

acknowledge bit (TXACK1–TXACK15) in the transmit acknowledge register (TXACK) and

transmit wait bit (TXPR1–TXPR15) in the transmit wait register (TXPR) are automatically

initialized. Also, if the corresponding bit (MBIMR1-MBIMR15) in the mailbox interrupt mask

(IMR) are set to the interrupt enable state at the same time, an interrupt can be sent to the CPU.

• Message transmission cancellation

Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait

message. A transmit wait message is canceled by setting the bit for the corresponding mailbox

(TXCR1–TXCR15) to 1 in the transmit cancel register (TXCR). When cancellation is

executed, the transmit wait register (TXPR) is automatically reset, and the corresponding bit is

set to 1 in the abort acknowledge register (ABACK). An interrupt to the CPU can be requested.

Also, if the mailbox empty interrupt (IRR8) is enabled for the bits (MBIMR1-MBIMR15)

corresponding to the mailbox interrupt mask register (MBIMR) and interrupt mask register

(IMR), interrupts may be sent to the CPU.

However, a transmit wait message cannot be canceled at the following times:

a. During internal arbitration or CAN bus arbitration

b. During data frame or remote frame transmission

Also, transmission cannot be canceled by clearing the transmit wait register (TXPR). Figure

15-8 shows a flowchart of transmit message cancellation.

• Message retransmission

If transmission of a transmit message is aborted in the following cases, the message is

retransmitted automatically:

a. CAN bus arbitration failure (failure to acquire the bus)

b. Error during transmission (bit error, stuff error, CRC error, frame error, ACK error)

567

Message transmit wait TXPR setting

Set TXCR bit corresponding to message

to be canceled

Cancellation possible? No

Message not sent

Clear TXCR, TXPR

ABACK = 1

IRR8 = 1

IMR8 = 1? Yes

Interrupt to CPU

Clear TXACK

Clear ABACK

Clear IRR8

End of transmission/transmission

cancellation

Completion of message transmission

TXACK = 1

Clear TXCR, TXPR

IRR8 = 1

Yes

: Settings by user

: Processing by hardware

Figure 15-8 Transmit Message Cancellation Flowchart

568

15.3.4 Receive Mode

Message reception is performed using mailboxes 0 and 1 to 15. The reception procedure is

described below, and a reception flowchart is shown in figure 15-9.

Initialization (after hardware reset only)

a. Clearing of IRR0 bit in interrupt register (IRR)

b. Bit rate settings

c. Mailbox transmit/receive settings

d. Mailbox (RAM) initialization

Interrupt and receive message settings

a. CPU interrupt source setting

b. Arbitration field setting

c. Local acceptance filter mask (LAFM) settings

Message reception and interrupts

a. Message reception CRC check

b. Data frame reception

c. Remote frame reception

d. Unread message reception

Initialization (After Hardware Reset Only): These settings should be made while the HCAN is

in bit configuration mode.

• IRR0 clearing

The reset interrupt flag (IRR0) is always set after a reset or recovery from software standby

mode. As an HCAN interrupt is initiated immediately when interrupts are enabled, IRR0

should be cleared.

• Bit rate settings

Set values relating to the CAN bus communication speed and resynchronization. Refer to Bit

Rate setting in 15.3.2 Initialization after Hardware Reset for details.

• Mailbox transmit/receive settings

Each channel has one receive-only mailbox (mailbox 0) plus 15 mailboxes that can be set for

reception. Thus a total of 16 mailboxes can be used for reception. To set a mailbox for

reception, set the corresponding bit to 1 in the mailbox configuration register (MBCR). The

initial setting for mailboxes is 0, designating transmission use. Refer to Mailbox

transmit/receive settings in 15.3.2 Initialization after Hardware Reset for details.

569

• Mailbox (RAM) initialization

As message control/data registers (MCx[x], MDx[x]) are configured in RAM, their initial

values after powering on are undefined, and so bit initialization is necessary. Write 0s or 1s to

the mailboxes. See Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Setting in

15.3.2, Initialization after a Hardware Reset, for details.

570

Initialization IRR0 clearing

BCR setting

MBCR setting

Mailbox (RAM) initialization

Interrupt settings

Arbitration field setting

Local acceptance filter settings

Receive data setting

Message reception

(Match of identifier

in mailbox?)

Same RXPR = 1? Yes

Data frame? No

RXPR

IRR1 = 1

Yes

IMR1 = 1?

Interrupt to CPU

Message control read

Message data read

Clear all RXPRn bits of mailbox for which

receive interrupt requests are enabled

by MBIMR

End of reception

Yes

Unread message

RXPR, RFPR = 1

IRR2 = 1, IRR1 = 1

Yes

IMR2 = 1?

Interrupt to CPU

Message control read

Message data read

Clear all RXPRn bits of mailbox for which

receive interrupt requests are enabled

by MBIMR

Transmission of data frame corresponding

to remote frame

IRR1 = 0 IRR2 = 0, IRR1 = 0

: Settings by user

: Processing by hardware

Figure 15-9 Reception Flowchart

571

Interrupt and Receive Message Settings: When mailbox initialization is finished, CPU interrupt

source settings and receive message specifications must be made. Interrupt source settings are

made in the mailbox interrupt register (MBIMR) and interrupt mask register (IMR). To receive a

message, the identifier must be set in advance in the message control (MCx[1]–MCx[8]) for the

receiving mailbox. When a message is received, all the bits in the receive message identifier are

compared, and if a 100% match is found, the message is stored in the matching mailbox. Mailbox

0 (MC0[x], MD0[x]) has a local acceptance filter mask (LAFM) that allows Don’t Care settings to

be made.

• CPU interrupt source settings

When transmitting, transmission acknowledge and transmission abort acknowledge interrupts

can be masked for individual mailboxes in the mailbox interrupt mask register (MBIMR).

When receiving, data frame and remote frame receive wait interrupts can be masked. Interrupt

• Arbitration field setting

In the arbitration field, the identifier (STD_ID0–STD_ID10, EXT_ID0–EXT_ID17) of the

message to be received is set. If all the bits in the set identifier do not match, the message is not

stored in a mailbox.

Example: Mailbox 1 010_1010_1010 (standard identifier)

Only one kind of message identifier can be received by MB1

Identifier 1: 010_1010_1010

• Local acceptance filter mask (LAFM) setting

The local acceptance filter mask is provided for mailbox 0 (MC0[x], MD0[x]) only, enabling a

Don’t Care specification to be made for all bits in the received identifier. This allows various

kinds of messages to be received.

Example: Mailbox 0 010_1010_1010 (standard identifier)

LAFM 000_0000_0011 (0: Care, 1: Don’t Care)

A total of four kinds of message identifiers can be received by MB0

Identifier 1: 010_1010_1000

Identifier 2: 010_1010_1001

Identifier 3: 010_1010_1010

Identifier 4: 010_1010_1011

572

Message Reception and Interrupts:

• Message reception CRC check

When a message is received, a CRC check is performed automatically (by hardware). If the

result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of

whether or not the message can be received.

• Data frame reception

If the received message is confirmed to be error-free by the CRC check, etc., the identifier in

the mailbox (and also LAFM in the case of mailbox 0 only) and the identifier of the receive

message are compared, and if a complete match is found, the message is stored in the mailbox.

The message identifier comparison is carried out on each mailbox in turn, starting with

mailbox 0 and ending with mailbox 15. If a complete match is found, the comparison ends at

that point, the message is stored in the matching mailbox, and the corresponding receive

complete bit (RXPR0–RXPR15) is set in the receive complete register (RXPR). However,

when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox

comparison sequence does not end at that point, but continues with mailbox 1 and then the

remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received

by another mailbox (however, the same message cannot be stored in more than one of

mailboxes 1 to 15). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox interrupt

mask register (MBIMR) and the receive message interrupt mask (IMR1) in the interrupt mask

CPU.

• Remote frame reception

Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A

remote frame differs from a data frame in that the remote reception request bit (RTR) in the

message control register (MC[x]5) and the data field are 0 bytes. The data length to be returned

in a data frame must be stored in the data length code (DLC) in the control field.

When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote

request wait register (RFPR). If the corresponding bit (MBIMR0–MBIMR15) in the mailbox

interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the

interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt can

be sent to the CPU.

• Unread message reception

When the identifier in a mailbox matches a receive message, the message is stored in the

mailbox. If a message overwrite occurs before the CPU reads the message, the corresponding

bit (UMSR0–UMSR15) is set in the unread message register (UMSR). In overwriting of an

unread message, when a new message is received before the corresponding bit in the receive

complete register (RXPR) has been cleared, the unread message register (UMSR) is set. If the

unread interrupt flag (IRR9) in the interrupt mask register (IMR) is set to the interrupt enable

573

value at this time, an interrupt can be sent to the CPU. Figure 15-10 shows a flowchart of

unread message overwriting.

UMSR = 1

IRR9 = 1

Unread message overwrite

IMR9 = 1?

End

Yes

Interrupt to CPU

Clear IRR9

Message control/message data read

: Settings by user

: Processing by hardware

Figure 15-10 Unread Message Overwrite Flowchart

574

15.3.5 HCAN Sleep Mode

The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep

state to reduce current dissipation. Figure 15-11 shows a flowchart of the HCAN sleep mode.

MCR5 = 1

Bus operation?

IRR12 = 1

Initialize TEC and REC

IMR12 = 1?

Sleep mode clearing method

MCR7 = 0?

MCR5 = 0

CAN bus communication possible

CPU interrupt

MCR5=0

Clear sleep mode?

Yes

Yes (manual)

No (automatic)

Yes

: Settings by user

: Processing by hardware

11 recessive bits?

Bus idle?

Figure 15-11 HCAN Sleep Mode Flowchart

575

HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master

control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is

delayed until the bus becomes idle.

Either of the following methods of clearing HCAN sleep mode can be selected by making a setting

in the MCR7 bit.

1. Clearing by software

2. Clearing by CAN bus operation

Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus

communication is enabled again.

Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.

Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the

CAN bus performs an operation and this change is detected. In this case, the first message is not

received in the mailbox, and normal reception starts from the next message. When a change is

detected on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in

the interrupt register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR)

is set to the interrupt enable value at this time, an interrupt can be sent to the CPU.

576

15.3.6 HCAN Halt Mode

The HCAN halt mode is provided to enable mailbox settings to be changed without performing an

HCAN hardware or software reset. Figure 15-12 shows a flowchart of the HCAN halt mode.

MCR1 = 1

Bus idle?

CAN bus communication possible

MBCR setting

MCR1 = 0

Yes

: Settings by user

: Processing by hardware

Figure 15-12 HCAN Halt Mode Flowchart

HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control

the bus becomes idle.

HCAN halt mode is cleared by clearing MCR1 to 0.

15.3.7 Interrupt Interface

There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned.

Table 15-5 lists the HCAN interrupt sources.

With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is

implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register

(IMR).

577

Table 15-5 HCAN Interrupt Sources

IPR Bits Vector Vector Number IRR Bit Description

IPRM (6–4) ERS0 104 IRR5 Error passive interrupt (TEC ≥ 128 or REC ≥

128)

IRR6 Bus off interrupt (TEC ≥ 256)

OVR0 105 IRR0 Hardware reset processing interrupt

IRR2 Remote frame reception interrupt

IRR3 Error warning interrupt (TEC ≥ 96)

IRR4 Error warning interrupt (REC ≥ 96)

IRR7 Overload frame transmission interrupt/bus off

recovery interrupt (11 recessive bits × 128

times)

IRR9 Unread message overwrite interrupt

IRR12 HCAN sleep mode CAN bus operation

interrupt

RM0 106 IRR1 Mailbox 0 message reception interrupt

RM1 107 IRR1 Mailbox 1-15 message reception interrupt

IPRM (2–0) SLE0 108 IRR8 Message transmission/cancellation interrupt

578

15.3.8 DTC Interface

The DTC can be activated by reception of a message in the HCAN’s mailbox 0. When DTC

transfer ends after DTC activation has been set, the RXPR0 and RFPR0 flags are acknowledge

signal automatically. An interrupt request due to a receive interrupt from the HCAN cannot be sent

to the CPU in this case. Figure 15-13 shows a DTC transfer flowchart.

DTC enable register setting

DTC register information setting

End of DTC transfer?

End

DTC initialization

Message reception in HCAN’s

mailbox 0

DTC activation

Transfer counter = 0

or DISEL = 1? No

Interrupt to CPU

Yes

: Settings by user

: Processing by hardware

RXPR and RFPR clearing

Figure 15-13 DTC Transfer Flowchart

579

15.4 CAN Bus Interface

A bus transceiver IC is necessary to connect the H8S/2626 Series or H8S/2623 Series chip to a

CAN bus. A Philips PCA82C250 transceiver IC, or compatible device, is recommended. Figure

15-14 shows a sample connection diagram.

RxD

TxD

Vref

Vcc

CANH

CANL

GND

HRxD

HTxD

H8S/2626 Series or

H8S/2623 Series

CAN bus

124 Ω

Vcc

PCA82C250

No connection

Figure 15-14 High-Speed Interface Using PCA82C250

580

15.5 Usage Notes

1. Reset

The HCAN is reset by a reset, and in hardware standby mode and software standby mode. All

the registers are initialized in a reset, but mailboxes (message control (MCx[x])/message data

(MDx[x]) are not. However, after powering on, mailboxes (message control (MCx[x])/message

data (MDx[x]) are initialized, and their values are undefined. Therefore, mailbox initialization

must always be carried out after a reset or a transition to hardware standby mode or software

standby mode. Also, the reset interrupt flag (IRR0) is always set after reset input or recovery

from software standby mode. As this bit cannot be masked in the interrupt mask register

(IMR), if HCAN interrupts are set as enabled by the interrupt controller without this flag

having been cleared, an HCAN interrupt will be initiated immediately. IRR0 must therefore be

cleared during initialization.

2. HCAN sleep mode

The bus operation interrupt flag (IRR12) in the interrupt register (IRR) is set by bus operation

in HCAN sleep mode. Therefore, this flag is not used by the HCAN to indicate sleep mode

release. Also note that the reset status bit (GSR3) in the general status register (GSR) is set in

sleep mode.

3. Interrupts

When the mailbox interrupt mask register (MBIMR) is set, the interrupt register (IRR8.2.1) is

not set by reception completion, transmission completion, or transmission cancellation for the

set mailboxes.

4. Error counters

In the case of error active and error passive, REC and TEC normally count up and down. In the

bus off state, 11-bit recessive sequences are counted (REC + 1) using REC. If REC reaches 96

during the count, IRR4 and GSR1 are set, and if REC reaches 128, IRR7 is set.

5. Register access

Byte or word access can be used on all HCAN registers. Longword access cannot be used.

6. HCAN medium-speed mode

HCAN registers cannot be read or written to in medium-speed mode.

7. Register retention during standby

All HCAN registers are initialized in hardware standby mode and software standby mode.

581

Section 16 A/D Converter

16.1 Overview

The H8S/2626 Series and H8S/2623 Series include a successive approximation type 10-bit A/D

converter that allows up to sixteen analog input channels to be selected.

16.1.1 Features

A/D converter features are listed below.

• 10-bit resolution

• Sixteen input channels

• Settable analog conversion voltage range

 Conversion of analog voltages with the reference voltage pin (Vref) as the analog reference

voltage

• High-speed conversion

 Minimum conversion time: 13.3 µs per channel (at 20 MHz operation)

• Choice of single mode or scan mode

 Single mode: Single-channel A/D conversion

 Scan mode: Continuous A/D conversion on 1 to 4 channels

• Four data registers

 Conversion results are held in a 16-bit data register for each channel

• Sample and hold function

• Three kinds of conversion start

 Choice of software or timer conversion start trigger (TPU), or ADTRG pin

• A/D conversion end interrupt generation

 A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion

• Module stop mode can be set

 As the initial setting, A/D converter operation is halted. Register access is enabled by

exiting module stop mode.

582

16.1.2 Block Diagram

Figure 16-1 shows a block diagram of the A/D converter.

Module data bus

Control circuit

Internal data bus

10-bit D/A

Comparator

–

Sample-and-

hold circuit

ø/2

ø/4

ø/8

ADI

interrupt

ø/16

Bus interface

AVCC

Vref

AVSS

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

ADTRG Conversion start

trigger from TPU

Successive approximations

Multiplexer

ADCR

ADCSR

ADDRA

ADDRB

ADDRC

ADDRD

: A/D control register

: A/D control/status register

: A/D data register A

: A/D data register B

: A/D data register C

: A/D data register D

Figure 16-1 Block Diagram of A/D Converter

583

16.1.3 Pin Configuration

Table 16-1 summarizes the input pins used by the A/D converter.

The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter.

The Vref pin is the A/D conversion reference voltage pin.

The 16 analog input pins are divided into two channel sets and two groups, with analog input pins

0 to 7 (AN0 to AN7) comprising channel set 0, analog input pins 8 to 15 (AN8 to AN15)

comprising channel set 1, analog input pins 0 to 3 and 8 to 11 (AN0 to AN3, AN8 to AN11)

comprising group 0, and analog input pins 4 to 7 and 12 to 15 (AN4 to AN7, AN12 to AN15)

comprising group 1.

Table 16-1 A/D Converter Pins

Pin Name Symbol I/O Function

Analog power supply pin AVCC Input Analog block power supply

Analog ground pin AVSS Input Analog block ground and reference voltage

Reference voltage pin Vref Input A/D conversion reference voltage

Analog input pin 0 AN0 Input Channel set 0 (CH3 = 0) group 0 analog inputs

Analog input pin 1 AN1 Input

Analog input pin 2 AN2 Input

Analog input pin 3 AN3 Input

Analog input pin 4 AN4 Input Channel set 0 (CH3 = 0) group 1 analog inputs

Analog input pin 5 AN5 Input

Analog input pin 6 AN6 Input

Analog input pin 7 AN7 Input

Analog input pin 8 AN8 Input Channel set 1 (CH3 = 1) group 0 analog inputs

Analog input pin 9 AN9 Input

Analog input pin 10 AN10 Input

Analog input pin 11 AN11 Input

Analog input pin 12 AN12 Input Channel set 1 (CH3 = 1) group 1 analog inputs

Analog input pin 13 AN13 Input

Analog input pin 14 AN14 Input

Analog input pin 15 AN15 Input

A/D external trigger input

pin ADTRG Input External trigger input for starting A/D

conversion

584

16.1.4 Register Configuration

Table 16-2 summarizes the registers of the A/D converter.

Table 16-2 A/D Converter Registers

Name Abbreviation R/W Initial Value Address*1

A/D data register AH ADDRAH R H'00 H'FF90

A/D data register AL ADDRAL R H'00 H'FF91

A/D data register BH ADDRBH R H'00 H'FF92

A/D data register BL ADDRBL R H'00 H'FF93

A/D data register CH ADDRCH R H'00 H'FF94

A/D data register CL ADDRCL R H'00 H'FF95

A/D data register DH ADDRDH R H'00 H'FF96

A/D data register DL ADDRDL R H'00 H'FF97

A/D control/status register ADCSR R/(W)*2H'00 H'FF98

A/D control register ADCR R/W H'33 H'FF99

Module stop control register A MSTPCRA R/W H'3F H'FDE8

Notes: 1. Lower 16 bits of the address.

2. Bit 7 can only be written with 0 for flag clearing.

585

16.2 Register Descriptions

16.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

AD9

Bit

Initial value

R/W

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

—

There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of

A/D conversion.

The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected

channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte

(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and

stored. Bits 5 to 0 are always read as 0.

The correspondence between the analog input channels and ADDR registers is shown in

table 16-3.

ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower

byte, data transfer is performed via a temporary register (TEMP). For details, see section 16.3,

Interface to Bus Master.

The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop

mode.

Table 16-3 Analog Input Channels and Corresponding ADDR Registers

Analog Input Channel

Channel Set 0 (CH3 = 0) Channel Set 1 (CH3 = 1)

Group 0 Group 1 Group 0 Group 1 A/D Data Register

AN0 AN4 AN8 AN12 ADDRA

AN1 AN5 AN9 AN13 ADDRB

AN2 AN6 AN10 AN14 ADDRC

AN3 AN7 AN11 AN15 ADDRD

586

16.2.2 A/D Control/Status Register (ADCSR)

ADF

R/(W)*

ADIE

R/W

ADST

R/W

SCAN

R/W

CH3

R/W

CH0

R/W

CH2

R/W

CH1

R/W

Bit

Initial value

R/W

Note: * Only 0 can be written to bit 7, to clear this flag.

ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.

ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.

Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.

Bit 7

ADF Description

0 [Clearing conditions] (Initial value)

• When 0 is written to the ADF flag after reading ADF = 1

• When the DTC is activated by an ADI interrupt and ADDR is read

1 [Setting conditions]

• Single mode: When A/D conversion ends

• Scan mode: When A/D conversion ends on all specified channels

Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests

at the end of A/D conversion.

Bit 6

ADIE Description

0 A/D conversion end interrupt (ADI) request disabled (Initial value)

1 A/D conversion end interrupt (ADI) request enabled

587

Bit 5—A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1

during A/D conversion.

The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external

trigger input pin (ADTRG).

Bit 5

ADST Description

0• A/D conversion stopped (Initial value)

1• Single mode: A/D conversion is started. Cleared to 0 automatically when

conversion on the specified channel ends

• Scan mode: A/D conversion is started. Conversion continues sequentially on the

selected channels until ADST is cleared to 0 by software, a reset, or

a transition to standby mode or module stop mode.

Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating

mode. See section 16.4, Operation, for single mode and scan mode operation. Only set the SCAN

bit while conversion is stopped (ADST = 0).

Bit 4

SCAN Description

0 Single mode (Initial value)

1 Scan mode

Bit 3—Channel Select 3 (CH3): Switches the analog input pins assigned to group 0 or group 1.

Setting CH3 to 1 enables AN8 to AN15 to be used instead of AN0 to AN7.

Bit 3

CH3 Description

0 AN8 to AN11 are group 0 analog input pins, AN12 to AN15 are group 1 analog input

pins

1 AN0 to AN3 are group 0 analog input pins, AN4 to AN7 are group 1 analog input pins

(Initial value)

588

Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select

the analog input channels.

Only set the input channel while conversion is stopped (ADST = 0).

Channel Selection Description

CH3 CH2 CH1 CH0 Single Mode

(SCAN = 0) Scan Mode

(SCAN = 1)

0000 AN0 (Initial value) AN0

1 AN1 AN0, AN1

1 0 AN2 AN0 to AN2

1 AN3 AN0 to AN3

1 0 0 AN4 AN4

1 AN5 AN4, AN5

1 0 AN6 AN4 to AN6

1 AN7 AN4 to AN7

1000 AN8 AN8

1 AN9 AN8, AN9

1 0 AN10 AN8 to AN10

1 AN11 AN8 to AN11

1 0 0 AN12 AN12

1 AN13 AN12, AN13

1 0 AN14 AN12 to AN14

1 AN15 AN12 to AN15

589

16.2.3 A/D Control Register (ADCR)

TRGS1

R/W

TRGS0

R/W

—

CKS1

R/W

—

CKS0

R/W

—

Bit

Initial value

R/W

ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D

conversion operations and sets the A/D conversion time.

ADCR is initialized to H'33 by a reset, and in standby mode or module stop mode.

Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of

the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion

is stopped (ADST = 0).

Bit 7 Bit 6

TRGS1 TRGS0 Description

0 0 A/D conversion start by software is enabled (Initial value)

1 A/D conversion start by TPU conversion start trigger is enabled

1 0 Setting prohibited

1 A/D conversion start by external trigger pin (ADTRG) is enabled

Bits 5, 4, 1, and 0—Reserved: These bits are always read as 1 and cannot be modified.

Bits 3 and 2—Clock Select 1 and 0 (CKS1, CKS0): These bits select the A/D conversion time.

The conversion time should be changed only when ADST = 0. Make a setting that gives a value

not lower than that shown in table 21-8, A/D Converter Characteristics.

Bit 3 Bit 2

CKS1 CKS0 Description

0 0 Conversion time = 530 states (max.) (Initial value)

1 Conversion time = 266 states (max.)

1 0 Conversion time = 134 states (max.)

1 Conversion time = 68 states (max.)

590

16.2.4 Module Stop Control Register A (MSTPCRA)

MSTPA7

R/W

MSTPA6

R/W

MSTPA5

R/W

MSTPA4

R/W

MSTPA3

R/W

MSTPA0

R/W

MSTPA2

R/W

MSTPA1

R/W

Bit

Initial value

R/W

MSTPCR is a 8-bit readable/writable register that performs module stop mode control.

When the MSTPA1 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus

cycle and a transition is made to module stop mode. Registers cannot be read or written to in

module stop mode. For details, see section 20.5, Module Stop Mode.

MSTPCRA is initialized to H'3F by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 1—Module Stop (MSTPA1): Specifies the A/D converter module stop mode.

Bit 1

MSTPA1 Description

0 A/D converter module stop mode cleared

1 A/D converter module stop mode set (Initial value)

591

16.3 Interface to Bus Master

ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide.

Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is

accessed via a temporary register (TEMP).

A data read from ADDR is performed as follows. When the upper byte is read, the upper byte

value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the

lower byte is read, the TEMP contents are transferred to the CPU.

When reading ADDR. always read the upper byte before the lower byte. It is possible to read only

the upper byte, but if only the lower byte is read, incorrect data may be obtained.

Figure 16-2 shows the data flow for ADDR access.

Bus master

(H'AA)

ADDRnH

(H'AA) ADDRnL

(H'40)

Lower byte read

ADDRnH

(H'AA) ADDRnL

(H'40)

TEMP

(H'40)

TEMP

(H'40)

(n = A to D)

Module data bus

Bus interface

Upper byte read

Bus master

(H'40) Bus interface

Figure 16-2 ADDR Access Operation (Reading H'AA40)

592

16.4 Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two

operating modes: single mode and scan mode.

16.4.1 Single Mode (SCAN = 0)

Single mode is selected when A/D conversion is to be performed on a single channel only. A/D

conversion is started when the ADST bit is set to 1, according to the software or external trigger

input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0

when conversion ends.

On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an

ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR.

When the operating mode or analog input channel must be changed during analog conversion, to

prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After

making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit

can be set at the same time as the operating mode or input channel is changed.

Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure

16-3 shows a timing diagram for this example.

[1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH3 = 0, CH2 = 0,

CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started

(ADST = 1).

[2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the

ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.

[3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.

[4] The A/D interrupt handling routine starts.

[5] The routine reads ADCSR, then writes 0 to the ADF flag.

[6] The routine reads and processes the connection result (ADDRB).

[7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,

A/D conversion starts again and steps [2] to [7] are repeated.

593

ADIE

ADST

ADF

State of channel 0 (AN0)

A/D

conversion

starts

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 1 (AN1)

State of channel 2 (AN2)

State of channel 3 (AN3)

Note: * Vertical arrows ( ) indicate instructions executed by software.

Set*

Clear*Clear*

A/D conversion result 1

A/D conversion

A/D conversion result 2

Read conversion result

Idle

Idle Idle

A/D conversion

Set*

Figure 16-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)

594

16.4.2 Scan Mode (SCAN = 1)

Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the

ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the

first channel in the group (AN0). When two or more channels are selected, after conversion of the

first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion

continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion

results are transferred for storage into the ADDR registers corresponding to the channels.

When the operating mode or analog input channel must be changed during analog conversion, to

prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After

making the necessary changes, set the ADST bit to 1 to start A/D conversion again from the first

channel (AN0). The ADST bit can be set at the same time as the operating mode or input channel

is changed.

Typical operations when three channels (AN0 to AN2) are selected in scan mode are described

next. Figure 16-4 shows a timing diagram for this example.

[1] Scan mode is selected (SCAN = 1), channel set 0 is selected (CH3 = 0), scan group 0 is

selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and

A/D conversion is started (ADST = 1)

[2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to

ADDRA. Next, conversion of the second channel (AN1) starts automatically.

[3] Conversion proceeds in the same way through the third channel (AN2).

[4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set

to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this

time, an ADI interrupt is requested after A/D conversion ends.

[5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is

cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion

starts again from the first channel (AN0).

595

ADST

ADF

ADDRA

ADDRB

ADDRC

ADDRD

State of channel 0 (AN0)

State of channel 1 (AN1)

State of channel 2 (AN2)

State of channel 3 (AN3)

Set*

Clear*

Idle

Notes: 1. Vertical arrows ( ) indicate instructions executed by software.

2. Data currently being converted is ignored.

Clear*

Idle

A/D conversion time

Idle

Continuous A/D conversion execution

A/D conversion 1

Idle Idle

Idle

Transfer

A/D conversion 3

A/D conversion 2 A/D conversion 5

A/D conversion 4

A/D conversion result 1

A/D conversion result 2

A/D conversion result 3

A/D conversion result 4

Figure 16-4 Example of A/D Converter Operation

(Scan Mode, 3 Channels AN0 to AN2 Selected)

596

16.4.3 Input Sampling and A/D Conversion Time

The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog

input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D

conversion timing. Table 16-4 indicates the A/D conversion time.

As indicated in figure 16-5, the A/D conversion time includes tD and the input sampling time. The

length of tD varies depending on the timing of the write access to ADCSR. The total conversion

time therefore varies within the ranges indicated in table 16-4.

In scan mode, the values given in table 16-4 apply to the first conversion time. The values given

in table 16-5 apply to the second and subsequent conversions. In both cases, set bits CKS1 and

CKS0 in ADCR to give a value not lower than that shown in table 21-8, A/D Converter

Characteristics.

(1)

(2)

tDtSPL tCONV

Input sampling

timing

ADF

Address

Write signal

Legend

(1) : ADCSR write cycle

(2) : ADCSR address

tD: A/D conversion start delay

tSPL : Input sampling time

tCONV : A/D conversion time

Figure 16-5 A/D Conversion Timing

597

Table 16-4 A/D Conversion Time (Single Mode)

CKS1 = 0 CKS1 = 0

CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1

Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max

A/D conversion start delay tD18 — 33 10 — 17 6 — 9 4 — 5

Input sampling time tSPL — 127 — — 63 — — 31 — — 15 —

A/D conversion time tCONV 515 — 530 259 — 266 131 — 134 67 — 68

Note: Values in the table are the number of states.

Table 16-5 A/D Conversion Time (Scan Mode)

CKS1 CKS0 Conversion Time (State)

0 0 512 (Fixed)

1 256 (Fixed)

1 0 128 (Fixed)

1 64 (Fixed)

16.4.4 External Trigger Input Timing

A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in

ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets

the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan

modes, are the same as if the ADST bit has been set to 1 by software. Figure 16-6 shows the

timing.

ADTRG

Internal trigger signal

ADST

A/D conversion

Figure 16-6 External Trigger Input Timing

598

16.5 Interrupts

The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.

ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR.

The DTC can be activated by an ADI interrupt. Having the converted data read by the DTC in

response to an ADI interrupt enables continuous conversion to be achieved without imposing a

load on software.

The A/D converter interrupt source is shown in table 16-6.

Table 16-6 A/D Converter Interrupt Source

Interrupt Source Description DTC Activation

ADI Interrupt due to end of conversion Possible

16.6 Usage Notes

The following points should be noted when using the A/D converter.

Setting Range of Analog Power Supply and Other Pins:

(1) Analog input voltage range

The voltage applied to analog input pin ANn during A/D conversion should be in the range

AVSS ≤ ANn ≤ Vref.

(2) Relation between AVCC, AVSS and VCC, VSS

As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D

converter is not used, the AVCC and AVSS pins must on no account be left open.

(3) Vref input range

The analog reference voltage input at the Vref pin set in the range Vref ≤ AVCC.

If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely

affected.

Notes on Board Design: In board design, digital circuitry and analog circuitry should be as

mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit

signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so

may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D

conversion values.

599

Also, digital circuitry must be isolated from the analog input signals (AN0 to AN15), analog

reference power supply (Vref), and analog power supply (AVCC) by the analog ground (AVSS).

Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS)

on the board.

Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an

abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN15) and analog

reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure

16-7.

Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to

AN0 to AN15 must be connected to AVSS.

If a filter capacitor is connected as shown in figure 16-7, the input currents at the analog input pins

(AN0 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is performed

frequently, as in scan mode, if the current charged and discharged by the capacitance of the

sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance

(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required

when deciding the circuit constants.

AVCC

*1*1

Vref

AN0 to AN15

AVSS

Notes: Values are reference values.

2. Rin: Input impedance

Rin*2100 Ω

0.1 µF

0.01 µF10 µF

Figure 16-7 Example of Analog Input Protection Circuit

600

Table 16-7 Analog Pin Specifications

Item Min Max Unit

Analog input capacitance — 20 pF

Permissible signal source impedance — 5 kΩ

20 pF

To A/D converterAN0 to AN15 10 kΩ

Note: Values are reference values.

Figure 16-8 Analog Input Pin Equivalent Circuit

A/D Conversion Precision Definitions: H8S/2626 Series and H8S/2623 Series A/D conversion

precision definitions are given below.

• Resolution

The number of A/D converter digital output codes

• Offset error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from the minimum voltage value B'0000000000 (H'00) to

B'0000000001 (H'01) (see figure 16-10).

• Full-scale error

The deviation of the analog input voltage value from the ideal A/D conversion characteristic

when the digital output changes from B'1111111110 (H'3E) to B'1111111111 (H'3F) (see

figure 16-10).

• Quantization error

The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16-9).

• Nonlinearity error

The error with respect to the ideal A/D conversion characteristic between the zero voltage and

the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.

• Absolute precision

The deviation between the digital value and the analog input value. Includes the offset error,

full-scale error, quantization error, and nonlinearity error.

601

111

110

101

100

011

010

001

000 FS

Quantization error

Digital output

Ideal A/D conversion

characteristic

Analog

input voltage

1024 2

1024 1022

1024 1023

1024

Figure 16-9 A/D Conversion Precision Definitions (1)

Offset error

Nonlinearity

error

Actual A/D conversion

characteristic

Analog

input voltage

Digital output

Ideal A/D conversion

characteristic

Full-scale error

Figure 16-10 A/D Conversion Precision Definitions (2)

602

Permissible Signal Source Impedance: H8S/2626 Series and H8S/2623 Series analog input is

designed so that conversion precision is guaranteed for an input signal for which the signal source

impedance is 10 kΩ or less. This specification is provided to enable the A/D converter’s sample-

and-hold circuit input capacitance to be charged within the sampling time; if the sensor output

impedance exceeds 10 kΩ, charging may be insufficient and it may not be possible to guarantee

the A/D conversion precision.

However, if a large capacitance is provided externally, the input load will essentially comprise

only the internal input resistance of 10 kΩ, and the signal source impedance is ignored.

However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an

analog signal with a large differential coefficient (e.g., 5 mV/µs or greater).

When converting a high-speed analog signal, a low-impedance buffer should be inserted.

Influences on Absolute Precision: Adding capacitance results in coupling with GND, and

therefore noise in GND may adversely affect absolute precision. Be sure to make the connection

to an electrically stable GND such as AVSS.

Care is also required to insure that filter circuits do not communicate with digital signals on the

mounting board, so acting as antennas.

A/D converter

equivalent circuit

H8S/2626 Series or

H8S/2623 Series

20 pF

Cin =

15 pF

10 kΩ

to 5 kΩ

Low-pass

filter

C to 0.1 µF

Sensor output

impedance

Sensor input

Figure 16-11 Example of Analog Input Circuit

603

Section 17 D/A Converter

[Provided in the H8S/2626 Series only]

17.1 Overview

The H8S/2626 Series has an on-chip two-channel D/A converter.

17.1.1 Features

The D/A converter has the following features.

• 8-bit resolution

• Two output channels

• Conversion time: maximum 10 µs (with 20 pF capacitive load)

• Output voltage: 0 V to Vref

• D/A output retention in software standby mode

• Module stop mode setting possible

 The initial setting is for D/A converter operation to be halted. Register access is enabled by

clearing module stop mode.

604

17.1.2 Block Diagram

Figure 17-1 shows a block diagram of the D/A converter.

Module data bus Internal data bus

Vref

AVCC

DA3

DA2

AVSS

8-bit D/A

Control circuit

DADR2

Legend

DACR23: D/A control register 23

DADR2, DADR3: D/A data registers 2 and 3

Bus interface

DADR3

DACR23

Figure 17-1 Block Diagram of D/A Converter

605

17.1.3 Pin Configuration

Table 17-1 summarizes the input and output pins used by the D/A converter.

Table 17-1 D/A Converter Pins

Pin Name Symbol I/O Function

Analog power supply pin AVCC Input Analog power supply

Analog ground pin AVSS Input Analog ground and reference voltage

Analog output pin 2 DA2 Output Channel 2 analog output

Analog output pin 3 DA3 Output Channel 3 analog output

Reference voltage pin Vref Input Analog reference voltage

17.1.4 Register Configuration

Table 17-2 summarizes the registers of the D/A converter.

Table 17-2 D/A Converter Registers

Channel Name Abbreviation R/W Initial Value Address*

2, 3 D/A data register 2 DADR2 R/W H'00 H'FDAC

D/A data register 3 DADR3 R/W H'00 H'FDAD

D/A control register 23 DACR23 R/W H'1F H'FDAE

All Module stop control register C MSTPCRC R/W H'FF H'FDEA

Note: *Lower 16 bits of the address

606

17.2 Register Descriptions

17.2.1 D/A Data Registers 2 and 3 (DADR2, DADR3)

Bit:76543210

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

DADR2 and DADR3 are 8-bit readable/writable registers that store the data to be converted.

When analog output is enabled, the values in DADR2 and DADR3 are constantly converted and

output at the analog output pins.

The D/A data registers are initialized to H'00 by a reset and in hardware standby mode.

17.2.2 D/A Control Register 23 (DACR23)

Bit:76543210

DAOE1 DAOE0 DAE — — — — —

Initial value : 0 0 0 1 1 1 1 1

R/W : R/W R/W R/W — — — — —

DACR23 is an 8-bit readable/writable register that controls the operation of the D/A converter.

DACR23 is initialized to H'1F by a reset and in hardware standby mode.

Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.

Bit 7

DAOE1 Description

0 DA3 analog output is disabled (Initial value)

1 Channel 3 D/A conversion and DA3 analog output are enabled

Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output.

Bit 6

DAOE0 Description

0 DA2 analog output is disabled (Initial value)

1 Channel 2 D/A conversion and DA2 analog output are enabled

607

Bit 5—D/A Enable (DAE): Controls D/A conversion, together with bits DAOE0 and DAOE1.

When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 2 and 3.

When the DAE bit is set to 1, D/A conversion is controlled together in channels 2 and 3.

Output of the conversion result is always controlled independently by bits DAOE0 and DAOE1.

Bit 7 Bit 6 Bit 5

DAOE1 DAOE0 DAE Description

00*D/A conversion is disabled in channels 2 and 3 (Initial value)

1 0 D/A conversion is enabled in channel 2

D/A conversion is disabled in channel 3

1 D/A conversion is enabled in channels 2 and 3

0 0 0 D/A conversion is disabled in channel 2

D/A conversion is enabled in channel 3

1 D/A conversion is enabled in channels 2 and 3

1*D/A conversion is enabled in channels 2 and 3

*: Don’t care

If the chip enters software standby mode while D/A conversion is enabled, the D/A output is

retained and the analog power supply current is the same as the analog power supply current

during D/A conversion. If it is necessary to reduce the analog power supply current in software

standby mode, D/A output should be disabled by clearing both the DAOE0 bit and the DAOE1 bit

to 0.

Bits 4 to 0—Reserved: These bits are always read as 1, and cannot be modified.

608

17.2.3 Module Stop Control Register C (MSTPCRC)

Bit:76543210

MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.

When the MSTPC5 bit is set to 1, D/A converter operation is stopped at the end of the bus cycle,

and module stop mode is entered. Register read/write accesses are not possible in module stop

mode. For details, see section 21B.5, Module Stop Mode.

MSTPCRC is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 5—Module Stop (MSTPC5): Specifies module stop mode for the D/A converter (channels 2

and 3).

Bit 5

MSTPC5 Description

0 D/A converter (channel 2 and 3) module stop mode is cleared

1 D/A converter (channel 2 and 3) module stop mode is set (Initial value)

609

17.3 Operation

The D/A converter has two built-in D/A conversion circuits that can perform conversion

independently.

D/A conversion is performed constantly while enabled in DACR23. If the DADR2 or DADR3

value is modified, conversion of the new data begins immediately. The conversion results are

output when bits DAOE0 and DAOE1 are set to 1.

An example of D/A conversion on channel 2 is given below. The timing is shown in figure 17-2.

1. Data to be converted is written in DADR2.

2. Bit DAOE0 is set to 1 in DACR23. D/A conversion starts and DA2 becomes an output pin.

The conversion result is output after the conversion time. The output value is (DADR2

contents/256) × Vref. Output of this conversion result continues until the value in DADR2 is

modified or the DAOE0 bit is cleared to 0.

3. If the DADR2 value is modified, conversion starts immediately, and the result is output after

the conversion time.

4. When the DAOE0 bit is cleared to 0, DA2 becomes an input pin.

Conversion data 1

Conversion

result 1

High-impedance state

tDCONV

DADR2

write cycle

DA2

DAOE0

DADR2

Address

DACR23

write cycle

Conversion data 2

Conversion

result 2

tDCONV

Legend

tDCONV: D/A conversion time

DADR2

write cycle DACR23

write cycle

Figure 17-2 Example of D/A Converter Operation

610

611

Section 18 RAM

18.1 Overview

The H8S/2626 and H8S/2623 have 12 kbytes of on-chip high-speed static RAM, the H8S/2625

and H8S/2622 have 8 kbytes, and the H8S/2624 and H8S/2621 have 4 kbytes. The RAM is

connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data

and word data. This makes it possible to perform fast word data transfer.

The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the

system control register (SYSCR).

18.1.1 Block Diagram

Figure 18-1 shows a block diagram of the on-chip RAM.

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

H'FFC000

H'FFC002

H'FFC004

H'FFFFC0

H'FFC001

H'FFC003

H'FFC005

H'FFFFC1

H'FFFFFE H'FFFFFF

H'FFEFBE H'FFEFBF

Figure 18-1 Block Diagram of RAM (H8S/2623)

612

18.1.2 Register Configuration

The on-chip RAM is controlled by SYSCR. Table 18-1 shows the address and initial value of

SYSCR.

Table 18-1 RAM Register

Name Abbreviation R/W Initial Value Address*

System control register SYSCR R/W H'01 H'FDE5

Note: *Lower 16 bits of the address.

18.2 Register Descriptions

18.2.1 System Control Register (SYSCR)

MACS

R/W

—

INTM1

R/W

INTM0

R/W

NMIEG

R/W

RAME

R/W

—

R/W

—

Bit

Initial value

R/W

The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in

SYSCR, see section 3.2.2, System Control Register (SYSCR).

Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is

initialized when the reset state is released. It is not initialized in software standby mode.

Note: When the DTC is used, the RAME bit must be set to 1.

Bit 0

RAME Description

0 On-chip RAM is disabled

1 On-chip RAM is enabled (Initial value)

613

18.3 Operation

When the RAME bit is set to 1, accesses to addresses H'FFC000 to H'FFEFBF and H'FFFFC0 to

H'FFFFFF in the H8S/2626 and H8S/2623, to addresses H'FFD000 to H'FFEFBF and H'FFFFC0

to H'FFFFFF in the H8S/2625 and H8S/2622, and to addresses H'FFE000 to H'FFEFBF and

H'FFFFC0 to H'FFFFFF in the H8S/2624 and H8S/2621, are directed to the on-chip RAM. When

the RAME bit is cleared to 0, the off-chip address space is accessed.

Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to

and read in byte or word units. Each type of access can be performed in one state.

Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start

at an even address.

18.4 Usage Notes

When Using the DTC: DTC register information can be located in addresses H'FFEBC0 to

H'FFEFBF. When the DTC is used, the RAME bit must not be cleared to 0.

Reserved Areas: Addresses H'FFB000 to H'FFBFFF in the H8S/2626 and H8S/2623, H'FFB000

to H'FFCFFF in the H8S/2625 and H8S/2622, and H'FFB000 to H'FFDFFF in the H8S/2624 and

H8S/2621, are reserved areas that cannot be read or written to. When the RAME bit is cleared to

0, external address space is accessed.

614

615

Section 19 ROM

19.1 Features

The H8S/2626 Series and H8S/2623 Series have 256 kbytes of on-chip flash memory. The

features of the flash memory are summarized below.

• Four flash memory operating modes

 Program mode

 Erase mode

 Program-verify mode

 Erase-verify mode

• Programming/erase methods

The flash memory is programmed 128 bytes at a time. Block erase (in single-block units) can

be performed. To erase the entire flash memory, each block must be erased in turn. Block

erasing can be performed as required on 4-kbyte, 32-kbyte, and 64-kbyte blocks.

• Programming/erase times

The flash memory programming time is 10 ms (typ.) for simultaneous 128-byte programming,

equivalent to 78 µs (typ.) per byte, and the erase time is 100 ms (typ.).

• Reprogramming capability

The flash memory can be reprogrammed up to 100 times.

• On-board programming modes

There are two modes in which flash memory can be programmed/erased/verified on-board:

 Boot mode

 User program mode

• Automatic bit rate adjustment

With data transfer in boot mode, the LSI’s bit rate can be automatically adjusted to match the

transfer bit rate of the host.

• Flash memory emulation in RAM

Flash memory programming can be emulated in real time by overlapping a part of RAM onto

flash memory.

• Protect modes

There are three protect modes, hardware, software, and error protection which allow protected

status to be designated for flash memory program/erase/verify operations.

• Programmer mode

Flash memory can be programmed/erased in programmer mode, using a PROM programmer,

as well as in on-board programming mode.

616

19.2 Overview

19.2.1 Block Diagram

Module bus

Bus interface/controller

Flash memory

(256 kbytes)

Operating

mode

FLMCR2

Internal address bus

Internal data bus (16 bits)

FWE pin

Mode pin

EBR1

EBR2

RAMER

FLPWCR

FLMCR1

Flash memory control register 1

Flash memory control register 2

Erase block register 1

Erase block register 2

RAM emulation register

Flash memory power control register

Legend

FLMCR1:

FLMCR2:

EBR1:

EBR2:

RAMER:

FLPWCR:

Figure 19-1 Block Diagram of Flash Memory

617

19.2.2 Mode Transitions

When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the

microcomputer enters an operating mode as shown in figure 19-2. In user mode, flash memory can

be read but not programmed or erased.

The boot, user program and programmer modes are provided as modes to write and erase the flash

memory.

Boot mode

On-board programming mode

User

program mode

User mode

(on-chip ROM

enabled)

Reset state

Programmer

mode

RES = 0

FWE = 1 FWE = 0

Notes: Only make a transition between user mode and user program mode when the CPU is

not accessing the flash memory.

1. RAM emulation possible

2. MD0 = 0, MD1 = 0, MD2 = 0, P14 = 0, P16 = 0, PF0 = 1

RES = 0

MD1 = 1,

MD2 = 0,

FWE = 1

RES = 0

MD1 = 1,

MD2 = 1,

FWE = 0

MD1 = 1,

MD2 = 1,

FWE = 1

Figure 19-2 Flash Memory State Transitions

618

19.2.3 On-Board Programming Modes

Boot Mode

Flash memory

LSI

RAM

Host

Programming control

program

SCI

Application program

(old version)

New application

program

Flash memory

LSI

RAM

Host

SCI

Application program

(old version)

Boot program area

New application

program

Flash memory

LSI

RAM

Host

SCI

Flash memory

preprogramming

erase

Boot program

New application

program

Flash memory

LSI

Program execution state

RAM

Host

SCI

New application

program

Boot program

Programming control

program

1. Initial state

The old program version or data remains written

in the flash memory. The user should prepare the

programming control program and new

application program beforehand in the host.

2. Programming control program transfer

When boot mode is entered, the boot program

in the H8S/2626 or H8S/2623 (originally

incorporated in the chip) is started and the

programming control program in the host is

transferred to RAM via SCI communication. The

boot program required for flash memory erasing

is automatically transferred to the RAM boot

program area.

3. Flash memory initialization

The erase program in the boot program area (in

RAM) is executed, and the flash memory is

initialized (to H'FF). In boot mode, total flash

memory erasure is performed, without regard to

blocks.

4. Writing new application program

The programming control program transferred

from the host to RAM is executed, and the new

application program in the host is written into the

flash memory.

Programming control

program

Boot programBoot program

Boot program area Boot program area

Programming control

program

619

User Program Mode

Flash memory

LSI

RAM

Host

Programming/

erase control program

SCI

Boot program

New application

program

Flash memory

LSI

RAM

Host

SCI

New application

program

Flash memory

LSI

RAM

Host

SCI

Flash memory

erase

Boot program

New application

program

Flash memory

LSI

Program execution state

RAM

Host

SCI

Boot program

FWE assessment

program

Application program

(old version)

New application

program

1. Initial state

The FWE assessment program that confirms that

user program mode has been entered, and the

program that will transfer the programming/erase

control program from flash memory to on-chip

RAM should be written into the flash memory by

the user beforehand. The programming/erase

control program should be prepared in the host or

in the flash memory.

2. Programming/erase control program transfer

When user program mode is entered, user

software confirms this fact, executes transfer

program in the flash memory, and transfers the

programming/erase control program to RAM.

3. Flash memory initialization

The programming/erase program in RAM is

executed, and the flash memory is initialized (to

H'FF). Erasing can be performed in block units,

but not in byte units.

4. Writing new application program

Next, the new application program in the host is

written into the erased flash memory blocks. Do

not write to unerased blocks.

Programming/

erase control program

Programming/

erase control program

Programming/

erase control program

Transfer program

Application program

(old version)

Transfer program

FWE assessment

program

FWE assessment

program

Transfer program

FWE assessment

program

Transfer program

620

19.2.4 Flash Memory Emulation in RAM

Emulation should be performed in user mode or user program mode. When the emulation block

set in RAMER is accessed while the emulation function is being executed, data written in the

overlap RAM is read.

Application program

Execution state

Flash memory

Emulation block

RAM

SCI

Overlap RAM

(emulation is performed

on data written in RAM)

Figure 19-3 Reading Overlap RAM Data in User Mode or User Program Mode

When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and

writes should actually be performed to the flash memory.

When the programming control program is transferred to RAM, ensure that the transfer

destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to

be rewritten.

621

Application program

Flash memory RAM

SCI

Programming control

program execution state

Overlap RAM

(programming data)

Programming data

Figure 19-4 Writing Overlap RAM Data in User Program Mode

19.2.5 Differences between Boot Mode and User Program Mode

Table 19-1 Differences between Boot Mode and User Program Mode

Boot Mode User Program Mode

Total erase Yes Yes

Block erase No Yes

Programming control program*Program/program-verify Erase/erase-verify

Program/program-verify

Emulation

Note: *To be provided by the user, in accordance with the recommended algorithm.

622

19.2.6 Block Configuration

The flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte

blocks.

Address H'00000

Address H'3FFFF

64 kbytes

32 kbytes

64 kbytes

256 kbytes

4 kbytes × 8

Figure 19-5 Flash Memory Block Configuration

19.3 Pin Configuration

The flash memory is controlled by means of the pins shown in table 19-2.

Table 19-2 Pin Configuration

Pin Name Abbreviation I/O Function

Reset RES Input Reset

Flash write enable FWE Input Flash memory program/erase protection by hardware

Mode 2 MD2 Input Sets MCU operating mode

Mode 1 MD1 Input Sets MCU operating mode

Mode 0 MD0 Input Sets MCU operating mode

Port F0 PF0 Input Sets MCU operating mode in programmer mode

Port 16 P16 Input Sets MCU operating mode in programmer mode

Port 14 P14 Input Sets MCU operating mode in programmer mode

Transmit data TxD2 Output Serial transmit data output

Receive data RxD2 Input Serial receive data input

623

19.4 Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 19-3.

In order to access these registers, the FLSHE bit in SCRX must be set to 1 (except for RAMER,

SCRX).

Table 19-3 Register Configuration

Flash memory control register 1 FLMCR1*5R/W*2H'00*3H'FFA8

Flash memory control register 2 FLMCR2*5R*2H'00 H'FFA9

Erase block register 1 EBR1*5R/W*2H'00*4H'FFAA

Erase block register 2 EBR2*5R/W*2H'00*4H'FFAB

RAM emulation register RAMER*5R/W H'00 H'FEDB

Flash memory power control register*6FLPWCR*5R/W*2H'00*4H'FFAC

Serial control register X SCRX R/W H'00 H'FDB4

Notes: 1. Lower 16 bits of the address.

2. To access these registers, set the FLSHE bit to 1 in serial control register X. Even if

FLSHE is set to 1, if the chip is in a mode in which the on-chip flash memory is

disabled, a read will return H'00 and writes are invalid. Writes are also invalid when the

FWE bit in FLMCR1 is not set to 1.

3. When a high level is input to the FWE pin, the initial value is H'80.

4. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in

FLMCR1 is not set, these registers are initialized to H'00.

5. FLMCR1, FLMCR2, EBR1, EBR2, RAMER, and FLPWCR are 8-bit registers.

Use byte access on these registers.

6. An invalid register in the H8S/2623.

19.5 Register Descriptions

19.5.1 Flash Memory Control Register 1 (FLMCR1)

FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode

or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when

FWE = 1, then setting the PV1 or EV1 bit. Program mode for addresses H'00000 to H'3FFFF is

entered by setting SWE1 bit to 1 when FWE = 1, then setting the PSU1 bit, and finally setting the

P1 bit. Erase mode for addresses H'00000 to H'3FFFF is entered by setting SWE1 bit to 1 when

FWE = 1, then setting the ESU1 bit, and finally setting the E1 bit. FLMCR1 is initialized by a

reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a

high level is input to the FWE pin, and H'00 when a low level is input. When on-chip flash

memory is disabled, a read will return H'00, and writes are invalid.

624

Writes are enabled only in the following cases: Writes to bit SWE1 of FLMCR1 enabled when

FWE = 1, to bits ESU1, PSU1, EV1, and PV1 when FWE = 1 and SWE1 = 1, to bit E1 when

FWE = 1, SWE1 = 1 and ESU1 = 1, and to bit P1 when FWE = 1, SWE1 = 1, and PSU1 = 1.

Bit: 7 6 5 4 3 2 1 0

FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1

Initial value: —*0000000

R/W: R R/W R/W R/W R/W R/W R/W R/W

Note: * Determined by the state of the FWE pin.

Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory

programming/erasing.

Bit 7: FWE Description

0 When a low level is input to the FWE pin (hardware-protected state)

1 When a high level is input to the FWE pin

Bit 6—Software Write Enable Bit 1 (SWE1): This bit selects write and erase valid/invalid of the

flash memory. Set it when setting bits 5 to 0, bits 7 to 0 of EBR1, and bits 3 to 0 of EBR2.

Bit 6: SWE1 Description

0 Writes disabled (Initial value)

1 Writes enabled

[Setting condition]

When FWE = 1

Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode. Set this bit to 1 before

setting the E1 bit in FLMCR1 to 1. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the

same time.

Bit 5: ESU1 Description

0 Erase setup cleared (Initial value)

1 Erase setup

[Setting condition]

When FWE = 1 and SWE1 = 1

Bit 4—Program Setup Bit 1 (PSU1): Prepares for a transition to program mode. Set this bit to 1

before setting the P1 bit in FLMCR1 to 1. Do not set the SWE1, ESU1, EV1, PV1, E1, or P1 bit

at the same time.

625

Bit 4: PSU1 Description

0 Program setup cleared (Initial value)

1 Program setup

[Setting condition]

When FWE = 1 and SWE1 = 1

Bit 3—Erase-Verify 1 (EV1): Selects erase-verify mode transition or clearing. Do not set the

SWE1, ESU1, PSU1, PV1, E1, or P1 bit at the same time.

Bit 3: EV1 Description

0 Erase-verify mode cleared (Initial value)

1 Transition to erase-verify mode

[Setting condition]

When FWE = 1 and SWE1 = 1

Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing. Do not set

the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time.

Bit 2: PV1 Description

0 Program-verify mode cleared (Initial value)

1 Transition to program-verify mode

[Setting condition]

When FWE = 1 and SWE1 = 1

Bit 1—Erase 1 (E1): Selects erase mode transition or clearing. Do not set the SWE1, ESU1,

PSU1, EV1, PV1, or P1 bit at the same time.

Bit 1: E1 Description

0 Erase mode cleared (Initial value)

1 Transition to erase mode

[Setting condition]

When FWE = 1, SWE1 = 1, and ESU1 = 1

626

Bit 0—Program 1 (P1): Selects program mode transition or clearing. Do not set the SWE1,

PSU1, ESU1, EV1, PV1, or E1 bit at the same time.

Bit 0: P1 Description

0 Program mode cleared (Initial value)

1 Transition to program mode

[Setting condition]

When FWE = 1, SWE1 = 1, and PSU1 = 1

19.5.2 Flash Memory Control Register 2 (FLMCR2)

FLMCR2 is an 8-bit register used for flash memory operating mode control. FLMCR2 is

initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When

on-chip flash memory is disabled, a read will return H'00.

Bit: 7 6 5 4 3 2 1 0

FLER — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R — — — — — — —

Note: FLMCR2 is a read-only register, and should not be written to.

Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on

flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-

protection state.

Bit 7: FLER Description

0 Flash memory is operating normally (Initial value)

Flash memory program/erase protection (error protection) is disabled

[Clearing condition]

Reset or hardware standby mode

1 An error has occurred during flash memory programming/erasing

Flash memory program/erase protection (error protection) is enabled

[Setting condition]

See 19.8.3, Error Protection

Bits 6 to 0—Reserved: These bits always read 0.

627

19.5.3 Erase Block Register 1 (EBR1)

EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is

initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low

level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE1 bit in

FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other

blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not

set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically

cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are

invalid.

The flash memory block configuration is shown in table 19-4.

Bit: 7 6 5 4 3 2 1 0

EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

19.5.4 Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is

initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low

level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE1 of FLMCR1 is not set, even

though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block

can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2

combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and

EBR2 to be automatically cleared to 0. Bits 7 to 4 are reserved and must only be written with 0.

When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.

The flash memory block configuration is shown in table 19-4.

Bit: 7 6 5 4 3 2 1 0

— — — — EB11 EB10 EB9 EB8

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R/W R/W R/W R/W R/W R/W R/W

628

Table 19-4 Flash Memory Erase Blocks

Block (Size) Addresses

EB0 (4 kbytes) H'000000–H'000FFF

EB1 (4 kbytes) H'001000–H'001FFF

EB2 (4 kbytes) H'002000–H'002FFF

EB3 (4 kbytes) H'003000–H'003FFF

EB4 (4 kbytes) H'004000–H'004FFF

EB5 (4 kbytes) H'005000–H'005FFF

EB6 (4 kbytes) H'006000–H'006FFF

EB7 (4 kbytes) H'007000–H'007FFF

EB8 (32 kbytes) H'008000–H'00FFFF

EB9 (64 kbytes) H'010000–H'01FFFF

EB10 (64 kbytes) H'020000–H'02FFFF

EB11 (64 kbytes) H'030000–H'03FFFF

19.5.5 RAM Emulation Register (RAMER)

RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating

real-time flash memory programming. RAMER initialized to H'00 by a reset and in hardware

standby mode. It is not initialized in software standby mode. RAMER settings should be made in

user mode or user program mode.

Flash memory area divisions are shown in table 19-5. To ensure correct operation of the emulation

function, the ROM for which RAM emulation is performed should not be accessed immediately

after this register has been modified. Normal execution of an access immediately after register

modification is not guaranteed.

Bit: 7 6 5 4 3 2 1 0

— — — — RAMS RAM2 RAM1 RAM0

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R/W R/W R/W R/W R/W R/W

Bits 7 and 6—Reserved: These bits always read 0.

Bits 5 and 4—Reserved: Only 0 may be written to these bits.

629

Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in

RAM. When RAMS = 1, all flash memory block are program/erase-protected.

Bit 3: RAMS Description

0 Emulation not selected (Initial value)

Program/erase-protection of all flash memory blocks is disabled

1 Emulation selected

Program/erase-protection of all flash memory blocks is enabled

Bits 2 to 0—Flash Memory Area Selection: These bits are used together with bit 3 to select the

flash memory area to be overlapped with RAM. (See table 19-5.)

Table 19-5 Flash Memory Area Divisions

Addresses Block Name RAMS RAM2 RAM1 RAM0

H'FFD000–H'FFDFFF RAM area 4 kbytes 0 ***

H'000000–H'000FFF EB0 (4 kbytes) 1 0 0 0

H'001000–H'001FFF EB1 (4 kbytes) 1 0 0 1

H'002000–H'002FFF EB2 (4 kbytes) 1 0 1 0

H'003000–H'003FFF EB3 (4 kbytes) 1 0 1 1

H'004000–H'004FFF EB4 (4 kbytes) 1 1 0 0

H'005000–H'005FFF EB5 (4 kbytes) 1 1 0 1

H'006000–H'006FFF EB6 (4 kbytes) 1 1 1 0

H'007000–H'007FFF EB7 (4 kbytes) 1 1 1 1

*: Don't care

19.5.6 Flash Memory Power Control Register (FLPWCR)*

Bit: 7 6 5 4 3 2 1 0

PDWND — — — — — — —

Initial value: 0 0 0 0 0 0 0 0

R/W: R/W R R R R R R R

FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI

switches to subactive mode.

Note: * An invalid register in the H8S/2623.

630

Bit 7—Power-Down Disable (PDWND): Enables or disables a transition to the flash memory

power-down mode when the LSI switches to subactive mode.

Bit 7: PDWND Description

0 Transition to flash memory power-down mode enabled (Initial value)

1 Transition to flash memory power-down mode disabled

Bits 6 to 0—Reserved: These bits always read 0.

19.5.7 Serial Control Register X (SCRX)

Bit 76543210

— — — — FLSHE — — —

Initial value 0 0 0 0 0 0 0 0

R/W R/W R/W R/W R/W R/W R/W R/W R/W

SCRX is an 8-bit readable/writable register that controls on-chip flash memory.

SCRX is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4—Reserved: Only 0 may be written to these bits.

Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash

memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1

enables read/write access to the flash memory control registers. If FLSHE is cleared to 0, the flash

memory control registers are deselected. In this case, the flash memory control register contents

are retained.

Bit 3: FLSHE Description

0 Flash control registers deselected in area H'FFFFA8 to H'FFFFAC (Initial value)

1 Flash control registers selected in area H'FFFFA8 to H'FFFFAC

Bits 2 to 0—Reserved: Only 0 may be written to these bits.

631

19.6 On-Board Programming Modes

When pins are set to on-board programming mode and a reset-start is executed, a transition is

made to the on-board programming state in which program/erase/verify operations can be

performed on the on-chip flash memory. There are two on-board programming modes: boot mode

and user program mode. The pin settings for transition to each of these modes are shown in table

19-6. For a diagram of the transitions to the various flash memory modes, see figure 19-2.

Table 19-6 Setting On-Board Programming Modes

Mode FWE MD2 MD1 MD0

Boot mode Expanded mode 1010

Single-chip mode 0 1 1

User program mode Expanded mode 1110

Single-chip mode 1 1 1

19.6.1 Boot Mode

When boot mode is used, the flash memory programming control program must be prepared in the

host beforehand. The SCI channel to be used is set to asynchronous mode.

When a reset-start is executed after the H8S/2626 or H8S/2623 pins have been set to boot mode,

the boot program built into the LSI is started and the programming control program prepared in

the host is serially transmitted to the LSI via the SCI. In the H8S/2626 and H8S/2623, the

programming control program received via the SCI is written into the programming control

program area in on-chip RAM. After the transfer is completed, control branches to the start

address of the programming control program area and the programming control program execution

state is entered (flash memory programming is performed).

The transferred programming control program must therefore include coding that follows the

programming algorithm given later.

The system configuration in boot mode is shown in figure 19-6, and the boot mode execution

procedure in figure 19-7.

632

RxD2

TxD2 SCI2

H8S/2626 or H8S/2623

Flash memory

Write data reception

Verify data transmission

Host

On-chip RAM

Figure 19-6 System Configuration in Boot Mode

633

Note: If a memory cell does not operate normally and cannot be erased, one H'FF byte is

transmitted as an erase error, and the erase operation and subsequent operations

are halted.

Start

Set pins to boot mode

and execute reset-start

Host transfers data (H'00)

continuously at prescribed bit rate

LSI measures low period

of H'00 data transmitted by host

LSI calculates bit rate and

sets value in bit rate register

After bit rate adjustment, LSI

transmits one H'00 data byte to

host to indicate end of adjustment

Host confirms normal reception

of bit rate adjustment end

indication (H'00), and transmits

one H'55 data byte

After receiving H'55,

LSI transmits one H'AA

data byte to host

Host transmits number

of programming control program

bytes (N), upper byte followed

by lower byte

LSI transmits received

number of bytes to host as verify

data (echo-back)

n = 1

Host transmits programming control

program sequentially in byte units

LSI transmits received

programming control program to

host as verify data (echo-back)

Transfer received programming

control program to on-chip RAM

n = N? No

Yes

End of transmission

Check flash memory data, and

if data has already been written,

erase all blocks

After confirming that all flash

memory data has been erased,

LSI transmits one H'AA data

byte to host

Execute programming control

program transferred to on-chip RAM

n + 1 → n

Figure 19-7 Boot Mode Execution Procedure

634

Automatic SCI Bit Rate Adjustment

Start

bit

Stop

bit

D0 D1 D2 D3 D4 D5 D6 D7

Low period (9 bits) measured (H'00 data) High period

(

1 or more bits

)

When boot mode is initiated, the LSI measures the low period of the asynchronous SCI

communication data (H'00) transmitted continuously from the host. The SCI transmit/receive

format should be set as follows: 8-bit data, 1 stop bit, no parity. The LSI calculates the bit rate of

the transmission from the host from the measured low period, and transmits one H'00 byte to the

host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end

indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception

cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.

Depending on the host’s transmission bit rate and the LSI’s system clock frequency, there will be

a discrepancy between the bit rates of the host and the LSI. Set the host transfer bit rate at 2,400,

4,800, 9,600 or 19,200 bps to operate the SCI properly.

Table 19-7 shows host transfer bit rates and system clock frequencies for which automatic

adjustment of the LSI bit rate is possible. The boot program should be executed within this system

clock range.

Table 19-7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is

Possible

Host Bit Rate System Clock Frequency for Which Automatic Adjustment

of LSI Bit Rate is Possible

2,400 bps 2 to 8 MHz

4,800 bps 4 to 16 MHz

9,600 bps 8 to 20 MHz

19,200 bps 16 to 20 MHz

635

On-Chip RAM Area Divisions in Boot Mode: In boot mode, the RAM area is divided into an

area used by the boot program and an area to which the programming control program is

transferred via the SCI, as shown in figure 19-8. The boot program area cannot be used until the

execution state in boot mode switches to the programming control program transferred from the

host.

H'FFC000

H'FFDFFF

H'FFE000

H'FFEFBF

Boot program area

(4 kbytes)

Programming

control program area

(8 kbytes)

Note: The boot program area cannot be used until a transition is made to the execution state for

the programming control program transferred to RAM. Note also that the boot program

remains in this area of the on-chip RAM even after control branches to the programming

control program.

Figure 19-8 RAM Areas in Boot Mode

Notes on Use of Boot Mode:

• When the chip comes out of reset in boot mode, it measures the low-level period of the input at

the SCI’s RxD2 pin. The reset should end with RxD2 high. After the reset ends, it takes

approximately 100 states before the chip is ready to measure the low-level period of the RxD2

pin.

• In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all

flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,

such as the first time on-board programming is performed, or if the program activated in user

program mode is accidentally erased.

• Interrupts cannot be used while the flash memory is being programmed or erased.

• The RxD2 and TxD2 pins should be pulled up on the board.

• Before branching to the programming control program (RAM area H'FFC000), the chip

terminates transmit and receive operations by the on-chip SCI (channel 2) (by clearing the RE

and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data

output pin, TxD2, goes to the high-level output state (PA1DDR = 1, PA1DR = 1).

636

The contents of the CPU’s internal general registers are undefined at this time, so these

registers must be initialized immediately after branching to the programming control program.

In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area

must be specified for use by the programming control program.

The initial values of other on-chip registers are not changed.

• Boot mode can be entered by making the pin settings shown in table 19-6 and executing a

reset-start.

Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting

the FWE pin and mode pins, and executing reset release*1. Boot mode can also be cleared by a

WDT overflow reset.

Do not change the mode pin input levels in boot mode, and do not drive the FWE pin low

while the boot program is being executed or while flash memory is being programmed or

erased*2.

• If the mode pin input levels are changed (for example, from low to high) during a reset, the

state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)

will change according to the change in the microcomputer’s operating mode*3.

Therefore, care must be taken to make pin settings to prevent these pins from becoming output

signal pins during a reset, or to prevent collision with signals outside the microcomputer.

Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (tMDS = 4

states) with respect to the reset release timing.

2. For further information on FWE application and disconnection, see 19.13, Flash

Memory Programming and Erasing Precautions.

3. See appendix D, Pin States.

19.6.2 User Program Mode

When set to user program mode, the chip can program and erase its flash memory by executing a

user program/erase control program. Therefore, on-board reprogramming of the on-chip flash

memory can be carried out by providing on-board means of FWE control and supply of

programming data, and storing a program/erase control program in part of the program area as

necessary.

To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7),

and apply a high level to the FWE pin. In this mode, on-chip supporting modules other than flash

memory operate as they normally would in modes 6 and 7.

The flash memory itself cannot be read while the SWE1 bit is set to 1 to perform programming or

erasing, so the control program that performs programming and erasing should be run in on-chip

RAM or external memory. If the program is to be located in external memory, the instruction for

writing to flash memory, and the following instruction, should be placed in on-chip RAM.

637

Figure 19-9 shows the procedure for executing the program/erase control program when

transferred to on-chip RAM.

Clear FWE*

FWE = high*

Branch to flash memory application

program

Branch to program/erase control

program in RAM area

Execute program/erase control

program (flash memory rewriting)

Transfer program/erase control

program to RAM

MD2, MD1, MD0 = 110, 111

Reset-start

Write the FWE assessment program and

transfer program (and the program/erase

control program if necessary) beforehand

Note: Do not apply a constant high level to the FWE pin. Apply a high level to the FWE pin

only when the flash memory is programmed or erased. Also, while a high level is

applied to the FWE pin, the watchdog timer should be activated to prevent

overprogramming or overerasing due to program runaway, etc.

*For further information on FWE application and disconnection, see 19.13, Flash

Memory Programming and Erasing Precautions.

Figure 19-9 User Program Mode Execution Procedure

638

19.7 Flash Memory Programming/Erasing

A software method, using the CPU, is employed to program and erase flash memory in the on-

board programming modes. There are four flash memory operating modes: program mode, erase

mode, program-verify mode, and erase-verify mode. Transitions to these modes for addresses

H'000000 to H'03FFFF are made by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in

FLMCR1.

The flash memory cannot be read while being programmed or erased. Therefore, the program

(user program) that controls flash memory programming/erasing should be located and executed in

on-chip RAM or external memory. If the program is to be located in external memory, the

instruction for writing to flash memory, and the following instruction, should be placed in on-chip

RAM. Also ensure that the DTC is not activated before or after execution of the flash memory

write instruction.

In the following operation descriptions, wait times after setting or clearing individual bits in

FLMCR1 are given as parameters; for details of the wait times, see 22.5, Flash Memory

Characteristics.

Notes: 1. Operation is not guaranteed if setting/resetting of the SWE1, ESU1, PSU1, EV1, PV1,

E1, and P1 bits in FLMCR1 is executed by a program in flash memory.

2. When programming or erasing, set FWE to 1 (programming/erasing will not be

executed if FWE = 0).

3. Programming must be executed in the erased state. Do not perform additional

programming on addresses that have already been programmed.

639

Normal mode

On-board

programming mode

Software programming

disable state

Erase setup

state Erase mode

Program mode

Erase-verify

mode

Program

setup state

Program-verify

mode

SWE1 = 1

SWE1 = 0

FWE = 1 FWE = 0

E1 = 1

E1 = 0

P1 = 1

P1 = 0

Software

programming

enable

state

Notes: In order to perform a normal read of flash memory, SWE1 must be cleared to 0. Also note that verify-reads

can be performed during the programming/erasing process.

1. : Normal mode : On-board programming mode

2. Do not make a state transition by setting or clearing multiple bits simultaneously.

3. After a transition from erase mode to the erase setup state, do not enter erase mode without passing

through the software programming enable state.

4. After a transition from program mode to the program setup state, do not enter program mode without

passing through the software programming enable state.

ESU1 = 0

ESU1 = 1

PSU1 = 1

PSU1 = 0

PV1 = 1

PV1 = 0

EV1 = 0

EV1 = 1

Figure 19-10 FLMCR1 Bit Settings and State Transitions

640

19.7.1 Program Mode

When writing data or programs to flash memory, the program/program-verify flowchart shown in

figure 19-11 should be followed. Performing programming operations according to this flowchart

will enable data or programs to be written to flash memory without subjecting the device to

voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes

at a time.

The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and

the maximum number of programming operations (N) are shown in table 22-9 in section 22.5,

Flash Memory Characteristics.

Following the elapse of (×0) µs or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte

program data is stored in the program data area and reprogram data area, and the 128-byte data in

the program data area in RAM is written consecutively to the program address (the lower 8 bits of

the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are

performed. The program address and program data are latched in the flash memory. A 128-byte

data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must

be written to the extra addresses.

Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.

Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)

is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of (y) µs or more, the

operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during

which the P1 bit is set is the flash memory programming time. Refer to the table in figure 19-11

for the programming time.

641

19.7.2 Program-Verify Mode

In program-verify mode, the data written in program mode is read to check whether it has been

correctly written in the flash memory.

After the elapse of the given programming time, clear the P1 bit in FLMCR1, then wait for at least

(α) µs before clearing the PSU1 bit to exit program mode. After the elapse of at least (β) µs, the

watchdog timer is cleared and the operating mode is switched to program-verify mode by setting

the PV1 bit in FLMCR1. Before reading in program-verify mode, a dummy write of H'FF data

should be made to the addresses to be read. The dummy write should be executed after the elapse

of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-bit units),

the data at the latched address is read. Wait at least (ε) µs after the dummy write before

performing this read operation. Next, the originally written data is compared with the verify data,

and reprogram data is computed (see figure 19-11) and transferred to RAM. After verification of

128 bytes of data has been completed, exit program-verify mode, wait for at least (η) µs, then

clear the SWE1 bit in FLMCR1. If reprogramming is necessary, set program mode again, and

repeat the program/program-verify sequence as before. The maximum number of repetitions of the

program/program-verify sequence is indicated by the maximum programming count (N).

However, ensure that the program/program-verify sequence is not repeated more than (N) times on

the same bits.

Notes on Program/Program-Verify Procedure

1. In order to perform 128-byte-unit programming, the lower 8 bits of the write start address must

be H'00 or H'80.

2. When performing continuous writing of 128-byte data to flash memory, byte-unit transfer

should be used.

128-byte data transfer is necessary even when writing fewer than 128 bytes of data. Write H'FF

data to the extra addresses.

3. Verify data is read in word units.

4. The write pulse is applied and a flash memory write executed while the P1 bit in FLMCR1 is

set. In the H8S/2626 and H8S/2623, write pulses should be applied as follows in the

program/program-verify procedure to prevent voltage stress on the device and loss of write

data reliability.

a. After write pulse application, perform a verify-read in program-verify mode and apply a

write pulse again for any bits read as 1 (reprogramming processing). When all the 0-write

bits in the 128-byte write data are read as 0 in the verify-read operation, the

program/program-verify procedure is completed. In the H8S/2626 and H8S/2623, the

number of loops in reprogramming processing is guaranteed not to exceed the maximum

value of the maximum programming count (N).

642

b. After write pulse application, a verify-read is performed in program-verify mode, and

programming is judged to have been completed for bits read as 0.

c. If programming of other bits is incomplete in the 128 bytes, reprogramming processing

should be executed. If a bit for which programming has been judged to be completed is

read as 1 in a subsequent verify-read, a write pulse should again be applied to that bit.

5. The period for which the P1 bit in FLMCR1 is set (the write pulse width) should be changed

according to the degree of progress through the program/program-verify procedure. For

detailed wait time specifications, see section 22.5, Flash Memory Characteristics.

6. The program/program-verify flowchart for the H8S/2626 and H8S/2623 is shown in figure 19-

11.

To cover the points noted above, bits on which reprogramming processing is to be executed,

and bits on which additional programming is to be executed, must be determined as shown

below.

Since reprogram data and additional-programming data vary according to the progress of the

programming procedure, it is recommended that the following data storage areas (128 bytes

each) be provided in RAM.

Reprogram Data Computation Table

(D)

Result of Verify-Read

after Write Pulse

Application (V) (X)

Result of Operation Comments

0 0 1 Programming completed: reprogramming

processing not to be executed

1 0 Programming incomplete: reprogramming

processing to be executed

10 1 

1 Still in erased state: no action

Legend

(D): Source data of bits on which programming is executed

(X): Source data of bits on which reprogramming is executed

643

Additional-Programming Data Computation Table

(X')

Result of Verify-Read

after Write Pulse

Application (V) (Y)

Result of Operation Comments

0 0 0 Programming by write pulse application

judged to be completed: additional

programming processing to be executed

1 1 Programming by write pulse application

incomplete: additional programming

processing not to be executed

1 0 Programming already completed: additional

programming processing not to be executed

1 Still in erased state: no action

Legend

(Y): Data of bits on which additional programming is executed

(X'): Data of bits on which reprogramming is executed in a certain reprogramming loop

7. It is necessary to execute additional programming processing during the course of the

H8S/2626 or H8S/2623 program/program-verify procedure. However, once 128-byte-unit

programming is finished, additional programming should not be carried out on the same

address area. When executing reprogramming, an erase must be executed first. Note that

normal operation of reads, etc., is not guaranteed if additional programming is performed on

addresses for which a program/program-verify operation has finished.

644

START

End of programming

Set SWE1 bit in FLMCR1

Wait (× 0) µstsswe:

tcpv:

tcswe:

n = 1

m = 0

Sub-Routine-Call

Set PV1 bit in FLMCR1

Wait (γ) µs

Wait (ε) µs

Read verify data

Wait (η) µs

Additional-programming data computation

Reprogram data computation

Transfer additional-programming data to

additional-programming data area

Transfer reprogram data to reprogram data area

Program data =

verify data?

Clear PV1 bit in FLMCR1

Clear SWE1 bit in FLMCR1

m = 1

128-byte data

verification completed?

Wait (×1) µs

m = 0 ?

N1 ≥ n ?

Increment address

Programming failure

Clear SWE1 bit in FLMCR1

Wait (×1) µs

n ≥ (N1 + N2) ?

n ← n + 1

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80. A 128-byte data transfer must be

performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.

2. Verify data is read in 16-bit (word) units.

3. Even bits for which programming has been completed in the 128-byte programming loop will be subject to programming again if they fail the

subsequent verify operation.

4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional-programming

data must be provided in RAM. The reprogram and additional-programming data contents are modified as programming proceeds.

5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths.

When writing of additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when

the write pulse is applied.

Original Data (D)

Verify Data (V)

Reprogram Data (X)

Comments

Programming complete

Programming is incomplete: reprogramming should be performed

Left in the erased state

Write pulse application subroutine

Programming must be executed in the erased state.

Do not perform additional programming on addresses

that have already been programmed.

RAM

Program data storage

area (128 bytes)

Reprogram data storage

area (128 bytes)

Additional-programming

data storage area (128 bytes)

Store 128 bytes of program data in program

data area and reprogram data area

Successively write 128-byte reprogram

data to flash memory

Enable WDT

Disable WDT

Set PSU1 bit in FLMCR1

Set P1 bit in FLMCR1

Clear PSU1 bit in FLMCR1

Wait (y) µstspsu:

tspv:

tspur:

tcpv:

tcswe:

Wait (α) µs

Wait (β) µs

tcp:

tsp10 or tsp30 or tsp200:

Wait (z0) µs or (z1) µs or (z2) µs

Sub-Routine-Call

Additional programming subroutine

Successively write 128-byte data from additional-

programming data area in RAM to flash memory

H'FF dummy write to verify address

tcswe:

Sub-Routine Write Pulse

End Sub

Clear P1 bit in FLMCR1

Start of programming

Write pulse application subroutine

Number of Writes

N1–1

N1+1

N1+2

N1+3

N1+N2–2

N1+N2–1

N1+N2

Programming

—

Additional

Programming

Note 6: Programming Time

Reprogram Data Computation Table

Reprogram Data (X')

Verify Data (V)

Additional-Programming Data (X)

Comments

Additional programming should be performed

Additional programming should not be performed

Additional-Programming Data Computation Table

P1 Bit Set Time (µs)

Figure 19-11 Program/Program-Verify Flowchart

645

19.7.3 Erase Mode

When erasing flash memory, the single-block erase/erase-verify flowchart shown in figure 19-12

should be followed.

To erase flash memory contents, make a 1-bit setting for the flash memory area to be erased in

erase block register 1 and 2 (EBR1, EBR2) at least (x) µs after setting the SWE1 bit to 1 in

FLMCR1. Next, the watchdog timer (WDT) is set to prevent overerasing due to program

runaway, etc. Set 6.6 ms as the WDT overflow period. Preparation for entering erase mode (erase

setup) is performed next by setting the ESU1 bit in FLMCR1. The operating mode is then

switched to erase mode by setting the E1 bit in FLMCR1 after the elapse of at least (y) µs. The

time during which the E1 bit is set is the flash memory erase time. Ensure that the erase time does

not exceed (z) ms.

Note: With flash memory erasing, preprogramming (setting all memory data in the memory to

be erased to all 0) is not necessary before starting the erase procedure.

19.7.4 Erase-Verify Mode

In erase-verify mode, data is read after memory has been erased to check whether it has been

correctly erased.

After the elapse of the fixed erase time, clear the E1 bit in FLMCR1, then wait for at least (α) µs

before clearing the ESU1 bit to exit erase mode. After exiting erase mode, the watchdog timer is

cleared after the elapse of (β) µs or more. The operating mode is then switched to erase-verify

mode by setting the EV1 bit in FLMCR1. Before reading in erase-verify mode, a dummy write of

H'FF data should be made to the addresses to be read. The dummy write should be executed after

the elapse of (γ) µs or more. When the flash memory is read in this state (verify data is read in 16-

bit units), the data at the latched address is read. Wait at least (ε) µs after the dummy write before

performing this read operation. If the read data has been erased (all 1), a dummy write is

performed to the next address, and erase-verify is performed. If the read data is unerased, set erase

mode again and repeat the erase/erase-verify sequence in the same way. The maximum number of

reoperations of the erase/erase-verify sequence is indicated by the maximum erase count (N).

However, ensure that the erase/erase-verify sequence is not repeated more than (N) times. When

verification is completed, exit erase-verify mode, and wait for at least (η) µs. If erasure has been

completed on all the erase blocks, clear the SWE1 bit in FLMCR1. If there are any unerased

blocks, make a 1 bit setting for the flash memory area to be erased, and repeat the erase/erase-

verify sequence as before.

646

End of erasing

Start

Set SWE1 bit in FLMCR1

Set ESU1 bit in FLMCR1

Set E1 bit in FLMCR1

tsswe: Wait (x) µs

tsesu: Wait (y) µs

n = 1

Set EBR1 and 2

Enable WDT

tse: Wait (z) ms

tce: Wait (α) µs

tcesu: Wait (β) µs

tsev: Wait (γ) µs

Set block start address to verify address

tsevr: Wait (ε) µs

tcev: Wait (η) µs

Start erase

Clear E1 bit in FLMCR1

Clear ESU1 bit in FLMCR1

Set EV1 bit in FLMCR1

H'FF dummy write to verify address

Read verify data

Clear EV1 bit in FLMCR1

tcev: Wait (η) µs

Clear EV1 bit in FLMCR1

Clear SWE1 bit in FLMCR1

Disable WDT

Halt erase

Verify data = all "1"?

Last address of block?

End of

erasing of all erase

blocks?

Erase failure

Clear SWE1 bit in FLMCR1

n ≥ (N)?

NG NG

OK OK

n ← n + 1

Increment

address

tcswe: Wait (× 1) µs tcswe: Wait (× 1) µs

Notes: 1. Preprogramming (setting erase block data to all "0") is not necessary.

2. Verify data is read in 16-bit (W) units.

3. Set only one bit in EBR1 and 2. More than 2 bits cannot be set.

4. Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.

Figure 19-12 Erase/Erase-Verify Flowchart

647

19.8 Protection

There are three kinds of flash memory program/erase protection: hardware protection, software

protection, and error protection.

19.8.1 Hardware Protection

Hardware protection refers to a state in which programming/erasing of flash memory is forcibly

disabled or aborted. Hardware protection is reset by settings in flash memory control register 1

(FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase

block register 2 (EBR2). The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained in the

error-protected state. (See table 19-8.)

Table 19-8 Hardware Protection

Functions

Item Description Program Erase

FWE pin protection • When a low level is input to the FWE pin,

FLMCR1, FLMCR2, (except bit FLER)

EBR1, and EBR2 are initialized, and the

program/erase-protected state is entered.

Yes Yes

Reset/standby

protection • In a reset (including a WDT reset) and in

standby mode, FLMCR1, FLMCR2, EBR1,

and EBR2 are initialized, and the

program/erase-protected state is entered.

• In a reset via the RES pin, the reset state

is not entered unless the RES pin is held

low until oscillation stabilizes after

powering on. In the case of a reset during

operation, hold the RES pin low for the

RES pulse width specified in the AC

Characteristics section.

Yes Yes

648

19.8.2 Software Protection

Software protection can be implemented by setting the SWE1 bit in FLMCR1, erase block register

1 (EBR1), erase block register 2 (EBR2), and the RAMS bit in the RAM emulation register

(RAMER). When software protection is in effect, setting the P1 or E1 bit in flash memory control

9.)

Table 19-9 Software Protection

Functions

Item Description Program Erase

SWE bit protection • Setting bit SWE1 in FLMCR1 to 0 will

place area H'000000 to H'03FFFFF in the

program/erase-protected state. (Execute

the program in the on-chip RAM, external

memory)

Yes Yes

Block specification

protection • Erase protection can be set for individual

blocks by settings in erase block register 1

(EBR1) and erase block register 2 (EBR2).

• Setting EBR1 and EBR2 to H'00 places all

blocks in the erase-protected state.

— Yes

Emulation protection • Setting the RAMS bit to 1 in the RAM

emulation register (RAMER) places all

blocks in the program/erase-protected

state.

Yes Yes

649

19.8.3 Error Protection

In error protection, an error is detected when H8S/2626 or H8S/2623 runaway occurs during flash

memory programming/erasing, or operation is not performed in accordance with the

program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase

operation prevents damage to the flash memory due to overprogramming or overerasing.

If the H8S/2626 or H8S/2623 malfunctions during flash memory programming/erasing, the FLER

bit is set to 1 in FLMCR2 and the error protection state is entered. The FLMCR1, FLMCR2,

EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at

which the error occurred. Program mode or erase mode cannot be re-entered by re-setting the P1

or E1 bit. However, PV1 and EV1 bit setting is enabled, and a transition can be made to verify

mode.

FLER bit setting conditions are as follows:

1. When the flash memory of the relevant address area is read during programming/erasing

(including vector read and instruction fetch)

2. When a SLEEP instruction (including software standby) is executed during

programming/erasing

Error protection is released only by a reset and in hardware standby mode.

650

Figure 19-13 shows the flash memory state transition diagram.

RD VF PR ER FLER = 0

Error

occurrence

RES = 0 or HSTBY = 0

RES = 0 or

HSTBY = 0

RD VF PR ER FLER = 0

Program mode

Erase mode Reset or standby

(hardware protection)

RD VF PR ER FLER = 1 RD VF PR ER FLER = 1

Error protection mode Error protection mode

(software standby)

Software

standby mode

FLMCR1, FLMCR2, EBR1, EBR2

initialization state

FLMCR1, FLMCR2,

EBR1, EBR2

initialization state

Software standby

mode release

RD: Memory read possible

VF: Verify-read possible

PR: Programming possible

ER: Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

Legend

RES = 0 or

HSTBY = 0

Error occurrence

(software standby)

Figure 19-13 Flash Memory State Transitions

651

19.9 Flash Memory Emulation in RAM

Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped

onto the flash memory area so that data to be written to flash memory can be emulated in RAM in

real time. After the RAMER setting has been made, accesses cannot be made from the flash

memory area or the RAM area overlapping flash memory. Emulation can be performed in user

mode and user program mode. Figure 19-14 shows an example of emulation of real-time flash

memory programming.

Start of emulation program

End of emulation program

Tuning OK?

Yes

Set RAMER

Write tuning data to overlap

RAM

Execute application program

Clear RAMER

Write to flash memory emulation

block

Figure 19-14 Flowchart for Flash Memory Emulation in RAM

652

H'00000

H'01000

H'02000

H'03000

H'04000

H'05000

H'06000

H'07000

H'08000

H'3FFFF

Flash memory

EB8 to EB11

EB0

EB1

EB2

EB3

EB4

EB5

EB6

EB7

H'FFD000

H'FFDFFF

H'FFEFBF

On-chip RAM

This area can be accessed

from both the RAM area

and flash memory area

Figure 19-15 Example of RAM Overlap Operation

Example in which Flash Memory Block Area EB0 is Overlapped

1. Set bits RAMS, RAM2 to RAM0 in RAMER to 1, 0, 0, 0, to overlap part of RAM onto the

area (EB0) for which real-time programming is required.

2. Real-time programming is performed using the overlapping RAM.

3. After the program data has been confirmed, the RAMS bit is cleared, releasing RAM overlap.

4. The data written in the overlapping RAM is written into the flash memory space (EB0).

Notes: 1. When the RAMS bit is set to 1, program/erase protection is enabled for all blocks

regardless of the value of RAM2 to RAM0 (emulation protection). In this state, setting

the P1 or E1 bit in flash memory control register 1 (FLMCR1), will not cause a

transition to program mode or erase mode. When actually programming or erasing a

flash memory area, the RAMS bit should be cleared to 0.

2. A RAM area cannot be erased by execution of software in accordance with the erase

algorithm while flash memory emulation in RAM is being used.

3. Block area EB0 contains the vector table. When performing RAM emulation, the

vector table is needed in the overlap RAM.

653

19.10 Interrupt Handling when Programming/Erasing Flash Memory

All interrupts, including NMI interrupt is disabled when flash memory is being programmed or

erased (when the P1 or E1 bit is set in FLMCR1), and while the boot program is executing in boot

mode*1, to give priority to the program or erase operation. There are three reasons for this:

1. Interrupt during programming or erasing might cause a violation of the programming or

erasing algorithm, with the result that normal operation could not be assured.

2. In the interrupt exception handling sequence during programming or erasing, the vector would

not be read correctly*2, possibly resulting in MCU runaway.

3. If interrupt occurred during boot program execution, it would not be possible to execute the

normal boot mode sequence.

For these reasons, in on-board programming mode alone there are conditions for disabling

interrupt, as an exception to the general rule. However, this provision does not guarantee normal

erasing and programming or MCU operation. All requests, including NMI interrupt, must

therefore be restricted inside and outside the MCU when programming or erasing flash memory.

NMI interrupt is also disabled in the error-protection state while the P1 or E1 bit remains set in

FLMCR1.

Notes: 1. Interrupt requests must be disabled inside and outside the MCU until the programming

control program has completed programming.

2. The vector may not be read correctly in this case for the following two reasons:

• If flash memory is read while being programmed or erased (while the P1 or E1 bit

is set in FLMCR1), correct read data will not be obtained (undetermined values will

be returned).

• If the interrupt entry in the vector table has not been programmed yet, interrupt

exception handling will not be executed correctly.

19.11 Flash Memory Programmer Mode

Programs and data can be written and erased in programmer mode as well as in the on-board

programming modes. In programmer mode, flash memory read mode, auto-program mode, auto-

erase mode, and status read mode are supported. In auto-program mode, auto-erase mode, and

status read mode, a status polling procedure is used, and in status read mode, detailed internal

signals are output after execution of an auto-program or auto-erase operation.

In programmer mode, set the mode pins to programmer mode (see table 19-10) and input a 12

MHz input clock.

Table 19-10 shows the pin settings for programmer mode.

654

Table 19-10 Programmer Mode Pin Settings

Pin Names Settings

Mode pins: MD2, MD1, MD0 Low level input to MD2, MD1, and MD0.

Mode setting pins: PF0, P16, P14 High level input to PF0, low level input to P16 and P14

FWE pin High level input (in auto-program and auto-erase

modes)

RES pin Reset circuit

XTAL, EXTAL, PLLVCC, PLLCAP,

PLLVSS pins Oscillator circuit

19.11.1 Socket Adapter Pin Correspondence Diagram

Connect the socket adapter to the chip as shown in figure 19-17. This will enable conversion to a

40-pin arrangement. The on-chip ROM memory map is shown in figure 19-16, and the socket

adapter pin correspondence diagram in figure 19-17.

H'000000

Addresses in

MCU mode Addresses in

programmer mode

H'03FFFF

H'00000

H'3FFFF

On-chip ROM space

256 kbytes

Figure 19-16 On-Chip ROM Memory Map

655

Socket Adapter

(Conversion to 40-Pin

Arrangement)

H8S/2626 or H8S/2623

Pin No. Pin Name

A10

A11

A12

A13

A14

A15

A16

A17

D10

D11

D12

D13

D14

D15

FWE

HN27C4096HG (40 Pins)

Pin No. Pin Name

1, 40

11, 30

5, 6, 7

A10

A11

A12

A13

A14

A15

A16

A17

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

FWE

VCC

VSS

A20

A19

A18

Other than the above

RES

XTAL

EXTAL

PLL VCC

PLLCAP

PLL VSS

NC (OPEN)

VCC

VSS

Power-on

reset circuit

6, 9, 13, 17, 39, 52, 61, 62,

63, 75, 76, 77, 97

2, 4, 8, 14, 15, 37, 48, 49,

53, 54, 55, 56, 65, 94, 95, 98

Oscillator circuit

PLL circuit

Legend

FWE: Flash write enable

I/O7–I/O0: Data input/output

A18–A0: Address input

CE: Chip enable

OE: Output enable

WE: Write enable

Figure 19-17 Socket Adapter Pin Correspondence Diagram

656

19.11.2 Programmer Mode Operation

Table 19-11 shows how the different operating modes are set when using programmer mode, and

table 19-12 lists the commands used in programmer mode. Details of each mode are given below.

• Memory Read Mode

Memory read mode supports byte reads.

• Auto-Program Mode

Auto-program mode supports programming of 128 bytes at a time. Status polling is used to

confirm the end of auto-programming.

• Auto-Erase Mode

Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used

to confirm the end of auto-programming.

• Status Read Mode

Status polling is used for auto-programming and auto-erasing, and normal termination can be

confirmed by reading the I/O6 signal. In status read mode, error information is output if an

error occurs.

Table 19-11 Settings for Various Operating Modes In Programmer Mode

Pin Names

Mode FWE CE OE WE I/O7– I/O0 A18–A0

Read H or L L L H Data output Ain

Output disable H or L L H H Hi-z X

Command write H or L L H L Data input *Ain

Chip disable H or L H X X Hi-z X

Notes: 1. Chip disable is not a standby state; internally, it is an operation state.

2. *Ain indicates that there is also address input in auto-program mode.

3. For command writes in auto-program and auto-erase modes, input a high level to the

FWE pin.

657

Table 19-12 Programmer Mode Commands

Number 1st Cycle 2nd Cycle

Command Name of Cycles Mode Address Data Mode Address Data

Memory read mode 1 + n Write X H'00 Read RA Dout

Auto-program mode 129 Write X H'40 Write WA Din

Auto-erase mode 2 Write X H'20 Write X H'20

Status read mode 2 Write X H'71 Write X H'71

Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous

128-byte write.

2. In memory read mode, the number of cycles depends on the number of address write

cycles (n).

19.11.3 Memory Read Mode

1. After completion of auto-program/auto-erase/status read operations, a transition is made to the

command wait state. When reading memory contents, a transition to memory read mode must

first be made with a command write, after which the memory contents are read.

2. In memory read mode, command writes can be performed in the same way as in the command

wait state.

3. Once memory read mode has been entered, consecutive reads can be performed.

4. After powering on, memory read mode is entered.

Table 19-13 AC Characteristics in Transition to Memory Read Mode

(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 — µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 — ns

Data setup time tds 50 — ns

Write pulse width twep 70 — ns

WE rise time tr—30ns

WE fall time tf—30ns

658

A18–A0

I/O7–I/O0

Note: Data is latched on the rising edge of WE.

tceh

twep

tftr

tces tnxtc

Address stable

tds tdh

Command write Memory read mode

Figure 19-18 Timing Waveforms for Memory Read after Memory Write

Table 19-14 AC Characteristics in Transition from Memory Read Mode to Another Mode

(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 — µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 — ns

Data setup time tds 50 — ns

Write pulse width twep 70 — ns

WE rise time tr—30ns

WE fall time tf—30ns

659

A18–A0

I/O7–I/O0

Note: Do not enable WE and OE at the same time.

tceh

twep

tftr

tces

tnxtc

Address stable

tds tdh

Other mode command writeMemory read mode

Figure 19-19 Timing Waveforms in Transition from Memory Read Mode to Another Mode

Table 19-15 AC Characteristics in Memory Read Mode (Conditions: VCC = 3.3 V ±0.3 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Access time tacc —20µs

CE output delay time tce — 150 ns

OE output delay time toe — 150 ns

Output disable delay time tdf — 100 ns

Data output hold time toh 5—ns

A18–A0

I/O7–I/O0

VIL

VIH tacc tacc

toh toh

Address stableAddress stable

Figure 19-20 CE and OE Enable State Read Timing Waveforms

660

A18–A0

I/O7–I/O0

VIH tacc

tce

toe toe

tce

tacc

toh tdf tdf

toh

Address stableAddress stable

Figure 19-21 CE and OE Clock System Read Timing Waveforms

19.11.4 Auto-Program Mode

1. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out

by executing 128 consecutive byte transfers.

2. A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this

case, H'FF data must be written to the extra addresses.

3. The lower 7 bits of the transfer address must be low. If a value other than an effective address

is input, processing will switch to a memory write operation but a write error will be flagged.

4. Memory address transfer is performed in the second cycle (figure 19-22). Do not perform

transfer after the third cycle.

5. Do not perform a command write during a programming operation.

6. Perform one auto-program operation for a 128-byte block for each address. Two or more

additional programming operations cannot be performed on a previously programmed address

block.

7. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode

can also be used for this purpose (I/O7 status polling uses the auto-program operation end

decision pin).

8. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long

as the next command write has not been performed, reading is possible by enabling CE and

OE.

661

Table 19-16 AC Characteristics in Auto-Program Mode (Conditions: VCC = 3.3 V ±0.3 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 — µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 — ns

Data setup time tds 50 — ns

Write pulse width twep 70 — ns

Status polling start time twsts 1—ms

Status polling access time tspa — 150 ns

Address setup time tas 0—ns

Address hold time tah 60 — ns

Memory write time twrite 1 3000 ms

Write setup time tpns 100 — ns

Write end setup time tpnh 100 — ns

WE rise time tr—30ns

WE fall time tf—30ns

A18–A0

FWE

I/O7

I/O6

I/O5–I/O0

tpns

twep

tds tdh

tftrtas tah twsts

twrite

tspa

tces tceh tnxtc tnxtc

tpnh

Address

stable

H'40 H'00

Data transfer

1 to 128 bytes

Write operation end decision signal

Write normal end decision signal

Figure 19-22 Auto-Program Mode Timing Waveforms

662

19.11.5 Auto-Erase Mode

1. Auto-erase mode supports only entire memory erasing.

2. Do not perform a command write during auto-erasing.

3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also

be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).

4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long

as the next command write has not been performed, reading is possible by enabling CE and

OE.

Table 19-17 AC Characteristics in Auto-Erase Mode (Conditions: VCC = 3.3 V ±0.3 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Command write cycle tnxtc 20 — µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 — ns

Data setup time tds 50 — ns

Write pulse width twep 70 — ns

Status polling start time tests 1—ms

Status polling access time tspa — 150 ns

Memory erase time terase 100 40000 ms

Erase setup time tens 100 — ns

Erase end setup time tenh 100 — ns

WE rise time tr—30ns

WE fall time tf—30ns

663

A18–A0

FWE

I/O7

I/O6

I/O5–I/O0

ens

wep

ests

erase

spa

ces

ceh

nxtc

pnh

H'20 H'20 H'00

,,,,

Erase end

decision signal

Erase normal

end

decision signal

Figure 19-23 Auto-Erase Mode Timing Waveforms

664

19.11.6 Status Read Mode

1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an

abnormal end occurs in auto-program mode or auto-erase mode.

2. The return code is retained until a command write other than a status read mode command

write is executed.

Table 19-18 AC Characteristics in Status Read Mode (Conditions: VCC = 3.3 V ±0.3 V,

VSS = 0 V, Ta = 25°C ±5°C)

Item Symbol Min Max Unit

Read time after command write tnxtc 20 — µs

CE hold time tceh 0—ns

CE setup time tces 0—ns

Data hold time tdh 50 — ns

Data setup time tds 50 — ns

Write pulse width twep 70 — ns

OE output delay time toe — 150 ns

Disable delay time tdf — 100 ns

CE output delay time tce — 150 ns

WE rise time tr—30ns

WE fall time tf—30ns

A18–A0

I/O7–I/O0

wep

ces

ceh

nxtc

ces

H'71



wep

H'71

Note: I/O2 and I/O3 are undefined.

Figure 19-24 Status Read Mode Timing Waveforms

665

Table 19-19 Status Read Mode Return Commands

Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Attribute Normal

end

decision

Command

error Program-

ming error Erase

error — — Program-

ming or

erase count

exceeded

Effective

address error

Initial value 00000000

Indications Normal

end: 0

Abnormal

end: 1

Command

error: 1

Otherwise: 0

Program-

ming

error: 1

Otherwise: 0

Erasing

error: 1

Otherwise: 0

— — Count

exceeded: 1

Otherwise: 0

Effective

address

error: 1

Otherwise: 0

Note: I/O2 and I/O3 are undefined.

19.11.7 Status Polling

1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.

2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase

mode.

Table 19-20 Status Polling Output Truth Table

Pin Name During Internal

Operation Abnormal End — Normal End

I/O7 0101

I/O6 0011

I/O0–I/O5 0000

19.11.8 Programmer Mode Transition Time

Commands cannot be accepted during the oscillation stabilization period or the programmer mode

setup period. After the programmer mode setup time, a transition is made to memory read mode.

Table 19-21 Stipulated Transition Times to Command Wait State

Item Symbol Min Max Unit

Standby release (oscillation

stabilization time) tosc1 30 — ms

Programmer mode setup time tbmv 10 — ms

VCC hold time tdwn 0—ms

666

tosc1 tbmv tdwn

VCC

RES

FWE

Memory read

mode

Command

wait state Auto-program mode

Auto-erase mode

Command wait state

Normal/abnormal

end decision

Note: When using other than the automatic write mode and automatic erase mode, drive the FWE

input pin low.

Figure 19-25 Oscillation Stabilization Time, Boot Program Transfer Time, and

Power-Down Sequence

19.11.9 Notes on Memory Programming

1. When programming addresses which have previously been programmed, carry out auto-

erasing before auto-programming.

2. When performing programming using programmer mode on a chip that has been

programmed/erased in an on-board programming mode, auto-erasing is recommended before

carrying out auto-programming.

Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi.

For other chips for which the erasure history is unknown, it is recommended that auto-

erasing be executed to check and supplement the initialization (erase) level.

2. Auto-programming should be performed once only on the same address block.

Additional programming cannot be performed on previously programmed address

blocks.

667

19.12 Flash Memory and Power-Down States

In addition to its normal operating state, the flash memory has power-down states in which power

consumption is reduced by halting part or all of the internal power supply circuitry.

There are three flash memory operating states:

(1) Normal operating mode: The flash memory can be read and written to.

(2) Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be

read when the LSI is operating on the subclock.

(3) Standby mode: All flash memory circuits are halted, and the flash memory cannot be read or

written to.

States (2) and (3) are flash memory power-down states. Table 19-22 shows the correspondence

between the operating states of the LSI and the flash memory.

Table 19-22 Flash Memory Operating States

LSI Operating State Flash Memory Operating State

High-speed mode

Medium-speed mode

Sleep mode

Normal mode (read/write)

Subactive mode

Subsleep mode When PDWND = 0: Power-down mode (read-only)

When PDWND = 1: Normal mode (read-only)

Watch mode

Software standby mode

Hardware standby mode

Standby mode

19.12.1 Note on Power-Down States

When the flash memory is in a power-down state, part or all of the internal power supply circuitry

is halted. Therefore, a power supply circuit stabilization period must be provided when returning

to normal operation. When the flash memory returns to its normal operating state from a power-

down state, bits STS2 to STS0 in SBYCR must be set to provide a wait time of at least 20 µs

(power supply stabilization time), even if an oscillation stabilization period is not necessary.

668

19.13 Flash Memory Programming and Erasing Precautions

Precautions concerning the use of on-board programming mode, the RAM emulation function, and

programmer mode are summarized below.

1. Use the specified voltages and timing for programming and erasing.

Applied voltages in excess of the rating can permanently damage the device. Use a PROM

programmer that supports the Hitachi microcomputer device type with 256-kbyte on-chip flash

memory (FZTAT256V3A).

Do not select the HN27C4096 setting for the PROM programmer, and only use the specified

socket adapter. Failure to observe these points may result in damage to the device.

2. Powering on and off (see figures 19-26 to 19-28)

Do not apply a high level to the FWE pin until VCC has stabilized. Also, drive the FWE pin low

before turning off VCC.

When applying or disconnecting VCC power, fix the FWE pin low and place the flash memory

in the hardware protection state.

The power-on and power-off timing requirements should also be satisfied in the event of a

power failure and subsequent recovery.

3. FWE application/disconnection (see figures 19-26 to 19-28)

FWE application should be carried out when MCU operation is in a stable condition. If MCU

operation is not stable, fix the FWE pin low and set the protection state.

The following points must be observed concerning FWE application and disconnection to

prevent unintentional programming or erasing of flash memory:

• Apply FWE when the VCC voltage has stabilized within its rated voltage range.

Apply FWE when oscillation has stabilized (after the elapse of the oscillation settling

time).

• In boot mode, apply and disconnect FWE during a reset.

• In user program mode, FWE can be switched between high and low level regardless of

RES input.

FWE input can also be switched during execution of a program in flash memory.

• Do not apply FWE if program runaway has occurred.

• Disconnect FWE only when the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits in

FLMCR1 are cleared.

Make sure that the SWE1, ESU1, PSU1, EV1, PV1, P1, and E1 bits are not set by mistake

when applying or disconnecting FWE.

669

4. Do not apply a constant high level to the FWE pin.

Apply a high level to the FWE pin only when programming or erasing flash memory. A system

configuration in which a high level is constantly applied to the FWE pin should be avoided.

Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to

prevent overprogramming or overerasing due to program runaway, etc.

5. Use the recommended algorithm when programming and erasing flash memory.

The recommended algorithm enables programming and erasing to be carried out without

subjecting the device to voltage stress or sacrificing program data reliability. When setting the

P1 or E1 bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against

program runaway, etc.

6. Do not set or clear the SWE1 bit during execution of a program in flash memory.

Do not set or clear the SWE1 bit during execution of a program in flash memory. Wait for at

least 100 µs after clearing the SWE1 bit before executing a program or reading data in flash

memory. When the SWE1 bit is set, data in flash memory can be rewritten, but when SWE1 =

1, flash memory can only be read in program-verify or erase-verify mode. Access flash

memory only for verify operations (verification during programming/erasing). Do not clear the

SWE1 bit during programming, erasing, or verifying.

Similarly, when using the RAM emulation function while a high level is being input to the

FWE pin, the SWE1 bit must be cleared before executing a program or reading data in flash

memory. However, the RAM area overlapping flash memory space can be read and written to

regardless of whether the SWE1 bit is set or cleared.

7. Do not use interrupts while flash memory is being programmed or erased.

All interrupt requests, including NMI, should be disabled during FWE application to give

priority to program/erase operations.

8. Do not perform additional programming. Erase the memory before reprogramming.

In on-board programming, perform only one programming operation on a 128-byte

programming unit block. In programmer mode, also, perform only one programming operation

on a 128-byte programming unit block.

9. Before programming, check that the chip is correctly mounted in the PROM

programmer.

Overcurrent damage to the device can result if the index marks on the PROM programmer

socket, socket adapter, and chip are not correctly aligned.

10.Do not touch the socket adapter or chip during programming.

Touching either of these can cause contact faults and write errors.

670

Period during which flash memory access is prohibited

(x: Wait time after setting SWE1 bit)*2

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations

prohibited)

VCC

FWE

tOSC1 Min 0 µs

tMDS*3

MD2 to MD0*1

RES

SWE1 bit

SWE1 set SWE1 cleared

Program-

ming/

erasing

possible

Wait time:

xWait time:

100 µs

Min 0 µs

Notes: 1. Except when switching modes, the level of the mode pins (MD2–MD0) must be fixed until power-

off by pulling the pins up or down.

2. See 22.5, Flash Memory Characteristics.

3. Mode programming setup time tMDS (min) = 200 ns

Figure 19-26 Power-On/Off Timing (Boot Mode)

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Period during which flash memory access is prohibited

(x: Wait time after setting SWE1 bit)*2

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations

prohibited)

VCC

FWE

tOSC1 Min 0 µs

MD2 to MD0*1

RES

SWE1 bit

SWE1 set SWE1 cleared

Program-

ming/

erasing

possible

Wait time:

xWait time:

100 µs

tMDS*3

Notes: 1. Except when switching modes, the level of the mode pins (MD2–MD0) must be fixed until power-

off by pulling the pins up or down.

2. See 22.5, Flash Memory Characteristics.

3. Mode programming setup time tMDS (min) = 200 ns

Figure 19-27 Power-On/Off Timing (User Program Mode)

672

Period during which flash memory access is prohibited

(x: Wait time after setting SWE1 bit)*3

Period during which flash memory can be programmed

(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)

VCC

FWE

tOSC1

Min 0µs

tMDS tMDS*1

tMDS

tRESW

MD2 to MD0

RES

SWE1 bit

Mode

change*1User

mode

Boot

mode User program mode

SWE1 set SWE1

cleared

Programming/

erasing possible

Wait time: x

Wait time: 100 µs

Programming/

erasing possible

Wait time: x

Wait time: 100 µs

Programming/

erasing possible

Wait time: x

Programming/

erasing possible

Wait time: x

Wait time: 100 µs

Mode

change*1User

mode User program

mode

Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried

out by means of RES input. The state of ports with multiplexed address functions and bus control output pins

(AS, RD, WR) will change during this switchover interval (the interval during which the RES pin input is low),

and therefore these pins should not be used as output signals during this time.

2. When making a transition from boot mode to another mode, a mode programming setup time, tMDS (min), of 200 ns

is necessary with respect to the RES clearance timing.

3. See 22.5, Flash Memory Characteristics.

Figure 19-28 Mode Transition Timing

(Example: Boot Mode → User Mode ↔ User Program Mode)

673

19.14 Note on Switching from F-ZTAT Version to Mask ROM Version

The mask ROM version does not have the internal registers for flash memory control that are

provided in the F-ZTAT version. Table 19-23 lists the registers that are present in the F-ZTAT

version but not in the mask ROM version. If a register listed in table 19-23 is read in the mask

ROM version, an undefined value will be returned. Therefore, if application software developed

on the F-ZTAT version is switched to a mask ROM version product, it must be modified to ensure

that the registers in table 19-23 have no effect.

Table 19-23 Registers Present in F-ZTAT Version but Absent in Mask ROM Version

Flash memory control register 1 FLMCR1 H'FFA8

Flash memory control register 2 FLMCR2 H'FFA9

Erase block register 1 EBR1 H'FFAA

Erase block register 2 EBR2 H'FFAB

RAM emulation register RAMER H'FEDB

Flash memory power control register FLPWCR H'FFAC

674

675

Section 20 Clock Pulse Generator

20.1 Overview

The H8S/2626 Series and H8S/2623 Series have an on-chip clock pulse generator (CPG) that

generates the system clock (ø), the bus master clock, and internal clocks.

The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock

selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock

oscillator*, and waveform shaping circuit*. The frequency can be changed by means of the PLL

circuit in the CPG. Frequency changes are performed by software by means of settings in the

system clock control register (SCKCR) and low-power control register (LPWRCR).

Note: * Supported only in the H8S/2626 Series; not available in the H8S/2623 Series.

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20.1.1 Block Diagram

Figure 20-1 shows a block diagram of the clock pulse generator.

Legend:

LPWRCR:

SCKCR:

Low-power control register

System clock control register

EXTAL

XTAL

PLL circuit

(×1, ×2, ×4) Medium-

speed

clock divider

System

clock

oscillator Clock

selection

circuit

ø SUB

WDT1 count clock

System clock

to ø pin Internal clock to

supporting modules Bus master clock

to CPU and DTC

ø/2 to

ø/32

SCK2 to SCK0

SCKCR

STC1, STC0

OSC1

OSC2

Waveform

shaping

circuit

Subclock

oscillator

LPWRCR

Bus

master

clock

selection

circuit

Figure 20-1 Block Diagram of Clock Pulse Generator

20.1.2 Register Configuration

The clock pulse generator is controlled by SCKCR and LPWRCR. Table 20-1 shows the register

configuration.

Table 20-1 Clock Pulse Generator Register

Name Abbreviation R/W Initial Value Address*

System clock control register SCKCR R/W H'00 H'FDE6

Low-power control register LPWRCR R/W H'00 H'FDEC

Note:*Lower 16 bits of the address.

677

20.2 Register Descriptions

20.2.1 System Clock Control Register (SCKCR)

PSTOP

R/W

—

STCS

R/W

SCK0

R/W

SCK2

R/W

SCK1

R/W

Bit

Initial value

R/W

SCKCR is an 8-bit readable/writable register that performs ø clock output control, selection of

operation when the PLL circuit frequency multiplication factor is changed, and medium-speed

mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.

Description

Bit 7 High-speed Mode, Software Hardware

PSTOP Medium-Speed Mode Sleep Mode Standby Mode Standby Mode

0 ø output (initial value) ø output Fixed high High impedance

1 Fixed high Fixed high Fixed high High impedance

Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.

Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation

when the PLL circuit frequency multiplication factor is changed.

Bit 3

STCS Description

0 Specified multiplication factor is valid after transition to software standby mode

(Initial value)

1 Specified multiplication factor is valid immediately after STC bits are rewritten

678

Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master

clock.

Bit 2 Bit 1 Bit 0

SCK2 SCK1 SCK0 Description

0 0 0 Bus master is in high-speed mode (Initial value)

1 Medium-speed clock is ø/2

1 0 Medium-speed clock is ø/4

1 Medium-speed clock is ø/8

1 0 0 Medium-speed clock is ø/16

1 Medium-speed clock is ø/32

1——

20.2.2 Low-Power Control Register (LPWRCR)

DTON

R/W

LSON

R/W

NESEL

R/W

SUBSTP

R/W

RFCUT

R/W

STC0

R/W

—

R/W

STC1

R/W

Bit

Initial value

Read/Write

LPWRCR is an 8-bit readable/writable register that performs power-down mode control.

LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized by a

manual reset or in software standby mode.

Bits 7 to 2—Reserved: The function of these bits differs between the H8S/2623 Series and

H8S/2626 Series.

For details see section 21A.2.3 or 21B.2.3, Low-Power Control Register (LPWRCR).

Bits 1 and 0—Frequency Multiplication Factor (STC1, STC0): The STC bits specify the

frequency multiplication factor of the PLL circuit.

Bit 1 Bit 0

STC1 STC0 Description

00×1 (Initial value)

1×2

10×4

1 Setting prohibited

679

Note: A system clock frequency multiplied by the multiplication factor (STC1 and STC0) should

not exceed the maximum operating frequency defined in section 21, Electrical

Characteristics.

20.3 Oscillator

Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.

In either case, the input clock should not exceed 20 MHz.

20.3.1 Connecting a Crystal Resonator

Circuit Configuration: A crystal resonator can be connected as shown in the example in figure

20-2. Select the damping resistance Rd according to table 20-2. An AT-cut parallel-resonance

crystal should be used.

EXTAL

XTAL RdCL2

CL1

CL1 = CL2 = 10 to 22pF

Figure 20-2 Connection of Crystal Resonator (Example)

Table 20-2 Damping Resistance Value

Frequency (MHz) 248121620

Rd (Ω) 1 k 500 200 0 0 0

Crystal Resonator: Figure 20-3 shows the equivalent circuit of the crystal resonator. Use a

crystal resonator that has the characteristics shown in table 20-3. The crystal resonator frequency

should not exceed 20 MHz.

XTAL

AT-cut parallel-resonance type

EXTAL

Figure 20-3 Crystal Resonator Equivalent Circuit

680

Table 20-3 Crystal Resonator Parameters

Frequency (MHz) 248121620

RS max (Ω) 500 120 80 60 50 40

C0 max (pF) 777777

Note on Board Design: When a crystal resonator is connected, the following points should be

noted:

Other signal lines should be routed away from the oscillator circuit to prevent induction from

interfering with correct oscillation. See figure 20-4.

When designing the board, place the crystal resonator and its load capacitors as close as possible

to the XTAL and EXTAL pins.

CL2

Signal A Signal B

CL1

H8S/2626 Series or

H8S/2623 Series

XTAL

EXTAL

Avoid

Figure 20-4 Example of Incorrect Board Design

681

External circuitry such as that shown below is recommended around the PLL.

PLLCAP

PLLVCC

PLLVSS

VCC

VSS

R1: 3 kΩC1: 470 pF

Rp: 200 Ω

CPB: 0.1 µF*

CB: 0.1 µF*

Note: * CB and CPB are laminated ceramic capacitors.

(Values are preliminary recommended values.)

Figure 20-5 Points for Attention when Using PLL Oscillation Circuit

Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure

that no other signal lines cross this line. Supply the C1 ground from PLLVSS.

Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply

source, and be sure to insert bypass capacitors CPB and CB close to the pins.

682

20.3.2 External Clock Input

Circuit Configuration: An external clock signal can be input as shown in the examples in figure

20-6. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF.

In example (b), make sure that the external clock is held high in standby mode.

EXTAL

XTAL

External clock input

Open

(a) XTAL pin left open

EXTAL

XTAL

External clock input

(

)

Com

lementar

clock in

ut at XTAL

Figure 20-6 External Clock Input (Examples)

683

External Clock: Use an external clock frequency of 20 MHz or less.

Table 20-4 and figure 20-7 show the input conditions for the external clock.

Table 20-4 External Clock Input Conditions

VCC = 3.0 V

to 3.6 V,

PVCC = 3.0 V

to 5.5 V

VCC = 3.0 V

to 3.6 V,

PVCC = 5.0 V

±10%

Item Symbol Min Max Min Max Unit Test Conditions

External clock input

low pulse width tEXL 40 — 15 — ns Figure 20-7

External clock input

high pulse width tEXH 40 — 15 — ns

External clock rise time tEXr —10 —5 ns

External clock fall time tEXf —10 —5 ns

Clock low pulse

width level tCL 0.4 0.6 0.4 0.6 tcyc ø ≥ 5 MHz Figure

22-2

80 — 80 — ns ø < 5 MHz

Clock high pulse

width level tCH 0.4 0.6 0.4 0.6 tcyc ø ≥ 5 MHz

80 — 80 — ns ø < 5 MHz

tEXH tEXL

tEXr tEXf

VCC × 0.5

EXTAL

Figure 20-7 External Clock Input Timing

684

20.4 PLL Circuit

The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a

factor of 1, 2, or 4. The multiplication factor is set with the STC bits in LPWRCR. The phase of

the rising edge of the internal clock is controlled so as to match that at the EXTAL pin.

When setting the multiplication factor, ensure that the clock frequency after multiplication does

not exceed the maximum operating frequency of the chip.

When the multiplication factor of the PLL circuit is changed, the operation varies according to the

setting of the STCS bit in SCKCR.

When STCS = 0 (initial value), the setting becomes valid after a transition to software standby

mode. The transition time count is performed in accordance with the setting of bits STS2 to STS0

in SBYCR.

[1] The initial PLL circuit multiplication factor is 1.

[2] A value is set in bits STS2 to STS0 to give the specified transition time.

[3] The target value is set in STC1 and STC0, and a transition is made to software standby mode.

[4] The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.

[5] Software standby mode is cleared, and a transition time is secured in accordance with the

setting in STS2 to STS0.

[6] After the set transition time has elapsed, the LSI resumes operation using the target

multiplication factor.

If a PC break is set for the SLEEP instruction that causes a transition to software standby mode in

[3], software standby mode is entered and break exception handling is executed after the

oscillation stabilization time. In this case, the instruction following the SLEEP instruction is

executed after execution of the RTE instruction.

When STCS = 1, the LSI operates on the changed multiplication factor immediately after bits

STC1 and STC0 are rewritten.

20.5 Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.

20.6 Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed

clocks (ø/2, ø/4, ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings of

the SCK2 to SCK0 bits in SCKCR.

685

20.7 Subclock Oscillator

(1) Connecting 32.768kHz Crystal Oscillator

To supply a clock to the subclock oscillator, connect a 32.768kHz crystal oscillator, as shown in

Figure 20-8. See Section 20.3.1, Note on Board Design for notes on connecting crystal oscillators.

OSC1

OSC2

C1 = C2 = 15 pF (typ)

Figure 20-8 Example Connection of 32.768 kHz Crystal Oscillator

Figure 20-9 shows the equivalence circuit for a 32.768kHz oscillator.

OSC1 OSC2

= 1.5 pF (typ.)

= 14 kΩ (typ.)

= 32.768 kHz

Type No.: MX38T (Nihon Dempa Kogyo)

Figure 20-9 Equivalence Circuit for 32.768 kHz Oscillator

686

(2) Handling pins when subclock not required

If no subclock is required, connect the OSC1 pin to Vcc and leave OSC2 open, as shown in Figure

20-10.

OSC1

OSC2

VCC

Open

Figure 20-10 Pin Handling When Subclock Not Required

20.8 Subclock Waveform Shaping Circuit

To eliminate noise from the subclock input to OSC1, the subclock is sampled using the dividing

clock ø. The sampling frequency is set using the NESEL bit of LPWRCR. For details, see Section

21.2.3, Low Power Control Register (LPWRCR).

No sampling is performed in sub-active mode, sub-sleep mode, or watch mode.

20.9 Note on Crystal Resonator

Since various characteristics related to the crystal resonator are closely linked to the user’s board

design, thorough evaluation is necessary on the user’s part, for both the mask versions and

F-ZTAT versions, using the resonator connection examples shown in this section as a guide. As

the resonator circuit ratings will depend on the floating capacitance of the resonator and the

mounting circuit, the ratings should be determined in consultation with the resonator

manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied

to the oscillator pin.

687

Section 21A Power-Down Modes

[H8S/2623 Series]

Subclock functions are not available in the H8S/2623 Series.

21A.1 Overview

In addition to the normal program execution state, the H8S/2623 Series has five power-down

modes in which operation of the CPU and oscillator is halted and power dissipation is reduced.

Low-power operation can be achieved by individually controlling the CPU, on-chip supporting

modules, and so on.

The H8S/2623 operating modes are as follows:

(1) High-speed mode

(2) Medium-speed mode

(3) Sleep mode

(4) Module stop mode

(5) Software standby mode

(6) Hardware standby mode

(2) to (6) are power-down modes. Sleep mode is CPU states, medium-speed mode is a CPU and

bus master state, and module stop mode is an internal peripheral function (including bus masters

other than the CPU) state. Some of these states can be combined.

After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop

mode.

Notes: 1. Subclock functions (subactive mode, subsleep mode, and watch mode) are not

available in the H8S/2623 Series, but are available in the H8S/2626 Series.

2. See section 20.7, Subclock Oscillator, for the method of fixing pins OSC1 and OSC2

when not used.

Table 21A-1 shows the internal state of the LSI in the respective modes.

Figure 21A-1 is a mode transition diagram.

688

Table 21A-1 LSI Internal States in Each Mode

Function High-

Speed Medium-

Speed Sleep Module Stop Software

Standby Hardware

Standby

System clock pulse

generator Functioning Functioning Functioning Functioning Halted Halted

CPU Instructions

Registers Functioning Medium-speed

operation Halted

(retained) High/medium-

speed

operation

Halted

(retained) Halted

(undefined)

External NMI Functioning Functioning Functioning Functioning Functioning Halted

interrupts IRQ0–IRQ5

Peripheral

functions WDT0 Functioning Functioning Functioning Halted

(retained) Halted (reset)

DTC Functioning Medium-speed

operation Functioning Halted

(retained) Halted

(retained) Halted (reset)

TPU Functioning Functioning Functioning Halted Halted Halted (reset)

PBC (retained) (retained)

PPG

SCI0 Functioning Functioning Functioning Halted (reset) Halted (reset) Halted (reset)

SCI1

SCI2

PWM

A/D

RAM Functioning Functioning Functioning

(DTC) Functioning Retained Retained

I/O Functioning Functioning Functioning Functioning Retained High impedance

HCAN Functioning Functioning*Functioning Halted (reset) Halted (reset) Halted (reset)

Notes: “Halted (retained)” means that internal register values are retained. The internal state is

“operation suspended.”

“Halted (reset)” means that internal register values and internal states are initialized.

In module stop mode, only modules for which a stop setting has been made are halted

(reset or retained).

* Note, however, that registers cannot be read or written to.

689

Program-halted state

Program execution state

SCK2 to

SCK0= 0 SCK2 to

SCK0≠ 0

SLEEP command

SLEEP

command

External

interrupt *

Any interrupt *

STBY pin = High

RES pin = Low

STBY pin = Low

SSBY = 0

SSBY = 1

RES pin = High

: Transition after exception processing : Low power dissipation mode

Reset state

High-speed mode

(main clock)

Medium-speed

mode

(main clock)

Hardware

standby mode

Software

standby mode

Sleep mode

(main clock)

Notes: 1.

2. All interrupts

NMI and IRQ0 to IRQ5

• When a transition is made between modes by means of an interrupt, the transition cannot be made

on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the

interrupt request.

• From any state except hardware standby mode, a transition to the reset state occurs when RES is

driven low.

• From any state, a transition to hardware standby mode occurs when STBY is driven low.

Figure 21A-1 Mode Transition Diagram

690

21A.1.1 Register Configuration

Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, and MSTPCR registers.

Table 21A-2 summarizes these registers.

Table 21A-2 Power-Down Mode Registers

Name Abbreviation R/W Initial Value Address*

Standby control register SBYCR R/W H'08 H'FDE4

System clock control register SCKCR R/W H'00 H'FDE6

Low power control register LPWRCR R/W H'00 H'FDEC

Module stop control register MSTPCRA R/W H'3F H'FDE8

A, B, C MSTPCRB R/W H'FF H'FDE9

MSTPCRC R/W H'FF H'FDEA

Note: * Lower 16 bits of the address.

21A.2 Register Descriptions

21A.2.1 Standby Control Register (SBYCR)

Bit:76543210

SSBY STS2 STS1 STS0 OPE — — —

Initial value : 0 0 0 0 1 0 0 0

R/W : R/W R/W R/W R/W R/W — — —

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by

executing the SLEEP instruction, the operating mode is determined in combination with other

control bits.

Note that the value of the SSBY bit does not change even when shifting between modes using

interrupts.

691

Bit 7

SSBY Description

0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed

mode or medium-speed mode. (Initial value)

1 Shifts to software standby mode when the SLEEP instruction is executed in high-

speed mode or medium-speed mode.

Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time

for clock stabilization when shifting to high-speed mode or medium-speed mode by using a

specific interrupt or command to cancel software standby mode. With a quartz oscillator (Table

21A-5), select a wait time of 8ms (oscillation stabilization time) or more, depending on the

operating frequency. With an external clock, there are no specific wait requirements.

Bit 6 Bit 5 Bit 4

STS2 STS1 STS0 Description

0 0 0 Standby time = 8192 states (Initial value)

1 Standby time = 16384 states

1 0 Standby time = 32768 states

1 Standby time = 65536 states

1 0 0 Standby time = 131072 states

1 Standby time = 262144 states

1 0 Reserved

1 Standby time = 16 states

Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and

bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the

software standby mode.

Bit 3

OPE Description

0 In software standby mode, address bus and bus control signals are high-impedance.

1 In software standby mode, the output state of the address bus and bus control signals

is retained. (Initial value)

Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.

692

21A.2.2 System Clock Control Register (SCKCR)

Bit:76543210

PSTOP — — — STCS SCK2 SCK1 SCK0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W — — — R/W R/W R/W R/W

SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—ø Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,

this bit controls ø output. See section 21A.8, ø Clock Output Disable Function for details.

Description

Bit 7 High-Speed Mode, Software Standby Hardware Standby

PSTOP Medium-Speed Mode Sleep Mode Mode Mode

0 ø output (initial value) ø output Fixed high High impedance

1 Fixed high Fixed high Fixed high High impedance

Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.

Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation

when the PLL circuit frequency multiplication factor is changed.

Bit 3

STCS Description

0 Specified multiplication factor is valid after transition to software standby mode

(Initial value)

1 Specified multiplication factor is valid immediately after STC bits are rewritten

693

Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in

high-speed mode, and medium-speed mode.

Bit 2 Bit 1 Bit 0

SCK2 SCK1 SCK0 Description

0 0 0 Bus master in high-speed mode (Initial value)

1 Medium-speed clock is ø/2

1 0 Medium-speed clock is ø/4

1 Medium-speed clock is ø/8

1 0 0 Medium-speed clock is ø/16

1 Medium-speed clock is ø/32

1——

21A.2.3 Low-Power Control Register (LPWRCR)

DTON

R/W

LSON

R/W

NESEL

R/W

SUBSTP

R/W

RFCUT

R/W

STC0

R/W

—

R/W

STC1

R/W

Bit

Initial value

R/W

The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.

The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not

initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,

see Section 20.2.2, Low-Power Control Register.

Bits 7 to 4—Reserved: Bits DTON, LSON, NESEL, and SUBSTP must always be written with 0

in the H8S/2623 Series, as this version does not support subclock operation.

Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the

internal feedback resistance of the main clock oscillation circuit ON/OFF.

Bit 3

RFCUT Description

0 When the main clock is oscillating, sets the feedback resistance ON. When the main

clock is stopped, sets the feedback resistance OFF. (Initial value)

1 Sets the feedback resistance OFF.

Bit 2—Reserved: Only write 0 to this bit.

694

21A.2.4 Module Stop Control Register (MSTPCR)

MSTPCRA

Bit:76543210

MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

Initial value : 0 0 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRB

Bit:76543210

MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRC

Bit:76543210

MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.

MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode.

They are not initialized in software standby mode.

MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0,

MSTPB7 to MSTPB0, MSTPC7 to MSTPC0, MSTPD7 and MSTPD6): These bits specify

module stop mode. See table 21A-4 for the method of selecting the on-chip peripheral functions.

MSTPCRA/MSTPCRB/

MSTPCRC Bits 7 to 0

MSTPA7 to MSTPA0,

MSTPB7 to MSTPB0,

MSTPC7 to MSTPC0 Description

0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)

1 Module stop mode is set (initial value of MSTPA5–0, MSTPB7–0,

MSTPC7–0)

695

21A.3 Medium-Speed Mode

In high-speed mode, when the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode

changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the

CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0

bits. The bus masters other than the CPU (DTC) also operate in medium-speed mode. On-chip

supporting modules other than the bus masters always operate on the high-speed clock (ø).

In medium-speed mode, a bus access is executed in the specified number of states with respect to

the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip

memory is accessed in 4 states, and internal I/O registers in 8 states.

Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to

high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.

If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is

made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.

When the SLEEP instruction is executed with the SSBY bit = 1, operation shifts to the software

standby mode. When software standby mode is cleared by an external interrupt, medium-speed

mode is restored.

When the RES pin is set low and medium-speed mode is cancelled, operation shifts to the reset

state. The same applies in the case of a reset caused by overflow of the watchdog timer.

When the STBY pin is driven low, a transition is made to hardware standby mode.

Figure 21A-2 shows the timing for transition to and clearance of medium-speed mode.

ø,

Bus master clock

supporting module clock

Internal address bus

Internal write signal

Medium-speed mode

SBYCRSBYCR

Figure 21A-2 Medium-Speed Mode Transition and Clearance Timing

696

21A.4 Sleep Mode

21A.4.1 Sleep Mode

When the SLEEP instruction is executed when the SBYCR SSBY bit = 0, the CPU enters the

sleep mode. In sleep mode, CPU operation stops but the contents of the CPUís internal registers

are retained. Other supporting modules do not stop.

21A.4.2 Exiting Sleep Mode

Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.

Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt

exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other

than NMI are masked by the CPU.

Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the

stipulated reset input duration, driving the RES pin High starts the CPU performing reset

exception processing.

Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made

to hardware standby mode.

21A.5 Module Stop Mode

21A.5.1 Module Stop Mode

Module stop mode can be set for individual on-chip supporting modules.

When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of

the bus cycle and a transition is made to module stop mode. The CPU continues operating

independently.

Table 21A-4 shows MSTP bits and the corresponding on-chip supporting modules.

When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module

starts operating at the end of the bus cycle. In module stop mode, the internal states of modules

other than the SCI, A/D converter and HCAN are retained.

After reset clearance, all modules other than DTC are in module stop mode.

When an on-chip supporting module is in module stop mode, read/write access to its registers is

disabled.

697

Table 21A-3 MSTP Bits and Corresponding On-Chip Supporting Modules

MSTPCRA MSTPA7*

MSTPA6 Data transfer controller (DTC)

MSTPA5 16-bit timer pulse unit (TPU)

MSTPA4*

MSTPA3 Programmable pulse generator (PPG)

MSTPA2*

MSTPA1 A/D converter

MSTPA0*

MSTPCRB MSTPB7 Serial communication interface 0 (SCI0)

MSTPB6 Serial communication interface 1 (SCI1)

MSTPB5 Serial communication interface 2 (SCI2)

MSTPB4*

MSTPB3*

MSTPB2*

MSTPB1*

MSTPB0*

MSTPCRC MSTPC7*

MSTPC6*

MSTPC5*

MSTPC4 PC break controller (PBC)

MSTPC3 HCAN

MSTPC2*

MSTPC1*

MSTPC0*

Note: *MSTPA7 is a readable/writable bit with an initial value of 0.

MSTPA4, MSTPA2, MSTPA0, MSTPB4 to MSTPB0, MSTPC7 to MSTPC5, and MSTPC2

to MSTPC0 are readable/writable bits with an initial value of 1 and should always be written

with 1.

698

21A.5.2 Usage Notes

DTC Module Stop: Depending on the operating status of the DTC, the MSTPA7 and MSTPA6

bits may not be set to 1. Setting of the DTC module stop mode should be carried out only when

the respective module is not activated.

For details, refer to section 8, Data Transfer Controller (DTC).

On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in

module stop mode. Consequently, if module stop mode is entered when an interrupt has been

requested, it will not be possible to clear the CPU interrupt source or the DTC activation source.

Interrupts should therefore be disabled before entering module stop mode.

Writing to MSTPCR: MSTPCR should only be written to by the CPU.

21A.6 Software Standby Mode

21A.6.1 Software Standby Mode

A transition is made to software standby mode when the SLEEP instruction is executed when the

SBYCR SSBY bit = 1. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.

However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip

supporting modules other than the SCI, A/D converter, HCAN and I/O ports, are retained.

Whether the address bus and bus control signals are placed in the high-impedance state or retain

the output state can be specified by the OPE bit in SBYCR.

In this mode the oscillator stops, and therefore power dissipation is significantly reduced.

21A.6.2 Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ5), or by

means of the RES pin or STBY pin.

• Clearing with an interrupt

When an NMI or IRQ0 to IRQ5 interrupt request signal is input, clock oscillation starts, and

after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to

the entire chip, software standby mode is cleared, and interrupt exception handling is started.

When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding

enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5

is generated. Software standby mode cannot be cleared if the interrupt has been masked on the

CPU side or has been designated as a DTC activation source.

699

• Clearing with the RES pin

When the RES pin is driven low, clock oscillation is started. At the same time as clock

oscillation starts, clocks are supplied to the entire chip. Note that the RES pin must be held

low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset

exception handling.

• Clearing with the STBY pin

When the STBY pin is driven low, a transition is made to hardware standby mode.

21A.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode

Bits STS2 to STS0 in SBYCR should be set as described below.

Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the

oscillation stabilization time).

Table 21A-4 shows the standby times for different operating frequencies and settings of bits STS2

to STS0.

Table 21A-4 Oscillation Stabilization Time Settings

STS2 STS1 STS0 Standby Time 20

MHz 16

MHz 12

MHz 10

MHz 8

MHz 6

MHz 4

MHz 2

MHz Unit

0 0 0 8192 states 0.41 0.51 0.68 0.8 1.0 1.3 2.0 4.1 ms

1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1 8.2

1 0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2 16.4

1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4 32.8

1 0 0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.8 65.5

1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2

10Reserved ————————µs

1 16 states*0.8 1.0 1.3 1.6 2.0 1.7 4.0 8.0

: Recommended time setting

Note: *Do not use this setting in the version with built-in flash memory.

700

21A.6.4 Software Standby Mode Application Example

Figure 21A-3 shows an example in which a transition is made to software standby mode at the

falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI

pin.

In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling

edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set

to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.

Software standby mode is then cleared at the rising edge on the NMI pin.

Oscillator

NMI

NMIEG

SSBY

NMI exception

handling

NMIEG=1

SSBY=1

SLEEP instruction

Software standby mode

(power-down mode) Oscillation

stabilization

time tOSC2

NMI exception

handling

Figure 21A-3 Software Standby Mode Application Example

701

21A.6.5 Usage Notes

I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1,

the address bus and bus control signal output is also retained. Therefore, there is no reduction in

current dissipation for the output current when a high-level signal is output.

Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation

increases during the oscillation stabilization wait period.

Write Data Buffer Function: The write data buffer function and software standby mode cannot

be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL

should be cleared to 0 to cancel the write data buffer function before entering software standby

mode. Also check that external writes have finished, by reading external addresses, etc., before

executing a SLEEP instruction to enter software standby mode. See section 7.7, Write Data Buffer

Function, for details of the write data buffer function.

21A.7 Hardware Standby Mode

21A.7.1 Hardware Standby Mode

When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.

In hardware standby mode, all functions enter the reset state and stop operation, resulting in a

significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip

RAM data is retained. I/O ports are set to the high-impedance state.

In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before

driving the STBY pin low.

Do not change the state of the mode pins (MD2 to MD0) while the H8S/2623 Series is in hardware

standby mode.

Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY

pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.

Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms—the

oscillation stabilization time—when using a crystal oscillator). When the RES pin is subsequently

driven high, a transition is made to the program execution state via the reset exception handling

state.

702

21A.7.2 Hardware Standby Mode Timing

Figure 21A-4 shows an example of hardware standby mode timing.

When the STBY pin is driven low after the RES pin has been driven low, a transition is made to

hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high,

waiting for the oscillation stabilization time, then changing the RES pin from low to high.

Oscillator

RES

STBY

Oscillation

stabilization

time

Reset

exception

handling

Figure 21A-4 Hardware Standby Mode Timing

21A.8 ø Clock Output Disabling Function

Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the

corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,

and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR

for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.

Table 21A-5 shows the state of the ø pin in each processing state.

Table 21A-5 ø Pin State in Each Processing State

DDR 0 1 1

PSTOP — 0 1

Hardware standby mode High impedance High impedance High impedance

Software standby High impedance Fixed high Fixed high

Sleep mode High impedance ø output Fixed high

High-speed mode, medium-speed

mode High impedance ø output Fixed high

703

Section 21B Power-Down Modes

[H8S/2626 Series]

21B.1 Overview

In addition to the normal program execution state, the H8S/2626 Series has nine power-down

modes in which operation of the CPU and oscillator is halted and power dissipation is reduced.

Low-power operation can be achieved by individually controlling the CPU, on-chip supporting

modules, and so on.

The H8S/2626 operating modes are as follows:

(1) High-speed mode

(2) Medium-speed mode

(3) Subactive mode*

(4) Sleep mode

(5) Subsleep mode*

(6) Watch mode*

(7) Module stop mode

(8) Software standby mode

(9) Hardware standby mode

(2) to (9) are power-down modes. Sleep mode and sub-sleep mode are CPU states, medium-speed

mode is a CPU and bus master state, sub-active mode is a CPU and bus master and internal

peripheral function state, and module stop mode is an internal peripheral function (including bus

masters other than the CPU) state. Some of these states can be combined.

After a reset, the LSI is in high-speed mode with modules other than the DTC in module stop

mode.

Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are not available in

the H8S/2623 Series, but are available in the H8S/2626 Series.

Table 21B-1 shows the internal state of the LSI in the respective modes. Table 21B-2 shows the

conditions for shifting between the low power dissipation modes.

Figure 21B-1 is a mode transition diagram.

704

Table 21B-1 LSI Internal States in Each Mode

Function High-

Speed Medium-

Speed Sleep Module

Stop Watch Sub-

active Subsleep Software

Standby Hardware

Standby

System clock pulse

generator Function-

ing Function-

ing Halted Halted Halted Halted Halted

Subclock pulse

generator Function-

ing Function-

ing Halted

CPU Instructions

Registers Function-

ing Medium-

speed

operation

Halted

(retained) High/

medium-

speed

operation

Halted

(retained) Subclock

operation Halted

(retained) Halted

(undefined)

External NMI Function- Function- Function- Function- Function- Function- Function- Function- Halted

interrupts IRQ0–IRQ5 ing ing ing ing ing ing ing ing

Peripheral

functions WDT1 Function-

ing Function-

ing Subclock

operation Subclock

operation Halted

(retained) Halted

(reset)

WDT0 Function- Function- Function Halted Subclock Subclock Halted Halted

ing ing ing (retained) operation operation (retained) (reset)

DTC Function- Medium- Function- Halted Halted Halted Halted Halted Halted

ing speed

operation ing (retained) (retained) (retained) (retained) (retained) (reset)

TPU Function- Function- Function- Halted Halted Halted Halted Halted Halted

PBC ing ing ing (retained) (retained) (retained) (retained) (retained) (reset)

PPG

D/A2, 3

SCI0 Function- Function- Function- Halted Halted Halted Halted Halted Halted

SCI1 ing ing ing (reset) (reset) (reset) (reset) (reset) (reset)

SCI2

PWM

A/D

RAM Function-

ing Function-

ing (DTC) Function-

ing Retained Function-

ing Retained Retained Retained

I/O Function-

ing Function-

ing Retained Function-

ing Retained Retained High

impedance

HCAN Function- Function- Function- Halted Halted Halted Halted Halted Halted

ing ing*ing (reset) (reset) (reset) (reset) (reset) (reset)

Note: “Halted (retained)” means that internal register values are retained. The internal state is

“operation suspended.”

“Halted (reset)” means that internal register values and internal states are initialized.

In module stop mode, only modules for which a stop setting has been made are halted

(reset or retained).

* Note, however, that registers cannot be read or written to.

705

Program-halted state

Program execution state

SCK2 to

SCK0= 0 SCK2 to

SCK0≠ 0

SLEEP command

SSBY = 1, PSS = 1

DTON = 1, LSON = 1

Clock switching

exception processing

SLEEP command

SSBY = 1, PSS = 1

DTON = 1, LSON = 0

After the oscillation

stabilization time

(STS2 to 0), clock

switching exception

processing

SLEEP command

SLEEP

command

External

interrupt *4

Any interrupt *3

SLEEP

command

SLEEP

command

SLEEP command

Interrupt *2

LSON bit = 0

Interrupt *2

Interrupt *1

LSON bit = 1

STBY pin = High

RES pin = Low

STBY pin = Low

SSBY= 0, LSON= 0

SSBY= 1,

PSS= 0, LSON= 0

SSBY= 0,

PSS= 1, LSON= 1

SSBY= 1,

PSS= 1, DTON= 0

RES pin = High

: Transition after exception processing : Low power dissipation mode

Reset state

High-speed mode

(main clock)

Medium-speed

mode

(main clock)

Sub-active mode

(subclock) Sub-sleep mode

(subclock)

Hardware

standby mode

Software

standby mode

Sleep mode

(main clock)

Watch mode

(subclock)

Notes: 1.

NMI, IRQ0 to IRQ5, and WDT1 interrupts

NMI, IRQ0 to IRQ5, IWDT0 interrupts, and WDT1 interrupt.

All interrupts

NMI and IRQ0 to IRQ5

• When a transition is made between modes by means of an interrupt, the transition cannot be made

on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the

interrupt request.

• From any state except hardware standby mode, a transition to the reset state occurs when RES is

driven Low.

• From any state, a transition to hardware standby mode occurs when STBY is driven low.

• Always select high-speed mode before making a transition to watch mode or sub-active mode.

Figure 21B-1 Mode Transition Diagram

706

Table 21B-2 Low Power Dissipation Mode Transition Conditions

Pre-Transition

Status of Control Bit at

Transition State After Transition

Invoked by SLEEP

State After Transition

Back from Low Power

Mode Invoked by

State SSBY PSS LSON DTON Command Interrupt

High-speed/ 0 *0*Sleep High-speed/Medium-speed

Medium-speed 0*1*——

100*Software standby High-speed/Medium-speed

101*——

1100Watch High-speed

1110Watch Sub-active

1101— —

1111Sub-active —

Sub-active 0 0 **——

010*——

011*Sub-sleep Sub-active

10**——

1100Watch High-speed

1110Watch Sub-active

1101High-speed —

1111— —

* : Don’t care

—: Do not set.

707

21B.1.1 Register Configuration

Power-down modes are controlled by the SBYCR, SCKCR, LPWRCR, TCSR (WDT1), and

MSTPCR registers. Table 21B-3 summarizes these registers.

Table 21B-3 Power-Down Mode Registers

Name Abbreviation R/W Initial Value Address*

Standby control register SBYCR R/W H'08 H'FDE4

System clock control register SCKCR R/W H'00 H'FDE6

Low-power control register LPWRCR R/W H'00 H'FDEC

Timer control/status register TCSR R/W H'00 H'FFA2

Module stop control register MSTPCRA R/W H'3F H'FDE8

A, B, C MSTPCRB R/W H'FF H'FDE9

MSTPCRC R/W H'FF H'FDEA

Note: * Lower 16 bits of the address.

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21B.2 Register Descriptions

21B.2.1 Standby Control Register (SBYCR)

Bit:76543210

SSBY STS2 STS1 STS0 OPE — — —

Initial value : 0 0 0 0 1 0 0 0

R/W : R/W R/W R/W R/W R/W — — —

SBYCR is an 8-bit readable/writable register that performs power-down mode control.

SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—Software Standby (SSBY): When making a low power dissipation mode transition by

executing the SLEEP instruction, the operating mode is determined in combination with other

control bits.

Note that the value of the SSBY bit does not change even when shifting between modes using

interrupts.

Bit 7

SSBY Description

0 Shifts to sleep mode when the SLEEP instruction is executed in high-speed

mode or medium-speed mode.

Shifts to sub-sleep mode when the SLEEP instruction is executed in

sub-active mode. (Initial value)

1 Shifts to software standby mode, sub-active mode, and watch mode when the SLEEP

instruction is executed in high-speed mode or medium-speed mode.

Shifts to watch mode or high-speed mode when the SLEEP instruction is executed in

sub-active mode.

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Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the MCU wait time

for clock stabilization when shifting to high-speed mode or medium-speed mode by using a

specific interrupt or command to cancel software standby mode, watch mode, or sub-active mode.

With a quartz oscillator (Table 21B-5), select a wait time of 8ms (oscillation stabilization time) or

more, depending on the operating frequency. With an external clock, there are no specific wait

requirements.

Bit 6 Bit 5 Bit 4

STS2 STS1 STS0 Description

0 0 0 Standby time = 8192 states (Initial value)

1 Standby time = 16384 states

1 0 Standby time = 32768 states

1 Standby time = 65536 states

1 0 0 Standby time = 131072 states

1 Standby time = 262144 states

1 0 Reserved

1 Standby time = 16 states

Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and

bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the

software standby mode, watch mode, and when making a direct transition.

Bit 3

OPE Description

0 In software standby mode, watch mode, and when making a direct transition, address

bus and bus control signals are high-impedance.

1 In software standby mode, watch mode, and when making a direct transition, the

output state of the address bus and bus control signals is retained. (Initial value)

Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.

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21B.2.2 System Clock Control Register (SCKCR)

Bit:76543210

PSTOP — — — STCS SCK2 SCK1 SCK0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W — — — R/W R/W R/W R/W

SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-

speed mode control.

SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bit 7—ø Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,

this bit controls ø output. See section 21B.12, ø Clock Output Disable Function for details.

Description

Bit 7 High-Speed Mode,

Medium-Speed Mode, Sleep Mode, Software Standby

Mode, Watch Mode, Hardware Standby

PSTOP Sub-Active Mode Sub-Sleep Mode Direct Transition Mode

0 ø output (initial value) ø output Fixed high High impedance

1 Fixed high Fixed high Fixed high High impedance

Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.

Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation

when the PLL circuit frequency multiplication factor is changed.

Bit 3

STCS Description

0 Specified multiplication factor is valid after transition to software standby mode, watch

mode, or subactive mode (Initial value)

1 Specified multiplication factor is valid immediately after STC bits are rewritten

711

Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in

high-speed mode, medium-speed mode, and sub-active mode.

Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode.

Bit 2 Bit 1 Bit 0

SCK2 SCK1 SCK0 Description

0 0 0 Bus master in high-speed mode (Initial value)

1 Medium-speed clock is ø/2

1 0 Medium-speed clock is ø/4

1 Medium-speed clock is ø/8

1 0 0 Medium-speed clock is ø/16

1 Medium-speed clock is ø/32

1——

21B.2.3 Low-Power Control Register (LPWRCR)

Bit:76543210

DTON*LSON*NESEL*SUBSTP*RFCUT — STC1 STC0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

Note: *Bits 7 to 4 in LPWRCR are valid in the H8S/2626 Series, but are reserved bits in the

H8S/2623 Series. For details see section 21A.2.3, Low-Power Control Register (LPWRCR).

The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.

The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not

initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,

see section 20.2.2, Low-Power Control Register.

Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by

executing the SLEEP instruction, this bit specifies whether or not to make a direct transition

between high-speed mode or medium-speed mode and the sub-active modes. The selected

operating mode after executing the SLEEP instruction is determined by the combination of other

control bits.

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Bit 7

DTON Description

0• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode, software standby mode, or watch mode*.

• When the SLEEP instruction is executed in sub-active mode, operation shifts

to sub-sleep mode or watch mode. (Initial value)

1• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts directly to sub-active mode*, or shifts to sleep mode or

software standby mode.

• When the SLEEP instruction is executed in sub-active mode, operation shifts directly

to high-speed mode, or shifts to sub-sleep mode.

Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.

Bit 6—Low-Speed ON Flag (LSON): When shifting to low power dissipation mode by executing

the SLEEP instruction, this bit specifies the operating mode, in combination with other control

bits. This bit also controls whether to shift to high-speed mode or sub-active mode when watch

mode is cancelled.

Bit 6

LSON Description

0• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode, software standby mode, or watch mode*.

• When the SLEEP instruction is executed in sub-active mode, operation shifts to

watch mode or shifts directly to high-speed mode.

• Operation shifts to high-speed mode when watch mode is cancelled. (Initial value)

1• When the SLEEP instruction is executed in high-speed mode, operation shifts to

watch mode or sub-active mode.

• When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-

sleep mode or watch mode.

• Operation shifts to sub-active mode when watch mode is cancelled.

Note: *Always set high-speed mode when shifting to watch mode or sub-active mode.

713

Bit 5—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the sampling

frequency of the subclock (øSUB) generated by the subclock oscillator is sampled by the clock (ø)

generated by the system clock oscillator. Set this bit to 0 when ø=5MHz or more.

Bit 5

NESEL Description

0 Sampling using 1/32 xø (Initial value)

1 Sampling using 1/4 xø

Bit 4—Subclock enable (SUBSTP): This bit enables/disables subclock generation.

Bit 4

SUBSTP Description

0 Enables subclock generation (Initial value)

1 Disables subclock generation

Bit 3—Oscillation Circuit Feedback Resistance Control Bit (RFCUT): This bit turns the

internal feedback resistance of the main clock oscillation circuit ON/OFF.

Bit 3

RFCUT Description

0 When the main clock is oscillating, sets the feedback resistance ON. When the main

clock is stopped, sets the feedback resistance OFF. (Initial value)

1 Sets the feedback resistance OFF.

Bit 2—Reserved: Only write 0 to this bit.

21B.2.4 Timer Control/Status Register (TCSR)

Bit:76543210

OVF WT/IT TME PSS*2RST/NMI CKS2 CKS1 CKS0

Initial value : 0 0 0 0 0 0 0 0

R/W : R/(W)*1R/W R/W R/W R/W R/W R/W R/W

Notes: 1. Only write 0 to clear the flag.

2. Bit 4 (PSS) in TCSR of WDT1 is valid in the H8S/2626 Series, but is a reserved bit in

the H8S/2623 Series. For details see section 21A.2.4, Timer Control/Status Register

(TCSR).

TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.

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Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer

Control/Status Register (TCSR).

The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized

in software standby mode.

Bit 4—Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT.

It also controls operation when shifting low power dissipation modes. The operating mode

selected after the SLEEP instruction is executed is determined in combination with other control

bits.

For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register

(TCSR), and this section.

Bit 4

PSS Description

0• TCNT counts the divided clock from the ø -based prescaler (PSM).

• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode or software standby mode. (Initial value)

1• TCNT counts the divided clock from the øsubclock-based prescaler (PSS).

• When the SLEEP instruction is executed in high-speed mode or medium-speed

mode, operation shifts to sleep mode, watch mode*1,*2, or sub-active mode*1,*2.

• When the SLEEP instruction is executed in sub-active mode*2, operation shifts to

sub-sleep mode*2, watch mode*2, or high-speed mode.

Notes: 1. Always set high-speed mode when shifting to watch mode or sub-active mode.

2. Bit 4 (PSS) of the TCSR register in WDT1 is valid in the H8S/2626 Series, but must

always be written with 0 in the H8S/2623 Series, as this version does not support

subclock operation. For details see section 21A.2.4, Timer Control/Status Register

(TCSR).

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21B.2.5 Module Stop Control Register (MSTPCR)

MSTPCRA

Bit:76543210

MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0

Initial value : 0 0 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRB

Bit:76543210

MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCRC

Bit:76543210

MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0

Initial value : 1 1 1 1 1 1 1 1

R/W : R/W R/W R/W R/W R/W R/W R/W R/W

MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.

MSTPCRA to MSTPCRC are initialized to H'3FFFFF by a reset and in hardware standby mode.

They are not initialized in software standby mode.

MSTPCRA/MSTPCRB/MSTPCRC Bits 7 to 0—Module Stop (MSTPA7 to MSTPA0,

MSTPB7 to MSTPB0, MSTPC7 to MSTPC0): These bits specify module stop mode. See table

21B-4 for the method of selecting the on-chip peripheral functions.

MSTPCRA/MSTPCRB/

MSTPCRC Bits 7 to 0

MSTPA7 to MSTPA0,

MSTPB7 to MSTPB0,

MSTPC7 to MSTPC0 Description

0 Module stop mode is cleared (initial value of MSTPA7 and MSTPA6)

1 Module stop mode is set (initial value of MSTPA5–0, MSTPB7–0,

MSTPC7–0)

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21B.3 Medium-Speed Mode