DG445DY-T - Intersil Corporation - Datasheet.Directory

FN3586.10

DG444, DG445

Monolithic, Quad SPST, CMOS Analog

Switches

The DG444 and DG445 monolithic CMOS analog switches

are drop-in replacements for the popular DG21 1 and DG212

series devices. They include four independent single pole

single throw (SPST) analog switches and TTL and CMOS

compatible digital inputs.

These switches feature lower analo g ON resistance (<85Ω)

and faster switch time (tON <250ns) compared to the DG211

and DG212. Charge injection has been reduced, simplifying

sample and hold applications.

The improvements in the DG444 series are made possible

by using a high voltage silicon-gate process. An epitaxial

layer prevents the latch-up associated with older CMOS

technologies. The 44V maximum voltage range permits

controlling ±20V signals when operating with ±20V power

supplies.

The four switches are bilateral, equally matched for AC or

bidirectional signals. The ON resistance variation with

analog signals is quite low over a ±5V analog input range.

The switches in th e DG444 and DG445 are identical,

differing only in the polarity of the selection logic.

Pinout DG444, DG445

(16 LD SOIC, TSSOP)

TOP VIEW

Features

• ON Resistance (Max). . . . . . . . . . . . . . . . . . . . . . . . . 85Ω

• Low Power Consumption (PD) . . . . . . . . . . . . . . . <35μW

• Fast Switching Action

-t

ON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns

-t

OFF (Max, DG444) . . . . . . . . . . . . . . . . . . . . . . . 140ns

• Low Charge Injection

• Upgrade from DG211, DG212

• TTL, CMOS Compatible

• Single or Split Supply Operation

• Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

• Audio Switching

• Battery Operated Systems

• Data Acquisition

• Hi-Rel Systems

• Sample and Hold Circuits

• Communication Systems

• Automatic Test Equipment

IN1

V-

GND

IN4

IN2

V+

IN3

Ordering Information

PART

NUMBER PART

MARKING TEMP.

RANGE (°C) PACKAGE PKG.

DWG. #

DG444DY* DG444DY -40 to +85 16 Ld SOIC M16.15

DG444DYZ*

(Note) DG444DYZ -40 to +85 16 Ld SOIC

(Pb-free) M16.15

DG444DVZ*

(Note) DG444DVZ -40 to +85 16 Ld TSSOP

(Pb-free) M16.173

DG445DY* DG445DY -40 to +85 16 Ld SOIC M16.15

DG445DYZ*

(Note) DG445DYZ -40 to +85 16 Ld SOIC

(Pb-free) M16.15

DG445DVZ*

(Note) DG445DVZ -40 to +85 16 Ld TSSOP

(Pb-free) M16.173

*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-fre e plus anne al produ cts e mploy specia l Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate term ination fin ish, which are RoHS complia nt and comp at ible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

product s are MS L classifi ed at Pb-f ree pea k reflow temper atures t hat

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Data Sheet June 4, 2007

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

2FN3586.10

June 4, 2007

Functional Diagrams

Schematic Diagram (One Channel)

TRUTH TABLE

LOGIC VIN DG444 DG445

0≤0.8V ON OFF

1≥2.4V OFF ON

IN1

DG444

IN2

IN3

IN4

IN1

DG445

SWITCHES SHOWN FOR LOGIC “1” INPUT

IN2

IN3

IN4

Pin Descriptions

PIN SYMBOL DESCRIPTION

1IN

1Logic Control for Switch 1

1Drain (Output) Terminal for Switch 1

1Source (Input) Terminal for Switch 1

4 V- Negative Power Supply Terminal

5 GND Ground Terminal (Logic Common)

4Source (Input) Terminal for Switch 4

4Drain (Output) Terminal for Switch 4

8IN

4Logic Control for Switch 4

9IN

3Logic Control for Switch 3

10 D3Drain (Output) Terminal for Switch 3

11 S3Source (Input) Term inal for Switch 3

12 VLLogic Reference Voltage

13 V+ Positive Power Supply Terminal (Substrate)

14 S2Source (Input) Terminal for Switch 2

15 D2Drain (Output) Terminal for Switch 2

16 IN2Logic Control for Switch 2

V+

INX

GND

V-

V+

DG444, DG445

3FN3586.10

June 4, 2007

Absolute Maximum Ratings Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44V

GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V

VL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to (V+) + 0.3V

Digital Inputs, VS, VD (Note 1). . . . . (V-) -2V to (V+) + 2V or 30mA,

Whichever Occurs First

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA

Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20V (Max)

Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max)

Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min)

Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20ns

Thermal Resistance (Typical, Note 2) θJA (°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Maximum Junction Temperature (Plastic Packages). . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.

2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(°C) (NOTE 4)

MIN (NOTE 5)

TYP (NOTE 4)

MAX UNITS

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON RL = 1kΩ, CL = 35pF, VS = ±10V

(Figure 1) +25 - 120 250 ns

Turn-OFF Time, tOFF

DG444 +25 - 110 140 ns

DG445 +25 - 160 210 ns

Charge Injection, Q (Figure 2) CL = 1nF, VG = 0V, RG = 0Ω+25 - -1 - pC

OFF Isolation (Figure 4) RL = 50Ω, CL = 5pF, f = 1MHz +25 - 60 - dB

Crosstalk (Channel-to-Channel)

(Figure 3) +25 - -100 - dB

Source OFF Capacitance, CS(OFF) f = 1MHz, VANALOG = 0 (Figure 5) +25 - 4 - pF

Drain OFF Capacitance, CD(OFF) +25 - 4 - pF

Channel ON Capacitance,

CD(ON) + CS(ON) +25 - 16 - pF

DIGITAL INPUT CHARACTERISTICS

Input Current VIN Low, IIL VIN Under Test = 0.8V,

All Others = 2.4V Full -0.5 -0.00001 0.5 μA

Input Current VIN High, IIH VIN Under Test = 2.4V,

All Others = 0.8V Full -0.5 0.00001 0.5 μA

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full -15 - 15 V

Drain-Source ON Resistance,

rDS(ON) IS = 10mA, VD = ±8.5V,

V+ = 13.5V, V- = -13.5V +25 - 50 85 Ω

Full - - 100 Ω

Source OFF Leakage Current, IS(OFF) V+ = 16.5V, V- = -16.5V,

VD = ±15.5V, VS = 15.5V +25 -0.5 0.01 0.5 nA

+85 -5 - 5 nA

DG444, DG445

4FN3586.10

June 4, 2007

Drain OFF Leakage Current,

ID(OFF) V+ = 16.5V, V- = -16.5V,

VD = ±15.5V, VS = 15.5V +25 -0.5 0.01 0.5 nA

+85 -5 - 5 nA

Channel ON Leakage Current,

ID(ON) + IS(ON) V+ = 16.5V, V- = -16.5V,

VS = VD, = ±15.5V +25 -0.5 0.08 0.5 nA

+85 -10 - 10 nA

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 16.5V, V- = -16.5V,

VIN = 0V or 5V +25 - 0.001 1 μA

+85 - - 5 μA

Negative Supply Current, I- +25 -1 -0.0001 - μA

+85 -5 - - μA

Logic Supply Current, IL+25 - 0.001 1 μA

+85 - - 5 μA

Ground Current, IGND +25 -1 -0.001 - μA

+85 -5 - - μA

Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),

Unless Otherwise Specified (Continued)

PARAMETER TEST CONDITIONS TEMP

(°C) (NOTE 4)

MIN (NOTE 5)

TYP (NOTE 4)

MAX UNITS

Electrical Specifications (Single Supply) Test Conditions: V+ = 12V, V- = 0V, VL = 5V, VIN = 2.4V, 0.8V (Note 3),

Unless Otherwise Specified

PARAMETER TEST CONDITIONS TEMP

(°C) (NOTE 4)

MIN (NOTE 5)

TYP (NOTE 4)

MAX UNITS

DYNAMIC CHARACTERISTICS

Turn-ON Time, tON RL = 1kΩ, CL = 35pF, VS = 8V

(Figure 1) +25 - 300 450 ns

Turn-OFF Time, tOFF +25 - 60 200 ns

Charge Injection, Q (Figure 2) CL = 1nF, VG = 6V, RG = 0Ω+25 - 2 - pC

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, VANALOG Full 0 - 12 V

Drain-Source ON Resistance, rDS(ON) IS = -10mA, VD = 3V, 8V

V+ = 10.8V, VL = 5.25V +25 - 100 160 Ω

Full - - 200 Ω

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+ V+ = 13.2V, VIN = 0V or 5V,

VL = 5.25V +25 - 0.001 1 μA

Full - - 5 μA

Negative Supply Current, I- +25 -1 -0.0001 - μA

Full -5 - - μA

Logic Supply Current, IL+25 - 0.001 1 μA

Full - - 5 μA

Ground Current, IGND +25 -1 -0.001 - μA

Full -5 - - μA

NOTES:

3. VIN = input voltage to perform proper function.

4. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

5. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

DG444, DG445

5FN3586.10

June 4, 2007

Test Circuits and Waveforms

VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing

edge of the output waveform.

FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

FIGURE 3. CROSSTALK TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT

NOTE: Logic input waveform is inverted for switches that have

the opposite logic sense.

50%

tr < 20ns

tf < 20ns

tOFF

80%

tON

LOGIC

INPUT

SWITCH

INPUT

SWITCH

OUTPUT

80%

Repeat test for Channels 2, 3 and 4.

For load conditions, see Specifications. CL includes fixture and

stray capacitance.

VOVSRL

RLrDS ON()

------------------------------------

SWITCH

INPUT

LOGIC

INPUT

IN1

V+

RLCL

GND V-

SWITCH ΔVO

INXOFF ON

INXOFF OFF

OFF

Q = ΔVO x CL

(DG444)

(DG445)

OUTPUT

V+

GND

V-

VIN = 3V

0V, 2.4V

ANALYZER

+15V

V+

10dBm

SIGNAL

GENERATOR

RLGND

IN1

IN2

50Ω

0V, 2.4V

V-

-15V

VDANALYZER

+15V

10dBm

SIGNAL

GENERATOR

V+

V-

-15V

0V, 2.4V

INX

GND

DG444, DG445

6FN3586.10

June 4, 2007

Application Information

FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT

Test Circuits and Waveforms (Continued)

+15V

V+

GND

INX

V-

-15V

IMPEDANCE

ANALYZER

f = 1MHz

0V, 2.4V

FIGURE 6. PRECISION WEIGHTED RESISTOR

PROGRAMMABLE GAIN AMPLIFIER

+15V

FET INPUT

OP AMP

VIN

+5V

4kΩ

5kΩ

90kΩ

VOUT

WITH SW4 CLOSED

VOUT

VIN

----------------R1R2R3R4

+++

-------------------------------------------------100==

GAIN ERROR IS DETERMINED ONLY BY

THE RESISTOR TOLERANCE, OP AMP OFFSET

AND CMRR WILL LIMIT ACCURACY OF CIRCUIT

GAIN1

AV = 1

GAIN2

AV = 10

GAIN3

AV = 20

GAIN4

AV = 100

V-

-15V

GND

1kΩ

-15V

VLV+

DG444 OR DG445

+15V

FIGURE 7. LEVEL SHIFTER

VIN

1/4 DG444

+5V

V-

VOUT

GND

+15V

V+

10kΩ

+5V 0V

+15V

DG444, DG445

7FN3586.10

June 4, 2007

Typical Performance Curves

FIGURE 8. SWITCHING THRESHOLD vs SUPPLY VOLTAGE FIGURE 9. SUPPLY CURRENT vs TEMPERATURE

FIGURE 10. INPUT CURRENT vs TEMPERATURE FIGURE 11. rDS(ON) vs VD AND TEMPERATURE

FIGURE 12. CROSST ALK REJECTION AND OFF ISOLA TION

vs FREQUENCY FIGURE 13. CHARGE INJECTION vs SOURCE VOLTAGE

VL = 7V

VL = 5V

04 8 12 16 20

SUPPLY VOLTAGE (±V)

VIN (V)

I+, IGND

-(I-)

0-55 50 100 125

0.001

0.01

0.1

102

103

104

105

TEMPERATURE (°C)

IL, I+, I-, IGND (nA )

0.1

102

103

104

105

IIN (pA)

0-55 50 100 125

TEMPERATURE (°C)

rDS(ON) (Ω)

VD (V)

V+ = +15V

V- = -15V

+85°C

+25°C

0°C

-40°C

-15 0 15

140

120

100

(dB)

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

V+ = +15V

V- = -15V

PGEN = 10dBm

CROSSTALK

OFF ISOLATION

VS (V)

-10 0 10

Q (pC)

-30

-20

-10

50 V+ = +15V

V- = -15V

CL = 10nF CL = 1nF

DG444, DG445

8FN3586.10

June 4, 2007

FIGURE 14. SOURCE/DRAIN CAP ACIT ANCE vs ANALOG

VOLTAGE FIGURE 15. LEAKAGE CURRENTS vs ANALOG VOLTAGE

FIGURE 16. SWITCHING TIME vs INPUT VOLTAGE (DG444) FIGURE 17. SWITCHING TIME vs INPUT VOLTAGE (DG445)

FIGURE 18. SWITCHING TIME vs POWER SUPPLY VOLT AGE

(DG444) FIGURE 19. SWITCHING TIME vs POWER SUPPLY VOLTAGE

(DG445)

Typical Performance Curves (Continued)

CS, D (pF)

-15 -10 -5 0 5 10 15

VA (V)

V+ = +15V

V- = -15V

CS(OFF), CD(OFF)

CS(ON) + CD(ON)

-20

-40

-60

-80

-100-15 -10 -5 0 5 10 15

VS, VD (V)

IS, ID (pA)

IS(OFF), ID(OFF)

IS(ON) + ID(ON)

V+ = +15V

V- = -15V

FOR I(OFF), VD = -VS

234 5

V+ = +15V

V- = -15V

tON

VIN (V)

tON, tOFF (ns)

160

140

120

100

tOFF

2345

V+ = +15V, V- = -15V

VL = 5V

tON

VIN (V)

150

100

tOFF

tON, tOFF (ns)

10 2212 16 20

SUPPLY VOLTAGE (±V)

14 18

160

140

120

100

tON

tOFF

tON, tOFF (ns)

10 2212 16 20

SUPPLY VOLTAGE (±V)

14 18

160

140

120

100

tON

tOFF

VL = 5V

tON, tOFF (ns)

DG444, DG445

9FN3586.10

June 4, 2007

FIGURE 20. SWITCHING TIME vs INPUT VOLTAGE (DG444)

(SINGLE 12V SUPPLY) FIGURE 21. SWITCHING TIMES vs SINGLE SUPPLY VOLTAGE

FIGURE 22. CHARGE INJECTION vs SOURCE VOL TAGE

(SINGLE 12V SUPPLY) FIGURE 23. SOURCE/DRAIN LEAKAGE CURRENTS (SINGLE

12V SUPPLY)

FIGURE 24. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY)

Typical Performance Curves (Continued)

2345

V+ = +12V, V- = 0V

VL = 5V tON

VIN (V)

400

300

200

100

tOFF

tON, tOFF (ns)

V- = 0V, VL = 5V

tON (444)

POSITIVE SU PPLY (V)

010 12 14 16 18 20 22

500

400

300

200

100

tON (445)

tOFF (445) tOFF (444)

tON, tOFF (ns)

VS (V)

04 8

Q (pC)

-10

V+ = 12V

V- = 0V

CL = 10nF CL = 1nF

30 10

-10

-20

-30

-40

IS, ID (pA)

06 12

VS, VD (V)

IS(OFF), ID(OFF)

IS(ON) + ID(ON) V+ = +12V

V- = 0V

FOR ID, VS = 0

FOR IS, VD = 0

00612

VA (V)

CS, D (pF)

V+ = +12V

V- = 0V

CS(OFF), CD(OFF)

CS(ON) + CD(ON)

DG444, DG445

10 FN3586.10

June 4, 2007

Die Characteristics

METALLIZATION:

Type: SiAl

Thickness: 12kÅ ±1kÅ

PASSIVATION:

Type: Nitride

Thickness: 8kÅ ±1kÅ

WORST CASE CURRENT DENSITY:

9.1 x 104 A/cm2

Metallization Mask Layout DG444, DG445

IN2

IN1

(7) (8) (9) (10)

(11) S3

(12) VL

(13) V+ SUBSTRATE

(14) S2

(15) D2

(16)(1)(2)

S1 (3)

V- (4)

GND (5)

S4 (6)

D4IN4IN3D3

DG444, DG445

11 FN3586.10

June 4, 2007

DG444, DG445

Thin Shrink Small Outline Plastic Packages (TSSOP)

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.15mm (0.006

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact. (Angles in degrees)

INDEX

AREA E1

123

-B-

0.10(0.004) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004) c

E0.25(0.010) BM M

0.25

0.010

GAUGE

PLANE

0.05(0.002)

M16.173

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A - 0.043 - 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.033 0.037 0.85 0.95 -

b 0.0075 0.012 0.19 0.30 9

c 0.0035 0.008 0.09 0.20 -

D 0.193 0.201 4.90 5.10 3

E1 0.169 0.177 4.30 4.50 4

e 0.026 BSC 0.65 BSC -

E 0.246 0.256 6.25 6.50 -

L 0.020 0.028 0.50 0.70 6

N16 167

α0o8o0o8o-

Rev. 1 2/02

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN3586.10

June 4, 2007

DG444, DG445

Small Outline Plastic Packages (SOIC)

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm

(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.3859 0.3937 9.80 10.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N16 167

α0° 8° 0° 8° -

Rev. 1 6/05