SHC803BM, CM SHC804BM, CM (R) High Speed SAMPLE/HOLD AMPLIFIER error is guaranteed to be within 1/2LSB for 12-bit systems. Stability over temperature is excellent, with only 5ppm/C of gain drift and 4ppm of FSR/C of charge offset drift over the -25 to +85C temperature range. FEATURES 350ns max ACQUISITION TIME 0.01% THROUGHPUT NONLINEARITY 150ns max SAMPLE-TO-HOLD SETTLING TIME INPUT BUFFER (SHC803) The 25ps maximum aperture uncertainty of SHC803 and SHC804 permits sampling (to 0.01% of Full Scale Range) of signals with rates of change of up to 100V/s. These sample/holds have been optimized for use with Burr-Brown's high speed 12-bit analog-todigital converter, model ADC803. Together these components are capable of accurately digitizing fast changing signals at sample rates as high as 500k samples per second. 24-PIN HERMETICALLY-SEALED METAL PACKAGE DESCRIPTION The SHC803 and SHC804 are high speed sample/hold amplifiers designed for use in fast 12-bit data acquisition systems and signal processing systems. The SHC803 contains a fast-settling unity-gain amplifier for buffering high impedance sources or for use with CMOS multiplexers. The digital inputs (HOLD and HOLD) are TTLcompatible. Power supply requirements are 15V and +5V and the specification temperature range is -25C to +85C. The SHC803 and SHC804 are packaged in a 24-pin dual-in-line hermetic metal package. SHC804 is pin-compatible with other sample/holds on the market with similar performance characteristics. The SHC804 acquires a 10V signal change in less than 350ns to 1/2LSB at 12 bits. Throughput nonlinearity Buffer Output Sample/Hold Analog Input SHC803 Only 1000 1000 CH Buffer Input Sample/ Hold Output Switch Drive Hold Hold Analog Common International Airport Industrial Park * Mailing Address: PO Box 11400 * Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (c) 1983 Burr-Brown Corporation PDS-512C Printed in U.S.A. October, 1993 SPECIFICATIONS ELECTRICAL At +25C, rated power supplies and a 1k output load, unless otherwise specified. SHC803/SHC804BM PARAMETER MIN SHC803/SHC804CM TYP MAX MIN TYP * * * MAX UNITS SAMPLE/HOLD INPUTS (without Input Buffer) ANALOG Voltage Range RIN DIGITAL (HOLD, HOLD) VIH VIL IIH, VIN = +2.7V IIL, VIN = +0.4V 10.25 11 1.00 +2.0 V k * +0.8 +60 -1.2 * * * V V A mA * 5 * 3 1.5 V/V % ppm/C % of FSR(1) mV ppm of FSR/C 5 4 * 0.1 * * * mV ppm of FSR/C V/s mV/s % of FSR % of FSR/%VCC % of FSR/%VDD * ns ns SAMPLE/HOLD TRANSFER CHARACTERISTICS (without Input Buffer) ACCURACY Sample Mode Gain Gain Error Temperature Coefficient Linearity Error Zero Offset Temperature Coefficient Hold Mode Charge Offset Temperature Coefficient Droop Rate: at +25C +85C Throughput Nonlinearity Power Supply Sensitivity(2): VCC V DD DYNAMIC CHARACTERISTICS Acquisition Time (with 10V Step) to within: 0.1% (10mV) 0.01% (1mV) Sample-to-Hold Settling Time to within 0.01% (1mV) Sample-to-Hold Transient Amplitude Aperture Delay TIme(3) Aperture Uncertainty Sample Mode: Output Slew Rate Full Power Bandwidth Small Signal Bandwidth Hold Mode Feedthrough Rejection (10V Square Wave Input) SAMPLE/HOLD OUTPUT Voltage Range Output Current Short Circuit Protection Output Impedance (at DC) -1 * 0.1 10 0.005 5 2.5 3 0.001 1 1 2 3 0.5 10 10 5 0.5 0.01 0.002 0.003 220 250 0.005 10.25 50 11 1 2 * * * 350 100 60 15 10 160 1 16 0.03 1 * 0.5 0.5 150 150 25 25 * * * * * * * * * Indefinite to Common 0.01 ns mVPEAK ns ps V/s MHz MHz * % * V mA * * 0.1 * * * * * * * * * * mV ppm of FSR/C nA || pF V * * * kHz V/s s INPUT BUFFER CHARACTERISTICS (SHC803 only) INPUT Offset Voltage vs Temperature Bias Current Impedance VIN Range 1/2 1.5 10.25 DYNAMIC CHARACTERISTICS Full Power Bandwidth Slew Rate(4) Settling Time(4) to 2mV for 10V Step OUTPUT VOUT Range Output Current 5 2.5 25 108 || 5 11 * * * 320 10 2.5 10.25 10.25 * * V mA The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) SHC803/804BM, CM 2 SPECIFICATIONS (CONT) ELECTRICAL At +25C, rated power supplies and a 1k output load, unless otherwise specified. SHC803/SHC804BM PARAMETER POWER SUPPLY REQUIREMENTS Rated Voltage: VCC VDD Quiescent Current (No Load) SHC804: +VCC -V CC VDD SHC803: +VCC -VCC V DD Power Dissipation: SHC804 SHC803 TEMPERATURE RANGE Specification Storage SHC803/SHC804CM MIN TYP MAX MIN TYP MAX UNITS 13.5 +4.75 15 +5.00 16.5 +5.25 * * * * * * V V 30 15 5 33 18 5 700 790 35 20 10 40 25 10 875 1100 * * * * * * * * * * * * * * * * mA mA mA mA mA mA mW mW * * C C -25 -55 +85 +125 * * * Specification same as SHC803/SHC804BM. NOTES: (1) FSR means Full Scale Range and is 20V for SHC803 and SHC804. (2) Sensitivity of offset plus charge offset. (3) With respect to HOLD. For HOLD add 5ns typical. (4) With buffer connected to the sample/hold amplifier. PACKAGE INFORMATION(1) ABSOLUTE MAXIMUM RATINGS Input Overvoltage .............................................................................. 15V +VCC to VCC COMMON ............................................................... 0 to +18V -VCC to VCC COMMON ............................................................... 0 to -18V Voltage on Digital Inputs (pins 11 and 12) ........................... -0.5V to +7V Power Dissipation ....................................................................... 1500mW VDD to DCOM .................................................................................... -0.5V Analog Output ............................................... Indefinite Short to VCC COM MODEL SCH803/804CM, BM SCH803/804BM PACKAGE PACKAGE DRAWING NUMBER 24-Pin Metal 24-Pin Metal 113 113 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliablility. (R) 3 SHC803/804BM, CM CONNECTION DIAGRAMS SHC803CM, BM VOUT Digital Power Supply 1 Analog Output 1F 2 NC VCC COM 23 COM 3 NC -VCC 22 -15V 4 NC COM 21 5 NC 6 NC 7 8 VOUT +15V +VCC 24 1F Analog Power Supply Analog Output 2 NC VCC COM 23 3 NC -VCC 22 COM 21 NC 20 5 NC NC 20 NC 19 6 NC NC 19 NC NC 18 7 NC NC 18 NC Buffer 17 In 8 NC NC 17 9 VDD NC 16 9 VDD NC 16 10 DCOM Digital Power Supply Signal Source COM 15 11 Hold Buffer 14 Out 12 Hold S/H In 13 COM NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 Sample/Hold Output NC NC NC NC NC NC NC VDD DCOM HOLD HOLD S/H In 14 15 16 17 18 19 20 21 22 23 Buffer Out, SHC803 only COM NC Buffer In, SHC803 only NC NC NC COM -VCC VCC COM 24 +VCC 1F COM -15V 1F Analog Power Supply +5V 10 DCOM 11 Hold NC 14 12 Hold S/H In 13 COM 15 Signal Source Hold mode due to storage capacitor and FET switch leakage current and the input bias current of the output amplifier. DESCRIPTION Analog voltage output Not connected Not connected Not connected Not connected Not connected Not connected Not connected Logic supply Logic supply common Logic "1" = HOLD Logic "0" = HOLD SHC804 input; for SHC803 connect pin 13 to pin14 Not connected for SHC804 Signal common Not connected Not connected for SHC804 Not connected Not connected Not connected Signal common -15V supply Analog to power common, connected to case +15V supply Feedthrough is the amount of output voltage change caused by an input voltage change when the sample/hold is in the Hold mode. Aperture Delay Time is the time required to switch from Sample to Hold. The time is measured from the 50% point of the Hold mode control transition to the time at which the output stops tracking the input. Aperture Uncertainty Time is the nonrepeatibility of aperture delay time. Acquisition Time is the time required for the sample/hold output to settle to within a given error band of its final value when the sample/hold is switched from Hold to Sample. Charge Offset (Pedestal) is the output voltage change that results from charge coupled into the Hold capacitor through the gate capacitance of the switching field effect transistor. This charge appears as an offset at the output. Sample-to-Hold Switching Transient is the switching transient which appears on the output when the sample/hold is switched from Sample to Hold. Both the magnitude and the settling time of the transient are specified. DISCUSSION OF SPECIFICATIONS OPERATION Throughput Nonlinearity is defined as total Hold mode, nonadjustable, input to output error caused by charge offset, gain nonlinearity, droop, feedthrough, and thermal transients. It is the inaccuracy due to these errors which cannot be corrected by Offset and Gain adjustments. A simplified circuit diagram of SHC803/804 is shown on page 1. The SHC803 includes a noninverting unity-gain op amp to serve as a source-impedance buffer when the sample/ hold is used with CMOS analog multiplexers. The SHC804 and SHC803 are identical except for this buffer. Gain Error is the difference between the input and output voltage magnitude (in the Sample mode) due to the amplifier gain errors. In the Sample (track) mode the circuit acts as a unity-gain inverting amplifier. In the Hold mode, the capacitor, CH, holds the value of the output at the time the unit was switched to the Hold mode. Additional circuits compensate for switching transients and provide switch leakage current Droop Rate is the voltage decay at the output when in the (R) SHC803/804BM, CM +15V +VCC 24 NC PIN ASSIGNMENTS PIN 1 4 +5V COM SHC804CM, BM 4 Hold mode. The output voltages will be held constant at the value present when the Hold command is given. cancellation. The amplifier provides high current drive and low output impedance to external loads. If pin 11 is used, pin 12 must be connected to the DCOM (pin 10). If pin 12 is used, pin 11 must be tied to VDD. Using the HOLD and HOLD inputs as logic function may adversely affect the charge offset (pedestal). A clean digital signal (no overshoot) at the HOLD of HOLD inputs will also reduce charge offset errors. Pins 11 and 12 present less than one standard TTL load (two LSTTL loads) to the digital drive circuit. GAIN, OFFSET, CHARGE OFFSET SCH803 and SCH804 have been internally-trimmed to eliminate the need for external trim potentiometers for Gain, Offset (in Sample mode) and Charge Offset (Pedestal). System Gain and Offset errors can be adjusted elsewhere in the system, at an input amplifier preceding the sample/hold, or at an analog-to-digital converter following the sample/ hold. V Sample-to-Hold Transient VIN VOUT OUTPUT LOADING Care must be taken when loading the output of the SHC803/ 804 to avoid possible oscillations, current limiting and performance variations over temperature. Acquisition Time The maximum capacitive load to avoid oscillations is about 300pF. Recommended resistive load is 500 or more, although values as low as 250 may be used. Acquisition and sample-to-hold settling times are relatively unaffected by resistive loads down to 250 in parallel with capacitive loads up to 100pF. Higher capacitances will affect acquisition and settling times. Droop Sample Hold t ANALOG SIGNAL SOURCE CONSIDERATIONS The output impedance of the signal source driving the SHC804 will affect the accuracy of the sample and hold operation both statically (at DC) and dynamically. The output impedance of the signal source should be low and remain low over a wide bandwidth. A small capacitor at the driving source may help to improve the charge offset errors that are affected by dynamic source impedance. FIGURE 1. Definition of Acquisition Time, Droop and Sample-to-Hold Transient. INSTALLATION GROUNDING AND BYPASSING SHC803 and SHC804 have four COMMON pins (pins 10, 15, 21 and 23) and all must be tied together and connected to the system analog common (VCC COM) as close to the package as possible. It is preferable to have a large ground plane surrounding the sample/hold and have all four common pins soldered directly to it. Note that the metal case is internally connected to pin 23; therefore, care must be taken to avoid a ground loop if the case is allowed to contact the ground plane. SHC803 BUFFER AMPLIFIER The buffer amplifier incorporated in the SHC803 provides appropriate drive characteristics to the sample/hold amplifier. Again a 20pF to 50pF capacitor added to the output of the buffer amplifier may improve charge offset performance. The buffer amplifier is optimized for fast settling with 10Vp-p signals. However, for step input signals greater than 10V, a protection network (Figure 2) is required to prevent the buffer from overload, resulting in excessive settling time. Most digital return currents pass through pin 10. Noise from the switch-drive circuit may couple directly into the main op amp summing junction, a very noise-sensitive node. Care must be taken to insure that no voltage differences occur between pin 10 and the other common pins. This is the reason pin 10 must be connected directly to the ground plane. The data sheet for the Burr-Brown model ADC803 analogto-digital converter contains a sample printed circuit board layout incorporating many of the above considerations. For the same reason, the logic supply should be kept as free of noise as possible. VCC supply lines (pins 24 and 22) are internally bypassed to common with 0.01F capacitors. It is recommended that the user install additional external 0.1F to 1F tantalum bypass capacitors at each supply pin. 2k IN914 SAMPLE/HOLD CONTROL A TTL logic "0" at pin 11 (or a logic "1" at pin 12) switches the SHC803/804 into the Sample (track) mode. In this mode, the device acts as a unity-gain inverting amplifier, the output following the inverse of the input. A logic "1" at pin 11 (or a logic "0" at pin 12) will switch the SHC803/804 into the 14 2k 17 FIGURE 2. SHC803 Buffer Amplifier Protection For Input Steps Greater Than 10V. (R) 5 SHC803/804BM, CM APPLICATIONS impedance amplifier to further minimize the effects of high frequency transient currents present in an output load. SIGNAL DIGITIZATION Sample/hold amplifiers are commonly used to hold input voltages to an A/D converter constant during conversion. Digitizing errors result if the analog signal being digitized varies excessively during conversion. A typical SHC804/ADC803 connection for high-speed digitization is illustrated in Figure 3. A short delay must occur before the A/D start command is asserted since the ADC803 makes its first conversion decision 100ns after the start command is asserted. Because the SHC804 sample-to-hold settling time is 150ns (maximum) the additional delay required is about 50ns. This can be achieved using a one-shot or by using the delay provided by the six inverters of a hex inverter integrated circuit. This combination can be triggered at rates of over 500k samples per second. For example, the Burr-Brown ADC803 is a 12-bit successive-approximation converter with a 1.5s conversion time. To insure the accuracy of the output data, the analog input signal to the A/D converter must not change more than 1/2LSB during the conversion. Using the input buffer of the SHC803 provides a high input impedance sample/hold for CMOS analog multiplexers such as the high speed Burr-Brown MPC800. The high input impedance of the SHC803 buffer minimizes DC errors caused by the ON resistance of the multiplexer switches and/ or relatively high impedance signal sources (Figure 4). The multiplexer can be switched to a new channel as soon as the SHC803 is switched to the Hold mode. The multiplexer/ buffer combination settles to the new input value during the sample/hold acquisition time and A/D conversion time. This "overlap" technique results in little or no loss in throughput rate. The maximum rate of change for sine wave inputs is dv/dt (max) = 2Af (V/s). If one allows a 1/2LSB change (2.44mV) for a 10V input swing to the A/D converter, the allowable input rate-of-change limit would be 2.44mV/1.5s = 1.63mV/ s. Thus the sampled sinusoidal signal frequency limit is f = (1.63 X 103)/2A = 259/A(Hz) where A is the amplitude of the sine wave. For a 10V sine wave this corresponds to a frequency of 26Hz. A sample/hold in front of the A/D converter "freezes" the converter's input signal whenever it is necessary to make a conversion. The rate-of-change limitation calculated above no longer exists. If a sample/hold has acquired an input signal and is tracking it, the sample/hold can be commanded to hold at any instant. There is a short delay between the time the hold command is asserted and the time the circuit actually holds. This delay is called aperture delay. The hold command signal can usually be advanced in time to cause the amplifier to hold when one wants it to hold. Analog Input VIN 13 SHC804 ADC803 A/D Converter 1 Start 12 The uncertainty in aperture delay, called aperture jitter, is a key consideration. For the SHC803/804 there is a 25ps maximum period during which the input signal should not change, for example, more than 1/2LSB for 12-bit systems. For a 10V input range (1/2LSB = 2.44mV), the input signal rate of change limitation is 2.44mV/25ps = 97.6V/s. The equivalent input sine wave frequency is 11 50ns Delay Start Conversion FIGURE 3. SHC804 and ADC803 Provide Sampling Rates Over 500k Samples Per Second. f = 97.6 X 10 /2A = 15.5/A(MHz), 6 60,000 times higher than using the A/D alone. Ch 1 However, there are other considerations. The resampling rate of an ADC803 is 1.5s (A/D conversion time) + 0.3s (sample/hold acquisition time) = 1.8s. If one samples a sine wave at the Nyquist rate this permits sampling a frequency of 278kHz. The above analysis assumed that the droop rate of the sample/hold is negligible--less than 1/2LSB during the conversion time--and that the large signal bandwidth response of the sample/hold causes negligible waveform distortion. To A/D Converter VOUT 16 Channels Single-ended Analog Inputs Burr-Brown MPC800 1 28 2 17 SHC803 14 Ch 16 Select USING THE SHC804 WITH THE ADC803 13 4 EN A3 A2 A1 A0 18 11 12 Hold 14 15 16 17 Channel Address ADC803 is a 1.5s, 12-bit successive approximation A/D converter. Its input circuitry has been designed to minimize high frequency current transients that appear at the input of successive approximation A/D converters. The SHC803 and SHC804 have been designed with a fast-settling, low output- FIGURE 4. Using SHC803 With The MPC800 Analog Multiplexer. (R) SHC803/804BM, CM 19 6