32-Channel, 14-Bit DAC with Full-Scale Output Voltage Programmable from 50 V to 200 V AD5535 FEATURES GENERAL DESCRIPTION High integration 32-channel, 14-bit DAC with integrated high voltage output amplifier Guaranteed monotonic Housed in 15 mm x 15 mm CSP_BGA package Full-scale output voltage Programmable from 50 V to 200 V via reference input 700 A drive capability Integrated silicon diode for temperature monitoring DSP-/microcontroller-compatible serial interface 1.2 MHz channel update rate Asynchronous RESET facility -10C to +85C temperature range The AD5535 is a 32-channel, 14-bit DAC with an on-chip high voltage output amplifier. This device is targeted for optical micro-electromechanical systems. The output voltage range is programmable via the REF_IN pin. The output range is 0 V to 50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V. Each amplifier can source 700 A, which is ideal for the deflection and control of optical MEMS mirrors. The selected DAC register is written to via the 3-wire interface. The serial interface operates at clock rates of up to 30 MHz and is compatible with DSP and microcontroller interface standards. The device is operated with AVCC = 4.75 V to 5.25 V, DVCC = 2.7 V to 5.25 V, V- = -4.75 V to -5.25 V, V+ = 4.75 V to 5.25 V, and VPP = 210 V. REF_IN is buffered internally on the AD5535 and should be driven from a stable reference source. APPLICATIONS Optical micro-electromechanical systems (MEMS) Optical crosspoint switches Micropositioning applications using piezoelectric actuators Level setting in automotive test and measurement FUNCTIONAL BLOCK DIAGRAM DVCC RESET AVCC REF_IN VPP PGND V- V+ ANODE AD5535 CATHODE DAC R1 VOUT0 RF 14-BIT BUS DAC R1 DAC_GND DAC R1 AGND VOUT30 RF DAC R1 INTERFACE CONTROL LOGIC SCLK DIN VOUT31 RF 05068-001 DGND VOUT1 RF SYNC Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved. AD5535 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 12 Applications....................................................................................... 1 Serial Interface ............................................................................ 12 General Description ......................................................................... 1 Microprocessor Interfacing....................................................... 12 Functional Block Diagram .............................................................. 1 Applications..................................................................................... 14 Specifications..................................................................................... 3 MEMS Mirror Control Application......................................... 14 Timing Characteristics ................................................................ 5 IPC-221-Compliant Board Layout........................................... 14 Absolute Maximum Ratings............................................................ 6 Power Supply Sequencing and Decoupling Recommendations...................................................................... 15 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 9 Terminology .................................................................................... 11 Guidelines for Printed Circuit Board Layout ......................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16 Functional Description .................................................................. 12 DAC Section................................................................................ 12 REVISION HISTORY 8/05--Rev. 0 to Rev. A Changes to Table 3............................................................................ 6 Changes to Ordering Guide .......................................................... 16 5/05--Revision 0: Initial Version Rev. A | Page 2 of 16 AD5535 SPECIFICATIONS VPP = 210 V, V- = -5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; PGND = AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V; all outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted. Table 1. 1 Parameter DC PERFORMANCE 3 Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Zero-Code Voltage Output Offset Error Offset Drift Voltage Gain Gain Temperature Coefficient Channel-to-Channel Gain Match 4 Full-Scale Voltage Drift OUTPUT CHARACTERISTICS Output Voltage Range3 Output Impedance Resistive Load4, 5 Capacitive Load4 Short-Circuit Current DC Crosstalk4 DC Power Supply Rejection (PSRR), VPP AC CHARACTERISTICS4 Settling Time 1/4 to 3/4 Scale Step Min -1 14 0.1 0.5 1 -2 47.5 0.02 50 5 -5 Max +1 2.5 +2 52.5 +5 3 2.5 VPP - 10 50 1 200 0.7 3 70 30 65 10 10 10 3 1 LSB Step Slew Rate -3 dB Bandwidth Output Noise Spectral Density 0.1 Hz to 10 Hz Output Noise Voltage Digital-to-Analog Glitch Impulse Analog Crosstalk Digital Feedthrough VOLTAGE REFERENCE, REF_IN 6 Input Voltage Range4 Input Current TEMPERATURE MEASUREMENT DIODE4 Peak Inverse Voltage, PIV Forward Diode Drop, VF Forward Diode Current, IF VF Temperature Coefficient, TC A Grade 2 Typ Unit Bits % of FSR LSB V V mV/C V/V ppm/C % ppm/C 4.5 1 10 13 1 Guaranteed monotonic V M pF mA LSB dB s s s s V/s V/s kHz V/Hz mV p-p nV-s V-s nV-s 5 Conditions/Comments No load 200 pF load No load 200 pF load No load 200 pF load Measured at 10 kHz 1 LSB change around major carry AVCC must exceed REF_IN by 1.15 V min 1 0.65 4.096 1.25 V A 5 0.8 100 V V A mV/C -2.20 Rev. A | Page 3 of 16 Cathode to anode IF = 100 A, anode to cathode Anode to cathode Anode to cathode AD5535 1 Parameter DIGITAL INPUTS4 Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and SYNC Only) Input Capacitance POWER SUPPLY VOLTAGES7 VPP V- V+ AVCC DVCC POWER SUPPLY CURRENTS 7 IPP I- I+ AICC DICC POWER DISSIPATION7 Min A Grade 2 Typ 5 Max Unit 10 0.8 10 A V V mV pF 225 -4.75 5.25 5.25 5.25 V V V V V 100 3.5 1 18 0.5 A/channel mA mA mA mA mW 2.0 200 (50 x REF_IN) + 10 -5.25 4.75 4.75 2.7 75 2.3 0.5 15 0.25 594 1 Conditions/Comments See the Terminology section. A Grade temperature range: -10C to +85C; typical = +25C. 3 Linear output voltage range: +7 V to VPP - 10 V. 4 Guaranteed by design and characterization, not production tested. 5 Ensure that TJ max is not exceeded. See the Absolute Maximum Ratings section. 6 Reference input determines output voltage range. Using a 4.096 V reference (REF198) gives an output voltage range of 2.50 V to 200 V. The output range is programmable via the reference input. The full-scale output range is programmable from 50 V to 200 V. The linear output voltage range is restricted from 7 V to VPP - 10 V. 7 Outputs unloaded. 2 Rev. A | Page 4 of 16 AD5535 TIMING CHARACTERISTICS VPP = 210 V, V- = -5 V, V+ = +5 V; AVCC = 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 4.096 V. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1, 2 , 3 fUPDATE fCLKIN t1 t2 t3 t4 t5 t6 t7 t8 t9 A Grade 1.2 30 13 13 15 50 10 10 5 200 20 Unit MHz max MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments Channel Update Rate SCLK Frequency SCLK High Pulse Width SCLK Low Pulse Width SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time SYNC High Time DIN Setup Time DIN Hold Time 19th SCLK Falling Edge to SYNC Falling Edge for Next Write RESET Pulse Width 1 See Figure 2. Guaranteed by design and characterization, not production tested. 3 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2. 2 t1 SCLK 1 2 t3 5 4 16 17 18 1 19 t2 t5 SYNC 3 t4 t6 t8 t7 DIN MSB LSB 05068-002 RESET t9 Figure 2. Serial Interface Timing Diagram Rev. A | Page 5 of 16 AD5535 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 3. Parameter VPP to AGND V- to AGND V+ to AGND AVCC to AGND, DAC_GND DVCC to DGND Digital Inputs to DGND REF_IN to AGND, DAC_GND VOUT (0 to 31) to AGND Anode/Cathode to AGND, DAC_GND AGND to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 124-Lead CSP_BGA Package, JA Thermal Impedance Lead Temperature Soldering Vapor Phase (60 sec) Infrared (15 sec) Reflow Soldering (Pb-free) Peak Temperature Time at Peak Temperature ESD (Human Body Model) Rating 0.3 V to 250 V +0.3 V to -6 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to +7 V -0.3 V to DVCC + 0.3 V -0.3 V to AVCC + 0.3 V V- to VPP -0.3 V to +7 V -0.3 V to +0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Transient currents up to 100 mA do not cause SCR latch-up. This device is an integrated high voltage circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. -10C to +85C -65C to +150C 150C 40C/W 215C 220C 260(0/-5)C 10 sec to 40 sec 450 V ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 16 AD5535 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 6 7 8 9 10 11 12 13 14 A B B C C D D E F G E F G H H J J K K L L M N M N P P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 05068-003 1 2 3 4 A Figure 3. Pin Configuration Table 4. 124-Lead CSP-BGA Ball Configuration CSP_BGA No. A1 A2 A4 A6 A8 A10 A12 A14 B1 B3 B5 B7 B9 B11 B13 C2 C12 Ball Name NC VOUT1 VOUT7 VOUT11 VOUT16 VOUT20 VOUT25 NC VOUT0 VOUT4 VOUT9 VOUT13 VOUT17 VOUT21 VOUT26 VOUT3 VOUT22 CSP_BGA No. C14 D1 D13 E2 E4 E6 E8 E10 E12 E14 F3 F5 F7 F9 F13 G14 H1 Ball Name VOUT29 VOUT2 VOUT23 VOUT5 VOUT8 VOUT12 VOUT15 VOUT19 VOUT24 VOUT31 VOUT6 VOUT10 VOUT14 VOUT18 VOUT30 VOUT28 VPP CSP_BGA No. H2 H4 to H11 H13 J3 to J12 K1 K2 K3 to K14 L1 L2 L3 to L13 L14 M1 M2 M3 to M12 M13 M14 N1 Rev. A | Page 7 of 16 Ball Name VPP AGND VOUT27 AGND V+ V+ AGND V- V- AGND DAC_GND AGND AGND AGND AVCC AVCC PGND CSP_BGA No. N2 N3 N4 N5 to N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 to P13 P14 Ball Name PGND CATHODE ANODE AGND NC REF_IN DAC_GND RESET DVCC DGND TEST DIN SCLK SYNC AGND NC AD5535 Table 5. Pin Function Descriptions Mnemonic AGND AVCC VPP V+ V- PGND DGND DVCC DAC_GND REF_IN VOUT0 to VOUT31 ANODE CATHODE SYNC SCLK 1 DIN1 TEST RESET1 NC 1 Description Analog GND Pins. Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. Output Amplifier High Voltage Supply. Voltage range from (REF_IN x 50) + 10 V to 225 V. V+ Amplifier Supply Pins. Voltage range from 4.75 V to 5.25 V. V- Amplifier Supply Pins. Voltage range from -4.75 V to -5.25 V. Output Amplifier Ground Reference Pins. Digital GND Pins. Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. Reference GND Supply for All DACs. Reference Voltage for Channel 0 to Channel 31. Reference input range is 1 V to 4 V and can be used to program the fullscale output voltage from 50 V to 200 V. Analog Output Voltages from the 32 Channels. Anode of Internal Diode for Diode Temperature Measurement. Cathode of Internal Diode for Diode Temperature Measurement. Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is transferred in upon the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register upon the falling edge of SCLK. This operates at clock speeds of up to 30 MHz. Serial Data Input. Data must be valid upon the falling edge of SCLK. Allows the same data to be simultaneously loaded to all channels of the AD5535. This pin is used for calibration purposes when loading zero scale and full scale to all channels. To invoke this feature, bring the TEST pin high. In normal operation, TEST should be tied low. Active Low Input. This pin can also be used to reset the complete device to its power-on reset conditions. Zero code is loaded to the DACs. No connect pins. The user should not connect any signals to these pins. Internal pull-up device on logic input; therefore, it can be left floating and defaults to a logic high condition. Rev. A | Page 8 of 16 AD5535 TYPICAL PERFORMANCE CHARACTERISTICS 16 1.00 VPP = 60V V- = -5V V+ = AVCC = +5V REF_IN = 1V TA = 25C DNL ERROR (LSB) 0.50 4 0 -4 0.25 0 -0.25 -8 -0.50 -12 -0.75 05068-018 -16 0 2048 4096 6144 8192 -1.00 0 10240 12288 14336 16384 2048 4096 6144 INPUT CODE Figure 4. Integral Linearity with Full-Scale Range = 50 V 1.00 VPP = 60V V- = -5V V+ = AVCC = +5V REF_IN = 1V TA = 25C 0 -0.25 0 -0.75 05068-019 -0.75 4096 6144 8192 CHANNEL 2 -0.25 -0.50 -1.00 AMP 0.25 -0.50 2048 DAC 0.50 0.25 0 CHANNEL 1 10k DNL ERROR (LSB) 0.50 CHANNEL 2 0.75 T CHANNEL 1 05068-008 0.75 DNL ERROR (LSB) 10240 12288 14336 16384 Figure 7. Differential Nonlinearity with Full-Scale Range = 200 V 1.00 -1.00 10240 12288 14336 16384 0CH1 5V 2048 INPUT CODE Figure 5. Differential Nonlinearity with Full-Scale Range = 50 V CH2 5V M 500ns 4096 6144 8192 10240 12288CH1 1433621.6V 16384 INPUT CODE Figure 8. Short-Circuit Current Limit Timing 16 1.00 T VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V TA = 25C 12 0.75 0.50 DNL ERROR (LSB) 8 4 0 -4 20 -0.25 -0.50 1 -12 -0.75 -16 0 2048 4096 6144 8192 10240 12288 14336 16384 INPUT CODE Figure 6. Integral Linearity with Full-Scale Range = 200 V CHANNEL 2 AREA 11Vs 0.25 -8 05068-020 INL ERROR (LSB) 8192 INPUT CODE VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V VOUT = 100V TA = 25C CHANNEL 1: CHANNEL OUTPUT SLEW CHANNEL 2: AC CROSSTALK 05068-009 INL ERROR (LSB) 8 VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V TA = 25C 0.75 05068-021 12 -1.00 0CH1 50V 2048 200mV M 10s 4096 CH2 6144 8192 10240 12288 INPUT CODE CH116384 14336 Figure 9. Worst-Case Adjacent Channel Crosstalk Rev. A | Page 9 of 16 AD5535 0.04 140 VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V TA = 25C 0.03 0.02 DC CROSSTALK (V) 100 80 60 -4 -0.01 -0.02 -3 -2 -1 0 1 VICTIM CHANNEL = 31 VOUT31 = MIDSCALE FULL-SCALE TRANSITION ON OTHER CHANNELS IN SEQUENCE. -0.03 -0.04 2 0 5 10 SOURCE/SINK CURRENT (mA) 0pF 140 OUTPUT VOLTAGE (V) 10.5 10.0 9.5 9.0 100pF 120 100 200pF 80 VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V TA = 25C 1/4 FULL-SCALE TO 3/4 FULL-SCALE STEP 60 40 05068-028 8.5 10 20 30 40 50 60 70 20 0 80 0 0.02 0.04 TEMPERATURE (C) 0.10 1.00 VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V 0.75 DNL ERROR (LSB) 0.50 -1.2 -1.3 0.25 20 -0.25 -0.50 -1.4 05068-029 GAIN ERROR (%) 0.08 Figure 14. Settling Time vs. Capacitive Load -1.0 -1.5 -10 0.06 TIME (ms) Figure 11. Offset Error vs. Temperature -1.1 30 160 11.0 0 25 180 VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V 8.0 -10 20 Figure 13. Cumulative DC Crosstalk Effects on a Single-Channel Output, Switching All Other Channels in Sequence 12.0 OFFSET ERROR (mV) 15 CHANNEL NUMBER Figure 10. Output Amplifier Source and Sink Capability 11.5 05068-025 0 -5 0 05068-026 20 VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V VOUT = 70V TA = 25C 0.01 0 10 20 30 40 50 60 70 80 -0.75 -1.00 VPP = 210V V- = -5V V+ = AVCC = +5.25V REF_IN = 4.096V VOUT = 100V TA = 25C 0CH2 200mV 2048 4096 TEMPERATURE (C) Figure 12. Gain Error vs. Temperature CHANNEL 2 6.88mV p-p CHANNEL 2 RMS 1.02mV 1s CH114336 300mV 6144 M8192 10240 12288 16384 INPUT CODE Figure 15. Wideband Noise Rev. A | Page 10 of 16 05068-027 40 05068-022 OUTPUT VOLTAGE (V) 120 AD5535 TERMINOLOGY Integral Nonlinearity (INL) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale range. Differential Nonlinearity (DNL) The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of 1 LSB maximum ensures monotonicity. DC Crosstalk The dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and the output change of all other DACs. It is expressed in LSB. Output Voltage Settling Time The time taken from when the last data bit is clocked into the DAC until the output has settled to within 0.5 LSB of its final value. Measured for a step change of 1/4 to 3/4 full scale. Zero-Code Voltage A measure of the output voltage present at the device output with all 0s loaded to the DAC. It includes the offset of the DAC and the output amplifier and is expressed in V. Digital-to-Analog Glitch Impulse The area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-s when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). Offset Error Calculated by taking two points in the linear region of the transfer function, drawing a line through these points, and extrapolating back to the y-axis. It is expressed in V. Voltage Gain Calculated from the change in output voltage for a change in code, multiplied by 16,384, and divided by the REF_IN voltage. This is calculated between two points in the linear section of the transfer function. Gain Error A measure of the output error with all 1s loaded to the DAC, and the difference between the ideal and actual analog output range. Ideally, the output should be 50 x REF_IN. It is expressed as a percentage of full-scale range. DC Power Supply Rejection Ratio (PSRR) A measure of the change in analog output for a change in VPP supply voltage. It is expressed in dB, and VPP is varied 5%. Analog Crosstalk The area of the glitch transferred to the output (VOUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-s. Digital Feedthrough A measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to (SYNC is high). It is specified in nV-s and measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s and vice versa. Output Noise Spectral Density A measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per Hz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/Hz. Rev. A | Page 11 of 16 AD5535 FUNCTIONAL DESCRIPTION At power-on, all the DAC registers are loaded with 0s. DAC SECTION The architecture of each DAC channel consists of a resistor string DAC, followed by an output buffer amplifier operating with a nominal gain of 50. The voltage at the REF_IN pin provides the reference voltage for the corresponding DAC. The input coding to the DAC is straight binary, and the ideal DAC output voltage is given by VOUT = 50 x VREF _ IN x D A4 to A0 Bits These bits can address any one of the 32 channels. A4 is the MSB of the address; A0 is the LSB. DB13 to DB0 Bits These bits are used to write a 14-bit word into the addressed DAC register. Figure 2 is the timing diagram for a serial write to the AD5535. The serial interface works with both a continuous and a discontinuous serial clock. The first falling edge of SYNC resets the serial clock counter to ensure that the correct number of bits are shifted into the serial shift register. Any further edges on SYNC are ignored until the correct number of bits are shifted in. Once 19 bits have been shifted in, the SCLK is ignored. For another serial transfer to take place, the counter must be reset by the falling edge of SYNC. The user must allow 200 ns (minimum) between successive writes. LSB MSB A4 A3 A2 A1 A0 DB13-DB0 05068-010 The AD5535 consists of a 32 channel, 14-bit DAC with 200 V high voltage amplifiers in a single 15 mm x 15 mm CSP_BGA package. The output voltage range is programmable via the REF_IN pin. The output range is 0 V to 50 V when REF_IN = 1 V, and 0 V to 200 V when REF_IN = 4 V. Communication to the device is through a serial interface operating at clock rates of up to 30 MHz, which is compatible with DSP and microcontroller interface standards. A 5-bit address and a 14-bit data-word are loaded into the AD5535 input register via the serial interface. The channel address is decoded, and the data-word is converted into an analog output voltage for this channel. Figure 16. Serial Data Format MICROPROCESSOR INTERFACING 214 AD5535-to-ADSP-21xx Interface where D is the decimal equivalent (0 to 16,383) of the binary code, which is loaded to the DAC register. The output buffer amplifier is specified to drive a load of 1 M and 200 pF. The linear output voltage range for the output amplifier is from 7 V to VPP - 10 V. The amplifier output bandwidth is typically 5 kHz, and is capable of sourcing 700 A and sinking 2.8 mA. Settling time for a 1/4 to 3/4 full-scale step change is typically 30 s with no load and 65 s with a 200 pF load. RESET FUNCTION The reset function on the AD5535 can be used to reset all nodes on the device to their power-on reset condition. All the DACs are loaded with 0s, and all registers are cleared. The reset function is implemented by taking the RESET pin low. SERIAL INTERFACE The serial interface is controlled by three pins: * SYNC is the frame synchronization pin for the serial interface. * SCLK is the serial clock input. This pin operates at clock speeds of up to 30 MHz. * DIN is the serial data input. Data must be valid upon the falling edge of SCLK. The ADSP-21xx family of DSPs is easily interfaced to the AD5535 without the need for extra logic. A data transfer is initiated by writing a word to the TX register after SPORT is enabled. In a write sequence, data is clocked out upon each rising edge of the DSP's serial clock and clocked into the AD5535 upon the falling edge of its SCLK. The easiest way to provide the 19-bit data-word required by the AD5535 is to transmit two 10-bit data-words from the ADSP-21xx. Ensure that the data is positioned correctly in the TX register so that the first 19 bits transmitted contain valid data. Set up the SPORT control register as shown in Table 6. Table 6. Name TFSW INVTFS DTYPE ISCLK TFSR ITFS SLEN To update a single DAC channel, a 19-bit data-word is written to the AD5535 input register. Rev. A | Page 12 of 16 Value 1 1 00 1 1 1 1001 Description Alternate framing Active low frame signal Right justify data Internal serial clock Frame every word Internal framing signal 10-bit data-word AD5535 Figure 17 shows the connection diagram. AD5535-to-PIC16C6x/7x Interface DIN SYNC SCLK DT TFS 05068-011 SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 17. AD5535-to-ADSP-2101/ADSP-2103 Interface AD5535-to-MC68HC11 Interface The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)--see the 68HC11 User Manual. SCK of the MC68HC11 drives the SCLK of the AD5535 and the MOSI output drives the serial data line (DIN) of the AD5535. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5535, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. The MC68HC11 transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. See Figure 18. AD5535* MC68HC11* DIN SYNC SCK MOSI PC7 *ADDITIONAL PINS OMITTED FOR CLARITY 05068-012 SCLK The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example, I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5535. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. RA1 must be pulled low to start a transfer. It must be brought high and pulled low again before any further write cycles can take place. Figure 19 shows the connection diagram. AD5535* PIC16C6x/7x* SCLK DIN SYNC SCK/RC3 SDI/RC4 RA1 05068-013 ADSP-2101/ ADSP-2103* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 19. AD5535-to-PIC16C6x/7x Interface AD5535-to-8051 Interface The AD5535 requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data exits the 8051 through RxD, and a shift clock is output upon TxD. The SYNC signal is derived from a port line (P1.1). Figure 20 shows how the 8051 is connected to the AD5535. Because the AD5535 shifts data out upon the rising edge of the shift clock and latches data in upon the falling edge, the shift clock must be inverted. Note also that the AD5535 requires its data with the MSB first. Because the 8051 outputs the LSB first, the transmit routine must take this into account. AD5535* Figure 18. AD5535-to-MC68HC11 Interface 8051* SCLK TxD DIN RxD SYNC P1.1 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. AD5535-to-8051 Interface Rev. A | Page 13 of 16 05068-014 AD5535* AD5535 APPLICATIONS MEMS MIRROR CONTROL APPLICATION REF198 +5V +210V (4.096V) OUTPUT RANGE 0V TO 200V VPP REF_IN V+ The AD5535 is targeted to all optical switching control systems based on MEMS technology. The AD5535 is a 32-channel, 14-bit DAC with integrated high voltage amplifiers. The output amplifiers are capable of generating an output range of 0 V to 200 V when using a 4 V reference. The full-scale output voltage is programmable from 50 V to 200 V using reference voltages from 1 V to 4 V. Each amplifier can output 700 A and directly drives the control actuators, which determine the position of MEMS mirrors in optical switch applications. 14-BIT DAC VOUT0 ACTUATORS FOR MEMS MIRROR VOUT31 ARRAY 14-BIT DAC SENSOR + 4-TO-1 MUX (ADG739) OR 32-TO-1 MUX (ADG732) AD5535 8-CHANNEL ADC (AD7856) OR SINGLECHANNEL ADC (AD7671) V- 05068-015 -5V ADSP-21065L The AD5535 is generally used in a closed-loop feedback system, as shown in Figure 21, with a high resolution ADC and DSP. The exact position of each mirror is measured using capacitive sensors. The sensor outputs are multiplexed using an ADG739 4:1 multiplexer to an 8-channel, 14-bit ADC (AD7856). An alternative solution is to multiplex using a 32-to-1 multiplexer (ADG732) into a single-channel ADC (AD7671). The control loop is driven by an ADSP-21065L, a 32-bit SHARC(R) DSP with an SPI-compatible SPORT interface. With 14-bit monotonic behavior and 0 V to 200 V output range, coupled with its fast serial interface, the AD5535 is ideally suited for controlling a cluster of MEMS-based mirrors. Figure 21. AD5535 in a MEMS-Based Optical Switch IPC-221-COMPLIANT BOARD LAYOUT The diagram in Figure 22 is a typical 2-layer printed circuit board layout for the AD5535 that complies with the specifications outlined in IPC-221. No signals should be connected to the four corner balls labeled as original no connects. Balls labeled as additional no connects should be connected to AGND. The routing shown in Figure 22 shows the feasibility of connecting to the high voltage balls while complying with the spacing requirements of IPC-221. Figure 22 also shows the physical distances that are available. A1 BALL PAD CORNER 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C D ORIGINAL NO CONNECTS E F G ADDITIONAL NO CONNECTS H J 1.414mm m m 5 5 D 40 AD 40 A = = R R E E m C m C A 0 0 PA 25 S m SP 25 0 10 A B DETAIL A 250m RAD SPACE = 433m 100m K 1 100m M N SPACE = 433m P 250m RAD 05068-016 1 2mm SPACE = 433m L 1 Figure 22. Layout Guidelines to Comply with IPC-221 Rev. A | Page 14 of 16 AD5535 POWER SUPPLY SEQUENCING AND DECOUPLING RECOMMENDATIONS The diagram in Figure 23 shows the recommended decoupling and power supply protection for the AD5535. On the AD5535, it is recommended to tie all grounds together as close to the device as possible. If the number of supplies must be reduced, all supplies should be brought back separately and a provision should be made on the board via a link option to drive the AVCC and V+ from the same supply. All power supplies should be adequately decoupled with 10 F tantalum and 0.1 F ceramic capacitors. Note that the capacitors on the VPP supply must be rated at greater than 210 V. To overcome issues associated with power supply sequencing when using high voltage supplies, the use of protection diodes as indicated in Figure 23 is recommended. V- = -5V V+ = +5V VPP = +210V 10F 10F 0.1F 0.1F SCHOTTKY DIODE MANUFACTURER: ITT HIGH VOLTAGE DIODE MANUFACTURER: GS SD103C PGND RS1G V- V+ 10F VPP AVCC 10F AVCC = +5V 0.1F AD5535 DGND 10F DVCC = +5V 0.1F 05068-017 DVCC A microstrip technique is by far the best, but it is not always possible to use with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, and signals are placed on the solder side. Multilayer printed circuit boards with dedicated ground, power, and tracking layers offer the optimum solution in terms of obtaining analog performance, but at increased manufacturing costs. 0.1F AGND DACGND Use as large a trace as possible for the supply lines of the device to provide low impedance paths and reduce the effects of glitches on the power supply line. Components, such as clocks with fastswitching signals, should be shielded with digital ground to avoid radiating noise to other sections of the board. Clock signals should never be run near the analog inputs of the device. Avoid crossovers of digital and analog signals. Traces for analog inputs should be kept as wide and short as possible and should be shielded with analog ground if possible. Traces on opposite sides of a 2-layer printed circuit board should run at right angles to each other to reduce the effects of feedthrough through the board. Figure 23. Recommended Power Supply Sequencing and Decoupling GUIDELINES FOR PRINTED CIRCUIT BOARD LAYOUT Printed circuit boards should be designed such that the analog and digital sections are separated and confined to designated analog and digital sections of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally found to be the best for ground planes because it optimizes shielding of sensitive signal lines. Digital and analog ground planes should be joined only in one place, at the AGND and DGND pins of the high resolution converter. Data and address buses on the board should be buffered or latched to isolate the high frequency bus of the processor from the bus of the high resolution converters. These act as a faraday shield and increase the signal-to-noise performance of the converters by reducing the amount of high frequency digital coupling. Avoid running digital lines under the device because they couple noise onto the die. The ground plane should be allowed to run under the IC to avoid noise coupling. Good decoupling is vitally important when using high resolution converters. All analog supplies should be decoupled with 10 F tantalum in parallel with 0.1 F ceramic capacitors to analog ground. To achieve the best from the decoupling components, these should be placed as close to the device as possible, ideally right up against the IC or the IC socket. The main aim of a bypassing element is to maximize the charge stored in the bypass loop while simultaneously minimizing the inductance of this loop. Inductance in the loop acts as an impedance to high frequency transients and results in power supply spiking. By keeping the decoupling as close to the device as possible, the loop area is kept as small as possible, thereby reducing the possibility of power supply spikes. Digital supplies of high resolution converters should be decoupled with 10 F tantalum and 0.1 F ceramic to the digital ground plane. The amplifiers' VDD and VSS supplies should be decoupled with 10 F and 0.1 F to AGND. All logic chips should be decoupled with 0.1 F to digital ground to decouple high frequency effects associated with digital circuitry. Rev. A | Page 15 of 16 AD5535 OUTLINE DIMENSIONS A1 CORNER INDEX AREA 15.00 BSC SQ 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P TOP VIEW 1.00 BSC BOTTOM VIEW DETAIL A 1.70 MAX DETAIL A *1.25 MAX 0.85 MIN *0.41 0.36 0.31 *0.46 NOM SEATING PLANE 0.12 NOM COPLANARITY BALL DIAMETER *COMPLIANT WITH JEDEC STANDARDS MO-192-AAE-1 WITH EXCEPTION TO DIMENSIONS INDICATED BY AN ASTERISK. NOMINAL BALL SIZE IS REDUCED FROM 0.60mm TO 0.46mm. Figure 24. 124-Lead Chip Scale Package Ball Grid Array [CSP_BGA] (BC-124-2) Dimensions shown in millimeters ORDERING GUIDE Model AD5535ABC AD5535ABCZ 1 EVAL-AD5535EB 1 Function 32 DACs 32 DACs Output Voltage Span 0 V to 200 V maximum 0 V to 200 V maximum Temperature Range -10C to +85C -10C to +85C Package Description 124-Lead CSP_BGA 124-Lead CSP_BGA Evaluation Board Package Option BC-124-2 BC-124-2 Z = Pb-free part. (c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05068-0-8/05(A) T T Rev. A | Page 16 of 16