PROFET® BTS 640 S2
Semiconductor Group Page 1 of 15 2003-Oct-01
Smart Sense High-Side
Power Switch
Features
• Short circuit protection
• Current limitation
• Proportional load current sense
• CMOS compatible input
• Open drain diagnostic output
• Fast demagnetization of inductive loads
• Undervoltage and overvoltage shutdown with
auto-restart and hysteresis
• Overload protection
• Thermal shutdown
• Overvoltage protection including load dump (with
external GND-resistor)
• Reverse battery protection (with external GND-resistor)
• Loss of ground and loss of Vbb protection
• Electrostatic discharge (ESD) protection
Application
• µC compatible power switch with diagnostic feedback for 12 V and 24 V DC grounded loads
• All types of resistive, inductive and capacitve loads
• Replaces electromechanical relays, fuses and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic
feedback, proportional sense of load current, monolithically integrated in Smart SIPMOS technology.
Providing embedded protective functions.
Block Diagram
IN
ST ESD Logic
Voltage
sensor
Voltage
source
Charge pump
Level shifter
Temperature
sensor
Rectifier
Limit for
unclamped
ind. loads
Gate
protection
Current
limit
3
1
Signal GND
GND
2
VLogic
Overvoltage
protection
+ Vbb
PROFET
OUT
4
6, 7
Load GND
Load
GND
RO
Current
Sense
Output
Voltage
detection
RIS
IS
5
IIS
IL
Product Summary
Operating voltage V
bb(on) 5.0 ... 34 V
On-state resistance RON 30 mΩ
Load current (ISO) IL(ISO) 12.6 A
Current limitation IL(SCr) 24 A
Package
TO220-7-11 TO263-7-2 TO220-7-12
1 1 1
Standard (staggered) SMD Straight
BTS 640 S2
Semiconductor Group Page 2 2003-Oct-01
Pin Symbol Function
1 ST Diagnostic feedback: open drain, invers to input level
2 GND Logic ground
3 IN Input, activates the power switch in case of logical high signal
4 Vbb Positive power supply voltage, the tab is shorted to this pin
5 IS Sense current output, proportional to the load current, zero in
the case of current limitation of load current
6 & 7 OUT
(Load, L) Output, protected high-side power output to the load.
Both output pins have to be connected in parallel for operation
according this spec (e.g. kILIS).
Design the wiring for the max. short circuit current
Maximum Ratings at Tj = 25 °C unless otherwise specified
Parameter Symbol Values Unit
Supply voltage (overvoltage protection see page 4) Vbb 43 V
Supply voltage for full short circuit protection
Tj Start=-40 ...+150°C Vbb 34 V
Load dump protection1) VLoadDump = VA + Vs, VA = 13.5V
RI2)= 2 Ω, RL= 1 Ω, td= 200 ms, IN= low or high VLoad dump3) 60 V
Load current (Short circuit current, see page 5) IL self-limited A
Operating temperature range
Storage temperature range Tj
Tstg -40 ...+150
-55 ...+150 °C
Power dissipation (DC), TC ≤ 25 °C Ptot 85 W
Inductive load switch-off energy dissipation, single pulse
Vbb = 12V, Tj,start = 150°C, TC = 150°C const.
IL = 12.6 A, ZL = 4,2 mH, 0 Ω:
IL = 4 A, ZL = 330 mH, 0 Ω:
EAS
EAS 0,41
3,5 J
Electrostatic discharge capability (ESD) IN:
(Human Body Model) ST, IS:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
VESD 1.0
4.0
8.0
kV
Input voltage (DC) VIN -10 ... +16 V
Current through input pin (DC)
Current through status pin (DC)
Current through current sense pin (DC)
see internal circuit diagrams page 8
IIN
IST
IIS
±2.0
±5.0
±14
mA
1) Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω
resistor in the GND connection is recommended).
2) RI = internal resistance of the load dump test pulse generator
3) VLoad dump is setup without the DUT connected to the generator according to ISO 7637-1 and DIN 40839
BTS 640 S2
Semiconductor Group Page 3 2003-Oct-01
Thermal Characteristics
Parameter and Conditions Symbol Values Unit
min typ max
Thermal re sistance chip - case: RthJC -- -- 1.47 K/W
junction - ambient (free air): RthJA -- -- 75
SMD version, device on PCB4): -- 33 --
4) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air.
Electrical Characteristics
Parameter and Conditions Symbol Values Unit
at Tj = 25 °C, Vbb = 12 V unless otherwise specified min typ max
Load Switching Capabilities and Characteristics
On-state resistance (pin 4 to 6&7)
IL = 5 A Tj=25 °C:
Tj=150 °C:
RON
--
27
54 30
60 mΩ
Output voltage drop limitation at small load
currents (pin 4 to 6&7), see page 14
IL = 0.5 A Tj =-40...+150°C:
VON(NL)
--
50 -- mV
Nominal load current, ISO Norm (pin 4 to 6&7)
VON = 0.5 V, TC = 85 °C
IL(ISO)
11.4
12.6 -- A
Nominal load current, device on PCB4)
TA = 85 °C, Tj ≤ 150 °C VON ≤ 0.5 V,
IL(NOM)
4.0
4.5 -- A
Output current (pin 6&7) while GND disconnected
or GND pulled up, Vbb=30 V, VIN= 0, see diagram page
9; not subject to production test, specified by design
IL(GNDhigh) -- -- 8 mA
Turn-on time IN to 90% VOUT:
Turn-off time IN to 10% VOUT:
RL = 12 Ω, Tj =-40...+150°C
ton
toff 25
25 70
80 150
200 µs
Slew rate on
10 to 30% VOUT, RL = 12 Ω, Tj =-40...+150°C dV /dton 0.1 -- 1 V/µs
Slew rate off
70 to 40% VOUT, RL = 12 Ω, Tj =-40...+150°C -dV/dtoff 0.1 -- 1 V/µs
BTS 640 S2
Parameter and Conditions Symbol Values Unit
at Tj = 25 °C, Vbb = 12 V unless otherwise specified min typ max
Semiconductor Group Page 4 2003-Oct-01
Operating Parameters
Operating voltage 5) Tj =-40...+150°C: Vbb(on) 5.0 -- 34 V
Undervoltage shutdown Tj =-40...+150°C: Vbb(under) 3.2 -- 5.0 V
Undervoltage restart Tj =-40...+25°C:
Tj =+150°C: Vbb(u rst) -- 4.5 5.5
6.0 V
Undervoltage restart of charge pump
see diagram page 13 Tj =-40...+25°C:
Tj =25...150°C:
Vbb(ucp)
--
--
4.7
-- 6.5
7.0 V
Undervoltage hysteresis
∆Vbb(under) = Vbb(u rst) - Vbb(under) ∆Vbb(under) -- 0.5 -- V
Overvoltage shutdown Tj =-40...+150°C: Vbb(over) 34 -- 43 V
Overvoltage restart Tj =-40...+150°C: Vbb(o rst) 33 -- -- V
Overvoltage hysteresis Tj =-40...+150°C: ∆Vbb(over) -- 1 -- V
Overvoltage protection6) Tj =-40°C:
Ibb=40 mA Tj =+25...+150°C Vbb(AZ) 41
43 --
47 --
52 V
Standby current (pin 4)
VIN=0 T
j=-40...+25°C:
T
j= 150°C:
Ibb(off)
--
--
4
12 15
25 µA
Off state output current (included in Ibb(off))
VIN=0, Tj =-40...+150°C:
IL(off) -- -- 10 µA
Operating current (Pin 2)7), VIN=5 V IGND -- 1.2 3 mA
5) At supply voltage increase up to Vbb= 4.7 V typ without charge pump, VOUT ≈Vbb - 2 V
6) Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 Ω
resistor in the GND connection is recommended). See also VON(CL) in table of protection functions and
circuit diagram page 9.
7) Add IST, if IST > 0, add IIN, if VIN>5.5 V
BTS 640 S2
Parameter and Conditions Symbol Values Unit
at Tj = 25 °C, Vbb = 12 V unless otherwise specified min typ max
Semiconductor Group Page 5 2003-Oct-01
Protection Functions8)
Initial peak short circuit current limit (pin 4 to 6&7) IL(SCp)
Tj =-40°C:
Tj =25°C:
Tj =+150°C:
48
40
31
56
50
37
65
58
45
A
Repetitive short circuit shutdown current limit IL(SCr)
Tj = Tjt (see timing diagrams, page 12) -- 24 -- A
Output clamp (inductive load switch off)
at VOUT = Vbb - VON(CL); IL= 40 mA, Tj =-40°C:
Tj =+25..+150°C:
VON(CL)
41
43
--
47 --
52 V
Thermal overload trip temperature Tjt 150 -- -- °C
Thermal hysteresis
∆
Tjt -- 10 -- K
Reverse battery (pin 4 to 2) 9) -Vbb -- -- 32 V
Reverse battery voltage drop (Vout > Vbb)
IL = -5 A Tj=150 °C:
-VON(rev)
--
600 -- mV
Diagnostic Characteristics
Current sense ratio10), static on-condition,
VIS = 0...5 V, Vbb(on) = 6.511)...27V,
kILIS = IL / IIS Tj = -40°C, IL = 5 A:
kILIS
4550
5000 6000
Tj= -40°C, IL= 0.5 A: 3300 5000 8000
Tj= 25...+150°C, IL= 5 A:
, Tj= 25...+150°C, IL = 0.5 A: 4550
4000 5000
5000
5550
6500
Current sense output voltage limitation
Tj = -40 ...+150°C IIS = 0, IL = 5 A:
VIS(lim)
5.4
6.1 6.9 V
Current sense leakage/offset current
Tj = -40 ...+150°C VIN=0, VIS = 0, IL = 0:
IIS(LL)
0
-- 1µA
VIN=5 V, VIS = 0, IL = 0: IIS(LH) 0 -- 15
VIN=5 V, VIS = 0, VOUT = 0 (short circuit): IIS(SH)12 ) 0 -- 10
8) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
9) Requires 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal
operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature
protection is not active during reverse current operation! Input and Status currents have to be limited (see
max. ratings page 2 and circuit page 9).
10) This range for the current sense ratio refers to all devices. The accuracy of the kILIS can be raised at least by
a factor of two by matching the value of kILIS for every single device.
In the case of current limitation the sense current IIS is zero and the diagnostic feedback potential VST is
High. See figure 2b, page 11.
11) Valid if Vbb(u rst) was exceeded before.
12) not subject to production test, specified by design
BTS 640 S2
Parameter and Conditions Symbol Values Unit
at Tj = 25 °C, Vbb = 12 V unless otherwise specified min typ max
Semiconductor Group Page 6 2003-Oct-01
Current sense settling time to IIS static±10% after
positive input slope13) , IL = 0 5 A,
Tj= -40...+150°C
tson(IS)
--
-- 300 µs
Current sense settling time to 10% of IIS static after
negative input slope13) , IL = 5 0 A ,
Tj= -40...+150°C
tsoff(IS)
--
30 100 µs
Current sense rise time (60% to 90%) after change
of load current13) , IL = 2.5 5 A
tslc(IS)
--
10 -- µs
Open load detection voltage14) (off-condition)
Tj=-40..150°C: VOUT(OL) 2 3 4V
Internal output pull down
(pin 6 to 2), VOUT=5 V, Tj=-40..150°C
RO
5
15 40 kΩ
Input and Status Feedback15)
Input resistance
see circuit page 8 RI 3,0 4,5 7,0 kΩ
Input turn-on threshold voltage Tj =-40..+150°C:VIN(T+) -- -- 3.5 V
Input turn-off threshold voltage Tj =-40..+150°C:VIN(T-) 1.5 -- -- V
Input threshold hysteresis ∆ VIN(T) -- 0.5 -- V
Off state input current (pin 3), VIN = 0.4 V
Tj =-40..+150°C
IIN(off)
1
-- 50 µA
On state input current (pin 3), VIN = 5 V
Tj =-40..+150°C
IIN(on)
20
50 90 µA
Delay time for status with open load
after Input neg. slope (see diagram page 13)
td(ST OL3)
--
400 -- µs
Status delay after positive input slope13)
T
j=-40 ... +150°C:
tdon(ST)
--
13 -- µs
Status delay after negative input slope13)
T
j=-40 ... +150°C:
tdoff(ST)
--
1 -- µs
Status output (open drain)
Zener lim it voltage T
j =-40...+150°C, IST = +1.6 mA:
ST low voltage Tj =-40...+25°C, IST = +1.6 mA:
T
j = +150°C, IST = +1.6 mA:
VST(high)
VST(low) 5.4
--
--
6.1
--
--
6.9
0.4
0.7
V
Status leakage current, VST = 5 V, Tj=25 ... +150°C: IST(high) -- -- 2 µA
13) not subject to production test, specified by design
14) External pull up resistor required for open load detection in off state.
15) If a ground resistor RGND is used, add the voltage drop across this resistor.
BTS 640 S2
Semiconductor Group Page 7 2003-Oct-01
Truth Table
Input Output Status Current
Sense
level level level IIS
Normal
operation L
H L
H H
L 0
nominal
Current-
limitation L
H L
H H
H 0
0
Short circuit to
GND L
H L
L16) H
H 0
0
Over-
temperature L
H L
L H
H 0
0
Short circuit to
Vbb L
H H
H L17)
L 0
<nominal 18)
Open load L
H L19)
H H (L20))
L 0
0
Undervoltage L
H L
L H
L 0
0
Overvoltage L
H L
L H
L 0
0
Negative output
voltage clamp L L H 0
L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit
H = "High" Level Status signal after the time delay shown in the diagrams (see fig 5. page 12...13)
16) The voltage drop over the power transistor is Vbb-VOUT>typ.3V. Under this condition the sense current IIS is
zero
17) An external short of output to Vbb, in the off state, causes an internal current from output to ground. If RGND
is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious.
18) Low ohmic short to Vbb may reduce the output current IL and therefore also the sense current IIS.
19) Power Transistor off, high impedance
20) with external resistor between pin 4 and pin 6&7
BTS 640 S2
Semiconductor Group Page 8 2003-Oct-01
Terms
PROFET
V
IS
ST
OUT
GND
bb
VST
VIN
IST
IIN
Vbb
Ibb
IGND
6
2
4
3
5
IN
VIS
IIS
VOUT
V
ON
IL
OUT
17
RGND
Input circuit (ESD protection)
IN
GND
I
R
ESD-ZD
I
I
I
The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended.
Status output
ST
GND
ESD-
ZD
+5V
RST(ON)
ESD-Zener diode: 6.1 V typ., max 5 mA;
RST(ON) < 440 Ω at 1.6 mA, The use of ESD zener
diodes as voltage clamp at DC conditions is not
recommended.
Current sense output
IS
GND
IS
R
IS
I
ESD-ZD
IS
V
ESD-Zener diode: 6.1 V typ., max 14 mA;
RIS = 1 kΩ nominal
Inductive and overvoltage output clamp
+ Vbb
OUT
GND PROFET
VZ
VON
VON clamped to 47 V typ.
BTS 640 S2
Semiconductor Group Page 9 2003-Oct-01
Overvoltage protection of logic part
+ Vbb
IS
ST
R
GND
GND
R
Signal GND
Logic
VZ2
IN
RI
VZ1
ST
IS
R
+ 5V
V
R
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RI= 4 kΩ typ,
RGND= 150 Ω, RST= 15 kΩ, RIS= 1 kΩ, RV= 15 kΩ,
Reverse battery protection
GND
Logic
IS
ST
R
IN
ST
IS
R
+ 5V
V
R
OUT
L
R
Power GND
GND
R
Signal GND
Power
Inverse
I
R
Vbb
-
Diode
Z1
V
The load RL is inverse on, temperature protection is
not active
RGND= 150 Ω, RI= 4 kΩ typ, RST≥ 500 Ω, RIS≥ 200 Ω,
RV≥ 500 Ω,
Open-load detection
OFF-state diagnostic condition: VOUT > 3 V typ.; IN low
Logic
ST
Out VOUT
Signal GND
REXT
RO
OFF
Vbb
GND disconnect
PROFET
V
ST
IS
OUT
GND
bb
Vbb
Ibb
6
2
4
3
5
IN
OUT
1
7
VIN V
ST V
IS V
GND
Any ki nd of load. In case of I nput =hi gh i s VOUT ≈ VIN - VIN(T+) .
Due to VGND >0, no VST = low signal av ai l abl e.
GND disconnect with GND pull up
PROFET
V
ST
IS
OUT
GND
bb
Vbb
6
2
4
3
5
IN
OUT
1
7
VIN VSTVIS VGND
Any kind of load. I f VGND > VIN - VIN(T+) device stays off
Due to VGND >0, no VST = low signal av ai l abl e.
Vbb disconnect with energized inductive
load
PROFET
V
ST
IS
OUT
GND
bb
Vbb
6
2
4
3
5
IN
OUT
1
7
high
Normal load current can be handled by the PROFET
itself.
BTS 640 S2
Semiconductor Group Page 10 2003-Oct-01
Vbb disconnect with charged external
inductive load
PROFET
V
ST
IS
OUT
GND
bb
6
2
4
3
5
IN
OUT
1
7
Vbb
high
D
RL
L
If other external induc tive loads L are connected t o the PROFET,
additional el em ents like D are necess ary.
Inductive Load switch-off energy
dissipation
PROFET
IN
ST
OUT
GND
Vbb
=
E
E
E
EAS
bb
L
R
ELoad
IS
1
2
5
3
4
6
7
OUT
Vbb
Energy stored in load inductance:
EL = 1/2·L·I2
L
While demagnetizing load inductance, the energy
dissipated in PROFET is
EAS= Ebb + EL - ER= VON(CL)·iL(t) dt,
with an approximate solution for RL > 0 Ω:
EAS= IL· L
2·RL·(Vbb + |VOUT(CL)|)· ln (1+ IL·RL
|VOUT(CL)| )
BTS 640 S2
Semiconductor Group Page 11 2003-Oct-01
Timing diagrams
Figure 1a: Switching a resistive load,
change of load current in on-condition:
IN
ST
OUT
L
t
V
I
IIS
tson
(
IS
)
tt
slc(IS)slc(IS)
Load 1 Load 2
soff
(
IS
)
t
tdon(ST) tdoff
(
ST
)
tt
on off
The sense s i gnal i s not vali d duri ng settli ng time aft er turn or
change of load current.
Figure 1b: Vbb turn on:
IN
V
L
t
I
bb
ST
IIS
proper turn on under all c ondi tions
Figure 2a: Switching a lamp
IN
ST
OUT
L
t
V
I
IIS
Figure 2b: Switching a lamp with current limit:
IN
ST
OUT
L
t
V
I
IIS
BTS 640 S2
Semiconductor Group Page 12 2003-Oct-01
Figure 2c: Switching an inductive load:
IN
ST
t
V
I
OUT
L
IIS
Figure 3a: Short circuit:
shut down by overtempertature, reset by cooling
IN
ST t
I
L(SCr)
I
IL(SCp)
IIS
L
Heating up may require se v eral milliseconds, depending on
external conditions
IL(SCp) = 50 A typ. i ncreases with decreasi ng temperature.
Figure 4a: Overtemperature:
Reset if Tj <Tjt
ST
J
t
T
IN
IL
IIS
Figure 5a: Open load: detection in ON-state,
open load occurs in on-state
IN
ST
OUT
L
t
V
I
opennormal normal
IIS
BTS 640 S2
Semiconductor Group Page 13 2003-Oct-01
Figure 5b: Open load: detection in ON- and OFF-state
(with REXT), turn on/off to open load
IN
ST
OUT
t
V
I
open load
L
IIS
d(ST OL3)
t
Figure 6a: Undervoltage:
IN
V
t
bb
ST
VV
bb(under) bb(u cp)
V
IL
IIS
bb(u rst)
not defined
Figure 6b: Undervoltage restart of charge pump
bb(under)
V
Vbb(u rst)
Vbb(over)
Vbb(o rst)
Vbb(u cp)
off-state
on-state
V
ON(CL)
Vbb
Von
off-state
charge pump starts at Vbb(ucp) =4.7 V typ.
Figure 7a: Overvoltage:
IN
V
t
bb
ST
ON(CL)
VVbb(over) Vbb(o rst)
IL
IIS
BTS 640 S2
Semiconductor Group Page 14 2003-Oct-01
Figure 8a: Current sense versus load current:
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
0123456
IL
[A]
[mA] IIS
Figure 8b: Current sense ratio21:
0
5000
10000
15000
012345678910111213
IL
[A]
kILIS
Figure 9a: Output voltage drop versus load current:
0.0
0.1
0.2
012345678
IL
[A]
[V] VON
ON(NL)
V
ON
R
21 This range for the current sense ratio refers to all
devices. The accuracy of the kILIS can be raised at
least by a factor of two by matching the value of
kILIS for every single device.
BTS 640 S2
Semiconductor Group Page 15 2003-Oct-01
Package and Ordering Code
All dimensions in mm
Standard (=staggered): P-TO220-7-11
Sales code BTS640S2
Ordering code Q67060-S6307-A5
SMD: P-TO263-7-2 (tape&reel)
Sales code BTS640S2 G
Ordering code Q67060-S6307-A6
Ordering code Q67060-S6307-A6
Straight: P-TO220-7-12
Sales Code BTS640S2 S
Ordering code Q67060-S6307-A7
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 München
© Infineon Technologies AG 2001
All Rights Reserved.
Attention please!
The informat i on herei n i s given to describe certain components and
shall not be considered as a guarantee of characteristics.
Terms of del i very and rights to tec hni cal change res erved.
We hereby disclaim any and al l warranties, i ncluding but not l i mited
to warranties of non-infri ngem ent, regarding ci rcuits, descri ptions
and charts stated herein.
Infineon Technologies is an approved CECC m anuf acturer.
Information
For further inf orm ation on technol ogy, delivery terms and condit i ons
and prices pl ease contac t your nearest Infineon Technol ogi es Office
in Germany or our I nfineon Technologies Representat i ves
worldwide (see addres s list).
Warnings
Due to techni cal requirement s component s may c ont ai n dangerous
subst ances. For information on t he t ypes in ques tion please c ontact
your nearest I nfineon Technologies Office.
Infineon Tec hnol ogi es Components m ay only be us ed i n l i f e-support
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health of t he user or other persons may be endangered.
Typical
±0.11.27 4.4
9.25
±0.2
0.05
1)
All metal surfaces tin plated, except area of cut.
C
2.4 0.5±0.1
±0.3
8.6
10.2
±0.3
±0.43.9
±0.48.4
3.7
±0.3
A
A0.25 M
9.8±0.15
2.8
1)
15.65
±0.3
13.4
0...0.15
1.27 0.6±0.1
C
±0.2
17
±0.3
8.51)
10±0.2
3.7-0.15
7x
A
8˚ max.
BA0.25
M
0.1
Typical
9.8
±0.15
±0.2
10
8.5
1)
8
1)
(15)
±0.2
9.25
±0.3
1
0...0.15
7x0.6
±0.1
±0.1
1.27 4.4
B
0.5
±0.1
±0.3
2.7
4.7
±0.5
0.05
1)
0.1
All metal surfaces tin plated, except area of cut.
±0.3
1.3
2.4
6x1.27
A
BA0.25
M
Typical
9.8
±0.15
2.8
1)
15.65±0.3
13.4
0...0.15
1.27 0.6
±0.1
±0.1
1.27 4.4
B
9.25±0.2
0.05
1)
All metal surfaces tin plated, except area of cut.
C
±0.2
17±0.3
8.5
1)
10
±0.2
3.7
-0.15
C
2.4 0.5
±0.1
13±0.5
±0.511
7x
