1White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
July 2003 Rev. 0
ECO #16318
CFA45 Series CompactFlashTM CARDS
8MB to 512MB
PRODUCT DESCRIPTION
CFA45 series CompactFlashTM cards are built with NAND
flash memory components operating as solid-state disk.
They comply with the CompactFlashTM card standard
and are suitable for use as a data storage memory
medium for PCs or other electronic equipment. The
read/write unit is 1 sector (512 bytes) sequential access.
FEATURES
■PC Card-ATA/True IDE/ I/O Card mode compatible
host interface
Automatic sensing of PC Card ATA and IDE mode
Included 256-byte CIS ROM
Support the five PC Card ATA addressing modes
Host Interface bus width: 8/16-bit Access
Flash Interface bus width: 8-bit Access
Support 3 power save mode: standby / idle / active
Auto power down function
2-bit ECC function
■Operating Voltage: 3.3 V and 5.0 V
■ISA standard and Read/Write unit is 512 bytes
(sector) sequential access
■High performance:
Host data transfer rate 20.0 MB/sec
Flash data transfer rate 10.0 MB/sec
■Maximum card density is 512 MB
■3 variations of mode access
Memory card mode
I/O card mode
True-IDE mode
■Internal self-diagnostic program operates at VCC
power on
■High data reliability
Endurance: 100,000 Program / Erase cycles
High reliability based on internal ECC (Error
Correcting Code) function 2-bit ECC
Data reliability is 1 error in 1014 bits read.
■Power Consumption
Active mode 30 mA (typ.), 40 mA (max.)
Idle mode 10 mA
Stop mode 400 µA
CARD BLOCK DIAGRAM
GND
Host
Interface Samsung
Controller
Data
In/Out
Control
Samsung
NAND
Flash
Internal Vcc
Vcc
2
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
CARD CAPACITIES (CF TYPE I BLANK HOUSING)
Capacity Part Number Sectors/Card Cylinder Sector/Track Heads
8 MB WED7P008CFA4501C25 15,616 122 32 4
16 MB WED7P016CFA4501C25 31,488 246 32 4
32 MB WED7P032CFA4501C25 62,976 492 32 4
48 MB WED7P048CFA4501C25 94,464 738 32 4
64 MB WED7P064CFA4501C25 125,952 246 32 16
96 MB WED7P096CFA4501C25 188,928 369 32 16
128 MB WED7P128CFA4501C25 251,904 492 32 16
256 MB WED7P256CFA4501C25 503,808 984 32 16
512 MB WED7P512CFA4501C25 1,029,168 1,021 63 16
CF CARD SIZE AND OUTLINE
PHYSICAL SPECIFICATION
The CFA45 series physical specification complies with CompactFlashTM standard card format.
1.27mm(Pitch)
3.3mm
BOTTOM
2x 12mm
Pin # 1
Pin # 26
Pin # 50
Pin # 25
1.00mm
1.60mm
BOTTOM
TOP
2x 1mm
42.8mm
0.6mm
36.4 mm
0.8mm
2x 25.78mm
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White Electronic Designs
CompactFlashTM Cards
CFA45 Series
SIGNAL PIN ASSIGNMENTS
INTERFACE SPECIFICATION
Memory Card Mode I/O Card Mode True IDE Mode
Pin NO. Signal name I/O Signal name I/O Signal name I/O
1 GND GND GND
2 D3 I/O D3 I/O D3 I/O
3 D4 I/O D4 I/O D4 I/O
4 D5 I/O D5 I/O D5 I/O
5 D6 I/O D6 I/O D6 I/O
6 D7 I/O D7 I/O D7 I/O
7 CE1 I CE1 I CE1 I
8 A10 I A10 I A10 I
9 OE I OE I ATASEL I
10 A9 I A9 I A9 I
11 A8 I A8 I A8 I
12 A7 I A7 I A7 I
13 VCC VCC VCC
14 A6 I A6 I A6 I
15 A5 I A5 I A5 I
16 A4 I A4 I A4 I
17 A3 I A3 I A3 I
18 A2 I A2 I A2 I
19 A1 I A1 I A1 I
20 A0 I A0 I A0 I
21 D0 I/O D0 I/O D0 I/O
22 D1 I/O D1 I/O D1 I/O
23 D2 I/O D2 I/O D2 I/O
24 WP O IOIS16 O IOIS16 O
25 CD2 O CD2 O CD2 O
26 CD1 O CD1 O CD1 O
27 D11 I/O D11 I/O D11 I/O
28 D12 I/O D12 I/O D12 I/O
29 D13 I/O D13 I/O D13 I/O
30 D14 I/O D14 I/O D14 I/O
31 D15 I/O D15 I/O D15 I/O
32 CE2 I CE2 I CE2 I
33 VS1 O VS1 O VS1 O
34 IORD I IORD I IORD I
35 IOWR IIOWR IIOWR I
36 WE I WE I WE I
37 RDY/BSY O IREQ O INTRQ O
38 VCC VCC VCC
39 CSEL I CSEL I CSEL I
40 VS2 O VS2 O VS2 O
41 RESET I RESET I RESET I
42 WAIT O WAIT O IORDY O
43 INPACK O INPACK O INPACK O
44 REG I REG I REG I
45 BVD2 I/O SPKR I/O DASP I/O
46 BVD1 I/O STSCHG I/O PDIAG I/O
47 D8 I/O D8 I/O D8 I/O
48 D9 I/O D9 I/O D9 I/O
49 D10 I/O D10 I/O D10 I/O
50 GND GND GND
4
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Symbol Type Name and Function
A0 - A10 INPUT ADDRESS BUS: These address lines along with the REG signal are used to select the following: The I/O port
address registers within the PC Storage Card, the memory mapped port address registers within the PC
Storage Card, a byte in the Cards information structure and its configuration control and status registers. This
signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. In True IDE Mode only A [2:0]
are used to select the one of eight registers in the Task File, the remaining address lines should be grounded
by the host.
D0 - D15 INPUT/ DATA BUS: These signal lines carry the Data, Commands and Status information between the host and the
OUTPUT controller. D0 is the LSB of the even byte of the word. D8 is the LSB of the odd byte of the word.
This signal is the same as the PC Card memory mode signal in PC Card I/O mode. In True IDE mode, all Task
File operations occur in byte mode on the low order bus D0-D7 while all data transfers are 16 bit using D0D15.
CE1, CE2INPUT CARD ENABLE: CE1 and CE2 are card select signals, active low. These input signals are used both to select
the card and to indicate to the card whether a byte or a word operation is being performed. CE2 always
accesses the odd byte of the word. CE1 accesses the even byte or the Odd byte of the word depending on
A0 and CE2. A multiplexing scheme based on A0, CE1, CE2 allows 8 bit hosts to access all data on
D0-D7. This signal is the same as the PC card memory mode signal in PC Card I/O mode. In the True IDE
mode, CE1 is the chip select for the task file registers while CE2 is used to select the Alternate Status
Register and the Device Control Register.
OE, ASTEL INPUT OUTPUT ENABLE, ATA SELECT: OE is used for the control of data read in Attribute area or Common memory
area. To enable True IDE Mode this input should be grounded by the host (in power up).
WE INPUT WRITE ENABLE: WE is used for the control of data write in Attribute memory area or Common memory area.
This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card
when the card is configured in the memory interface mode. It is also used for writing the configuration
registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode,
this input signal is not used and should be connected to VCC by the host.
IORD INPUT I/O READ: IORD is used for control of read data in the Task File area. This card does not respond to IORD
until I/O card interface setting up.
IOWR INPUT I/O WRITE: IOWR is used for control of data write in the Task File area. This card does not respond to IOWR
until I/O card interface setting up. This signal is not used in memory mode. The I/O write strobe pulse is used
to clock I/O data on the card data bus into the CF Card controller registers when the CF Card is configured to
use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In
True IDE mode, this signal has the same function as in PC Card I/O Mode.
RDY/BSY, OUTPUT READY/BUSY, INTERRUPT REQUEST: In memory mode, this signal is set high when the CF Card is
IREQ, INTRQ ready to accept a new data transfer operation and held low when the card is busy. The host memory card
socket must provide a pull-up resistor. At power up and at reset, the RDY/BSY signal is held low (busy) until
the CF Card has completed its power up or reset function. No access of any type should be made to the CF
Card during this time. The RDY/BSY signal is held high (disabled from being busy) whenever the following
condition is true: The CF Card has been powered up with RESET continuously disconnected or asserted. I/O
operation - After the CF Card has been configured for I/O operation, this signal is used as Interrupt request.
This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE
mode, this signal is the active high Interrupt request to the host.
CD1, CD2OUTPUT CARD DETECTION: CD1 and CD2 are the card detection signals. CD1 and CD2 are connected to ground in
this card, so the host can detect if the card is inserted or not.
WP, IOIS16 OUTPUT WRITE PROTECT, 16 BIT I/O PORT: In memory card mode, WP is held low because this card does not have a
write protect switch. In the I/O card mode, IOIS16 is asserted when Task File registers are accessed in 16-bit
mode. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer
cycle.
REG INPUT ATTRIBUTE MEMORY AREA SELECTION: REG should be high level during common memory area accessing,
and low level during Attribute area accessing. The attribute memory area is located only in an even address, so
D0 to D7 are valid and D8 to D15 are invalid in the word access mode. Odd addresses are invalid in the byte
access mode. The signal must also be active (low) during I/O cycles when the I/O address is on the Bus. In
True IDE Mode this input signal is not used and should be connected to VCC.
BVD2, SPKR, INPUT/ BATTERY VOLTAGE DETECTION, DIGITAL AUDIO OUTPUT, DISK ACTIVE/SLAVE PRESENT: In memory card
DASP OUTPUT mode, BVD2 outputs the battery voltage status in the card. This card has no battery, so this output is high
level constantly. In the I/O card mode, SPKR is held High because this card does not have digital audio output.
In True IDE Mode DASP is the Disk Active/Slave Present signal in the Master/Slave handshake protocol.
RESET, INPUT RESET: By assertion of the RESET signal, all registers of this card are cleared and the RDY/BSY signal turns
RESET to high level. In True IDE Mode RESET is the active low hardware reset from the host.
INTERFACE SIGNALS DESCRIPTION
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White Electronic Designs
CompactFlashTM Cards
CFA45 Series
Symbol Type Name and Function
WAIT, IORDY OUTPUT WAIT: This signal outputs low level for the purpose of delaying memory access cycle or I/O access cycle. In
True IDE Mode this output signal may be used as IORDY. As for this controller, this output is high impedance
state constantly.
INPACK OUTPUT INPUT ACKNOWLEDGE: This signal is not used in the memory card mode. The Input acknowledge signal is
asserted by the CF Card when the card is selected and responding to an I/O read cycle at the address that is
on the address bus. This signal is used by the host to control the enable of any input data buffers between the
CF Card and the CPU. In True IDE mode, this output signal is not used and should be connected to VCC at
the host.
BVD1, INPUT/ BATTERY VOLTAGE DETECTION, STATUS CHANGE, PASS DIAGNOSTIC: In the memory card mode, BVD1
STSCHG, OUTPUT outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly.
PDIAG In the I/O card mode, STSCHG is used for changing the status of the Configuration status register in the
Attribute area, while the card is set I/O card interface. In True IDE Mode, PDIAG is the Pass Diagnostic signal
in the Master/Slave handshake protocol.
VS1, VS2OUTPUT VCC VOLTAGE SENSE: These signals are intended to notify the socket of the CF Cards CIS VCC requirement.
VS1 is held low and VS2 is not connected in this card.
CSEL INPUT CARD SELECT: This signal is not used in the memory card mode and I/O card mode. This internally pulled up
signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When
this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as
a Slave.
INTERFACE SIGNALS DESCRIPTION CONT.
COMPACTFLASHTM/PCMCIA-ATA REGISTER MAPPING ADDRESS.
COMPACTFLASHTM/PCMCIA-ATA I/O MAPPING A DDRESS
REG Primary I/O Secondary I/O Independent I/O IORD = L IOWR = L
A[10:0] A[10:0] A[3:0]
L 1F0H 170H 0H Read Even Data Write Even Data
L 1F1H 171H 1H Error Register Feature Register
L 1F2H 172H 2H Sector Count Sector Count
L 1F3H 173H 3H Sector Number Sector Number
L 1F4H 174H 4H Cylinder Low Cylinder Low
L 1F5H 175H 5H Cylinder High Cylinder High
L 1F6H 176H 6H Drive/Head Drive/Head
L 1F7H 177H 7H Status Register Command
L - - 8H Duplicate Read Even Data Duplicate Write Even Data
L - - 9H Duplicate Read Odd Data Duplicate Write Odd Data
L - - 0DH Duplicate Error Duplicate Feature
L 3F6H 376H 0EH Alternate Status Device Control
L 3F7H 377H 0FH Drive Address Reserved
6
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
COMPACTFLASHTM /PCMCIA-ATA MEMORY MAPPING A DDRESS
REG A10 A[9:4] A[3] A[2] A[1] A[0] IORD = L IOWR = L
H L X L L L L Read Data Write Data
H L X L L L H Error Register Feature
H L X L L H L Sector Count Sector Count
H L X L L H H Sector Number Sector Number
H L X L H L L Cylinder Low Cylinder Low
H L X L H L H Cylinder High Cylinder High
H L X L H H L Drive/Head Drive/Head
H L X L H H H Status Register Command
H L X H L L L Duplicate Read Even Data Duplicate Write Even Data
H L X H L L H Duplicate Read Odd Data Duplicate Write Odd Data
H L X H H L H Duplicate Error Duplicate Feature
H L X H H H L Alternate Status Device Control
H L X H H H H Drive Address Reserved
H H X X X X L Read Even Data Write Even Data
H H X X X X H Read Odd Data Write Odd Data
THE ATA REGISTERS AND PCMCIA REGISTERS
STATUS REGISTER
DIRECTION - This register is read-only by the host.
ACCESS RESTRICTION - The contents of this register, except for BSY, will be ignored when BSY is set to one. BSY
is valid at all time. The contents of the register and all other Command Block registers are not valid while a device
is in the Sleep mode.
FUNCTIONAL DESCRIPTION - This register contains the device status. The contents of this register are updated to
reflect the current state of the device and the progress of any command being executed by the device.
BIT DESCRIPTION
7 6 5 4 3 2 1 0
BSY DRDY DF DSC DRQ CORR IDX ERR
BIT 0 ERR (Error) indicates that an error occurred during execution of the previous command. The Error register has
additional information regarding the cause of the error when this bit is asserted.
BIT 1 IDX (Index) is vendor specific.
BIT 2 CORR (Corrected Data) is used to indicate a correctable data error. The definition of what constitutes a
correctable error is vendor specific.
BIT 3 DRQ (Data Request) indicates that the device is ready to transfer a word or byte between the host and the
device.
BIT 4 DSC (Device Seek Complete) indicates that the device heads are settled over a track.
BIT 5 DF (Device Fault) indicates a device fault error has been detected. The internal status or internal conditions that
causes this error to be indicated is vendor specific.
BIT 6 DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codes. This bit will
be cleared at power on.
BIT 7 BSY (Busy) is set whenever the device has control of the command block registers. When the BSY bit is equal
to one, the commands written to this register will be ignored by the device.
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CompactFlashTM Cards
CFA45 Series
COMMAND REGISTER
DIRECTION - This register is write-only by host.
ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. The contents of this
register and all other Command Block registers are not valid while a device is in the Sleep mode.
FUNCTIONAL DESCRIPTION - This register contains the command code being sent to the device. Command
execution begins immediately after this register is written.
BIT DESCRIPTION
76543210
Command Code
ERROR REGISTER
DIRECTION - This register is read-only by host.
ACCESS RESTRICTION - The contents of this register shall be valid when BSY and DRQ are equal to zero and ERR
is asserted.
FUNCTIONAL DESCRIPTION - This register contains the operation status for the current command.
BIT DESCRIPTION
76543210
R UNC MC IDNF MCR ABRT TKONF AMNF
BIT 0 AMNF (Address Mark Not Found) indicates the data address mark has not been found after finding the correct
ID field.
BIT 1 TKONF (Track 0 Not Found) indicates the track 0 has not been found during a RECALIBRATE command.
BIT 2 ABRT (Aborted Command) indicates the requested command has been aborted because the command code or a
command parameter is invalid or some other error has occurred.
BIT 3 MCR (Media Change Requested) is used by removable media devices.
BIT 4 IDNF (ID Not Found) indicates the requested sectors ID field could not be found.
BIT 5 MC (Media Change) is used by removable media devices.
BIT 6 UNC (Uncorrectable Data Error) indicate an uncorrectable data error has been encountered.
BIT 7 Reserved
FEATURE REGISTER
DIRECTION - This register is write-only by host.
ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero.
FUNCTIONAL DESCRIPTION - This register is command specific.
BIT DESCRIPTION
76543210
Command Specific
8
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CompactFlashTM Cards
CFA45 Series
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SECTOR NUMBER REGISTER
DIRECTION - This register is bi-directional for the drive and host.
ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero.
FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the
starting sector number for any media access. If the LBA bit is set to one in the Device/Head register, this register
contains Bits 7-0 of the LBA for any media access.
BIT DESCRIPTION
CHS
7654 3 2 10
Sector (7:0)
LBA
7654 3 2 10
LBA (7:0)
SECTOR COUNT REGISTER
DIRECTION - This register is bi-directional for the drive and host.
ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero.
FUNCTIONAL DESCRIPTION - This register contains the number of sector of data requested to be transferred on a
read or write operation between the host and the device. If the value in this register is zero, a count of 256 sectors is
specified.
BIT DESCRIPTION
7654 3 2 10
Sector Count
CYLINDER LOW REGISTER
DIRECTION - This register is bi-directional for the drive and host.
ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero.
FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the
low order bits of the starting cylinder address for any media access. If the LBA bit is set to one in the Device/Head
register, this register contains Bits 15-8 of the LBA for any media access.
BIT DESCRIPTION
CHS
7654 3 2 10
Cylinder (7:0)
LBA
7654 3 2 10
LBA (15:8)
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CompactFlashTM Cards
CFA45 Series
CYLINDER HIGH REGISTER
DIRECTION - This register is bi-directional for the drive and host.
ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero.
FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the
low order bits of the starting cylinder address for any media access. If the LBA bit is set to one in the Device/Head
register, this register contains Bits 23-16 of the LBA for any media access.
BIT DESCRIPTION
CHS
76543210
Cylinder (7:0)
LBA
76543210
LBA (15:8)
DEVICE/HEAD REGISTER
DIRECTION - This register is bi-directional for the drive and host.
ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero.
FUNCTIONAL DESCRIPTION - This register selects the device, defines address translation as CHS or LBA, and
provides the head address if CHS mode or LBA (27:24) if LBA mode.
BIT DESCRIPTION
CHS (CYLINDER-HEAD-SECTOR)
76543210
1 LBA 1 DEV HS3 HS2 HS1 HS0
LBA (LOGIC BLOCK ADDRESS)
76543210
1 LBA 1 DEV LBA (27:24)
BIT 0~3 If LBA is equal to zero (CHS), these contain the head address of the starting CHS address. The HS3 bit is the
most significant bit. If LBA is equal to one (LBA), these bits represent bits 27 through 24 of the LBA.
BIT 4 DEV is the device address. When the DEV bit is equal to zero, Device 0 is selected. When the DEV bit is equal to
one, Device 1 is selected.
BIT 5 Bit 5 is set to one for backward compatibility.
BIT 6 LBA mode if this bit is set to one, otherwise, CHS mode.
BIT 7 Bit 7 is set to one for backward compatibility.
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CompactFlashTM Cards
CFA45 Series
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DATA REGISTER
DIRECTION - This register is bi-directional for the drive and host.
ACCESS RESTRUCTIONS - This register can be written or the content is valid on read when DRQ is set to one.
FUNCTIONAL DESCRIPTION - The data register is 16-bit wide.
BIT DESCRIPTION
15 14 13 12 11 10 9 8
Data (15:8)
7654 3 2 10
Data (7:0)
PCMICA CONFIGURATION OPTION REGISTER
DIRECTION - This register is read-only by host.
FUNCTION DESCRIPTION - Direct map to 0x200H in the Attribute Memory.
BIT DESCRIPTION
7654 3 2 10
SRESET LevlReq Configuration Index
BIT 0~5 Configuration Index:
0 : common memory mode
1 : Independent IO mode
2 : Primary IO mode
3 : Secondary IO mode
BIT 6 LevlReq (level Mode IREQ#) : Level Mode Interrupts are selected when this bit is set to one, otherwise it is Pulse
Mode Interrupts.
BIT 7 SRESET (Soft Reset): Setting this bit to one places the card in the reset state. This is equivalent to assertion of
the RESET signal.
PCMICA CARD CONFIGURATION AND STATUS REGISTER
DIRECTION - This register is bi-directional for the drive and host.
FUNCTION DESCRIPTION - Direct map to 0x202H in the Attribute Memory.
BIT DESCRIPTION
7654 3 2 10
SCDect SigChg IOis8 ResrV SPKR/DASP PwrDn Intr ResrV
BIT 0 Reserved
BIT 1 Intr (Interrupt Request Pending) : The real time status of the host interrupt signal pin.
BIT 2 PwrDn (Power Down): This bit will enable the power down mode.
BIT 3 SPKR/DASP: Setting this bit to 1 will enable DASP- to the BVD2 pin of the PCMCIA connector, otherwise, the BVD2
will be held at high-impedance.
BIT 4 ResrV: Reserved bit must be 0.
BIT 5 IOis8 (I/O Cycles Occur Only as 8-bit Transfer): When the host can provide I/O cycle only using the D7:D0 data
path, the PCMCIA software will set this bit to 1.
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CompactFlashTM Cards
CFA45 Series
BIT 6 SigChg (Signal Change Enable/Disable): If this bit is set to one, the Signal Changed output is enabled.
BIT 7 SCDect (Status Change Detected): This bit indicates that at least one bit of the Pin replacement Register is set one.
PCMICA PIN REPLACEMENT REGISTER
DIRECTION - This register is read-only by host.
FUNCTION DESCRIPTION - Direct map to 0x204H in the Attribute Memory.
BIT DESCRIPTION
76543210
ResrV ResrV CRdy CWProt ResrV ResrV CSRdy CSWProt
BIT 0 CSWProt (Current State of Write Protect) : This bit represents the current the state of the Write Protect.
BIT 1 CSRdy (Current State of Ready) : This bit represents the internal state of the READY signal.
BIT 2~3 Reserved.
BIT 4 CWProt (Change Write Protect) : This bit is set to one when CSWProt changes state.
BIT 5 CRdy (Changed Ready) : This bit is set to one when CSRdy changes state.
BIT 6~7 ResrV : Reserved bit must be 0.
PCMICA SOCKET AND COPY REGISTER
DIRECTION - This register is bi-directional for the drive and host.
FUNCTION DESCRIPTION - Direct map to 0x206H in the Attribute Memory.
BIT DESCRIPTION
76543210
ResrV Copy Number Socket Number
BIT 0~2 Socket Number : The first Socket is numbered 0.
BIT 3~5 Copy Number
BIT 6~7 ResrV : Reserved bit must be 0.
12
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CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Symbol Parameter Ratings Unit
VDD Supply voltage  0.3 to + 7.0 V
VIN Input voltage 0.3 to V DD + 0.3 V
IIN DC input current 10 mA
TSTG Storage temperature  40 to + 80 °C
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Ratings Unit
VDD DC supply voltage 5V 4.5 to + 5.5 V
3.3V 3.0 to 3.6 V
Ta Storage temperature 0 to + 60 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Conditions Min Typ Max Unit
VIH High level input voltage CMOS 2.0 V
VIL Low level input voltage CMOS 1.0 V
VTSwitching threshold CMOS 1.4 V
VT+Switching trigger, CMOS 2.0 V
positive-going threshold
VT-Switching trigger, CMOS 1.0 V
negative-going threshold
IIH High level input current Input buffer VIN = VDD 10 10 uA
Input buffer with pull-up 10 30 60
IIL Low level input current Input buffer VIN = VSS 10 10 uA
Input buffer with pull-up 160 30 10
VOH High level output voltage IOH = 8 mA 2.4 V
VOL Low level output voltage IOL = 8 mA 0.4 V
IOZ Tri-state output leakage current VOUT = VSS or VDD 10 10 uA
IDD Maximum operating current VDD = 5.0V, 30 40 mA
Iidle Idle current fMCLK = 20 MHz 10 mA
Ids Stop current 300 uA
D.C. ELECTRICAL CHARACTERISTICS @ 3.3V
(TA = 0 TO +60°C, VCC = 3.3V ± 5%)
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CompactFlashTM Cards
CFA45 Series
Symbol Parameter Conditions Min Typ Max Unit
VIH High level input voltage CMOS 3.5 V
TTL 2.0
VIL Low level input voltage CMOS 1.5 V
TTL 0.8
VTSwitching threshold CMOS 2.5 V
TTL 1.4
VT+Switching trigger, CMOS 4.0 V
positive-going threshold TTL 2.0
VT-Switching trigger, CMOS 1.0 V
negative-going threshold TTL 0.8
IIH High level input current Input buffer VIN = VDD 10 10 uA
Input buffer with pull-up 10 50 100
IIL Low level input current Input buffer VIN = VSS 10 10 uA
Input buffer with pull-up 100 50 10
VOH High level output voltage IOH = 8 mA 2.4 V
VOL Low level output voltage IOL = 8 mA 0.4 V
IOZ Tri-state output leakage current VOUT = VSS or VDD 10 10 uA
IDD Maximum operating current VDD = 5.0V, 30 40 mA
Iidle Idle current fMCLK = 24 MHz 10 mA
Ids Stop current 400 uA
ELECTRICAL CHARACTERISTICS @ 5V
(TA = 0 TO 60°C, VCC = 5V ± 10%)
ITEM SPECIFICATION
Vibration Operating 15G peak to peak Max.
Non-Operating 15G peak to peak Max.
Shock Operating 2,000G Max.
Non-Operating 2,000G Max.
Relative Humidity Operating 8% ~ 95%
(non-condensing) Non-Operating 8% ~ 95%
MTBF Operating > 1,000,000 hours
Endurance Operating ³ 100,000 erase program cycles
Data Reliability Operating < 1 non-recoverable error in 1014 bits read
ENVIRONMENTAL AND RELIABILITY SPECIFICATIONS
14
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
INTERFACE SIGNAL TIMING
There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped
I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card
Standard. The PC Card conforms to the timing in that reference document.
PC CARD INTERFACE
Parameter Symbol IEEE Symbol 300ns
Min. ns Max. ns
Read Cycle Time tC(R) TAVAV 300
Address Access Time tA(A) TAVQV 300
Card Enable Access Time tA(CE) TELQV 300
Output Enable Access Time tA(OE) TGLQV 150
Output Disable Time from CE tDIS(CE) TEHQZ 100
Output Disable Time from OE tDIS(OE) TGHQZ 100
Address Setup Time tSU(A) tAVWL 30
Output Enable Time from CE tEN(CE) tELQNZ 5
Output Enable Time from OE tEN(OE) tGLQNZ 5
Data Valid from Address Change tV(A) tAXQX 0
ATTRIBUTE MEMORY READ TIMING
NOTE: All times are in nanosecond. Dout signifies data provided by the PC Card to the system. The CE signal or both
the OE signal & the WE signal must be de-asserted between consecutive cycle operations.
An
REG
CE
OE
D
OUT
t
C
(R)
t
A
(A)
t
SU
(A)
t
A
(CE)
t
V
(A)
t
EN
(CE)
t
EN
(OE)
t
A
(OE)
t
DIS
(CE)
t
DIS
(OE)
ATTRIBUTE MEMORY READ TIMING DIAGRAM
15 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
Parameter Symbol IEEE Symbol 250ns
Min. ns Max. ns
Write Cycle Time tC(W) tAVAV 250
Write Pulse Width tW(WE) tWLWH 150
Address Setup Time tSU(A) tAVWL 30
Write Recovery Time tREC(WE) tWMAX 30
Data Setup Time for WE tSU(D-WEH) tDVWH 80
Data Hold Time tH(D) tWMDX 30
ATTRIBUTE MEMORY WRITE TIMING
Note: A host cannot write to CIS. This timing is specified
only for the write to Configuration Register.
NOTE: All times are in nanosecond. Din signifies data provided by the system to the PC Card.
ATTRIBUTE MEMORY WRITE TIMING DIAGRAM
REG
An
WE
CE
DOUT
tC (W)
tSU (A)
tW (WE)
tH (D)
Data In Valid
tSU (D-WEH)
OE
tREC (WE)
16
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Parameter Symbol IEEE Symbol Min. ns Max. ns
Output Enable Access Time ta (OE) tGLQV 125
Output Disable Time from OE tdis (OE) tGHQZ 100
Address Setup Time tsu (A) tAVGL 30
Address Hold Time th (A) tGHAX 20
CE Setup before OE tsu (CE) tELGL 0
CE Hold following OE th (CE) tGHEH 20
Wait Delay Falling from OE tv (WT-OE) tGLWTV 35
Data Setup for Wait Release tv (WT) tQVWTH 0
Wait Width Time tw (WT) tWTLWTH 350
COMMON MEMORY READ TIMING
NOTE: The maximum load on WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. DOUT signifies data
provided by the PC Card to the system. The WAIT signal may be ignored if the OE cycle-to-cycle time is greater than the
Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time
meets the PCMCIA specification of 12s but is intentionally less in this specification.
COMMON MEMORY READ TIMING DIAGRAM
An
REG
CE
OE
D
OUT
t
SU
(A)
t
A
(OE)
t
SU
(CE)
WAIT
t
H
(A)
t
W
(WT)
t
H
(CE)
t
DIS
(CE)
t
V
(WT-OE) t
V
(WT)
t
DIS
(OE)
17 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
Parameter Symbol IEEE Symbol Min. ns Max. ns
Data Setup before WE tsu (D-WEH) tDVWH 80
Data Hold following WE th (D) tlWMDX 30
WE Pulse Width tw (WE) tWLWH 150
Address Setup Time tsu (A) tAVWL 30
CE Setup before WE tsu (CE) tELWL 0
Write recovery Time trec (WE) tWMAX 30
Address Hold Time th (A) tGHAX 20
CE Hold following WE th (CE) tGHEH 20
Wait Delay Falling from WE tv (WT-WE) tWLWTV 35
WE High from Wait Release tv (WT) tWTHWH 0
Wait Width Time tw (WT) tWTLWTH 350
COMMON MEMORY WRITE TIMING
NOTE: The maximum load on WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. DIN signifies data
provided by the system to the PC Card. The WAIT signal may be ignored if the WE cycle-to-cycle time is greater than the
Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time
meets the PCMCIA specification of 12s but is intentionally less in this specification.
COMMON MEMORY WRITE TIMING DIAGRAM
An
REG
CE
WE
DIN
tSU (A)
tW (WE)
tSU (CE)
WAIT
tH (A)
tW (WT)
tH (CE)
tREC (WE)
tV (WT-WE)
tSU (D-WEH)
tV (WT)
tH (D)
DIN Valid
18
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Parameter Symbol IEEE Symbol Min. ns Max. ns
Data Delay after IORD td (IORD) tlGLQV 100
Data Hold following IORD th (IORD) tlGHQX 0
IORD Width Time tw (IORD) tlGLIGH 165
Address Setup before IORD tsuA (IORD) tAVIGL 70
Address Hold following IORD thA (IORD) tlGHAX 20
CE Setup before IORD tsuCE (IORD) tELIGL 5
CE Hold following IORD thCE (IORD) tlGHEH 20
REG Setup before IORD (IORD) tsuREG tRGLIGL 5
REG Hold following IORD thREG (IORD) tlGHRGH 0
INPACK Delay Falling from IORD tdfINPACK (IORD) tlGLIAL 0 45
INPACK Delay Rising from IORD tdrINPACK (IORD) tlGHIAH 45
IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35
IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35
Wait Delay Falling from IORD tdWT (IORD) tlGLWTL 35
Data Delay from Wait Rising td (WT) tWTHQV 0
Wait Width Time tw (WT) tWTLWTH 350
I/O INPUT (READ) TIMING
NOTE: The maximum load on WAIT, INPACK and IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds.
Minimum time from WAIT high to IORD high is 0nsec, but minimum IORD width must still be met. DOUT signifies data
provided by the PC Card to the system. The Wait Width time meets the PCMCIA specification of 12s but is intentionally
less in this specification.
I/O READ TIMING DIAGRAM
An
REG
CE
IORD
D
OUT
t
SU
(IORD)
t
W
IORD
t
SU
CE (IORD)
WAIT
t
W
(WT)
t
H
A (IORD)
t
D
WT (IORD)
t
H
(IORD)
INPACK
IOIS
16
t
SU
REG (IORD) t
H
RE (IORD)
t
H
CE (IORD)
t
D
(IORD)
t
D
(WT)
t
DR
INPACK (IORD)
t
DR
IOIS
16
(ADR)
t
DF
INPACK (IORD)
t
DF
IOIS
16
(ADR)
19 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
Parameter Symbol IEEE Symbol Min. ns Max. ns
Data Setup before IOWR tsu (IOWR) tDVIWH 60
Data Hold following IOWR th (IOWR) tlWHDX 30
IOWR Width Time tw (IOWR) tlWLIWH 165
Address Setup before IOWR tsuA (IOWR) tAVIWL 70
Address Hold following IOWR thA (IOWR) tlWHAX 20
CE Setup before IOWR tsuCE (IOWR) tELIWL 5
CE Hold following IOWR thCE (IOWR) tlWHEH 20
REG Setup before IOWR tsuREG (IOWR) tRGLIWL 5
REG Hold following IOWR thREG (IOWR) tlWHRGH 0
IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35
IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35
Wait Delay Falling from IOWR tdWT (IOWR) tlWLWTL 35
IOWR high from Wait high tdrIOWR (WT) tWTJIWH 0
Wait Width Time tw (WT) tWTLWTH 350
I/O INPUT (WRITE) TIMING
NOTE: The maximum load on WAIT, INPACK, and IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds.
Minimum time from WAIT high to IOWR high is 0nsec, but minimum IOWR width must still be met. DIN signifies data
provided by the system to the PC Card. The Wait Width time meets the PCMCIA specification of 12s but is intentionally
less in this specification.
I/O WRITE TIMING DIAGRAM
An
REG
CE
IOWR
DIN
tSU (IOWR)
tWIORD
tSUCE (IOWR)
WAIT
tDRIOWR (WT)
tHA (IOWR)
tDWT (IOWR) tH (IOWR)
IOIS16
tSUREG (IOWR) tHRE (IOWR)
tHCE (IOWR)
tSU (IOWR)
tW (WT)
tDRIOIS16 (ADR)
tDFIOIS16 (ADR)
20
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Parameter Symbol IEEE Symbol Min. ns Max. ns
Data Delay after IORD td (IORD) tlGLQV 100
Data Hold following IORD th (IORD) tlGHQX 0
IORD Width Time tw (IORD) tlGLIGH 165
Address Setup before IORD tsuA (IORD) tAVIGL 70
Address Hold following IORD thA (IORD) tlGHAX 20
CE Setup before IORD tsuCE (IORD) tELIGL 5
CE Hold following IORD thCE (IORD) tlGHEH 20
IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35
IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35
IDE MODE READ TIMING
NOTE: The maximum load on IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from
WAIT high to IORD high is 0nsec, but minimum IORD width must still be met. DOUT signifies data provided by the PC Card
to the system.
IDE MODE READ TIMING DIAGRAM
IDE MODE INTERFACE
An
CE
IORD
DOUT
tSU (IORD)
tWIORD
tD (IORD)
tHA (IORD)
tH (IORD)
IOIS16
tSUCE (IORD) tHCE (IORD)
tDRIOIS16 (ADR)
tDFIOIS16 (ADR)
21 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
Parameter Symbol IEEE Symbol Min. ns Max. ns
Data Setup before IOWR tsu(IOWR) tDVIWH 60
Data Hold following IOWR th(IOWR) tlWHDX 30
IOWR Width Time twI(OWR) tlWLIWH 165
Address Setup before IOWR tsuA(IOWR) tAVIWL 70
Address Hold following IOWR thA(IOWR) tlWHAX 20
CE Setup before IOWR tsuCE(IOWR) tELIWL 5
CE Hold following IOWR thCE(IOWR) tlWHEH 20
IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 35
IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 35
IDE MODE WRITE TIMING
NOTE: The maximum load on IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from -
WAIT high to IOWR high is 0nsec, but minimum IOWR width must still be met. DIN signifies data provided by the system to
the PC Card.
IDE MODE WRITE TIMING DIAGRAM
An
CE
IOWR
DIN
tSU (IOWR)
tWIOWR
tSU (IOWR)
tHA (IOWR)
tH (IOWR)
IOIS16
tSUCE (IOWR) tHCE (IOWR)
tDRIOIS16 (ADR)
tDFIOIS16 (ADR)
22
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Parameter Symbol Min Typ Max Unit
Level Set before Power On tset 1 ms
Power on Reset tpor 10 ms
Reset time trst 10 ms
RESET TIMING
RESET TIMING DIAGRAM
T
RST
T
POR
T
SET
CSEL Pin
OE Pin
RDY/BSY Pin
Reset Pin
V
CC
POR
(Internal)
Parameter Symbol Min Typ Max Unit Test conditions
CE setup time tsu(VCC) 100 ms
VCC rising up time tpr 0.1 100 ms
POWER ON RESET CHARACTERISTICS
All card status are reset automatically when VCC voltage goes over about 2.3 V.
t
SU(VCC)
t
PR
CE
1
, CE
2
V
CC
Attention for Card Use
In the reset or power off, all register information is
cleared.
All card status are cleared automatically when Vcc
voltage turns below about 2.5V.
Notice that the card insertion/removal should not be
executed during host is active, if the card is used in true
IDE mode.
After the card hard reset, soft reset, or power on reset, the
card cannot access during +READY pin is low level.
Please notice that the card insertion/removal should be
executed after card internal operations are completed
(status register bit 7 turns from 1 to 0).
Before the card insertion Vcc cannot be supplied to the
card. After confirmation that CD1, CD2 pins are inserted,
supply Vcc to the card.
OE must be kept at the Vcc level during power on reset
in memory card mode and I/O card mode. OE must be
kept constantly at the GND level in True IDE mode.
Unused pins of data bus (D0 to D15) signals should not
be opened.
POWER ON RESET TIMING
23 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
Word 8MB 16MB 32MB 48MB 64MB 96MB 128MB 256MB
0 848A 848A 848A 848A 848A 848A 848A 848A
1 007A 00F6 01EC 02E2 00F6 0171 01EC 03D8
2 0000 0000 0000 0000 0000 0000 0000 0000
3 0004 0004 0004 0004 0010 0010 0010 0010
4 0000 0000 0000 0000 0000 0000 0000 0000
5 0200 0200 0200 0200 0200 0200 0200 0200
6 0020 0020 0020 0020 0020 0020 0020 0020
7-8 0000 0000 0000 0001 0001 0002 0003 0007
3D00 7B00 F600 7100 EC00 E200 D800 B000
9 0000 0000 0000 0000 0000 0000 0000 0000
10-19 All 2020 All 2020 All 2020 All 2020 All 2020 All 2020 All 2020 All 2020
20 0000 0000 0000 0000 0000 0000 0000 0000
21 0002 0002 0002 0002 0002 0002 0002 0002
22 0004 0004 0004 0004 0004 0004 0004 0004
23-26 *1 *1 *1 *1 *1 *1 1 *1
27-46 *2 *2 *2 2 *2 *2 *2 *2
47 0004 0004 0004 0004 0004 0004 0004 0004
48 0000 0000 0000 0000 0000 0000 0000 0000
49 0200 0200 0200 0200 0200 0200 0200 0200
50 0000 0000 0000 0000 0000 0000 0000 0000
51 0200 0200 0200 0200 0200 0200 0200 0200
52 0000 0000 0000 0000 0000 0000 0000 0000
53 0001 0001 0001 0001 0001 0001 0001 0001
54 007A 00F6 01EC 02E2 00F6 0171 01EC 03D8
55 0004 0004 0004 0004 0010 0010 0010 0010
56 0020 0020 0020 0020 0020 0020 0020 0020
57-58 3D00 7B00 F600 7100 EC00 E200 D800 B000
0000 0000 0000 0001 0001 0002 0003 0007
59 0100 0100 0100 0100 0100 0100 0100 0100
60-61 3D00 7B00 F600 7100 EC00 E200 D800 B000
0000 0000 0000 0001 0001 0002 0003 0007
62-127 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000
128 0000 0000 0000 0000 0000 0000 0000 0000
129-159 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000
160 0000 0000 0000 0000 0000 0000 0000 0000
161-255 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000
IDENTIFY DRIVE INFORMATION
CARD INFORMATION STRUCTURE (CIS) & IDENTIFY DRIVE (ID) INFORMATION
Note 1. Firmware Version: Rev 1.15 (52 65 76 20 31 2E 31 35)
2. Model Number: SAMSUNG CF/ATA (53 41 4d 53 55 4e 47 20 43 46 2f 41 54 41 20 20 20 20 20 20)
24
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
AttributeOffset Data 76543210Description of Contents CIS Function
000h 01 CISTPL_DEVICE Device Info Tuple Tuple Code
002h 04 Link is 4bytes Link to next tuple
004h DF Device Type Code W Speed I/O device, Device ID
Dh=I/O 1 7h No Write Protects, WPS, Speed
006h 4A X 9h 2h Device Speed = 400ns
008h 01 Device Size 2Kbyte of address Space Device Size
00Ah FF List End Marker End of Devices End Marker
00Ch 1 C CISTPL_DEVICE_OC Other Condition Device Info Tuple Tuple Code
00Eh 04 Link is 4bytes Link to next tuple
010h 02 0 Reserved, 0 VccU M 3.3V Vcc Operation OC Info
012h D9 Device Type Code W Speed I/O device, No Write Protects, Device ID WPS, Speed
Dh=I/O 1 1h Device Speed=250ns
014h 01 Device Size 2Kbyte of address Space Device Size
016h FF List End Marker End of Devices End Marker
018h 18 CISTPL_JEDEC_C JEDEC ID Common Mem Tuple Code
01Ah 02 Link is 2bytes Link to next tuple
01Ch DF PCMCIA Manufacture s ID First Byte of JEDEC ID JEDEC ID of Device 1
01Eh 01 PCMCIA Code for PC Card-ATA Second Byte of JEDEC ID JEDEC ID
No Vpp Required
020h 20 CISTPL_MANFID Manufacture ID String Tuple Code
022h 04 Link is 4bytes Link to next tuple
024h CE PC Card Manufactures ID Code TPLMID_MANF
026h 00 TPLMID_MANF
028h 00 Manufacture Information TPLMID_CARD
02Ah 00 TPLMID_CARD
02Ch 15 CISTPL_VERS_1 Level 1 Version/Product Tuple Code
Infor mation
02Eh 20 Link is 20bytes Link to next tuple
030h 04 Major Version Number PCMCIA 2.1 TPLLV1_MAJOR
032h 01 Minor Version Number JEIDA 4.2 TPLLV1_MINOR
034h 53 Manufacture Information S String 1
036h 41 A
038h 4D M
03Ah 53 S
03Ch 55 U
03Eh 4E N
040h 47 G Name of Manufacture
042h 20
044h 20
046h 20
048h 20
04Ah 20
04Ch 20
04Eh 00 End of Manufacture Information Null Terminator End String 1
050h 52 Product Information R String 2
052h 65 e
054h 76 v
056h 20
058h 31 1
05Ah 2E .
05Ch 31 1 Firmware Revision
05Eh 35 5
060h 20
062h 20
064h 20
066h 20
068h 20
CARD INFORMATION STRUCTURE
25 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
AttributeOffset Data 7 6 5 43210Description of Contents CIS Function
06Ah 00 End of Product Information Null Terminator End String 2
06Ch 00 End of CIS Revision Number Null Terminator
06Eh FF List End Marker End Marker
070h 21 CISTPL_FUNCID Function ID Tuple Tuple Code
072h 02 Link is 2bytes Link to next tuple
074h 04 IC Card Function Code Fixed Disk Function TPLFID_FUNCTION
076h 01 RFU, 0 R P System Initialization Bit Mask, TPLFID_SYSINIT
Power-On-Self Test
078h 22 CISTPL_FUNCE Function Extention Tuple Tuple Code
07Ah 02 Link is 2bytes Link to next tuple
07Ch 01 Disk Function Extension Tuple Type Disk Device Interface TPLFE_TYPE
07Eh 01 Interface Type Code PCCard-ATA Interface TPLFE_DATA
080h 22 CISTPL_FUNCE Function Extention Tuple Tuple Code
082h 03 Link is 3bytes Link to next tuple
084h 02 Disk Function Extension Tuple Type Disk Device Interface TPLFE_TYPE
086h 0C RFU U S V Silicon/Rotating, ID/SN is unique TPLFE_DATA
088h 0F R I E N P3 P2 P1 P0 Auto, Idle, Standby, Sleep Mode TPLFE_DATA
supported
08Ah 1A CISTPL_CONFIG Configuration Tuple Tuple Code
08Ch 05 Link is 5bytes Link to next tuple
08Eh 01 RFSZ RMSZ RASZ Size of Fields Byte TPCC_SZ
090h 03 TPCC_LAST Entry Index 03h Last entry of
Configuration table
092h 00 TPCC_RADR Configuration Registers are Location of Config
located at 200h Registers
094h 02 TPCC_RADR
096h 0F RFU S P C I 4 Configuration Registers are TPCC_RMSK
present
098h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
09Ah 08 Link is 8bytes Link to next tuple
09Ch C0 I D Configuration Entry Number Memory Mapped I/O, D: Default TPCE_INDX
Configuration, I: Interface Byte
Follows
09Eh C0 M R W B Interface Type Memory Only Interface, Bvd & WP TPCE_IF
W P V not used, RDY/BSY & Wait used
for Memory Cycle
0A0h A1 M MS I IO T Power Vcc power-description structure only, TPCE_FS
R MS: Single 2-byte length specified
Q M: Misc field structure is present
0A2h 01 R DI PI AI SI H L N Nominal Operating Supply Voltage, Power Parameters for Vcc
V V V No Extension
0A4h 55 X Ah 5h Vcc Nominal is 5V Vcc Nominal Value
0A6h 08 Length in 256 bytes pages(LSB) Length of Mem Space is 2KB TPCE_MS Length LSB
0A8h 00 Length in 256 bytes pages(MSB) Start at 0 on Card TPCE_MS Length MSB
0AAh 20 X R P R A Twin Power Down TPCE_MI
0ACh 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
0AEh 06 Link is 6bytes Link to next tuple
0B0h 00 I D Configuration Entry Number TPCE_INDX
0B2h 01 M MS IR IO T Power Vcc power-description structure only TPCE_FS
Q
0B4h 21 R DI PI AI SI H L N Maximum Current required averaged TPCE_PD
V V V over 10ms, Nominal Operating
Supply Voltage, With Extension
0B6h B5 X 6h 5h 1V x3 Vcc Nominal Value
0B8h 1E X 1Eh(30d) Vcc Nominal is 3.3V
CARD INFORMATION STRUCTURE CONT.
26
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
AttributeOffset Data 76543210Description of Contents CIS Function
0BAh 4D X 9h 5h Peak I is 45mA Peak I Value
0BCh 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
0Beh 0A Link is 10bytes Link to next tuple
0C0h C1 I D Configuration Entry Number I/O Mapped Contiguous 16 TPCE_INDX
Registers Configuration, D: Default
Configuration, I: Interface Byte
Follows
0C2h 41 W R P B Interface Type I/O Interface, Bvd & WP not used, TPCE_IF
RDY/BSY active, Wait not used
for memory access
0C4h 99 M MS IR IO T Power Misc & IRQ field are present, Vcc TPCE_FS
Q power-description structure only
0C6h 01 R D I PI AI SI H L N Nominal Operating supply Voltage TPCE_PD
VVV
0C8h 55 X Ah 5h Vcc Nominal is 5V Vcc Nominal Value
0CAh 64 R Bus 16/8 I/O AddrLines Support 16/8 bit I/O access, TPCE_IO
I/O Address Lines are 16
0CCh F0 S P L M V B I N IRQ Sharing TPCE_IR
S: Share Logic active
P: Pulse IRQ supported
L: Level IRQ supported
M: Bit Mask of IRQ
0CEh F F IRQ Levels to be routed 0-7 TPCE_IR Mask
recommended Extension
0D0h FF IRQ Levels to be routed 8-15 TPCE_IR Mask
recommended Extension
0D2h 20 X R P R A T Power Down supported TPCE_MI
O
0D4h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
0D6h 06 Link is 6 bytes Link to next tuple
0D8h 01 I D Configuration Entry Number TPCE_INDX
0DAh 01 M MS IR IO T Power Vcc power-description structure only TPCE_FS
Q
0DCh 21 R DI PI AI SI H L N Nominal Operating supply Voltage, TPCE_PD
V V V Maximum Current required averaged
over 10ms
0DEh B5 X 6h 5h 1Vx3 Vcc Nominal Value
0E0h 1E X 1Eh(30d) Vcc Nominal is 3.3V
0E2h 4D X 9h 5h Peak I is 45mA Peak I Value
0E4h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
0E6h 0F Link is 15bytes Link to next tuple
0E8h C2 I D Configuration Entry Number TPCE_INDX
0EAh 41 W R P B Interface Type I/O Interface, Bvd & WP not used, TPCE_IF
RDY/BSY active, Wait not used
for memory access
0ECh 99 M MS IR IO T Power Misc & IRQ field are present, Vcc TPCE_FS
Q power-description structure only
0EEh 01 R DI PI AI SI H L N Nominal Operating supply Voltage TPCE_PD
VVV
0F0h 55 X Ah 5h Vcc Nominal is 5V Vcc Nominal Value
CARD INFORMATION STRUCTURE CONT.
27 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
AttributeOffset Data 7 6543210Description of Contents CIS Function
0F2h EA R Bus 16/8 I/O AddrLines I/O range description, Support TPCE_IO
16/8 bit I/O access, A 1 Kbyte
I/O address space
0F4h 61 Size of Size of Number of I/O Length is 1 byte long, Address is I/O Range Description
length address Address Ranges 2 byte long, 1 I/O Address Range Byte
Description field
0F6h F0 Start of I/O Address Block First(LSB)
0F8h 01 Start of I/O Address Block First(MSB)
0FAh 07 First I/O Range Length
0FCh F6 Start of I/O Address Block Second(LSB)
0FEh 03 Start of I/O Address Block Second(MSB)
100h 01 Second I/O Range Length
102h EE S P L M V B I N IRQ Sharing TPCE_IR
S: Share Logic active,
P: Pulse IRQ supported,
L: Level IRQ supported,
V: Vendor-Specific supported,
B: Bus-Error supported,
I: I/O-check supported
104h 20 X R P R A T Power Down supported TPCE_MI
O
106h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
108h 06 Link is 6bytes Link to next tuple
10Ah 02 I D Configuration Entry Number TPCE_INDX
10Ch 01 M MS IR I T Power Vcc power-description structure TPCE_FS
Q O only
10Eh 21 R D I PI AI SI H L N Nominal Operating supply Voltage, TPCE_PD
VVVMaximum Current required
averaged over 10ms
110h B5 X 6h 5h 1Vx3 Vcc Nominal Value
112h 1E X 1Eh(30d) Vcc Nominal is 3.3V
114h 4D X 9h 5h Peak I is 45mA Peak I Value
116h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
118h 0F Link is 15bytes Link to next tuple
11Ah C3 I D Configuration Entry Number TPCE_INDX
11Ch 41 W R P B Interface Type I/O Interface, Bvd & WP not used, TPCE_IF
RDY/BSY active, Wait not used
for memory access
11Eh 99 M MS IR I T Power Misc & IRQ field are present, Vcc TPCE_FS
Q O power-description structure only
120h 01 R D I PI AI SI H L N Nominal Operating supply Voltage TPCE_PD
VVV
122h 55 X Ah 5h Vcc Nominal is 5V Vcc Nominal Value
124h EA R Bus I/O AddrLines I/O range description, Support TPCE_IO
16/8 16/8 bit I/O access, A 1 Kbyte I/O
address space
CARD INFORMATION STRUCTURE CONT.
28
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
AttributeOffset Data 76543210Description of Contents CIS Function
126h 61 Size of Size of Number of I/O Length is 1 byte long, Address is I/O Range Description
length address Address Ranges 2 byte long, 1 I/O Address Range Byte
Description field
128h 70 Start of I/O Address Block First (LSB)
12Ah 01 Start of I/O Address Block First (MSB)
12Ch 07 First I/O Range Length
12Eh 76 Start of I/O Address Block Second(LSB)
130h 03 Start of I/O Address Block Second(MSB)
132h 01 Second I/O Range Length
134h EE S P L M V B I N IRQ Sharing TPCE_IR
S: Share Logic active,
P: Pulse IRQ supported,
L: Level IRQ supported,
V: Vendor-Specific supported,
B: Bus-Error supported,
I: I/O-check supported
136h 20 X R P R A T Power Down supported TPCE_MI
O
138h 1B CISTPL_CFTABLE_ENTRY Configuration Entry Tuple Tuple Code
13Ah 06 Link is 6bytes Link to next tuple
13Ch 03 I D Configuration Entry Number TPCE_INDX
13Eh 01 M MS IR I T Power Vcc power-description structure TPCE_FS
Q O only
140h 21 R D I PI AI SI H L N Nominal Operating supply Voltage, TPCE_PD
V V V Maximum Current required
averaged over 10ms
142h B5 X 6h 5h 1Vx3 Vcc Nominal Value
144h 1E X 1Eh(30d) Vcc Nominal is 3.3V
146h 4D X 9h 5h Peak I is 45mA Peak I Value
148h 14 CISTPL_NO_LINK No Link to Common Memory Tuple Code
14Ah 00 No Bytes Following Link Length is 0 byte Link to next tuple
14Ch FF End of CIS Tuple Chain End of CIS Tuple Code
CARD INFORMATION STRUCTURE CONT.
29 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
True IDE CompactFlashTM
No(#) 40pin No(#) 68pin
1 RESET 41 RESET
2 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL (39)
3D7 6 D7
4D8 47 D8
5D6 5 D6
6D9 48 D9
7D5 4 D5
8 D10 49 D10
9D4 3 D4
10 D11 27 D11
11 D 3 2 D 3
12 D12 28 D12
13 D2 23 D2
14 D13 29 D13
15 D1 22 D1
16 D14 30 D14
17 D0 21 D0
18 D15 31 D15
19 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39)
20 (keypin)
21 DMACK 44 INPACK
22 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39)
23 IOWR 35 IOWR
24 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39)
25 IORD 34 IORD
26 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39)
27 IO RDY 42 WAIT
28 CSEL 39 CSEL
29 DMACK 44 REG
30 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39)
31 IREQ 37 RDY/BSY
32 IOIS16 24 WP
33 A1 19 A1
34 PDIAG 46 BVD1
35 A0 20 A0
36 A2 18 A2
37 CS0 7 CS0
38 CS1 32 CS1
39 DASP 45 BVD2
40 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39)
TRUE IDE TO COMPACTFLASHTM INTERFACE
30
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
7 P 256 CFA45 00 C 25
CARD TECHNOLOGY
7 FLASH
8 SRAM
PC CARD
P Standard
R Ruggedized
CARD CAPACITY
256 256MB
CARD FAMILY AND VERSION
PACKAGING OPTION
00 Standard CF, WEDC logo
TEMPERATURE RANGE
C = Commercial 0°C to +70°C
CARD ACCESS TIME
25 250ns
PART NUMBERING
PRODUCT MARKING
COMPANY NAME
PART NUMBER
LOT CODE/TRACE NUMBER
DATE CODE
WED 7P016CFA4500C25 C995 0322
31 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com
White Electronic Designs
CompactFlashTM Cards
CFA45 Series
XXX (unformatted capacity)
008 8MB
016 16MB
032 32MB
048 48MB
064 64MB
096 96MB
128 128MB
256 256MB
512 512MB
CFA45
Samsung based CompactFlash
SS
00 CompactFlash Type I WEDC logo
01 CompactFlash Type I Blank
T
C Commercial Temperature Range
ZZ
25 250ns
ORDERING INFORMATION
7P XXX CFA45 SS T ZZ
32
White Electronic Designs Corporation Marlborough, MA (508) 485-4000
CompactFlashTM Cards
CFA45 Series
White Electronic Designs
Document Title
CompactFlash Cards - CFA45 Series
Revision History
Rev level Description Date
Rev 0 Initial release May 16, 2003