CompactFlashTM Cards CFA45 Series White Electronic Designs CFA45 Series CompactFlashTM CARDS 8MB to 512MB PRODUCT DESCRIPTION High performance: CFA45 series CompactFlashTM cards are built with NAND flash memory components operating as solid-state disk. They comply with the CompactFlashTM card standard and are suitable for use as a data storage memory medium for PCs or other electronic equipment. The read/write unit is 1 sector (512 bytes) sequential access. Host data transfer rate 20.0 MB/sec Flash data transfer rate 10.0 MB/sec Maximum card density is 512 MB 3 variations of mode access Memory card mode I/O card mode FEATURES True-IDE mode PC Card-ATA/True IDE/ I/O Card mode compatible host interface Internal self-diagnostic program operates at VCC power on Automatic sensing of PC Card ATA and IDE mode High data reliability Included 256-byte CIS ROM Endurance: 100,000 Program / Erase cycles Support the five PC Card ATA addressing modes High reliability based on internal ECC (Error Correcting Code) function 2-bit ECC Host Interface bus width: 8/16-bit Access Flash Interface bus width: 8-bit Access Data reliability is 1 error in 1014 bits read. Support 3 power save mode: standby / idle / active Power Consumption Auto power down function Active mode 2-bit ECC function Operating Voltage: 3.3 V and 5.0 V ISA standard and Read/Write unit is 512 bytes (sector) sequential access 30 mA (typ.), 40 mA (max.) Idle mode 10 mA Stop mode 400 A CARD BLOCK DIAGRAM Vcc GND Internal Vcc Data In/Out Host Interface July 2003 Rev. 0 ECO #16318 Samsung Control Controller 1 Samsung NAND Flash White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs CARD CAPACITIES (CF TYPE I BLANK HOUSING) Capacity Sector/Track Heads 8 MB WED7P008CFA4501C25 Part Number Sectors/Card 15,616 Cylinder 122 32 4 16 MB WED7P016CFA4501C25 31,488 246 32 4 32 MB WED7P032CFA4501C25 62,976 492 32 4 48 MB 64 MB WED7P048CFA4501C25 WED7P064CFA4501C25 94,464 125,952 738 246 32 32 4 16 96 MB WED7P096CFA4501C25 188,928 369 32 16 128 MB WED7P128CFA4501C25 251,904 492 32 16 256 MB WED7P256CFA4501C25 503,808 984 32 16 512 MB WED7P512CFA4501C25 1,029,168 1,021 63 16 PHYSICAL SPECIFICATION The CFA45 series physical specification complies with CompactFlashTM standard card format. CF CARD SIZE AND OUTLINE 0.8mm 0.6mm 42.8mm 36.4 mm 3.3mm BOTTOM 2x 25.78mm 2x 1mm 2x 12mm Pin # 26 Pin # 50 BOTTOM 1.60mm 1.00mm TOP Pin # 1 1.27mm(Pitch) White Electronic Designs Corporation Marlborough, MA (508) 485-4000 Pin # 25 2 CompactFlashTM Cards CFA45 Series White Electronic Designs INTERFACE SPECIFICATION SIGNAL PIN ASSIGNMENTS Pin NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Memory Card Mode Signal name GND D3 D4 D5 D6 D7 CE1 A10 OE A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP CD2 CD1 D11 D12 D13 D14 D15 CE2 VS1 IORD IOWR WE RDY/BSY VCC CSEL VS2 RESET WAIT INPACK REG BVD2 BVD1 D8 D9 D10 GND I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I O O I I/O I/O I/O I/O I/O I/O Card Mode Signal name GND D3 D4 D5 D6 D7 CE1 A10 OE A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16 CD2 CD1 D11 D12 D13 D14 D15 CE2 VS1 IORD IOWR WE IREQ VCC CSEL VS2 RESET WAIT INPACK REG SPKR STSCHG D8 D9 D10 GND 3 I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I O O I I/O I/O I/O I/O I/O True IDE Mode Signal name GND D3 D4 D5 D6 D7 CE1 A10 ATASEL A9 A8 A7 VCC A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16 CD2 CD1 D11 D12 D13 D14 D15 CE2 VS1 IORD IOWR WE INTRQ VCC CSEL VS2 RESET IORDY INPACK REG DASP PDIAG D8 D9 D10 GND I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I/O I/O I/O O O O I/O I/O I/O I/O I/O I O I I I O I O I O O I I/O I/O I/O I/O I/O White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series INTERFACE SIGNALS DESCRIPTION Symbol Type Name and Function A0 - A10 INPUT ADDRESS BUS: These address lines along with the REG signal are used to select the following: The I/O port address registers within the PC Storage Card, the memory mapped port address registers within the PC Storage Card, a byte in the Cards information structure and its configuration control and status registers. This signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. In True IDE Mode only A [2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. D0 - D15 INPUT/ OUTPUT DATA BUS: These signal lines carry the Data, Commands and Status information between the host and the controller. D0 is the LSB of the even byte of the word. D8 is the LSB of the odd byte of the word. This signal is the same as the PC Card memory mode signal in PC Card I/O mode. In True IDE mode, all Task File operations occur in byte mode on the low order bus D0-D7 while all data transfers are 16 bit using D0D15. CE1 , CE2 INPUT CARD ENABLE: CE1 and CE2 are card select signals, active low. These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. CE2 always accesses the odd byte of the word. CE1 accesses the even byte or the Odd byte of the word depending on A0 and CE2. A multiplexing scheme based on A0, CE1 , CE2 allows 8 bit hosts to access all data on D0 -D7. This signal is the same as the PC card memory mode signal in PC Card I/O mode. In the True IDE mode, CE1 is the chip select for the task file registers while CE2 is used to select the Alternate Status Register and the Device Control Register. OE, ASTEL INPUT OUTPUT ENABLE, ATA SELECT: OE is used for the control of data read in Attribute area or Common memory area. To enable True IDE Mode this input should be grounded by the host (in power up). WE INPUT WRITE ENABLE: WE is used for the control of data write in Attribute memory area or Common memory area. This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode, this input signal is not used and should be connected to VCC by the host. IORD INPUT I/O READ: IORD is used for control of read data in the Task File area. This card does not respond to IORD until I/O card interface setting up. IOWR INPUT I/O WRITE: IOWR is used for control of data write in the Task File area. This card does not respond to IOWR until I/O card interface setting up. This signal is not used in memory mode. The I/O write strobe pulse is used to clock I/O data on the card data bus into the CF Card controller registers when the CF Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In True IDE mode, this signal has the same function as in PC Card I/O Mode. RDY/BSY, IREQ, INTRQ OUTPUT READY/BUSY, INTERRUPT REQUEST: In memory mode, this signal is set high when the CF Card is ready to accept a new data transfer operation and held low when the card is busy. The host memory card socket must provide a pull-up resistor. At power up and at reset, the RDY/BSY signal is held low (busy) until the CF Card has completed its power up or reset function. No access of any type should be made to the CF Card during this time. The RDY/BSY signal is held high (disabled from being busy) whenever the following condition is true: The CF Card has been powered up with RESET continuously disconnected or asserted. I/O operation - After the CF Card has been configured for I/O operation, this signal is used as Interrupt request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE mode, this signal is the active high Interrupt request to the host. CD1, CD2 OUTPUT CARD DETECTION: CD1 and CD2 are the card detection signals. CD1 and CD2 are connected to ground in this card, so the host can detect if the card is inserted or not. WP, IOIS16 OUTPUT WRITE PROTECT, 16 BIT I/O PORT: In memory card mode, WP is held low because this card does not have a write protect switch. In the I/O card mode, IOIS16 is asserted when Task File registers are accessed in 16-bit mode. In True IDE Mode this output signal is asserted low when this device is expecting a word data transfer cycle. REG INPUT ATTRIBUTE MEMORY AREA SELECTION: REG should be high level during common memory area accessing, and low level during Attribute area accessing. The attribute memory area is located only in an even address, so D0 to D7 are valid and D8 to D 15 are invalid in the word access mode. Odd addresses are invalid in the byte access mode. The signal must also be active (low) during I/O cycles when the I/O address is on the Bus. In True IDE Mode this input signal is not used and should be connected to VCC. BVD2, SPKR, DASP INPUT/ OUTPUT BATTERY VOLTAGE DETECTION, DIGITAL AUDIO OUTPUT, DISK ACTIVE/SLAVE PRESENT: In memory card mode, BVD2 outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly. In the I/O card mode, SPKR is held High because this card does not have digital audio output. In True IDE Mode DASP is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. RESET, RESET INPUT RESET: By assertion of the RESET signal, all registers of this card are cleared and the RDY/BSY signal turns to high level. In True IDE Mode RESET is the active low hardware reset from the host. White Electronic Designs Corporation Marlborough, MA (508) 485-4000 4 White Electronic Designs CompactFlashTM Cards CFA45 Series INTERFACE SIGNALS DESCRIPTION CONT. Symbol Type Name and Function WAIT, IORDY OUTPUT WAIT: This signal outputs low level for the purpose of delaying memory access cycle or I/O access cycle. In True IDE Mode this output signal may be used as IORDY. As for this controller, this output is high impedance state constantly. INPACK OUTPUT INPUT ACKNOWLEDGE: This signal is not used in the memory card mode. The Input acknowledge signal is asserted by the CF Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CF Card and the CPU. In True IDE mode, this output signal is not used and should be connected to VCC at the host. BVD1, STSCHG, PDIAG INPUT/ OUTPUT BATTERY VOLTAGE DETECTION, STATUS CHANGE, PASS DIAGNOSTIC: In the memory card mode, BVD1 outputs the battery voltage status in the card. This card has no battery, so this output is high level constantly. In the I/O card mode, STSCHG is used for changing the status of the Configuration status register in the Attribute area, while the card is set I/O card interface. In True IDE Mode, PDIAG is the Pass Diagnostic signal in the Master/Slave handshake protocol. VS1, VS2 OUTPUT VCC VOLTAGE SENSE: These signals are intended to notify the socket of the CF Cards CIS V CC requirement. VS1 is held low and VS2 is not connected in this card. CSEL INPUT CARD SELECT: This signal is not used in the memory card mode and I/O card mode. This internally pulled up signal is used to configure this device as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. COMPACTFLASHTM/PCMCIA-ATA REGISTER MAPPING ADDRESS. COMPACTFLASHTM/PCMCIA-ATA I/O MAPPING A DDRESS REG L Primary I/O A[10:0] 1F0H Secondary I/O A[10:0] 170H Independent I/O A[3:0] 0H L 1F1H 171H 1H Error Register Feature Register L 1F2H 172H 2H Sector Count Sector Count L 1F3H 173H 3H Sector Number Sector Number L 1F4H 174H 4H Cylinder Low Cylinder Low L 1F5H 175H 5H Cylinder High Cylinder High L 1F6H 176H 6H Drive/Head Drive/Head L 1F7H 177H 7H Status Register Command L - - 8H Duplicate Read Even Data Duplicate Write Even Data L - - 9H Duplicate Read Odd Data Duplicate Write Odd Data L - - 0DH Duplicate Error Duplicate Feature L L 3F6H 3F7H 376H 377H 0EH 0FH Alternate Status Drive Address Device Control Reserved 5 IORD = L IOWR = L Read Even Data Write Even Data White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs COMPACTFLASHTM /PCMCIA-ATA MEMORY MAPPING ADDRESS REG H A10 L A[9:4] X A[3] L A[2] L A[1] L A[0] L H L X L H L X L H L X H L X H L H H H IORD = L Read Data IOWR = L Write Data L L H Error Register Feature L H L Sector Count Sector Count L L H H Sector Number Sector Number L H L L Cylinder Low Cylinder Low X L H L H Cylinder High Cylinder High L X L H H L Drive/Head Drive/Head L X L H H H Status Register Command L X H L L L Duplicate Read Even Data Duplicate Write Even Data H L X H L L H Duplicate Read Odd Data Duplicate Write Odd Data H L X H H L H Duplicate Error Duplicate Feature H H L L X X H H H H H H L H Alternate Status Drive Address Device Control Reserved H H X X X X L Read Even Data Write Even Data H H X X X X H Read Odd Data Write Odd Data THE ATA REGISTERS AND PCMCIA REGISTERS STATUS REGISTER DIRECTION - This register is read-only by the host. ACCESS RESTRICTION - The contents of this register, except for BSY, will be ignored when BSY is set to one. BSY is valid at all time. The contents of the register and all other Command Block registers are not valid while a device is in the Sleep mode. FUNCTIONAL DESCRIPTION - This register contains the device status. The contents of this register are updated to reflect the current state of the device and the progress of any command being executed by the device. BIT DESCRIPTION 7 BSY BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 6 DRDY 5 DF 4 DSC 3 DRQ 2 CORR 1 IDX 0 ERR ERR (Error) indicates that an error occurred during execution of the previous command. The Error register has additional information regarding the cause of the error when this bit is asserted. IDX (Index) is vendor specific. CORR (Corrected Data) is used to indicate a correctable data error. The definition of what constitutes a correctable error is vendor specific. DRQ (Data Request) indicates that the device is ready to transfer a word or byte between the host and the device. DSC (Device Seek Complete) indicates that the device heads are settled over a track. DF (Device Fault) indicates a device fault error has been detected. The internal status or internal conditions that causes this error to be indicated is vendor specific. DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codes. This bit will be cleared at power on. BSY (Busy) is set whenever the device has control of the command block registers. When the BSY bit is equal to one, the commands written to this register will be ignored by the device. White Electronic Designs Corporation Marlborough, MA (508) 485-4000 6 White Electronic Designs CompactFlashTM Cards CFA45 Series COMMAND REGISTER DIRECTION - This register is write-only by host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. The contents of this register and all other Command Block registers are not valid while a device is in the Sleep mode. FUNCTIONAL DESCRIPTION - This register contains the command code being sent to the device. Command execution begins immediately after this register is written. BIT DESCRIPTION 7 6 5 4 3 Command Code 2 1 0 ERROR REGISTER DIRECTION - This register is read-only by host. ACCESS RESTRICTION - The contents of this register shall be valid when BSY and DRQ are equal to zero and ERR is asserted. FUNCTIONAL DESCRIPTION - This register contains the operation status for the current command. BIT DESCRIPTION 7 R BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 6 UNC 5 MC 4 IDNF 3 MCR 2 ABRT 1 TKONF 0 AMNF AMNF (Address Mark Not Found) indicates the data address mark has not been found after finding the correct ID field. TKONF (Track 0 Not Found) indicates the track 0 has not been found during a RECALIBRATE command. ABRT (Aborted Command) indicates the requested command has been aborted because the command code or a command parameter is invalid or some other error has occurred. MCR (Media Change Requested) is used by removable media devices. IDNF (ID Not Found) indicates the requested sectors ID field could not be found. MC (Media Change) is used by removable media devices. UNC (Uncorrectable Data Error) indicate an uncorrectable data error has been encountered. Reserved FEATURE REGISTER DIRECTION - This register is write-only by host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - This register is command specific. BIT DESCRIPTION 7 6 5 4 3 Command Specific 7 2 1 0 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series SECTOR NUMBER REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the starting sector number for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 7-0 of the LBA for any media access. BIT DESCRIPTION CHS 7 6 5 4 3 Sector (7:0) 2 1 0 2 1 0 LBA 7 6 5 4 3 LBA (7:0) SECTOR COUNT REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - This register contains the number of sector of data requested to be transferred on a read or write operation between the host and the device. If the value in this register is zero, a count of 256 sectors is specified. BIT DESCRIPTION 7 6 5 4 3 Sector Count 2 1 0 CYLINDER LOW REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the low order bits of the starting cylinder address for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 15-8 of the LBA for any media access. BIT DESCRIPTION CHS 7 6 5 4 3 Cylinder (7:0) 2 1 0 2 1 0 LBA 7 6 5 White Electronic Designs Corporation Marlborough, MA (508) 485-4000 4 3 LBA (15:8) 8 White Electronic Designs CompactFlashTM Cards CFA45 Series CYLINDER HIGH REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - If the LBA bit is cleared to zero in the Device/Head register, this register contains the low order bits of the starting cylinder address for any media access. If the LBA bit is set to one in the Device/Head register, this register contains Bits 23-16 of the LBA for any media access. BIT DESCRIPTION CHS 7 6 5 4 3 Cylinder (7:0) 2 1 0 2 1 0 LBA 7 6 5 4 3 LBA (15:8) DEVICE/HEAD REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRICTION - This register is write-only when BSY and DRQ are both equal to zero. FUNCTIONAL DESCRIPTION - This register selects the device, defines address translation as CHS or LBA, and provides the head address if CHS mode or LBA (27:24) if LBA mode. BIT DESCRIPTION CHS (CYLINDER-HEAD-SECTOR) 7 1 6 LBA 5 1 4 DEV 3 HS3 2 HS2 1 HS1 0 HS0 2 (27:24) 1 0 LBA (LOGIC BLOCK ADDRESS) 7 1 6 LBA 5 1 4 DEV 3 LBA BIT 0~3 If LBA is equal to zero (CHS), these contain the head address of the starting CHS address. The HS3 bit is the most significant bit. If LBA is equal to one (LBA), these bits represent bits 27 through 24 of the LBA. BIT 4 DEV is the device address. When the DEV bit is equal to zero, Device 0 is selected. When the DEV bit is equal to one, Device 1 is selected. BIT 5 Bit 5 is set to one for backward compatibility. BIT 6 LBA mode if this bit is set to one, otherwise, CHS mode. BIT 7 Bit 7 is set to one for backward compatibility. 9 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series DATA REGISTER DIRECTION - This register is bi-directional for the drive and host. ACCESS RESTRUCTIONS - This register can be written or the content is valid on read when DRQ is set to one. FUNCTIONAL DESCRIPTION - The data register is 16-bit wide. BIT DESCRIPTION 15 14 13 12 7 6 5 4 11 Data (15:8) 10 9 8 3 2 1 0 1 0 Data (7:0) PCMICA CONFIGURATION OPTION REGISTER DIRECTION - This register is read-only by host. FUNCTION DESCRIPTION - Direct map to 0x200H in the Attribute Memory. BIT DESCRIPTION 7 SRESET 6 LevlReq 5 4 3 2 Configuration Index BIT 0~5 Configuration Index: 0 : common memory mode 1 : Independent IO mode 2 : Primary IO mode 3 : Secondary IO mode BIT 6 LevlReq (level Mode IREQ#) : Level Mode Interrupts are selected when this bit is set to one, otherwise it is Pulse Mode Interrupts. BIT 7 SRESET (Soft Reset): Setting this bit to one places the card in the reset state. This is equivalent to assertion of the RESET signal. PCMICA CARD CONFIGURATION AND STATUS REGISTER DIRECTION - This register is bi-directional for the drive and host. FUNCTION DESCRIPTION - Direct map to 0x202H in the Attribute Memory. BIT DESCRIPTION 7 SCDect BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 6 SigChg 5 IOis8 4 ResrV 3 SPKR/DASP 2 PwrDn 1 Intr 0 ResrV Reserved Intr (Interrupt Request Pending) : The real time status of the host interrupt signal pin. PwrDn (Power Down): This bit will enable the power down mode. SPKR/DASP: Setting this bit to 1 will enable DASP- to the BVD2 pin of the PCMCIA connector, otherwise, the BVD2 will be held at high-impedance. ResrV: Reserved bit must be 0. IOis8 (I/O Cycles Occur Only as 8-bit Transfer): When the host can provide I/O cycle only using the D7:D0 data path, the PCMCIA software will set this bit to 1. White Electronic Designs Corporation Marlborough, MA (508) 485-4000 10 White Electronic Designs BIT 6 BIT 7 CompactFlashTM Cards CFA45 Series SigChg (Signal Change Enable/Disable): If this bit is set to one, the Signal Changed output is enabled. SCDect (Status Change Detected): This bit indicates that at least one bit of the Pin replacement Register is set one. PCMICA PIN REPLACEMENT REGISTER DIRECTION - This register is read-only by host. FUNCTION DESCRIPTION - Direct map to 0x204H in the Attribute Memory. BIT DESCRIPTION 7 ResrV 6 ResrV BIT 0 BIT 1 BIT 2~3 BIT 4 BIT 5 BIT 6~7 5 CRdy 4 CWProt 3 ResrV 2 ResrV 1 CSRdy 0 CSWProt CSWProt (Current State of Write Protect) : This bit represents the current the state of the Write Protect. CSRdy (Current State of Ready) : This bit represents the internal state of the READY signal. Reserved. CWProt (Change Write Protect) : This bit is set to one when CSWProt changes state. CRdy (Changed Ready) : This bit is set to one when CSRdy changes state. ResrV : Reserved bit must be 0. PCMICA SOCKET AND COPY REGISTER DIRECTION - This register is bi-directional for the drive and host. FUNCTION DESCRIPTION - Direct map to 0x206H in the Attribute Memory. BIT DESCRIPTION 7 6 ResrV 5 4 Copy Number 3 2 1 Socket Number 0 BIT 0~2 Socket Number : The first Socket is numbered 0. BIT 3~5 Copy Number BIT 6~7 ResrV : Reserved bit must be 0. 11 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol Parameter Ratings VDD Supply voltage VIN Input voltage I IN TSTG DC input current Storage temperature Unit 0.3 to + 7.0 V 0.3 to V DD + 0.3 V 10 40 to + 80 mA C RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter DC supply voltage Ta 5V 3.3V Storage temperature Ratings Unit 4.5 to + 5.5 3.0 to 3.6 V V 0 to + 60 C D.C. ELECTRICAL CHARACTERISTICS @ 3.3V (TA = 0 TO +60C, VCC = 3.3V 5%) Symbol Parameter Conditions VIH High level input voltage CMOS VIL Low level input voltage CMOS VT Switching threshold CMOS VT+ Switching trigger, positive-going threshold CMOS V T- Switching trigger, negative-going threshold CMOS I IH High level input current I IL Low level input current VIN = VDD Input buffer VIN = VSS VOH High level output voltage I OH = 8 mA VOL Low level output voltage I OL = 8 mA VOUT = VSS or VDD Maximum operating current Iidle Idle current Ids Stop current White Electronic Designs Corporation Marlborough, MA (508) 485-4000 Unit 1.0 V 2.0 V V V 1.0 Input buffer with pull-up Tri-state output leakage current Max 1.4 Input buffer I OZ Typ 2.0 Input buffer with pull-up I DD Min VDD = 5.0V, fMCLK = 20 MHz 12 V 10 10 10 30 60 30 10 10 160 10 2.4 uA uA V 0.4 10 30 V 10 uA 40 mA 10 mA 300 uA CompactFlashTM Cards CFA45 Series White Electronic Designs ELECTRICAL CHARACTERISTICS @ 5V (TA = 0 TO 60C, VCC = 5V 10%) Symbol Parameter Conditions VIH High level input voltage CMOS TTL VIL Low level input voltage CMOS TTL VT Switching threshold CMOS TTL VT+ Switching trigger, positive-going threshold CMOS TTL V T- Switching trigger, negative-going threshold CMOS TTL I IH High level input current I IL Low level input current 1.0 0.8 Input buffer VIN = VSS VOH High level output voltage I OH = 8 mA VOL Low level output voltage I OL = 8 mA VOUT = VSS or VDD Maximum operating current Iidle Idle current Ids Stop current 10 10 50 100 50 10 10 2.4 uA uA V 0.4 10 VDD = 5.0V, V V 10 10 100 V V 4.0 2.0 VIN = VDD Unit V 2.5 1.4 Input buffer with pull-up Tri-state output leakage current Max 1.5 0.8 Input buffer with pull-up I OZ Typ 3.5 2.0 Input buffer I DD Min 30 fMCLK = 24 MHz V 10 uA 40 mA 10 mA 400 uA ENVIRONMENTAL AND RELIABILITY SPECIFICATIONS ITEM SPECIFICATION Vibration Operating Non-Operating 15G peak to peak Max. 15G peak to peak Max. Shock Operating Non-Operating 2,000G Max. 2,000G Max. Relative Humidity (non-condensing) Operating Non-Operating 8% ~ 95% 8% ~ 95% MTBF Operating > 1,000,000 hours Endurance Operating 100,000 erase program cycles Data Reliability Operating < 1 non-recoverable error in 10 14 bits read 13 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs INTERFACE SIGNAL TIMING There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card Standard. The PC Card conforms to the timing in that reference document. PC CARD INTERFACE A TTRIBUTE MEMORY READ TIMING Parameter Symbol IEEE Symbol 300ns Min. ns Max. ns Read Cycle Time tC(R) TAVAV Address Access Time tA(A) TAVQV 300 Card Enable Access Time tA(CE) TELQV 300 Output Enable Access Time tA(OE) TGLQV 150 Output Disable Time from CE tDIS (CE) TEHQZ 100 Output Disable Time from OE tDIS(OE) TGHQZ tSU (A) t AVWL 30 Address Setup Time 300 100 Output Enable Time from CE t EN(CE) t ELQNZ 5 Output Enable Time from OE tEN(OE) tGLQNZ 5 tV(A) t AXQX 0 Data Valid from Address Change NOTE: All times are in nanosecond. Dout signifies data provided by the PC Card to the system. The CE signal or both the OE signal & the WE signal must be de-asserted between consecutive cycle operations. ATTRIBUTE MEMORY READ TIMING DIAGRAM tC (R) An tA (A) REG tSU (A) tV (A) tA (CE) CE tEN (CE) tDIS (CE) tA (OE) OE tDIS (OE) tEN (OE) DOUT White Electronic Designs Corporation Marlborough, MA (508) 485-4000 14 CompactFlashTM Cards CFA45 Series White Electronic Designs A TTRIBUTE MEMORY WRITE TIMING Note: A host cannot write to CIS. This timing is specified only for the write to Configuration Register. Parameter Symbol IEEE Symbol 250ns Min. ns Max. ns Write Cycle Time tC(W) tAVAV 250 Write Pulse Width tW(WE) t WLWH 150 tSU (A) t AVWL 30 tREC (WE) t WMAX 30 tSU (D-WEH) t DVWH 80 tH(D) t WMDX 30 Address Setup Time Write Recovery Time Data Setup Time for WE Data Hold Time NOTE: All times are in nanosecond. Din signifies data provided by the system to the PC Card. ATTRIBUTE MEMORY WRITE TIMING DIAGRAM tC (W) REG An tREC (WE) tSU (A) tW (WE) WE tSU (D-WEH) tH (D) CE OE DOUT Data In Valid 15 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs COMMON MEMORY READ TIMING Parameter Symbol IEEE Symbol Output Enable Access Time ta (OE) tGLQV 125 tdis (OE) tGHQZ 100 Output Disable Time from OE Min. ns Address Setup Time tsu (A) tAVGL 30 Address Hold Time th (A) tGHAX 20 CE Setup before OE tsu (CE) tELGL 0 CE Hold following OE th (CE) tGHEH 20 Max. ns Wait Delay Falling from OE tv (WT-OE) tGLWTV Data Setup for Wait Release tv (WT) tQVWTH 35 0 Wait Width Time tw (WT) tWTLWTH 350 NOTE: The maximum load on WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. DOUT signifies data provided by the PC Card to the system. The WAIT signal may be ignored if the OE cycle-to-cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. COMMON MEMORY READ TIMING DIAGRAM An tSU (A) tH (A) REG CE tH (CE) tSU (CE) tDIS (CE) tA (OE) OE tW (WT) WAIT tDIS (OE) tV (WT-OE) tV (WT) DOUT White Electronic Designs Corporation Marlborough, MA (508) 485-4000 16 CompactFlashTM Cards CFA45 Series White Electronic Designs COMMON MEMORY WRITE TIMING Parameter Data Setup before WE Data Hold following WE Symbol IEEE Symbol Min. ns tsu (D-WEH) tDVWH 80 th (D) tlWMDX 30 tw (WE) tWLWH 150 Address Setup Time tsu (A) tAVWL 30 CE Setup before WE tsu (CE) tELWL 0 Write recovery Time trec (WE) tWMAX 30 WE Pulse Width Address Hold Time CE Hold following WE th (A) tGHAX 20 th (CE) tGHEH 20 Wait Delay Falling from WE tv (WT-WE) tWLWTV WE High from Wait Release tv (WT) tWTHWH Wait Width Time tw (WT) tWTLWTH Max. ns 35 0 350 NOTE: The maximum load on WAIT is 1 LSTTL with 50pF total load. All times are in nanoseconds. DIN signifies data provided by the system to the PC Card. The WAIT signal may be ignored if the WE cycle-to-cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. COMMON MEMORY WRITE TIMING DIAGRAM An tSU (A) tH (A) REG tH (CE) tSU (CE) CE tREC (WE) tW (WE) WE tW (WT) WAIT tV (WT) tV (WT-WE) tH (D) tSU (D-WEH) DIN DIN Valid 17 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs I/O INPUT (READ) TIMING Parameter Symbol IEEE Symbol Data Delay after IORD td (IORD) tlGLQV Data Hold following IORD th (IORD) tlGHQX 0 IORD Width Time Min. ns 100 tw (IORD) tlGLIGH 165 Address Setup before IORD tsuA (IORD) tAVIGL 70 Address Hold following IORD thA (IORD) tlGHAX 20 CE Setup before IORD tsuCE (IORD) tELIGL 5 CE Hold following IORD thCE (IORD) tlGHEH 20 REG Setup before IORD (IORD) REG Hold following IORD tsuREG tRGLIGL 5 thREG (IORD) tlGHRGH 0 0 INPACK Delay Falling from IORD tdfINPACK (IORD) tlGLIAL INPACK Delay Rising from IORD tdrINPACK (IORD) tlGHIAH Max. ns 45 45 IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35 35 Wait Delay Falling from IORD tdWT (IORD) tlGLWTL Data Delay from Wait Rising td (WT) tWTHQV 0 Wait Width Time tw (WT) tWTLWTH 350 NOTE: The maximum load on WAIT, INPACK and IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT high to IORD high is 0nsec, but minimum IORD width must still be met. DOUT signifies data provided by the PC Card to the system. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. I/O READ TIMING DIAGRAM An tSU (IORD) tHA (IORD) tSUREG (IORD) REG tHRE (IORD) tSUCE (IORD) CE tHCE (IORD) tWIORD IORD tDRINPACK (IORD) tDFINPACK (IORD) INPACK tDRIOIS16 (ADR) tD (IORD) IOIS16 tDFIOIS16 (ADR) WAIT tDWT (IORD) tD (WT) tW (WT) DOUT White Electronic Designs Corporation Marlborough, MA (508) 485-4000 18 tH (IORD) CompactFlashTM Cards CFA45 Series White Electronic Designs I/O INPUT (WRITE) TIMING Parameter Data Setup before IOWR Symbol IEEE Symbol Min. ns tsu (IOWR) tDVIWH 60 Data Hold following IOWR th (IOWR) tlWHDX 30 IOWR Width Time tw (IOWR) tlWLIWH 165 Address Setup before IOWR tsuA (IOWR) tAVIWL 70 Address Hold following IOWR thA (IOWR) tlWHAX 20 CE Setup before IOWR tsuCE (IOWR) tELIWL 5 CE Hold following IOWR thCE (IOWR) tlWHEH 20 REG Setup before IOWR tsuREG (IOWR) tRGLIWL 5 REG Hold following IOWR thREG (IOWR) tlWHRGH 0 Max. ns IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35 Wait Delay Falling from IOWR tdWT (IOWR) tlWLWTL IOWR high from Wait high tdrIOWR (WT) tWTJIWH tw (WT) tWTLWTH Wait Width Time 35 0 350 NOTE: The maximum load on WAIT, INPACK, and IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT high to IOWR high is 0nsec, but minimum IOWR width must still be met. DIN signifies data provided by the system to the PC Card. The Wait Width time meets the PCMCIA specification of 12s but is intentionally less in this specification. I/O WRITE TIMING DIAGRAM An tSU (IOWR) tHA (IOWR) tSUREG (IOWR) REG tHRE (IOWR) tSUCE (IOWR) CE tHCE (IOWR) tWIORD IOWR tDRIOIS16 (ADR) IOIS16 tDFIOIS16 (ADR) tSU (IOWR) tW (WT) WAIT tDWT (IOWR) tDRIOWR (WT) tH (IOWR) DIN 19 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs IDE MODE INTERFACE IDE MODE READ TIMING Parameter Symbol IEEE Symbol Data Delay after IORD td (IORD) tlGLQV Data Hold following IORD th (IORD) tlGHQX 0 IORD Width Time Min. ns Max. ns 100 tw (IORD) tlGLIGH 165 Address Setup before IORD tsuA (IORD) tAVIGL 70 Address Hold following IORD thA (IORD) tlGHAX 20 CE Setup before IORD tsuCE (IORD) tELIGL 5 CE Hold following IORD thCE (IORD) tlGHEH 20 IOIS16 Delay Falling from Address tdfIOIS16 (ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16 (ADR) tAVISH 35 NOTE: The maximum load on IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT high to IORD high is 0nsec, but minimum IORD width must still be met. DOUT signifies data provided by the PC Card to the system. IDE MODE READ TIMING DIAGRAM An tSU (IORD) tHA (IORD) tSUCE (IORD) CE tHCE (IORD) tWIORD IORD tD (IORD) tDRIOIS16 (ADR) IOIS16 tDFIOIS16 (ADR) tH (IORD) DOUT White Electronic Designs Corporation Marlborough, MA (508) 485-4000 20 CompactFlashTM Cards CFA45 Series White Electronic Designs IDE MODE WRITE TIMING Parameter Data Setup before IOWR Symbol IEEE Symbol Min. ns tsu(IOWR) tDVIWH 60 Data Hold following IOWR th(IOWR) tlWHDX 30 IOWR Width Time twI(OWR) tlWLIWH 165 Address Setup before IOWR tsuA(IOWR) tAVIWL 70 Address Hold following IOWR thA(IOWR) tlWHAX 20 CE Setup before IOWR tsuCE(IOWR) tELIWL 5 CE Hold following IOWR thCE(IOWR) tlWHEH 20 Max. ns IOIS16 Delay Falling from Address tdfIOIS16(ADR) tAVISL 35 IOIS16 Delay Rising from Address tdrIOIS16(ADR) tAVISH 35 NOTE: The maximum load on IOIS16 is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT high to IOWR high is 0nsec, but minimum IOWR width must still be met. DIN signifies data provided by the system to the PC Card. IDE MODE WRITE TIMING DIAGRAM An tSU (IOWR) tHA (IOWR) tSUCE (IOWR) CE tHCE (IOWR) tWIOWR IOWR tDRIOIS16 (ADR) IOIS16 tDFIOIS16 (ADR) tSU (IOWR) tH (IOWR) DIN 21 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs RESET TIMING Parameter Symbol Min Level Set before Power On tset 1 Typ Max Unit Power on Reset tpor 10 ms Reset time trst 10 ms ms RESET TIMING DIAGRAM VCC POR (Internal) Reset Pin TRST TPOR RDY/BSY Pin TSET OE Pin CSEL Pin POWER ON RESET CHARACTERISTICS All card status are reset automatically when VCC voltage goes over about 2.3 V. Parameter Symbol Min Typ Max Unit CE setup time tsu(VCC ) 100 ms tpr 0.1 100 ms VCC rising up time POWER ON RESET TIMING Test conditions t PR VCC tSU(VCC) CE1 , CE 2 Please notice that the card insertion/removal should be executed after card internal operations are completed (status register bit 7 turns from 1 to 0). Attention for Card Use In the reset or power off, all register information is cleared. Before the card insertion Vcc cannot be supplied to the card. After confirmation that CD1, CD2 pins are inserted, supply Vcc to the card. All card status are cleared automatically when Vcc voltage turns below about 2.5V. Notice that the card insertion/removal should not be executed during host is active, if the card is used in true IDE mode. OE must be kept at the Vcc level during power on reset in memory card mode and I/O card mode. OE must be kept constantly at the GND level in True IDE mode. After the card hard reset, soft reset, or power on reset, the card cannot access during +READY pin is low level. White Electronic Designs Corporation Marlborough, MA (508) 485-4000 Unused pins of data bus (D0 to D15) signals should not be opened. 22 CompactFlashTM Cards CFA45 Series White Electronic Designs CARD INFORMATION STRUCTURE (CIS) & IDENTIFY DRIVE (ID) INFORMATION IDENTIFY DRIVE INFORMATION Word 8MB 16MB 32MB 48MB 64MB 96MB 128MB 0 848A 848A 848A 848A 848A 848A 848A 848A 1 007A 00F6 01EC 02E2 00F6 0171 01EC 03D8 2 0000 0000 0000 0000 0000 0000 0000 0000 3 0004 0004 0004 0004 0010 0010 0010 0010 4 0000 0000 0000 0000 0000 0000 0000 0000 5 0200 0200 0200 0200 0200 0200 0200 0200 6 0020 0020 0020 0020 0020 0020 0020 0020 7-8 0000 0000 0000 0001 0001 0002 0003 0007 3D00 7B00 F600 7100 EC00 E200 D800 B000 9 256MB 0000 0000 0000 0000 0000 0000 0000 0000 All 2020 0000 All 2020 0000 All 2020 0000 All 2020 0000 All 2020 0000 All 2020 0000 All 2020 0000 All 2020 0000 21 0002 0002 0002 0002 0002 0002 0002 0002 22 0004 0004 0004 0004 0004 0004 0004 0004 23-26 *1 *1 *1 *1 *1 *1 1 *1 27-46 *2 *2 *2 2 *2 *2 *2 *2 47 0004 0004 0004 0004 0004 0004 0004 0004 48 0000 0000 0000 0000 0000 0000 0000 0000 49 0200 0200 0200 0200 0200 0200 0200 0200 50 0000 0000 0000 0000 0000 0000 0000 0000 51 0200 0200 0200 0200 0200 0200 0200 0200 52 53 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 0000 0001 54 007A 00F6 01EC 02E2 00F6 0171 01EC 03D8 55 0004 0004 0004 0004 0010 0010 0010 0010 56 0020 0020 0020 0020 0020 0020 0020 0020 57-58 3D00 7B00 F600 7100 EC00 E200 D800 B000 0007 10-19 20 0000 0000 0000 0001 0001 0002 0003 59 0100 0100 0100 0100 0100 0100 0100 0100 60-61 3D00 7B00 F600 7100 EC00 E200 D800 B000 62-127 128 0000 0000 0000 0001 0001 0002 0003 0007 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 0000 0000 0000 0000 0000 0000 0000 0000 129-159 160 All 0000 0000 All 0000 0000 All 0000 0000 All 0000 0000 All 0000 0000 All 0000 0000 All 0000 0000 All 0000 0000 161-255 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 All 0000 Note 1. Firmware Version: Rev 1.15 (52 65 76 20 31 2E 31 35) 2. Model Number: SAMSUNG CF/ATA (53 41 4d 53 55 4e 47 20 43 46 2f 41 54 41 20 20 20 20 20 20) 23 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com CompactFlashTM Cards CFA45 Series White Electronic Designs CARD INFORMATION STRUCTURE AttributeOffset 000h 002h 004h Data 01 04 DF 006h 008h 00Ah 00Ch 00Eh 010h 012h 4A 01 FF 1C 04 02 D9 014h 016h 018h 01Ah 01Ch 01Eh 01 FF 18 02 DF 01 020h 022h 024h 026h 028h 02Ah 02Ch 20 04 CE 00 00 00 15 02Eh 030h 032h 034h 036h 038h 03Ah 03Ch 03Eh 040h 042h 044h 046h 048h 04Ah 04Ch 04Eh 050h 052h 054h 056h 058h 05Ah 05Ch 05Eh 060h 062h 064h 066h 068h 20 04 01 53 41 4D 53 55 4E 47 20 20 20 20 20 20 00 52 65 76 20 31 2E 31 35 20 20 20 20 20 7 6 5 4 CISTPL_DEVICE 3 2 Device Type Code Dh=I/O X 9h Device Size List End Marker CISTPL_DEVICE_OC W 1 Speed 7h 2h 0 Reserved, 0 Device Type Code Dh=I/O Device Size List End Marker CISTPL_JEDEC_C W 1 1 0 VccU Speed 1h M PCMCIA Manufacture s ID PCMCIA Code for PC Card-ATA No Vpp Required CISTPL_MANFID Description of Contents Device Info Tuple Link is 4bytes I/O device, No Write Protects, Device Speed = 400ns 2Kbyte of address Space End of Devices Other Condition Device Info Tuple Link is 4bytes 3.3V Vcc Operation I/O device, No Write Protects, Device Speed=250ns 2Kbyte of address Space End of Devices JEDEC ID Common Mem Link is 2bytes First Byte of JEDEC ID Second Byte of JEDEC ID Manufacture ID String Link is 4bytes PC Card Manufactures ID Code Manufacture Information CISTPL_VERS_1 Level 1 Version/Product Infor mation Link is 20bytes PCMCIA 2.1 JEIDA 4.2 S A M S U N G Name of Manufacture Major Version Number Minor Version Number Manufacture Information End of Manufacture Information Product Information White Electronic Designs Corporation Marlborough, MA (508) 485-4000 Null Terminator R e v 1 . 1 5 24 Firmware Revision CIS Function Tuple Code Link to next tuple Device ID WPS, Speed Device Size End Marker Tuple Code Link to next tuple OC Info Device ID WPS, Speed Device Size End Marker Tuple Code Link to next tuple JEDEC ID of Device 1 JEDEC ID Tuple Code Link to next tuple TPLMID_MANF TPLMID_MANF TPLMID_CARD TPLMID_CARD Tuple Code Link to next tuple TPLLV1_MAJOR TPLLV1_MINOR String 1 End String 1 String 2 White Electronic Designs CompactFlashTM Cards CFA45 Series CARD INFORMATION STRUCTURE CONT. AttributeOffset 06Ah 06Ch 06Eh 070h 072h 074h 076h Data 00 00 FF 21 02 04 01 7 6 5 4 3 2 End of Product Information End of CIS Revision Number List End Marker CISTPL_FUNCID 078h 07Ah 07Ch 07Eh 080h 082h 084h 086h 088h 22 02 01 01 22 03 02 0C 0F CISTPL_FUNCE 08Ah 08Ch 08Eh 090h 1A 05 01 03 CISTPL_CONFIG 092h 00 TPCC_RADR 094h 096h 02 0F TPCC_RADR RFU 098h 09Ah 09Ch 1B 08 C0 CISTPL_CFTABLE_ENTRY 09Eh IC Card Function Code RFU, 0 1 0 R Disk Function Extension Tuple Type Interface Type Code CISTPL_FUNCE Disk Function Extension Tuple Type RFU U S R I E N P3 P2 P1 RFSZ TPCC_LAST RMSZ S P D C0 M W R 0A0h A1 M 0A2h 01 R 0A4h 0A6h 0A8h 0AAh 0ACh 0AEh 0B0h 0B2h 55 08 00 20 1B 06 00 01 X Ah Length in 256 bytes pages(LSB) Length in 256 bytes pages(MSB) X R P R A Twin CISTPL_CFTABLE_ENTRY 0B4h 21 R 0B6h 0B8h B5 1E X X I M Function ID Tuple Link is 2bytes Fixed Disk Function P System Initialization Bit Mask, Power-On-Self Test Function Extention Tuple Link is 2bytes Disk Device Interface PCCard-ATA Interface Function Extention Tuple Link is 3bytes Disk Device Interface V Silicon/Rotating, ID/SN is unique P0 Auto, Idle, Standby, Sleep Mode supported Configuration Tuple Link is 5bytes RASZ Size of Fields Byte Entry Index 03h Configuration Registers are located at 200h I C I Configuration Entry Number W P MS DI Description of Contents Null Terminator Null Terminator PI B V Interface Type I R Q AI IO T Power SI H V L V 5h N V D Configuration Entry Number MS IR IO T Power Q DI PI AI SI H L N V V V 6h 5h 1Eh(30d) 25 4 Configuration Registers are present Configuration Entry Tuple Link is 8bytes Memory Mapped I/O, D: Default Configuration, I: Interface Byte Follows Memory Only Interface, Bvd & WP not used, RDY/BSY & Wait used for Memory Cycle Vcc power-description structure only, MS: Single 2-byte length specified M: Misc field structure is present Nominal Operating Supply Voltage, No Extension Vcc Nominal is 5V Length of Mem Space is 2KB Start at 0 on Card Power Down Configuration Entry Tuple Link is 6bytes Vcc power-description structure only CIS Function End String 2 End Marker Tuple Code Link to next tuple TPLFID_FUNCTION TPLFID_SYSINIT Tuple Code Link to next tuple TPLFE_TYPE TPLFE_DATA Tuple Code Link to next tuple TPLFE_TYPE TPLFE_DATA TPLFE_DATA Tuple Code Link to next tuple TPCC_SZ Last entry of Configuration table Location of Config Registers TPCC_RMSK Tuple Code Link to next tuple TPCE_INDX TPCE_IF TPCE_FS Power Parameters for Vcc Vcc Nominal Value TPCE_MS Length LSB TPCE_MS Length MSB TPCE_MI Tuple Code Link to next tuple TPCE_INDX TPCE_FS Maximum Current required averaged TPCE_PD over 10ms, Nominal Operating Supply Voltage, With Extension 1V x3 Vcc Nominal Value Vcc Nominal is 3.3V White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series CARD INFORMATION STRUCTURE CONT. AttributeOffset 0BAh 0BCh 0Beh 0C0h Data 4D 1B 0A C1 7 6 5 4 3 X 9h CISTPL_CFTABLE_ENTRY I D 0C2h 41 W R 0C4h 99 M 0C6h 01 R DI 0C8h 0CAh 55 64 X R Bus 16/8 I/O AddrLines 0CCh F0 S P M 0CEh FF 0D0h FF 0D2h 20 0D4h 0D6h 0D8h 0DAh 1B 06 01 01 0DCh X 1 5h 0 Configuration Entry Number P MS PI B Interface Type IR Q AI IO T Power SI H V L V 5h N V I N Ah L R V R A O CISTPL_CFTABLE_ENTRY P I M D 21 R DI 0DEh 0E0h 0E2h 0E4h 0E6h 0E8h 0EAh B5 1E 4D 1B 0F C2 41 X 6h X 1Eh(30d) X 9h CISTPL_CFTABLE_ENTRY 0ECh 99 M 0EEh 01 R 0F0h 55 X I W 2 MS D R T P 5h 5h Configuration Entry Number B Interface Type PI IR Q AI IO T Power SI H V L V 5h Ah White Electronic Designs Corporation Marlborough, MA (508) 485-4000 CIS Function Peak I Value Tuple Code Link to next tuple TPCE_INDX Vcc Nominal is 5V Support 16/8 bit I/O access, I/O Address Lines are 16 IRQ Sharing S: Share Logic active P: Pulse IRQ supported L: Level IRQ supported M: Bit Mask of IRQ IRQ Levels to be routed 0-7 recommended IRQ Levels to be routed 8-15 recommended Power Down supported Vcc Nominal Value TPCE_IO Configuration Entry Tuple Link is 6 bytes Configuration Entry Number IR IO T Power Q PI AI SI H L N V V V MS DI B Description of Contents Peak I is 45mA Configuration Entry Tuple Link is 10bytes I/O Mapped Contiguous 16 Registers Configuration, D: Default Configuration, I: Interface Byte Follows I/O Interface, Bvd & WP not used, RDY/BSY active, Wait not used for memory access Misc & IRQ field are present, Vcc power-description structure only Nominal Operating supply Voltage 26 N V Vcc power-description structure only TPCE_IF TPCE_FS TPCE_PD TPCE_IR TPCE_IR Mask Extension TPCE_IR Mask Extension TPCE_MI Tuple Code Link to next tuple TPCE_INDX TPCE_FS Nominal Operating supply Voltage, Maximum Current required averaged over 10ms 1Vx3 Vcc Nominal is 3.3V Peak I is 45mA Configuration Entry Tuple Link is 15bytes TPCE_PD Vcc Nominal is 5V Vcc Nominal Value Vcc Nominal Value Peak I Value Tuple Code Link to next tuple TPCE_INDX I/O Interface, Bvd & WP not used, TPCE_IF RDY/BSY active, Wait not used for memory access Misc & IRQ field are present, Vcc TPCE_FS power-description structure only Nominal Operating supply Voltage TPCE_PD White Electronic Designs CompactFlashTM Cards CFA45 Series CARD INFORMATION STRUCTURE CONT. AttributeOffset 0F2h Data EA 7 R 6 5 Bus 16/8 4 0F4h 61 Size of length 0F6h 0F8h 0FAh 0FCh 0FEh 100h 102h F0 01 07 F6 03 01 EE Start of I/O Address Block First(LSB) Start of I/O Address Block First(MSB) First I/O Range Length Start of I/O Address Block Second(LSB) Start of I/O Address Block Second(MSB) Second I/O Range Length S P L M V B I 104h 20 X 106h 108h 10Ah 10Ch 1B 06 02 01 I M 10Eh 21 R 110h 112h 114h 116h 118h 11Ah 11Ch B5 1E 4D 1B 0F C3 41 X 6h X 1Eh(30d) X 9h CISTPL_CFTABLE_ENTRY I W 11Eh 99 M 120h 01 R 122h 124h 55 EA X R Size of address R 3 2 1 I/O AddrLines Number of I/O Address Ranges P R A O CISTPL_CFTABLE_ENTRY D Configuration MS IR Q DI PI AI D R 0 N T Entry Number I T Power O SI H L N V V V 5h 5h Configuration Entry Number P B Interface Type MS DI PI IR Q AI I O SI T Power H V L V 5h Ah Bus 16/8 I/O AddrLines 27 N V Description of Contents I/O range description, Support 16/8 bit I/O access, A 1 Kbyte I/O address space Length is 1 byte long, Address is 2 byte long, 1 I/O Address Range Description field CIS Function TPCE_IO IRQ Sharing S: Share Logic active, P: Pulse IRQ supported, L: Level IRQ supported, V: Vendor-Specific supported, B: Bus-Error supported, I: I/O-check supported Power Down supported TPCE_IR Configuration Entry Tuple Link is 6bytes Tuple Code Link to next tuple TPCE_INDX TPCE_FS only TPCE_PD Vcc power-description structure Nominal Operating supply Voltage, Maximum Current required averaged over 10ms 1Vx3 Vcc Nominal is 3.3V Peak I is 45mA Configuration Entry Tuple Link is 15bytes I/O Range Description Byte TPCE_MI Vcc Nominal Value Peak I Value Tuple Code Link to next tuple TPCE_INDX I/O Interface, Bvd & WP not used, TPCE_IF RDY/BSY active, Wait not used for memory access Misc & IRQ field are present, Vcc TPCE_FS power-description structure only Nominal Operating supply Voltage TPCE_PD Vcc Nominal is 5V I/O range description, Support 16/8 bit I/O access, A 1 Kbyte I/O address space Vcc Nominal Value TPCE_IO White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series CARD INFORMATION STRUCTURE CONT. AttributeOffset 126h Data 61 7 6 Size of length 5 4 Size of address 128h 12Ah 12Ch 12Eh 130h 132h 134h 70 01 07 76 03 01 EE Start of I/O Address Block First (LSB) Start of I/O Address Block First (MSB) First I/O Range Length Start of I/O Address Block Second(LSB) Start of I/O Address Block Second(MSB) Second I/O Range Length S P L M V B I 136h 20 X 138h 13Ah 13Ch 13Eh 1B 06 03 01 I M D 140h 21 R DI 142h 144h 146h 148h 14Ah 14Ch B5 1E 4D 14 00 FF X 6h X 1Eh(30d) X 9h CISTPL_NO_LINK No Bytes Following End of CIS Tuple Chain R 3 2 1 Number of I/O Address Ranges P R A O CISTPL_CFTABLE_ENTRY MS 0 Description of Contents Length is 1 byte long, Address is 2 byte long, 1 I/O Address Range Description field CIS Function I/O Range Description Byte N IRQ Sharing S: Share Logic active, P: Pulse IRQ supported, L: Level IRQ supported, V: Vendor-Specific supported, B: Bus-Error supported, I: I/O-check supported Power Down supported TPCE_IR Configuration Entry Tuple Link is 6bytes Tuple Code Link to next tuple TPCE_INDX TPCE_FS T Configuration Entry Number IR I T Power Q O PI AI SI H L N V V V White Electronic Designs Corporation Marlborough, MA (508) 485-4000 5h 5h 28 Vcc power-description structure only Nominal Operating supply Voltage, Maximum Current required averaged over 10ms 1Vx3 Vcc Nominal is 3.3V Peak I is 45mA No Link to Common Memory Link Length is 0 byte End of CIS TPCE_MI TPCE_PD Vcc Nominal Value Peak I Value Tuple Code Link to next tuple Tuple Code White Electronic Designs CompactFlashTM Cards CFA45 Series TRUE IDE TO COMPACTFLASHTM INTERFACE True IDE CompactFlashTM No(#) 40pin No(#) 1 RESET 41 68pin RESET 2 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL (39) 3 D7 6 D7 4 5 D8 D6 47 5 D8 D6 6 D9 48 D9 7 D5 4 D5 8 D10 49 D10 9 D4 3 D4 10 D11 27 D11 11 D3 2 D3 12 D12 28 D12 13 D2 23 D2 14 D13 29 D13 15 D1 22 D1 16 17 D14 D0 30 21 D14 D0 18 D15 31 D15 19 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39) 20 (keypin) 21 DMACK 44 INPACK 22 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39) 23 IOWR 35 IOWR 24 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39) 25 IORD 34 IORD 26 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39) 27 28 IORDY CSEL 42 39 WAIT CSEL 29 DMACK 44 REG 30 GND 1,8,9,11,12,14,15,16,17,50,(39) GND, A10-A3, OE, CSEL(39) 31 IREQ 37 RDY/BSY 32 IOIS16 24 WP 33 A1 19 A1 34 PDIAG 46 BVD1 35 A0 20 A0 36 A2 18 A2 37 CS0 7 CS0 38 CS1 32 CS1 39 40 DASP GND 45 1,8,9,11,12,14,15,16,17,50,(39) BVD2 GND, A10-A3, OE, CSEL(39) 29 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series PRODUCT MARKING WED 7P016CFA4500C25 C995 0322 COMPANY NAME PART NUMBER LOT CODE/TRACE NUMBER DATE CODE P ART NUMBERING 7 P 256 CFA45 00 C 25 CARD TECHNOLOGY 7 FLASH 8 SRAM PC CARD P Standard R Ruggedized CARD CAPACITY 256 256MB CARD FAMILY AND VERSION PACKAGING OPTION 00 Standard CF, WEDC logo TEMPERATURE RANGE C = Commercial 0C to +70C CARD ACCESS TIME 25 250ns White Electronic Designs Corporation Marlborough, MA (508) 485-4000 30 White Electronic Designs CompactFlashTM Cards CFA45 Series ORDERING INFORMATION 7P XXX CFA45 SS T ZZ XXX (unformatted capacity) 008 8MB 016 16MB 032 32MB 048 48MB 064 64MB 096 96MB 128 128MB 256 256MB 512 512MB CFA45 Samsung based CompactFlash SS T ZZ 00 01 CompactFlash Type I WEDC logo CompactFlash Type I Blank C Commercial Temperature Range 25 250ns 31 White Electronic Designs Corporation (508) 485-4000 www.whiteedc.com White Electronic Designs CompactFlashTM Cards CFA45 Series Document Title CompactFlash Cards - CFA45 Series Revision History Rev level Rev 0 Description Date Initial release May 16, 2003 White Electronic Designs Corporation Marlborough, MA (508) 485-4000 32