Features and Benefits
Low RDS(ON) outputs
Internal mixed current decay mode
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
3.3 and 5 V compatible logic supply
Thin profile QFN and TSSOP packages
Thermal shutdown circuitry
Short-to-ground protection
Shorted load protection
Low current Sleep mode, < 10 μA
Description
The A4986 is a dual DMOS full-bridge stepper motor driver
with parallel input communication and overcurrent protection.
Each full-bridge output is rated up to 35 V and ±2 A.
The A4986 includes fixed off-time pulse width modulation
(PWM) current regulators, along with 2- bit nonlinear DACs
(digital-to-analog converters) that allow stepper motors to be
controlled in full, half, and quarter steps. The PWM current
regulator uses the Allegro® patented mixed decay mode for
reduced audible motor noise, increased step accuracy, and
reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
The outputs are protected from shorted load and short-to-
ground events, which protect the driver and associated circuitry
from thermal damage or flare-ups. Other protection features
include thermal shutdown with hysteresis, undervoltage lockout
(UVLO) and crossover current protection. Special power-up
sequencing is not required.
The A4986 is supplied in a 24-contact QFN package (ES), and
a 24-pin TSSOP package (LP) with an overall package height
of 1.2 mm. Both packages have exposed pads for enhanced
thermal dissipation, and are lead (Pb) free (suffix –T), with
100% matte tin plated leadframes.
4986-DS, Rev. 4
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
24-contact QFN
4 mm × 4 mm × 0.75 mm
(ES package)
Microcontroller or
Controller Logic
VDD
VREF GND GND
PH2
IN12
SLEEP
IN11
PH1
IN02
IN01
VBB1
CP1 VCPVREG
VDD
ROSC
0.22 F
0.22 F
0.1 F0.1 F
100 F
CP2
VBB2
OUT1A
OUT1B
SENSE1
OUT2A
OUT2B
SENSE2
A4986
Typical Application Diagram
Packages:
24-pin TSSOP
with exposed thermal pad
(LP Package)
Approximate size
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 35 V
Output Current IOUT ±2 A
Logic Input Voltage VIN –0.3 to 5.5 V
Logic Supply Voltage VDD –0.3 to 5.5 V
Motor Outputs Voltage –2.0 to 37 V
Sense Voltage VSENSE –0.5 to 0.5 V
Reference Voltage VREF 5.5 V
Operating Ambient Temperature TARange S –20 to 85 ºC
Maximum Junction TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Selection Guide
Part Number Package Packing
A4986SESTR-T 24-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel
A4986SLPTR-T 24-pin TSSOP with exposed thermal pad 4000 pieces per 13-in. reel
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Functional Block Diagram
0.1 F
REGULATOR
GATE
DRIVE
CHARGE PUMP
DMOS FULL-BRIDGE 1
0.1 F
DMOS FULL-BRIDGE 2
VCP
PWM Latch
BLANKING
Mixed Decay
To
VBB2
IN02
PH1
IN11
SENSE1
OUT1B
OUT1A
VBB1
SENSE2
OUT2B
OUT2A
VBB2
VCP
CP2
CP1
VREG
VDD
CONTROL
LOGIC
OSC
OSC
VREG
0.22 F
Sense2
IN01
IN12
PH2
DAC
+-
VREF
Sense2
Rosc
GND
GND
SLEEP
OCP
OCP
DAC
+-
VREF
PWM Latch
BLANKING
Mixed Decay
OSC
Sense2
VREG
REF VREF
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)
Characteristics Symbol Test Conditions Min. Typ.2Max. Units
Output Drivers
Load Supply Voltage Range VBB
Operating 8 35 V
During Sleep Mode 0 35 V
Logic Supply Voltage Range VDD Operating 3.0 5.5 V
Output On Resistance RDSON
Source Driver, IOUT = –1.5 A 320 430 m
Sink Driver, IOUT = 1.5 A 320 430 m
Body Diode Forward Voltage VF
Source Diode, IF = –1.5 A 1.3 V
Sink Diode, IF = 1.5 A 1.3 V
Motor Supply Current IBB
fPWM < 50 kHz 4 mA
Operating, outputs disabled 2 mA
Sleep Mode 10 A
Logic Supply Current IDD
fPWM < 50 kHz 8 mA
Outputs off 5 mA
Sleep Mode 10 A
Control Logic
Logic Input Voltage VIN(1) VDD0.7 ––V
VIN(0) ––
VDD0.3 V
Logic Input Current IIN(1) VIN = VDD0.7 –20 <1.0 20 A
IIN(0) VIN = VDD0.3 –20 <1.0 20 A
Logic Input Pull-down RIN02 100 k
RIN12 –50–k
Logic Input Hysteresis VHYS(IN) As a % of VDD 51119%
Blank Time tBLANK 0.7 1 1.3 s
Fixed Off-Time tOFF
OSC = VDD or GND 20 30 40 s
ROSC = 25 k23 30 37 s
Reference Input Voltage Range VREF 0–4V
Reference Input Current IREF –3 0 3 A
Current Trip-Level Error3errI
VREF = 2 V, %ITripMAX = 33.3% ±15 %
VREF = 2 V, %ITripMAX = 66.7% ±5 %
VREF = 2 V, %ITripMAX = 100.00% ±5 %
Crossover Dead Time tDT 100 475 800 ns
Protection
Overcurrent Protection Threshold4IOCPST 2.1 A
Thermal Shutdown Temperature TTSD 165 °C
Thermal Shutdown Hysteresis TTSDHYS –15–°C
VDD Undervoltage Lockout VDDUVLO VDD rising 2.7 2.8 2.9 V
VDD Undervoltage Hysteresis VDDUVLOHYS –90–mV
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
3VERR = [(VREF/8) – VSENSE] / (VREF/8).
4Overcurrent protection (OCP) is tested at TA = 25°C in a restricted range and guaranteed by characterization.
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
ES package; estimated, on 4-layer PCB, based on JEDEC standard 37 ºC/W
LP package; on 4-layer PCB, based on JEDEC standard 28 ºC/W
*In still air. Additional thermal information available on Allegro Web site.
20 40 60 80 100 120 140 160 180
Temperature (°C)
Power Dissipation, P
D
(W)
0.0
0.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.0
1.5
Maximum Power Dissipation, PD(max)
(RθJA = 28 ºC/W)
(RθJA = 37 ºC/W)
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Functional Description
Device Operation. The A4986 is designed to operate one
stepper motor in full, half, or quarter step mode. The currents in
each of the output full-bridges, all N-channel DMOS, are regu-
lated with fixed off-time pulse width modulated (PWM) control
circuitry. Each full-bridge peak current is set by the value of
an external current sense resistor, RSx , and a reference voltage,
VREFx .
Percentages of the peak current are set using a 2-bit nonlinear
DAC that programs 33%, 66%, or 100% of the peak current, or
disables the outputs.
Internal PWM Current Control. Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, ITRIP
. Initially, a diagonal pair
of source and sink FET outputs are enabled and current flows
through the motor winding and the current sense resistor, RSx.
When the voltage across RSx equals the DAC output voltage, the
current sense comparator resets the PWM latch. The latch then
turns off the sink and source FETs.
The maximum value of current limiting is set by the selection of
RSx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by
ITripMAX = VREF / ( 8 R S)
where RS is the resistance of the sense resistor (Ω) and VREF is
the input voltage on the REF pin (V).
The 2-bit DAC output reduces the VREF output to the current
sense comparator in precise steps, such that
Itrip = (%ITripMAX / 100) × ITripMAX
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The off-time, tOFF, is determined by the
ROSC terminal. The ROSC terminal has two settings:
ROSC tied to VDD or ground — off-time internally set to
30 μs
ROSC through a resistor to ground — off-time is determined
by the following formula
tOFF ROSC 825
Where tOFF is in μs.
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal
current control circuitry. The comparator outputs are blanked
to prevent false overcurrent detection due to reverse recovery
currents of the clamp diodes, and switching transients related
to the capacitance of the load. The blank time, tBLANK (μs), is
approximately
tBLANK 1 μs
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is
shorted to ground, the driver will protect itself by sensing the
overcurrent event and disabling the driver that is shorted, protect-
ing the device from damage. In the case of a short-to-ground, the
device will remain disabled (latched) until the S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
input goes
high or VDD power is removed. A short-to-ground overcurrent
event is shown in figure 1.
When the two outputs are shorted together, the current path is
through the sense resistor. After the blanking time (1 μs) expires,
the sense resistor voltage is exceeding its trip value, due to the
overcurrent condition that exists. This causes the driver to go into
a fixed off-time cycle. After the fixed off-time expires the driver
turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in figure 2.
If the driver is operating in Mixed decay mode, it is normal for
the positive current to spike, due to the bridge going in the for-
ward direction and also in the negative direction, as a result of the
direction change implemented by the Mixed decay feature. This
is shown in figure 3. In both instances the overcurrent circuitry is
protecting the driver and prevents damage to the device.
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
Functional Description
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
VREG (VREG). This internally-generated voltage is used to
operate the sink-side FET outputs. The nominal output voltage
of the VREG terminal is 7 V. The VREG pin must be decoupled
with a 0.22 μF ceramic capacitor to ground. VREG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4986 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4986 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Sleep Mode ( ¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯
). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator, and
charge pump. A logic low on the SLEEP pin puts the A4986 into
Sleep mode. When emerging from Sleep mode, in order to allow
the charge pump to stabilize, provide a delay of 1 ms before issu-
ing a logic command.
Mixed Decay Operation. The bridge operates in Mixed
Decay mode, as shown in figures 5 through 7. As the trip point
is reached, the A4986 initially goes into a fast decay mode for
31.25% of the off-time, tOFF. After that, it switches to Slow Decay
mode for the remainder of tOFF. A timing diagram for this feature
appears in figure 4.
Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed-off time cycle, load current recir-
culates in Mixed Decay mode. This synchronous rectification
feature turns on the appropriate FETs during current decay, and
effectively shorts out the body diodes with the low FET RDS(ON).
This reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications. Syn-
chronous rectification turns off when the load current approaches
zero (0 A), preventing reversal of the load current.
t
Fixed off-time
5 A / div.
t
5 A / div.
Figure 1. Short-to-ground event
Figure 2. Shorted load (OUTxA OUTxB) in
Slow decay mode
Figure 3. Shorted load (OUTxA OUTxB) in Mixed decay mode
Fixed off-time
Fast decay portion
(direction change)
t
5 A / div. Fault
latched
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
I
OUT
I
OUT
t
See Enlargement A
Enlargement A
t
SD
t
FD
t
off
Slow Decay
Mixed Decay
Fast Decay
I
PEAK
70.71
–70.71
0
100.00
–100.00
PHx
INx1
INx2
Symbol Characteristic
toff Device fixed off-time
IPEAK Maximum output current
tSD Slow decay interval
tFD Fast decay interval
IOUT Device output current
Figure 4. Current Decay Modes Timing Chart
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Application Layout
Layout. The printed circuit board should use a heavy ground-
plane. For optimum electrical and thermal performance, the
A4986 must be soldered directly onto the board. On the under-
side of the A4986 package is an exposed pad, which provides a
path for enhanced thermal dissipation. The thermal pad should be
soldered directly to an exposed surface on the PCB. Thermal vias
are used to transfer heat to other layers of the PCB.
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A4986, that area becomes an ideal location for
a star ground point. A low impedance ground will prevent ground
bounce during high current operation and ensure that the supply
voltage remains stable at the input terminal.
The two input capacitors should be placed in parallel, and as
close to the device supply pins as possible. The ceramic capaci-
tor (CIN1) should be closer to the pins than the bulk capacitor
(CIN2). This is necessary because the ceramic capacitor will be
responsible for delivering the high frequency current components.
The sense resistors, RSx , should have a very low impedance
path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
to accurately measure the current in the windings. The SENSEx
pins have very short traces to the RSx resistors and very thick,
low impedance traces directly to the star ground underneath the
device. If possible, there should be no other components on the
sense circuits.
V
DD
V
BB
C2
ROSC
PAD
A4986
C5
C6
C3
C4
R4
R5
C1
OUT2B
OUT1B
OUT2A
OUT1A
VBB2
VBB1
PH1
SENSE2
SENSE1
CP1 GND
PH2
GND
CP2
VCP
VREG
ROSC
VDD
INO2
IN12
IN11
IN01
REF
SLEEP
GND
GND
GND
GND
GND
GND GND
R4
U1
OUT2B
GND
R5
OUT2A
OUT1A
OUT1B
C3
C4
C5
ROSC
C2
C6
C1
VBB
VDD
CAPACITANCE
BULK
PCB
Thermal Vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
Solder
A4986
LP package configuration
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
V
DD
V
BB
C2
ROSC
PAD
A4986
C6
C7
C3
C4
R4 R5
C1
OUT2B OUT1A OUT1BOUT2A
VBB2
SENSE2
OUT2A
OUT1A
SENSE1
VBB1
OUT2B
PH2
GND
CP1
CP2
VCP
OUT1B
PH1
GND
REF
IN01
VDD
VREG
IN02
IN12
IN11
ROSC
SLEEP
R4
U1
OUT2B
GND
R5
OUT2A OUT1A OUT1B
GND
GND
GND
C3
C4
C6
ROSC C2
C7
C1
VBBVDD
CAPACITANCE
BULK
ES package configuration
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
VCP
GND
CP2
GND
CP1VBB
8 V
GND
VDD
GND GND
8 V
GND GND
8 V
VBB
VREG
10 V
GND
DMOS
Parasitic
SENSE VREG
GND
VBB
40 V
GND
VBB
OUT
DMOS
Parasitic
DMOS
Parasitic
GND
PGND GND
IN01
IN02
IN11
IN12
PH1
PH2
VREF
ROSC
SLEEP
Pin Circuit Diagrams
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Figure 5. Step Sequencing for Full-Step Increments.
0
100.0
66.7
–100.0
–66.7
(%)
Phase 1
0
100.0
66.7
–100.0
–66.7
(%)
Phase 2
Full step 2 phase
Modified full step 2 phase
Step Sequencing Diagrams
0
100.0
66.7
–100.0
–66.7
(%)
Phase 1
0
100.0
66.7
–100.0
–66.7
(%)
Phase 2
Half step 2 phase
Modified half step 2 phase
Figure 6. Step Sequencing for Half-Step Increments.
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
0
100.0
66.7
33.3
–33.3
–100.0
–66.7
0
100.0
66.7
33.3
–33.3
–100.0
–66.7
(%)
Phase 1
(%)
Phase 2
Figure 7. Step Sequence for Quarter-Step Increments
Step Sequencing Settings
Full 1/2 1/4 Phase 1
(%ITripMax)I01 I11 PHASE Phase 2
(%ITripMax)I02 I12 PHASE
11 0 HHx 100LL1
2 33 L H 1 100 L L 1
1 2 3 100/66* L/H* L 1 100/66* L/H* L 1
4 100 L L 1 33 L H 1
3 5 100 L L 1 0 H H X
6 100 L L 1 33 L H 0
2 4 7 100/66* L/H* L 1 100/66* L/H* L 0
8 33 L H 1 100 L L 0
59 0 HHx 100LL0
10 33 L H 0 100 L L 0
3 6 11 100/66* L/H* L 0 100/66* L/H* L 0
12 100 L L 0 33 L H 0
7 13 100 L L 0 0 H H X
14 100 L L 0 33 L H 1
4 8 15 100/66* L/H* L 0 100/66* L/H* L 1
16 33 L H 0 100 L L 1
* Denotes modified step mode
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
14
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Terminal List Table
Name Number Description
ES LP
CP1 4 1 Charge pump capacitor terminal
CP2 5 2 Charge pump capacitor terminal
PH1 17 14 Logic input
PH2 2 23 Logic input
GND 3, 16 13, 24 Ground*
IN02 8 5 Logic input
IN12 9 6 Logic input
OUT1A 21 18 DMOS Full Bridge 1 Output A
OUT1B 18 15 DMOS Full Bridge 1 Output B
OUT2A 22 19 DMOS Full Bridge 2 Output A
OUT2B 1 22 DMOS Full Bridge 2 Output B
REF 15 12 Gm reference voltage input
IN11 10 7 Logic input
ROSC 11 8 Timing set
SENSE1 20 17 Sense resistor terminal for Bridge 1
SENSE2 23 20 Sense resistor terminal for Bridge 2
¯
S
¯
¯
L
¯
¯
E
¯
¯
E
¯
¯
P
¯ 12 9 Logic input
IN01 14 11 Logic input
VBB1 19 16 Load supply
VBB2 24 21 Load supply
VCP 6 3 Reservoir capacitor terminal
VDD 13 10 Logic supply
VREG 7 4 Regulator decoupling terminal
PAD Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
PAD
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
VBB2
SENSE2
OUT2A
OUT1A
SENSE1
VBB1
VREG
IN02
IN12
IN11
ROSC
SLEEP
OUT1B
PH1
GND
REF
IN01
VDD
OUT2B
PH2
GND
CP1
CP2
VCP
Pin-out Diagrams
ES Package LP Package
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GND
PH2
OUT2B
VBB2
SENSE2
OUT2A
OUT1A
SENSE1
VBB1
OUT1B
PH1
GND
CP1
CP2
VCP
VREG
IN02
IN12
IN11
ROSC
SLEEP
VDD
IN01
REF
PAD
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
15
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
ES Package, 24-Pin QFN with Exposed Thermal Pad
0.95
C
SEATING
PLANE
C0.08
25X
24
24
2
1
1
2
24
2
1
A
ATerminal #1 mark area
Coplanarity includes exposed thermal pad and terminals
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
For Reference Only; not for tooling use (reference JEDEC MO-220WGGD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
C
D
D
C
Reference land pattern layout (reference IPC7351
QFN50P400X400X80-25W6M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
4.10
0.30
0.50
4.10
0.50 BSC
4.00 ±0.15
4.00 ±0.15
2.70
2.70
2.70
2.70
0.75 ±0.05
0.40 ±0.10 B
PCB Layout Reference View
0.25 +0.05
–0.07
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
16
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
1.20 MAX
C
SEATING
PLANE
0.15 MAX
C0.10
24X
0.65
6.103.00
4.32
1.65
0.45
0.65
0.25
21
24
3.00±0.05
4.32±0.05
(1.00)
GAUGE PLANE
SEATING PLANE
B
A
ATerminal #1 mark area
B
For reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
C
C
7.80 ±0.10
4.40 ±0.10 6.40 ±0.20 0.60 ±0.15
4° ±4
0.25 +0.05
–0.06
0.15 +0.05
–0.06
DMOS Dual Full-Bridge PWM Motor Driver
With Overcurrent Protection
A4986
17
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Copyright ©2009-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
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Revision History
Revision Revision Date Description of Revision
Rev. 4 March 21, 2012 Update Step Sequence and example layout