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SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
 
  
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FEATURES
DOperating Input Voltage 2.25 V to 5.5 V
DOutput Voltage as Low as 0.7 V
D1% Internal 0.7 V Reference
DPredictive Gate Drivet N-Channel MOSFET
Drivers for Higher Efficiency
DExternally Adjustable Soft-Start and
Overcurrent Limit
DSource-Only Current or Source/Sink Current
DVersions for Starting Into VOUT Pre-Bias
D10-Lead MSOP PowerPadt Package for
Higher Performance
DThermal Shutdown
DInternal Boostrap Diode
DFixed-Frequency, Voltage-Mode Control
− TPS40000/1/4 300-kHz
− TPS40002/3/5 600-kHz
SIMPLIFIED APPLICATION DIAGRAM
APPLICATIONS
DNetworking Equipment
DTelecom Equipment
DBase Stations
DServers
DDSP Power
DPower Modules
DESCRIPTION
The TPS4000x are controllers for low-voltage,
non-isolated synchronous buck regulators. These
controllers drive an N-channel MOSFET for the
primary buck switch, and an N-channel MOSFET
for the synchronous rectifier switch, thereby
achieving very high-ef ficiency power conversion. In
addition, the device controls the delays from main
switch off to rectifier turn-on and from rectifier
turn-off to main switch turn-on in such a way as to
minimize diode losses (both conduction and
recovery) in the synchronous rectifier with TI’s
proprietary Predictive Gate D rivet t echnology. The
reduction i n t hese l osses i s s ignificant a nd i ncreases
efficiency. F or a g iven c onverter p ower l evel, s maller
FETs can be used, or heat sinking can be reduced
or even eliminated.
UDG−01141
VIN
VOUT
1 ILIM 10BOOT
2FB 9HDRV
3 COMP 8SW
4 SS/SD 7VDD
5 GND 6LDRV
TPS40000
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'&%.%#. 2%##%&3/ #".)(&" +#"(*''4 ."*' "& *(*''%#-3 (-).*
&*'&4 "! %-- +%#%$*&*#'/
Copyright 2005, Texas Instruments Incorporated
PowerPADt and Predictive Gate Drivet are trademarks of Texas Instruments Incorporated.
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SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
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DESCRIPTION (continued)
The current-limit threshold is adjustable with a single resistor connected to the device. The TPS4000x
controllers implement a closed-loop soft start function. Startup ramp time is set by a single external capacitor
connected to the SS/SD pin. The SS/SD pin is also used for shutdown.
ORDERING INFORMATION
PACKAGED DEVICES MSOP(2) (DGQ)
APPLICATION
TAFREQUENCY SOURCE
ONLY SOURCE/SINK
WITH PREBIAS(3) SOURCE/SINK(3)
−40°C to 85°C
300 kHz TPS40000DGQ TPS40001DGQ TPS40004DGQ
−40°C to 85°C600 kHz TPS40002DGQ TPS40003DGQ TPS40005DGQ
(2) The DGQ package is available taped and reeled. Add R suffix to device type (e.g.
TPS40000DGQR) to order quantities of 2,500 devices per reel and 80 units per tube.
(3) See Application Information section, p. 8.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS4000x UNIT
BOOT VSW + 6.5
COMP, FB, ILIM, SS/SD −0.3 to 6
Input voltage range, V
IN
SW −0.7 to 10.5 V
Input voltage range, VIN
SWT (SW transient < 50 ns) −2.5
V
VDD 6
Operating junction temperature range, TJ−40 to 150
Storage temperature, Tstg −55 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260
C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ACTUAL SIZE
3,05mm x 4,98mm
1
2
3
4
5
10
9
8
7
6
ILIM
FB
COMP
SS/SD
GND
BOOT
HDRV
SW
VDD
LDRV
DGQ PACKAGE(4).(5)
(TOP VIEW)
(4) See technical brief SLMA002 for PCB guidelines for PowerPAD packages.
(5) PowerPADt heat slug can be connected to GND (pin 5).
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ELECTRICAL CHARACTERISTICS
over recommended operating temperature range, TA = −40_C to 85_C, VDD = 5.0 V, all parameters measured at zero
power dissipation (unless otherwise noted)
input supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Input voltage range 2.25 5.5
V
VHGATE High-side gate voltage VBOOT − VSW 5.5 V
Shutdown current SS/SD = 0 V, Outputs off 0.25 0.45
I
DD
Quiescent current FB = 0.8 V 1.4 2.0 mA
IDD
Switching current No load at HDRV/LDRV 1.5 4.0
mA
UVLO Minimum on-voltage 1.95 2.05 2.15 V
Hysteresis 80 140 200 mV
oscillator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOSC
Oscillator frequency
TPS40000
TPS40001
TPS40004
2.25 V VDD 5.00 V
250 300 350
kHz
fOSC Oscillator frequency TPS40002
TPS40003
TPS40005
2.25 V VDD 5.00 V
500 600 700
kHz
VRAMP Ramp voltage VPEAK − VVALLEY 0.80 0.93 1.07
V
Ramp valley voltage 0.24 0.31 0.41 V
PWM
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Maximum duty cycle(2)
TPS40000
TPS40001
TPS40004
FB = 0 V, VDD = 3.3 V
87% 94% 97%
Maximum duty cycle
(2)
TPS40002
TPS40003
TPS40005
FB = 0 V, VDD = 3.3 V
83% 93% 97%
Minimum duty cycle 0%
error amplifier
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB
FB input voltage
Line, Temperature 0.689 0.700 0.711
V
VFB FB input voltage TA = 25°C0.693 0.700 0.707 V
FB input bias current 30 130 nA
VOH High-level output voltage FB = 0 V, IOH = 0.5 mA 2.0 2.5
V
VOL Low-level output voltage FB =VDD, IOL = 0.5 mA 0.08 0.15 V
IOH Output source current COMP = 0.7 V, FB = GND 2 6
mA
IOL Output sink current COMP = 0.7 V, FB = VDD 3 8 mA
GBW Gain bandwidth(1) 5 10 MHz
AOL Open loop gain 55 85 dB
(1) Ensured by design. Not production tested.
(2) At VDD input voltage of 2.25 V, derate the maximum duty cycle by 3%.
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SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
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ELECTRICAL CHARACTERISTICS
over recommended operating temperature range, TA = −40_C to 85_C, VDD = 5.0 V, all parameters measured at zero
power dissipation (unless otherwise noted)
current limit
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISINK
ILIM sink current
VDD = 5 V 11 15 19
A
ISINK ILIM sink current VDD = 2.25 V 9.5 13.0 16.5 µA
VOS Offset voltage SW vs ILIM(1) 2.25 V VDD 5.00 −20 0 20 mV
VILIM Input voltage range 2 VDD V
tON Minimum HDRV pulse time in overcurrent VDD = 3.3 V 200 300 ns
SW leading edge blanking pulse in over-
current detection 100 ns
tSS Soft-start capacitor cycles as fault timer(1) 6
rectifier zero current comparator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSW Sense voltage to turn off
rectifier TPS40000
TPS40002 LDRV output OFF −15 −7 −2 mV
SW leading edge blanking pulse in zero
current detection 75 ns
predictive delay
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSWP Sense threshold to modulate delay time −350 mV
TLDHD Maximum delay modulation range time LDRV OFF − to − HDR V ON 50 75 100 ns
Predictive counter delay time per bit LDRV OFF − to − HDRV ON 3.0 4.5 6.2 ns
THDLD Maximum delay modulation range HDRV OFF − to − LDRV ON 40 65 90 ns
Predictive counter delay time per bit HDRV OFF − to − LDRV ON 2.4 4.0 5.6 ns
shutdown
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSD Shutdown threshold voltage Outputs OFF 0.09 0.13 0.205 V
VEN Device active threshold voltage 0.14 0.17 0.235 V
soft start
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISS Soft-start source current Outputs OFF 2.0 3.7 5.4 µA
VSS Soft-start clamp voltage 1.1 1.5 1.9 V
bootstrap
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RBOOT
VDD = 3.3 V 50 100
RBOOT Bootstrap switch resistance VDD = 5 V 35 70
(1) Ensured by design. Not production tested.
(2) At VDD input voltage of 2.25 V, derate the maximum duty cycle by 3%.
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SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
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ELECTRICAL CHARACTERISTICS
over recommended operating temperature range, TA = −40_C to 85_C, VDD = 5.0 V, all parameters measured at zero
power dissipation (unless otherwise noted)
output driver
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RHDHI HDRV pull-up resistance VBOOT−VSW = 3.3 V,
ISOURCE = −100 mA 3 5.5
RHDLO HDRV pull-down resistance VBOOT − VSW = 3.3 V,
ISINK = 100 mA 1.5 3
RLDHI LDRV pull-up resistance VDD = 3.3 V, ISOURCE = −100 mA 3 5.5
RLDLO LDRV pull-down resistance VDD = 3.3 V, ISINK = 100 mA 1.0 2.0
tRISE LDRV rise time 15 35
tFALL LDRV fall time
CLOAD = 1 nF
10 25
ns
HDRV rise time CLOAD = 1 nF 15 35 ns
HDRV fall time 10 25
thermal shutdown
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSD Shutdown temperature(1) 165
°C
Hysteresiss(1) 15 °C
sw node
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISW Leakage current in shutdown (1) 15 µA
(1) Ensured by design. Not production tested.
(2) At VDD input voltage of 2.25 V, derate the maximum duty cycle by 3%.
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Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
BOOT 10 O Provides a bootstrapped supply for the topside MOSFET driver, enabling the gate of the topside
MOSFET to be driven above the input supply rail
COMP 3 O Output of the error amplifier
FB 2 I Inverting input of the error amplifier. In normal operation the voltage at this pin is the internal reference level of 700 mV.
GND 5 Power supply return for the device. The power stage ground return on the board requires a separate path from other
sensitive signal ground returns.
HDRV 9 O This is the gate drive output for the topside N-channel MOSFET. HDRV is bootstrapped to near 2×VDD for good en-
hancement of the topside MOSFET.
ILIM 1 I
A resistor is connected between this pin and VDD to set up the over current threshold voltage. A 15-µA current sink at
the pin establishes a voltage drop across the external resistor that represents the drain-to-source voltage across the
top side N-channel MOSFET during an over current condition. The ILIM over current comparator is blanked for the
first 100 ns to allow full enhancement of the top
MOSFET. Set the ILIM voltage level such that it is within 800 mV of VDD; that is, (VDD − 0.8) IILIM VDD.
LDRV 6 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET
SS/SD 4 I
Soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor connected to this pin.
A closed loop soft-start occurs when the internal 3-µA current source charges the external capacitor from 0.17 V to
0.70 V. During the soft-start period, the current sink capability of the TPS40001 and TPS40003 is disabled. When the
SS/SD voltage is less than 0.12 V, the device is shutdown and the HDRV and LDRV are driven low. In normal opera-
tion, the capacitor is charged to 1.5 V. When a fault condition is asserted, the HDRV is driven low, and the LDRV is
driven high. The soft-start capacitor goes through six charge/discharge cycles, restarting the converter on the seventh
cycle.
SW 8 O
Connect to the switched node on the converter. This pin is used for overcurrent sensing in the topside N-channel
MOSFET, zero current sensing in synchronous rectifier N-channel MOSFET, and level sensing for predictive delay
circuit. Overcurrent is determined, when the topside N-channel MOSFET is on, by comparing the voltage on SW with
respect to VDD and the voltage on the ILIM with respect to VDD. Zero current is sensed, when the rectifier N-channel
MOSFET is on, by measuring the voltage on SW with respect to ground. Zero current sensing applies to the
TPS40000/2 devices only.
VDD 7 I Power input for the chip, 5.5-V maximum. Decouple close to the pin with a low-ESR capacitor, 1-µF or larger.
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SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
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functional block diagram
UDG−01142
15 µA
3 µA
7
BOOT
10
VDD
ILIM
1
3
SW
8
COMP
4
HDRV9
SS/SD
5
LDRV
6
GND
UVLO
VDD
2 V
SOFT
START
0.12 V SHUT DOWN
OSC
UVLO
DISCHARGE
SS ACTIVE
FAULT
COUNTER
PWM COMP
PWM
LOGIC
OC
THERMAL
SHUTDOWN
CLK
UVLO
PREDICTIVE
GATE
DRIVE
(VDD−1.2 V)
CURRENT
LIMIT COMP
LDRV
RECTIFIER
ZERO−CURRENT
COMPARATOR
VDD
PWM
LO
VDD
HI
FAULT
LDRV
100 ns DELAY
EN
EN
75 ns
DELAY
2FB
+
REF
ERROR AMPLIFIER
0.7 V
+
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APPLICATION INFORMATION
The TPS4000x series of synchronous buck controller devices is optimized for high-efficiency dc-to-dc
conversion in non-isolated distributed power systems. A typical application circuit is shown in Figure 1.
The TPS40004 and TPS40005 are the controllers of choice for most general purpose synchronous buck
designs. Each operates in two quadrant mode (i.e. source or sink current) full time. This choice provides the
best performance for output voltage load transient response over the widest load current range.
The TPS40001 and TPS40003 add an additional feature: They operate in single quadrant mode (i.e. source
current only) during converter startup, and then when the converter has reached the regulation point, the
controllers change to operate in two quadrant mode. This is useful for applications that have outputs pre-biased
at some voltage before the controller is enabled. When the TPS40001 or TPS40003 is enabled, it does not sink
current during startup and therefore does not pull current from the pre-biased voltage supply.
The TPS40000 and TPS40002 operate in single quadrant mode (source current only) full time, allowing the
paralleling of converters. Single quadrant operation ensures one converter does pull current from a paralleled
converter. A converter using one of these controllers emulates a non-synchronous buck converter at light loads.
When current in the output inductor attempts to reverse, an internal zero-current detection circuit turns OFF the
synchronous rectifier and causes the current flow in the inductor to become discontinuous. At average load
currents greater than the peak amplitude of the inductor ripple current, the converter returns to operation as a
synchronous buck converter to maximize efficiency.
UDG−02013
10 µF
20 kW
100 µF
7.68 k
470 µF10 µF15.7 k
243
10 k
VOUT 1.8 V
10 A
1.0 µH
Si4836DY
IHLP5050CE−01
Si4836DY
5
8
7
10
9
1
2
3
ILIM
FB
COMP
GND
HDRV
SW
VDD
LDRV
3.6 nF
4
4.7 nF
SS/SD
6
BOOT
100 pF
TPS40001
100 nF
3.3 nF
3.3
VDD
3.0 V to 5.5 V
Figure 1. Typical Application Circuit
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APPLICATION INFORMATION
error amplifier
The error amplifier has a bandwidth of greater than 5 MHz, with open loop gain of at least 55 dB. The COMP
output voltage is clamped to a level above the oscillator ramp in order to improve large-scale transient response.
oscillator
The oscillator uses an internal resistor and capacitor to set the oscillation frequency. The ramp waveform is a
triangle at the PWM frequency with a peak voltage of 1.25 V, and a valley of 0.25 V. The PWM duty cycle is limited
to a maximum of 95%, allowing the bootstrap capacitor to charge during every cycle.
bootstrap/charge pump
There is an internal switch between VDD and BOOT. This switch charges the external bootstrap capacitor for
the floating supply. If the resistance of this switch is too high for the application, an external schottky diode
between VDD and BOOT can be used. The peak voltage on the bootstrap capacitor is approximately equal to
VDD.
driver
The HDR V and LDR V MOSFET drivers are capable of driving gate-to-source voltages up to 5.5 V. At VIN, = 5 V
and using appropriate MOSFETs, a 20-A converter can be achieved. The LDRV driver switches between VDD
and ground, while the HDRV driver is referenced to SW and switches between BOOT and SW. The maximum
voltage between BOOT and SW is 5.5 V.
synchronous rectification and predictive delay
In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This
current cannot be stopped immediately without using infinite voltage. For the current path to flow and maintain
voltage levels at a safe level, a rectifier or catch device is used. This device can be either a conventional diode,
or it can be a controlled active device if a control signal is available to drive it. The TPS4000x provides a signal
to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with the drive signal
for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns off and the main
switch turns on, and minimum delay from when the main switch turns off and the rectifier MOSFET turns on.
This scheme, Predictive Gate Drivet delay, uses information from the current switching cycle to adjust the
delays that are to be used in the next cycle. Figure 2 shows the switch-node voltage waveform for a
synchronously rectified buck converter. Illustrated are the relative effects of a fixed-delay drive scheme
(constant, pre-set delays for the turn-off to turn-on intervals), an adaptive delay drive scheme (variable delays
based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme.
Note that the longer the time spent in diode conduction during the rectifier conduction period, the lower the
efficiency. Also, not described in Figure 2 is the fact that the predictive delay circuit can prevent the body diode
from becoming forward biased at all while at the same time avoiding cross conduction or shoot through. This
results in a significant power savings when the main MOSFET turns on, and minimizes reverse recovery loss
in the body diode of the rectifier MOSFET.
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APPLICATION INFORMATION
UDG−01144
GND
Fixed Delay
Adaptive Delay
Predictive Delay
Channel Conduction
Body Diode Conduction
Figure 2. Switch Node Waveforms for Synchronous Buck Converter
overcurrent
Overcurrent conditions in the TPS4000x are sensed by detecting the voltage across the main MOSFET while
it is on.
basic description
If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device is
incremented. If this counter fills up, a fault condition is declared and the device disables switching for a period
of time and then attempts to restart the converter with a full soft-start cycle.
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APPLICATION INFORMATION
detailed description
During each switching cycle, a comparator looks at the voltage across the top side MOSFET while it is on. This
comparator is enabled after the SW node reaches a voltage greater than (VDD−1.2 V) followed by a 100-ns
blanking time. If the voltage across that MOSFET exceeds a programmable threshold voltage, the
current-switching pulse is terminated and a 3-bit counter is incremented by one count. If, during the switching
cycle, the topside MOSFET voltage does not exceed a preset threshold, then this counter is decremented by
one count. (The counter does not wrap around from 7 to 0 or from 0 to 7). If the counter reaches a full count
of 7, the device declares that a fault condition exists at the output of the converter. In this fault state, HDRV is
turned off and LDRV is turned on and the soft-start capacitor is discharged. The counter is decremented by one
by the soft start capacitor (CSS) discharge. When the soft-start capacitor is fully discharged, the discharging
circuit is turned off and the capacitor is allowed to charge up at the nominal charging rate. When the soft-start
capacitor reaches about 700 mV, it is discharged again and the overcurrent counter is decremented by one
count. The capacitor is charged and discharged, and the counter decremented until the count reaches zero (a
total of six times). When this happens, the outputs are again enabled as the soft-start capacitor generates a
reference ramp for the converter to follow while attempting to restart.
During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the
first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault
until the soft-start cycle has been completed. It is possible to have a supply attempt to bring up a short circuit
for the duration of the soft start period plus seven switching cycles. Power stage designs should take this into
account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation.
UDG−01145
0V
VTS
Overcurrent
Cycle
Normal
Cycle
Internal PWM
External
Main Drive
Overcurrent
Threshold
Voltage
(+) VTS (−)
Figure 3. Switch Node Waveforms for Synchronous Buck Converter
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
12 www.ti.com
APPLICATION INFORMATION
Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.
At time t0, power is applied to the converter. The voltage on the soft-start capacitor (VCSS) begins to ramp up
and acts as the reference until it passes the internal reference voltage at t1. At this point the soft-start period
is over and the converter is regulating its output at the desired voltage level. From t0 to t1, pulse-by-pulse current
limiting is i n e ffect, and from t1 onward, overcurrent pulses are counted for purposes of determining a possible
fault condition. At t2, a heavy overload is applied to the converter. This overload is in excess of the overcurrent
threshold. The converter starts limiting current and the output voltage falls to some level depending on the
overload applied. During the period from t2 to t3, the counter is counting overcurrent pulses, and at time t3
reaches a full count of 7. The soft-start capacitor is then discharged, the counter is decremented, and a fault
condition is declared.
VCSS
VOUT
ILOAD
UDG−01144
t
t0 t1 t2 t3 t10
0 6 5 4 3 2 1 0
t4 t5 t6 t7 t8 t9
1 2 3 4 5 6 7
0.7 V
FAULT
Figure 4. Switch Node Waveforms for Synchronous Buck Converter
When the soft start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,
with a nominal 3-µA current source. As the capacitor voltage reaches full charge, it is discharged again and the
counter is decremented by one count. These transitions occur at t3 through t9. At t9, the counter has been
decremented to 0 . The fault logic is then cleared, the outputs are enabled, and the converter attempts to restart
with a full soft-start cycle. The converter comes into regulation at t10.
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
13
www.ti.com
APPLICATION INFORMATION
setting the current limit
Connecting a resistor from VDD to ILIM sets the current limit. A 15-µA current sink internal to the device causes
a voltage drop at ILIM that is equal to the overcurrent threshold voltage. Ensure that (VDD−0.8 V) VILIM VDD.
The tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault
protection of the power switches. Given the tolerance of the ILIM sink current, and the RDS(on) range for a
MOSFET, it i s generally possible to apply a load that thermally damages the converter. This device is intended
for embedded converters where load characteristics are defined and can be controlled.
soft-start and shutdown
These two functions are common to the SS/SD pin. The voltage at this pin is the controlling voltage of the error
amplifier during startup. This reduces the transient current required to charge the output capacitor at startup,
and allows for a smooth startup with no overshoot of the output voltage if done properly. A shutdown feature
can be implemented as shown in Figure 5.
CSS
UDG−01143
SS/SD
4
TPS40000
SHUTDOWN
3 µA
Figure 5. Shutdown Implementation
The device shuts down when the voltage at the SS/SD pin falls below 120 mV. Because of this limitation, it is
recommended that a MOSFET be used as the controlling device, as in Figure 5. An open-drain CMOS logic
output would work equally well.
rectifier zero-current
Both the TPS40000 and TPS40002 parts are source-only, thus preventing reverse current in the synchronous
rectifier. Synchronous rectification is terminated by sensing the voltage, SW with respect to ground, across the
low-side MOSFET. When SW node is greater than −7 mV, rectification is terminated and stays off until the next
PWM cycle. In order to filter out undesired noise on the SW node, the zero-current comparator is blanked for
75 ns from the time the rectifier is turned on.
The TPS40001 and TPS40003 parts enable the zero-current comparator, (and therefore prevent reverse
current), while soft-start is active. However, when the output reaches regulation; that is, at the end of the
soft-start time, this comparator is disabled to allow the synchronous rectifier to sink current.
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
14 www.ti.com
APPLICATION INFORMATION
The following pages include design ideas for a few applications. For more ideas, detailed design information,
and helpful hints, visit the TPS40000 resources at http://power.ti.com.
FDS6894A
UDG−02081
22 µF
12.1 k
1 k
16.9 k
22 µF
22 µF
2.2
.0033 µF
22 µF
1 µF
15 k
8.66 k
1 µF
4.7 nF
68 pF
1 nF
5
8
7
10
9
1
2
3
ILIM
FB
COMP
GND
HDRV
SW
VDD
LDRV
4SS/SD
6
BOOT
TPS40002/3/5
FDS6894A
1.2 V
5 A
3.3 V
PWP
470 pF
1.0 µH
3.3 VOUT
VDD
Figure 6. Small-Form Factor Converter for 3.3 V to 1.2 V at 5 A.
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
15
www.ti.com
APPLICATION INFORMATION
5
8
7
10
9
1
2
3
ILIM
FB
COMP
GND
HDRV
SW
VDD
LDRV
4
C14
4.7 nF
SS/SD
6
BOOT
TPS40000/1/4 Si4866DY
1.2 V
10 A
3.3 V
Si4866DY
PWP
++
UDG−02082
1.5 µH
392 1200 pF
10 k
14 kW
1.8
1.8
1 µF
2.2 nF 6.19 k
1 µF
22 µF
330 µF22 µF
330 µF
82 pF
2.2
10 nF
11 k
22 µF
22 µF
3.3
22 µF22 µF22 µF
VDD
VOUT
Figure 7. High-Current Converter for 3.3 V to 1.2 V at 10 A.
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
16 www.ti.com
APPLICATION INFORMATION
UDG−02083
22 µF 22 µF
536
6.19 k
2.2
1000 pF
8.66 k
3.3 nF
1 µF
22 µF
1 µF
1.8
1500 pF
1.8
5.62 k
15 k
100 pF 22 µF
1.0 µH
L1
5
8
7
10
9
1
2
3
ILIM
FB
COMP
GND
HDRV
SW
VDD
LDRV
4
4.7 nF SS/SD
6
BOOT
TPS40002/3/5 FDS6894A
FDS6894A
1.2 V
5 A
2.5 V BAT54
PWP
VOUT
VDD
3.3
Figure 8. Ultra-Low-Input Voltage Converter for 2.5 V to 1.2 V at 5 A
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
17
www.ti.com
APPLICATION INFORMATION
UDG−02084
24.9 k
820 pF
470 pF
22 µF330 µF330 µF
2.2 nF 12.7 k
11 k
1.8
1.8
1 µF
1 µF
22 µ
F
0.01 µF
2.2
470 µF
1.27 k
9.76 k
1.0 µH
L2
5
8
7
10
9
1
2
3
ILIM
FB
COMP
GND
HDRV
SW
VDD
LDRV
4
4.7 nF
SS/SD
6
BOOT
TPS40000/1/4 Q1
Si4866DY
VOUT
2.5 V
10 A
VDD
3.3 V
+
Q2
Si4866DY
PWP
++ 22 µF22 µF
22 µF
3.3
Figure 9. Ultra-High-Efficiency Converter for 3.3 V to 2.5 V at 10 A
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
18 www.ti.com
TYPICAL CHARACTERISTICS
Figure 10
VIN − Input Voltage − V
OSCILLATOR FREQUENCY PERCENT CHANGE
vs
INPUT VOLTAGE
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0
1
2
3
4
5
6
fOSC − Change in Oscillator Frequency − %
Figure 11
Temperature − °C
fOSC − Change in Oscillator Frequency − %
−50 −25 0 25 50 75 100 125
−6
−5
−4
−3
−1
0
1
−2
OSCILLATOR FREQUENCY PERCENT CHANGE
vs
TEMPERATURE
Figure 12
VIN − Input Voltage − V
VFB − Feedback Voltage − V
FEEDBACK VOLTAGE
vs
INPUT VOLTAGE
0.6990
0.6995
0.7000
0.7010
0.7005
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Figure 13
VFB − Feedback Voltage − V
FEEDBACK VOLTAGE
vs
TEMPERATURE
Temperature − °C
0.693
0.695
0.697
0.699
0.703
0.705
0.707
0.701
−50 −25 0 25 50 75 100 125
 
 
 
SLUS507D − JANUAR Y 2002 − REVISED NOVEMBER 2005
19
www.ti.com
TYPICAL CHARACTERISTICS
Figure 14
VIN − Input Voltage − V
ILIMIT − Sink Current Limit − µA
CURRENT LIMIT SINK CURRENT
vs
INPUT VOLTAGE
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
14.0
14.5
15.5
13.0
12.5
13.5
15.0
Figure 15
CURRENT LIMIT SINK CURRENT
vs
TEMPERATURE
Temperature − °C
14.0
14.5
15.0
15.5
16.0
−50 −25 0 25 50 75 100 125
ILIMIT − Sink Current Limit − µA
Figure 16
t − Time − 1 ms/div
OVERCURRENT
SS/SD Node
(1 V/div)
SW Node
(2 V/ div)
Figure 17
TYPICAL PREDICTIVE
DELAY SWITCHING
LDRV
(2 V/div)
SW Node
(2 V/ div)
t − Time − 400 ns/div
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS40000DGQ ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40000DGQG4 ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40000DGQR ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40000DGQRG4 ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40001DGQ NRND MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40001DGQG4 NRND MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40001DGQR NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40001DGQRG4 NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40002DGQ ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40002DGQG4 ACTIVE MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40002DGQR ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40002DGQRG4 ACTIVE MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40003DGQ NRND MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40003DGQG4 NRND MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40003DGQR NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40003DGQRG4 NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS40004DGQ NRND MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40004DGQG4 NRND MSOP- DGQ 10 80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 22-Apr-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Power
PAD no Sb/Br)
TPS40004DGQR NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40004DGQRG4 NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40005DGQ NRND MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40005DGQG4 NRND MSOP-
Power
PAD
DGQ 10 80 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40005DGQR NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS40005DGQRG4 NRND MSOP-
Power
PAD
DGQ 10 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Apr-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS40000DGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS40001DGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS40002DGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS40003DGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS40004DGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0