SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DOperating Voltage Range of 4.5 V to 5.5 V
DState-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
DFull Parallel Access for Loading
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54BCT573...FK PACKAGE
(TOP VIEW)
SN54BCT573 ...J OR W PACKAGE
SN74BCT573 ...DW, N, OR NS PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q 1Q
8D
GND
LE
V
CC
description/ordering information
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is
high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched
at the logic levels that were set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N Tube SN74BCT573N SN74BCT573N
0°Cto70°C
SOIC DW
Tube SN74BCT573DW
BCT573
0°C to 70°CSOIC − DW Tape and reel SN74BCT573DWR BCT573
SOP − NS Tape and reel SN74BCT573NSR BCT573
CDIP − J Tube SNJ54BCT573J SNJ54BCT573J
−55°C to 125°CCFP − W Tube SNJ54BCT573W SNJ54BCT573W
LCCC − FK Tube SNJ54BCT573FK SNJ54BCT573FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright © 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
OE LE D
OUTPUT
Q
L H H H
LHL L
LLX Q
0
H X X Z
logic diagram (positive logic)
OE
LE
1D
1Q
1
11
2
19
To Seven Other Channels
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, VO −0.5 V to 5.5 V. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO −0.5 V to VCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state: SN54BCT573 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74BCT573 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions (see Note 3)
SN54BCT573 SN74BCT573
UNIT
MIN NOM MAX MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
IIK Input clamp current −18 −18 mA
IOH High-level output current −12 −15 mA
IOL Low-level output current 48 64 mA
TAOperating free-air temperature −55 125 0 70 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54BCT573 SN74BCT573
UNIT
PARAMETER TEST CONDITIONS MIN TYP†MAX MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V
IOH = −3 mA 2.4 3.3 2.4 3.3
VOH VCC = 4.5 V IOH = −12 mA 2 3.2 V
VOH
VCC
4.5
V
IOH = −15 mA 2 3.1
V
V
V45V
IOL = 48 mA 0.38 0.55
V
VOL VCC = 4.5 V IOL = 64 mA 0.42 0.55 V
IIVCC = 5.5 V, VI = 5.5 V 0.4 0.4 mA
IIH VCC = 5.5 V, VI = 2.7 V 20 20 μA
IIL VCC = 5.5 V, VI = 0.5 V −0.6 −0.6 mA
IOS‡VCC = 5.5 V, VO = 0 −100 −225 −100 −225 mA
IOZH VCC = 5.5 V, VO = 2.7 V 50 50 μA
IOZL VCC = 5.5 V, VO = 0.5 V −50 −50 μA
ICCL VCC = 5.5 V, Outputs open 62 62 mA
ICCH VCC = 5.5 V, Outputs open 8 8 mA
ICCZ VCC = 5.5 V, Outputs open 8 8 mA
CiVCC = 5 V, VI = 2.5 V or 0.5 V 5.5 5.5 pF
CoVCC = 5 V, VO = 2.5 V or 0.5 V 7.5 7.5 pF
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°CSN54BCT573 SN74BCT573 UNIT
MIN MAX MIN MAX MIN MAX
UNIT
twPulse duration, LE high 4 4 4 ns
tsu Setup time, data before LE↓1 2.5 1 ns
thHold time, data after LE↓4 4 4 ns
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°CSN54BCT573 SN74BCT573 UNIT
PARAMETER
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
UNIT
tPLH
D
Q
2 5 7.2 1 9.8 2 8.4
ns
tPHL
D Q 2.8 5.9 8.2 1.5 10.3 2.8 9.6 ns
tPLH
LE
Q
2.4 6.1 7.2 2 9.7 2.4 8.1
ns
tPHL
LE Q 2.9 5.2 7.1 2 8.8 2.9 7.8 ns
tPZH
OE
Q
3 6.2 8.5 2.5 11 3 10.4
ns
tPZL
OE Q4.3 7.1 9.3 3.5 11.5 4.3 11 ns
tPHZ
OE
Q
2.2 3.9 5.6 1.5 7.2 2.2 6
ns
tPLZ
OE Q1.7 3.6 5.2 1 7 1.7 6 ns
SN54BCT573, SN74BCT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS071B − AUGUST 1990 − REVISED MARCH 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = tf≤ 2.5 ns, duty cycle = 50%.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
E. When measuring propagation delay times of 3-state outputs, switch S1 is open.
F. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
Test
Point
R1
CL
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-COLLECTOR OUTPUTS
R1
S1
7 V (tPZL, tPLZ, O.C.)
Open
(all others)
From Output
Under Test
Test
Point
R2
CL
(see Note A)
RL = R1 = R2
1.5 V
1.5 V
1.5 V
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing Input
(see Note B)
Data Input
(see Note B)
1.5 V 1.5 V
3 V
3 V
0 V
0 V
High-Level
Pulse
(see Note B)
Low-Level
Pulse
tw
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
tPHL
tPLH
tPLH tPHL
Input
(see Note B)
Out-of-Phase
Output
(see Note D)
1.5 V 1.5 V
1.5 V1.5 V
1.5 V 1.5 V
3 V
0 V
VOL
VOH
VOH
VOL
In-Phase
Output
(see Note D)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (see Note D)
tPHZ
tPLZ
0.3 V
tPZL
tPZH
1.5 V1.5 V
1.5 V
1.5 V
3 V
0 V
Output
Control
(low-level enable)
Waveform 1
(see Notes C and D)
Waveform 2
(see Notes C and D)
0 V
VOH
VOL
3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9583501Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9583501QRA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-9583501QSA ACTIVE CFP W 20 1 TBD Call TI Call TI
SN74BCT573DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74BCT573DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74BCT573DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74BCT573DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74BCT573DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74BCT573DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74BCT573N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74BCT573NE4 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SNJ54BCT573FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54BCT573J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54BCT573W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54BCT573, SN74BCT573 :
•Catalog: SN74BCT573
•Military: SN54BCT573
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74BCT573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74BCT573DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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