CY7C1339
4
Introduction
Functional Overview
All synchrono us inp uts pass th rough inp ut regi sters con tr olle d
by the rising edge of the clock. All data outputs pass through
outpu t regist ers contr olled b y the rising ed ge of the clock. Max-
imum access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).
The CY7C133 9 supports secondary cache in sys tems util izin g
either a linear or interleaved bur st sequence. The i nterleaved
burst ord er supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear
burst sequence. The burst order i s user select able, and is de-
termined by sampl ing the MODE input. Accesses can be initi-
ated with either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two- bit on-ch ip wrap around burst co unter captu res the first ad-
dress in a burst sequence and automatically increments the
address for the rest of t h e burst a cce ss.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) input s. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed wri te ci rcuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE ) provide for easy bank se-
lection and output three-state control. ADSP is ignor ed if CE1
is HIGH.
Singl e Read Accesses
This access is initiated when the fol lowing condi tions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE 2, CE3 ar e all ass erted acti ve, a nd (3) the write s ignals
(GW, B W E) are all deser ted HIGH . ADSP is i g nored if C E 1 is
HIGH. The address presented to the address inputs (A[16:0]) is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Regist ers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LO W. The only e x ceptio n occurs when the SRAM is emerg ing
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once t he SRAM is deselect ed at cl ock ri se by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Singl e Writ e Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE 2, CE3 a re all a sserted act iv e. Th e addres s pr esente d
to A [16:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BW E, and BW[3:0]) and ADV inputs are ig-
no red during this fi rst cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second cloc k rise , the
data presented t o the DQ[31:0] inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write oper ation is contro ll ed by BW E and BW[3:0] sig-
nals. The CY7C1339 provides byte write capability that is de-
scribed in the Write Cycle Descriptions table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW[3:0]) input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1339 is a common I/O device, the Output
Enable (OE) must be deser ted HIGH before presenti ng data
to the DQ[31:0] inputs . Doing so wi ll three- stat e the out put driv -
ers. As a safety precaution, DQ[31:0] are automatically
three- stated whenever a write c ycle is de tected, regardless of
the stat e of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE1, CE2, CE3 are all asserted activ e, and
(4) t he approp riate c ombinati on of t he writ e input s (GW, BWE,
and BW[3:0]) are asserted active to conduct a write to the de-
sired byte(s). ADSC- triggered write ac cess es r equir e a singl e
clock cycle to complete. The address presented to A[16:0] is
loaded into the address register and the address advancement
logic whil e being delivered to the RAM core. The ADV inp u t is
ignored during this cycle. If a global write is conducted, the
data pr esented to t he DQ[31:0] is writ ten in to the c orrespondi ng
address l oca tion in the RAM core . If a b yte write is conduc ted ,
only the select ed bytes are wr itten. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self- timed write me chanism has been provided to simpli fy the
write operations .
Because the CY7C1339 is a common I/O device, the Output
Enable (OE) must be deser ted HIGH before presenti ng data
to the DQ[31:0] inputs . Doing so wi ll three- stat e the out put driv -
ers. As a safety precaution, DQ[31:0] are automatically
three- stated whenever a write c ycle is de tected, regardless of
the stat e of OE.
Burst Sequences
The CY7C1339 pr ov ides a tw o-bit wrapar ound count er , f ed b y
A[1:0], that imp lements ei ther an in terleaved or linear burst se-
quence. The interleaved burst sequence is designed specifi-
cally to support Intel Pentium applications. The linear burst
sequence is designed to suppor t processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input .
Asser ting ADV LO W at clock rise wil l aut om atically inc rement
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burs t Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
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