1
®
IVC102
I
IN
V
B
1
2
3
4
5
6
11 12 13
Digital
Ground
Analog
Ground
Logic Low closes switches
9
10
14
V
O
V+
V–
S
1
S
2
Ionization
Chamber
Photodiode
60pF
30pF
10pF
S
1
C
1
C
2
C
3
S
2
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
PRECISION SWITCHED INTEGRATOR
TRANSIMPEDANCE AMPLIFIER
APPLICATIONS
● PRECISION LOW CURRENT MEASUREMENT
● PHOTODIODE MEASUREMENTS
● IONIZATION CHAMBER MEASUREMENTS
● CURRENT/CHARGE-OUTPUT SENSORS
● LEAKAGE CURRENT MEASUREMENT
IVC102
FEATURES
● ON-CHIP INTEGRATING CAPACITORS
● GAIN PROGRAMMED BY TIMING
● LOW INPUT BIAS CURRENT: 750fA max
● LOW NOISE
● LOW SWITCH CHARGE INJECTION
● FAST PULSE INTEGRATION
● LOW NONLINEARITY: 0.005% typ
●14-PIN DIP, SO-14 SURFACE MOUNT
DESCRIPTION
The IVC102 is a precision integrating amplifier with
FET op amp, integrating capacitors, and low leakage
FET switches. It integrates low-level input current for
a user-determined period, storing the resulting voltage
on the integrating capacitor. The output voltage can be
held for accurate measurement. The IVC102 provides
a precision, lower noise alternative to conventional
transimpedance op amp circuits that require a very
high value feedback resistor.
The IVC102 is ideal for amplifying low-level sensor
currents from photodiodes and ionization chambers.
The input signal current can be positive or negative.
TTL/CMOS-compatible timing inputs control the inte-
gration period, hold and reset functions to set the
effective transimpedance gain and to reset (discharge)
the integrator capacitor.
Package options include 14-Pin plastic DIP and SO-14
surface-mount packages. Both are specified for the
–40°C to 85°C industrial temperature range.
© 1996 Burr-Brown Corporation PDS-1329A Printed in U.S.A. June, 1996
0V
Hold Integrate Hold Reset
Positive or Negative
Signal Integration
S
1
S
2
I
IN
(t)
V
O =
–1
∫
dt
C
INT
SBFS009
2
®
IVC102
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
NOTES: (1) Standard test timing: 1ms integration, 200µs hold, 100µs reset. (2) Hold mode output voltage after 1ms integration of zero input current. Includes op
amp offset voltage, integration of input error current and switch charge injection effects.
SPECIFICATIONS
At TA = +25°C, VS = ±15V, RL = 2kΩ, CINT = C1 + C2 + C3, 1ms integration period(1), unless otherwise specified.
IVC102P, U
PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSFER FUNCTION VO = –(IIN)(TINT)/CINT
Gain Error CINT = C1 + C2 + C3±5 +25/–17 %
vs Temperature ±25 ppm/°C
Nonlinearity VO = ±10V ±0.005 %
Input Current Range ±100 µA
Offset Voltage(2) IIN = 0, CIN = 50pF –5 ±20 mV
vs Temperature ±30 µV/°C
vs Power Supply VS = +4.75/–10 to +18/–18V 150 750 µV/V
Droop Rate, Hold Mode –1 nV/µs
OP AMP
Input Bias Current S1, S2 Open –100 ±750 fA
vs Temperature See Typical Curve
Offset Voltage (Op Amp VOS)±0.5 ±5mV
vs Temperature ±5µV/°C
vs Power Supply VS = +4.75/–10 to +18/–18V 10 100 µV/V
Noise Voltage f = 1kHz 10 nV/√Hz
INTEGRATION CAPACITORS
C1 + C2 + C380 100 120 pF
vs Temperature ±25 ppm/°C
C110 pF
C230 pF
C360 pF
OUTPUT
Voltage Range, Positive RL = 2kΩ(V+)–3 (V+)–1.3 V
Negative RL = 2kΩ(V–)+3 (V–)+2.6 V
Short-Circuit Current ±20 mA
Capacitive Load Drive 500 pF
Noise Voltage See Typical Curve
DYNAMIC CHARACTERISTIC
Op Amp Gain-Bandwidth 2 MHz
Op Amp Slew Rate 3V/µs
Reset
Slew Rate 3V/µs
Settling Time, 0.01% 10V Step 6 µs
DIGITAL INPUTS (TTL/CMOS Compatible)
VIH (referred to digital ground) (Logic High) 2 5.5 V
VIL (referred to digital ground) (Logic Low) –0.5 0.8 V
IIH VIH = 5V 2 µA
IIL VIL = 0V 0 µA
Switching Time 100 ns
POWER SUPPLY
Voltage Range: Positive +4.75 +15 +18 V
Negative –10 –15 –18 V
Current: Positive 4.1 5.5 mA
Negative –1.6 –2.2 mA
Analog Ground –0.2 mA
Digital Ground –2.3 mA
TEMPERATURE RANGE
Operating Range –40 85 °C
Storage –55 125 °C
Thermal Resistance,
θ
JA
DIP 100 °C/W
SO-14 150 °C/W
3
®
IVC102
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V+ to V– .................................................................... 36V
Logic Input Voltage...................................................................... V– to V+
Output Short Circuit to Ground ............................................... Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –55°C to +125°C
Lead Temperature (soldering, 10s) ................................................. 300°C
PIN CONNECTIONS
Top View 14-Pin DIP/
SO-14 Surface Mount
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER(1)
IVC102P 14-Pin DIP 010
IVC102U SO-14 Surface Mount 235
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
V+
Digital Ground
S
2
S
1
V
O
V–
NC
Analog Ground
I
IN
–In
C
1
C
2
C
3
NC
NC = No Internal Connection
Connect to Analog Ground for Lowest Noise
14
13
12
11
10
9
8
1
2
3
4
5
6
7
4
®
IVC102
10 100 1000
C
IN
(pF)
TOTAL OUTPUT NOISE vs C
IN
1000
100
10
1
Noise Voltage (µVrms)
rms Variation
of 100 Measurement
Cycles, T
INT
= 1ms. C
INT
= 10pF
C
INT
= 30pF
C
INT
= 100pF
C
INT
= 300pF
C
INT
= 1000pF
Reset Mode, S
1
Open, S
2
Closed.
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, RL = 2kΩ, CINT = C1 + C2 + C3, 1ms integration period, unless otherwise specified.
–50 –25 0 25 50 75 100 125
Temperature (°C)
INPUT BIAS CURRENT vs TEMPERATURE
100p
10p
1p
100f
10f
Input Bias Current (A)
S1, S2 Open
0 100 200 300 400 500 600 700 800 900 1000
C
INT
(pF)
RESET TIME vs C
INT
30
25
20
15
10
5
0
Reset Time (µs)
Time Required to
Reset from ±10V
to 0V. 0.01%
1%
10 100 1000
Input Capacitance, C
IN
(pF)
S
1
CHARGE INJECTION vs INPUT CAPACITANCE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
Charge Injection, ∆Q (pC)
100pF
∆VO
=
∆Q
100pF
S1
CIN
10 100 1000
Input Capacitance, CIN (pF)
S2 CHARGE INJECTION vs INPUT CAPACITANCE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Charge Injection, ∆Q (pC)
(V+) = +18V
(V+) = +15V
(V+) = +4.75V
100pF
∆V
O
=
∆Q
100pF
C
IN
S
2
5
®
IVC102
Charge Injection
of S
2
Op Amp V
OS
+
I
IN
• R
S2
0V
Integrate
(S
2
Open)
T
1
0V
S
2
V
O
T
2
10µs
Reset 10µs
Reset
I
IN
Photodiode
60pF
30pF
10pF
0.1µF
0.1µF
1
2
3
4
5
6
11 12 13
10 V
O
14
V+
+15V
Logic
High
(+5V)
S
1
C
1
C
2
C
3
S
2
Digital
Ground
Analog
Ground
S
2
9
–15V
V–
Digital
Data
Sampling
A/D
Converter
See timing
signal below
APPLICATION INFORMATION
Figure 1 shows the basic circuit connections to operate the
IVC102. Bypass capacitors are shown connected to the
power supply pins. Noisy power supplies should be avoided
or decoupled and carefully bypassed.
The Analog Ground terminal, pin 1, is shown internally
connected to the non-inverting input of the op amp. This
terminal connects to other internal circuitry and should be
connected to ground. Approximately 200µA flows out of
this terminal.
Digital Ground, pin 13, should be at the same voltage
potential as analog ground (within 100mV). Analog and
Digital grounds should be connected at some point in the
system, usually at the power supply connections to the
circuit board. A separate Digital Ground is provided so that
noisy logic signals can be referenced to separate circuit
board traces.
Integrator capacitors C1, C2 and C3 are shown connected in
parallel for a total CINT = 100pF. The IVC102 can be used
for a wide variety of integrating current measurements. The
input signal connections and control timing and CINT value
will depend on the sensor or signal type and other applica-
tion details.
BASIC RESET-AND-INTEGRATE MEASUREMENT
Figure 1 shows the circuit and timing for a simple reset-and-
integrate measurement. The input current is connected di-
rectly to the inverting input of the IVC102, pin 3. Input
current is shown flowing out of pin 3, which produces a
positive-going ramp at VO. Current flowing into pin 3 would
produce a negative-going ramp.
A measurement cycle starts by resetting the integrator output
voltage to 0V by closing S2 for 10µs. Integration of the input
current begins when S2 opens and the input current begins to
charge CINT. VO is measured with a sampling a/d converter
at the end of an integration period, just prior to the next reset
period. The ideal result is proportional to the average input
current (or total accumulated charge).
Switch S2 is again closed to reset the integrator output to 0V
before the next integration period.
This simple measurement arrangement is suited to many
applications. There are, however, limitations to this basic
approach. Input current continues to flow through S2 during
the reset period. This leaves a small voltage on CINT equal
to the input current times RS2, the on-resistance of S2,
approximately 1.5kΩ.
FIGURE 1. Reset-and Integrate Connections and Timing.
Figure 1b
Figure 1a
6
®
IVC102
C
INT
for constant I
IN
, at the end of T
INT
V
O
= –I
IN
T
INT
C
INT
V
O
I
IN
I
IN
(t)
V
O
=
–1
∫
dt
C
INT
In addition, the offset voltage of the internal op amp and
charge injection of S2 contribute to the voltage on C INT at the
start of integration.
Performance of this basic approach can be improved by
sampling VO after the reset period at T1 and subtracting this
measurement from the final sample at T2. Op amp offset
voltage, charge injection effects and I•RS2 offset voltage on
S2 are removed with this two-point measurement. The effec-
tive integration period is the time between the two measure-
ments, T2-T1.
COMPARISON TO CONVENTIONAL TRANSIMPEDANCE AMPLIFIERS
With the conventional transimpedance amplifier circuit
of Figure 2a, input current flows through the feedback
resistor, RF, to create a proportional output voltage.
VO = –IIN RF
The transimpedance gain is determined by RF. Very large
values of RF are required to measure very small signal
current. Feedback resistor values exceeding 100MΩ are
common.
The IVC102 (Figure 2b) provides a similar function,
converting an input current to an output voltage. The
input current flows through the feedback capacitor, CINT,
charging it at a rate that is proportional to the input
current. With a constant input current, the IVC102’s
output voltage is
VO = –IIN TINT/CINT
after an integration time of TINT.
VO is proportional to the integration time, TINT, and
inversely proportional to the feedback capacitor, CINT.
The effective transimpedance gain is TINT /CINT. Ex-
tremely high gain that would be impractical to achieve
with a conventional transimpedance amplifier can be
achieved with small integration capacitor values and/or
long integration times. For example the IVC102 with
CINT = 100pF and TINT = 100ms provides an effective
transimpedance of 1GΩ. A 10nA input current would
produce a 10V output after 100ms integration.
The integrating behavior of the IVC102 reduces noise by
averaging the input noise of the sensor, amplifier, and
external sources.
Conventional Transimpedance Amplifier
Figure 2a Integrating Transimpedance Amplifier
Figure 2b
R
F
V
O
= –I
IN
R
F
V
O
I
IN
CURRENT-OUTPUT SENSORS
Figure 3 shows a model for many current-output sensors
such as photodiodes and ionization chambers. Sensor output
is a signal-dependent current with a very high source resis-
tance. The output is generally loaded into a low impedance
FIGURE 2. Comparison to a Conventional Transimpedance Amplifier.
so that the terminal voltage is kept very low. Typical sensor
capacitance values range from 10pF to over 100pF. This
capacitance plays a key role in operation of the switched-
input measurement technique (see next section).
Provides time-continuous output
voltage proportional to IIN.
Output voltage after integration period is
proportional to average IIN throughout
the period.
7
®
IVC102
60pF
30pF
10pF
0.1µF
0.1µF
1
I
Photodiode
Sensor
RC 2
3
4
5
6
11
I: Signal - Dependent Current
R: Sensor Resistance
C: Sensor Capacitance
12 13
10 V
O
14
V+
+15V
S
1
S
1
C
1
C
2
C
3
S
2
S
2
9
–15V
V–
Digital
Data
A/D
Converter
See timing
signals below
3a
3b
3c
Charge transferred
from sensor C
to C
INT
.
A
A
B
B
Transfer Function
Offset Voltage
Ramp due to
input bias current
(exaggerated).
Effective
Signal Integration
Period, T
S
V
O
waveform with
approx. half-scale input current.
V
O
waveform with
zero input current.
∆Q
S
1
Opening
0V
0V
0V
V
O
S
2
S
1
V
O
0V
+10mV
–10mV
10µs
Hold 10µs
Reset
10µs
Hold 10µs
Reset 10µs
Pre-Int.
Hold
∆Q
S
2
Opening
∆Q
S
1
Closing
Op Amp
V
OS
(S
1
Open) (S
1
Closed)
(S
2
Open)
FIGURE 3. Switched-Input Measurement Technique.
Input connections and timing are shown in Figure 3.
The timing diagram, Figure 3b, shows that S1 is closed only
when S2 is open. During the short period that S1 is open
(30µs in this timing example), any signal current produced
by the sensor will charge the sensor’s source capacitance.
This charge is then transferred to CINT when S 1 is closed. As
a result, no charge produced by the sensor is lost and the
input signal is continuously integrated. Even fast input
pulses are accurately integrated.
SWITCHED-INPUT MEASUREMENT TECHNIQUE
While the basic reset-and-integrate measurement arrange-
ment in Figure 1 is satisfactory for many applications, the
switched-input timing technique shown in Figure 3 has
important advantages. This method can provide continuous
integration of the input signal. Furthermore, it can hold the
output voltage constant after integration for stable conver-
sion (desirable for a/d converter without a sample/hold).
8
®
IVC102
The input current, IIN, is shown as a conventional current
flowing into pin 2 in this diagram but the input current could
be bipolar (positive or negative). Current flowing out of pin
2 would produce a positive-ramping VO.
The timing sequence proceeds as follows:
Reset Period
The integrator is reset by closing switch S2 with S 1 open. A
10µs reset time is recommended to allow the op amp to slew
to 0V and settle to its final value.
Pre-Integration Hold
S2 is opened, holding VO constant for 10µs prior to integra-
tion. This pre-integration hold period assures that S2 is fully
open before S1 is closed so that no input signal is lost. A
minimum of 1µs is recommended to avoid switching over-
lap. The 10µs hold period shown in Figure 3b also allows an
a/d converter measurement to be made at point A. The
purpose of this measurement at A is discussed in the “Offset
Errors” section.
Integration on CINT
Integration of the input current on CINT begins when S1 is
closed. An immediate step output voltage change occurs as
the charge that was stored on the input sensor capacitance is
transferred to CINT. Although this period of charging CINT
occurs only while S1 is closed, the charge transferred as S1
is closed causes the effective integration time to be equal to
the complete conversion period—see Figure 3b.
The integration period could range from 100µs to many
minutes, depending on the input current and CINT value.
While S1 is closed, I IN charges CINT, producing a negative-
going ramp at the integrator output voltage, VO. The output
voltage at the end of integration is proportional to the
average input current throughout the complete conversion
cycle, including the integration period, reset and both hold
periods.
Hold Period
Opening S1 halts integration on CINT. Approximately 5µs
after S1 is opened, the output voltage is stable and can be
measured (at point B). The hold period is 10µs in this
example. CINT remains charged until a S2 is again closed, to
reset for the next conversion cycle.
In this timing example, S 1 is open for a total of 30 µs. During
this time, signal current from the sensor charges the sensor
source capacitance. Care should be used to assure that the
voltage developed on the sensor does not exceed approxi-
mately 200mV during this time. The IIN terminal, pin 2, is
internally clamped with diodes. If these diodes forward bias,
signal current will flow to ground and will not be accurately
integrated.
A maximum of 333nA signal current could be accurately
integrated on a 50pF sensor capacitance for 30µs before
200mV would be developed on the sensor.
IMAX = (50pF) (200mV)/30µs = 333nA
OFFSET ERRORS
Figure 3c shows the effect on VO due to op amp input offset
voltage, input bias current and switch charge injection. It
assumes zero input current from the sensor. The various
offsets and charge injection (∆Q) jumps shown are typical of
that seen with a 50pF source capacitance. The specified
“transfer function offset voltage” is the voltage measured
during the hold period at B. Transfer function offset voltage
is dominated by the charge injection of S2 opening and op
amp VOS. The opening and closing charge injections of S1
are very nearly equal and opposite and are not significant
contributors.
Note that using a two-point difference measurement at A
and B can dramatically reduce offset due to op amp VOS and
S2 charge injection. The remaining offset with this B-A
measurement is due to op amp input bias current charging
CINT. This error is usually very small and is exaggerated in
the figure.
DIGITAL SWITCH INPUTS
The digital control inputs to S1 and S2 are compatible with
standard CMOS or TTL logic. Logic input pins 11 and 12
are high impedance and the threshold is approximately 1.4V
relative to Digital Ground, pin 13. A logic “low” closes the
switch.
Use care in routing these logic signals to their respective
input pins. Capacitive coupling of logic transitions to sensi-
tive input nodes (pins 2 through 6) and to the positive power
supply (pin 14) will dramatically increase charge injection
and produce errors. Route these circuit board traces over a
ground plane (digital ground) and route digital ground traces
between logic traces and other critical traces for lowest
charge injection. See Figure 4.
5V logic levels are generally satisfactory. Lower voltage
logic levels may help reduce charge injection errors, de-
pending on circuit layout. Logic high voltages greater than
5.5V, or higher than the V+ supply are not recommended.
FIGURE 4. Circuit Board Layout Techniques.
•
•• •
•
•
•
•
•
•
•
•
•
•
•
Input trace guarded
all the way to sensor. Switch logic inputs
guarded by digital
ground.
Analog
Ground
Digital
Ground
Pins 7 and 8 have no internal
connection but are connected to
ground for lowest noise pickup.
V+
Input nodes
guarded by
analog ground.
V–
V
O
S
1
S
2
14
8
7
1
9
®
IVC102
CHOOSING CINT
Internal capacitors C1, C2 and C3 are high quality metal/
oxide types with low leakage and excellent dielectric char-
acteristics. Temperature stability is excellent—see typical
curve. They can be connected for CINT = 10pF, 30pF, 40pF,
60pF, 70pF, 90pF or 100pF. Connect unused internal ca-
pacitor pins to analog ground. Accuracy is ±20%, which
directly influences the gain of the transfer function.
A larger value external CINT can be connected between pins
3 and 10 for slower/longer integration. Select a capacitor
type with low leakage and good temperature stability.
Teflon, polystyrene or polypropylene capacitors generally
provide excellent leakage, temperature drift and voltage
coefficient characteristics. Lower cost types such as NPO
ceramic, mica or glass may be adequate for many applica-
tions. Larger values for CINT require a longer reset time—see
typical curves.
FREQUENCY RESPONSE
Integration of the input signal for a fixed period produces a
deep null (zero response) at the frequency 1/TINT and its
harmonics. An ac input current at this frequency (or its
harmonics) has zero average value and therefore produces
no output. This property can be used to position response
nulls at critical frequencies. For example, a 16.67ms integra-
tion period produces response nulls at 60Hz, 120Hz, 180Hz,
etc., which will reject ac line frequency noise and its har-
monics. Response nulls can be positioned to reduce interfer-
ence from system clocks or other periodic noise.
Response to all frequencies above f = 1/TINT falls at –20dB/
decade. The effective corner frequency of this single-pole
response is approximately 1/2.8TINT.
For the simple reset-and-integrate measurement technique,
TINT is equal to the to the time that S 2 is open. The switched-
input technique, however, effectively integrates the input
signal throughout the full measurement cycle, including the
reset period and both hold periods. Using the timing shown
in Figure 3, the effective integration time is 1/Ts, where Ts
is the repetition rate of the sampling.
INPUT IMPEDANCE
The input impedance of a perfect transimpedance circuit is
zero ohms. The input voltage ideally would be zero for any
input current. The actual input voltage when directly driving
the integrator input (pin 3) is proportional to the output slew
rate of the integrator. A 1V/µs slew rate produces approxi-
mately 100mV at pin 3. The input of the integrator can be
modeled as a resistance:
RIN = 10–7/CINT
with RIN in Ω and CINT in Farads.
Using the internal CINT = C1 + C2 + C3 = 100pF
RIN = 10–7/ 100pF = 1kΩ
(2)
(3)
INPUT BIAS CURRENT ERRORS
Careful circuit board layout and assembly techniques are
required to achieve the very low input bias current capability
of the IVC102. The critical input connections are at ground
potential, so analog ground should be used as a circuit board
guard trace surrounding all critical nodes. These include
pins 2, 3, 4, 5 and 6. See Figure 4.
Input bias current increases with temperature—see typical
performance curve Input Bias Current vs Temperature.
HOLD MODE DROOP
Hold-mode droop is a slow change in output voltage prima-
rily due to op amp input bias current. Droop is specified
using the internal CINT = 100pF and is based on a –100fA
typical input bias current. Current flows out of the inverting
input of the internal op amp.
With CINT = 100pF, the droop rate is typically only
1nV/µs—slow enough that it rarely contributes significant
error at moderate temperatures.
Since the input bias current increases with temperature, the
droop rate will also increase with temperature. The droop
rate will approximately double for each 10°C increase in
junction temperature—see typical curves.
Droop rate is inversely proportional to CINT. If an external
integrator capacitor is used, a low leakage capacitor should
be selected to preserve the low droop performance of the
IVC102.
INPUT CURRENT RANGE
Extremely low input currents can be measured by integrat-
ing for long periods and/or using a small value for CINT.
Input bias current of the internal op amp is the primary
source of error.
Larger input currents can be measured by increasing the
value of CINT and/or using a shorter integration time. Input
currents greater than 200 µA should not be applied to the pin
2 input, however. The approximately 1.5k Ω series resistance
of S1 will create an input voltage at pin 2 that will begin to
forward-bias internal protection clamp diodes. Any current
that flows through these protection diodes will not be accu-
rately integrated. See “Input Impedance” section for more
information on input current-induced voltage.
Input current greater than 200µA can, however, be con-
nected directly to pin 3, using the simple reset-integrate
technique shown in Figure 1. Current applied at this input
can be externally switched to avoid excessive I•R voltage
across S2 during reset. Inputs up to 5mA at pin 3 can be
accurately integrated if CINT is made large enough to limit
slew rate to less than 1V/µs. A 5mA input current would
require CINT = 5nF to produce a 1V/µs slew rate. The input
current appears as load current to the internal op amp,
reducing its ability to drive an external load.
Droop Rate =–100fA
C
INT
Teflon E. I. Du Pont de Nemours & Co.
10
®
IVC102
The input resistance seen at pin 2 includes an additional
1.5kΩ, the on-resistance of S1. The total input resistance is
the sum of the switch resistance and RIN, or 2.5kΩ in this
example.
Slew rate limit of the internal op amp is approximately
3V/µs. For most applications, the slew rate of VOUT should
be limited to 1V/µs or less. The rate of change is propor-
tional to IIN and inversely proportional to CINT:
This can be important in some applications since the slew-
induced input voltage is applied to the sensor or signal
source. The slew-induced input voltage can be reduced by
increasing CINT, which reduces the output slew rate.
NONLINEARITY
Careful nonlinearity measurements of the IVC102 yield
typical results of approximately ±0.005% using the internal
input capacitors (CINT = 100pF). Nonlinearity will be de-
graded by using an external integrator capacitor with poor
voltage coefficient. Performance with the internal capacitors
is typically equal or better than the sensors it is used to
measure. Actual application circuits with sensors such as a
photodiode may have other sources of nonlinearity.
1/10T
INT
1/T
INT
10/T
INT
●●●
–20dB/decade
slope
Frequency
0
–10
–20
–30
–40
–50
Frequency Response (dB)
Corner at
f = 0.32/T
INT
–3dB at
f = 0.44/T
INT
FIGURE 5. Frequency Response of Integrating Converter.
Slew Rate =I
IN
C
INT
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
IVC102P OBSOLETE PDIP N 14 TBD Call TI Call TI
IVC102U ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
IVC102U/2K5 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
IVC102U/2K5G4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 12-Oct-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
IVC102U/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
IVC102U/2K5 SOIC D 14 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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