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1
FEATURES APPLICATIONS
DESCRIPTION
ADS7884
ADS7885
SLAS567 – MARCH 2008
10-/8-BIT, 3-MSPS, MICRO-POWER, MINIATURESAR ANALOG-TO-DIGITAL CONVERTERS
•Base Band Converters in Radio•3-MHz Sample Rate Serial Device
Communication•10-Bit Resolution – ADS7884
•Motor Current/Bus Voltage Sensors in Digital•8-Bit Resolution – ADS7885
Drives•Zero Latency
•Optical Networking (DWDM, MEMS Based•48-MHz Serial Interface
Switching)•Supply Range: 2.7 V to 5.5 V
•Optical Sensors•Battery Powered Systems•Low Power Dissipation:
•Medical Instrumentations– 6.8 mW at 3-V V
DD
, 2.5 MSPS
•High-Speed Data Acquisition Systems– 15 mw at 5-V V
DD
, 3 MSPS
•High-Speed Closed-Loop Systems•± 0.3 LSB INL, ± 0.3 LSB DNL – ADS7884•± 0.15 LSB INL, ± 0.1 LSB DNL – ADS7885•61.7 dB SINAD, – 81 dB THD – ADS7884•49.8 dB SINAD, – 68 dB THD – ADS7885•Unipolar Input Range: 0 V to V
DD•Powerdown Current: 1 µA•Wide Input Bandwidth: 30 MHz at 3 dB•6-Pin SOT23 Package
The ADS7884 is a 10-bit, 3-MSPS analog-to-digital converter (ADC), and the ADS7885 is a 8-bit, 3-MSPS ADC.The devices include a capacitor based SAR A/D converter with inherent sample and hold. The serial interface ineach device is controlled by the CS and SCLK signals for glueless connections with microprocessors and DSPs.The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial data output.
The devices operate from a wide supply range from 2.7 V to 5.5 V. The low power consumption of the devicesmake them suitable for battery-powered applications. The devices also include a power saving powerdownfeature for when the devices are operated at lower conversion speeds.
The high level of the digital input to the device is not limited to device V
DD
. This means the digital input can go ashigh as 5.5 V when device supply is 2.7 V. This feature is useful when digital signals are coming from othercircuit with different supply levels. Also this relaxes restriction on power up sequencing.
The ADS7884 and ADS7885 are available in a 6-pin SOT23 package and are specified for operation from – 40 °Cto 125 °C.
Micro-Power Miniature SAR Converter Family
BIT < 300 KSPS 300 KSPS – 1.25 MSPS 3 MSPS
12-Bit ADS7866 (1.2 V
DD
to 3.6 V
DD
) ADS7886 (2.35 V
DD
to 5.25 V
DD
) —10-Bit ADS7867 (1.2 V
DD
to 3.6 V
DD
) ADS7887 (2.35 V
DD
to 5.25 V
DD
) ADS7884 (2.7 V
DD
to 5.5 V
DD
)8-Bit ADS7868 (1.2 V
DD
to 3.6 V
DD
) ADS7888 (2.35 V
DD
to 5.25 V
DD
) ADS7885 (2.7 V
DD
to 5.5 V
DD
)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
SCLK
+IN
VDD
CDAC
SAR
COMPARATOR
OUTPUT
LATCHES
&
3−STATE
DRIVERS
CONVERSION
&
CONTROL
LOGIC
SDO
ADS7884/ADS7885 CS
ABSOLUTE MAXIMUM RATINGS
(1)
ADS7884
ADS7885
SLAS567 – MARCH 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
(1)
MAXIMUM MAXIMUM NO MISSING
PACKAGE TRANSPORTINTEGRAL DIFFERENTIAL CODES AT PACKAGE TEMPERATURE PACKAGE ORDERINGDEVICE DESIGNAT MEDIALINEARITY LINEARITY RESOLUTION TYPE RANGE MARKING INFORMATIONOR QUANTITY(LSB) (LSB) (BIT)
Tape and7884 ADS7884SDBVT
reel 2506-PinADS7884 ± 0.8 ± 0.8 10 DBV – 40 °C to 125 °CSOT23
Tape and7884 ADS7884SDBVR
reel 3000
Tape and7885 ADS7885SDBVT
reel 2506-PinADS7885 ± 0.4 ± 0.4 8 DBV – 40 °C to 125 °CSOT23
Tape and7885 ADS7885SDBVR
reel 3000
(1) For most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.
UNIT
+IN to AGND – 0.3 V to +V
DD
+0.3 V+V
DD
to AGND – 0.3 V to 7.0 VDigital input voltage to GND – 0.3V to (7.0 V)Digital output to GND – 0.3 V to (+V
DD
+ 0.3 V)Operating temperature range – 40 °C to 125 °CStorage temperature range – 65 °C to 150 °CJunction temperature (T
J
Max) 150 °CPower dissipation, SOT23 package (T
J
Max – T
A
)/ θ
JA
Thermal impedance, θ
JA
SOT23 295.2 °C/WVapor phase (60 sec) 215 °CLead temperature, soldering
Infrared (15 sec) 220 °C
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.
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ADS7884 SPECIFICATIONS
ADS7884
ADS7885
SLAS567 – MARCH 2008
+V
DD
= 2.7 V to 5.5 V, T
A
= – 40 °C to 125 °C, f
sample
= 2.5 MSPS for V
DD
= 2.7 V to 3.6 V, f
sample
= 3 MSPS for V
DD
= 3.6 V to5.5 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span
(1)
0 V
DD
VAbsolute input voltage range +IN – 0.20 V
DD
+0.20 VC
i
Input capacitance
(2)
27 pFI
Ilkg
Input leakage current T
A
= 125 °C 40 nA
SYSTEM PERFORMANCE
Resolution 10 BitsNo missing codes 10 BitsINL Integral nonlinearity – 0.8 ± 0.3 0.8 LSB
(3)
DNL Differential nonlinearity – 0.8 ± 0.3 0.8 LSBE
O
Offset error
(4) (5) (6)
– 1 ± 0.2 1 LSBE
G
Gain error
(5)
– 1 ± 0.2 1 LSB
SAMPLING DYNAMICS
Conversion time 48-MHz SCLK, V
DD
= 5 V 224 240 nsAcquisition time 93.3 nsMaximum throughput rate 48-MHz SCLK, V
DD
= 5 V 3 MHzAperture delay 10 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion
(7)
100 kHz – 81 dBSINAD Signal-to-noise and distortion 100 kHz 60 61.7 dBSFDR Spurious free dynamic range 100 kHz 81 dBFull power bandwidth At – 3 dB 30 MHz
DIGITAL INPUT/OUTPUT
Logic family — CMOS
V
DD
= 2.7 V to 3.6 V 1.5 5.5V
IH
High-level input voltage VV
DD
= 3.6 V to 5.5 V 2.2 5.5V
DD
= 5 V 0.8V
IL
Low-level input voltage VV
DD
= 3 V 0.4V
OH
High-level output voltage At I
source
= 200 µA V
DD
– 0.2
VV
OL
Low-level output voltage At I
sink
= 200 µA 0.4
POWER SUPPLY REQUIREMENTS
+V
DD
Supply voltage 2.7 3.3 5.5 VAt V
DD
= 3.0 V, 2.5-MSPS throughput 2.25 3At V
DD
= 3.0 V, static state 1.8Supply current (normal mode) mAAt V
DD
= 5.0 V, 3-MSPS throughput 3 4At V
DD
= 5.0 V, static state 2SCLK off 1Power down state supply current µASCLK on (48 MHz) 90 200V
DD
= 5 V, 3 MSPS 15 20Power dissipation mWV
DD
= 3 V, 2.5 MSPS 6.8
(1) Ideal input span; does not include gain or offset error.(2) Refer to Figure 43 for details on sampling circuit(3) LSB means least significant bit(4) Measured relative to an ideal full-scale input(5) Offset error and gain error ensured by characterization.(6) First transition of 000H to 001H at (V
ref
/2
10
)(7) Calculated on the first nine harmonics of the input frequency
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
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ADS7884
ADS7885
SLAS567 – MARCH 2008
ADS7884 SPECIFICATIONS (continued)+V
DD
= 2.7 V to 5.5 V, T
A
= – 40 °C to 125 °C, f
sample
= 2.5 MSPS for V
DD
= 2.7 V to 3.6 V, f
sample
= 3 MSPS for V
DD
= 3.6 V to5.5 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5 V 10Power dissipation in static state mWV
DD
= 3 V 5.4Powerdown time 0.1 µsPowerup time 0.8 µs
TEMPERATURE RANGE
Specified performance – 40 125 °C
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ADS7885 SPECIFICATIONS
ADS7884
ADS7885
SLAS567 – MARCH 2008
+V
DD
= 2.7 V to 5.5 V, T
A
= – 40 °C to 125 °C, f
sample
= 2.5 MSPS for V
DD
= 2.7 V to 3.6 V, f
sample
= 3 MSPS for V
DD
= 3.6 V to5.5 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span
(1)
0 V
DD
VAbsolute input voltage range +IN – 0.20 V
DD
+0.20 VC
i
Input capacitance
(2)
27 pFI
Ilkg
Input leakage current T
A
= 125 °C 40 nA
SYSTEM PERFORMANCE
Resolution 8 BitsNo missing codes 8 BitsINL Integral nonlinearity – 0.4 ± 0.15 0.4 LSB
(3)
DNL Differential nonlinearity – 0.4 ± 0.1 0.4 LSBE
O
Offset error
(4) (5) (6)
– 0.4 ± 0.1 0.4 LSBE
G
Gain error
(5)
– 0.5 ± 0.1 0.5 LSB
SAMPLING DYNAMICS
Conversion time 48-MHz SCLK, V
DD
= 5 V 182 198 nsAcquisition time 3 MSPS mode 135 nsMaximum throughput rate 48-MHz SCLK, V
DD
= 5 V 3 MHzAperture delay 10 ns
DYNAMIC CHARACTERISTICS
THD Total harmonic distortion
(7)
100 kHz – 68 dBSINAD Signal-to-noise and distortion 100 kHz 49 49.8 dBSFDR Spurious free dynamic range 100 kHz 74 dBFull power bandwidth At – 3 dB 30 MHz
DIGITAL INPUT/OUTPUT
Logic family — CMOS
V
DD
= 2.7 V to 3.6 V 1.5 5.5V
IH
High-level input voltage VV
DD
= 3.6 V to 5.5 V 2.2 5.5V
DD
= 5 V 0.8V
IL
Low-level input voltage VV
DD
= 3 V 0.4V
OH
High-level output voltage At I
source
= 200 µA V
DD
– 0.2
VV
OL
Low-level output voltage At I
sink
= 200 µA 0.4
POWER SUPPLY REQUIREMENTS
+V
DD
Supply voltage 2.7 3.3 5.5 VAt V
DD
= 3.0 V, 2.5-MSPS throughput 2.25 3At V
DD
= 3.0 V, static state 1.8Supply current (normal mode) mAAt V
DD
= 5.0 V, 3-MSPS throughput 3 4At V
DD
= 5.0 V, static state 2SCLK off 1Power down state supply current µASCLK on (48 MHz) 90 200V
DD
= 5 V, 3 MSPS 15 20Power dissipation mWV
DD
= 3 V, 2.5 MSPS 6.8
(1) Ideal input span; does not include gain or offset error.(2) Refer to Figure 43 for details on sampling circuit(3) LSB means least significant bit(4) Measured relative to an ideal full-scale input(5) Offset error and gain error ensured by characterization.(6) First transition of 000H to 001H at (V
ref
/2
8
)(7) Calculated on the first nine harmonics of the input frequency
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TIMING REQUIREMENTS (see Figure 1 )
ADS7884
ADS7885
SLAS567 – MARCH 2008
ADS7885 SPECIFICATIONS (continued)+V
DD
= 2.7 V to 5.5 V, T
A
= – 40 °C to 125 °C, f
sample
= 2.5 MSPS for V
DD
= 2.7 V to 3.6 V, f
sample
= 3 MSPS for V
DD
= 3.6 V to5.5 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
DD
= 5 V 10Power dissipation in static state mWV
DD
= 3 V 5.4Powerdown time 0.1 µsPowerup time 0.8 µs
TEMPERATURE RANGE
Specified performance – 40 125 °C
All specifications typical at T
A
= – 40 °C to 125 °C, V
DD
= 2.7 V to 5.5 V, unless otherwise specified.
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
V
DD
= 3 V 11.5 ×t
SCLKADS7884
V
DD
= 5 V 11.5 ×t
conv
Conversion time nst
SCLK
V
DD
= 3 V 9.5 ×t
SCLKADS7885
V
DD
= 5 V 9.5 ×t
SCLK
V
DD
= 3 V 62.5t
acq
Aquisition time nsV
DD
= 5 V 52V
DD
= 3 V 10Minimum quiet time needed from bus 3-state to startt
q
nsof next conversion
V
DD
= 5 V 10V
DD
= 3 V 9 15t
d1
Delay time, CS low to first data (0) out nsV
DD
= 5 V 8 11V
DD
= 3 V 7t
su1
Setup time, CS low to SCLK low nsV
DD
= 5 V 5V
DD
= 3 V 11 20t
d2
Delay time, SCLK falling to SDO nsV
DD
= 5 V 9 12V
DD
< 3 V 5.5t
h1
Hold time, SCLK falling to data valid
(2)
nsV
DD
> 5 V 4V
DD
= 3 V 9 15t
d3
Delay time, 16th SCLK falling edge to SDO 3-state nsV
DD
= 5 V 8 11V
DD
= 3 V 10t
w1
Pulse duration, CS nsV
DD
= 5 V 10V
DD
= 3 V 9 15t
d4
Delay time, CS high to SDO 3-state, nsV
DD
= 5 V 8 11V
DD
= 3 V 0.45 ×t
SCLKt
wH
Pulse duration, SCLK high nsV
DD
= 5 V 0.45 ×t
SCLK
V
DD
= 3 V 0.45 ×t
SCLKt
wL
Pulse duration, SCLK low nsV
DD
= 5 V 0.45 ×t
SCLK
V
DD
= 3 V 40Frequency, SCLK MHzV
DD
= 5 V 48Delay time, second falling edge of clock and CS to V
DD
= 3 V – 2 4t
d5
enter in powerdown (use min spec not to accidently nsV
DD
= 5 V – 2 3enter in powerdown) Figure 3
(1) 3-V Specifications apply from 2.7 V to 3.6 V, and 5-V specifications apply from 4.5 V to 5.5 V.(2) With 10-pf load.
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DEVICE INFORMATION
3
2
4
6
1
VDD
GND
VIN
CS
SCLK
SDO
5
ADS7884 NORMAL OPERATION
ADS7884
ADS7885
SLAS567 – MARCH 2008
TIMING REQUIREMENTS (see Figure 1 ) (continued)All specifications typical at T
A
= – 40 °C to 125 °C, V
DD
= 2.7 V to 5.5 V, unless otherwise specified.
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
Delay time, CS and 10th falling edge of clock to V
DD
= 3 V – 2 4t
d6
enter in powerdown (use max spec not to accidently nsV
DD
= 5 V – 2 3enter in powerdown) Figure 3
SOT23 PACKAGE
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
V
DD
1 – Power supply input also acts like a reference voltage to ADC.GND 2 – Ground for power supply, all analog and digital signals are referred with respect to this pin.VIN 3 I Analog signal inputSCLK 4 I Serial clockSDO 5 O Serial data outCS 6 I Chip select signal, active low
The cycle begins with the falling edge of CS. This point is indicated as ain Figure 1 . With the falling edge of CS,the input signal is sampled and the conversion process is initiated. The device outputs data while the conversionis in progress. The data word contains 2 leading zeros, followed by 10-bit data in MSB first format and padded by4 lagging zeros.
The falling edge of CS clocks out the first zero, and a second zero is clocked out on FIRST falling edge of theclock. Data is in MSB first format with the MSB being clocked out on the 2nd falling edge. Data is padded withfour lagging zeros as shown in Figure 1 . The conversion ends on the first rising edge of SCLK after the 11thfalling edge. At this point the device enters the acquisition phase. This point is indicated by bin Figure 1 .
Figure 1 shows device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any timeafter 11 clocks have elapsed. SDO goes to 3-state with the CS high level. The next conversion should not bestarted (by pulling CS low) until the end of the quiet sampling time (t
q
) after SDO goes to 3-state or until theminimum acquisition time (t
acq
) has elapsed. To continue normal operation, it is necessary that CS is not pulledhigh until point b. Without this, the device does not enter the acquisition phase and no valid data is available inthe next cycle. (Also refer to the Powerdown Mode section for more details.) CS going high any time after theconversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device V
DD
. This means the digital input can go ashigh as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are coming fromanother circuit with different supply levels. Also, this relaxes the restriction on powerup sequencing. However, thedigital output levels (V
OH
and V
OL
) are governed by V
DD
as listed in the Specifications table.
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12 3 11 12 14 15
CS
SCLK
SDO 00 D9 D8 D0 00
13
0 0
16
td1 td2 th1
tconv
tq
td3
tw1
b
tsu1
a
td4
tacq a
ADS7885 NORMAL OPERATION
12 3 910 14 15
CS
SCLK
SDO 00 D7 D6 D0 00
11
0 0
16
td1 td2 th1
tconv
tq
td3
tw1
b
tsu1
a
td4
tacq a
0
POWER DOWN MODE
ADS7884
ADS7885
SLAS567 – MARCH 2008
Figure 1. ADS7884 Interface Timing Diagram
The cycle begins with the falling edge of CS . This point is indicated as ain Figure 2 . With the falling edge of CS,the input signal is sampled and the conversion process is initiated. The device outputs data while the conversionis in progress. The data word contains 2 leading zeros, followed by 8-bit data in MSB first format and padded by6 lagging zeros.
The falling edge of CS clocks out the first zero, and a second zero is clocked out on FIRST falling edge of theclock. Data is in MSB first format with the MSB being clocked out on the 3rd falling edge. Data is padded with sixlagging zeros as shown in Figure 2 . On the 16th falling edge of SCLK, SDO goes to the 3-state condition. Theconversion ends on the first rising edge of SCLK after the 9th falling edge. At this point the device enters theacquisition phase. This point is indicated by bin Figure 2 .
Figure 2 shows device data is read in a sixteen clock frame. However, CS can be asserted (pulled high) any timeafter 9 clocks have elapsed (after the 10th falling edge of SCLK). SDO goes to 3-state with the CS high level.The next conversion should not be started (by pulling CS low) until the end of the quiet sampling time (t
q
) afterSDO goes to 3-state or until the minimum acquisition time (t
acq
) has elapsed. To continue normal operation, it isnecessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phaseand no valid data is available in the next cycle. (Also refer to the Powerdown Mode section for more details.) CSgoing high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.
The high level of the digital input to the device is not limited to device V
DD
. This means the digital input can go ashigh as 5.5 V when the device supply is 2.7 V. This feature is useful when digital signals are coming fromanother circuit with different supply levels. Also, this relaxes the restriction on powerup sequencing. However, thedigital output levels (V
OH
and V
OL
) are governed by V
DD
as listed in the Specifications section.
Figure 2. ADS7885 Interface Timing Diagram
The device enters powerdown mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10thSCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this powerdown condition asshown in Figure 3 .
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1 2 3 4 5 9 10 16
CS
SCLK
SDO
td5 td6
Invalid Data Valid Data
SDO
1 5432 6 10987 131211 161514 1 5432 6 10987 131211 161514
SCLK
Device Fully
Powered-Up
Device Starts
Powering Up
CS
ADS7884
ADS7885
SLAS567 – MARCH 2008
Figure 3. Entering Power Down Mode
A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of powerdown mode. Forthe device to come to the fully powered up condition it takes 0.8 µs. CS can be pulled high any time after the10th falling edge as shown in Figure 4 . Note that the powerup time of 0.8 µsec is more than a single conversioncycle at 3 MSPS speed. This means the device requires three dummy conversion frames at 3 MSPS speed orone elongated dummy conversion frame. The data during dummy conversion frames is invalid.
Figure 4. Exiting Power Down Mode
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TYPICAL CHARACTERISTICS ADS7884
0
0.5
1
1.5
2
2.5
3
3.5
0 10 20 30 40 50
f -Frequency-MHz
SCLK
I-SupplyCurrent-mA
CC
5V
3V
T =25°C
A
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400 500 600 700
f -SampleRate-KSPS
s
5V
3V
I -SupplyCurrent-mA
CC
T =25°C,
SCLK=48MHzatV =5V,
SCLK=40MHzatV =3V,
PowerDown,
SCLK=FreeRunning
A
DD
DD
-40
-30
-20
-10
0
10
20
30
-40 -20 0 20 40 60 80 100 120
T -Free-AirTemperature-°C
A
InputLeakageCurrent-nA
5V
0V
V =5V
DD
61
61.1
61.2
61.3
61.4
61.5
61.6
61.7
61.8
61.9
62
0 200 400 600 800 1000
f -InputFrequency-KHz
i
Signal-to-NoiseRatio-dB
SNR5V
T =25°C,
f =3MSPS,
V =5V
A
s
DD
61
61.1
61.2
61.3
61.4
61.5
61.6
61.7
61.8
61.9
62
0 200 400 600 800 1000
f -InputFrequency-KHz
i
Signal-to-Noise+Distortion-dB
SINAD5V
T =25°C,
f =3MSPS,
V =5V
A
s
DD
61
61.1
61.2
61.3
61.4
61.5
61.6
61.7
61.8
61.9
62
2.7 3.4 4.1 4.8 5.5
V -SupplyVoltage-V
DD
SINAD-Signal-to-NoiseandDistortion-dB
3MSPS
2.5MSPS
T =25°C,
f =3MSPSor2.5MSPS
A
s
61
61.1
61.2
61.3
61.4
61.5
61.6
61.7
61.8
61.9
62
-40 -20 0 20 40 60 80 100 120
5V,3MSPS
3V,2.5MSPS
SINAD-Signal-to-NoiseandDistortion-dB
T -Free-AirTemperature-°C
A
V =5Vat3MSPS,
V =3Vat2.5MSPS
DD
DD
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
-40 -20 0 20 40 60 80 100 120
DNL -DifferentialNonlinearity-LSBs
MAXDNL,3V,2.5MSPS
MINDNL,3V,2.5MSPS
MAXDNL,5V,3MSPS
MINDNL,5V,3MSPS
T -Free-AirTemperature-°C
A
T =25°C
V =5Vat3MSPS,
V =3Vat2.5MSPS
A
DD
DD
ADS7884
ADS7885
SLAS567 – MARCH 2008
SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENTvs vs vsSUPPLY VOLTAGE SCLK FREQUENCY SAMPLE RATE
Figure 5. Figure 6. Figure 7.
INPUT LEAKAGE CURRENT SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTIONvs vs vsFREE-AIR TEMPERATURE INPUT FREQUENCY INPUT FREQUENCY
Figure 8. Figure 9. Figure 10.
SIGNAL-TO-NOISE + DISTORTION SIGNAL-TO-NOISE + DISTORTION DIFFERENTIAL NONLINEARITYvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 11. Figure 12. Figure 13.
10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS7884 ADS7885
www.ti.com
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
-40 -20 0 20 40 60 80 100 120
INL -IntegralNonlinearity-LSBs
MAXINL,3V,2.5MSPS
MININL,3V,2.5MSPS
MAXINL,5V,3MSPS
MININL,5V,3MSPS
T =25°C
V =5Vat3MSPS,
V =3Vat2.5MSPS
A
DD
DD
T -Free-AirTemperature-°C
A
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
2.7 3.4 4.1 4.8 5.5
DNL -DifferentialNonlinearity-LSBs
MAXDNL,3MSPS
MINDNL,3MSPS
MAXDNL,2.5MSPS
MINDNL,2.5MSPS
V -SupplyVoltage-V
DD
T =25°C
A
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
2.7 3.4 4.1 4.8 5.5
INL -IntegralNonlinearity-LSBs
MAXINL,3MSPS
MININL,3MSPS
MAXINL,2.5MSPS
MININL,2.5MSPS
V -SupplyVoltage-V
DD
T =25°C
A
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
2.7 3.4 4.1 4.8 5.5
GainError-LSBs
3MSPS
2.5MSPS
T =25°C,
f =3MSPSor2.5MSPS,
V =5Vat3MSPS,
V =3Vat2.5MSPS
A
s
DD
DD
V -SupplyVoltage-V
DD
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
-40 -20 0 20 40 60 80 100 120
5V,3MSPS
T -Free-AirTemperature-°C
A
OffsetError-LSBs
3V,2.5MSPS
f =3MSPSor2.5MSPS,
V =5Vat3MSPS,
V =3Vat2.5MSPS
s
DD
DD
-0.5
-0.25
0
0.25
0.5
2.7 3.4 4.1 4.8 5.5
OffsetError-LSBs
3MSPS
2.5MSPS
V -SupplyVoltage-V
DD
T =25°C,
f =3MSPSor2.5MSPS,
V =5Vat3MSPS,
V =3Vat2.5MSPS
A
s
DD
DD
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
-40 -20 0 20 40 60 80 100 120
GainError-LSBs
5V,3MSPS
3V,2.5MSPS
T -Free-AirTemperature-°C
A
f =3MSPSor2.5MSPS,
V =5Vat3MSPS,
V =3Vat2.5MSPS
s
DD
DD
ADS7884
ADS7885
SLAS567 – MARCH 2008
TYPICAL CHARACTERISTICS ADS7884 (continued)
INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITYvs vs vsFREE-AIR TEMPERATURE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 14. Figure 15. Figure 16.
OFFSET ERROR OFFSET ERROR GAIN ERRORvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 17. Figure 18. Figure 19.
GAIN ERROR
vsFREE-AIR TEMPERATURE
Figure 20.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
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-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0 256 512 768 1024
OutputCode
DNL -LSBs
V =5V,
f =3MSPS,
T =25°C
DD
s
A
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
0 256 512 768 1024
OutputCode
INL -LSBs
V =5V,
f =3MSPS,
T =25°C
DD
s
A
-140
-120
-100
-80
-60
-40
-20
0
0 250 500 750 1000 1250 1500
f-Frequency-kHz
power-dB
f =3MSPS,
f -100kHz,
V =5V,
NPoints
s
in
DD
16384
ADS7884
ADS7885
SLAS567 – MARCH 2008
TYPICAL CHARACTERISTICS ADS7884 (continued)DNL
Figure 21.
INL
Figure 22.
FFT
Figure 23.
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TYPICAL CHARACTERISTICS ADS7885
0
0.5
1
1.5
2
2.5
3
0 10 20 30 40 50
f -Frequency-MHz
SCLK
5V
3V
I -SupplyCurrent-mA
CC
T =25°C
A
0
0.5
1
1.5
2
2.5
3
0 100 200 300 400 500 600 700
f -SampleRate-KSPS
s
5V
3V
T =25°C,
SCLK=48MHzatV =5V,
SCLK=40MHzatV =3V,
PowerDown,
SCLK=FreeRunning
A
DD
DD
I-SupplyCurrent-mA
CC
-40
-30
-20
-10
0
10
20
30
-40 -20 0 20 40 60 80 100 120
InputLeakageCurrent-nA
5V
0V
T -Free-AirTemperature-°C
A
V =5V
DD
49
49.2
49.4
49.6
49.8
50
50.2
50.4
50.6
50.8
51
0 200 400 600 800 1000
f -InputFrequency-KHz
i
Signal-to-NoiseRatio-dB
SNR5V
T =25°C,
f =3MSPS,
V =5V
A
s
DD
49
49.2
49.4
49.6
49.8
50
50.2
50.4
50.6
50.8
51
0 200 400 600 800 1000
f -InputFrequency-KHz
i
Signal-to-Noise+Distortion-dB
SINAD5V
T =25°C,
f =3MSPS,
V =5V
A
s
DD
49
49.2
49.4
49.6
49.8
50
50.2
50.4
50.6
50.8
51
-40 -20 0 20 40 60 80 100 120
5V,3MSPS
3V,2.5MSPS
SINAD-Signal-to-NoiseandDistortion-dB
T -Free-AirTemperature-°C
A
V =5Vat3MSPS,
V =3Vat2.5MSPS
DD
DD
49
49.2
49.4
49.6
49.8
50
50.2
50.4
50.6
50.8
51
2.7 3.4 4.1 4.8 5.5
3MSPS
2.5MSPS
V -SupplyVoltage-V
DD
SINAD-Signal-to-NoiseandDistortion-dB
T =25°C,
f =3MSPSor2.5MSPS
A
s
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-40 -20 0 20 40 60 80 100 120
MAXDNL,3V,2.5MSPS
MINDNL,3V,2.5MSPS
MAXDNL,5V,3MSPS
MINDNL,5V,3MSPS
T =25°C
V =5Vat3MSPS,
V =3Vat2.5MSPS
A
DD
DD
T -Free-AirTemperature-°C
A
DNL -DifferentialNonlinearity-LSBs
ADS7884
ADS7885
SLAS567 – MARCH 2008
SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENTvs vs vsSUPPLY VOLTAGE SCLK FREQUENCY SAMPLE RATE
Figure 24. Figure 25. Figure 26.
INPUT LEAKAGE CURRENT SIGNAL-TO-NOISE RATIO SIGNAL-TO-NOISE + DISTORTIONvs vs vsFREE-AIR TEMPERATURE INPUT FREQUENCY INPUT FREQUENCY
Figure 27. Figure 28. Figure 29.
SIGNAL-TO-NOISE + DISTORTION SIGNAL-TO-NOISE + DISTORTION DIFFERENTIAL NONLINEARITYvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE
Figure 30. Figure 31. Figure 32.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
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www.ti.com
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-40 -20 0 20 40 60 80 100 120
MAXINL,3V,2.5MSPS
MININL,3V,2.5MSPS
MAXINL,5V,3MSPS
MININL,5V,3MSPS
T -Free-AirTemperature-°C
A
INL -IntegralNonlinearity-LSBs
T =25°C
V =5Vat3MSPS,
V =3Vat2.5MSPS
A
DD
DD
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
2.7 3.4 4.1 4.8 5.5
MAXDNL,3MSPS
MINDNL,3MSPS
MAXDNL,2.5MSPS
MINDNL,2.5MSPS
V -SupplyVoltage-V
DD
DNL -DifferentialNonlinearity-LSBs
T =25°C
A
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
2.7 3.4 4.1 4.8 5.5
MAXINL,3MSPS
MININL,3MSPS
MAXINL,2.5MSPS
MININL,2.5MSPS
V -SupplyVoltage-V
DD
INL -IntegralNonlinearity-LSBs
T =25°C
A
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
-40 -20 0 20 40 60 80 100 120
5V,3MSPS
3V,2.5MSPS
f =3MSPSor2.5MSPS,
V =5Vat3MSPS,
V =3Vat2.5MSPS
s
DD
DD
T -Free-AirTemperature-°C
A
OffsetError-LSBs
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
2.7 3.4 4.1 4.8 5.5
3MSPS
2.5MSPS
GainError-LSBs
V -SupplyVoltage-V
DD
T =25°C,
f =3MSPSor2.5MSPS,
V =5Vat3MSPS,
V =3Vat2.5MSPS
A
s
DD
DD
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
-40 -20 0 20 40 60 80 100 120
GainError-LSBs
5V,3MSPS
3V,2.5MSPS
T -Free-AirTemperature-°C
A
f =3MSPSor2.5MSPS,
V =5Vat3MSPS,
V =3Vat2.5MSPS
s
DD
DD
ADS7884
ADS7885
SLAS567 – MARCH 2008
TYPICAL CHARACTERISTICS ADS7885 (continued)
INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY INTEGRAL NONLINEARITYvs vs vsFREE-AIR TEMPERATURE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 33. Figure 34. Figure 35.
OFFSET ERROR OFFSET ERROR GAIN ERRORvs vs vsSUPPLY VOLTAGE FREE-AIR TEMPERATURE SUPPLY VOLTAGE
Figure 36. Figure 37. Figure 38.
GAIN ERROR
vsFREE-AIR TEMPERATURE
Figure 39.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS7884 ADS7885
www.ti.com
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0 64 128 192 256
OutputCode
DNL -LSBs
V =5V,
f =3MSPS,
T =25°C
DD
s
A
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0 64 128 192 256
OutputCode
INL -LSBs
V =5V,
f =3MSPS,
T =25°C
DD
s
A
0 250 500 750 1000 1250 1500
F-Frequency-kHz
-120
-100
-80
-60
-40
-20
0
Power-dB
f =3MSPS,
f -100kHz,
V =5V,
16384NPoints
s
in
DD
ADS7884
ADS7885
SLAS567 – MARCH 2008
TYPICAL CHARACTERISTICS ADS7885 (continued)DNL
Figure 40.
INL
Figure 41.
FFT
Figure 42.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
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www.ti.com
APPLICATION INFORMATION
50 W
50 W20 pF
20 W
7 pF
VDD
IN
GND
Driving the VIN and V
DD
Pins of the ADS7884 and ADS7885
VDD
VIN
GND
CS
SDO
SCLK
10 nF1 mF
VDD
VDD
VIN
GND
CS
SDO
SCLK
10 nF1 mF
GND
IN
OUT 3 V
1 mF
5 V REF3030
ADS7884
ADS7885
SLAS567 – MARCH 2008
Figure 43. Typical Equivalent Sampling Circuit
The VIN input to the ADS7884 and ADS7885 should be driven with a low impedance source. In most casesadditional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer wouldhelp achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifierbuffer.
The reference voltage for the ADS7884 and ADS7885 A/D converters are derived from the supply voltageinternally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters shouldbe driven with a low impedance source and should be decoupled to the ground. A 1-µF storage capacitor and a10-nF decoupling capacitor should be placed close to the device. Wide, low impedance traces should be used toconnect the capacitor to the pins of the device. The ADS7884 and ADS7885 draw very little current from thesupply lines. The supply line can be driven by either:•Directly from the system supply.•A reference output from a low drift and low drop out reference voltage generator like REF3030 or REF3130.The ADS7884 and ADS7885 can operate off a wide range of supply voltages. The actual choice of thereference voltage generator would depend upon the system. Figure 45 shows one possible application circuit.•A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also beused in cases where the system power supply is noisy. Care should be taken to ensure that the voltage at theV
DD
input does not exceed 7 V (especially during power up) to avoid damage to the converter. This can bedone easily using single supply CMOS amplifiers like the OPA735. Figure 46 shows one possible applicationcircuit.
Figure 44. Supply/Reference Decoupling Capacitors
Figure 45. Using the REF3030 Reference
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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VDD
VIN
GND
CS
SDO
SCLK
10 nF1 mF
1 mF
7 V
_
+
R1
C1
R2
5 V
10 W
ADS7884
ADS7885
SLAS567 – MARCH 2008
Figure 46. Buffering with the OPA735
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS7884 ADS7885
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS7884SDBVR ACTIVE SOT-23 DBV 6 3000 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR
ADS7884SDBVT ACTIVE SOT-23 DBV 6 250 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR
ADS7885SDBVR ACTIVE SOT-23 DBV 6 3000 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR
ADS7885SDBVT ACTIVE SOT-23 DBV 6 250 Pb-Free (RoHS
Exempt) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 31-Mar-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7884SDBVR SOT-23 DBV 6 3000 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
ADS7884SDBVT SOT-23 DBV 6 250 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
ADS7885SDBVR SOT-23 DBV 6 3000 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
ADS7885SDBVT SOT-23 DBV 6 250 177.8 9.7 3.2 3.1 1.39 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7884SDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0
ADS7884SDBVT SOT-23 DBV 6 250 184.0 184.0 50.0
ADS7885SDBVR SOT-23 DBV 6 3000 184.0 184.0 50.0
ADS7885SDBVT SOT-23 DBV 6 250 184.0 184.0 50.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Mar-2008
Pack Materials-Page 2
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